1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
43 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
81 #ifndef REGISTER_MOVE_COST
82 #define REGISTER_MOVE_COST(x, y) 2
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Describes order of preference for putting regs into spill_regs.
217 Contains the numbers of all the hard regs, in order most preferred first.
218 This order is different for each function.
219 It is set up by order_regs_for_reload.
220 Empty elements at the end contain -1. */
221 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
223 /* Nonzero if indirect addressing is supported on the machine; this means
224 that spilling (REG n) does not require reloading it into a register in
225 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
226 value indicates the level of indirect addressing supported, e.g., two
227 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
229 static char spill_indirect_levels;
231 /* Nonzero if indirect addressing is supported when the innermost MEM is
232 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
233 which these are valid is the same as spill_indirect_levels, above. */
234 char indirect_symref_ok;
236 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
237 char double_reg_address_ok;
239 /* Record the stack slot for each spilled hard register. */
240 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
242 /* Width allocated so far for that stack slot. */
243 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
245 /* Record which pseudos needed to be spilled. */
246 static regset spilled_pseudos;
248 /* First uid used by insns created by reload in this function.
249 Used in find_equiv_reg. */
250 int reload_first_uid;
252 /* Flag set by local-alloc or global-alloc if anything is live in
253 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
258 int reload_in_progress = 0;
260 /* These arrays record the insn_code of insns that may be needed to
261 perform input and output reloads of special objects. They provide a
262 place to pass a scratch register. */
263 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
264 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
266 /* This obstack is used for allocation of rtl during register elimination.
267 The allocated storage can be freed once find_reloads has processed the
269 struct obstack reload_obstack;
271 /* Points to the beginning of the reload_obstack. All insn_chain structures
272 are allocated first. */
273 char *reload_startobj;
275 /* The point after all insn_chain structures. Used to quickly deallocate
276 memory used while processing one insn. */
277 char *reload_firstobj;
279 #define obstack_chunk_alloc xmalloc
280 #define obstack_chunk_free free
282 /* List of labels that must never be deleted. */
283 extern rtx forced_labels;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table * reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 struct hard_reg_n_uses
375 static void maybe_fix_stack_asms PROTO((void));
376 static void calculate_needs_all_insns PROTO((int));
377 static void calculate_needs PROTO((struct insn_chain *));
378 static void find_reload_regs PROTO((struct insn_chain *chain,
380 static void find_tworeg_group PROTO((struct insn_chain *, int,
382 static void find_group PROTO((struct insn_chain *, int,
384 static int possible_group_p PROTO((struct insn_chain *, int));
385 static void count_possible_groups PROTO((struct insn_chain *, int));
386 static int modes_equiv_for_class_p PROTO((enum machine_mode,
389 static void delete_caller_save_insns PROTO((void));
391 static void spill_failure PROTO((rtx));
392 static void new_spill_reg PROTO((struct insn_chain *, int, int,
394 static void maybe_mark_pseudo_spilled PROTO((int));
395 static void delete_dead_insn PROTO((rtx));
396 static void alter_reg PROTO((int, int));
397 static void set_label_offsets PROTO((rtx, rtx, int));
398 static int eliminate_regs_in_insn PROTO((rtx, int));
399 static void update_eliminable_offsets PROTO((void));
400 static void mark_not_eliminable PROTO((rtx, rtx));
401 static void set_initial_elim_offsets PROTO((void));
402 static void verify_initial_elim_offsets PROTO((void));
403 static void set_initial_label_offsets PROTO((void));
404 static void set_offsets_for_label PROTO((rtx));
405 static void init_elim_table PROTO((void));
406 static void update_eliminables PROTO((HARD_REG_SET *));
407 static void spill_hard_reg PROTO((int, FILE *, int));
408 static int finish_spills PROTO((int, FILE *));
409 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
410 static void scan_paradoxical_subregs PROTO((rtx));
411 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
412 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
413 static void order_regs_for_reload PROTO((struct insn_chain *));
414 static void reload_as_needed PROTO((int));
415 static void forget_old_reloads_1 PROTO((rtx, rtx));
416 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
417 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
419 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
421 static int reload_reg_free_p PROTO((int, int, enum reload_type));
422 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
423 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
424 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
426 static void choose_reload_regs PROTO((struct insn_chain *));
427 static void merge_assigned_reloads PROTO((rtx));
428 static void emit_reload_insns PROTO((struct insn_chain *));
429 static void delete_output_reload PROTO((rtx, int, int));
430 static void delete_address_reloads PROTO((rtx, rtx));
431 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
432 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
433 static int constraint_accepts_reg_p PROTO((const char *, rtx));
434 static void reload_cse_regs_1 PROTO((rtx));
435 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
436 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
437 static void reload_cse_invalidate_mem PROTO((rtx));
438 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
439 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
440 static int reload_cse_noop_set_p PROTO((rtx, rtx));
441 static int reload_cse_simplify_set PROTO((rtx, rtx));
442 static int reload_cse_simplify_operands PROTO((rtx));
443 static void reload_cse_check_clobber PROTO((rtx, rtx));
444 static void reload_cse_record_set PROTO((rtx, rtx));
445 static void reload_combine PROTO((void));
446 static void reload_combine_note_use PROTO((rtx *, rtx));
447 static void reload_combine_note_store PROTO((rtx, rtx));
448 static void reload_cse_move2add PROTO((rtx));
449 static void move2add_note_store PROTO((rtx, rtx));
451 static void add_auto_inc_notes PROTO((rtx, rtx));
454 /* Initialize the reload pass once per compilation. */
461 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
462 Set spill_indirect_levels to the number of levels such addressing is
463 permitted, zero if it is not permitted at all. */
466 = gen_rtx_MEM (Pmode,
468 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
470 spill_indirect_levels = 0;
472 while (memory_address_p (QImode, tem))
474 spill_indirect_levels++;
475 tem = gen_rtx_MEM (Pmode, tem);
478 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
480 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
481 indirect_symref_ok = memory_address_p (QImode, tem);
483 /* See if reg+reg is a valid (and offsettable) address. */
485 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
487 tem = gen_rtx_PLUS (Pmode,
488 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
489 gen_rtx_REG (Pmode, i));
490 /* This way, we make sure that reg+reg is an offsettable address. */
491 tem = plus_constant (tem, 4);
493 if (memory_address_p (QImode, tem))
495 double_reg_address_ok = 1;
500 /* Initialize obstack for our rtl allocation. */
501 gcc_obstack_init (&reload_obstack);
502 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
505 /* List of insn chains that are currently unused. */
506 static struct insn_chain *unused_insn_chains = 0;
508 /* Allocate an empty insn_chain structure. */
512 struct insn_chain *c;
514 if (unused_insn_chains == 0)
516 c = (struct insn_chain *)
517 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
519 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
536 compute_use_by_pseudos (to, from)
541 EXECUTE_IF_SET_IN_REG_SET
542 (from, FIRST_PSEUDO_REGISTER, regno,
544 int r = reg_renumber[regno];
548 /* reload_combine uses the information from
549 BASIC_BLOCK->global_live_at_start, which might still
550 contain registers that have not actually been allocated
551 since they have an equivalence. */
552 if (! reload_completed)
557 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Global variables used by reload and its subroutines. */
566 /* Set during calculate_needs if an insn needs register elimination. */
567 static int something_needs_elimination;
568 /* Set during calculate_needs if an insn needs an operand changed. */
569 int something_needs_operands_changed;
571 /* Nonzero means we couldn't get enough spill regs. */
574 /* Main entry point for the reload pass.
576 FIRST is the first insn of the function being compiled.
578 GLOBAL nonzero means we were called from global_alloc
579 and should attempt to reallocate any pseudoregs that we
580 displace from hard regs we will use for reloads.
581 If GLOBAL is zero, we do not have enough information to do that,
582 so any pseudo reg that is spilled must go to the stack.
584 DUMPFILE is the global-reg debugging dump file stream, or 0.
585 If it is nonzero, messages are written to it to describe
586 which registers are seized as reload regs, which pseudo regs
587 are spilled from them, and where the pseudo regs are reallocated to.
589 Return value is nonzero if reload failed
590 and we must not do any more for this function. */
593 reload (first, global, dumpfile)
600 register struct elim_table *ep;
602 /* The two pointers used to track the true location of the memory used
603 for label offsets. */
604 char *real_known_ptr = NULL_PTR;
605 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
607 /* Make sure even insns with volatile mem refs are recognizable. */
612 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
614 /* Make sure that the last insn in the chain
615 is not something that needs reloading. */
616 emit_note (NULL_PTR, NOTE_INSN_DELETED);
618 /* Enable find_equiv_reg to distinguish insns made by reload. */
619 reload_first_uid = get_max_uid ();
621 #ifdef SECONDARY_MEMORY_NEEDED
622 /* Initialize the secondary memory table. */
623 clear_secondary_mem ();
626 /* We don't have a stack slot for any spill reg yet. */
627 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
628 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
630 /* Initialize the save area information for caller-save, in case some
634 /* Compute which hard registers are now in use
635 as homes for pseudo registers.
636 This is done here rather than (eg) in global_alloc
637 because this point is reached even if not optimizing. */
638 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
641 /* A function that receives a nonlocal goto must save all call-saved
643 if (current_function_has_nonlocal_label)
644 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
646 if (! call_used_regs[i] && ! fixed_regs[i])
647 regs_ever_live[i] = 1;
650 /* Find all the pseudo registers that didn't get hard regs
651 but do have known equivalent constants or memory slots.
652 These include parameters (known equivalent to parameter slots)
653 and cse'd or loop-moved constant memory addresses.
655 Record constant equivalents in reg_equiv_constant
656 so they will be substituted by find_reloads.
657 Record memory equivalents in reg_mem_equiv so they can
658 be substituted eventually by altering the REG-rtx's. */
660 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
661 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
662 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
663 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
664 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
665 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
666 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
667 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
668 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
669 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
670 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
671 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
672 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
673 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
674 pseudo_forbidden_regs
675 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
677 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
679 CLEAR_HARD_REG_SET (bad_spill_regs_global);
680 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
682 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
683 Also find all paradoxical subregs and find largest such for each pseudo.
684 On machines with small register classes, record hard registers that
685 are used for user variables. These can never be used for spills.
686 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
687 caller-saved registers must be marked live. */
689 num_eliminable_invariants = 0;
690 for (insn = first; insn; insn = NEXT_INSN (insn))
692 rtx set = single_set (insn);
694 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
697 if (! call_used_regs[i])
698 regs_ever_live[i] = 1;
700 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
702 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
704 #ifdef LEGITIMATE_PIC_OPERAND_P
705 && (! function_invariant_p (XEXP (note, 0))
707 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
711 rtx x = XEXP (note, 0);
712 i = REGNO (SET_DEST (set));
713 if (i > LAST_VIRTUAL_REGISTER)
715 if (GET_CODE (x) == MEM)
717 /* If the operand is a PLUS, the MEM may be shared,
718 so make sure we have an unshared copy here. */
719 if (GET_CODE (XEXP (x, 0)) == PLUS)
722 reg_equiv_memory_loc[i] = x;
724 else if (function_invariant_p (x))
726 if (GET_CODE (x) == PLUS)
728 /* This is PLUS of frame pointer and a constant,
729 and might be shared. Unshare it. */
730 reg_equiv_constant[i] = copy_rtx (x);
731 num_eliminable_invariants++;
733 else if (x == frame_pointer_rtx
734 || x == arg_pointer_rtx)
736 reg_equiv_constant[i] = x;
737 num_eliminable_invariants++;
739 else if (LEGITIMATE_CONSTANT_P (x))
740 reg_equiv_constant[i] = x;
742 reg_equiv_memory_loc[i]
743 = force_const_mem (GET_MODE (SET_DEST (set)), x);
748 /* If this register is being made equivalent to a MEM
749 and the MEM is not SET_SRC, the equivalencing insn
750 is one with the MEM as a SET_DEST and it occurs later.
751 So don't mark this insn now. */
752 if (GET_CODE (x) != MEM
753 || rtx_equal_p (SET_SRC (set), x))
755 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
760 /* If this insn is setting a MEM from a register equivalent to it,
761 this is the equivalencing insn. */
762 else if (set && GET_CODE (SET_DEST (set)) == MEM
763 && GET_CODE (SET_SRC (set)) == REG
764 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
765 && rtx_equal_p (SET_DEST (set),
766 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
767 reg_equiv_init[REGNO (SET_SRC (set))]
768 = gen_rtx_INSN_LIST (VOIDmode, insn,
769 reg_equiv_init[REGNO (SET_SRC (set))]);
771 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
772 scan_paradoxical_subregs (PATTERN (insn));
777 num_labels = max_label_num () - get_first_label_num ();
779 /* Allocate the tables used to store offset information at labels. */
780 /* We used to use alloca here, but the size of what it would try to
781 allocate would occasionally cause it to exceed the stack limit and
782 cause a core dump. */
783 real_known_ptr = xmalloc (num_labels);
785 = (int (*)[NUM_ELIMINABLE_REGS])
786 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
788 offsets_known_at = real_known_ptr - get_first_label_num ();
790 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
792 /* Alter each pseudo-reg rtx to contain its hard reg number.
793 Assign stack slots to the pseudos that lack hard regs or equivalents.
794 Do not touch virtual registers. */
796 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
807 || GET_CODE (insn) == CALL_INSN)
808 note_stores (PATTERN (insn), mark_not_eliminable);
810 #ifndef REGISTER_CONSTRAINTS
811 /* If all the pseudo regs have hard regs,
812 except for those that are never referenced,
813 we know that no reloads are needed. */
814 /* But that is not true if there are register constraints, since
815 in that case some pseudos might be in the wrong kind of hard reg. */
817 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
818 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
821 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
823 free (real_known_ptr);
825 free (reg_equiv_constant);
826 free (reg_equiv_memory_loc);
827 free (reg_equiv_mem);
828 free (reg_equiv_init);
829 free (reg_equiv_address);
830 free (reg_max_ref_width);
831 free (reg_old_renumber);
832 free (pseudo_previous_regs);
833 free (pseudo_forbidden_regs);
838 maybe_fix_stack_asms ();
840 insns_need_reload = 0;
841 something_needs_elimination = 0;
843 /* Initialize to -1, which means take the first spill register. */
846 spilled_pseudos = ALLOCA_REG_SET ();
848 /* Spill any hard regs that we know we can't eliminate. */
849 CLEAR_HARD_REG_SET (used_spill_regs);
850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
851 if (! ep->can_eliminate)
852 spill_hard_reg (ep->from, dumpfile, 1);
854 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
855 if (frame_pointer_needed)
856 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
858 finish_spills (global, dumpfile);
860 /* From now on, we may need to generate moves differently. We may also
861 allow modifications of insns which cause them to not be recognized.
862 Any such modifications will be cleaned up during reload itself. */
863 reload_in_progress = 1;
865 /* This loop scans the entire function each go-round
866 and repeats until one repetition spills no additional hard regs. */
869 int something_changed;
871 struct insn_chain *chain;
873 HOST_WIDE_INT starting_frame_size;
875 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
876 here because the stack size may be a part of the offset computation
877 for register elimination, and there might have been new stack slots
878 created in the last iteration of this loop. */
879 assign_stack_local (BLKmode, 0, 0);
881 starting_frame_size = get_frame_size ();
883 set_initial_elim_offsets ();
884 set_initial_label_offsets ();
886 /* For each pseudo register that has an equivalent location defined,
887 try to eliminate any eliminable registers (such as the frame pointer)
888 assuming initial offsets for the replacement register, which
891 If the resulting location is directly addressable, substitute
892 the MEM we just got directly for the old REG.
894 If it is not addressable but is a constant or the sum of a hard reg
895 and constant, it is probably not addressable because the constant is
896 out of range, in that case record the address; we will generate
897 hairy code to compute the address in a register each time it is
898 needed. Similarly if it is a hard register, but one that is not
899 valid as an address register.
901 If the location is not addressable, but does not have one of the
902 above forms, assign a stack slot. We have to do this to avoid the
903 potential of producing lots of reloads if, e.g., a location involves
904 a pseudo that didn't get a hard register and has an equivalent memory
905 location that also involves a pseudo that didn't get a hard register.
907 Perhaps at some point we will improve reload_when_needed handling
908 so this problem goes away. But that's very hairy. */
910 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
911 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
913 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
915 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
917 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
918 else if (CONSTANT_P (XEXP (x, 0))
919 || (GET_CODE (XEXP (x, 0)) == REG
920 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
921 || (GET_CODE (XEXP (x, 0)) == PLUS
922 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
923 && (REGNO (XEXP (XEXP (x, 0), 0))
924 < FIRST_PSEUDO_REGISTER)
925 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
926 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
929 /* Make a new stack slot. Then indicate that something
930 changed so we go back and recompute offsets for
931 eliminable registers because the allocation of memory
932 below might change some offset. reg_equiv_{mem,address}
933 will be set up for this pseudo on the next pass around
935 reg_equiv_memory_loc[i] = 0;
936 reg_equiv_init[i] = 0;
941 if (caller_save_needed)
944 /* If we allocated another stack slot, redo elimination bookkeeping. */
945 if (starting_frame_size != get_frame_size ())
948 if (caller_save_needed)
950 save_call_clobbered_regs ();
951 /* That might have allocated new insn_chain structures. */
952 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
955 calculate_needs_all_insns (global);
957 CLEAR_REG_SET (spilled_pseudos);
960 something_changed = 0;
962 /* If we allocated any new memory locations, make another pass
963 since it might have changed elimination offsets. */
964 if (starting_frame_size != get_frame_size ())
965 something_changed = 1;
968 HARD_REG_SET to_spill;
969 CLEAR_HARD_REG_SET (to_spill);
970 update_eliminables (&to_spill);
971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
972 if (TEST_HARD_REG_BIT (to_spill, i))
974 spill_hard_reg (i, dumpfile, 1);
977 /* Regardless of the state of spills, if we previously had
978 a register that we thought we could eliminate, but no can
979 not eliminate, we must run another pass.
981 Consider pseudos which have an entry in reg_equiv_* which
982 reference an eliminable register. We must make another pass
983 to update reg_equiv_* so that we do not substitute in the
984 old value from when we thought the elimination could be
986 something_changed = 1;
990 CLEAR_HARD_REG_SET (used_spill_regs);
991 /* Try to satisfy the needs for each insn. */
992 for (chain = insns_need_reload; chain != 0;
993 chain = chain->next_need_reload)
994 find_reload_regs (chain, dumpfile);
999 if (insns_need_reload != 0 || did_spill)
1000 something_changed |= finish_spills (global, dumpfile);
1002 if (! something_changed)
1005 if (caller_save_needed)
1006 delete_caller_save_insns ();
1009 /* If global-alloc was run, notify it of any register eliminations we have
1012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1013 if (ep->can_eliminate)
1014 mark_elimination (ep->from, ep->to);
1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017 If that insn didn't set the register (i.e., it copied the register to
1018 memory), just delete that insn instead of the equivalencing insn plus
1019 anything now dead. If we call delete_dead_insn on that insn, we may
1020 delete the insn that actually sets the register if the register dies
1021 there and that is incorrect. */
1023 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1025 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1028 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1030 rtx equiv_insn = XEXP (list, 0);
1031 if (GET_CODE (equiv_insn) == NOTE)
1033 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1034 delete_dead_insn (equiv_insn);
1037 PUT_CODE (equiv_insn, NOTE);
1038 NOTE_SOURCE_FILE (equiv_insn) = 0;
1039 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1045 /* Use the reload registers where necessary
1046 by generating move instructions to move the must-be-register
1047 values into or out of the reload registers. */
1049 if (insns_need_reload != 0 || something_needs_elimination
1050 || something_needs_operands_changed)
1052 int old_frame_size = get_frame_size ();
1054 reload_as_needed (global);
1056 if (old_frame_size != get_frame_size ())
1060 verify_initial_elim_offsets ();
1063 /* If we were able to eliminate the frame pointer, show that it is no
1064 longer live at the start of any basic block. If it ls live by
1065 virtue of being in a pseudo, that pseudo will be marked live
1066 and hence the frame pointer will be known to be live via that
1069 if (! frame_pointer_needed)
1070 for (i = 0; i < n_basic_blocks; i++)
1071 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1072 HARD_FRAME_POINTER_REGNUM);
1074 /* Come here (with failure set nonzero) if we can't get enough spill regs
1075 and we decide not to abort about it. */
1078 reload_in_progress = 0;
1080 /* Now eliminate all pseudo regs by modifying them into
1081 their equivalent memory references.
1082 The REG-rtx's for the pseudos are modified in place,
1083 so all insns that used to refer to them now refer to memory.
1085 For a reg that has a reg_equiv_address, all those insns
1086 were changed by reloading so that no insns refer to it any longer;
1087 but the DECL_RTL of a variable decl may refer to it,
1088 and if so this causes the debugging info to mention the variable. */
1090 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1095 int is_readonly = 0;
1097 if (reg_equiv_memory_loc[i])
1099 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1100 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1101 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1104 if (reg_equiv_mem[i])
1105 addr = XEXP (reg_equiv_mem[i], 0);
1107 if (reg_equiv_address[i])
1108 addr = reg_equiv_address[i];
1112 if (reg_renumber[i] < 0)
1114 rtx reg = regno_reg_rtx[i];
1115 XEXP (reg, 0) = addr;
1116 REG_USERVAR_P (reg) = 0;
1117 RTX_UNCHANGING_P (reg) = is_readonly;
1118 MEM_IN_STRUCT_P (reg) = in_struct;
1119 MEM_SCALAR_P (reg) = is_scalar;
1120 /* We have no alias information about this newly created
1122 MEM_ALIAS_SET (reg) = 0;
1123 PUT_CODE (reg, MEM);
1125 else if (reg_equiv_mem[i])
1126 XEXP (reg_equiv_mem[i], 0) = addr;
1130 /* We must set reload_completed now since the cleanup_subreg_operands call
1131 below will re-recognize each insn and reload may have generated insns
1132 which are only valid during and after reload. */
1133 reload_completed = 1;
1135 /* Make a pass over all the insns and delete all USEs which we
1136 inserted only to tag a REG_EQUAL note on them. Remove all
1137 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1138 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1139 REG_LIBCALL notes since they are no longer useful or accurate.
1140 Strip and regenerate REG_INC notes that may have been moved
1143 for (insn = first; insn; insn = NEXT_INSN (insn))
1144 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1148 if ((GET_CODE (PATTERN (insn)) == USE
1149 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1150 || GET_CODE (PATTERN (insn)) == CLOBBER)
1152 PUT_CODE (insn, NOTE);
1153 NOTE_SOURCE_FILE (insn) = 0;
1154 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1158 pnote = ®_NOTES (insn);
1161 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1162 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1163 || REG_NOTE_KIND (*pnote) == REG_INC
1164 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1165 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1166 *pnote = XEXP (*pnote, 1);
1168 pnote = &XEXP (*pnote, 1);
1172 add_auto_inc_notes (insn, PATTERN (insn));
1175 /* And simplify (subreg (reg)) if it appears as an operand. */
1176 cleanup_subreg_operands (insn);
1179 /* If we are doing stack checking, give a warning if this function's
1180 frame size is larger than we expect. */
1181 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1183 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1184 static int verbose_warned = 0;
1186 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1187 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1188 size += UNITS_PER_WORD;
1190 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1192 warning ("frame size too large for reliable stack checking");
1193 if (! verbose_warned)
1195 warning ("try reducing the number of local variables");
1201 /* Indicate that we no longer have known memory locations or constants. */
1202 if (reg_equiv_constant)
1203 free (reg_equiv_constant);
1204 reg_equiv_constant = 0;
1205 if (reg_equiv_memory_loc)
1206 free (reg_equiv_memory_loc);
1207 reg_equiv_memory_loc = 0;
1210 free (real_known_ptr);
1214 free (reg_equiv_mem);
1215 free (reg_equiv_init);
1216 free (reg_equiv_address);
1217 free (reg_max_ref_width);
1218 free (reg_old_renumber);
1219 free (pseudo_previous_regs);
1220 free (pseudo_forbidden_regs);
1222 FREE_REG_SET (spilled_pseudos);
1224 CLEAR_HARD_REG_SET (used_spill_regs);
1225 for (i = 0; i < n_spills; i++)
1226 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1228 /* Free all the insn_chain structures at once. */
1229 obstack_free (&reload_obstack, reload_startobj);
1230 unused_insn_chains = 0;
1235 /* Yet another special case. Unfortunately, reg-stack forces people to
1236 write incorrect clobbers in asm statements. These clobbers must not
1237 cause the register to appear in bad_spill_regs, otherwise we'll call
1238 fatal_insn later. We clear the corresponding regnos in the live
1239 register sets to avoid this.
1240 The whole thing is rather sick, I'm afraid. */
1242 maybe_fix_stack_asms ()
1245 const char *constraints[MAX_RECOG_OPERANDS];
1246 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1247 struct insn_chain *chain;
1249 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1252 HARD_REG_SET clobbered, allowed;
1255 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1256 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1258 pat = PATTERN (chain->insn);
1259 if (GET_CODE (pat) != PARALLEL)
1262 CLEAR_HARD_REG_SET (clobbered);
1263 CLEAR_HARD_REG_SET (allowed);
1265 /* First, make a mask of all stack regs that are clobbered. */
1266 for (i = 0; i < XVECLEN (pat, 0); i++)
1268 rtx t = XVECEXP (pat, 0, i);
1269 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1270 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1273 /* Get the operand values and constraints out of the insn. */
1274 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1275 constraints, operand_mode);
1277 /* For every operand, see what registers are allowed. */
1278 for (i = 0; i < noperands; i++)
1280 char *p = constraints[i];
1281 /* For every alternative, we compute the class of registers allowed
1282 for reloading in CLS, and merge its contents into the reg set
1284 int cls = (int) NO_REGS;
1290 if (c == '\0' || c == ',' || c == '#')
1292 /* End of one alternative - mark the regs in the current
1293 class, and reset the class. */
1294 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1299 } while (c != '\0' && c != ',');
1307 case '=': case '+': case '*': case '%': case '?': case '!':
1308 case '0': case '1': case '2': case '3': case '4': case 'm':
1309 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1310 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1311 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1313 #ifdef EXTRA_CONSTRAINT
1314 case 'Q': case 'R': case 'S': case 'T': case 'U':
1319 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1324 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1328 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1333 /* Those of the registers which are clobbered, but allowed by the
1334 constraints, must be usable as reload registers. So clear them
1335 out of the life information. */
1336 AND_HARD_REG_SET (allowed, clobbered);
1337 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1338 if (TEST_HARD_REG_BIT (allowed, i))
1340 CLEAR_REGNO_REG_SET (chain->live_before, i);
1341 CLEAR_REGNO_REG_SET (chain->live_after, i);
1349 /* Walk the chain of insns, and determine for each whether it needs reloads
1350 and/or eliminations. Build the corresponding insns_need_reload list, and
1351 set something_needs_elimination as appropriate. */
1353 calculate_needs_all_insns (global)
1356 struct insn_chain **pprev_reload = &insns_need_reload;
1357 struct insn_chain **pchain;
1359 something_needs_elimination = 0;
1361 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1364 struct insn_chain *chain;
1369 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1370 include REG_LABEL), we need to see what effects this has on the
1371 known offsets at labels. */
1373 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1374 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1375 && REG_NOTES (insn) != 0))
1376 set_label_offsets (insn, insn, 0);
1378 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1380 rtx old_body = PATTERN (insn);
1381 int old_code = INSN_CODE (insn);
1382 rtx old_notes = REG_NOTES (insn);
1383 int did_elimination = 0;
1384 int operands_changed = 0;
1385 rtx set = single_set (insn);
1387 /* Skip insns that only set an equivalence. */
1388 if (set && GET_CODE (SET_DEST (set)) == REG
1389 && reg_renumber[REGNO (SET_DEST (set))] < 0
1390 && reg_equiv_constant[REGNO (SET_DEST (set))])
1392 /* Must clear out the shortcuts, in case they were set last
1394 chain->need_elim = 0;
1395 chain->need_reload = 0;
1396 chain->need_operand_change = 0;
1400 /* If needed, eliminate any eliminable registers. */
1401 if (num_eliminable || num_eliminable_invariants)
1402 did_elimination = eliminate_regs_in_insn (insn, 0);
1404 /* Analyze the instruction. */
1405 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1406 global, spill_reg_order);
1408 /* If a no-op set needs more than one reload, this is likely
1409 to be something that needs input address reloads. We
1410 can't get rid of this cleanly later, and it is of no use
1411 anyway, so discard it now.
1412 We only do this when expensive_optimizations is enabled,
1413 since this complements reload inheritance / output
1414 reload deletion, and it can make debugging harder. */
1415 if (flag_expensive_optimizations && n_reloads > 1)
1417 rtx set = single_set (insn);
1419 && SET_SRC (set) == SET_DEST (set)
1420 && GET_CODE (SET_SRC (set)) == REG
1421 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1423 PUT_CODE (insn, NOTE);
1424 NOTE_SOURCE_FILE (insn) = 0;
1425 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1430 update_eliminable_offsets ();
1432 /* Remember for later shortcuts which insns had any reloads or
1433 register eliminations. */
1434 chain->need_elim = did_elimination;
1435 chain->need_reload = n_reloads > 0;
1436 chain->need_operand_change = operands_changed;
1438 /* Discard any register replacements done. */
1439 if (did_elimination)
1441 obstack_free (&reload_obstack, reload_firstobj);
1442 PATTERN (insn) = old_body;
1443 INSN_CODE (insn) = old_code;
1444 REG_NOTES (insn) = old_notes;
1445 something_needs_elimination = 1;
1448 something_needs_operands_changed |= operands_changed;
1452 *pprev_reload = chain;
1453 pprev_reload = &chain->next_need_reload;
1455 calculate_needs (chain);
1462 /* Compute the most additional registers needed by one instruction,
1463 given by CHAIN. Collect information separately for each class of regs.
1465 To compute the number of reload registers of each class needed for an
1466 insn, we must simulate what choose_reload_regs can do. We do this by
1467 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1468 reloads are used in both. The input part uses those reloads,
1469 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1470 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1471 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1473 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1474 which are live for the entire output portion, and the maximum of all the
1475 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1477 The total number of registers needed is the maximum of the
1478 inputs and outputs. */
1481 calculate_needs (chain)
1482 struct insn_chain *chain;
1486 /* Each `struct needs' corresponds to one RELOAD_... type. */
1490 struct needs output;
1492 struct needs other_addr;
1493 struct needs op_addr;
1494 struct needs op_addr_reload;
1495 struct needs in_addr[MAX_RECOG_OPERANDS];
1496 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1497 struct needs out_addr[MAX_RECOG_OPERANDS];
1498 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1501 bzero ((char *) chain->group_size, sizeof chain->group_size);
1502 for (i = 0; i < N_REG_CLASSES; i++)
1503 chain->group_mode[i] = VOIDmode;
1504 bzero ((char *) &insn_needs, sizeof insn_needs);
1506 /* Count each reload once in every class
1507 containing the reload's own class. */
1509 for (i = 0; i < n_reloads; i++)
1511 register enum reg_class *p;
1512 enum reg_class class = reload_reg_class[i];
1514 enum machine_mode mode;
1515 struct needs *this_needs;
1517 /* Don't count the dummy reloads, for which one of the
1518 regs mentioned in the insn can be used for reloading.
1519 Don't count optional reloads.
1520 Don't count reloads that got combined with others. */
1521 if (reload_reg_rtx[i] != 0
1522 || reload_optional[i] != 0
1523 || (reload_out[i] == 0 && reload_in[i] == 0
1524 && ! reload_secondary_p[i]))
1527 mode = reload_inmode[i];
1528 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1529 mode = reload_outmode[i];
1530 size = CLASS_MAX_NREGS (class, mode);
1532 /* Decide which time-of-use to count this reload for. */
1533 switch (reload_when_needed[i])
1536 this_needs = &insn_needs.other;
1538 case RELOAD_FOR_INPUT:
1539 this_needs = &insn_needs.input;
1541 case RELOAD_FOR_OUTPUT:
1542 this_needs = &insn_needs.output;
1544 case RELOAD_FOR_INSN:
1545 this_needs = &insn_needs.insn;
1547 case RELOAD_FOR_OTHER_ADDRESS:
1548 this_needs = &insn_needs.other_addr;
1550 case RELOAD_FOR_INPUT_ADDRESS:
1551 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1553 case RELOAD_FOR_INPADDR_ADDRESS:
1554 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1556 case RELOAD_FOR_OUTPUT_ADDRESS:
1557 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1559 case RELOAD_FOR_OUTADDR_ADDRESS:
1560 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1562 case RELOAD_FOR_OPERAND_ADDRESS:
1563 this_needs = &insn_needs.op_addr;
1565 case RELOAD_FOR_OPADDR_ADDR:
1566 this_needs = &insn_needs.op_addr_reload;
1574 enum machine_mode other_mode, allocate_mode;
1576 /* Count number of groups needed separately from
1577 number of individual regs needed. */
1578 this_needs->groups[(int) class]++;
1579 p = reg_class_superclasses[(int) class];
1580 while (*p != LIM_REG_CLASSES)
1581 this_needs->groups[(int) *p++]++;
1583 /* Record size and mode of a group of this class. */
1584 /* If more than one size group is needed,
1585 make all groups the largest needed size. */
1586 if (chain->group_size[(int) class] < size)
1588 other_mode = chain->group_mode[(int) class];
1589 allocate_mode = mode;
1591 chain->group_size[(int) class] = size;
1592 chain->group_mode[(int) class] = mode;
1597 allocate_mode = chain->group_mode[(int) class];
1600 /* Crash if two dissimilar machine modes both need
1601 groups of consecutive regs of the same class. */
1603 if (other_mode != VOIDmode && other_mode != allocate_mode
1604 && ! modes_equiv_for_class_p (allocate_mode,
1606 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1611 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1612 p = reg_class_superclasses[(int) class];
1613 while (*p != LIM_REG_CLASSES)
1614 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1620 /* All reloads have been counted for this insn;
1621 now merge the various times of use.
1622 This sets insn_needs, etc., to the maximum total number
1623 of registers needed at any point in this insn. */
1625 for (i = 0; i < N_REG_CLASSES; i++)
1627 int j, in_max, out_max;
1629 /* Compute normal and nongroup needs. */
1630 for (j = 0; j <= 1; j++)
1633 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1635 in_max = MAX (in_max,
1636 (insn_needs.in_addr[k].regs[j][i]
1637 + insn_needs.in_addr_addr[k].regs[j][i]));
1638 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1639 out_max = MAX (out_max,
1640 insn_needs.out_addr_addr[k].regs[j][i]);
1643 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1644 and operand addresses but not things used to reload
1645 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1646 don't conflict with things needed to reload inputs or
1649 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1650 insn_needs.op_addr_reload.regs[j][i]),
1653 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1655 insn_needs.input.regs[j][i]
1656 = MAX (insn_needs.input.regs[j][i]
1657 + insn_needs.op_addr.regs[j][i]
1658 + insn_needs.insn.regs[j][i],
1659 in_max + insn_needs.input.regs[j][i]);
1661 insn_needs.output.regs[j][i] += out_max;
1662 insn_needs.other.regs[j][i]
1663 += MAX (MAX (insn_needs.input.regs[j][i],
1664 insn_needs.output.regs[j][i]),
1665 insn_needs.other_addr.regs[j][i]);
1669 /* Now compute group needs. */
1670 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1672 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1673 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1674 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1675 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1678 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1679 insn_needs.op_addr_reload.groups[i]),
1681 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1683 insn_needs.input.groups[i]
1684 = MAX (insn_needs.input.groups[i]
1685 + insn_needs.op_addr.groups[i]
1686 + insn_needs.insn.groups[i],
1687 in_max + insn_needs.input.groups[i]);
1689 insn_needs.output.groups[i] += out_max;
1690 insn_needs.other.groups[i]
1691 += MAX (MAX (insn_needs.input.groups[i],
1692 insn_needs.output.groups[i]),
1693 insn_needs.other_addr.groups[i]);
1696 /* Record the needs for later. */
1697 chain->need = insn_needs.other;
1700 /* Find a group of exactly 2 registers.
1702 First try to fill out the group by spilling a single register which
1703 would allow completion of the group.
1705 Then try to create a new group from a pair of registers, neither of
1706 which are explicitly used.
1708 Then try to create a group from any pair of registers. */
1711 find_tworeg_group (chain, class, dumpfile)
1712 struct insn_chain *chain;
1717 /* First, look for a register that will complete a group. */
1718 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1722 j = potential_reload_regs[i];
1723 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1724 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1725 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1726 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1727 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1728 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1729 /* We don't want one part of another group.
1730 We could get "two groups" that overlap! */
1731 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1732 || (j < FIRST_PSEUDO_REGISTER - 1
1733 && (other = j + 1, spill_reg_order[other] >= 0)
1734 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1735 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1736 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1737 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1738 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1740 register enum reg_class *p;
1742 /* We have found one that will complete a group,
1743 so count off one group as provided. */
1744 chain->need.groups[class]--;
1745 p = reg_class_superclasses[class];
1746 while (*p != LIM_REG_CLASSES)
1748 if (chain->group_size [(int) *p] <= chain->group_size [class])
1749 chain->need.groups[(int) *p]--;
1753 /* Indicate both these regs are part of a group. */
1754 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1755 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1759 /* We can't complete a group, so start one. */
1760 if (i == FIRST_PSEUDO_REGISTER)
1761 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1764 j = potential_reload_regs[i];
1765 /* Verify that J+1 is a potential reload reg. */
1766 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1767 if (potential_reload_regs[k] == j + 1)
1769 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1770 && k < FIRST_PSEUDO_REGISTER
1771 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1772 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1773 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1774 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1775 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1776 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1780 /* I should be the index in potential_reload_regs
1781 of the new reload reg we have found. */
1783 new_spill_reg (chain, i, class, 0, dumpfile);
1786 /* Find a group of more than 2 registers.
1787 Look for a sufficient sequence of unspilled registers, and spill them all
1791 find_group (chain, class, dumpfile)
1792 struct insn_chain *chain;
1798 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1800 int j = potential_reload_regs[i];
1803 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1804 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1807 /* Check each reg in the sequence. */
1808 for (k = 0; k < chain->group_size[class]; k++)
1809 if (! (spill_reg_order[j + k] < 0
1810 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1811 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1813 /* We got a full sequence, so spill them all. */
1814 if (k == chain->group_size[class])
1816 register enum reg_class *p;
1817 for (k = 0; k < chain->group_size[class]; k++)
1820 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1821 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1822 if (potential_reload_regs[idx] == j + k)
1824 new_spill_reg (chain, idx, class, 0, dumpfile);
1827 /* We have found one that will complete a group,
1828 so count off one group as provided. */
1829 chain->need.groups[class]--;
1830 p = reg_class_superclasses[class];
1831 while (*p != LIM_REG_CLASSES)
1833 if (chain->group_size [(int) *p]
1834 <= chain->group_size [class])
1835 chain->need.groups[(int) *p]--;
1842 /* There are no groups left. */
1843 spill_failure (chain->insn);
1847 /* If pseudo REG conflicts with one of our reload registers, mark it as
1850 maybe_mark_pseudo_spilled (reg)
1854 int r = reg_renumber[reg];
1859 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1860 for (i = 0; i < n_spills; i++)
1861 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1863 SET_REGNO_REG_SET (spilled_pseudos, reg);
1868 /* Find more reload regs to satisfy the remaining need of an insn, which
1870 Do it by ascending class number, since otherwise a reg
1871 might be spilled for a big class and might fail to count
1872 for a smaller class even though it belongs to that class.
1874 Count spilled regs in `spills', and add entries to
1875 `spill_regs' and `spill_reg_order'.
1877 ??? Note there is a problem here.
1878 When there is a need for a group in a high-numbered class,
1879 and also need for non-group regs that come from a lower class,
1880 the non-group regs are chosen first. If there aren't many regs,
1881 they might leave no room for a group.
1883 This was happening on the 386. To fix it, we added the code
1884 that calls possible_group_p, so that the lower class won't
1885 break up the last possible group.
1887 Really fixing the problem would require changes above
1888 in counting the regs already spilled, and in choose_reload_regs.
1889 It might be hard to avoid introducing bugs there. */
1892 find_reload_regs (chain, dumpfile)
1893 struct insn_chain *chain;
1897 short *group_needs = chain->need.groups;
1898 short *simple_needs = chain->need.regs[0];
1899 short *nongroup_needs = chain->need.regs[1];
1902 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1904 /* Compute the order of preference for hard registers to spill.
1905 Store them by decreasing preference in potential_reload_regs. */
1907 order_regs_for_reload (chain);
1909 /* So far, no hard regs have been spilled. */
1911 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1912 spill_reg_order[i] = -1;
1914 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1915 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1916 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1918 for (class = 0; class < N_REG_CLASSES; class++)
1920 /* First get the groups of registers.
1921 If we got single registers first, we might fragment
1923 while (group_needs[class] > 0)
1925 /* If any single spilled regs happen to form groups,
1926 count them now. Maybe we don't really need
1927 to spill another group. */
1928 count_possible_groups (chain, class);
1930 if (group_needs[class] <= 0)
1933 /* Groups of size 2, the only groups used on most machines,
1934 are treated specially. */
1935 if (chain->group_size[class] == 2)
1936 find_tworeg_group (chain, class, dumpfile);
1938 find_group (chain, class, dumpfile);
1943 /* Now similarly satisfy all need for single registers. */
1945 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1947 /* If we spilled enough regs, but they weren't counted
1948 against the non-group need, see if we can count them now.
1949 If so, we can avoid some actual spilling. */
1950 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1951 for (i = 0; i < n_spills; i++)
1953 int regno = spill_regs[i];
1954 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1955 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1956 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1957 && nongroup_needs[class] > 0)
1959 register enum reg_class *p;
1961 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1962 nongroup_needs[class]--;
1963 p = reg_class_superclasses[class];
1964 while (*p != LIM_REG_CLASSES)
1965 nongroup_needs[(int) *p++]--;
1969 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1972 /* Consider the potential reload regs that aren't
1973 yet in use as reload regs, in order of preference.
1974 Find the most preferred one that's in this class. */
1976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1978 int regno = potential_reload_regs[i];
1980 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1981 /* If this reg will not be available for groups,
1982 pick one that does not foreclose possible groups.
1983 This is a kludge, and not very general,
1984 but it should be sufficient to make the 386 work,
1985 and the problem should not occur on machines with
1987 && (nongroup_needs[class] == 0
1988 || possible_group_p (chain, regno)))
1992 /* If we couldn't get a register, try to get one even if we
1993 might foreclose possible groups. This may cause problems
1994 later, but that's better than aborting now, since it is
1995 possible that we will, in fact, be able to form the needed
1996 group even with this allocation. */
1998 if (i >= FIRST_PSEUDO_REGISTER
1999 && asm_noperands (chain->insn) < 0)
2000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2001 if (potential_reload_regs[i] >= 0
2002 && TEST_HARD_REG_BIT (reg_class_contents[class],
2003 potential_reload_regs[i]))
2006 /* I should be the index in potential_reload_regs
2007 of the new reload reg we have found. */
2009 new_spill_reg (chain, i, class, 1, dumpfile);
2015 /* We know which hard regs to use, now mark the pseudos that live in them
2016 as needing to be kicked out. */
2017 EXECUTE_IF_SET_IN_REG_SET
2018 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
2020 maybe_mark_pseudo_spilled (i);
2022 EXECUTE_IF_SET_IN_REG_SET
2023 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
2025 maybe_mark_pseudo_spilled (i);
2028 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
2032 dump_needs (chain, dumpfile)
2033 struct insn_chain *chain;
2036 static char *reg_class_names[] = REG_CLASS_NAMES;
2038 struct needs *n = &chain->need;
2040 for (i = 0; i < N_REG_CLASSES; i++)
2042 if (n->regs[i][0] > 0)
2044 ";; Need %d reg%s of class %s.\n",
2045 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2046 reg_class_names[i]);
2047 if (n->regs[i][1] > 0)
2049 ";; Need %d nongroup reg%s of class %s.\n",
2050 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2051 reg_class_names[i]);
2052 if (n->groups[i] > 0)
2054 ";; Need %d group%s (%smode) of class %s.\n",
2055 n->groups[i], n->groups[i] == 1 ? "" : "s",
2056 mode_name[(int) chain->group_mode[i]],
2057 reg_class_names[i]);
2061 /* Delete all insns that were inserted by emit_caller_save_insns during
2064 delete_caller_save_insns ()
2066 struct insn_chain *c = reload_insn_chain;
2070 while (c != 0 && c->is_caller_save_insn)
2072 struct insn_chain *next = c->next;
2075 if (insn == BLOCK_HEAD (c->block))
2076 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2077 if (insn == BLOCK_END (c->block))
2078 BLOCK_END (c->block) = PREV_INSN (insn);
2079 if (c == reload_insn_chain)
2080 reload_insn_chain = next;
2082 if (NEXT_INSN (insn) != 0)
2083 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2084 if (PREV_INSN (insn) != 0)
2085 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2088 next->prev = c->prev;
2090 c->prev->next = next;
2091 c->next = unused_insn_chains;
2092 unused_insn_chains = c;
2100 /* Nonzero if, after spilling reg REGNO for non-groups,
2101 it will still be possible to find a group if we still need one. */
2104 possible_group_p (chain, regno)
2105 struct insn_chain *chain;
2109 int class = (int) NO_REGS;
2111 for (i = 0; i < (int) N_REG_CLASSES; i++)
2112 if (chain->need.groups[i] > 0)
2118 if (class == (int) NO_REGS)
2121 /* Consider each pair of consecutive registers. */
2122 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2124 /* Ignore pairs that include reg REGNO. */
2125 if (i == regno || i + 1 == regno)
2128 /* Ignore pairs that are outside the class that needs the group.
2129 ??? Here we fail to handle the case where two different classes
2130 independently need groups. But this never happens with our
2131 current machine descriptions. */
2132 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2133 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2136 /* A pair of consecutive regs we can still spill does the trick. */
2137 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2138 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2139 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2142 /* A pair of one already spilled and one we can spill does it
2143 provided the one already spilled is not otherwise reserved. */
2144 if (spill_reg_order[i] < 0
2145 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2146 && spill_reg_order[i + 1] >= 0
2147 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2148 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2150 if (spill_reg_order[i + 1] < 0
2151 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2152 && spill_reg_order[i] >= 0
2153 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2154 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2161 /* Count any groups of CLASS that can be formed from the registers recently
2165 count_possible_groups (chain, class)
2166 struct insn_chain *chain;
2172 /* Now find all consecutive groups of spilled registers
2173 and mark each group off against the need for such groups.
2174 But don't count them against ordinary need, yet. */
2176 if (chain->group_size[class] == 0)
2179 CLEAR_HARD_REG_SET (new);
2181 /* Make a mask of all the regs that are spill regs in class I. */
2182 for (i = 0; i < n_spills; i++)
2184 int regno = spill_regs[i];
2186 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2187 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2188 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2189 SET_HARD_REG_BIT (new, regno);
2192 /* Find each consecutive group of them. */
2193 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2194 if (TEST_HARD_REG_BIT (new, i)
2195 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2196 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2198 for (j = 1; j < chain->group_size[class]; j++)
2199 if (! TEST_HARD_REG_BIT (new, i + j))
2202 if (j == chain->group_size[class])
2204 /* We found a group. Mark it off against this class's need for
2205 groups, and against each superclass too. */
2206 register enum reg_class *p;
2208 chain->need.groups[class]--;
2209 p = reg_class_superclasses[class];
2210 while (*p != LIM_REG_CLASSES)
2212 if (chain->group_size [(int) *p] <= chain->group_size [class])
2213 chain->need.groups[(int) *p]--;
2217 /* Don't count these registers again. */
2218 for (j = 0; j < chain->group_size[class]; j++)
2219 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2222 /* Skip to the last reg in this group. When i is incremented above,
2223 it will then point to the first reg of the next possible group. */
2228 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2229 another mode that needs to be reloaded for the same register class CLASS.
2230 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2231 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2233 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2234 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2235 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2236 causes unnecessary failures on machines requiring alignment of register
2237 groups when the two modes are different sizes, because the larger mode has
2238 more strict alignment rules than the smaller mode. */
2241 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2242 enum machine_mode allocate_mode, other_mode;
2243 enum reg_class class;
2246 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2248 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2249 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2250 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2256 /* Handle the failure to find a register to spill.
2257 INSN should be one of the insns which needed this particular spill reg. */
2260 spill_failure (insn)
2263 if (asm_noperands (PATTERN (insn)) >= 0)
2264 error_for_asm (insn, "`asm' needs too many reloads");
2266 fatal_insn ("Unable to find a register to spill.", insn);
2269 /* Add a new register to the tables of available spill-registers.
2270 CHAIN is the insn for which the register will be used; we decrease the
2272 I is the index of this register in potential_reload_regs.
2273 CLASS is the regclass whose need is being satisfied.
2274 NONGROUP is 0 if this register is part of a group.
2275 DUMPFILE is the same as the one that `reload' got. */
2278 new_spill_reg (chain, i, class, nongroup, dumpfile)
2279 struct insn_chain *chain;
2285 register enum reg_class *p;
2286 int regno = potential_reload_regs[i];
2288 if (i >= FIRST_PSEUDO_REGISTER)
2290 spill_failure (chain->insn);
2295 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2297 static char *reg_class_names[] = REG_CLASS_NAMES;
2299 if (asm_noperands (PATTERN (chain->insn)) < 0)
2301 /* The error message is still correct - we know only that it wasn't
2302 an asm statement that caused the problem, but one of the global
2303 registers declared by the users might have screwed us. */
2304 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2305 regno, reg_names[regno], reg_class_names[class]);
2306 error ("This may be due to a compiler bug or to impossible asm");
2307 error ("statements or clauses.");
2308 fatal_insn ("This is the instruction:", chain->insn);
2310 error_for_asm (chain->insn, "Invalid `asm' statement:");
2311 error_for_asm (chain->insn,
2312 "fixed or forbidden register %d (%s) was spilled for class %s.",
2313 regno, reg_names[regno], reg_class_names[class]);
2318 /* Make reg REGNO an additional reload reg. */
2320 potential_reload_regs[i] = -1;
2321 spill_regs[n_spills] = regno;
2322 spill_reg_order[regno] = n_spills;
2324 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2325 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2327 /* Clear off the needs we just satisfied. */
2329 chain->need.regs[0][class]--;
2330 p = reg_class_superclasses[class];
2331 while (*p != LIM_REG_CLASSES)
2332 chain->need.regs[0][(int) *p++]--;
2334 if (nongroup && chain->need.regs[1][class] > 0)
2336 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2337 chain->need.regs[1][class]--;
2338 p = reg_class_superclasses[class];
2339 while (*p != LIM_REG_CLASSES)
2340 chain->need.regs[1][(int) *p++]--;
2346 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2347 data that is dead in INSN. */
2350 delete_dead_insn (insn)
2353 rtx prev = prev_real_insn (insn);
2356 /* If the previous insn sets a register that dies in our insn, delete it
2358 if (prev && GET_CODE (PATTERN (prev)) == SET
2359 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2360 && reg_mentioned_p (prev_dest, PATTERN (insn))
2361 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2362 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2363 delete_dead_insn (prev);
2365 PUT_CODE (insn, NOTE);
2366 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2367 NOTE_SOURCE_FILE (insn) = 0;
2370 /* Modify the home of pseudo-reg I.
2371 The new home is present in reg_renumber[I].
2373 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2374 or it may be -1, meaning there is none or it is not relevant.
2375 This is used so that all pseudos spilled from a given hard reg
2376 can share one stack slot. */
2379 alter_reg (i, from_reg)
2383 /* When outputting an inline function, this can happen
2384 for a reg that isn't actually used. */
2385 if (regno_reg_rtx[i] == 0)
2388 /* If the reg got changed to a MEM at rtl-generation time,
2390 if (GET_CODE (regno_reg_rtx[i]) != REG)
2393 /* Modify the reg-rtx to contain the new hard reg
2394 number or else to contain its pseudo reg number. */
2395 REGNO (regno_reg_rtx[i])
2396 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2398 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2399 allocate a stack slot for it. */
2401 if (reg_renumber[i] < 0
2402 && REG_N_REFS (i) > 0
2403 && reg_equiv_constant[i] == 0
2404 && reg_equiv_memory_loc[i] == 0)
2407 int inherent_size = PSEUDO_REGNO_BYTES (i);
2408 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2411 /* Each pseudo reg has an inherent size which comes from its own mode,
2412 and a total size which provides room for paradoxical subregs
2413 which refer to the pseudo reg in wider modes.
2415 We can use a slot already allocated if it provides both
2416 enough inherent space and enough total space.
2417 Otherwise, we allocate a new slot, making sure that it has no less
2418 inherent space, and no less total space, then the previous slot. */
2421 /* No known place to spill from => no slot to reuse. */
2422 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2423 inherent_size == total_size ? 0 : -1);
2424 if (BYTES_BIG_ENDIAN)
2425 /* Cancel the big-endian correction done in assign_stack_local.
2426 Get the address of the beginning of the slot.
2427 This is so we can do a big-endian correction unconditionally
2429 adjust = inherent_size - total_size;
2431 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2433 /* Reuse a stack slot if possible. */
2434 else if (spill_stack_slot[from_reg] != 0
2435 && spill_stack_slot_width[from_reg] >= total_size
2436 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2438 x = spill_stack_slot[from_reg];
2439 /* Allocate a bigger slot. */
2442 /* Compute maximum size needed, both for inherent size
2443 and for total size. */
2444 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2446 if (spill_stack_slot[from_reg])
2448 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2450 mode = GET_MODE (spill_stack_slot[from_reg]);
2451 if (spill_stack_slot_width[from_reg] > total_size)
2452 total_size = spill_stack_slot_width[from_reg];
2454 /* Make a slot with that size. */
2455 x = assign_stack_local (mode, total_size,
2456 inherent_size == total_size ? 0 : -1);
2458 if (BYTES_BIG_ENDIAN)
2460 /* Cancel the big-endian correction done in assign_stack_local.
2461 Get the address of the beginning of the slot.
2462 This is so we can do a big-endian correction unconditionally
2464 adjust = GET_MODE_SIZE (mode) - total_size;
2466 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2469 plus_constant (XEXP (x, 0), adjust));
2471 spill_stack_slot[from_reg] = stack_slot;
2472 spill_stack_slot_width[from_reg] = total_size;
2475 /* On a big endian machine, the "address" of the slot
2476 is the address of the low part that fits its inherent mode. */
2477 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2478 adjust += (total_size - inherent_size);
2480 /* If we have any adjustment to make, or if the stack slot is the
2481 wrong mode, make a new stack slot. */
2482 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2484 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2485 plus_constant (XEXP (x, 0), adjust));
2487 /* If this was shared among registers, must ensure we never
2488 set it readonly since that can cause scheduling
2489 problems. Note we would only have in this adjustment
2490 case in any event, since the code above doesn't set it. */
2493 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2496 /* Save the stack slot for later. */
2497 reg_equiv_memory_loc[i] = x;
2501 /* Mark the slots in regs_ever_live for the hard regs
2502 used by pseudo-reg number REGNO. */
2505 mark_home_live (regno)
2508 register int i, lim;
2509 i = reg_renumber[regno];
2512 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2514 regs_ever_live[i++] = 1;
2517 /* This function handles the tracking of elimination offsets around branches.
2519 X is a piece of RTL being scanned.
2521 INSN is the insn that it came from, if any.
2523 INITIAL_P is non-zero if we are to set the offset to be the initial
2524 offset and zero if we are setting the offset of the label to be the
2528 set_label_offsets (x, insn, initial_p)
2533 enum rtx_code code = GET_CODE (x);
2536 struct elim_table *p;
2541 if (LABEL_REF_NONLOCAL_P (x))
2546 /* ... fall through ... */
2549 /* If we know nothing about this label, set the desired offsets. Note
2550 that this sets the offset at a label to be the offset before a label
2551 if we don't know anything about the label. This is not correct for
2552 the label after a BARRIER, but is the best guess we can make. If
2553 we guessed wrong, we will suppress an elimination that might have
2554 been possible had we been able to guess correctly. */
2556 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2558 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2559 offsets_at[CODE_LABEL_NUMBER (x)][i]
2560 = (initial_p ? reg_eliminate[i].initial_offset
2561 : reg_eliminate[i].offset);
2562 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2565 /* Otherwise, if this is the definition of a label and it is
2566 preceded by a BARRIER, set our offsets to the known offset of
2570 && (tem = prev_nonnote_insn (insn)) != 0
2571 && GET_CODE (tem) == BARRIER)
2572 set_offsets_for_label (insn);
2574 /* If neither of the above cases is true, compare each offset
2575 with those previously recorded and suppress any eliminations
2576 where the offsets disagree. */
2578 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2579 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2580 != (initial_p ? reg_eliminate[i].initial_offset
2581 : reg_eliminate[i].offset))
2582 reg_eliminate[i].can_eliminate = 0;
2587 set_label_offsets (PATTERN (insn), insn, initial_p);
2589 /* ... fall through ... */
2593 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2594 and hence must have all eliminations at their initial offsets. */
2595 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2596 if (REG_NOTE_KIND (tem) == REG_LABEL)
2597 set_label_offsets (XEXP (tem, 0), insn, 1);
2602 /* Each of the labels in the address vector must be at their initial
2603 offsets. We want the first field for ADDR_VEC and the second
2604 field for ADDR_DIFF_VEC. */
2606 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2607 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2612 /* We only care about setting PC. If the source is not RETURN,
2613 IF_THEN_ELSE, or a label, disable any eliminations not at
2614 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2615 isn't one of those possibilities. For branches to a label,
2616 call ourselves recursively.
2618 Note that this can disable elimination unnecessarily when we have
2619 a non-local goto since it will look like a non-constant jump to
2620 someplace in the current function. This isn't a significant
2621 problem since such jumps will normally be when all elimination
2622 pairs are back to their initial offsets. */
2624 if (SET_DEST (x) != pc_rtx)
2627 switch (GET_CODE (SET_SRC (x)))
2634 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2638 tem = XEXP (SET_SRC (x), 1);
2639 if (GET_CODE (tem) == LABEL_REF)
2640 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2641 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2644 tem = XEXP (SET_SRC (x), 2);
2645 if (GET_CODE (tem) == LABEL_REF)
2646 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2647 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2655 /* If we reach here, all eliminations must be at their initial
2656 offset because we are doing a jump to a variable address. */
2657 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2658 if (p->offset != p->initial_offset)
2659 p->can_eliminate = 0;
2667 /* Used for communication between the next two function to properly share
2668 the vector for an ASM_OPERANDS. */
2670 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2672 /* Scan X and replace any eliminable registers (such as fp) with a
2673 replacement (such as sp), plus an offset.
2675 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2676 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2677 MEM, we are allowed to replace a sum of a register and the constant zero
2678 with the register, which we cannot do outside a MEM. In addition, we need
2679 to record the fact that a register is referenced outside a MEM.
2681 If INSN is an insn, it is the insn containing X. If we replace a REG
2682 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2683 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2684 the REG is being modified.
2686 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2687 That's used when we eliminate in expressions stored in notes.
2688 This means, do not set ref_outside_mem even if the reference
2691 If we see a modification to a register we know about, take the
2692 appropriate action (see case SET, below).
2694 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2695 replacements done assuming all offsets are at their initial values. If
2696 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2697 encounter, return the actual location so that find_reloads will do
2698 the proper thing. */
2701 eliminate_regs (x, mem_mode, insn)
2703 enum machine_mode mem_mode;
2706 enum rtx_code code = GET_CODE (x);
2707 struct elim_table *ep;
2714 if (! current_function_decl)
2733 /* This is only for the benefit of the debugging backends, which call
2734 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2735 removed after CSE. */
2736 new = eliminate_regs (XEXP (x, 0), 0, insn);
2737 if (GET_CODE (new) == MEM)
2738 return XEXP (new, 0);
2744 /* First handle the case where we encounter a bare register that
2745 is eliminable. Replace it with a PLUS. */
2746 if (regno < FIRST_PSEUDO_REGISTER)
2748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2750 if (ep->from_rtx == x && ep->can_eliminate)
2753 /* Refs inside notes don't count for this purpose. */
2754 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2755 || GET_CODE (insn) == INSN_LIST)))
2756 ep->ref_outside_mem = 1;
2757 return plus_constant (ep->to_rtx, ep->previous_offset);
2761 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2762 && reg_equiv_constant[regno]
2763 && ! CONSTANT_P (reg_equiv_constant[regno]))
2764 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2769 /* If this is the sum of an eliminable register and a constant, rework
2771 if (GET_CODE (XEXP (x, 0)) == REG
2772 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2773 && CONSTANT_P (XEXP (x, 1)))
2775 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2777 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2780 /* Refs inside notes don't count for this purpose. */
2781 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2782 || GET_CODE (insn) == INSN_LIST)))
2783 ep->ref_outside_mem = 1;
2785 /* The only time we want to replace a PLUS with a REG (this
2786 occurs when the constant operand of the PLUS is the negative
2787 of the offset) is when we are inside a MEM. We won't want
2788 to do so at other times because that would change the
2789 structure of the insn in a way that reload can't handle.
2790 We special-case the commonest situation in
2791 eliminate_regs_in_insn, so just replace a PLUS with a
2792 PLUS here, unless inside a MEM. */
2793 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2794 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2797 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2798 plus_constant (XEXP (x, 1),
2799 ep->previous_offset));
2802 /* If the register is not eliminable, we are done since the other
2803 operand is a constant. */
2807 /* If this is part of an address, we want to bring any constant to the
2808 outermost PLUS. We will do this by doing register replacement in
2809 our operands and seeing if a constant shows up in one of them.
2811 We assume here this is part of an address (or a "load address" insn)
2812 since an eliminable register is not likely to appear in any other
2815 If we have (plus (eliminable) (reg)), we want to produce
2816 (plus (plus (replacement) (reg) (const))). If this was part of a
2817 normal add insn, (plus (replacement) (reg)) will be pushed as a
2818 reload. This is the desired action. */
2821 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2822 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2824 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2826 /* If one side is a PLUS and the other side is a pseudo that
2827 didn't get a hard register but has a reg_equiv_constant,
2828 we must replace the constant here since it may no longer
2829 be in the position of any operand. */
2830 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2831 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2832 && reg_renumber[REGNO (new1)] < 0
2833 && reg_equiv_constant != 0
2834 && reg_equiv_constant[REGNO (new1)] != 0)
2835 new1 = reg_equiv_constant[REGNO (new1)];
2836 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2837 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2838 && reg_renumber[REGNO (new0)] < 0
2839 && reg_equiv_constant[REGNO (new0)] != 0)
2840 new0 = reg_equiv_constant[REGNO (new0)];
2842 new = form_sum (new0, new1);
2844 /* As above, if we are not inside a MEM we do not want to
2845 turn a PLUS into something else. We might try to do so here
2846 for an addition of 0 if we aren't optimizing. */
2847 if (! mem_mode && GET_CODE (new) != PLUS)
2848 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2856 /* If this is the product of an eliminable register and a
2857 constant, apply the distribute law and move the constant out
2858 so that we have (plus (mult ..) ..). This is needed in order
2859 to keep load-address insns valid. This case is pathological.
2860 We ignore the possibility of overflow here. */
2861 if (GET_CODE (XEXP (x, 0)) == REG
2862 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2863 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2864 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2866 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2869 /* Refs inside notes don't count for this purpose. */
2870 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2871 || GET_CODE (insn) == INSN_LIST)))
2872 ep->ref_outside_mem = 1;
2875 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2876 ep->previous_offset * INTVAL (XEXP (x, 1)));
2879 /* ... fall through ... */
2884 case DIV: case UDIV:
2885 case MOD: case UMOD:
2886 case AND: case IOR: case XOR:
2887 case ROTATERT: case ROTATE:
2888 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2890 case GE: case GT: case GEU: case GTU:
2891 case LE: case LT: case LEU: case LTU:
2893 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2895 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2897 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2898 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2903 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2906 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2907 if (new != XEXP (x, 0))
2909 /* If this is a REG_DEAD note, it is not valid anymore.
2910 Using the eliminated version could result in creating a
2911 REG_DEAD note for the stack or frame pointer. */
2912 if (GET_MODE (x) == REG_DEAD)
2914 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2917 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2921 /* ... fall through ... */
2924 /* Now do eliminations in the rest of the chain. If this was
2925 an EXPR_LIST, this might result in allocating more memory than is
2926 strictly needed, but it simplifies the code. */
2929 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2930 if (new != XEXP (x, 1))
2931 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2939 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2940 if (ep->to_rtx == XEXP (x, 0))
2942 int size = GET_MODE_SIZE (mem_mode);
2944 /* If more bytes than MEM_MODE are pushed, account for them. */
2945 #ifdef PUSH_ROUNDING
2946 if (ep->to_rtx == stack_pointer_rtx)
2947 size = PUSH_ROUNDING (size);
2949 if (code == PRE_DEC || code == POST_DEC)
2955 /* Fall through to generic unary operation case. */
2956 case STRICT_LOW_PART:
2958 case SIGN_EXTEND: case ZERO_EXTEND:
2959 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2960 case FLOAT: case FIX:
2961 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2965 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2966 if (new != XEXP (x, 0))
2967 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2971 /* Similar to above processing, but preserve SUBREG_WORD.
2972 Convert (subreg (mem)) to (mem) if not paradoxical.
2973 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2974 pseudo didn't get a hard reg, we must replace this with the
2975 eliminated version of the memory location because push_reloads
2976 may do the replacement in certain circumstances. */
2977 if (GET_CODE (SUBREG_REG (x)) == REG
2978 && (GET_MODE_SIZE (GET_MODE (x))
2979 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2980 && reg_equiv_memory_loc != 0
2981 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2984 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2987 /* If we didn't change anything, we must retain the pseudo. */
2988 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2989 new = SUBREG_REG (x);
2992 /* In this case, we must show that the pseudo is used in this
2993 insn so that delete_output_reload will do the right thing. */
2994 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2995 && GET_CODE (insn) != INSN_LIST)
2996 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2999 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3001 /* Ensure NEW isn't shared in case we have to reload it. */
3002 new = copy_rtx (new);
3005 new = SUBREG_REG (x);
3009 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3011 if (new != XEXP (x, 0))
3013 int x_size = GET_MODE_SIZE (GET_MODE (x));
3014 int new_size = GET_MODE_SIZE (GET_MODE (new));
3016 if (GET_CODE (new) == MEM
3017 && ((x_size < new_size
3018 #ifdef WORD_REGISTER_OPERATIONS
3019 /* On these machines, combine can create rtl of the form
3020 (set (subreg:m1 (reg:m2 R) 0) ...)
3021 where m1 < m2, and expects something interesting to
3022 happen to the entire word. Moreover, it will use the
3023 (reg:m2 R) later, expecting all bits to be preserved.
3024 So if the number of words is the same, preserve the
3025 subreg so that push_reloads can see it. */
3026 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3029 || (x_size == new_size))
3032 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3033 enum machine_mode mode = GET_MODE (x);
3035 if (BYTES_BIG_ENDIAN)
3036 offset += (MIN (UNITS_PER_WORD,
3037 GET_MODE_SIZE (GET_MODE (new)))
3038 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3040 PUT_MODE (new, mode);
3041 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3045 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3051 /* If using a register that is the source of an eliminate we still
3052 think can be performed, note it cannot be performed since we don't
3053 know how this register is used. */
3054 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3055 if (ep->from_rtx == XEXP (x, 0))
3056 ep->can_eliminate = 0;
3058 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3059 if (new != XEXP (x, 0))
3060 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3064 /* If clobbering a register that is the replacement register for an
3065 elimination we still think can be performed, note that it cannot
3066 be performed. Otherwise, we need not be concerned about it. */
3067 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3068 if (ep->to_rtx == XEXP (x, 0))
3069 ep->can_eliminate = 0;
3071 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3072 if (new != XEXP (x, 0))
3073 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3079 /* Properly handle sharing input and constraint vectors. */
3080 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3082 /* When we come to a new vector not seen before,
3083 scan all its elements; keep the old vector if none
3084 of them changes; otherwise, make a copy. */
3085 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3086 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3087 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3088 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3091 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3092 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3095 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3096 new_asm_operands_vec = old_asm_operands_vec;
3098 new_asm_operands_vec
3099 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3102 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3103 if (new_asm_operands_vec == old_asm_operands_vec)
3106 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3107 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3108 ASM_OPERANDS_OUTPUT_IDX (x),
3109 new_asm_operands_vec,
3110 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3111 ASM_OPERANDS_SOURCE_FILE (x),
3112 ASM_OPERANDS_SOURCE_LINE (x));
3113 new->volatil = x->volatil;
3118 /* Check for setting a register that we know about. */
3119 if (GET_CODE (SET_DEST (x)) == REG)
3121 /* See if this is setting the replacement register for an
3124 If DEST is the hard frame pointer, we do nothing because we
3125 assume that all assignments to the frame pointer are for
3126 non-local gotos and are being done at a time when they are valid
3127 and do not disturb anything else. Some machines want to
3128 eliminate a fake argument pointer (or even a fake frame pointer)
3129 with either the real frame or the stack pointer. Assignments to
3130 the hard frame pointer must not prevent this elimination. */
3132 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3134 if (ep->to_rtx == SET_DEST (x)
3135 && SET_DEST (x) != hard_frame_pointer_rtx)
3137 /* If it is being incremented, adjust the offset. Otherwise,
3138 this elimination can't be done. */
3139 rtx src = SET_SRC (x);
3141 if (GET_CODE (src) == PLUS
3142 && XEXP (src, 0) == SET_DEST (x)
3143 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3144 ep->offset -= INTVAL (XEXP (src, 1));
3146 ep->can_eliminate = 0;
3149 /* Now check to see we are assigning to a register that can be
3150 eliminated. If so, it must be as part of a PARALLEL, since we
3151 will not have been called if this is a single SET. So indicate
3152 that we can no longer eliminate this reg. */
3153 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3155 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3156 ep->can_eliminate = 0;
3159 /* Now avoid the loop below in this common case. */
3161 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3162 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3164 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3165 write a CLOBBER insn. */
3166 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3167 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3168 && GET_CODE (insn) != INSN_LIST)
3169 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3171 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3172 return gen_rtx_SET (VOIDmode, new0, new1);
3178 /* This is only for the benefit of the debugging backends, which call
3179 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3180 removed after CSE. */
3181 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3182 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3184 /* Our only special processing is to pass the mode of the MEM to our
3185 recursive call and copy the flags. While we are here, handle this
3186 case more efficiently. */
3187 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3188 if (new != XEXP (x, 0))
3190 new = gen_rtx_MEM (GET_MODE (x), new);
3191 new->volatil = x->volatil;
3192 new->unchanging = x->unchanging;
3193 new->in_struct = x->in_struct;
3203 /* Process each of our operands recursively. If any have changed, make a
3205 fmt = GET_RTX_FORMAT (code);
3206 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3210 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3211 if (new != XEXP (x, i) && ! copied)
3213 rtx new_x = rtx_alloc (code);
3214 bcopy ((char *) x, (char *) new_x,
3215 (sizeof (*new_x) - sizeof (new_x->fld)
3216 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3222 else if (*fmt == 'E')
3225 for (j = 0; j < XVECLEN (x, i); j++)
3227 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3228 if (new != XVECEXP (x, i, j) && ! copied_vec)
3230 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3234 rtx new_x = rtx_alloc (code);
3235 bcopy ((char *) x, (char *) new_x,
3236 (sizeof (*new_x) - sizeof (new_x->fld)
3237 + (sizeof (new_x->fld[0])
3238 * GET_RTX_LENGTH (code))));
3242 XVEC (x, i) = new_v;
3245 XVECEXP (x, i, j) = new;
3253 /* Scan INSN and eliminate all eliminable registers in it.
3255 If REPLACE is nonzero, do the replacement destructively. Also
3256 delete the insn as dead it if it is setting an eliminable register.
3258 If REPLACE is zero, do all our allocations in reload_obstack.
3260 If no eliminations were done and this insn doesn't require any elimination
3261 processing (these are not identical conditions: it might be updating sp,
3262 but not referencing fp; this needs to be seen during reload_as_needed so
3263 that the offset between fp and sp can be taken into consideration), zero
3264 is returned. Otherwise, 1 is returned. */
3267 eliminate_regs_in_insn (insn, replace)
3271 rtx old_body = PATTERN (insn);
3272 rtx old_set = single_set (insn);
3275 struct elim_table *ep;
3278 push_obstacks (&reload_obstack, &reload_obstack);
3280 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3281 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3283 /* Check for setting an eliminable register. */
3284 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3285 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3287 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3288 /* If this is setting the frame pointer register to the
3289 hardware frame pointer register and this is an elimination
3290 that will be done (tested above), this insn is really
3291 adjusting the frame pointer downward to compensate for
3292 the adjustment done before a nonlocal goto. */
3293 if (ep->from == FRAME_POINTER_REGNUM
3294 && ep->to == HARD_FRAME_POINTER_REGNUM)
3296 rtx src = SET_SRC (old_set);
3297 int offset = 0, ok = 0;
3298 rtx prev_insn, prev_set;
3300 if (src == ep->to_rtx)
3302 else if (GET_CODE (src) == PLUS
3303 && GET_CODE (XEXP (src, 0)) == CONST_INT
3304 && XEXP (src, 1) == ep->to_rtx)
3305 offset = INTVAL (XEXP (src, 0)), ok = 1;
3306 else if (GET_CODE (src) == PLUS
3307 && GET_CODE (XEXP (src, 1)) == CONST_INT
3308 && XEXP (src, 0) == ep->to_rtx)
3309 offset = INTVAL (XEXP (src, 1)), ok = 1;
3310 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3311 && (prev_set = single_set (prev_insn)) != 0
3312 && rtx_equal_p (SET_DEST (prev_set), src))
3314 src = SET_SRC (prev_set);
3315 if (src == ep->to_rtx)
3317 else if (GET_CODE (src) == PLUS
3318 && GET_CODE (XEXP (src, 0)) == CONST_INT
3319 && XEXP (src, 1) == ep->to_rtx)
3320 offset = INTVAL (XEXP (src, 0)), ok = 1;
3321 else if (GET_CODE (src) == PLUS
3322 && GET_CODE (XEXP (src, 1)) == CONST_INT
3323 && XEXP (src, 0) == ep->to_rtx)
3324 offset = INTVAL (XEXP (src, 1)), ok = 1;
3332 = plus_constant (ep->to_rtx, offset - ep->offset);
3334 /* First see if this insn remains valid when we
3335 make the change. If not, keep the INSN_CODE
3336 the same and let reload fit it up. */
3337 validate_change (insn, &SET_SRC (old_set), src, 1);
3338 validate_change (insn, &SET_DEST (old_set),
3340 if (! apply_change_group ())
3342 SET_SRC (old_set) = src;
3343 SET_DEST (old_set) = ep->to_rtx;
3353 /* In this case this insn isn't serving a useful purpose. We
3354 will delete it in reload_as_needed once we know that this
3355 elimination is, in fact, being done.
3357 If REPLACE isn't set, we can't delete this insn, but needn't
3358 process it since it won't be used unless something changes. */
3360 delete_dead_insn (insn);
3365 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3366 in the insn is the negative of the offset in FROM. Substitute
3367 (set (reg) (reg to)) for the insn and change its code.
3369 We have to do this here, rather than in eliminate_regs, so that we can
3370 change the insn code. */
3372 if (GET_CODE (SET_SRC (old_set)) == PLUS
3373 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3374 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3375 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3377 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3378 && ep->can_eliminate)
3380 /* We must stop at the first elimination that will be used.
3381 If this one would replace the PLUS with a REG, do it
3382 now. Otherwise, quit the loop and let eliminate_regs
3383 do its normal replacement. */
3384 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3386 /* We assume here that we don't need a PARALLEL of
3387 any CLOBBERs for this assignment. There's not
3388 much we can do if we do need it. */
3389 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3392 INSN_CODE (insn) = -1;
3401 old_asm_operands_vec = 0;
3403 /* Replace the body of this insn with a substituted form. If we changed
3404 something, return non-zero.
3406 If we are replacing a body that was a (set X (plus Y Z)), try to
3407 re-recognize the insn. We do this in case we had a simple addition
3408 but now can do this as a load-address. This saves an insn in this
3411 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3412 if (new_body != old_body)
3414 /* If we aren't replacing things permanently and we changed something,
3415 make another copy to ensure that all the RTL is new. Otherwise
3416 things can go wrong if find_reload swaps commutative operands
3417 and one is inside RTL that has been copied while the other is not. */
3419 /* Don't copy an asm_operands because (1) there's no need and (2)
3420 copy_rtx can't do it properly when there are multiple outputs. */
3421 if (! replace && asm_noperands (old_body) < 0)
3422 new_body = copy_rtx (new_body);
3424 /* If we had a move insn but now we don't, rerecognize it. This will
3425 cause spurious re-recognition if the old move had a PARALLEL since
3426 the new one still will, but we can't call single_set without
3427 having put NEW_BODY into the insn and the re-recognition won't
3428 hurt in this rare case. */
3430 && ((GET_CODE (SET_SRC (old_set)) == REG
3431 && (GET_CODE (new_body) != SET
3432 || GET_CODE (SET_SRC (new_body)) != REG))
3433 /* If this was a load from or store to memory, compare
3434 the MEM in recog_operand to the one in the insn. If they
3435 are not equal, then rerecognize the insn. */
3437 && ((GET_CODE (SET_SRC (old_set)) == MEM
3438 && SET_SRC (old_set) != recog_operand[1])
3439 || (GET_CODE (SET_DEST (old_set)) == MEM
3440 && SET_DEST (old_set) != recog_operand[0])))
3441 /* If this was an add insn before, rerecognize. */
3442 || GET_CODE (SET_SRC (old_set)) == PLUS))
3444 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3445 /* If recognition fails, store the new body anyway.
3446 It's normal to have recognition failures here
3447 due to bizarre memory addresses; reloading will fix them. */
3448 PATTERN (insn) = new_body;
3451 PATTERN (insn) = new_body;
3456 /* Loop through all elimination pairs. See if any have changed.
3458 We also detect a cases where register elimination cannot be done,
3459 namely, if a register would be both changed and referenced outside a MEM
3460 in the resulting insn since such an insn is often undefined and, even if
3461 not, we cannot know what meaning will be given to it. Note that it is
3462 valid to have a register used in an address in an insn that changes it
3463 (presumably with a pre- or post-increment or decrement).
3465 If anything changes, return nonzero. */
3467 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3469 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3470 ep->can_eliminate = 0;
3472 ep->ref_outside_mem = 0;
3474 if (ep->previous_offset != ep->offset)
3479 /* If we changed something, perform elimination in REG_NOTES. This is
3480 needed even when REPLACE is zero because a REG_DEAD note might refer
3481 to a register that we eliminate and could cause a different number
3482 of spill registers to be needed in the final reload pass than in
3484 if (val && REG_NOTES (insn) != 0)
3485 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3493 /* Loop through all elimination pairs.
3494 Recalculate the number not at initial offset.
3496 Compute the maximum offset (minimum offset if the stack does not
3497 grow downward) for each elimination pair. */
3500 update_eliminable_offsets ()
3502 struct elim_table *ep;
3504 num_not_at_initial_offset = 0;
3505 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3507 ep->previous_offset = ep->offset;
3508 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3509 num_not_at_initial_offset++;
3513 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3514 replacement we currently believe is valid, mark it as not eliminable if X
3515 modifies DEST in any way other than by adding a constant integer to it.
3517 If DEST is the frame pointer, we do nothing because we assume that
3518 all assignments to the hard frame pointer are nonlocal gotos and are being
3519 done at a time when they are valid and do not disturb anything else.
3520 Some machines want to eliminate a fake argument pointer with either the
3521 frame or stack pointer. Assignments to the hard frame pointer must not
3522 prevent this elimination.
3524 Called via note_stores from reload before starting its passes to scan
3525 the insns of the function. */
3528 mark_not_eliminable (dest, x)
3532 register unsigned int i;
3534 /* A SUBREG of a hard register here is just changing its mode. We should
3535 not see a SUBREG of an eliminable hard register, but check just in
3537 if (GET_CODE (dest) == SUBREG)
3538 dest = SUBREG_REG (dest);
3540 if (dest == hard_frame_pointer_rtx)
3543 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3544 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3545 && (GET_CODE (x) != SET
3546 || GET_CODE (SET_SRC (x)) != PLUS
3547 || XEXP (SET_SRC (x), 0) != dest
3548 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3550 reg_eliminate[i].can_eliminate_previous
3551 = reg_eliminate[i].can_eliminate = 0;
3556 /* Verify that the initial elimination offsets did not change since the
3557 last call to set_initial_elim_offsets. This is used to catch cases
3558 where something illegal happened during reload_as_needed that could
3559 cause incorrect code to be generated if we did not check for it. */
3561 verify_initial_elim_offsets ()
3565 #ifdef ELIMINABLE_REGS
3566 struct elim_table *ep;
3568 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3570 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3571 if (t != ep->initial_offset)
3575 INITIAL_FRAME_POINTER_OFFSET (t);
3576 if (t != reg_eliminate[0].initial_offset)
3581 /* Reset all offsets on eliminable registers to their initial values. */
3583 set_initial_elim_offsets ()
3585 struct elim_table *ep = reg_eliminate;
3587 #ifdef ELIMINABLE_REGS
3588 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3590 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3591 ep->previous_offset = ep->offset = ep->initial_offset;
3594 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3595 ep->previous_offset = ep->offset = ep->initial_offset;
3598 num_not_at_initial_offset = 0;
3601 /* Initialize the known label offsets.
3602 Set a known offset for each forced label to be at the initial offset
3603 of each elimination. We do this because we assume that all
3604 computed jumps occur from a location where each elimination is
3605 at its initial offset.
3606 For all other labels, show that we don't know the offsets. */
3609 set_initial_label_offsets ()
3612 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3614 for (x = forced_labels; x; x = XEXP (x, 1))
3616 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3619 /* Set all elimination offsets to the known values for the code label given
3622 set_offsets_for_label (insn)
3626 int label_nr = CODE_LABEL_NUMBER (insn);
3627 struct elim_table *ep;
3629 num_not_at_initial_offset = 0;
3630 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3632 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3633 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3634 num_not_at_initial_offset++;
3638 /* See if anything that happened changes which eliminations are valid.
3639 For example, on the Sparc, whether or not the frame pointer can
3640 be eliminated can depend on what registers have been used. We need
3641 not check some conditions again (such as flag_omit_frame_pointer)
3642 since they can't have changed. */
3645 update_eliminables (pset)
3648 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3649 int previous_frame_pointer_needed = frame_pointer_needed;
3651 struct elim_table *ep;
3653 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3654 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3655 #ifdef ELIMINABLE_REGS
3656 || ! CAN_ELIMINATE (ep->from, ep->to)
3659 ep->can_eliminate = 0;
3661 /* Look for the case where we have discovered that we can't replace
3662 register A with register B and that means that we will now be
3663 trying to replace register A with register C. This means we can
3664 no longer replace register C with register B and we need to disable
3665 such an elimination, if it exists. This occurs often with A == ap,
3666 B == sp, and C == fp. */
3668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3670 struct elim_table *op;
3671 register int new_to = -1;
3673 if (! ep->can_eliminate && ep->can_eliminate_previous)
3675 /* Find the current elimination for ep->from, if there is a
3677 for (op = reg_eliminate;
3678 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3679 if (op->from == ep->from && op->can_eliminate)
3685 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3687 for (op = reg_eliminate;
3688 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3689 if (op->from == new_to && op->to == ep->to)
3690 op->can_eliminate = 0;
3694 /* See if any registers that we thought we could eliminate the previous
3695 time are no longer eliminable. If so, something has changed and we
3696 must spill the register. Also, recompute the number of eliminable
3697 registers and see if the frame pointer is needed; it is if there is
3698 no elimination of the frame pointer that we can perform. */
3700 frame_pointer_needed = 1;
3701 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3703 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3704 && ep->to != HARD_FRAME_POINTER_REGNUM)
3705 frame_pointer_needed = 0;
3707 if (! ep->can_eliminate && ep->can_eliminate_previous)
3709 ep->can_eliminate_previous = 0;
3710 SET_HARD_REG_BIT (*pset, ep->from);
3715 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3716 /* If we didn't need a frame pointer last time, but we do now, spill
3717 the hard frame pointer. */
3718 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3719 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3723 /* Initialize the table of registers to eliminate. */
3727 struct elim_table *ep;
3728 #ifdef ELIMINABLE_REGS
3729 struct elim_table_1 *ep1;
3734 reg_eliminate = (struct elim_table *)
3735 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3736 bzero ((PTR) reg_eliminate,
3737 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3740 /* Does this function require a frame pointer? */
3742 frame_pointer_needed = (! flag_omit_frame_pointer
3743 #ifdef EXIT_IGNORE_STACK
3744 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3745 and restore sp for alloca. So we can't eliminate
3746 the frame pointer in that case. At some point,
3747 we should improve this by emitting the
3748 sp-adjusting insns for this case. */
3749 || (current_function_calls_alloca
3750 && EXIT_IGNORE_STACK)
3752 || FRAME_POINTER_REQUIRED);
3756 #ifdef ELIMINABLE_REGS
3757 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3758 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3760 ep->from = ep1->from;
3762 ep->can_eliminate = ep->can_eliminate_previous
3763 = (CAN_ELIMINATE (ep->from, ep->to)
3764 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3767 reg_eliminate[0].from = reg_eliminate_1[0].from;
3768 reg_eliminate[0].to = reg_eliminate_1[0].to;
3769 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3770 = ! frame_pointer_needed;
3773 /* Count the number of eliminable registers and build the FROM and TO
3774 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3775 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3776 We depend on this. */
3777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3779 num_eliminable += ep->can_eliminate;
3780 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3781 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3785 /* Kick all pseudos out of hard register REGNO.
3786 If DUMPFILE is nonzero, log actions taken on that file.
3788 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3789 because we found we can't eliminate some register. In the case, no pseudos
3790 are allowed to be in the register, even if they are only in a block that
3791 doesn't require spill registers, unlike the case when we are spilling this
3792 hard reg to produce another spill register.
3794 Return nonzero if any pseudos needed to be kicked out. */
3797 spill_hard_reg (regno, dumpfile, cant_eliminate)
3806 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3807 regs_ever_live[regno] = 1;
3810 /* Spill every pseudo reg that was allocated to this reg
3811 or to something that overlaps this reg. */
3813 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3814 if (reg_renumber[i] >= 0
3815 && reg_renumber[i] <= regno
3817 + HARD_REGNO_NREGS (reg_renumber[i],
3818 PSEUDO_REGNO_MODE (i))
3820 SET_REGNO_REG_SET (spilled_pseudos, i);
3823 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3824 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3826 ior_hard_reg_set (set1, set2)
3827 HARD_REG_SET *set1, *set2;
3829 IOR_HARD_REG_SET (*set1, *set2);
3832 /* After find_reload_regs has been run for all insn that need reloads,
3833 and/or spill_hard_regs was called, this function is used to actually
3834 spill pseudo registers and try to reallocate them. It also sets up the
3835 spill_regs array for use by choose_reload_regs. */
3838 finish_spills (global, dumpfile)
3842 struct insn_chain *chain;
3843 int something_changed = 0;
3846 /* Build the spill_regs array for the function. */
3847 /* If there are some registers still to eliminate and one of the spill regs
3848 wasn't ever used before, additional stack space may have to be
3849 allocated to store this register. Thus, we may have changed the offset
3850 between the stack and frame pointers, so mark that something has changed.
3852 One might think that we need only set VAL to 1 if this is a call-used
3853 register. However, the set of registers that must be saved by the
3854 prologue is not identical to the call-used set. For example, the
3855 register used by the call insn for the return PC is a call-used register,
3856 but must be saved by the prologue. */
3859 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3860 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3862 spill_reg_order[i] = n_spills;
3863 spill_regs[n_spills++] = i;
3864 if (num_eliminable && ! regs_ever_live[i])
3865 something_changed = 1;
3866 regs_ever_live[i] = 1;
3869 spill_reg_order[i] = -1;
3871 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3872 if (REGNO_REG_SET_P (spilled_pseudos, i))
3874 /* Record the current hard register the pseudo is allocated to in
3875 pseudo_previous_regs so we avoid reallocating it to the same
3876 hard reg in a later pass. */
3877 if (reg_renumber[i] < 0)
3879 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3880 /* Mark it as no longer having a hard register home. */
3881 reg_renumber[i] = -1;
3882 /* We will need to scan everything again. */
3883 something_changed = 1;
3886 /* Retry global register allocation if possible. */
3889 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3890 /* For every insn that needs reloads, set the registers used as spill
3891 regs in pseudo_forbidden_regs for every pseudo live across the
3893 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3895 EXECUTE_IF_SET_IN_REG_SET
3896 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3898 ior_hard_reg_set (pseudo_forbidden_regs + i,
3899 &chain->used_spill_regs);
3901 EXECUTE_IF_SET_IN_REG_SET
3902 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3904 ior_hard_reg_set (pseudo_forbidden_regs + i,
3905 &chain->used_spill_regs);
3909 /* Retry allocating the spilled pseudos. For each reg, merge the
3910 various reg sets that indicate which hard regs can't be used,
3911 and call retry_global_alloc.
3912 We change spill_pseudos here to only contain pseudos that did not
3913 get a new hard register. */
3914 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3915 if (reg_old_renumber[i] != reg_renumber[i])
3917 HARD_REG_SET forbidden;
3918 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3919 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3920 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3921 retry_global_alloc (i, forbidden);
3922 if (reg_renumber[i] >= 0)
3923 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3927 /* Fix up the register information in the insn chain.
3928 This involves deleting those of the spilled pseudos which did not get
3929 a new hard register home from the live_{before,after} sets. */
3930 for (chain = reload_insn_chain; chain; chain = chain->next)
3932 HARD_REG_SET used_by_pseudos;
3933 HARD_REG_SET used_by_pseudos2;
3935 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3936 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3938 /* Mark any unallocated hard regs as available for spills. That
3939 makes inheritance work somewhat better. */
3940 if (chain->need_reload)
3942 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3943 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3944 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3946 /* Save the old value for the sanity test below. */
3947 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3949 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3950 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3951 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3952 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3954 /* Make sure we only enlarge the set. */
3955 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3961 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3962 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3964 int regno = reg_renumber[i];
3965 if (reg_old_renumber[i] == regno)
3968 alter_reg (i, reg_old_renumber[i]);
3969 reg_old_renumber[i] = regno;
3973 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3975 fprintf (dumpfile, " Register %d now in %d.\n\n",
3976 i, reg_renumber[i]);
3980 return something_changed;
3983 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3984 Also mark any hard registers used to store user variables as
3985 forbidden from being used for spill registers. */
3988 scan_paradoxical_subregs (x)
3993 register enum rtx_code code = GET_CODE (x);
3999 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4000 && REG_USERVAR_P (x))
4001 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4017 if (GET_CODE (SUBREG_REG (x)) == REG
4018 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4019 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4020 = GET_MODE_SIZE (GET_MODE (x));
4027 fmt = GET_RTX_FORMAT (code);
4028 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4031 scan_paradoxical_subregs (XEXP (x, i));
4032 else if (fmt[i] == 'E')
4035 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4036 scan_paradoxical_subregs (XVECEXP (x, i, j));
4042 hard_reg_use_compare (p1p, p2p)
4043 const GENERIC_PTR p1p;
4044 const GENERIC_PTR p2p;
4046 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
4047 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
4048 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4049 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4051 return p1->regno - p2->regno;
4056 if (p1->uses > p2->uses)
4058 if (p1->uses < p2->uses)
4060 /* If regs are equally good, sort by regno,
4061 so that the results of qsort leave nothing to chance. */
4062 return p1->regno - p2->regno;
4065 /* Used for communication between order_regs_for_reload and count_pseudo.
4066 Used to avoid counting one pseudo twice. */
4067 static regset pseudos_counted;
4069 /* Update the costs in N_USES, considering that pseudo REG is live. */
4071 count_pseudo (n_uses, reg)
4072 struct hard_reg_n_uses *n_uses;
4075 int r = reg_renumber[reg];
4078 if (REGNO_REG_SET_P (pseudos_counted, reg))
4080 SET_REGNO_REG_SET (pseudos_counted, reg);
4085 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4087 n_uses[r++].uses += REG_N_REFS (reg);
4089 /* Choose the order to consider regs for use as reload registers
4090 based on how much trouble would be caused by spilling one.
4091 Store them in order of decreasing preference in potential_reload_regs. */
4094 order_regs_for_reload (chain)
4095 struct insn_chain *chain;
4099 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4101 pseudos_counted = ALLOCA_REG_SET ();
4103 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4105 /* Count number of uses of each hard reg by pseudo regs allocated to it
4106 and then order them by decreasing use. */
4108 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4112 hard_reg_n_uses[i].regno = i;
4113 hard_reg_n_uses[i].uses = 0;
4115 /* Test the various reasons why we can't use a register for
4116 spilling in this insn. */
4118 || REGNO_REG_SET_P (chain->live_before, i)
4119 || REGNO_REG_SET_P (chain->live_after, i))
4121 SET_HARD_REG_BIT (bad_spill_regs, i);
4125 /* Now find out which pseudos are allocated to it, and update
4127 CLEAR_REG_SET (pseudos_counted);
4129 EXECUTE_IF_SET_IN_REG_SET
4130 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4132 count_pseudo (hard_reg_n_uses, j);
4134 EXECUTE_IF_SET_IN_REG_SET
4135 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4137 count_pseudo (hard_reg_n_uses, j);
4141 FREE_REG_SET (pseudos_counted);
4143 /* Prefer registers not so far used, for use in temporary loading.
4144 Among them, if REG_ALLOC_ORDER is defined, use that order.
4145 Otherwise, prefer registers not preserved by calls. */
4147 #ifdef REG_ALLOC_ORDER
4148 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4150 int regno = reg_alloc_order[i];
4152 if (hard_reg_n_uses[regno].uses == 0
4153 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4154 potential_reload_regs[o++] = regno;
4157 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4159 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4160 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4161 potential_reload_regs[o++] = i;
4163 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4165 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4166 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4167 potential_reload_regs[o++] = i;
4171 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4172 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4174 /* Now add the regs that are already used,
4175 preferring those used less often. The fixed and otherwise forbidden
4176 registers will be at the end of this list. */
4178 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4179 if (hard_reg_n_uses[i].uses != 0
4180 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4181 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4182 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4183 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4184 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4187 /* Reload pseudo-registers into hard regs around each insn as needed.
4188 Additional register load insns are output before the insn that needs it
4189 and perhaps store insns after insns that modify the reloaded pseudo reg.
4191 reg_last_reload_reg and reg_reloaded_contents keep track of
4192 which registers are already available in reload registers.
4193 We update these for the reloads that we perform,
4194 as the insns are scanned. */
4197 reload_as_needed (live_known)
4200 struct insn_chain *chain;
4201 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4206 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4207 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4208 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4209 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4210 reg_has_output_reload = (char *) alloca (max_regno);
4211 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4213 set_initial_elim_offsets ();
4215 for (chain = reload_insn_chain; chain; chain = chain->next)
4218 rtx insn = chain->insn;
4219 rtx old_next = NEXT_INSN (insn);
4221 /* If we pass a label, copy the offsets from the label information
4222 into the current offsets of each elimination. */
4223 if (GET_CODE (insn) == CODE_LABEL)
4224 set_offsets_for_label (insn);
4226 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4228 rtx oldpat = PATTERN (insn);
4230 /* If this is a USE and CLOBBER of a MEM, ensure that any
4231 references to eliminable registers have been removed. */
4233 if ((GET_CODE (PATTERN (insn)) == USE
4234 || GET_CODE (PATTERN (insn)) == CLOBBER)
4235 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4236 XEXP (XEXP (PATTERN (insn), 0), 0)
4237 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4238 GET_MODE (XEXP (PATTERN (insn), 0)),
4241 /* If we need to do register elimination processing, do so.
4242 This might delete the insn, in which case we are done. */
4243 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4245 eliminate_regs_in_insn (insn, 1);
4246 if (GET_CODE (insn) == NOTE)
4248 update_eliminable_offsets ();
4253 /* If need_elim is nonzero but need_reload is zero, one might think
4254 that we could simply set n_reloads to 0. However, find_reloads
4255 could have done some manipulation of the insn (such as swapping
4256 commutative operands), and these manipulations are lost during
4257 the first pass for every insn that needs register elimination.
4258 So the actions of find_reloads must be redone here. */
4260 if (! chain->need_elim && ! chain->need_reload
4261 && ! chain->need_operand_change)
4263 /* First find the pseudo regs that must be reloaded for this insn.
4264 This info is returned in the tables reload_... (see reload.h).
4265 Also modify the body of INSN by substituting RELOAD
4266 rtx's for those pseudo regs. */
4269 bzero (reg_has_output_reload, max_regno);
4270 CLEAR_HARD_REG_SET (reg_is_output_reload);
4272 find_reloads (insn, 1, spill_indirect_levels, live_known,
4276 if (num_eliminable && chain->need_elim)
4277 update_eliminable_offsets ();
4281 rtx next = NEXT_INSN (insn);
4284 prev = PREV_INSN (insn);
4286 /* Now compute which reload regs to reload them into. Perhaps
4287 reusing reload regs from previous insns, or else output
4288 load insns to reload them. Maybe output store insns too.
4289 Record the choices of reload reg in reload_reg_rtx. */
4290 choose_reload_regs (chain);
4292 /* Merge any reloads that we didn't combine for fear of
4293 increasing the number of spill registers needed but now
4294 discover can be safely merged. */
4295 if (SMALL_REGISTER_CLASSES)
4296 merge_assigned_reloads (insn);
4298 /* Generate the insns to reload operands into or out of
4299 their reload regs. */
4300 emit_reload_insns (chain);
4302 /* Substitute the chosen reload regs from reload_reg_rtx
4303 into the insn's body (or perhaps into the bodies of other
4304 load and store insn that we just made for reloading
4305 and that we moved the structure into). */
4308 /* If this was an ASM, make sure that all the reload insns
4309 we have generated are valid. If not, give an error
4312 if (asm_noperands (PATTERN (insn)) >= 0)
4313 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4314 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4315 && (recog_memoized (p) < 0
4316 || (extract_insn (p), ! constrain_operands (1))))
4318 error_for_asm (insn,
4319 "`asm' operand requires impossible reload");
4321 NOTE_SOURCE_FILE (p) = 0;
4322 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4325 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4326 is no longer validly lying around to save a future reload.
4327 Note that this does not detect pseudos that were reloaded
4328 for this insn in order to be stored in
4329 (obeying register constraints). That is correct; such reload
4330 registers ARE still valid. */
4331 note_stores (oldpat, forget_old_reloads_1);
4333 /* There may have been CLOBBER insns placed after INSN. So scan
4334 between INSN and NEXT and use them to forget old reloads. */
4335 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4336 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4337 note_stores (PATTERN (x), forget_old_reloads_1);
4340 /* Likewise for regs altered by auto-increment in this insn.
4341 REG_INC notes have been changed by reloading:
4342 find_reloads_address_1 records substitutions for them,
4343 which have been performed by subst_reloads above. */
4344 for (i = n_reloads - 1; i >= 0; i--)
4346 rtx in_reg = reload_in_reg[i];
4349 enum rtx_code code = GET_CODE (in_reg);
4350 /* PRE_INC / PRE_DEC will have the reload register ending up
4351 with the same value as the stack slot, but that doesn't
4352 hold true for POST_INC / POST_DEC. Either we have to
4353 convert the memory access to a true POST_INC / POST_DEC,
4354 or we can't use the reload register for inheritance. */
4355 if ((code == POST_INC || code == POST_DEC)
4356 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4357 REGNO (reload_reg_rtx[i]))
4358 /* Make sure it is the inc/dec pseudo, and not
4359 some other (e.g. output operand) pseudo. */
4360 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4361 == REGNO (XEXP (in_reg, 0))))
4364 rtx reload_reg = reload_reg_rtx[i];
4365 enum machine_mode mode = GET_MODE (reload_reg);
4369 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4371 /* We really want to ignore REG_INC notes here, so
4372 use PATTERN (p) as argument to reg_set_p . */
4373 if (reg_set_p (reload_reg, PATTERN (p)))
4375 n = count_occurrences (PATTERN (p), reload_reg);
4380 n = validate_replace_rtx (reload_reg,
4381 gen_rtx (code, mode,
4385 /* We must also verify that the constraints
4386 are met after the replacement. */
4389 n = constrain_operands (1);
4393 /* If the constraints were not met, then
4394 undo the replacement. */
4397 validate_replace_rtx (gen_rtx (code, mode,
4409 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4411 /* Mark this as having an output reload so that the
4412 REG_INC processing code below won't invalidate
4413 the reload for inheritance. */
4414 SET_HARD_REG_BIT (reg_is_output_reload,
4415 REGNO (reload_reg));
4416 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4419 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4421 else if ((code == PRE_INC || code == PRE_DEC)
4422 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4423 REGNO (reload_reg_rtx[i]))
4424 /* Make sure it is the inc/dec pseudo, and not
4425 some other (e.g. output operand) pseudo. */
4426 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4427 == REGNO (XEXP (in_reg, 0))))
4429 SET_HARD_REG_BIT (reg_is_output_reload,
4430 REGNO (reload_reg_rtx[i]));
4431 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4435 /* If a pseudo that got a hard register is auto-incremented,
4436 we must purge records of copying it into pseudos without
4438 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4439 if (REG_NOTE_KIND (x) == REG_INC)
4441 /* See if this pseudo reg was reloaded in this insn.
4442 If so, its last-reload info is still valid
4443 because it is based on this insn's reload. */
4444 for (i = 0; i < n_reloads; i++)
4445 if (reload_out[i] == XEXP (x, 0))
4449 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4453 /* A reload reg's contents are unknown after a label. */
4454 if (GET_CODE (insn) == CODE_LABEL)
4455 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4457 /* Don't assume a reload reg is still good after a call insn
4458 if it is a call-used reg. */
4459 else if (GET_CODE (insn) == CALL_INSN)
4460 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4462 /* In case registers overlap, allow certain insns to invalidate
4463 particular hard registers. */
4465 #ifdef INSN_CLOBBERS_REGNO_P
4466 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4467 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4468 && INSN_CLOBBERS_REGNO_P (insn, i))
4469 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4478 /* Discard all record of any value reloaded from X,
4479 or reloaded in X from someplace else;
4480 unless X is an output reload reg of the current insn.
4482 X may be a hard reg (the reload reg)
4483 or it may be a pseudo reg that was reloaded from. */
4486 forget_old_reloads_1 (x, ignored)
4488 rtx ignored ATTRIBUTE_UNUSED;
4494 /* note_stores does give us subregs of hard regs. */
4495 while (GET_CODE (x) == SUBREG)
4497 offset += SUBREG_WORD (x);
4501 if (GET_CODE (x) != REG)
4504 regno = REGNO (x) + offset;
4506 if (regno >= FIRST_PSEUDO_REGISTER)
4511 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4512 /* Storing into a spilled-reg invalidates its contents.
4513 This can happen if a block-local pseudo is allocated to that reg
4514 and it wasn't spilled because this block's total need is 0.
4515 Then some insn might have an optional reload and use this reg. */
4516 for (i = 0; i < nr; i++)
4517 /* But don't do this if the reg actually serves as an output
4518 reload reg in the current instruction. */
4520 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4521 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4524 /* Since value of X has changed,
4525 forget any value previously copied from it. */
4528 /* But don't forget a copy if this is the output reload
4529 that establishes the copy's validity. */
4530 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4531 reg_last_reload_reg[regno + nr] = 0;
4534 /* For each reload, the mode of the reload register. */
4535 static enum machine_mode reload_mode[MAX_RELOADS];
4537 /* For each reload, the largest number of registers it will require. */
4538 static int reload_nregs[MAX_RELOADS];
4540 /* Comparison function for qsort to decide which of two reloads
4541 should be handled first. *P1 and *P2 are the reload numbers. */
4544 reload_reg_class_lower (r1p, r2p)
4545 const GENERIC_PTR r1p;
4546 const GENERIC_PTR r2p;
4548 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4551 /* Consider required reloads before optional ones. */
4552 t = reload_optional[r1] - reload_optional[r2];
4556 /* Count all solitary classes before non-solitary ones. */
4557 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4558 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4562 /* Aside from solitaires, consider all multi-reg groups first. */
4563 t = reload_nregs[r2] - reload_nregs[r1];
4567 /* Consider reloads in order of increasing reg-class number. */
4568 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4572 /* If reloads are equally urgent, sort by reload number,
4573 so that the results of qsort leave nothing to chance. */
4577 /* The following HARD_REG_SETs indicate when each hard register is
4578 used for a reload of various parts of the current insn. */
4580 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4581 static HARD_REG_SET reload_reg_used;
4582 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4583 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4584 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4585 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4586 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4587 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4588 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4589 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4590 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4591 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4592 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4593 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4594 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4595 static HARD_REG_SET reload_reg_used_in_op_addr;
4596 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4597 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4598 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4599 static HARD_REG_SET reload_reg_used_in_insn;
4600 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4601 static HARD_REG_SET reload_reg_used_in_other_addr;
4603 /* If reg is in use as a reload reg for any sort of reload. */
4604 static HARD_REG_SET reload_reg_used_at_all;
4606 /* If reg is use as an inherited reload. We just mark the first register
4608 static HARD_REG_SET reload_reg_used_for_inherit;
4610 /* Records which hard regs are used in any way, either as explicit use or
4611 by being allocated to a pseudo during any point of the current insn. */
4612 static HARD_REG_SET reg_used_in_insn;
4614 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4615 TYPE. MODE is used to indicate how many consecutive regs are
4619 mark_reload_reg_in_use (regno, opnum, type, mode)
4622 enum reload_type type;
4623 enum machine_mode mode;
4625 int nregs = HARD_REGNO_NREGS (regno, mode);
4628 for (i = regno; i < nregs + regno; i++)
4633 SET_HARD_REG_BIT (reload_reg_used, i);
4636 case RELOAD_FOR_INPUT_ADDRESS:
4637 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4640 case RELOAD_FOR_INPADDR_ADDRESS:
4641 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4644 case RELOAD_FOR_OUTPUT_ADDRESS:
4645 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4648 case RELOAD_FOR_OUTADDR_ADDRESS:
4649 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4652 case RELOAD_FOR_OPERAND_ADDRESS:
4653 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4656 case RELOAD_FOR_OPADDR_ADDR:
4657 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4660 case RELOAD_FOR_OTHER_ADDRESS:
4661 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4664 case RELOAD_FOR_INPUT:
4665 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4668 case RELOAD_FOR_OUTPUT:
4669 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4672 case RELOAD_FOR_INSN:
4673 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4677 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4681 /* Similarly, but show REGNO is no longer in use for a reload. */
4684 clear_reload_reg_in_use (regno, opnum, type, mode)
4687 enum reload_type type;
4688 enum machine_mode mode;
4690 int nregs = HARD_REGNO_NREGS (regno, mode);
4691 int start_regno, end_regno;
4693 /* A complication is that for some reload types, inheritance might
4694 allow multiple reloads of the same types to share a reload register.
4695 We set check_opnum if we have to check only reloads with the same
4696 operand number, and check_any if we have to check all reloads. */
4697 int check_opnum = 0;
4699 HARD_REG_SET *used_in_set;
4704 used_in_set = &reload_reg_used;
4707 case RELOAD_FOR_INPUT_ADDRESS:
4708 used_in_set = &reload_reg_used_in_input_addr[opnum];
4711 case RELOAD_FOR_INPADDR_ADDRESS:
4713 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4716 case RELOAD_FOR_OUTPUT_ADDRESS:
4717 used_in_set = &reload_reg_used_in_output_addr[opnum];
4720 case RELOAD_FOR_OUTADDR_ADDRESS:
4722 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4725 case RELOAD_FOR_OPERAND_ADDRESS:
4726 used_in_set = &reload_reg_used_in_op_addr;
4729 case RELOAD_FOR_OPADDR_ADDR:
4731 used_in_set = &reload_reg_used_in_op_addr_reload;
4734 case RELOAD_FOR_OTHER_ADDRESS:
4735 used_in_set = &reload_reg_used_in_other_addr;
4739 case RELOAD_FOR_INPUT:
4740 used_in_set = &reload_reg_used_in_input[opnum];
4743 case RELOAD_FOR_OUTPUT:
4744 used_in_set = &reload_reg_used_in_output[opnum];
4747 case RELOAD_FOR_INSN:
4748 used_in_set = &reload_reg_used_in_insn;
4753 /* We resolve conflicts with remaining reloads of the same type by
4754 excluding the intervals of of reload registers by them from the
4755 interval of freed reload registers. Since we only keep track of
4756 one set of interval bounds, we might have to exclude somewhat
4757 more then what would be necessary if we used a HARD_REG_SET here.
4758 But this should only happen very infrequently, so there should
4759 be no reason to worry about it. */
4761 start_regno = regno;
4762 end_regno = regno + nregs;
4763 if (check_opnum || check_any)
4765 for (i = n_reloads - 1; i >= 0; i--)
4767 if (reload_when_needed[i] == type
4768 && (check_any || reload_opnum[i] == opnum)
4769 && reload_reg_rtx[i])
4771 int conflict_start = true_regnum (reload_reg_rtx[i]);
4774 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4776 /* If there is an overlap with the first to-be-freed register,
4777 adjust the interval start. */
4778 if (conflict_start <= start_regno && conflict_end > start_regno)
4779 start_regno = conflict_end;
4780 /* Otherwise, if there is a conflict with one of the other
4781 to-be-freed registers, adjust the interval end. */
4782 if (conflict_start > start_regno && conflict_start < end_regno)
4783 end_regno = conflict_start;
4787 for (i = start_regno; i < end_regno; i++)
4788 CLEAR_HARD_REG_BIT (*used_in_set, i);
4791 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4792 specified by OPNUM and TYPE. */
4795 reload_reg_free_p (regno, opnum, type)
4798 enum reload_type type;
4802 /* In use for a RELOAD_OTHER means it's not available for anything. */
4803 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4809 /* In use for anything means we can't use it for RELOAD_OTHER. */
4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4815 for (i = 0; i < reload_n_operands; i++)
4816 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4817 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4820 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4826 case RELOAD_FOR_INPUT:
4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4828 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4834 /* If it is used for some other input, can't use it. */
4835 for (i = 0; i < reload_n_operands; i++)
4836 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4839 /* If it is used in a later operand's address, can't use it. */
4840 for (i = opnum + 1; i < reload_n_operands; i++)
4841 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4842 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4847 case RELOAD_FOR_INPUT_ADDRESS:
4848 /* Can't use a register if it is used for an input address for this
4849 operand or used as an input in an earlier one. */
4850 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4851 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4854 for (i = 0; i < opnum; i++)
4855 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4860 case RELOAD_FOR_INPADDR_ADDRESS:
4861 /* Can't use a register if it is used for an input address
4862 for this operand or used as an input in an earlier
4864 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4867 for (i = 0; i < opnum; i++)
4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4873 case RELOAD_FOR_OUTPUT_ADDRESS:
4874 /* Can't use a register if it is used for an output address for this
4875 operand or used as an output in this or a later operand. */
4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4879 for (i = opnum; i < reload_n_operands; i++)
4880 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4885 case RELOAD_FOR_OUTADDR_ADDRESS:
4886 /* Can't use a register if it is used for an output address
4887 for this operand or used as an output in this or a
4889 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4892 for (i = opnum; i < reload_n_operands; i++)
4893 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4898 case RELOAD_FOR_OPERAND_ADDRESS:
4899 for (i = 0; i < reload_n_operands; i++)
4900 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4903 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4904 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4906 case RELOAD_FOR_OPADDR_ADDR:
4907 for (i = 0; i < reload_n_operands; i++)
4908 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4911 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4913 case RELOAD_FOR_OUTPUT:
4914 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4915 outputs, or an operand address for this or an earlier output. */
4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4919 for (i = 0; i < reload_n_operands; i++)
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4923 for (i = 0; i <= opnum; i++)
4924 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4925 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4930 case RELOAD_FOR_INSN:
4931 for (i = 0; i < reload_n_operands; i++)
4932 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4933 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4936 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4937 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4939 case RELOAD_FOR_OTHER_ADDRESS:
4940 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4945 /* Return 1 if the value in reload reg REGNO, as used by a reload
4946 needed for the part of the insn specified by OPNUM and TYPE,
4947 is still available in REGNO at the end of the insn.
4949 We can assume that the reload reg was already tested for availability
4950 at the time it is needed, and we should not check this again,
4951 in case the reg has already been marked in use. */
4954 reload_reg_reaches_end_p (regno, opnum, type)
4957 enum reload_type type;
4964 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4965 its value must reach the end. */
4968 /* If this use is for part of the insn,
4969 its value reaches if no subsequent part uses the same register.
4970 Just like the above function, don't try to do this with lots
4973 case RELOAD_FOR_OTHER_ADDRESS:
4974 /* Here we check for everything else, since these don't conflict
4975 with anything else and everything comes later. */
4977 for (i = 0; i < reload_n_operands; i++)
4978 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4979 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4980 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4981 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4982 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4983 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4986 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4987 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4988 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4990 case RELOAD_FOR_INPUT_ADDRESS:
4991 case RELOAD_FOR_INPADDR_ADDRESS:
4992 /* Similar, except that we check only for this and subsequent inputs
4993 and the address of only subsequent inputs and we do not need
4994 to check for RELOAD_OTHER objects since they are known not to
4997 for (i = opnum; i < reload_n_operands; i++)
4998 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5001 for (i = opnum + 1; i < reload_n_operands; i++)
5002 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5003 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5006 for (i = 0; i < reload_n_operands; i++)
5007 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5008 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5009 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5015 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5016 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5018 case RELOAD_FOR_INPUT:
5019 /* Similar to input address, except we start at the next operand for
5020 both input and input address and we do not check for
5021 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5024 for (i = opnum + 1; i < reload_n_operands; i++)
5025 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5026 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5030 /* ... fall through ... */
5032 case RELOAD_FOR_OPERAND_ADDRESS:
5033 /* Check outputs and their addresses. */
5035 for (i = 0; i < reload_n_operands; i++)
5036 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5043 case RELOAD_FOR_OPADDR_ADDR:
5044 for (i = 0; i < reload_n_operands; i++)
5045 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5046 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5047 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5050 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5051 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5053 case RELOAD_FOR_INSN:
5054 /* These conflict with other outputs with RELOAD_OTHER. So
5055 we need only check for output addresses. */
5059 /* ... fall through ... */
5061 case RELOAD_FOR_OUTPUT:
5062 case RELOAD_FOR_OUTPUT_ADDRESS:
5063 case RELOAD_FOR_OUTADDR_ADDRESS:
5064 /* We already know these can't conflict with a later output. So the
5065 only thing to check are later output addresses. */
5066 for (i = opnum + 1; i < reload_n_operands; i++)
5067 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5068 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5077 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5080 This function uses the same algorithm as reload_reg_free_p above. */
5083 reloads_conflict (r1, r2)
5086 enum reload_type r1_type = reload_when_needed[r1];
5087 enum reload_type r2_type = reload_when_needed[r2];
5088 int r1_opnum = reload_opnum[r1];
5089 int r2_opnum = reload_opnum[r2];
5091 /* RELOAD_OTHER conflicts with everything. */
5092 if (r2_type == RELOAD_OTHER)
5095 /* Otherwise, check conflicts differently for each type. */
5099 case RELOAD_FOR_INPUT:
5100 return (r2_type == RELOAD_FOR_INSN
5101 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5102 || r2_type == RELOAD_FOR_OPADDR_ADDR
5103 || r2_type == RELOAD_FOR_INPUT
5104 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5105 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5106 && r2_opnum > r1_opnum));
5108 case RELOAD_FOR_INPUT_ADDRESS:
5109 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5110 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5112 case RELOAD_FOR_INPADDR_ADDRESS:
5113 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5114 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5116 case RELOAD_FOR_OUTPUT_ADDRESS:
5117 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5118 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5120 case RELOAD_FOR_OUTADDR_ADDRESS:
5121 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5122 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5124 case RELOAD_FOR_OPERAND_ADDRESS:
5125 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5126 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5128 case RELOAD_FOR_OPADDR_ADDR:
5129 return (r2_type == RELOAD_FOR_INPUT
5130 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5132 case RELOAD_FOR_OUTPUT:
5133 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5134 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5135 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5136 && r2_opnum >= r1_opnum));
5138 case RELOAD_FOR_INSN:
5139 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5140 || r2_type == RELOAD_FOR_INSN
5141 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5143 case RELOAD_FOR_OTHER_ADDRESS:
5144 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5154 /* Vector of reload-numbers showing the order in which the reloads should
5156 short reload_order[MAX_RELOADS];
5158 /* Indexed by reload number, 1 if incoming value
5159 inherited from previous insns. */
5160 char reload_inherited[MAX_RELOADS];
5162 /* For an inherited reload, this is the insn the reload was inherited from,
5163 if we know it. Otherwise, this is 0. */
5164 rtx reload_inheritance_insn[MAX_RELOADS];
5166 /* If non-zero, this is a place to get the value of the reload,
5167 rather than using reload_in. */
5168 rtx reload_override_in[MAX_RELOADS];
5170 /* For each reload, the hard register number of the register used,
5171 or -1 if we did not need a register for this reload. */
5172 int reload_spill_index[MAX_RELOADS];
5174 /* Return 1 if the value in reload reg REGNO, as used by a reload
5175 needed for the part of the insn specified by OPNUM and TYPE,
5176 may be used to load VALUE into it.
5178 Other read-only reloads with the same value do not conflict
5179 unless OUT is non-zero and these other reloads have to live while
5180 output reloads live.
5181 If OUT is CONST0_RTX, this is a special case: it means that the
5182 test should not be for using register REGNO as reload register, but
5183 for copying from register REGNO into the reload register.
5185 RELOADNUM is the number of the reload we want to load this value for;
5186 a reload does not conflict with itself.
5188 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5189 reloads that load an address for the very reload we are considering.
5191 The caller has to make sure that there is no conflict with the return
5194 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5195 ignore_address_reloads)
5198 enum reload_type type;
5201 int ignore_address_reloads;
5207 if (out == const0_rtx)
5213 /* We use some pseudo 'time' value to check if the lifetimes of the
5214 new register use would overlap with the one of a previous reload
5215 that is not read-only or uses a different value.
5216 The 'time' used doesn't have to be linear in any shape or form, just
5218 Some reload types use different 'buckets' for each operand.
5219 So there are MAX_RECOG_OPERANDS different time values for each
5221 We compute TIME1 as the time when the register for the prospective
5222 new reload ceases to be live, and TIME2 for each existing
5223 reload as the time when that the reload register of that reload
5225 Where there is little to be gained by exact lifetime calculations,
5226 we just make conservative assumptions, i.e. a longer lifetime;
5227 this is done in the 'default:' cases. */
5230 case RELOAD_FOR_OTHER_ADDRESS:
5234 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5236 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5237 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5238 respectively, to the time values for these, we get distinct time
5239 values. To get distinct time values for each operand, we have to
5240 multiply opnum by at least three. We round that up to four because
5241 multiply by four is often cheaper. */
5242 case RELOAD_FOR_INPADDR_ADDRESS:
5243 time1 = opnum * 4 + 2;
5245 case RELOAD_FOR_INPUT_ADDRESS:
5246 time1 = opnum * 4 + 3;
5248 case RELOAD_FOR_INPUT:
5249 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5250 executes (inclusive). */
5251 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5253 case RELOAD_FOR_OPADDR_ADDR:
5255 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5256 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5258 case RELOAD_FOR_OPERAND_ADDRESS:
5259 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5261 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5263 case RELOAD_FOR_OUTADDR_ADDRESS:
5264 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5266 case RELOAD_FOR_OUTPUT_ADDRESS:
5267 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5270 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5273 for (i = 0; i < n_reloads; i++)
5275 rtx reg = reload_reg_rtx[i];
5276 if (reg && GET_CODE (reg) == REG
5277 && ((unsigned) regno - true_regnum (reg)
5278 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5281 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5282 || reload_out[i] || out)
5285 switch (reload_when_needed[i])
5287 case RELOAD_FOR_OTHER_ADDRESS:
5290 case RELOAD_FOR_INPADDR_ADDRESS:
5291 /* find_reloads makes sure that a
5292 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5293 by at most one - the first -
5294 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5295 address reload is inherited, the address address reload
5296 goes away, so we can ignore this conflict. */
5297 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5298 && ignore_address_reloads
5299 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5300 Then the address address is still needed to store
5301 back the new address. */
5302 && ! reload_out[reloadnum])
5304 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5305 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5307 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5308 && ignore_address_reloads
5309 /* Unless we are reloading an auto_inc expression. */
5310 && ! reload_out[reloadnum])
5312 time2 = reload_opnum[i] * 4 + 2;
5314 case RELOAD_FOR_INPUT_ADDRESS:
5315 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5316 && ignore_address_reloads
5317 && ! reload_out[reloadnum])
5319 time2 = reload_opnum[i] * 4 + 3;
5321 case RELOAD_FOR_INPUT:
5322 time2 = reload_opnum[i] * 4 + 4;
5324 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5325 == MAX_RECOG_OPERAND * 4 */
5326 case RELOAD_FOR_OPADDR_ADDR:
5327 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5328 && ignore_address_reloads
5329 && ! reload_out[reloadnum])
5331 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5333 case RELOAD_FOR_OPERAND_ADDRESS:
5334 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5336 case RELOAD_FOR_INSN:
5337 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5339 case RELOAD_FOR_OUTPUT:
5340 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5341 instruction is executed. */
5342 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5344 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5345 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5347 case RELOAD_FOR_OUTADDR_ADDRESS:
5348 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5349 && ignore_address_reloads
5350 && ! reload_out[reloadnum])
5352 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5354 case RELOAD_FOR_OUTPUT_ADDRESS:
5355 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5358 /* If there is no conflict in the input part, handle this
5359 like an output reload. */
5360 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5362 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5366 /* RELOAD_OTHER might be live beyond instruction execution,
5367 but this is not obvious when we set time2 = 1. So check
5368 here if there might be a problem with the new reload
5369 clobbering the register used by the RELOAD_OTHER. */
5377 && (! reload_in[i] || reload_out[i]
5378 || ! rtx_equal_p (reload_in[i], value)))
5379 || (out && reload_out_reg[reloadnum]
5380 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5388 /* Find a spill register to use as a reload register for reload R.
5389 LAST_RELOAD is non-zero if this is the last reload for the insn being
5392 Set reload_reg_rtx[R] to the register allocated.
5394 If NOERROR is nonzero, we return 1 if successful,
5395 or 0 if we couldn't find a spill reg and we didn't change anything. */
5398 allocate_reload_reg (chain, r, last_reload, noerror)
5399 struct insn_chain *chain;
5404 rtx insn = chain->insn;
5405 int i, pass, count, regno;
5408 /* If we put this reload ahead, thinking it is a group,
5409 then insist on finding a group. Otherwise we can grab a
5410 reg that some other reload needs.
5411 (That can happen when we have a 68000 DATA_OR_FP_REG
5412 which is a group of data regs or one fp reg.)
5413 We need not be so restrictive if there are no more reloads
5416 ??? Really it would be nicer to have smarter handling
5417 for that kind of reg class, where a problem like this is normal.
5418 Perhaps those classes should be avoided for reloading
5419 by use of more alternatives. */
5421 int force_group = reload_nregs[r] > 1 && ! last_reload;
5423 /* If we want a single register and haven't yet found one,
5424 take any reg in the right class and not in use.
5425 If we want a consecutive group, here is where we look for it.
5427 We use two passes so we can first look for reload regs to
5428 reuse, which are already in use for other reloads in this insn,
5429 and only then use additional registers.
5430 I think that maximizing reuse is needed to make sure we don't
5431 run out of reload regs. Suppose we have three reloads, and
5432 reloads A and B can share regs. These need two regs.
5433 Suppose A and B are given different regs.
5434 That leaves none for C. */
5435 for (pass = 0; pass < 2; pass++)
5437 /* I is the index in spill_regs.
5438 We advance it round-robin between insns to use all spill regs
5439 equally, so that inherited reloads have a chance
5440 of leapfrogging each other. Don't do this, however, when we have
5441 group needs and failure would be fatal; if we only have a relatively
5442 small number of spill registers, and more than one of them has
5443 group needs, then by starting in the middle, we may end up
5444 allocating the first one in such a way that we are not left with
5445 sufficient groups to handle the rest. */
5447 if (noerror || ! force_group)
5452 for (count = 0; count < n_spills; count++)
5454 int class = (int) reload_reg_class[r];
5460 regnum = spill_regs[i];
5462 if ((reload_reg_free_p (regnum, reload_opnum[r],
5463 reload_when_needed[r])
5465 /* We check reload_reg_used to make sure we
5466 don't clobber the return register. */
5467 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5468 && reload_reg_free_for_value_p (regnum,
5470 reload_when_needed[r],
5472 reload_out[r], r, 1)))
5473 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5474 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5475 /* Look first for regs to share, then for unshared. But
5476 don't share regs used for inherited reloads; they are
5477 the ones we want to preserve. */
5479 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5481 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5484 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5485 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5486 (on 68000) got us two FP regs. If NR is 1,
5487 we would reject both of them. */
5489 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5490 /* If we need only one reg, we have already won. */
5493 /* But reject a single reg if we demand a group. */
5498 /* Otherwise check that as many consecutive regs as we need
5500 Also, don't use for a group registers that are
5501 needed for nongroups. */
5502 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5505 regno = regnum + nr - 1;
5506 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5507 && spill_reg_order[regno] >= 0
5508 && reload_reg_free_p (regno, reload_opnum[r],
5509 reload_when_needed[r])
5510 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5520 /* If we found something on pass 1, omit pass 2. */
5521 if (count < n_spills)
5525 /* We should have found a spill register by now. */
5526 if (count == n_spills)
5533 /* I is the index in SPILL_REG_RTX of the reload register we are to
5534 allocate. Get an rtx for it and find its register number. */
5536 new = spill_reg_rtx[i];
5538 if (new == 0 || GET_MODE (new) != reload_mode[r])
5539 spill_reg_rtx[i] = new
5540 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5542 regno = true_regnum (new);
5544 /* Detect when the reload reg can't hold the reload mode.
5545 This used to be one `if', but Sequent compiler can't handle that. */
5546 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5548 enum machine_mode test_mode = VOIDmode;
5550 test_mode = GET_MODE (reload_in[r]);
5551 /* If reload_in[r] has VOIDmode, it means we will load it
5552 in whatever mode the reload reg has: to wit, reload_mode[r].
5553 We have already tested that for validity. */
5554 /* Aside from that, we need to test that the expressions
5555 to reload from or into have modes which are valid for this
5556 reload register. Otherwise the reload insns would be invalid. */
5557 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5558 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5559 if (! (reload_out[r] != 0
5560 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5562 /* The reg is OK. */
5565 /* Mark as in use for this insn the reload regs we use
5567 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5568 reload_when_needed[r], reload_mode[r]);
5570 reload_reg_rtx[r] = new;
5571 reload_spill_index[r] = spill_regs[i];
5576 /* The reg is not OK. */
5581 if (asm_noperands (PATTERN (insn)) < 0)
5582 /* It's the compiler's fault. */
5583 fatal_insn ("Could not find a spill register", insn);
5585 /* It's the user's fault; the operand's mode and constraint
5586 don't match. Disable this reload so we don't crash in final. */
5587 error_for_asm (insn,
5588 "`asm' operand constraint incompatible with operand size");
5591 reload_reg_rtx[r] = 0;
5592 reload_optional[r] = 1;
5593 reload_secondary_p[r] = 1;
5598 /* Assign hard reg targets for the pseudo-registers we must reload
5599 into hard regs for this insn.
5600 Also output the instructions to copy them in and out of the hard regs.
5602 For machines with register classes, we are responsible for
5603 finding a reload reg in the proper class. */
5606 choose_reload_regs (chain)
5607 struct insn_chain *chain;
5609 rtx insn = chain->insn;
5611 int max_group_size = 1;
5612 enum reg_class group_class = NO_REGS;
5616 rtx save_reload_reg_rtx[MAX_RELOADS];
5617 char save_reload_inherited[MAX_RELOADS];
5618 rtx save_reload_inheritance_insn[MAX_RELOADS];
5619 rtx save_reload_override_in[MAX_RELOADS];
5620 int save_reload_spill_index[MAX_RELOADS];
5621 HARD_REG_SET save_reload_reg_used;
5622 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5623 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5624 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5625 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5626 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5627 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5628 HARD_REG_SET save_reload_reg_used_in_op_addr;
5629 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5630 HARD_REG_SET save_reload_reg_used_in_insn;
5631 HARD_REG_SET save_reload_reg_used_in_other_addr;
5632 HARD_REG_SET save_reload_reg_used_at_all;
5634 bzero (reload_inherited, MAX_RELOADS);
5635 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5636 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5638 CLEAR_HARD_REG_SET (reload_reg_used);
5639 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5640 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5641 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5642 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5643 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5645 CLEAR_HARD_REG_SET (reg_used_in_insn);
5648 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5649 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5650 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5651 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5652 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5653 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5655 for (i = 0; i < reload_n_operands; i++)
5657 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5658 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5659 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5660 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5661 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5662 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5665 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5667 #if 0 /* Not needed, now that we can always retry without inheritance. */
5668 /* See if we have more mandatory reloads than spill regs.
5669 If so, then we cannot risk optimizations that could prevent
5670 reloads from sharing one spill register.
5672 Since we will try finding a better register than reload_reg_rtx
5673 unless it is equal to reload_in or reload_out, count such reloads. */
5677 for (j = 0; j < n_reloads; j++)
5678 if (! reload_optional[j]
5679 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5680 && (reload_reg_rtx[j] == 0
5681 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5682 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5689 /* In order to be certain of getting the registers we need,
5690 we must sort the reloads into order of increasing register class.
5691 Then our grabbing of reload registers will parallel the process
5692 that provided the reload registers.
5694 Also note whether any of the reloads wants a consecutive group of regs.
5695 If so, record the maximum size of the group desired and what
5696 register class contains all the groups needed by this insn. */
5698 for (j = 0; j < n_reloads; j++)
5700 reload_order[j] = j;
5701 reload_spill_index[j] = -1;
5704 = (reload_inmode[j] == VOIDmode
5705 || (GET_MODE_SIZE (reload_outmode[j])
5706 > GET_MODE_SIZE (reload_inmode[j])))
5707 ? reload_outmode[j] : reload_inmode[j];
5709 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5711 if (reload_nregs[j] > 1)
5713 max_group_size = MAX (reload_nregs[j], max_group_size);
5714 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5717 /* If we have already decided to use a certain register,
5718 don't use it in another way. */
5719 if (reload_reg_rtx[j])
5720 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5721 reload_when_needed[j], reload_mode[j]);
5725 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5727 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5728 sizeof reload_reg_rtx);
5729 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5730 bcopy ((char *) reload_inheritance_insn,
5731 (char *) save_reload_inheritance_insn,
5732 sizeof reload_inheritance_insn);
5733 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5734 sizeof reload_override_in);
5735 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5736 sizeof reload_spill_index);
5737 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5738 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5739 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5740 reload_reg_used_in_op_addr);
5742 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5743 reload_reg_used_in_op_addr_reload);
5745 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5746 reload_reg_used_in_insn);
5747 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5748 reload_reg_used_in_other_addr);
5750 for (i = 0; i < reload_n_operands; i++)
5752 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5753 reload_reg_used_in_output[i]);
5754 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5755 reload_reg_used_in_input[i]);
5756 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5757 reload_reg_used_in_input_addr[i]);
5758 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5759 reload_reg_used_in_inpaddr_addr[i]);
5760 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5761 reload_reg_used_in_output_addr[i]);
5762 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5763 reload_reg_used_in_outaddr_addr[i]);
5766 /* If -O, try first with inheritance, then turning it off.
5767 If not -O, don't do inheritance.
5768 Using inheritance when not optimizing leads to paradoxes
5769 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5770 because one side of the comparison might be inherited. */
5772 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5774 /* Process the reloads in order of preference just found.
5775 Beyond this point, subregs can be found in reload_reg_rtx.
5777 This used to look for an existing reloaded home for all
5778 of the reloads, and only then perform any new reloads.
5779 But that could lose if the reloads were done out of reg-class order
5780 because a later reload with a looser constraint might have an old
5781 home in a register needed by an earlier reload with a tighter constraint.
5783 To solve this, we make two passes over the reloads, in the order
5784 described above. In the first pass we try to inherit a reload
5785 from a previous insn. If there is a later reload that needs a
5786 class that is a proper subset of the class being processed, we must
5787 also allocate a spill register during the first pass.
5789 Then make a second pass over the reloads to allocate any reloads
5790 that haven't been given registers yet. */
5792 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5794 for (j = 0; j < n_reloads; j++)
5796 register int r = reload_order[j];
5797 rtx search_equiv = NULL_RTX;
5799 /* Ignore reloads that got marked inoperative. */
5800 if (reload_out[r] == 0 && reload_in[r] == 0
5801 && ! reload_secondary_p[r])
5804 /* If find_reloads chose to use reload_in or reload_out as a reload
5805 register, we don't need to chose one. Otherwise, try even if it
5806 found one since we might save an insn if we find the value lying
5808 Try also when reload_in is a pseudo without a hard reg. */
5809 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5810 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5811 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5812 && GET_CODE (reload_in[r]) != MEM
5813 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5816 #if 0 /* No longer needed for correct operation.
5817 It might give better code, or might not; worth an experiment? */
5818 /* If this is an optional reload, we can't inherit from earlier insns
5819 until we are sure that any non-optional reloads have been allocated.
5820 The following code takes advantage of the fact that optional reloads
5821 are at the end of reload_order. */
5822 if (reload_optional[r] != 0)
5823 for (i = 0; i < j; i++)
5824 if ((reload_out[reload_order[i]] != 0
5825 || reload_in[reload_order[i]] != 0
5826 || reload_secondary_p[reload_order[i]])
5827 && ! reload_optional[reload_order[i]]
5828 && reload_reg_rtx[reload_order[i]] == 0)
5829 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5832 /* First see if this pseudo is already available as reloaded
5833 for a previous insn. We cannot try to inherit for reloads
5834 that are smaller than the maximum number of registers needed
5835 for groups unless the register we would allocate cannot be used
5838 We could check here to see if this is a secondary reload for
5839 an object that is already in a register of the desired class.
5840 This would avoid the need for the secondary reload register.
5841 But this is complex because we can't easily determine what
5842 objects might want to be loaded via this reload. So let a
5843 register be allocated here. In `emit_reload_insns' we suppress
5844 one of the loads in the case described above. */
5849 register int regno = -1;
5850 enum machine_mode mode;
5852 if (reload_in[r] == 0)
5854 else if (GET_CODE (reload_in[r]) == REG)
5856 regno = REGNO (reload_in[r]);
5857 mode = GET_MODE (reload_in[r]);
5859 else if (GET_CODE (reload_in_reg[r]) == REG)
5861 regno = REGNO (reload_in_reg[r]);
5862 mode = GET_MODE (reload_in_reg[r]);
5864 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5865 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5867 word = SUBREG_WORD (reload_in_reg[r]);
5868 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5869 if (regno < FIRST_PSEUDO_REGISTER)
5871 mode = GET_MODE (reload_in_reg[r]);
5874 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5875 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5876 || GET_CODE (reload_in_reg[r]) == POST_INC
5877 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5878 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5880 regno = REGNO (XEXP (reload_in_reg[r], 0));
5881 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5882 reload_out[r] = reload_in[r];
5886 /* This won't work, since REGNO can be a pseudo reg number.
5887 Also, it takes much more hair to keep track of all the things
5888 that can invalidate an inherited reload of part of a pseudoreg. */
5889 else if (GET_CODE (reload_in[r]) == SUBREG
5890 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5891 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5894 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5896 enum reg_class class = reload_reg_class[r], last_class;
5897 rtx last_reg = reg_last_reload_reg[regno];
5899 i = REGNO (last_reg) + word;
5900 last_class = REGNO_REG_CLASS (i);
5901 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5902 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5903 && reg_reloaded_contents[i] == regno
5904 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5905 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5906 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5907 /* Even if we can't use this register as a reload
5908 register, we might use it for reload_override_in,
5909 if copying it to the desired class is cheap
5911 || ((REGISTER_MOVE_COST (last_class, class)
5912 < MEMORY_MOVE_COST (mode, class, 1))
5913 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5914 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5918 #ifdef SECONDARY_MEMORY_NEEDED
5919 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5924 && (reload_nregs[r] == max_group_size
5925 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5927 && reload_reg_free_for_value_p (i, reload_opnum[r],
5928 reload_when_needed[r],
5932 /* If a group is needed, verify that all the subsequent
5933 registers still have their values intact. */
5935 = HARD_REGNO_NREGS (i, reload_mode[r]);
5938 for (k = 1; k < nr; k++)
5939 if (reg_reloaded_contents[i + k] != regno
5940 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5947 last_reg = (GET_MODE (last_reg) == mode
5948 ? last_reg : gen_rtx_REG (mode, i));
5950 /* We found a register that contains the
5951 value we need. If this register is the
5952 same as an `earlyclobber' operand of the
5953 current insn, just mark it as a place to
5954 reload from since we can't use it as the
5955 reload register itself. */
5957 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5958 if (reg_overlap_mentioned_for_reload_p
5959 (reg_last_reload_reg[regno],
5960 reload_earlyclobbers[i1]))
5963 if (i1 != n_earlyclobbers
5964 || ! (reload_reg_free_for_value_p
5965 (i, reload_opnum[r], reload_when_needed[r],
5966 reload_in[r], reload_out[r], r, 1))
5967 /* Don't use it if we'd clobber a pseudo reg. */
5968 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5970 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5971 /* Don't clobber the frame pointer. */
5972 || (i == HARD_FRAME_POINTER_REGNUM
5974 /* Don't really use the inherited spill reg
5975 if we need it wider than we've got it. */
5976 || (GET_MODE_SIZE (reload_mode[r])
5977 > GET_MODE_SIZE (mode))
5978 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5981 /* If find_reloads chose reload_out as reload
5982 register, stay with it - that leaves the
5983 inherited register for subsequent reloads. */
5984 || (reload_out[r] && reload_reg_rtx[r]
5985 && rtx_equal_p (reload_out[r],
5986 reload_reg_rtx[r])))
5988 reload_override_in[r] = last_reg;
5989 reload_inheritance_insn[r]
5990 = reg_reloaded_insn[i];
5995 /* We can use this as a reload reg. */
5996 /* Mark the register as in use for this part of
5998 mark_reload_reg_in_use (i,
6000 reload_when_needed[r],
6002 reload_reg_rtx[r] = last_reg;
6003 reload_inherited[r] = 1;
6004 reload_inheritance_insn[r]
6005 = reg_reloaded_insn[i];
6006 reload_spill_index[r] = i;
6007 for (k = 0; k < nr; k++)
6008 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6016 /* Here's another way to see if the value is already lying around. */
6018 && reload_in[r] != 0
6019 && ! reload_inherited[r]
6020 && reload_out[r] == 0
6021 && (CONSTANT_P (reload_in[r])
6022 || GET_CODE (reload_in[r]) == PLUS
6023 || GET_CODE (reload_in[r]) == REG
6024 || GET_CODE (reload_in[r]) == MEM)
6025 && (reload_nregs[r] == max_group_size
6026 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
6027 search_equiv = reload_in[r];
6028 /* If this is an output reload from a simple move insn, look
6029 if an equivalence for the input is available. */
6030 else if (inheritance && reload_in[r] == 0 && reload_out[r] != 0)
6032 rtx set = single_set (insn);
6035 && rtx_equal_p (reload_out[r], SET_DEST (set))
6036 && CONSTANT_P (SET_SRC (set)))
6037 search_equiv = SET_SRC (set);
6043 = find_equiv_reg (search_equiv, insn, reload_reg_class[r],
6044 -1, NULL_PTR, 0, reload_mode[r]);
6049 if (GET_CODE (equiv) == REG)
6050 regno = REGNO (equiv);
6051 else if (GET_CODE (equiv) == SUBREG)
6053 /* This must be a SUBREG of a hard register.
6054 Make a new REG since this might be used in an
6055 address and not all machines support SUBREGs
6057 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6058 equiv = gen_rtx_REG (reload_mode[r], regno);
6064 /* If we found a spill reg, reject it unless it is free
6065 and of the desired class. */
6067 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6068 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
6069 reload_when_needed[r],
6071 reload_out[r], r, 1))
6072 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6076 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
6079 /* We found a register that contains the value we need.
6080 If this register is the same as an `earlyclobber' operand
6081 of the current insn, just mark it as a place to reload from
6082 since we can't use it as the reload register itself. */
6085 for (i = 0; i < n_earlyclobbers; i++)
6086 if (reg_overlap_mentioned_for_reload_p (equiv,
6087 reload_earlyclobbers[i]))
6089 reload_override_in[r] = equiv;
6094 /* If the equiv register we have found is explicitly clobbered
6095 in the current insn, it depends on the reload type if we
6096 can use it, use it for reload_override_in, or not at all.
6097 In particular, we then can't use EQUIV for a
6098 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6100 if (equiv != 0 && regno_clobbered_p (regno, insn))
6102 switch (reload_when_needed[r])
6104 case RELOAD_FOR_OTHER_ADDRESS:
6105 case RELOAD_FOR_INPADDR_ADDRESS:
6106 case RELOAD_FOR_INPUT_ADDRESS:
6107 case RELOAD_FOR_OPADDR_ADDR:
6110 case RELOAD_FOR_INPUT:
6111 case RELOAD_FOR_OPERAND_ADDRESS:
6112 reload_override_in[r] = equiv;
6120 /* If we found an equivalent reg, say no code need be generated
6121 to load it, and use it as our reload reg. */
6122 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6124 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6126 reload_reg_rtx[r] = equiv;
6127 reload_inherited[r] = 1;
6129 /* If reg_reloaded_valid is not set for this register,
6130 there might be a stale spill_reg_store lying around.
6131 We must clear it, since otherwise emit_reload_insns
6132 might delete the store. */
6133 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6134 spill_reg_store[regno] = NULL_RTX;
6135 /* If any of the hard registers in EQUIV are spill
6136 registers, mark them as in use for this insn. */
6137 for (k = 0; k < nr; k++)
6139 i = spill_reg_order[regno + k];
6142 mark_reload_reg_in_use (regno, reload_opnum[r],
6143 reload_when_needed[r],
6145 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6152 /* If we found a register to use already, or if this is an optional
6153 reload, we are done. */
6154 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6157 #if 0 /* No longer needed for correct operation. Might or might not
6158 give better code on the average. Want to experiment? */
6160 /* See if there is a later reload that has a class different from our
6161 class that intersects our class or that requires less register
6162 than our reload. If so, we must allocate a register to this
6163 reload now, since that reload might inherit a previous reload
6164 and take the only available register in our class. Don't do this
6165 for optional reloads since they will force all previous reloads
6166 to be allocated. Also don't do this for reloads that have been
6169 for (i = j + 1; i < n_reloads; i++)
6171 int s = reload_order[i];
6173 if ((reload_in[s] == 0 && reload_out[s] == 0
6174 && ! reload_secondary_p[s])
6175 || reload_optional[s])
6178 if ((reload_reg_class[s] != reload_reg_class[r]
6179 && reg_classes_intersect_p (reload_reg_class[r],
6180 reload_reg_class[s]))
6181 || reload_nregs[s] < reload_nregs[r])
6188 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6192 /* Now allocate reload registers for anything non-optional that
6193 didn't get one yet. */
6194 for (j = 0; j < n_reloads; j++)
6196 register int r = reload_order[j];
6198 /* Ignore reloads that got marked inoperative. */
6199 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6202 /* Skip reloads that already have a register allocated or are
6204 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6207 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6211 /* If that loop got all the way, we have won. */
6215 /* Loop around and try without any inheritance. */
6216 /* First undo everything done by the failed attempt
6217 to allocate with inheritance. */
6218 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6219 sizeof reload_reg_rtx);
6220 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6221 sizeof reload_inherited);
6222 bcopy ((char *) save_reload_inheritance_insn,
6223 (char *) reload_inheritance_insn,
6224 sizeof reload_inheritance_insn);
6225 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6226 sizeof reload_override_in);
6227 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6228 sizeof reload_spill_index);
6229 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6230 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6231 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6232 save_reload_reg_used_in_op_addr);
6233 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6234 save_reload_reg_used_in_op_addr_reload);
6235 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6236 save_reload_reg_used_in_insn);
6237 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6238 save_reload_reg_used_in_other_addr);
6240 for (i = 0; i < reload_n_operands; i++)
6242 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6243 save_reload_reg_used_in_input[i]);
6244 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6245 save_reload_reg_used_in_output[i]);
6246 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6247 save_reload_reg_used_in_input_addr[i]);
6248 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6249 save_reload_reg_used_in_inpaddr_addr[i]);
6250 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6251 save_reload_reg_used_in_output_addr[i]);
6252 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6253 save_reload_reg_used_in_outaddr_addr[i]);
6257 /* If we thought we could inherit a reload, because it seemed that
6258 nothing else wanted the same reload register earlier in the insn,
6259 verify that assumption, now that all reloads have been assigned.
6260 Likewise for reloads where reload_override_in has been set. */
6262 /* If doing expensive optimizations, do one preliminary pass that doesn't
6263 cancel any inheritance, but removes reloads that have been needed only
6264 for reloads that we know can be inherited. */
6265 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6267 for (j = 0; j < n_reloads; j++)
6269 register int r = reload_order[j];
6271 if (reload_inherited[r] && reload_reg_rtx[r])
6272 check_reg = reload_reg_rtx[r];
6273 else if (reload_override_in[r]
6274 && (GET_CODE (reload_override_in[r]) == REG
6275 || GET_CODE (reload_override_in[r]) == SUBREG))
6276 check_reg = reload_override_in[r];
6279 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6281 reload_when_needed[r],
6283 (reload_inherited[r]
6284 ? reload_out[r] : const0_rtx),
6289 reload_inherited[r] = 0;
6290 reload_override_in[r] = 0;
6292 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6293 reload_override_in, then we do not need its related
6294 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6295 likewise for other reload types.
6296 We handle this by removing a reload when its only replacement
6297 is mentioned in reload_in of the reload we are going to inherit.
6298 A special case are auto_inc expressions; even if the input is
6299 inherited, we still need the address for the output. We can
6300 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6301 If we suceeded removing some reload and we are doing a preliminary
6302 pass just to remove such reloads, make another pass, since the
6303 removal of one reload might allow us to inherit another one. */
6304 else if (reload_in[r]
6305 && reload_out[r] != reload_in[r]
6306 && remove_address_replacements (reload_in[r]) && pass)
6311 /* Now that reload_override_in is known valid,
6312 actually override reload_in. */
6313 for (j = 0; j < n_reloads; j++)
6314 if (reload_override_in[j])
6315 reload_in[j] = reload_override_in[j];
6317 /* If this reload won't be done because it has been cancelled or is
6318 optional and not inherited, clear reload_reg_rtx so other
6319 routines (such as subst_reloads) don't get confused. */
6320 for (j = 0; j < n_reloads; j++)
6321 if (reload_reg_rtx[j] != 0
6322 && ((reload_optional[j] && ! reload_inherited[j])
6323 || (reload_in[j] == 0 && reload_out[j] == 0
6324 && ! reload_secondary_p[j])))
6326 int regno = true_regnum (reload_reg_rtx[j]);
6328 if (spill_reg_order[regno] >= 0)
6329 clear_reload_reg_in_use (regno, reload_opnum[j],
6330 reload_when_needed[j], reload_mode[j]);
6331 reload_reg_rtx[j] = 0;
6334 /* Record which pseudos and which spill regs have output reloads. */
6335 for (j = 0; j < n_reloads; j++)
6337 register int r = reload_order[j];
6339 i = reload_spill_index[r];
6341 /* I is nonneg if this reload uses a register.
6342 If reload_reg_rtx[r] is 0, this is an optional reload
6343 that we opted to ignore. */
6344 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6345 && reload_reg_rtx[r] != 0)
6347 register int nregno = REGNO (reload_out_reg[r]);
6350 if (nregno < FIRST_PSEUDO_REGISTER)
6351 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6354 reg_has_output_reload[nregno + nr] = 1;
6358 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6360 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6363 if (reload_when_needed[r] != RELOAD_OTHER
6364 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6365 && reload_when_needed[r] != RELOAD_FOR_INSN)
6371 /* Deallocate the reload register for reload R. This is called from
6372 remove_address_replacements. */
6374 deallocate_reload_reg (r)
6379 if (! reload_reg_rtx[r])
6381 regno = true_regnum (reload_reg_rtx[r]);
6382 reload_reg_rtx[r] = 0;
6383 if (spill_reg_order[regno] >= 0)
6384 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6386 reload_spill_index[r] = -1;
6389 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6390 reloads of the same item for fear that we might not have enough reload
6391 registers. However, normally they will get the same reload register
6392 and hence actually need not be loaded twice.
6394 Here we check for the most common case of this phenomenon: when we have
6395 a number of reloads for the same object, each of which were allocated
6396 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6397 reload, and is not modified in the insn itself. If we find such,
6398 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6399 This will not increase the number of spill registers needed and will
6400 prevent redundant code. */
6403 merge_assigned_reloads (insn)
6408 /* Scan all the reloads looking for ones that only load values and
6409 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6410 assigned and not modified by INSN. */
6412 for (i = 0; i < n_reloads; i++)
6414 int conflicting_input = 0;
6415 int max_input_address_opnum = -1;
6416 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6418 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6419 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6420 || reg_set_p (reload_reg_rtx[i], insn))
6423 /* Look at all other reloads. Ensure that the only use of this
6424 reload_reg_rtx is in a reload that just loads the same value
6425 as we do. Note that any secondary reloads must be of the identical
6426 class since the values, modes, and result registers are the
6427 same, so we need not do anything with any secondary reloads. */
6429 for (j = 0; j < n_reloads; j++)
6431 if (i == j || reload_reg_rtx[j] == 0
6432 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6436 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6437 && reload_opnum[j] > max_input_address_opnum)
6438 max_input_address_opnum = reload_opnum[j];
6440 /* If the reload regs aren't exactly the same (e.g, different modes)
6441 or if the values are different, we can't merge this reload.
6442 But if it is an input reload, we might still merge
6443 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6445 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6446 || reload_out[j] != 0 || reload_in[j] == 0
6447 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6449 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6450 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6451 || reload_opnum[i] > reload_opnum[j])
6452 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6454 conflicting_input = 1;
6455 if (min_conflicting_input_opnum > reload_opnum[j])
6456 min_conflicting_input_opnum = reload_opnum[j];
6460 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6461 we, in fact, found any matching reloads. */
6464 && max_input_address_opnum <= min_conflicting_input_opnum)
6466 for (j = 0; j < n_reloads; j++)
6467 if (i != j && reload_reg_rtx[j] != 0
6468 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6469 && (! conflicting_input
6470 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6471 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6473 reload_when_needed[i] = RELOAD_OTHER;
6475 reload_spill_index[j] = -1;
6476 transfer_replacements (i, j);
6479 /* If this is now RELOAD_OTHER, look for any reloads that load
6480 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6481 if they were for inputs, RELOAD_OTHER for outputs. Note that
6482 this test is equivalent to looking for reloads for this operand
6485 if (reload_when_needed[i] == RELOAD_OTHER)
6486 for (j = 0; j < n_reloads; j++)
6487 if (reload_in[j] != 0
6488 && reload_when_needed[i] != RELOAD_OTHER
6489 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6491 reload_when_needed[j]
6492 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6493 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6494 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6500 /* Output insns to reload values in and out of the chosen reload regs. */
6503 emit_reload_insns (chain)
6504 struct insn_chain *chain;
6506 rtx insn = chain->insn;
6509 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6510 rtx other_input_address_reload_insns = 0;
6511 rtx other_input_reload_insns = 0;
6512 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6513 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6514 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6515 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6516 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6517 rtx operand_reload_insns = 0;
6518 rtx other_operand_reload_insns = 0;
6519 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6520 rtx following_insn = NEXT_INSN (insn);
6521 rtx before_insn = PREV_INSN (insn);
6523 /* Values to be put in spill_reg_store are put here first. */
6524 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6525 HARD_REG_SET reg_reloaded_died;
6527 CLEAR_HARD_REG_SET (reg_reloaded_died);
6529 for (j = 0; j < reload_n_operands; j++)
6530 input_reload_insns[j] = input_address_reload_insns[j]
6531 = inpaddr_address_reload_insns[j]
6532 = output_reload_insns[j] = output_address_reload_insns[j]
6533 = outaddr_address_reload_insns[j]
6534 = other_output_reload_insns[j] = 0;
6536 /* Now output the instructions to copy the data into and out of the
6537 reload registers. Do these in the order that the reloads were reported,
6538 since reloads of base and index registers precede reloads of operands
6539 and the operands may need the base and index registers reloaded. */
6541 for (j = 0; j < n_reloads; j++)
6544 rtx oldequiv_reg = 0;
6545 rtx this_reload_insn = 0;
6546 int expect_occurrences = 1;
6548 if (reload_reg_rtx[j]
6549 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6550 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6552 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6553 ? reload_in_reg[j] : reload_in[j]);
6556 /* AUTO_INC reloads need to be handled even if inherited. We got an
6557 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6558 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6559 && ! rtx_equal_p (reload_reg_rtx[j], old)
6560 && reload_reg_rtx[j] != 0)
6562 register rtx reloadreg = reload_reg_rtx[j];
6564 enum machine_mode mode;
6567 /* Determine the mode to reload in.
6568 This is very tricky because we have three to choose from.
6569 There is the mode the insn operand wants (reload_inmode[J]).
6570 There is the mode of the reload register RELOADREG.
6571 There is the intrinsic mode of the operand, which we could find
6572 by stripping some SUBREGs.
6573 It turns out that RELOADREG's mode is irrelevant:
6574 we can change that arbitrarily.
6576 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6577 then the reload reg may not support QImode moves, so use SImode.
6578 If foo is in memory due to spilling a pseudo reg, this is safe,
6579 because the QImode value is in the least significant part of a
6580 slot big enough for a SImode. If foo is some other sort of
6581 memory reference, then it is impossible to reload this case,
6582 so previous passes had better make sure this never happens.
6584 Then consider a one-word union which has SImode and one of its
6585 members is a float, being fetched as (SUBREG:SF union:SI).
6586 We must fetch that as SFmode because we could be loading into
6587 a float-only register. In this case OLD's mode is correct.
6589 Consider an immediate integer: it has VOIDmode. Here we need
6590 to get a mode from something else.
6592 In some cases, there is a fourth mode, the operand's
6593 containing mode. If the insn specifies a containing mode for
6594 this operand, it overrides all others.
6596 I am not sure whether the algorithm here is always right,
6597 but it does the right things in those cases. */
6599 mode = GET_MODE (old);
6600 if (mode == VOIDmode)
6601 mode = reload_inmode[j];
6603 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6604 /* If we need a secondary register for this operation, see if
6605 the value is already in a register in that class. Don't
6606 do this if the secondary register will be used as a scratch
6609 if (reload_secondary_in_reload[j] >= 0
6610 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6613 = find_equiv_reg (old, insn,
6614 reload_reg_class[reload_secondary_in_reload[j]],
6615 -1, NULL_PTR, 0, mode);
6618 /* If reloading from memory, see if there is a register
6619 that already holds the same value. If so, reload from there.
6620 We can pass 0 as the reload_reg_p argument because
6621 any other reload has either already been emitted,
6622 in which case find_equiv_reg will see the reload-insn,
6623 or has yet to be emitted, in which case it doesn't matter
6624 because we will use this equiv reg right away. */
6626 if (oldequiv == 0 && optimize
6627 && (GET_CODE (old) == MEM
6628 || (GET_CODE (old) == REG
6629 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6630 && reg_renumber[REGNO (old)] < 0)))
6631 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6632 -1, NULL_PTR, 0, mode);
6636 int regno = true_regnum (oldequiv);
6638 /* Don't use OLDEQUIV if any other reload changes it at an
6639 earlier stage of this insn or at this stage. */
6640 if (! reload_reg_free_for_value_p (regno, reload_opnum[j],
6641 reload_when_needed[j],
6642 reload_in[j], const0_rtx, j,
6646 /* If it is no cheaper to copy from OLDEQUIV into the
6647 reload register than it would be to move from memory,
6648 don't use it. Likewise, if we need a secondary register
6652 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6653 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6654 reload_reg_class[j])
6655 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6656 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6657 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6661 #ifdef SECONDARY_MEMORY_NEEDED
6662 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6663 reload_reg_class[j],
6670 /* delete_output_reload is only invoked properly if old contains
6671 the original pseudo register. Since this is replaced with a
6672 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6673 find the pseudo in RELOAD_IN_REG. */
6675 && reload_override_in[j]
6676 && GET_CODE (reload_in_reg[j]) == REG)
6679 old = reload_in_reg[j];
6683 else if (GET_CODE (oldequiv) == REG)
6684 oldequiv_reg = oldequiv;
6685 else if (GET_CODE (oldequiv) == SUBREG)
6686 oldequiv_reg = SUBREG_REG (oldequiv);
6688 /* If we are reloading from a register that was recently stored in
6689 with an output-reload, see if we can prove there was
6690 actually no need to store the old value in it. */
6692 if (optimize && GET_CODE (oldequiv) == REG
6693 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6694 && spill_reg_store[REGNO (oldequiv)]
6695 && GET_CODE (old) == REG
6696 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6697 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6698 reload_out_reg[j])))
6699 delete_output_reload (insn, j, REGNO (oldequiv));
6701 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6702 then load RELOADREG from OLDEQUIV. Note that we cannot use
6703 gen_lowpart_common since it can do the wrong thing when
6704 RELOADREG has a multi-word mode. Note that RELOADREG
6705 must always be a REG here. */
6707 if (GET_MODE (reloadreg) != mode)
6708 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6709 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6710 oldequiv = SUBREG_REG (oldequiv);
6711 if (GET_MODE (oldequiv) != VOIDmode
6712 && mode != GET_MODE (oldequiv))
6713 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6715 /* Switch to the right place to emit the reload insns. */
6716 switch (reload_when_needed[j])
6719 where = &other_input_reload_insns;
6721 case RELOAD_FOR_INPUT:
6722 where = &input_reload_insns[reload_opnum[j]];
6724 case RELOAD_FOR_INPUT_ADDRESS:
6725 where = &input_address_reload_insns[reload_opnum[j]];
6727 case RELOAD_FOR_INPADDR_ADDRESS:
6728 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6730 case RELOAD_FOR_OUTPUT_ADDRESS:
6731 where = &output_address_reload_insns[reload_opnum[j]];
6733 case RELOAD_FOR_OUTADDR_ADDRESS:
6734 where = &outaddr_address_reload_insns[reload_opnum[j]];
6736 case RELOAD_FOR_OPERAND_ADDRESS:
6737 where = &operand_reload_insns;
6739 case RELOAD_FOR_OPADDR_ADDR:
6740 where = &other_operand_reload_insns;
6742 case RELOAD_FOR_OTHER_ADDRESS:
6743 where = &other_input_address_reload_insns;
6749 push_to_sequence (*where);
6752 /* Auto-increment addresses must be reloaded in a special way. */
6753 if (reload_out[j] && ! reload_out_reg[j])
6755 /* We are not going to bother supporting the case where a
6756 incremented register can't be copied directly from
6757 OLDEQUIV since this seems highly unlikely. */
6758 if (reload_secondary_in_reload[j] >= 0)
6761 if (reload_inherited[j])
6762 oldequiv = reloadreg;
6764 old = XEXP (reload_in_reg[j], 0);
6766 if (optimize && GET_CODE (oldequiv) == REG
6767 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6768 && spill_reg_store[REGNO (oldequiv)]
6769 && GET_CODE (old) == REG
6770 && (dead_or_set_p (insn,
6771 spill_reg_stored_to[REGNO (oldequiv)])
6772 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6774 delete_output_reload (insn, j, REGNO (oldequiv));
6776 /* Prevent normal processing of this reload. */
6778 /* Output a special code sequence for this case. */
6779 new_spill_reg_store[REGNO (reloadreg)]
6780 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6784 /* If we are reloading a pseudo-register that was set by the previous
6785 insn, see if we can get rid of that pseudo-register entirely
6786 by redirecting the previous insn into our reload register. */
6788 else if (optimize && GET_CODE (old) == REG
6789 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6790 && dead_or_set_p (insn, old)
6791 /* This is unsafe if some other reload
6792 uses the same reg first. */
6793 && reload_reg_free_for_value_p (REGNO (reloadreg),
6795 reload_when_needed[j],
6799 rtx temp = PREV_INSN (insn);
6800 while (temp && GET_CODE (temp) == NOTE)
6801 temp = PREV_INSN (temp);
6803 && GET_CODE (temp) == INSN
6804 && GET_CODE (PATTERN (temp)) == SET
6805 && SET_DEST (PATTERN (temp)) == old
6806 /* Make sure we can access insn_operand_constraint. */
6807 && asm_noperands (PATTERN (temp)) < 0
6808 /* This is unsafe if prev insn rejects our reload reg. */
6809 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6811 /* This is unsafe if operand occurs more than once in current
6812 insn. Perhaps some occurrences aren't reloaded. */
6813 && count_occurrences (PATTERN (insn), old) == 1
6814 /* Don't risk splitting a matching pair of operands. */
6815 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6817 /* Store into the reload register instead of the pseudo. */
6818 SET_DEST (PATTERN (temp)) = reloadreg;
6820 /* If the previous insn is an output reload, the source is
6821 a reload register, and its spill_reg_store entry will
6822 contain the previous destination. This is now
6824 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6825 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6827 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6828 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6831 /* If these are the only uses of the pseudo reg,
6832 pretend for GDB it lives in the reload reg we used. */
6833 if (REG_N_DEATHS (REGNO (old)) == 1
6834 && REG_N_SETS (REGNO (old)) == 1)
6836 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6837 alter_reg (REGNO (old), -1);
6843 /* We can't do that, so output an insn to load RELOADREG. */
6847 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6848 rtx second_reload_reg = 0;
6849 enum insn_code icode;
6851 /* If we have a secondary reload, pick up the secondary register
6852 and icode, if any. If OLDEQUIV and OLD are different or
6853 if this is an in-out reload, recompute whether or not we
6854 still need a secondary register and what the icode should
6855 be. If we still need a secondary register and the class or
6856 icode is different, go back to reloading from OLD if using
6857 OLDEQUIV means that we got the wrong type of register. We
6858 cannot have different class or icode due to an in-out reload
6859 because we don't make such reloads when both the input and
6860 output need secondary reload registers. */
6862 if (reload_secondary_in_reload[j] >= 0)
6864 int secondary_reload = reload_secondary_in_reload[j];
6865 rtx real_oldequiv = oldequiv;
6869 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6870 and similarly for OLD.
6871 See comments in get_secondary_reload in reload.c. */
6872 /* If it is a pseudo that cannot be replaced with its
6873 equivalent MEM, we must fall back to reload_in, which
6874 will have all the necessary substitutions registered.
6875 Likewise for a pseudo that can't be replaced with its
6876 equivalent constant.
6878 Take extra care for subregs of such pseudos. Note that
6879 we cannot use reg_equiv_mem in this case because it is
6880 not in the right mode. */
6883 if (GET_CODE (tmp) == SUBREG)
6884 tmp = SUBREG_REG (tmp);
6885 if (GET_CODE (tmp) == REG
6886 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6887 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6888 || reg_equiv_constant[REGNO (tmp)] != 0))
6890 if (! reg_equiv_mem[REGNO (tmp)]
6891 || num_not_at_initial_offset
6892 || GET_CODE (oldequiv) == SUBREG)
6893 real_oldequiv = reload_in[j];
6895 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6899 if (GET_CODE (tmp) == SUBREG)
6900 tmp = SUBREG_REG (tmp);
6901 if (GET_CODE (tmp) == REG
6902 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6903 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6904 || reg_equiv_constant[REGNO (tmp)] != 0))
6906 if (! reg_equiv_mem[REGNO (tmp)]
6907 || num_not_at_initial_offset
6908 || GET_CODE (old) == SUBREG)
6909 real_old = reload_in[j];
6911 real_old = reg_equiv_mem[REGNO (tmp)];
6914 second_reload_reg = reload_reg_rtx[secondary_reload];
6915 icode = reload_secondary_in_icode[j];
6917 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6918 || (reload_in[j] != 0 && reload_out[j] != 0))
6920 enum reg_class new_class
6921 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6922 mode, real_oldequiv);
6924 if (new_class == NO_REGS)
6925 second_reload_reg = 0;
6928 enum insn_code new_icode;
6929 enum machine_mode new_mode;
6931 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6932 REGNO (second_reload_reg)))
6933 oldequiv = old, real_oldequiv = real_old;
6936 new_icode = reload_in_optab[(int) mode];
6937 if (new_icode != CODE_FOR_nothing
6938 && ((insn_operand_predicate[(int) new_icode][0]
6939 && ! ((*insn_operand_predicate[(int) new_icode][0])
6941 || (insn_operand_predicate[(int) new_icode][1]
6942 && ! ((*insn_operand_predicate[(int) new_icode][1])
6943 (real_oldequiv, mode)))))
6944 new_icode = CODE_FOR_nothing;
6946 if (new_icode == CODE_FOR_nothing)
6949 new_mode = insn_operand_mode[(int) new_icode][2];
6951 if (GET_MODE (second_reload_reg) != new_mode)
6953 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6955 oldequiv = old, real_oldequiv = real_old;
6958 = gen_rtx_REG (new_mode,
6959 REGNO (second_reload_reg));
6965 /* If we still need a secondary reload register, check
6966 to see if it is being used as a scratch or intermediate
6967 register and generate code appropriately. If we need
6968 a scratch register, use REAL_OLDEQUIV since the form of
6969 the insn may depend on the actual address if it is
6972 if (second_reload_reg)
6974 if (icode != CODE_FOR_nothing)
6976 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6977 second_reload_reg));
6982 /* See if we need a scratch register to load the
6983 intermediate register (a tertiary reload). */
6984 enum insn_code tertiary_icode
6985 = reload_secondary_in_icode[secondary_reload];
6987 if (tertiary_icode != CODE_FOR_nothing)
6989 rtx third_reload_reg
6990 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6992 emit_insn ((GEN_FCN (tertiary_icode)
6993 (second_reload_reg, real_oldequiv,
6994 third_reload_reg)));
6997 gen_reload (second_reload_reg, real_oldequiv,
6999 reload_when_needed[j]);
7001 oldequiv = second_reload_reg;
7007 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7009 rtx real_oldequiv = oldequiv;
7011 if ((GET_CODE (oldequiv) == REG
7012 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7013 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7014 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7015 || (GET_CODE (oldequiv) == SUBREG
7016 && GET_CODE (SUBREG_REG (oldequiv)) == REG
7017 && (REGNO (SUBREG_REG (oldequiv))
7018 >= FIRST_PSEUDO_REGISTER)
7019 && ((reg_equiv_memory_loc
7020 [REGNO (SUBREG_REG (oldequiv))] != 0)
7021 || (reg_equiv_constant
7022 [REGNO (SUBREG_REG (oldequiv))] != 0))))
7023 real_oldequiv = reload_in[j];
7024 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
7025 reload_when_needed[j]);
7030 this_reload_insn = get_last_insn ();
7031 /* End this sequence. */
7032 *where = get_insns ();
7035 /* Update reload_override_in so that delete_address_reloads_1
7036 can see the actual register usage. */
7038 reload_override_in[j] = oldequiv;
7041 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7042 e.g. inheriting a SImode output reload for
7043 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7044 if (optimize && reload_inherited[j] && reload_in[j]
7045 && GET_CODE (reload_in[j]) == MEM
7046 && GET_CODE (reload_in_reg[j]) == MEM
7047 && reload_spill_index[j] >= 0
7048 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7051 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
7053 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7056 /* If we are reloading a register that was recently stored in with an
7057 output-reload, see if we can prove there was
7058 actually no need to store the old value in it. */
7061 && (reload_inherited[j] || reload_override_in[j])
7062 && reload_reg_rtx[j]
7063 && GET_CODE (reload_reg_rtx[j]) == REG
7064 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
7066 /* There doesn't seem to be any reason to restrict this to pseudos
7067 and doing so loses in the case where we are copying from a
7068 register of the wrong class. */
7069 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7070 >= FIRST_PSEUDO_REGISTER
7072 /* The insn might have already some references to stackslots
7073 replaced by MEMs, while reload_out_reg still names the
7075 && (dead_or_set_p (insn,
7076 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7077 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
7078 reload_out_reg[j])))
7079 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
7081 /* Input-reloading is done. Now do output-reloading,
7082 storing the value from the reload-register after the main insn
7083 if reload_out[j] is nonzero.
7085 ??? At some point we need to support handling output reloads of
7086 JUMP_INSNs or insns that set cc0. */
7088 /* If this is an output reload that stores something that is
7089 not loaded in this same reload, see if we can eliminate a previous
7092 rtx pseudo = reload_out_reg[j];
7095 && GET_CODE (pseudo) == REG
7096 && ! rtx_equal_p (reload_in_reg[j], pseudo)
7097 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7098 && reg_last_reload_reg[REGNO (pseudo)])
7100 int pseudo_no = REGNO (pseudo);
7101 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7103 /* We don't need to test full validity of last_regno for
7104 inherit here; we only want to know if the store actually
7105 matches the pseudo. */
7106 if (reg_reloaded_contents[last_regno] == pseudo_no
7107 && spill_reg_store[last_regno]
7108 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7109 delete_output_reload (insn, j, last_regno);
7113 old = reload_out_reg[j];
7115 && reload_reg_rtx[j] != old
7116 && reload_reg_rtx[j] != 0)
7118 register rtx reloadreg = reload_reg_rtx[j];
7119 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7120 register rtx second_reloadreg = 0;
7123 enum machine_mode mode;
7126 /* An output operand that dies right away does need a reload,
7127 but need not be copied from it. Show the new location in the
7129 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7130 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7132 XEXP (note, 0) = reload_reg_rtx[j];
7135 /* Likewise for a SUBREG of an operand that dies. */
7136 else if (GET_CODE (old) == SUBREG
7137 && GET_CODE (SUBREG_REG (old)) == REG
7138 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7141 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7145 else if (GET_CODE (old) == SCRATCH)
7146 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7147 but we don't want to make an output reload. */
7151 /* Strip off of OLD any size-increasing SUBREGs such as
7152 (SUBREG:SI foo:QI 0). */
7154 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7155 && (GET_MODE_SIZE (GET_MODE (old))
7156 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7157 old = SUBREG_REG (old);
7160 /* If is a JUMP_INSN, we can't support output reloads yet. */
7161 if (GET_CODE (insn) == JUMP_INSN)
7164 if (reload_when_needed[j] == RELOAD_OTHER)
7167 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7169 old = reload_out[j];
7171 /* Determine the mode to reload in.
7172 See comments above (for input reloading). */
7174 mode = GET_MODE (old);
7175 if (mode == VOIDmode)
7177 /* VOIDmode should never happen for an output. */
7178 if (asm_noperands (PATTERN (insn)) < 0)
7179 /* It's the compiler's fault. */
7180 fatal_insn ("VOIDmode on an output", insn);
7181 error_for_asm (insn, "output operand is constant in `asm'");
7182 /* Prevent crash--use something we know is valid. */
7184 old = gen_rtx_REG (mode, REGNO (reloadreg));
7187 if (GET_MODE (reloadreg) != mode)
7188 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7190 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7192 /* If we need two reload regs, set RELOADREG to the intermediate
7193 one, since it will be stored into OLD. We might need a secondary
7194 register only for an input reload, so check again here. */
7196 if (reload_secondary_out_reload[j] >= 0)
7200 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7201 && reg_equiv_mem[REGNO (old)] != 0)
7202 real_old = reg_equiv_mem[REGNO (old)];
7204 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7208 second_reloadreg = reloadreg;
7209 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7211 /* See if RELOADREG is to be used as a scratch register
7212 or as an intermediate register. */
7213 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7215 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7216 (real_old, second_reloadreg, reloadreg)));
7221 /* See if we need both a scratch and intermediate reload
7224 int secondary_reload = reload_secondary_out_reload[j];
7225 enum insn_code tertiary_icode
7226 = reload_secondary_out_icode[secondary_reload];
7228 if (GET_MODE (reloadreg) != mode)
7229 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7231 if (tertiary_icode != CODE_FOR_nothing)
7234 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7237 /* Copy primary reload reg to secondary reload reg.
7238 (Note that these have been swapped above, then
7239 secondary reload reg to OLD using our insn. */
7241 /* If REAL_OLD is a paradoxical SUBREG, remove it
7242 and try to put the opposite SUBREG on
7244 if (GET_CODE (real_old) == SUBREG
7245 && (GET_MODE_SIZE (GET_MODE (real_old))
7246 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7247 && 0 != (tem = gen_lowpart_common
7248 (GET_MODE (SUBREG_REG (real_old)),
7250 real_old = SUBREG_REG (real_old), reloadreg = tem;
7252 gen_reload (reloadreg, second_reloadreg,
7253 reload_opnum[j], reload_when_needed[j]);
7254 emit_insn ((GEN_FCN (tertiary_icode)
7255 (real_old, reloadreg, third_reloadreg)));
7260 /* Copy between the reload regs here and then to
7263 gen_reload (reloadreg, second_reloadreg,
7264 reload_opnum[j], reload_when_needed[j]);
7270 /* Output the last reload insn. */
7275 /* Don't output the last reload if OLD is not the dest of
7276 INSN and is in the src and is clobbered by INSN. */
7277 if (! flag_expensive_optimizations
7278 || GET_CODE (old) != REG
7279 || !(set = single_set (insn))
7280 || rtx_equal_p (old, SET_DEST (set))
7281 || !reg_mentioned_p (old, SET_SRC (set))
7282 || !regno_clobbered_p (REGNO (old), insn))
7283 gen_reload (old, reloadreg, reload_opnum[j],
7284 reload_when_needed[j]);
7287 /* Look at all insns we emitted, just to be safe. */
7288 for (p = get_insns (); p; p = NEXT_INSN (p))
7289 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7291 rtx pat = PATTERN (p);
7293 /* If this output reload doesn't come from a spill reg,
7294 clear any memory of reloaded copies of the pseudo reg.
7295 If this output reload comes from a spill reg,
7296 reg_has_output_reload will make this do nothing. */
7297 note_stores (pat, forget_old_reloads_1);
7299 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7301 rtx set = single_set (insn);
7302 if (reload_spill_index[j] < 0
7304 && SET_SRC (set) == reload_reg_rtx[j])
7306 int src = REGNO (SET_SRC (set));
7308 reload_spill_index[j] = src;
7309 SET_HARD_REG_BIT (reg_is_output_reload, src);
7310 if (find_regno_note (insn, REG_DEAD, src))
7311 SET_HARD_REG_BIT (reg_reloaded_died, src);
7313 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7315 int s = reload_secondary_out_reload[j];
7316 set = single_set (p);
7317 /* If this reload copies only to the secondary reload
7318 register, the secondary reload does the actual
7320 if (s >= 0 && set == NULL_RTX)
7321 ; /* We can't tell what function the secondary reload
7322 has and where the actual store to the pseudo is
7323 made; leave new_spill_reg_store alone. */
7325 && SET_SRC (set) == reload_reg_rtx[j]
7326 && SET_DEST (set) == reload_reg_rtx[s])
7328 /* Usually the next instruction will be the
7329 secondary reload insn; if we can confirm
7330 that it is, setting new_spill_reg_store to
7331 that insn will allow an extra optimization. */
7332 rtx s_reg = reload_reg_rtx[s];
7333 rtx next = NEXT_INSN (p);
7334 reload_out[s] = reload_out[j];
7335 reload_out_reg[s] = reload_out_reg[j];
7336 set = single_set (next);
7337 if (set && SET_SRC (set) == s_reg
7338 && ! new_spill_reg_store[REGNO (s_reg)])
7340 SET_HARD_REG_BIT (reg_is_output_reload,
7342 new_spill_reg_store[REGNO (s_reg)] = next;
7346 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7351 if (reload_when_needed[j] == RELOAD_OTHER)
7353 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7354 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7357 output_reload_insns[reload_opnum[j]] = get_insns ();
7363 /* Now write all the insns we made for reloads in the order expected by
7364 the allocation functions. Prior to the insn being reloaded, we write
7365 the following reloads:
7367 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7369 RELOAD_OTHER reloads.
7371 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7372 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7373 RELOAD_FOR_INPUT reload for the operand.
7375 RELOAD_FOR_OPADDR_ADDRS reloads.
7377 RELOAD_FOR_OPERAND_ADDRESS reloads.
7379 After the insn being reloaded, we write the following:
7381 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7382 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7383 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7384 reloads for the operand. The RELOAD_OTHER output reloads are
7385 output in descending order by reload number. */
7387 emit_insns_before (other_input_address_reload_insns, insn);
7388 emit_insns_before (other_input_reload_insns, insn);
7390 for (j = 0; j < reload_n_operands; j++)
7392 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7393 emit_insns_before (input_address_reload_insns[j], insn);
7394 emit_insns_before (input_reload_insns[j], insn);
7397 emit_insns_before (other_operand_reload_insns, insn);
7398 emit_insns_before (operand_reload_insns, insn);
7400 for (j = 0; j < reload_n_operands; j++)
7402 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7403 emit_insns_before (output_address_reload_insns[j], following_insn);
7404 emit_insns_before (output_reload_insns[j], following_insn);
7405 emit_insns_before (other_output_reload_insns[j], following_insn);
7408 /* Keep basic block info up to date. */
7411 if (BLOCK_HEAD (chain->block) == insn)
7412 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7413 if (BLOCK_END (chain->block) == insn)
7414 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7417 /* For all the spill regs newly reloaded in this instruction,
7418 record what they were reloaded from, so subsequent instructions
7419 can inherit the reloads.
7421 Update spill_reg_store for the reloads of this insn.
7422 Copy the elements that were updated in the loop above. */
7424 for (j = 0; j < n_reloads; j++)
7426 register int r = reload_order[j];
7427 register int i = reload_spill_index[r];
7429 /* If this is a non-inherited input reload from a pseudo, we must
7430 clear any memory of a previous store to the same pseudo. Only do
7431 something if there will not be an output reload for the pseudo
7433 if (reload_in_reg[r] != 0
7434 && ! (reload_inherited[r] || reload_override_in[r]))
7436 rtx reg = reload_in_reg[r];
7438 if (GET_CODE (reg) == SUBREG)
7439 reg = SUBREG_REG (reg);
7441 if (GET_CODE (reg) == REG
7442 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7443 && ! reg_has_output_reload[REGNO (reg)])
7445 int nregno = REGNO (reg);
7447 if (reg_last_reload_reg[nregno])
7449 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7451 if (reg_reloaded_contents[last_regno] == nregno)
7452 spill_reg_store[last_regno] = 0;
7457 /* I is nonneg if this reload used a register.
7458 If reload_reg_rtx[r] is 0, this is an optional reload
7459 that we opted to ignore. */
7461 if (i >= 0 && reload_reg_rtx[r] != 0)
7464 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7466 int part_reaches_end = 0;
7467 int all_reaches_end = 1;
7469 /* For a multi register reload, we need to check if all or part
7470 of the value lives to the end. */
7471 for (k = 0; k < nr; k++)
7473 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7474 reload_when_needed[r]))
7475 part_reaches_end = 1;
7477 all_reaches_end = 0;
7480 /* Ignore reloads that don't reach the end of the insn in
7482 if (all_reaches_end)
7484 /* First, clear out memory of what used to be in this spill reg.
7485 If consecutive registers are used, clear them all. */
7487 for (k = 0; k < nr; k++)
7488 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7490 /* Maybe the spill reg contains a copy of reload_out. */
7491 if (reload_out[r] != 0
7492 && (GET_CODE (reload_out[r]) == REG
7494 || ! reload_out_reg[r]
7496 || GET_CODE (reload_out_reg[r]) == REG))
7498 rtx out = (GET_CODE (reload_out[r]) == REG
7502 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7503 register int nregno = REGNO (out);
7504 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7505 : HARD_REGNO_NREGS (nregno,
7506 GET_MODE (reload_reg_rtx[r])));
7508 spill_reg_store[i] = new_spill_reg_store[i];
7509 spill_reg_stored_to[i] = out;
7510 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7512 /* If NREGNO is a hard register, it may occupy more than
7513 one register. If it does, say what is in the
7514 rest of the registers assuming that both registers
7515 agree on how many words the object takes. If not,
7516 invalidate the subsequent registers. */
7518 if (nregno < FIRST_PSEUDO_REGISTER)
7519 for (k = 1; k < nnr; k++)
7520 reg_last_reload_reg[nregno + k]
7522 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7523 REGNO (reload_reg_rtx[r]) + k)
7526 /* Now do the inverse operation. */
7527 for (k = 0; k < nr; k++)
7529 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7530 reg_reloaded_contents[i + k]
7531 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7534 reg_reloaded_insn[i + k] = insn;
7535 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7539 /* Maybe the spill reg contains a copy of reload_in. Only do
7540 something if there will not be an output reload for
7541 the register being reloaded. */
7542 else if (reload_out_reg[r] == 0
7543 && reload_in[r] != 0
7544 && ((GET_CODE (reload_in[r]) == REG
7545 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7546 && ! reg_has_output_reload[REGNO (reload_in[r])])
7547 || (GET_CODE (reload_in_reg[r]) == REG
7548 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7549 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7551 register int nregno;
7554 if (GET_CODE (reload_in[r]) == REG
7555 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7556 nregno = REGNO (reload_in[r]);
7557 else if (GET_CODE (reload_in_reg[r]) == REG)
7558 nregno = REGNO (reload_in_reg[r]);
7560 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7562 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7563 : HARD_REGNO_NREGS (nregno,
7564 GET_MODE (reload_reg_rtx[r])));
7566 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7568 if (nregno < FIRST_PSEUDO_REGISTER)
7569 for (k = 1; k < nnr; k++)
7570 reg_last_reload_reg[nregno + k]
7572 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7573 REGNO (reload_reg_rtx[r]) + k)
7576 /* Unless we inherited this reload, show we haven't
7577 recently done a store.
7578 Previous stores of inherited auto_inc expressions
7579 also have to be discarded. */
7580 if (! reload_inherited[r]
7581 || (reload_out[r] && ! reload_out_reg[r]))
7582 spill_reg_store[i] = 0;
7584 for (k = 0; k < nr; k++)
7586 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7587 reg_reloaded_contents[i + k]
7588 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7591 reg_reloaded_insn[i + k] = insn;
7592 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7597 /* However, if part of the reload reaches the end, then we must
7598 invalidate the old info for the part that survives to the end. */
7599 else if (part_reaches_end)
7601 for (k = 0; k < nr; k++)
7602 if (reload_reg_reaches_end_p (i + k,
7604 reload_when_needed[r]))
7605 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7609 /* The following if-statement was #if 0'd in 1.34 (or before...).
7610 It's reenabled in 1.35 because supposedly nothing else
7611 deals with this problem. */
7613 /* If a register gets output-reloaded from a non-spill register,
7614 that invalidates any previous reloaded copy of it.
7615 But forget_old_reloads_1 won't get to see it, because
7616 it thinks only about the original insn. So invalidate it here. */
7617 if (i < 0 && reload_out[r] != 0
7618 && (GET_CODE (reload_out[r]) == REG
7619 || (GET_CODE (reload_out[r]) == MEM
7620 && GET_CODE (reload_out_reg[r]) == REG)))
7622 rtx out = (GET_CODE (reload_out[r]) == REG
7623 ? reload_out[r] : reload_out_reg[r]);
7624 register int nregno = REGNO (out);
7625 if (nregno >= FIRST_PSEUDO_REGISTER)
7627 rtx src_reg, store_insn;
7629 reg_last_reload_reg[nregno] = 0;
7631 /* If we can find a hard register that is stored, record
7632 the storing insn so that we may delete this insn with
7633 delete_output_reload. */
7634 src_reg = reload_reg_rtx[r];
7636 /* If this is an optional reload, try to find the source reg
7637 from an input reload. */
7640 rtx set = single_set (insn);
7641 if (set && SET_DEST (set) == reload_out[r])
7645 src_reg = SET_SRC (set);
7647 for (k = 0; k < n_reloads; k++)
7649 if (reload_in[k] == src_reg)
7651 src_reg = reload_reg_rtx[k];
7658 store_insn = new_spill_reg_store[REGNO (src_reg)];
7659 if (src_reg && GET_CODE (src_reg) == REG
7660 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7662 int src_regno = REGNO (src_reg);
7663 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7664 /* The place where to find a death note varies with
7665 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7666 necessarily checked exactly in the code that moves
7667 notes, so just check both locations. */
7668 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7670 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7673 spill_reg_store[src_regno + nr] = store_insn;
7674 spill_reg_stored_to[src_regno + nr] = out;
7675 reg_reloaded_contents[src_regno + nr] = nregno;
7676 reg_reloaded_insn[src_regno + nr] = store_insn;
7677 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7678 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7679 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7681 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7683 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7685 reg_last_reload_reg[nregno] = src_reg;
7690 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7692 while (num_regs-- > 0)
7693 reg_last_reload_reg[nregno + num_regs] = 0;
7697 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7700 /* Emit code to perform a reload from IN (which may be a reload register) to
7701 OUT (which may also be a reload register). IN or OUT is from operand
7702 OPNUM with reload type TYPE.
7704 Returns first insn emitted. */
7707 gen_reload (out, in, opnum, type)
7711 enum reload_type type;
7713 rtx last = get_last_insn ();
7716 /* If IN is a paradoxical SUBREG, remove it and try to put the
7717 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7718 if (GET_CODE (in) == SUBREG
7719 && (GET_MODE_SIZE (GET_MODE (in))
7720 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7721 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7722 in = SUBREG_REG (in), out = tem;
7723 else if (GET_CODE (out) == SUBREG
7724 && (GET_MODE_SIZE (GET_MODE (out))
7725 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7726 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7727 out = SUBREG_REG (out), in = tem;
7729 /* How to do this reload can get quite tricky. Normally, we are being
7730 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7731 register that didn't get a hard register. In that case we can just
7732 call emit_move_insn.
7734 We can also be asked to reload a PLUS that adds a register or a MEM to
7735 another register, constant or MEM. This can occur during frame pointer
7736 elimination and while reloading addresses. This case is handled by
7737 trying to emit a single insn to perform the add. If it is not valid,
7738 we use a two insn sequence.
7740 Finally, we could be called to handle an 'o' constraint by putting
7741 an address into a register. In that case, we first try to do this
7742 with a named pattern of "reload_load_address". If no such pattern
7743 exists, we just emit a SET insn and hope for the best (it will normally
7744 be valid on machines that use 'o').
7746 This entire process is made complex because reload will never
7747 process the insns we generate here and so we must ensure that
7748 they will fit their constraints and also by the fact that parts of
7749 IN might be being reloaded separately and replaced with spill registers.
7750 Because of this, we are, in some sense, just guessing the right approach
7751 here. The one listed above seems to work.
7753 ??? At some point, this whole thing needs to be rethought. */
7755 if (GET_CODE (in) == PLUS
7756 && (GET_CODE (XEXP (in, 0)) == REG
7757 || GET_CODE (XEXP (in, 0)) == SUBREG
7758 || GET_CODE (XEXP (in, 0)) == MEM)
7759 && (GET_CODE (XEXP (in, 1)) == REG
7760 || GET_CODE (XEXP (in, 1)) == SUBREG
7761 || CONSTANT_P (XEXP (in, 1))
7762 || GET_CODE (XEXP (in, 1)) == MEM))
7764 /* We need to compute the sum of a register or a MEM and another
7765 register, constant, or MEM, and put it into the reload
7766 register. The best possible way of doing this is if the machine
7767 has a three-operand ADD insn that accepts the required operands.
7769 The simplest approach is to try to generate such an insn and see if it
7770 is recognized and matches its constraints. If so, it can be used.
7772 It might be better not to actually emit the insn unless it is valid,
7773 but we need to pass the insn as an operand to `recog' and
7774 `extract_insn' and it is simpler to emit and then delete the insn if
7775 not valid than to dummy things up. */
7777 rtx op0, op1, tem, insn;
7780 op0 = find_replacement (&XEXP (in, 0));
7781 op1 = find_replacement (&XEXP (in, 1));
7783 /* Since constraint checking is strict, commutativity won't be
7784 checked, so we need to do that here to avoid spurious failure
7785 if the add instruction is two-address and the second operand
7786 of the add is the same as the reload reg, which is frequently
7787 the case. If the insn would be A = B + A, rearrange it so
7788 it will be A = A + B as constrain_operands expects. */
7790 if (GET_CODE (XEXP (in, 1)) == REG
7791 && REGNO (out) == REGNO (XEXP (in, 1)))
7792 tem = op0, op0 = op1, op1 = tem;
7794 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7795 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7797 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7798 code = recog_memoized (insn);
7802 extract_insn (insn);
7803 /* We want constrain operands to treat this insn strictly in
7804 its validity determination, i.e., the way it would after reload
7806 if (constrain_operands (1))
7810 delete_insns_since (last);
7812 /* If that failed, we must use a conservative two-insn sequence.
7814 Use a move to copy one operand into the reload register. Prefer
7815 to reload a constant, MEM or pseudo since the move patterns can
7816 handle an arbitrary operand. If OP1 is not a constant, MEM or
7817 pseudo and OP1 is not a valid operand for an add instruction, then
7820 After reloading one of the operands into the reload register, add
7821 the reload register to the output register.
7823 If there is another way to do this for a specific machine, a
7824 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7827 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7829 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7830 || (GET_CODE (op1) == REG
7831 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7832 || (code != CODE_FOR_nothing
7833 && ! (*insn_operand_predicate[code][2]) (op1, insn_operand_mode[code][2])))
7834 tem = op0, op0 = op1, op1 = tem;
7836 gen_reload (out, op0, opnum, type);
7838 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7839 This fixes a problem on the 32K where the stack pointer cannot
7840 be used as an operand of an add insn. */
7842 if (rtx_equal_p (op0, op1))
7845 insn = emit_insn (gen_add2_insn (out, op1));
7847 /* If that failed, copy the address register to the reload register.
7848 Then add the constant to the reload register. */
7850 code = recog_memoized (insn);
7854 extract_insn (insn);
7855 /* We want constrain operands to treat this insn strictly in
7856 its validity determination, i.e., the way it would after reload
7858 if (constrain_operands (1))
7860 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7862 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7867 delete_insns_since (last);
7869 gen_reload (out, op1, opnum, type);
7870 insn = emit_insn (gen_add2_insn (out, op0));
7871 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7874 #ifdef SECONDARY_MEMORY_NEEDED
7875 /* If we need a memory location to do the move, do it that way. */
7876 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7877 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7878 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7879 REGNO_REG_CLASS (REGNO (out)),
7882 /* Get the memory to use and rewrite both registers to its mode. */
7883 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7885 if (GET_MODE (loc) != GET_MODE (out))
7886 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7888 if (GET_MODE (loc) != GET_MODE (in))
7889 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7891 gen_reload (loc, in, opnum, type);
7892 gen_reload (out, loc, opnum, type);
7896 /* If IN is a simple operand, use gen_move_insn. */
7897 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7898 emit_insn (gen_move_insn (out, in));
7900 #ifdef HAVE_reload_load_address
7901 else if (HAVE_reload_load_address)
7902 emit_insn (gen_reload_load_address (out, in));
7905 /* Otherwise, just write (set OUT IN) and hope for the best. */
7907 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7909 /* Return the first insn emitted.
7910 We can not just return get_last_insn, because there may have
7911 been multiple instructions emitted. Also note that gen_move_insn may
7912 emit more than one insn itself, so we can not assume that there is one
7913 insn emitted per emit_insn_before call. */
7915 return last ? NEXT_INSN (last) : get_insns ();
7918 /* Delete a previously made output-reload
7919 whose result we now believe is not needed.
7920 First we double-check.
7922 INSN is the insn now being processed.
7923 LAST_RELOAD_REG is the hard register number for which we want to delete
7924 the last output reload.
7925 J is the reload-number that originally used REG. The caller has made
7926 certain that reload J doesn't use REG any longer for input. */
7929 delete_output_reload (insn, j, last_reload_reg)
7932 int last_reload_reg;
7934 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7935 rtx reg = spill_reg_stored_to[last_reload_reg];
7938 int n_inherited = 0;
7942 /* Get the raw pseudo-register referred to. */
7944 while (GET_CODE (reg) == SUBREG)
7945 reg = SUBREG_REG (reg);
7946 substed = reg_equiv_memory_loc[REGNO (reg)];
7948 /* This is unsafe if the operand occurs more often in the current
7949 insn than it is inherited. */
7950 for (k = n_reloads - 1; k >= 0; k--)
7952 rtx reg2 = reload_in[k];
7955 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7956 reg2 = reload_in_reg[k];
7958 if (reload_out[k] && ! reload_out_reg[k])
7959 reg2 = XEXP (reload_in_reg[k], 0);
7961 while (GET_CODE (reg2) == SUBREG)
7962 reg2 = SUBREG_REG (reg2);
7963 if (rtx_equal_p (reg2, reg))
7965 if (reload_inherited[k] || reload_override_in[k] || k == j)
7968 reg2 = reload_out_reg[k];
7971 while (GET_CODE (reg2) == SUBREG)
7972 reg2 = XEXP (reg2, 0);
7973 if (rtx_equal_p (reg2, reg))
7980 n_occurrences = count_occurrences (PATTERN (insn), reg);
7982 n_occurrences += count_occurrences (PATTERN (insn), substed);
7983 if (n_occurrences > n_inherited)
7986 /* If the pseudo-reg we are reloading is no longer referenced
7987 anywhere between the store into it and here,
7988 and no jumps or labels intervene, then the value can get
7989 here through the reload reg alone.
7990 Otherwise, give up--return. */
7991 for (i1 = NEXT_INSN (output_reload_insn);
7992 i1 != insn; i1 = NEXT_INSN (i1))
7994 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7996 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7997 && reg_mentioned_p (reg, PATTERN (i1)))
7999 /* If this is USE in front of INSN, we only have to check that
8000 there are no more references than accounted for by inheritance. */
8001 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
8003 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8004 i1 = NEXT_INSN (i1);
8006 if (n_occurrences <= n_inherited && i1 == insn)
8012 /* The caller has already checked that REG dies or is set in INSN.
8013 It has also checked that we are optimizing, and thus some inaccurancies
8014 in the debugging information are acceptable.
8015 So we could just delete output_reload_insn.
8016 But in some cases we can improve the debugging information without
8017 sacrificing optimization - maybe even improving the code:
8018 See if the pseudo reg has been completely replaced
8019 with reload regs. If so, delete the store insn
8020 and forget we had a stack slot for the pseudo. */
8021 if (reload_out[j] != reload_in[j]
8022 && REG_N_DEATHS (REGNO (reg)) == 1
8023 && REG_N_SETS (REGNO (reg)) == 1
8024 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8025 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8029 /* We know that it was used only between here
8030 and the beginning of the current basic block.
8031 (We also know that the last use before INSN was
8032 the output reload we are thinking of deleting, but never mind that.)
8033 Search that range; see if any ref remains. */
8034 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8036 rtx set = single_set (i2);
8038 /* Uses which just store in the pseudo don't count,
8039 since if they are the only uses, they are dead. */
8040 if (set != 0 && SET_DEST (set) == reg)
8042 if (GET_CODE (i2) == CODE_LABEL
8043 || GET_CODE (i2) == JUMP_INSN)
8045 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
8046 && reg_mentioned_p (reg, PATTERN (i2)))
8048 /* Some other ref remains; just delete the output reload we
8050 delete_address_reloads (output_reload_insn, insn);
8051 PUT_CODE (output_reload_insn, NOTE);
8052 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8053 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8058 /* Delete the now-dead stores into this pseudo. */
8059 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8061 rtx set = single_set (i2);
8063 if (set != 0 && SET_DEST (set) == reg)
8065 delete_address_reloads (i2, insn);
8066 /* This might be a basic block head,
8067 thus don't use delete_insn. */
8068 PUT_CODE (i2, NOTE);
8069 NOTE_SOURCE_FILE (i2) = 0;
8070 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8072 if (GET_CODE (i2) == CODE_LABEL
8073 || GET_CODE (i2) == JUMP_INSN)
8077 /* For the debugging info,
8078 say the pseudo lives in this reload reg. */
8079 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
8080 alter_reg (REGNO (reg), -1);
8082 delete_address_reloads (output_reload_insn, insn);
8083 PUT_CODE (output_reload_insn, NOTE);
8084 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8085 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8089 /* We are going to delete DEAD_INSN. Recursively delete loads of
8090 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8091 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8093 delete_address_reloads (dead_insn, current_insn)
8094 rtx dead_insn, current_insn;
8096 rtx set = single_set (dead_insn);
8097 rtx set2, dst, prev, next;
8100 rtx dst = SET_DEST (set);
8101 if (GET_CODE (dst) == MEM)
8102 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8104 /* If we deleted the store from a reloaded post_{in,de}c expression,
8105 we can delete the matching adds. */
8106 prev = PREV_INSN (dead_insn);
8107 next = NEXT_INSN (dead_insn);
8108 if (! prev || ! next)
8110 set = single_set (next);
8111 set2 = single_set (prev);
8113 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8114 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8115 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8117 dst = SET_DEST (set);
8118 if (! rtx_equal_p (dst, SET_DEST (set2))
8119 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8120 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8121 || (INTVAL (XEXP (SET_SRC (set), 1))
8122 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8128 /* Subfunction of delete_address_reloads: process registers found in X. */
8130 delete_address_reloads_1 (dead_insn, x, current_insn)
8131 rtx dead_insn, x, current_insn;
8133 rtx prev, set, dst, i2;
8135 enum rtx_code code = GET_CODE (x);
8139 char *fmt= GET_RTX_FORMAT (code);
8140 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8143 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8144 else if (fmt[i] == 'E')
8146 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8147 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8154 if (spill_reg_order[REGNO (x)] < 0)
8157 /* Scan backwards for the insn that sets x. This might be a way back due
8159 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8161 code = GET_CODE (prev);
8162 if (code == CODE_LABEL || code == JUMP_INSN)
8164 if (GET_RTX_CLASS (code) != 'i')
8166 if (reg_set_p (x, PATTERN (prev)))
8168 if (reg_referenced_p (x, PATTERN (prev)))
8171 if (! prev || INSN_UID (prev) < reload_first_uid)
8173 /* Check that PREV only sets the reload register. */
8174 set = single_set (prev);
8177 dst = SET_DEST (set);
8178 if (GET_CODE (dst) != REG
8179 || ! rtx_equal_p (dst, x))
8181 if (! reg_set_p (dst, PATTERN (dead_insn)))
8183 /* Check if DST was used in a later insn -
8184 it might have been inherited. */
8185 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8187 if (GET_CODE (i2) == CODE_LABEL)
8189 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8191 if (reg_referenced_p (dst, PATTERN (i2)))
8193 /* If there is a reference to the register in the current insn,
8194 it might be loaded in a non-inherited reload. If no other
8195 reload uses it, that means the register is set before
8197 if (i2 == current_insn)
8199 for (j = n_reloads - 1; j >= 0; j--)
8200 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8201 || reload_override_in[j] == dst)
8203 for (j = n_reloads - 1; j >= 0; j--)
8204 if (reload_in[j] && reload_reg_rtx[j] == dst)
8211 if (GET_CODE (i2) == JUMP_INSN)
8213 /* If DST is still live at CURRENT_INSN, check if it is used for
8214 any reload. Note that even if CURRENT_INSN sets DST, we still
8215 have to check the reloads. */
8216 if (i2 == current_insn)
8218 for (j = n_reloads - 1; j >= 0; j--)
8219 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8220 || reload_override_in[j] == dst)
8222 /* ??? We can't finish the loop here, because dst might be
8223 allocated to a pseudo in this block if no reload in this
8224 block needs any of the clsses containing DST - see
8225 spill_hard_reg. There is no easy way to tell this, so we
8226 have to scan till the end of the basic block. */
8228 if (reg_set_p (dst, PATTERN (i2)))
8232 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8233 reg_reloaded_contents[REGNO (dst)] = -1;
8234 /* Can't use delete_insn here because PREV might be a basic block head. */
8235 PUT_CODE (prev, NOTE);
8236 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8237 NOTE_SOURCE_FILE (prev) = 0;
8240 /* Output reload-insns to reload VALUE into RELOADREG.
8241 VALUE is an autoincrement or autodecrement RTX whose operand
8242 is a register or memory location;
8243 so reloading involves incrementing that location.
8244 IN is either identical to VALUE, or some cheaper place to reload from.
8246 INC_AMOUNT is the number to increment or decrement by (always positive).
8247 This cannot be deduced from VALUE.
8249 Return the instruction that stores into RELOADREG. */
8252 inc_for_reload (reloadreg, in, value, inc_amount)
8257 /* REG or MEM to be copied and incremented. */
8258 rtx incloc = XEXP (value, 0);
8259 /* Nonzero if increment after copying. */
8260 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8266 rtx real_in = in == value ? XEXP (in, 0) : in;
8268 /* No hard register is equivalent to this register after
8269 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8270 we could inc/dec that register as well (maybe even using it for
8271 the source), but I'm not sure it's worth worrying about. */
8272 if (GET_CODE (incloc) == REG)
8273 reg_last_reload_reg[REGNO (incloc)] = 0;
8275 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8276 inc_amount = - inc_amount;
8278 inc = GEN_INT (inc_amount);
8280 /* If this is post-increment, first copy the location to the reload reg. */
8281 if (post && real_in != reloadreg)
8282 emit_insn (gen_move_insn (reloadreg, real_in));
8286 /* See if we can directly increment INCLOC. Use a method similar to
8287 that in gen_reload. */
8289 last = get_last_insn ();
8290 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8291 gen_rtx_PLUS (GET_MODE (incloc),
8294 code = recog_memoized (add_insn);
8297 extract_insn (add_insn);
8298 if (constrain_operands (1))
8300 /* If this is a pre-increment and we have incremented the value
8301 where it lives, copy the incremented value to RELOADREG to
8302 be used as an address. */
8305 emit_insn (gen_move_insn (reloadreg, incloc));
8310 delete_insns_since (last);
8313 /* If couldn't do the increment directly, must increment in RELOADREG.
8314 The way we do this depends on whether this is pre- or post-increment.
8315 For pre-increment, copy INCLOC to the reload register, increment it
8316 there, then save back. */
8320 if (in != reloadreg)
8321 emit_insn (gen_move_insn (reloadreg, real_in));
8322 emit_insn (gen_add2_insn (reloadreg, inc));
8323 store = emit_insn (gen_move_insn (incloc, reloadreg));
8328 Because this might be a jump insn or a compare, and because RELOADREG
8329 may not be available after the insn in an input reload, we must do
8330 the incrementation before the insn being reloaded for.
8332 We have already copied IN to RELOADREG. Increment the copy in
8333 RELOADREG, save that back, then decrement RELOADREG so it has
8334 the original value. */
8336 emit_insn (gen_add2_insn (reloadreg, inc));
8337 store = emit_insn (gen_move_insn (incloc, reloadreg));
8338 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8344 /* Return 1 if we are certain that the constraint-string STRING allows
8345 the hard register REG. Return 0 if we can't be sure of this. */
8348 constraint_accepts_reg_p (string, reg)
8353 int regno = true_regnum (reg);
8356 /* Initialize for first alternative. */
8358 /* Check that each alternative contains `g' or `r'. */
8360 switch (c = *string++)
8363 /* If an alternative lacks `g' or `r', we lose. */
8366 /* If an alternative lacks `g' or `r', we lose. */
8369 /* Initialize for next alternative. */
8374 /* Any general reg wins for this alternative. */
8375 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8379 /* Any reg in specified class wins for this alternative. */
8381 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8383 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8389 /* Return the number of places FIND appears within X, but don't count
8390 an occurrence if some SET_DEST is FIND. */
8393 count_occurrences (x, find)
8394 register rtx x, find;
8397 register enum rtx_code code;
8398 register char *format_ptr;
8406 code = GET_CODE (x);
8421 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8425 if (SET_DEST (x) == find)
8426 return count_occurrences (SET_SRC (x), find);
8433 format_ptr = GET_RTX_FORMAT (code);
8436 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8438 switch (*format_ptr++)
8441 count += count_occurrences (XEXP (x, i), find);
8445 if (XVEC (x, i) != NULL)
8447 for (j = 0; j < XVECLEN (x, i); j++)
8448 count += count_occurrences (XVECEXP (x, i, j), find);
8456 /* This array holds values which are equivalent to a hard register
8457 during reload_cse_regs. Each array element is an EXPR_LIST of
8458 values. Each time a hard register is set, we set the corresponding
8459 array element to the value. Each time a hard register is copied
8460 into memory, we add the memory location to the corresponding array
8461 element. We don't store values or memory addresses with side
8462 effects in this array.
8464 If the value is a CONST_INT, then the mode of the containing
8465 EXPR_LIST is the mode in which that CONST_INT was referenced.
8467 We sometimes clobber a specific entry in a list. In that case, we
8468 just set XEXP (list-entry, 0) to 0. */
8470 static rtx *reg_values;
8472 /* This is a preallocated REG rtx which we use as a temporary in
8473 reload_cse_invalidate_regno, so that we don't need to allocate a
8474 new one each time through a loop in that function. */
8476 static rtx invalidate_regno_rtx;
8478 /* Invalidate any entries in reg_values which depend on REGNO,
8479 including those for REGNO itself. This is called if REGNO is
8480 changing. If CLOBBER is true, then always forget anything we
8481 currently know about REGNO. MODE is the mode of the assignment to
8482 REGNO, which is used to determine how many hard registers are being
8483 changed. If MODE is VOIDmode, then only REGNO is being changed;
8484 this is used when invalidating call clobbered registers across a
8488 reload_cse_invalidate_regno (regno, mode, clobber)
8490 enum machine_mode mode;
8496 /* Our callers don't always go through true_regnum; we may see a
8497 pseudo-register here from a CLOBBER or the like. We probably
8498 won't ever see a pseudo-register that has a real register number,
8499 for we check anyhow for safety. */
8500 if (regno >= FIRST_PSEUDO_REGISTER)
8501 regno = reg_renumber[regno];
8505 if (mode == VOIDmode)
8506 endregno = regno + 1;
8508 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8511 for (i = regno; i < endregno; i++)
8514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8518 for (x = reg_values[i]; x; x = XEXP (x, 1))
8520 if (XEXP (x, 0) != 0
8521 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8523 /* If this is the only entry on the list, clear
8524 reg_values[i]. Otherwise, just clear this entry on
8526 if (XEXP (x, 1) == 0 && x == reg_values[i])
8536 /* We must look at earlier registers, in case REGNO is part of a
8537 multi word value but is not the first register. If an earlier
8538 register has a value in a mode which overlaps REGNO, then we must
8539 invalidate that earlier register. Note that we do not need to
8540 check REGNO or later registers (we must not check REGNO itself,
8541 because we would incorrectly conclude that there was a conflict). */
8543 for (i = 0; i < regno; i++)
8547 for (x = reg_values[i]; x; x = XEXP (x, 1))
8549 if (XEXP (x, 0) != 0)
8551 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8552 REGNO (invalidate_regno_rtx) = i;
8553 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8556 reload_cse_invalidate_regno (i, VOIDmode, 1);
8564 /* The memory at address MEM_BASE is being changed.
8565 Return whether this change will invalidate VAL. */
8568 reload_cse_mem_conflict_p (mem_base, val)
8576 code = GET_CODE (val);
8579 /* Get rid of a few simple cases quickly. */
8592 if (GET_MODE (mem_base) == BLKmode
8593 || GET_MODE (val) == BLKmode)
8595 if (anti_dependence (val, mem_base))
8597 /* The address may contain nested MEMs. */
8604 fmt = GET_RTX_FORMAT (code);
8606 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8610 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8613 else if (fmt[i] == 'E')
8617 for (j = 0; j < XVECLEN (val, i); j++)
8618 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8626 /* Invalidate any entries in reg_values which are changed because of a
8627 store to MEM_RTX. If this is called because of a non-const call
8628 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8631 reload_cse_invalidate_mem (mem_rtx)
8636 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8640 for (x = reg_values[i]; x; x = XEXP (x, 1))
8642 if (XEXP (x, 0) != 0
8643 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8645 /* If this is the only entry on the list, clear
8646 reg_values[i]. Otherwise, just clear this entry on
8648 if (XEXP (x, 1) == 0 && x == reg_values[i])
8659 /* Invalidate DEST, which is being assigned to or clobbered. The
8660 second parameter exists so that this function can be passed to
8661 note_stores; it is ignored. */
8664 reload_cse_invalidate_rtx (dest, ignore)
8666 rtx ignore ATTRIBUTE_UNUSED;
8668 while (GET_CODE (dest) == STRICT_LOW_PART
8669 || GET_CODE (dest) == SIGN_EXTRACT
8670 || GET_CODE (dest) == ZERO_EXTRACT
8671 || GET_CODE (dest) == SUBREG)
8672 dest = XEXP (dest, 0);
8674 if (GET_CODE (dest) == REG)
8675 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8676 else if (GET_CODE (dest) == MEM)
8677 reload_cse_invalidate_mem (dest);
8680 /* Do a very simple CSE pass over the hard registers.
8682 This function detects no-op moves where we happened to assign two
8683 different pseudo-registers to the same hard register, and then
8684 copied one to the other. Reload will generate a useless
8685 instruction copying a register to itself.
8687 This function also detects cases where we load a value from memory
8688 into two different registers, and (if memory is more expensive than
8689 registers) changes it to simply copy the first register into the
8692 Another optimization is performed that scans the operands of each
8693 instruction to see whether the value is already available in a
8694 hard register. It then replaces the operand with the hard register
8695 if possible, much like an optional reload would. */
8698 reload_cse_regs_1 (first)
8706 init_alias_analysis ();
8708 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8709 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8711 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8712 free them when we are done. */
8713 push_obstacks (&reload_obstack, &reload_obstack);
8714 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8716 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8717 memory for a non-const call instruction. */
8718 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8720 /* This is used in reload_cse_invalidate_regno to avoid consing a
8721 new REG in a loop in that function. */
8722 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8724 for (insn = first; insn; insn = NEXT_INSN (insn))
8728 if (GET_CODE (insn) == CODE_LABEL)
8730 /* Forget all the register values at a code label. We don't
8731 try to do anything clever around jumps. */
8732 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8738 #ifdef NON_SAVING_SETJMP
8739 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8740 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8742 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8749 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8752 /* If this is a call instruction, forget anything stored in a
8753 call clobbered register, or, if this is not a const call, in
8755 if (GET_CODE (insn) == CALL_INSN)
8757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8758 if (call_used_regs[i])
8759 reload_cse_invalidate_regno (i, VOIDmode, 1);
8761 if (! CONST_CALL_P (insn))
8762 reload_cse_invalidate_mem (callmem);
8766 /* Forget all the register values at a volatile asm. */
8767 if (GET_CODE (insn) == INSN
8768 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8769 && MEM_VOLATILE_P (PATTERN (insn)))
8770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8773 body = PATTERN (insn);
8774 if (GET_CODE (body) == SET)
8777 if (reload_cse_noop_set_p (body, insn))
8779 /* If this sets the return value of the function, we must keep
8780 a USE around, in case this is in a different basic block
8781 than the final USE. Otherwise, we could loose important
8782 register lifeness information on SMALL_REGISTER_CLASSES
8783 machines, where return registers might be used as spills:
8784 subsequent passes assume that spill registers are dead at
8785 the end of a basic block. */
8786 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8789 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8790 INSN_CODE (insn) = -1;
8791 REG_NOTES (insn) = NULL_RTX;
8792 push_obstacks (&reload_obstack, &reload_obstack);
8796 PUT_CODE (insn, NOTE);
8797 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8798 NOTE_SOURCE_FILE (insn) = 0;
8801 /* We're done with this insn. */
8805 /* It's not a no-op, but we can try to simplify it. */
8806 count += reload_cse_simplify_set (body, insn);
8809 apply_change_group ();
8811 reload_cse_simplify_operands (insn);
8813 reload_cse_record_set (body, body);
8815 else if (GET_CODE (body) == PARALLEL)
8818 rtx value = NULL_RTX;
8820 /* If every action in a PARALLEL is a noop, we can delete
8821 the entire PARALLEL. */
8822 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8824 rtx part = XVECEXP (body, 0, i);
8825 if (GET_CODE (part) == SET)
8827 if (! reload_cse_noop_set_p (part, insn))
8829 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8833 value = SET_DEST (part);
8836 else if (GET_CODE (part) != CLOBBER)
8844 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8845 INSN_CODE (insn) = -1;
8846 REG_NOTES (insn) = NULL_RTX;
8847 push_obstacks (&reload_obstack, &reload_obstack);
8851 PUT_CODE (insn, NOTE);
8852 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8853 NOTE_SOURCE_FILE (insn) = 0;
8856 /* We're done with this insn. */
8860 /* It's not a no-op, but we can try to simplify it. */
8861 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8862 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8863 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8866 apply_change_group ();
8868 reload_cse_simplify_operands (insn);
8870 /* Look through the PARALLEL and record the values being
8871 set, if possible. Also handle any CLOBBERs. */
8872 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8874 rtx x = XVECEXP (body, 0, i);
8876 if (GET_CODE (x) == SET)
8877 reload_cse_record_set (x, body);
8879 note_stores (x, reload_cse_invalidate_rtx);
8883 note_stores (body, reload_cse_invalidate_rtx);
8886 /* Clobber any registers which appear in REG_INC notes. We
8887 could keep track of the changes to their values, but it is
8888 unlikely to help. */
8892 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8893 if (REG_NOTE_KIND (x) == REG_INC)
8894 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8898 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8899 after we have processed the insn. */
8900 if (GET_CODE (insn) == CALL_INSN)
8904 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8905 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8906 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8910 /* Free all the temporary structures we created, and go back to the
8911 regular obstacks. */
8912 obstack_free (&reload_obstack, firstobj);
8916 /* Call cse / combine like post-reload optimization phases.
8917 FIRST is the first instruction. */
8919 reload_cse_regs (first)
8922 reload_cse_regs_1 (first);
8924 reload_cse_move2add (first);
8925 if (flag_expensive_optimizations)
8926 reload_cse_regs_1 (first);
8929 /* Return whether the values known for REGNO are equal to VAL. MODE
8930 is the mode of the object that VAL is being copied to; this matters
8931 if VAL is a CONST_INT. */
8934 reload_cse_regno_equal_p (regno, val, mode)
8937 enum machine_mode mode;
8944 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8945 if (XEXP (x, 0) != 0
8946 && rtx_equal_p (XEXP (x, 0), val)
8947 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8948 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8949 && (GET_CODE (val) != CONST_INT
8950 || mode == GET_MODE (x)
8951 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8952 /* On a big endian machine if the value spans more than
8953 one register then this register holds the high part of
8954 it and we can't use it.
8956 ??? We should also compare with the high part of the
8958 && !(WORDS_BIG_ENDIAN
8959 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8960 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8961 GET_MODE_BITSIZE (GET_MODE (x))))))
8967 /* See whether a single set is a noop. SET is the set instruction we
8968 are should check, and INSN is the instruction from which it came. */
8971 reload_cse_noop_set_p (set, insn)
8976 enum machine_mode dest_mode;
8980 src = SET_SRC (set);
8981 dest = SET_DEST (set);
8982 dest_mode = GET_MODE (dest);
8984 if (side_effects_p (src))
8987 dreg = true_regnum (dest);
8988 sreg = true_regnum (src);
8990 /* Check for setting a register to itself. In this case, we don't
8991 have to worry about REG_DEAD notes. */
8992 if (dreg >= 0 && dreg == sreg)
8998 /* Check for setting a register to itself. */
9002 /* Check for setting a register to a value which we already know
9003 is in the register. */
9004 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
9007 /* Check for setting a register DREG to another register SREG
9008 where SREG is equal to a value which is already in DREG. */
9013 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9017 if (XEXP (x, 0) == 0)
9020 if (dest_mode == GET_MODE (x))
9022 else if (GET_MODE_BITSIZE (dest_mode)
9023 < GET_MODE_BITSIZE (GET_MODE (x)))
9024 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9029 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
9037 else if (GET_CODE (dest) == MEM)
9039 /* Check for storing a register to memory when we know that the
9040 register is equivalent to the memory location. */
9042 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
9043 && ! side_effects_p (dest))
9050 /* Try to simplify a single SET instruction. SET is the set pattern.
9051 INSN is the instruction it came from.
9052 This function only handles one case: if we set a register to a value
9053 which is not a register, we try to find that value in some other register
9054 and change the set into a register copy. */
9057 reload_cse_simplify_set (set, insn)
9063 enum machine_mode dest_mode;
9064 enum reg_class dclass;
9067 dreg = true_regnum (SET_DEST (set));
9071 src = SET_SRC (set);
9072 if (side_effects_p (src) || true_regnum (src) >= 0)
9075 dclass = REGNO_REG_CLASS (dreg);
9077 /* If memory loads are cheaper than register copies, don't change them. */
9078 if (GET_CODE (src) == MEM
9079 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9082 /* If the constant is cheaper than a register, don't change it. */
9083 if (CONSTANT_P (src)
9084 && rtx_cost (src, SET) < 2)
9087 dest_mode = GET_MODE (SET_DEST (set));
9088 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9091 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9092 && reload_cse_regno_equal_p (i, src, dest_mode))
9096 /* Pop back to the real obstacks while changing the insn. */
9099 validated = validate_change (insn, &SET_SRC (set),
9100 gen_rtx_REG (dest_mode, i), 1);
9102 /* Go back to the obstack we are using for temporary
9104 push_obstacks (&reload_obstack, &reload_obstack);
9113 /* Try to replace operands in INSN with equivalent values that are already
9114 in registers. This can be viewed as optional reloading.
9116 For each non-register operand in the insn, see if any hard regs are
9117 known to be equivalent to that operand. Record the alternatives which
9118 can accept these hard registers. Among all alternatives, select the
9119 ones which are better or equal to the one currently matching, where
9120 "better" is in terms of '?' and '!' constraints. Among the remaining
9121 alternatives, select the one which replaces most operands with
9125 reload_cse_simplify_operands (insn)
9128 #ifdef REGISTER_CONSTRAINTS
9131 const char *constraints[MAX_RECOG_OPERANDS];
9133 /* Vector recording how bad an alternative is. */
9134 int *alternative_reject;
9135 /* Vector recording how many registers can be introduced by choosing
9136 this alternative. */
9137 int *alternative_nregs;
9138 /* Array of vectors recording, for each operand and each alternative,
9139 which hard register to substitute, or -1 if the operand should be
9141 int *op_alt_regno[MAX_RECOG_OPERANDS];
9142 /* Array of alternatives, sorted in order of decreasing desirability. */
9143 int *alternative_order;
9144 rtx reg = gen_rtx_REG (VOIDmode, -1);
9146 extract_insn (insn);
9148 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9151 /* Figure out which alternative currently matches. */
9152 if (! constrain_operands (1))
9153 fatal_insn_not_found (insn);
9155 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9156 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9157 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9158 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9159 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9161 for (i = 0; i < recog_n_operands; i++)
9163 enum machine_mode mode;
9167 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9168 for (j = 0; j < recog_n_alternatives; j++)
9169 op_alt_regno[i][j] = -1;
9171 p = constraints[i] = recog_constraints[i];
9172 mode = recog_operand_mode[i];
9174 /* Add the reject values for each alternative given by the constraints
9175 for this operand. */
9183 alternative_reject[j] += 3;
9185 alternative_reject[j] += 300;
9188 /* We won't change operands which are already registers. We
9189 also don't want to modify output operands. */
9190 regno = true_regnum (recog_operand[i]);
9192 || constraints[i][0] == '='
9193 || constraints[i][0] == '+')
9196 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9198 int class = (int) NO_REGS;
9200 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9203 REGNO (reg) = regno;
9204 PUT_MODE (reg, mode);
9206 /* We found a register equal to this operand. Now look for all
9207 alternatives that can accept this register and have not been
9208 assigned a register they can use yet. */
9217 case '=': case '+': case '?':
9218 case '#': case '&': case '!':
9220 case '0': case '1': case '2': case '3': case '4':
9221 case 'm': case '<': case '>': case 'V': case 'o':
9222 case 'E': case 'F': case 'G': case 'H':
9223 case 's': case 'i': case 'n':
9224 case 'I': case 'J': case 'K': case 'L':
9225 case 'M': case 'N': case 'O': case 'P':
9226 #ifdef EXTRA_CONSTRAINT
9227 case 'Q': case 'R': case 'S': case 'T': case 'U':
9230 /* These don't say anything we care about. */
9234 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9239 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9242 case ',': case '\0':
9243 /* See if REGNO fits this alternative, and set it up as the
9244 replacement register if we don't have one for this
9245 alternative yet and the operand being replaced is not
9246 a cheap CONST_INT. */
9247 if (op_alt_regno[i][j] == -1
9248 && reg_fits_class_p (reg, class, 0, mode)
9249 && (GET_CODE (recog_operand[i]) != CONST_INT
9250 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9252 alternative_nregs[j]++;
9253 op_alt_regno[i][j] = regno;
9265 /* Record all alternatives which are better or equal to the currently
9266 matching one in the alternative_order array. */
9267 for (i = j = 0; i < recog_n_alternatives; i++)
9268 if (alternative_reject[i] <= alternative_reject[which_alternative])
9269 alternative_order[j++] = i;
9270 recog_n_alternatives = j;
9272 /* Sort it. Given a small number of alternatives, a dumb algorithm
9273 won't hurt too much. */
9274 for (i = 0; i < recog_n_alternatives - 1; i++)
9277 int best_reject = alternative_reject[alternative_order[i]];
9278 int best_nregs = alternative_nregs[alternative_order[i]];
9281 for (j = i + 1; j < recog_n_alternatives; j++)
9283 int this_reject = alternative_reject[alternative_order[j]];
9284 int this_nregs = alternative_nregs[alternative_order[j]];
9286 if (this_reject < best_reject
9287 || (this_reject == best_reject && this_nregs < best_nregs))
9290 best_reject = this_reject;
9291 best_nregs = this_nregs;
9295 tmp = alternative_order[best];
9296 alternative_order[best] = alternative_order[i];
9297 alternative_order[i] = tmp;
9300 /* Substitute the operands as determined by op_alt_regno for the best
9302 j = alternative_order[0];
9304 /* Pop back to the real obstacks while changing the insn. */
9307 for (i = 0; i < recog_n_operands; i++)
9309 enum machine_mode mode = recog_operand_mode[i];
9310 if (op_alt_regno[i][j] == -1)
9313 validate_change (insn, recog_operand_loc[i],
9314 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9317 for (i = recog_n_dups - 1; i >= 0; i--)
9319 int op = recog_dup_num[i];
9320 enum machine_mode mode = recog_operand_mode[op];
9322 if (op_alt_regno[op][j] == -1)
9325 validate_change (insn, recog_dup_loc[i],
9326 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9329 /* Go back to the obstack we are using for temporary
9331 push_obstacks (&reload_obstack, &reload_obstack);
9333 return apply_change_group ();
9339 /* These two variables are used to pass information from
9340 reload_cse_record_set to reload_cse_check_clobber. */
9342 static int reload_cse_check_clobbered;
9343 static rtx reload_cse_check_src;
9345 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9346 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9347 second argument, which is passed by note_stores, is ignored. */
9350 reload_cse_check_clobber (dest, ignore)
9352 rtx ignore ATTRIBUTE_UNUSED;
9354 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9355 reload_cse_check_clobbered = 1;
9358 /* Record the result of a SET instruction. SET is the set pattern.
9359 BODY is the pattern of the insn that it came from. */
9362 reload_cse_record_set (set, body)
9368 enum machine_mode dest_mode;
9370 dest = SET_DEST (set);
9371 src = SET_SRC (set);
9372 dreg = true_regnum (dest);
9373 sreg = true_regnum (src);
9374 dest_mode = GET_MODE (dest);
9376 /* Some machines don't define AUTO_INC_DEC, but they still use push
9377 instructions. We need to catch that case here in order to
9378 invalidate the stack pointer correctly. Note that invalidating
9379 the stack pointer is different from invalidating DEST. */
9381 while (GET_CODE (x) == SUBREG
9382 || GET_CODE (x) == ZERO_EXTRACT
9383 || GET_CODE (x) == SIGN_EXTRACT
9384 || GET_CODE (x) == STRICT_LOW_PART)
9386 if (push_operand (x, GET_MODE (x)))
9388 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9389 reload_cse_invalidate_rtx (dest, NULL_RTX);
9393 /* We can only handle an assignment to a register, or a store of a
9394 register to a memory location. For other cases, we just clobber
9395 the destination. We also have to just clobber if there are side
9396 effects in SRC or DEST. */
9397 if ((dreg < 0 && GET_CODE (dest) != MEM)
9398 || side_effects_p (src)
9399 || side_effects_p (dest))
9401 reload_cse_invalidate_rtx (dest, NULL_RTX);
9406 /* We don't try to handle values involving CC, because it's a pain
9407 to keep track of when they have to be invalidated. */
9408 if (reg_mentioned_p (cc0_rtx, src)
9409 || reg_mentioned_p (cc0_rtx, dest))
9411 reload_cse_invalidate_rtx (dest, NULL_RTX);
9416 /* If BODY is a PARALLEL, then we need to see whether the source of
9417 SET is clobbered by some other instruction in the PARALLEL. */
9418 if (GET_CODE (body) == PARALLEL)
9422 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9426 x = XVECEXP (body, 0, i);
9430 reload_cse_check_clobbered = 0;
9431 reload_cse_check_src = src;
9432 note_stores (x, reload_cse_check_clobber);
9433 if (reload_cse_check_clobbered)
9435 reload_cse_invalidate_rtx (dest, NULL_RTX);
9445 /* This is an assignment to a register. Update the value we
9446 have stored for the register. */
9451 /* This is a copy from one register to another. Any values
9452 which were valid for SREG are now valid for DREG. If the
9453 mode changes, we use gen_lowpart_common to extract only
9454 the part of the value that is copied. */
9455 reg_values[dreg] = 0;
9456 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9460 if (XEXP (x, 0) == 0)
9462 if (dest_mode == GET_MODE (XEXP (x, 0)))
9464 else if (GET_MODE_BITSIZE (dest_mode)
9465 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9468 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9470 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9475 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9477 /* We've changed DREG, so invalidate any values held by other
9478 registers that depend upon it. */
9479 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9481 /* If this assignment changes more than one hard register,
9482 forget anything we know about the others. */
9483 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9484 reg_values[dreg + i] = 0;
9486 else if (GET_CODE (dest) == MEM)
9488 /* Invalidate conflicting memory locations. */
9489 reload_cse_invalidate_mem (dest);
9491 /* If we're storing a register to memory, add DEST to the list
9493 if (sreg >= 0 && ! side_effects_p (dest))
9494 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9499 /* We should have bailed out earlier. */
9504 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9506 This code might also be useful when reload gave up on reg+reg addresssing
9507 because of clashes between the return register and INDEX_REG_CLASS. */
9509 /* The maximum number of uses of a register we can keep track of to
9510 replace them with reg+reg addressing. */
9511 #define RELOAD_COMBINE_MAX_USES 6
9513 /* INSN is the insn where a register has ben used, and USEP points to the
9514 location of the register within the rtl. */
9515 struct reg_use { rtx insn, *usep; };
9517 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9518 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9519 indicates where it becomes live again.
9520 Otherwise, USE_INDEX is the index of the last encountered use of the
9521 register (which is first among these we have seen since we scan backwards),
9522 OFFSET contains the constant offset that is added to the register in
9523 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9524 last, of these uses.
9525 STORE_RUID is always meaningful if we only want to use a value in a
9526 register in a different place: it denotes the next insn in the insn
9527 stream (i.e. the last ecountered) that sets or clobbers the register. */
9530 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9535 } reg_state[FIRST_PSEUDO_REGISTER];
9537 /* Reverse linear uid. This is increased in reload_combine while scanning
9538 the instructions from last to first. It is used to set last_label_ruid
9539 and the store_ruid / use_ruid fields in reg_state. */
9540 static int reload_combine_ruid;
9542 #define LABEL_LIVE(LABEL) \
9543 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9549 int first_index_reg = 1, last_index_reg = 0;
9551 int last_label_ruid;
9552 int min_labelno, n_labels;
9553 HARD_REG_SET ever_live_at_start, *label_live;
9555 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9556 reload has already used it where appropriate, so there is no use in
9557 trying to generate it now. */
9558 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9561 /* To avoid wasting too much time later searching for an index register,
9562 determine the minimum and maximum index register numbers. */
9563 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9565 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9567 if (! last_index_reg)
9569 first_index_reg = i;
9572 /* If no index register is available, we can quit now. */
9573 if (first_index_reg > last_index_reg)
9576 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9577 information is a bit fuzzy immediately after reload, but it's
9578 still good enough to determine which registers are live at a jump
9580 min_labelno = get_first_label_num ();
9581 n_labels = max_label_num () - min_labelno;
9582 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9583 CLEAR_HARD_REG_SET (ever_live_at_start);
9584 for (i = n_basic_blocks - 1; i >= 0; i--)
9586 insn = BLOCK_HEAD (i);
9587 if (GET_CODE (insn) == CODE_LABEL)
9591 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9592 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9593 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9594 IOR_HARD_REG_SET (ever_live_at_start, live);
9598 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9599 last_label_ruid = reload_combine_ruid = 0;
9600 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9602 reg_state[i].store_ruid = reload_combine_ruid;
9604 reg_state[i].use_index = -1;
9606 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9609 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9613 /* We cannot do our optimization across labels. Invalidating all the use
9614 information we have would be costly, so we just note where the label
9615 is and then later disable any optimization that would cross it. */
9616 if (GET_CODE (insn) == CODE_LABEL)
9617 last_label_ruid = reload_combine_ruid;
9618 if (GET_CODE (insn) == BARRIER)
9620 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9621 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9623 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9625 reload_combine_ruid++;
9627 /* Look for (set (REGX) (CONST_INT))
9628 (set (REGX) (PLUS (REGX) (REGY)))
9630 ... (MEM (REGX)) ...
9632 (set (REGZ) (CONST_INT))
9634 ... (MEM (PLUS (REGZ) (REGY)))... .
9636 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9637 and that we know all uses of REGX before it dies. */
9638 set = single_set (insn);
9640 && GET_CODE (SET_DEST (set)) == REG
9641 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9642 GET_MODE (SET_DEST (set)))
9644 && GET_CODE (SET_SRC (set)) == PLUS
9645 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9646 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9647 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9649 rtx reg = SET_DEST (set);
9650 rtx plus = SET_SRC (set);
9651 rtx base = XEXP (plus, 1);
9652 rtx prev = prev_nonnote_insn (insn);
9653 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9654 int regno = REGNO (reg);
9656 rtx reg_sum = NULL_RTX;
9658 /* Now, we need an index register.
9659 We'll set index_reg to this index register, const_reg to the
9660 register that is to be loaded with the constant
9661 (denoted as REGZ in the substitution illustration above),
9662 and reg_sum to the register-register that we want to use to
9663 substitute uses of REG (typically in MEMs) with.
9664 First check REG and BASE for being index registers;
9665 we can use them even if they are not dead. */
9666 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9667 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9675 /* Otherwise, look for a free index register. Since we have
9676 checked above that neiter REG nor BASE are index registers,
9677 if we find anything at all, it will be different from these
9679 for (i = first_index_reg; i <= last_index_reg; i++)
9681 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9682 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9683 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9684 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9686 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9687 const_reg = index_reg;
9688 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9693 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9694 (REGY), i.e. BASE, is not clobbered before the last use we'll
9697 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9698 && rtx_equal_p (SET_DEST (prev_set), reg)
9699 && reg_state[regno].use_index >= 0
9700 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9705 /* Change destination register and - if necessary - the
9706 constant value in PREV, the constant loading instruction. */
9707 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9708 if (reg_state[regno].offset != const0_rtx)
9709 validate_change (prev,
9710 &SET_SRC (prev_set),
9711 GEN_INT (INTVAL (SET_SRC (prev_set))
9712 + INTVAL (reg_state[regno].offset)),
9714 /* Now for every use of REG that we have recorded, replace REG
9716 for (i = reg_state[regno].use_index;
9717 i < RELOAD_COMBINE_MAX_USES; i++)
9718 validate_change (reg_state[regno].reg_use[i].insn,
9719 reg_state[regno].reg_use[i].usep,
9722 if (apply_change_group ())
9726 /* Delete the reg-reg addition. */
9727 PUT_CODE (insn, NOTE);
9728 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9729 NOTE_SOURCE_FILE (insn) = 0;
9731 if (reg_state[regno].offset != const0_rtx)
9733 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9735 for (np = ®_NOTES (prev); *np; )
9737 if (REG_NOTE_KIND (*np) == REG_EQUAL
9738 || REG_NOTE_KIND (*np) == REG_EQUIV)
9739 *np = XEXP (*np, 1);
9741 np = &XEXP (*np, 1);
9744 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9745 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9750 note_stores (PATTERN (insn), reload_combine_note_store);
9751 if (GET_CODE (insn) == CALL_INSN)
9755 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9757 if (call_used_regs[i])
9759 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9760 reg_state[i].store_ruid = reload_combine_ruid;
9763 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9764 link = XEXP (link, 1))
9766 rtx use = XEXP (link, 0);
9767 int regno = REGNO (XEXP (use, 0));
9768 if (GET_CODE (use) == CLOBBER)
9770 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9771 reg_state[regno].store_ruid = reload_combine_ruid;
9774 reg_state[regno].use_index = -1;
9777 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9779 /* Non-spill registers might be used at the call destination in
9780 some unknown fashion, so we have to mark the unknown use. */
9782 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9783 && JUMP_LABEL (insn))
9784 live = &LABEL_LIVE (JUMP_LABEL (insn));
9786 live = &ever_live_at_start;
9787 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9789 if (TEST_HARD_REG_BIT (*live, i))
9790 reg_state[i].use_index = -1;
9793 reload_combine_note_use (&PATTERN (insn), insn);
9794 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9796 if (REG_NOTE_KIND (note) == REG_INC
9797 && GET_CODE (XEXP (note, 0)) == REG)
9799 int regno = REGNO (XEXP (note, 0));
9801 reg_state[regno].store_ruid = reload_combine_ruid;
9802 reg_state[regno].use_index = -1;
9809 /* Check if DST is a register or a subreg of a register; if it is,
9810 update reg_state[regno].store_ruid and reg_state[regno].use_index
9811 accordingly. Called via note_stores from reload_combine. */
9813 reload_combine_note_store (dst, set)
9818 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9820 if (GET_CODE (dst) == SUBREG)
9822 regno = SUBREG_WORD (dst);
9823 dst = SUBREG_REG (dst);
9825 if (GET_CODE (dst) != REG)
9827 regno += REGNO (dst);
9829 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9830 careful with registers / register parts that are not full words.
9832 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9833 if (GET_CODE (set) != SET
9834 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9835 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9836 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9838 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9840 reg_state[i].use_index = -1;
9841 reg_state[i].store_ruid = reload_combine_ruid;
9846 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9848 reg_state[i].store_ruid = reload_combine_ruid;
9849 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9854 /* XP points to a piece of rtl that has to be checked for any uses of
9856 *XP is the pattern of INSN, or a part of it.
9857 Called from reload_combine, and recursively by itself. */
9859 reload_combine_note_use (xp, insn)
9863 enum rtx_code code = x->code;
9866 rtx offset = const0_rtx; /* For the REG case below. */
9871 if (GET_CODE (SET_DEST (x)) == REG)
9873 reload_combine_note_use (&SET_SRC (x), insn);
9879 if (GET_CODE (SET_DEST (x)) == REG)
9884 /* We are interested in (plus (reg) (const_int)) . */
9885 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9887 offset = XEXP (x, 1);
9892 int regno = REGNO (x);
9895 /* Some spurious USEs of pseudo registers might remain.
9896 Just ignore them. */
9897 if (regno >= FIRST_PSEUDO_REGISTER)
9900 /* If this register is already used in some unknown fashion, we
9902 If we decrement the index from zero to -1, we can't store more
9903 uses, so this register becomes used in an unknown fashion. */
9904 use_index = --reg_state[regno].use_index;
9908 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9910 /* We have found another use for a register that is already
9911 used later. Check if the offsets match; if not, mark the
9912 register as used in an unknown fashion. */
9913 if (! rtx_equal_p (offset, reg_state[regno].offset))
9915 reg_state[regno].use_index = -1;
9921 /* This is the first use of this register we have seen since we
9922 marked it as dead. */
9923 reg_state[regno].offset = offset;
9924 reg_state[regno].use_ruid = reload_combine_ruid;
9926 reg_state[regno].reg_use[use_index].insn = insn;
9927 reg_state[regno].reg_use[use_index].usep = xp;
9935 /* Recursively process the components of X. */
9936 fmt = GET_RTX_FORMAT (code);
9937 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9940 reload_combine_note_use (&XEXP (x, i), insn);
9941 else if (fmt[i] == 'E')
9943 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9944 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9949 /* See if we can reduce the cost of a constant by replacing a move with
9951 /* We cannot do our optimization across labels. Invalidating all the
9952 information about register contents we have would be costly, so we
9953 use last_label_luid (local variable of reload_cse_move2add) to note
9954 where the label is and then later disable any optimization that would
9956 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9957 reg_set_luid[n] is larger than last_label_luid[n] . */
9958 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9959 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9960 reg_mode[n] to be valid.
9961 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9962 has been set to reg_offset[n] in mode reg_mode[n] .
9963 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9964 register n has been set to the sum of reg_offset[n] and register
9965 reg_base_reg[n], calculated in mode reg_mode[n] . */
9966 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9967 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9968 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9969 /* move2add_luid is linearily increased while scanning the instructions
9970 from first to last. It is used to set reg_set_luid in
9971 reload_cse_move2add and move2add_note_store. */
9972 static int move2add_luid;
9974 /* Generate a CONST_INT and force it in the range of MODE. */
9976 gen_mode_int (mode, value)
9977 enum machine_mode mode;
9978 HOST_WIDE_INT value;
9980 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9981 int width = GET_MODE_BITSIZE (mode);
9983 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9985 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9986 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9987 cval |= (HOST_WIDE_INT) -1 << width;
9989 return GEN_INT (cval);
9993 reload_cse_move2add (first)
9998 int last_label_luid;
10000 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10001 reg_set_luid[i] = 0;
10003 last_label_luid = 0;
10005 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
10009 if (GET_CODE (insn) == CODE_LABEL)
10010 last_label_luid = move2add_luid;
10011 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
10013 pat = PATTERN (insn);
10014 /* For simplicity, we only perform this optimization on
10015 straightforward SETs. */
10016 if (GET_CODE (pat) == SET
10017 && GET_CODE (SET_DEST (pat)) == REG)
10019 rtx reg = SET_DEST (pat);
10020 int regno = REGNO (reg);
10021 rtx src = SET_SRC (pat);
10023 /* Check if we have valid information on the contents of this
10024 register in the mode of REG. */
10025 /* ??? We don't know how zero / sign extension is handled, hence
10026 we can't go from a narrower to a wider mode. */
10027 if (reg_set_luid[regno] > last_label_luid
10028 && (GET_MODE_SIZE (GET_MODE (reg))
10029 <= GET_MODE_SIZE (reg_mode[regno]))
10030 && GET_CODE (reg_offset[regno]) == CONST_INT)
10032 /* Try to transform (set (REGX) (CONST_INT A))
10034 (set (REGX) (CONST_INT B))
10036 (set (REGX) (CONST_INT A))
10038 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10040 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
10044 = gen_mode_int (GET_MODE (reg),
10045 INTVAL (src) - INTVAL (reg_offset[regno]));
10046 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10047 use (set (reg) (reg)) instead.
10048 We don't delete this insn, nor do we convert it into a
10049 note, to avoid losing register notes or the return
10050 value flag. jump2 already knowns how to get rid of
10052 if (new_src == const0_rtx)
10053 success = validate_change (insn, &SET_SRC (pat), reg, 0);
10054 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
10055 && have_add2_insn (GET_MODE (reg)))
10056 success = validate_change (insn, &PATTERN (insn),
10057 gen_add2_insn (reg, new_src), 0);
10058 reg_set_luid[regno] = move2add_luid;
10059 reg_mode[regno] = GET_MODE (reg);
10060 reg_offset[regno] = src;
10064 /* Try to transform (set (REGX) (REGY))
10065 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10067 (set (REGX) (REGY))
10068 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10071 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10073 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10074 else if (GET_CODE (src) == REG
10075 && reg_base_reg[regno] == REGNO (src)
10076 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10078 rtx next = next_nonnote_insn (insn);
10081 set = single_set (next);
10084 && SET_DEST (set) == reg
10085 && GET_CODE (SET_SRC (set)) == PLUS
10086 && XEXP (SET_SRC (set), 0) == reg
10087 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10089 rtx src3 = XEXP (SET_SRC (set), 1);
10091 = gen_mode_int (GET_MODE (reg),
10093 - INTVAL (reg_offset[regno]));
10096 if (new_src == const0_rtx)
10097 /* See above why we create (set (reg) (reg)) here. */
10099 = validate_change (next, &SET_SRC (set), reg, 0);
10100 else if ((rtx_cost (new_src, PLUS)
10101 < 2 + rtx_cost (src3, SET))
10102 && have_add2_insn (GET_MODE (reg)))
10104 = validate_change (next, &PATTERN (next),
10105 gen_add2_insn (reg, new_src), 0);
10108 /* INSN might be the first insn in a basic block
10109 if the preceding insn is a conditional jump
10110 or a possible-throwing call. */
10111 PUT_CODE (insn, NOTE);
10112 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10113 NOTE_SOURCE_FILE (insn) = 0;
10116 reg_set_luid[regno] = move2add_luid;
10117 reg_mode[regno] = GET_MODE (reg);
10118 reg_offset[regno] = src3;
10125 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10127 if (REG_NOTE_KIND (note) == REG_INC
10128 && GET_CODE (XEXP (note, 0)) == REG)
10130 /* Indicate that this register has been recently written to,
10131 but the exact contents are not available. */
10132 int regno = REGNO (XEXP (note, 0));
10133 if (regno < FIRST_PSEUDO_REGISTER)
10135 reg_set_luid[regno] = move2add_luid;
10136 reg_offset[regno] = note;
10140 note_stores (PATTERN (insn), move2add_note_store);
10141 /* If this is a CALL_INSN, all call used registers are stored with
10143 if (GET_CODE (insn) == CALL_INSN)
10145 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10147 if (call_used_regs[i])
10149 reg_set_luid[i] = move2add_luid;
10150 reg_offset[i] = insn; /* Invalidate contents. */
10157 /* SET is a SET or CLOBBER that sets DST.
10158 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10159 Called from reload_cse_move2add via note_stores. */
10161 move2add_note_store (dst, set)
10167 enum machine_mode mode = GET_MODE (dst);
10168 if (GET_CODE (dst) == SUBREG)
10170 regno = SUBREG_WORD (dst);
10171 dst = SUBREG_REG (dst);
10173 if (GET_CODE (dst) != REG)
10176 regno += REGNO (dst);
10178 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10179 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10180 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10181 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10183 rtx src = SET_SRC (set);
10185 reg_mode[regno] = mode;
10186 switch (GET_CODE (src))
10190 rtx src0 = XEXP (src, 0);
10191 if (GET_CODE (src0) == REG)
10193 if (REGNO (src0) != regno
10194 || reg_offset[regno] != const0_rtx)
10196 reg_base_reg[regno] = REGNO (src0);
10197 reg_set_luid[regno] = move2add_luid;
10199 reg_offset[regno] = XEXP (src, 1);
10202 reg_set_luid[regno] = move2add_luid;
10203 reg_offset[regno] = set; /* Invalidate contents. */
10208 reg_base_reg[regno] = REGNO (SET_SRC (set));
10209 reg_offset[regno] = const0_rtx;
10210 reg_set_luid[regno] = move2add_luid;
10214 reg_base_reg[regno] = -1;
10215 reg_offset[regno] = SET_SRC (set);
10216 reg_set_luid[regno] = move2add_luid;
10222 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10224 /* Indicate that this register has been recently written to,
10225 but the exact contents are not available. */
10226 reg_set_luid[i] = move2add_luid;
10227 reg_offset[i] = dst;
10232 #ifdef AUTO_INC_DEC
10234 add_auto_inc_notes (insn, x)
10238 enum rtx_code code = GET_CODE (x);
10242 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10245 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10249 /* Scan all the operand sub-expressions. */
10250 fmt = GET_RTX_FORMAT (code);
10251 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10254 add_auto_inc_notes (insn, XEXP (x, i));
10255 else if (fmt[i] == 'E')
10256 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10257 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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