1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Number of labels in the current function. */
383 static int num_labels;
385 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
386 static void maybe_fix_stack_asms (void);
387 static void copy_reloads (struct insn_chain *);
388 static void calculate_needs_all_insns (int);
389 static int find_reg (struct insn_chain *, int);
390 static void find_reload_regs (struct insn_chain *);
391 static void select_reload_regs (void);
392 static void delete_caller_save_insns (void);
394 static void spill_failure (rtx, enum reg_class);
395 static void count_spilled_pseudo (int, int, int);
396 static void delete_dead_insn (rtx);
397 static void alter_reg (int, int, bool);
398 static void set_label_offsets (rtx, rtx, int);
399 static void check_eliminable_occurrences (rtx);
400 static void elimination_effects (rtx, enum machine_mode);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_elim_table (void);
409 static void update_eliminables (HARD_REG_SET *);
410 static void spill_hard_reg (unsigned int, int);
411 static int finish_spills (int);
412 static void scan_paradoxical_subregs (rtx);
413 static void count_pseudo (int);
414 static void order_regs_for_reload (struct insn_chain *);
415 static void reload_as_needed (int);
416 static void forget_old_reloads_1 (rtx, const_rtx, void *);
417 static void forget_marked_reloads (regset);
418 static int reload_reg_class_lower (const void *, const void *);
419 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
421 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
423 static int reload_reg_free_p (unsigned int, int, enum reload_type);
424 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
426 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
428 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
429 static int allocate_reload_reg (struct insn_chain *, int, int);
430 static int conflicts_with_override (rtx);
431 static void failed_reload (rtx, int);
432 static int set_reload_reg (int, int);
433 static void choose_reload_regs_init (struct insn_chain *, rtx *);
434 static void choose_reload_regs (struct insn_chain *);
435 static void merge_assigned_reloads (rtx);
436 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
438 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
440 static void do_input_reload (struct insn_chain *, struct reload *, int);
441 static void do_output_reload (struct insn_chain *, struct reload *, int);
442 static void emit_reload_insns (struct insn_chain *);
443 static void delete_output_reload (rtx, int, int, rtx);
444 static void delete_address_reloads (rtx, rtx);
445 static void delete_address_reloads_1 (rtx, rtx, rtx);
446 static rtx inc_for_reload (rtx, rtx, rtx, int);
448 static void add_auto_inc_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
803 if (NONDEBUG_INSN_P (insn))
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1005 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1006 else if (CONSTANT_P (XEXP (x, 0))
1007 || (REG_P (XEXP (x, 0))
1008 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1009 || (GET_CODE (XEXP (x, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (x, 0), 0))
1011 && (REGNO (XEXP (XEXP (x, 0), 0))
1012 < FIRST_PSEUDO_REGISTER)
1013 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1014 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1017 /* Make a new stack slot. Then indicate that something
1018 changed so we go back and recompute offsets for
1019 eliminable registers because the allocation of memory
1020 below might change some offset. reg_equiv_{mem,address}
1021 will be set up for this pseudo on the next pass around
1023 reg_equiv_memory_loc[i] = 0;
1024 reg_equiv_init[i] = 0;
1025 alter_reg (i, -1, true);
1029 if (caller_save_needed)
1030 setup_save_areas ();
1032 /* If we allocated another stack slot, redo elimination bookkeeping. */
1033 if (starting_frame_size != get_frame_size ())
1035 if (starting_frame_size && crtl->stack_alignment_needed)
1037 /* If we have a stack frame, we must align it now. The
1038 stack size may be a part of the offset computation for
1039 register elimination. So if this changes the stack size,
1040 then repeat the elimination bookkeeping. We don't
1041 realign when there is no stack, as that will cause a
1042 stack frame when none is needed should
1043 STARTING_FRAME_OFFSET not be already aligned to
1045 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1046 if (starting_frame_size != get_frame_size ())
1050 if (caller_save_needed)
1052 save_call_clobbered_regs ();
1053 /* That might have allocated new insn_chain structures. */
1054 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1057 calculate_needs_all_insns (global);
1059 if (! ira_conflicts_p)
1060 /* Don't do it for IRA. We need this info because we don't
1061 change live_throughout and dead_or_set for chains when IRA
1063 CLEAR_REG_SET (&spilled_pseudos);
1067 something_changed = 0;
1069 /* If we allocated any new memory locations, make another pass
1070 since it might have changed elimination offsets. */
1071 if (starting_frame_size != get_frame_size ())
1072 something_changed = 1;
1074 /* Even if the frame size remained the same, we might still have
1075 changed elimination offsets, e.g. if find_reloads called
1076 force_const_mem requiring the back end to allocate a constant
1077 pool base register that needs to be saved on the stack. */
1078 else if (!verify_initial_elim_offsets ())
1079 something_changed = 1;
1082 HARD_REG_SET to_spill;
1083 CLEAR_HARD_REG_SET (to_spill);
1084 update_eliminables (&to_spill);
1085 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (TEST_HARD_REG_BIT (to_spill, i))
1090 spill_hard_reg (i, 1);
1093 /* Regardless of the state of spills, if we previously had
1094 a register that we thought we could eliminate, but now can
1095 not eliminate, we must run another pass.
1097 Consider pseudos which have an entry in reg_equiv_* which
1098 reference an eliminable register. We must make another pass
1099 to update reg_equiv_* so that we do not substitute in the
1100 old value from when we thought the elimination could be
1102 something_changed = 1;
1106 select_reload_regs ();
1110 if (insns_need_reload != 0 || did_spill)
1111 something_changed |= finish_spills (global);
1113 if (! something_changed)
1116 if (caller_save_needed)
1117 delete_caller_save_insns ();
1119 obstack_free (&reload_obstack, reload_firstobj);
1122 /* If global-alloc was run, notify it of any register eliminations we have
1125 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1126 if (ep->can_eliminate)
1127 mark_elimination (ep->from, ep->to);
1129 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1130 If that insn didn't set the register (i.e., it copied the register to
1131 memory), just delete that insn instead of the equivalencing insn plus
1132 anything now dead. If we call delete_dead_insn on that insn, we may
1133 delete the insn that actually sets the register if the register dies
1134 there and that is incorrect. */
1136 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1141 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1143 rtx equiv_insn = XEXP (list, 0);
1145 /* If we already deleted the insn or if it may trap, we can't
1146 delete it. The latter case shouldn't happen, but can
1147 if an insn has a variable address, gets a REG_EH_REGION
1148 note added to it, and then gets converted into a load
1149 from a constant address. */
1150 if (NOTE_P (equiv_insn)
1151 || can_throw_internal (equiv_insn))
1153 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1154 delete_dead_insn (equiv_insn);
1156 SET_INSN_DELETED (equiv_insn);
1161 /* Use the reload registers where necessary
1162 by generating move instructions to move the must-be-register
1163 values into or out of the reload registers. */
1165 if (insns_need_reload != 0 || something_needs_elimination
1166 || something_needs_operands_changed)
1168 HOST_WIDE_INT old_frame_size = get_frame_size ();
1170 reload_as_needed (global);
1172 gcc_assert (old_frame_size == get_frame_size ());
1174 gcc_assert (verify_initial_elim_offsets ());
1177 /* If we were able to eliminate the frame pointer, show that it is no
1178 longer live at the start of any basic block. If it ls live by
1179 virtue of being in a pseudo, that pseudo will be marked live
1180 and hence the frame pointer will be known to be live via that
1183 if (! frame_pointer_needed)
1185 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1187 /* Come here (with failure set nonzero) if we can't get enough spill
1191 CLEAR_REG_SET (&changed_allocation_pseudos);
1192 CLEAR_REG_SET (&spilled_pseudos);
1193 reload_in_progress = 0;
1195 /* Now eliminate all pseudo regs by modifying them into
1196 their equivalent memory references.
1197 The REG-rtx's for the pseudos are modified in place,
1198 so all insns that used to refer to them now refer to memory.
1200 For a reg that has a reg_equiv_address, all those insns
1201 were changed by reloading so that no insns refer to it any longer;
1202 but the DECL_RTL of a variable decl may refer to it,
1203 and if so this causes the debugging info to mention the variable. */
1205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1209 if (reg_equiv_mem[i])
1210 addr = XEXP (reg_equiv_mem[i], 0);
1212 if (reg_equiv_address[i])
1213 addr = reg_equiv_address[i];
1217 if (reg_renumber[i] < 0)
1219 rtx reg = regno_reg_rtx[i];
1221 REG_USERVAR_P (reg) = 0;
1222 PUT_CODE (reg, MEM);
1223 XEXP (reg, 0) = addr;
1224 if (reg_equiv_memory_loc[i])
1225 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1228 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1229 MEM_ATTRS (reg) = 0;
1231 MEM_NOTRAP_P (reg) = 1;
1233 else if (reg_equiv_mem[i])
1234 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We don't want complex addressing modes in debug insns
1238 if simpler ones will do, so delegitimize equivalences
1240 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1242 rtx reg = regno_reg_rtx[i];
1246 if (reg_equiv_constant[i])
1247 equiv = reg_equiv_constant[i];
1248 else if (reg_equiv_invariant[i])
1249 equiv = reg_equiv_invariant[i];
1250 else if (reg && MEM_P (reg))
1251 equiv = targetm.delegitimize_address (reg);
1252 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1258 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1260 rtx *loc = DF_REF_LOC (use);
1263 insn = DF_REF_INSN (use);
1264 next = DF_REF_NEXT_REG (use);
1266 if (DEBUG_INSN_P (insn))
1268 gcc_assert (x == reg
1269 || (GET_CODE (x) == SUBREG
1270 && SUBREG_REG (x) == reg));
1274 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1275 df_insn_rescan_debug_internal (insn);
1280 *loc = copy_rtx (equiv);
1281 else if (GET_CODE (x) == SUBREG
1282 && SUBREG_REG (x) == reg)
1283 *loc = simplify_gen_subreg (GET_MODE (x), equiv,
1288 *loc = wrap_constant (GET_MODE (x), *loc);
1295 /* We must set reload_completed now since the cleanup_subreg_operands call
1296 below will re-recognize each insn and reload may have generated insns
1297 which are only valid during and after reload. */
1298 reload_completed = 1;
1300 /* Make a pass over all the insns and delete all USEs which we inserted
1301 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1302 notes. Delete all CLOBBER insns, except those that refer to the return
1303 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1304 from misarranging variable-array code, and simplify (subreg (reg))
1305 operands. Strip and regenerate REG_INC notes that may have been moved
1308 for (insn = first; insn; insn = NEXT_INSN (insn))
1314 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1315 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1317 if ((GET_CODE (PATTERN (insn)) == USE
1318 /* We mark with QImode USEs introduced by reload itself. */
1319 && (GET_MODE (insn) == QImode
1320 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1321 || (GET_CODE (PATTERN (insn)) == CLOBBER
1322 && (!MEM_P (XEXP (PATTERN (insn), 0))
1323 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1324 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1325 && XEXP (XEXP (PATTERN (insn), 0), 0)
1326 != stack_pointer_rtx))
1327 && (!REG_P (XEXP (PATTERN (insn), 0))
1328 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1334 /* Some CLOBBERs may survive until here and still reference unassigned
1335 pseudos with const equivalent, which may in turn cause ICE in later
1336 passes if the reference remains in place. */
1337 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1338 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1339 VOIDmode, PATTERN (insn));
1341 /* Discard obvious no-ops, even without -O. This optimization
1342 is fast and doesn't interfere with debugging. */
1343 if (NONJUMP_INSN_P (insn)
1344 && GET_CODE (PATTERN (insn)) == SET
1345 && REG_P (SET_SRC (PATTERN (insn)))
1346 && REG_P (SET_DEST (PATTERN (insn)))
1347 && (REGNO (SET_SRC (PATTERN (insn)))
1348 == REGNO (SET_DEST (PATTERN (insn)))))
1354 pnote = ®_NOTES (insn);
1357 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1358 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1359 || REG_NOTE_KIND (*pnote) == REG_INC)
1360 *pnote = XEXP (*pnote, 1);
1362 pnote = &XEXP (*pnote, 1);
1366 add_auto_inc_notes (insn, PATTERN (insn));
1369 /* Simplify (subreg (reg)) if it appears as an operand. */
1370 cleanup_subreg_operands (insn);
1372 /* Clean up invalid ASMs so that they don't confuse later passes.
1374 if (asm_noperands (PATTERN (insn)) >= 0)
1376 extract_insn (insn);
1377 if (!constrain_operands (1))
1379 error_for_asm (insn,
1380 "%<asm%> operand has impossible constraints");
1387 /* If we are doing generic stack checking, give a warning if this
1388 function's frame size is larger than we expect. */
1389 if (flag_stack_check == GENERIC_STACK_CHECK)
1391 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1392 static int verbose_warned = 0;
1394 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1395 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1396 size += UNITS_PER_WORD;
1398 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1400 warning (0, "frame size too large for reliable stack checking");
1401 if (! verbose_warned)
1403 warning (0, "try reducing the number of local variables");
1409 /* Indicate that we no longer have known memory locations or constants. */
1410 if (reg_equiv_constant)
1411 free (reg_equiv_constant);
1412 if (reg_equiv_invariant)
1413 free (reg_equiv_invariant);
1414 reg_equiv_constant = 0;
1415 reg_equiv_invariant = 0;
1416 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1417 reg_equiv_memory_loc = 0;
1419 free (temp_pseudo_reg_arr);
1421 if (offsets_known_at)
1422 free (offsets_known_at);
1426 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1427 if (reg_equiv_alt_mem_list[i])
1428 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1429 free (reg_equiv_alt_mem_list);
1431 free (reg_equiv_mem);
1433 free (reg_equiv_address);
1434 free (reg_max_ref_width);
1435 free (reg_old_renumber);
1436 free (pseudo_previous_regs);
1437 free (pseudo_forbidden_regs);
1439 CLEAR_HARD_REG_SET (used_spill_regs);
1440 for (i = 0; i < n_spills; i++)
1441 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1443 /* Free all the insn_chain structures at once. */
1444 obstack_free (&reload_obstack, reload_startobj);
1445 unused_insn_chains = 0;
1446 fixup_abnormal_edges ();
1448 /* Replacing pseudos with their memory equivalents might have
1449 created shared rtx. Subsequent passes would get confused
1450 by this, so unshare everything here. */
1451 unshare_all_rtl_again (first);
1453 #ifdef STACK_BOUNDARY
1454 /* init_emit has set the alignment of the hard frame pointer
1455 to STACK_BOUNDARY. It is very likely no longer valid if
1456 the hard frame pointer was used for register allocation. */
1457 if (!frame_pointer_needed)
1458 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1464 /* Yet another special case. Unfortunately, reg-stack forces people to
1465 write incorrect clobbers in asm statements. These clobbers must not
1466 cause the register to appear in bad_spill_regs, otherwise we'll call
1467 fatal_insn later. We clear the corresponding regnos in the live
1468 register sets to avoid this.
1469 The whole thing is rather sick, I'm afraid. */
1472 maybe_fix_stack_asms (void)
1475 const char *constraints[MAX_RECOG_OPERANDS];
1476 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1477 struct insn_chain *chain;
1479 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1482 HARD_REG_SET clobbered, allowed;
1485 if (! INSN_P (chain->insn)
1486 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1488 pat = PATTERN (chain->insn);
1489 if (GET_CODE (pat) != PARALLEL)
1492 CLEAR_HARD_REG_SET (clobbered);
1493 CLEAR_HARD_REG_SET (allowed);
1495 /* First, make a mask of all stack regs that are clobbered. */
1496 for (i = 0; i < XVECLEN (pat, 0); i++)
1498 rtx t = XVECEXP (pat, 0, i);
1499 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1500 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1503 /* Get the operand values and constraints out of the insn. */
1504 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1505 constraints, operand_mode, NULL);
1507 /* For every operand, see what registers are allowed. */
1508 for (i = 0; i < noperands; i++)
1510 const char *p = constraints[i];
1511 /* For every alternative, we compute the class of registers allowed
1512 for reloading in CLS, and merge its contents into the reg set
1514 int cls = (int) NO_REGS;
1520 if (c == '\0' || c == ',' || c == '#')
1522 /* End of one alternative - mark the regs in the current
1523 class, and reset the class. */
1524 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1530 } while (c != '\0' && c != ',');
1538 case '=': case '+': case '*': case '%': case '?': case '!':
1539 case '0': case '1': case '2': case '3': case '4': case '<':
1540 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1541 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1542 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1543 case TARGET_MEM_CONSTRAINT:
1547 cls = (int) reg_class_subunion[cls]
1548 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1553 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1557 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1558 cls = (int) reg_class_subunion[cls]
1559 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1561 cls = (int) reg_class_subunion[cls]
1562 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1564 p += CONSTRAINT_LEN (c, p);
1567 /* Those of the registers which are clobbered, but allowed by the
1568 constraints, must be usable as reload registers. So clear them
1569 out of the life information. */
1570 AND_HARD_REG_SET (allowed, clobbered);
1571 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1572 if (TEST_HARD_REG_BIT (allowed, i))
1574 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1575 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1582 /* Copy the global variables n_reloads and rld into the corresponding elts
1585 copy_reloads (struct insn_chain *chain)
1587 chain->n_reloads = n_reloads;
1588 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1589 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1590 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1593 /* Walk the chain of insns, and determine for each whether it needs reloads
1594 and/or eliminations. Build the corresponding insns_need_reload list, and
1595 set something_needs_elimination as appropriate. */
1597 calculate_needs_all_insns (int global)
1599 struct insn_chain **pprev_reload = &insns_need_reload;
1600 struct insn_chain *chain, *next = 0;
1602 something_needs_elimination = 0;
1604 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1605 for (chain = reload_insn_chain; chain != 0; chain = next)
1607 rtx insn = chain->insn;
1611 /* Clear out the shortcuts. */
1612 chain->n_reloads = 0;
1613 chain->need_elim = 0;
1614 chain->need_reload = 0;
1615 chain->need_operand_change = 0;
1617 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1618 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1619 what effects this has on the known offsets at labels. */
1621 if (LABEL_P (insn) || JUMP_P (insn)
1622 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1623 set_label_offsets (insn, insn, 0);
1627 rtx old_body = PATTERN (insn);
1628 int old_code = INSN_CODE (insn);
1629 rtx old_notes = REG_NOTES (insn);
1630 int did_elimination = 0;
1631 int operands_changed = 0;
1632 rtx set = single_set (insn);
1634 /* Skip insns that only set an equivalence. */
1635 if (set && REG_P (SET_DEST (set))
1636 && reg_renumber[REGNO (SET_DEST (set))] < 0
1637 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1638 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1639 && reg_equiv_init[REGNO (SET_DEST (set))])
1642 /* If needed, eliminate any eliminable registers. */
1643 if (num_eliminable || num_eliminable_invariants)
1644 did_elimination = eliminate_regs_in_insn (insn, 0);
1646 /* Analyze the instruction. */
1647 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1648 global, spill_reg_order);
1650 /* If a no-op set needs more than one reload, this is likely
1651 to be something that needs input address reloads. We
1652 can't get rid of this cleanly later, and it is of no use
1653 anyway, so discard it now.
1654 We only do this when expensive_optimizations is enabled,
1655 since this complements reload inheritance / output
1656 reload deletion, and it can make debugging harder. */
1657 if (flag_expensive_optimizations && n_reloads > 1)
1659 rtx set = single_set (insn);
1662 ((SET_SRC (set) == SET_DEST (set)
1663 && REG_P (SET_SRC (set))
1664 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1665 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1666 && reg_renumber[REGNO (SET_SRC (set))] < 0
1667 && reg_renumber[REGNO (SET_DEST (set))] < 0
1668 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1669 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1670 && rtx_equal_p (reg_equiv_memory_loc
1671 [REGNO (SET_SRC (set))],
1672 reg_equiv_memory_loc
1673 [REGNO (SET_DEST (set))]))))
1675 if (ira_conflicts_p)
1676 /* Inform IRA about the insn deletion. */
1677 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1678 REGNO (SET_SRC (set)));
1680 /* Delete it from the reload chain. */
1682 chain->prev->next = next;
1684 reload_insn_chain = next;
1686 next->prev = chain->prev;
1687 chain->next = unused_insn_chains;
1688 unused_insn_chains = chain;
1693 update_eliminable_offsets ();
1695 /* Remember for later shortcuts which insns had any reloads or
1696 register eliminations. */
1697 chain->need_elim = did_elimination;
1698 chain->need_reload = n_reloads > 0;
1699 chain->need_operand_change = operands_changed;
1701 /* Discard any register replacements done. */
1702 if (did_elimination)
1704 obstack_free (&reload_obstack, reload_insn_firstobj);
1705 PATTERN (insn) = old_body;
1706 INSN_CODE (insn) = old_code;
1707 REG_NOTES (insn) = old_notes;
1708 something_needs_elimination = 1;
1711 something_needs_operands_changed |= operands_changed;
1715 copy_reloads (chain);
1716 *pprev_reload = chain;
1717 pprev_reload = &chain->next_need_reload;
1724 /* Comparison function for qsort to decide which of two reloads
1725 should be handled first. *P1 and *P2 are the reload numbers. */
1728 reload_reg_class_lower (const void *r1p, const void *r2p)
1730 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1733 /* Consider required reloads before optional ones. */
1734 t = rld[r1].optional - rld[r2].optional;
1738 /* Count all solitary classes before non-solitary ones. */
1739 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1740 - (reg_class_size[(int) rld[r1].rclass] == 1));
1744 /* Aside from solitaires, consider all multi-reg groups first. */
1745 t = rld[r2].nregs - rld[r1].nregs;
1749 /* Consider reloads in order of increasing reg-class number. */
1750 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1754 /* If reloads are equally urgent, sort by reload number,
1755 so that the results of qsort leave nothing to chance. */
1759 /* The cost of spilling each hard reg. */
1760 static int spill_cost[FIRST_PSEUDO_REGISTER];
1762 /* When spilling multiple hard registers, we use SPILL_COST for the first
1763 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1764 only the first hard reg for a multi-reg pseudo. */
1765 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1767 /* Map of hard regno to pseudo regno currently occupying the hard
1769 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1771 /* Update the spill cost arrays, considering that pseudo REG is live. */
1774 count_pseudo (int reg)
1776 int freq = REG_FREQ (reg);
1777 int r = reg_renumber[reg];
1780 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1781 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1782 /* Ignore spilled pseudo-registers which can be here only if IRA
1784 || (ira_conflicts_p && r < 0))
1787 SET_REGNO_REG_SET (&pseudos_counted, reg);
1789 gcc_assert (r >= 0);
1791 spill_add_cost[r] += freq;
1792 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1795 hard_regno_to_pseudo_regno[r + nregs] = reg;
1796 spill_cost[r + nregs] += freq;
1800 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1801 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1804 order_regs_for_reload (struct insn_chain *chain)
1807 HARD_REG_SET used_by_pseudos;
1808 HARD_REG_SET used_by_pseudos2;
1809 reg_set_iterator rsi;
1811 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1813 memset (spill_cost, 0, sizeof spill_cost);
1814 memset (spill_add_cost, 0, sizeof spill_add_cost);
1815 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1816 hard_regno_to_pseudo_regno[i] = -1;
1818 /* Count number of uses of each hard reg by pseudo regs allocated to it
1819 and then order them by decreasing use. First exclude hard registers
1820 that are live in or across this insn. */
1822 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1823 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1824 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1825 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1827 /* Now find out which pseudos are allocated to it, and update
1829 CLEAR_REG_SET (&pseudos_counted);
1831 EXECUTE_IF_SET_IN_REG_SET
1832 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1836 EXECUTE_IF_SET_IN_REG_SET
1837 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1841 CLEAR_REG_SET (&pseudos_counted);
1844 /* Vector of reload-numbers showing the order in which the reloads should
1846 static short reload_order[MAX_RELOADS];
1848 /* This is used to keep track of the spill regs used in one insn. */
1849 static HARD_REG_SET used_spill_regs_local;
1851 /* We decided to spill hard register SPILLED, which has a size of
1852 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1853 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1854 update SPILL_COST/SPILL_ADD_COST. */
1857 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1859 int freq = REG_FREQ (reg);
1860 int r = reg_renumber[reg];
1861 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1863 /* Ignore spilled pseudo-registers which can be here only if IRA is
1865 if ((ira_conflicts_p && r < 0)
1866 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1867 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1870 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1872 spill_add_cost[r] -= freq;
1875 hard_regno_to_pseudo_regno[r + nregs] = -1;
1876 spill_cost[r + nregs] -= freq;
1880 /* Find reload register to use for reload number ORDER. */
1883 find_reg (struct insn_chain *chain, int order)
1885 int rnum = reload_order[order];
1886 struct reload *rl = rld + rnum;
1887 int best_cost = INT_MAX;
1889 unsigned int i, j, n;
1891 HARD_REG_SET not_usable;
1892 HARD_REG_SET used_by_other_reload;
1893 reg_set_iterator rsi;
1894 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1895 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1897 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1898 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1899 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1901 CLEAR_HARD_REG_SET (used_by_other_reload);
1902 for (k = 0; k < order; k++)
1904 int other = reload_order[k];
1906 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1907 for (j = 0; j < rld[other].nregs; j++)
1908 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1911 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1913 #ifdef REG_ALLOC_ORDER
1914 unsigned int regno = reg_alloc_order[i];
1916 unsigned int regno = i;
1919 if (! TEST_HARD_REG_BIT (not_usable, regno)
1920 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1921 && HARD_REGNO_MODE_OK (regno, rl->mode))
1923 int this_cost = spill_cost[regno];
1925 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1927 for (j = 1; j < this_nregs; j++)
1929 this_cost += spill_add_cost[regno + j];
1930 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1931 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1937 if (ira_conflicts_p)
1939 /* Ask IRA to find a better pseudo-register for
1941 for (n = j = 0; j < this_nregs; j++)
1943 int r = hard_regno_to_pseudo_regno[regno + j];
1947 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1948 regno_pseudo_regs[n++] = r;
1950 regno_pseudo_regs[n++] = -1;
1952 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1953 best_regno_pseudo_regs,
1960 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1961 if (regno_pseudo_regs[j] < 0)
1968 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1970 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1972 if (this_cost < best_cost
1973 /* Among registers with equal cost, prefer caller-saved ones, or
1974 use REG_ALLOC_ORDER if it is defined. */
1975 || (this_cost == best_cost
1976 #ifdef REG_ALLOC_ORDER
1977 && (inv_reg_alloc_order[regno]
1978 < inv_reg_alloc_order[best_reg])
1980 && call_used_regs[regno]
1981 && ! call_used_regs[best_reg]
1986 best_cost = this_cost;
1994 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1996 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1997 rl->regno = best_reg;
1999 EXECUTE_IF_SET_IN_REG_SET
2000 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
2002 count_spilled_pseudo (best_reg, rl->nregs, j);
2005 EXECUTE_IF_SET_IN_REG_SET
2006 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
2008 count_spilled_pseudo (best_reg, rl->nregs, j);
2011 for (i = 0; i < rl->nregs; i++)
2013 gcc_assert (spill_cost[best_reg + i] == 0);
2014 gcc_assert (spill_add_cost[best_reg + i] == 0);
2015 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2016 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2021 /* Find more reload regs to satisfy the remaining need of an insn, which
2023 Do it by ascending class number, since otherwise a reg
2024 might be spilled for a big class and might fail to count
2025 for a smaller class even though it belongs to that class. */
2028 find_reload_regs (struct insn_chain *chain)
2032 /* In order to be certain of getting the registers we need,
2033 we must sort the reloads into order of increasing register class.
2034 Then our grabbing of reload registers will parallel the process
2035 that provided the reload registers. */
2036 for (i = 0; i < chain->n_reloads; i++)
2038 /* Show whether this reload already has a hard reg. */
2039 if (chain->rld[i].reg_rtx)
2041 int regno = REGNO (chain->rld[i].reg_rtx);
2042 chain->rld[i].regno = regno;
2044 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2047 chain->rld[i].regno = -1;
2048 reload_order[i] = i;
2051 n_reloads = chain->n_reloads;
2052 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2054 CLEAR_HARD_REG_SET (used_spill_regs_local);
2057 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2059 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2061 /* Compute the order of preference for hard registers to spill. */
2063 order_regs_for_reload (chain);
2065 for (i = 0; i < n_reloads; i++)
2067 int r = reload_order[i];
2069 /* Ignore reloads that got marked inoperative. */
2070 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2071 && ! rld[r].optional
2072 && rld[r].regno == -1)
2073 if (! find_reg (chain, i))
2076 fprintf (dump_file, "reload failure for reload %d\n", r);
2077 spill_failure (chain->insn, rld[r].rclass);
2083 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2084 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2086 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2090 select_reload_regs (void)
2092 struct insn_chain *chain;
2094 /* Try to satisfy the needs for each insn. */
2095 for (chain = insns_need_reload; chain != 0;
2096 chain = chain->next_need_reload)
2097 find_reload_regs (chain);
2100 /* Delete all insns that were inserted by emit_caller_save_insns during
2103 delete_caller_save_insns (void)
2105 struct insn_chain *c = reload_insn_chain;
2109 while (c != 0 && c->is_caller_save_insn)
2111 struct insn_chain *next = c->next;
2114 if (c == reload_insn_chain)
2115 reload_insn_chain = next;
2119 next->prev = c->prev;
2121 c->prev->next = next;
2122 c->next = unused_insn_chains;
2123 unused_insn_chains = c;
2131 /* Handle the failure to find a register to spill.
2132 INSN should be one of the insns which needed this particular spill reg. */
2135 spill_failure (rtx insn, enum reg_class rclass)
2137 if (asm_noperands (PATTERN (insn)) >= 0)
2138 error_for_asm (insn, "can't find a register in class %qs while "
2139 "reloading %<asm%>",
2140 reg_class_names[rclass]);
2143 error ("unable to find a register to spill in class %qs",
2144 reg_class_names[rclass]);
2148 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2149 debug_reload_to_stream (dump_file);
2151 fatal_insn ("this is the insn:", insn);
2155 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2156 data that is dead in INSN. */
2159 delete_dead_insn (rtx insn)
2161 rtx prev = prev_real_insn (insn);
2164 /* If the previous insn sets a register that dies in our insn, delete it
2166 if (prev && GET_CODE (PATTERN (prev)) == SET
2167 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2168 && reg_mentioned_p (prev_dest, PATTERN (insn))
2169 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2170 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2171 delete_dead_insn (prev);
2173 SET_INSN_DELETED (insn);
2176 /* Modify the home of pseudo-reg I.
2177 The new home is present in reg_renumber[I].
2179 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2180 or it may be -1, meaning there is none or it is not relevant.
2181 This is used so that all pseudos spilled from a given hard reg
2182 can share one stack slot. */
2185 alter_reg (int i, int from_reg, bool dont_share_p)
2187 /* When outputting an inline function, this can happen
2188 for a reg that isn't actually used. */
2189 if (regno_reg_rtx[i] == 0)
2192 /* If the reg got changed to a MEM at rtl-generation time,
2194 if (!REG_P (regno_reg_rtx[i]))
2197 /* Modify the reg-rtx to contain the new hard reg
2198 number or else to contain its pseudo reg number. */
2199 SET_REGNO (regno_reg_rtx[i],
2200 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2202 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2203 allocate a stack slot for it. */
2205 if (reg_renumber[i] < 0
2206 && REG_N_REFS (i) > 0
2207 && reg_equiv_constant[i] == 0
2208 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2209 && reg_equiv_memory_loc[i] == 0)
2212 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2213 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2214 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2215 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2216 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2219 if (ira_conflicts_p)
2221 /* Mark the spill for IRA. */
2222 SET_REGNO_REG_SET (&spilled_pseudos, i);
2224 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2230 /* Each pseudo reg has an inherent size which comes from its own mode,
2231 and a total size which provides room for paradoxical subregs
2232 which refer to the pseudo reg in wider modes.
2234 We can use a slot already allocated if it provides both
2235 enough inherent space and enough total space.
2236 Otherwise, we allocate a new slot, making sure that it has no less
2237 inherent space, and no less total space, then the previous slot. */
2238 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2242 /* No known place to spill from => no slot to reuse. */
2243 x = assign_stack_local (mode, total_size,
2244 min_align > inherent_align
2245 || total_size > inherent_size ? -1 : 0);
2249 /* Cancel the big-endian correction done in assign_stack_local.
2250 Get the address of the beginning of the slot. This is so we
2251 can do a big-endian correction unconditionally below. */
2252 if (BYTES_BIG_ENDIAN)
2254 adjust = inherent_size - total_size;
2257 = adjust_address_nv (x, mode_for_size (total_size
2263 if (! dont_share_p && ira_conflicts_p)
2264 /* Inform IRA about allocation a new stack slot. */
2265 ira_mark_new_stack_slot (stack_slot, i, total_size);
2268 /* Reuse a stack slot if possible. */
2269 else if (spill_stack_slot[from_reg] != 0
2270 && spill_stack_slot_width[from_reg] >= total_size
2271 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2273 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2274 x = spill_stack_slot[from_reg];
2276 /* Allocate a bigger slot. */
2279 /* Compute maximum size needed, both for inherent size
2280 and for total size. */
2283 if (spill_stack_slot[from_reg])
2285 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2287 mode = GET_MODE (spill_stack_slot[from_reg]);
2288 if (spill_stack_slot_width[from_reg] > total_size)
2289 total_size = spill_stack_slot_width[from_reg];
2290 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2291 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2294 /* Make a slot with that size. */
2295 x = assign_stack_local (mode, total_size,
2296 min_align > inherent_align
2297 || total_size > inherent_size ? -1 : 0);
2300 /* Cancel the big-endian correction done in assign_stack_local.
2301 Get the address of the beginning of the slot. This is so we
2302 can do a big-endian correction unconditionally below. */
2303 if (BYTES_BIG_ENDIAN)
2305 adjust = GET_MODE_SIZE (mode) - total_size;
2308 = adjust_address_nv (x, mode_for_size (total_size
2314 spill_stack_slot[from_reg] = stack_slot;
2315 spill_stack_slot_width[from_reg] = total_size;
2318 /* On a big endian machine, the "address" of the slot
2319 is the address of the low part that fits its inherent mode. */
2320 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2321 adjust += (total_size - inherent_size);
2323 /* If we have any adjustment to make, or if the stack slot is the
2324 wrong mode, make a new stack slot. */
2325 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2327 /* Set all of the memory attributes as appropriate for a spill. */
2328 set_mem_attrs_for_spill (x);
2330 /* Save the stack slot for later. */
2331 reg_equiv_memory_loc[i] = x;
2335 /* Mark the slots in regs_ever_live for the hard regs used by
2336 pseudo-reg number REGNO, accessed in MODE. */
2339 mark_home_live_1 (int regno, enum machine_mode mode)
2343 i = reg_renumber[regno];
2346 lim = end_hard_regno (mode, i);
2348 df_set_regs_ever_live(i++, true);
2351 /* Mark the slots in regs_ever_live for the hard regs
2352 used by pseudo-reg number REGNO. */
2355 mark_home_live (int regno)
2357 if (reg_renumber[regno] >= 0)
2358 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2361 /* This function handles the tracking of elimination offsets around branches.
2363 X is a piece of RTL being scanned.
2365 INSN is the insn that it came from, if any.
2367 INITIAL_P is nonzero if we are to set the offset to be the initial
2368 offset and zero if we are setting the offset of the label to be the
2372 set_label_offsets (rtx x, rtx insn, int initial_p)
2374 enum rtx_code code = GET_CODE (x);
2377 struct elim_table *p;
2382 if (LABEL_REF_NONLOCAL_P (x))
2387 /* ... fall through ... */
2390 /* If we know nothing about this label, set the desired offsets. Note
2391 that this sets the offset at a label to be the offset before a label
2392 if we don't know anything about the label. This is not correct for
2393 the label after a BARRIER, but is the best guess we can make. If
2394 we guessed wrong, we will suppress an elimination that might have
2395 been possible had we been able to guess correctly. */
2397 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2399 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401 = (initial_p ? reg_eliminate[i].initial_offset
2402 : reg_eliminate[i].offset);
2403 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2406 /* Otherwise, if this is the definition of a label and it is
2407 preceded by a BARRIER, set our offsets to the known offset of
2411 && (tem = prev_nonnote_insn (insn)) != 0
2413 set_offsets_for_label (insn);
2415 /* If neither of the above cases is true, compare each offset
2416 with those previously recorded and suppress any eliminations
2417 where the offsets disagree. */
2419 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2420 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2421 != (initial_p ? reg_eliminate[i].initial_offset
2422 : reg_eliminate[i].offset))
2423 reg_eliminate[i].can_eliminate = 0;
2428 set_label_offsets (PATTERN (insn), insn, initial_p);
2430 /* ... fall through ... */
2434 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2435 to indirectly and hence must have all eliminations at their
2437 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2438 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2439 set_label_offsets (XEXP (tem, 0), insn, 1);
2445 /* Each of the labels in the parallel or address vector must be
2446 at their initial offsets. We want the first field for PARALLEL
2447 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2449 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2450 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2455 /* We only care about setting PC. If the source is not RETURN,
2456 IF_THEN_ELSE, or a label, disable any eliminations not at
2457 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2458 isn't one of those possibilities. For branches to a label,
2459 call ourselves recursively.
2461 Note that this can disable elimination unnecessarily when we have
2462 a non-local goto since it will look like a non-constant jump to
2463 someplace in the current function. This isn't a significant
2464 problem since such jumps will normally be when all elimination
2465 pairs are back to their initial offsets. */
2467 if (SET_DEST (x) != pc_rtx)
2470 switch (GET_CODE (SET_SRC (x)))
2477 set_label_offsets (SET_SRC (x), insn, initial_p);
2481 tem = XEXP (SET_SRC (x), 1);
2482 if (GET_CODE (tem) == LABEL_REF)
2483 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2484 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2487 tem = XEXP (SET_SRC (x), 2);
2488 if (GET_CODE (tem) == LABEL_REF)
2489 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2490 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2498 /* If we reach here, all eliminations must be at their initial
2499 offset because we are doing a jump to a variable address. */
2500 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2501 if (p->offset != p->initial_offset)
2502 p->can_eliminate = 0;
2510 /* Scan X and replace any eliminable registers (such as fp) with a
2511 replacement (such as sp), plus an offset.
2513 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2514 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2515 MEM, we are allowed to replace a sum of a register and the constant zero
2516 with the register, which we cannot do outside a MEM. In addition, we need
2517 to record the fact that a register is referenced outside a MEM.
2519 If INSN is an insn, it is the insn containing X. If we replace a REG
2520 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2521 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2522 the REG is being modified.
2524 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2525 That's used when we eliminate in expressions stored in notes.
2526 This means, do not set ref_outside_mem even if the reference
2529 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2530 replacements done assuming all offsets are at their initial values. If
2531 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2532 encounter, return the actual location so that find_reloads will do
2533 the proper thing. */
2536 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2537 bool may_use_invariant)
2539 enum rtx_code code = GET_CODE (x);
2540 struct elim_table *ep;
2547 if (! current_function_decl)
2570 /* First handle the case where we encounter a bare register that
2571 is eliminable. Replace it with a PLUS. */
2572 if (regno < FIRST_PSEUDO_REGISTER)
2574 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2576 if (ep->from_rtx == x && ep->can_eliminate)
2577 return plus_constant (ep->to_rtx, ep->previous_offset);
2580 else if (reg_renumber && reg_renumber[regno] < 0
2581 && reg_equiv_invariant && reg_equiv_invariant[regno])
2583 if (may_use_invariant)
2584 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2585 mem_mode, insn, true);
2586 /* There exists at least one use of REGNO that cannot be
2587 eliminated. Prevent the defining insn from being deleted. */
2588 reg_equiv_init[regno] = NULL_RTX;
2589 alter_reg (regno, -1, true);
2593 /* You might think handling MINUS in a manner similar to PLUS is a
2594 good idea. It is not. It has been tried multiple times and every
2595 time the change has had to have been reverted.
2597 Other parts of reload know a PLUS is special (gen_reload for example)
2598 and require special code to handle code a reloaded PLUS operand.
2600 Also consider backends where the flags register is clobbered by a
2601 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2602 lea instruction comes to mind). If we try to reload a MINUS, we
2603 may kill the flags register that was holding a useful value.
2605 So, please before trying to handle MINUS, consider reload as a
2606 whole instead of this little section as well as the backend issues. */
2608 /* If this is the sum of an eliminable register and a constant, rework
2610 if (REG_P (XEXP (x, 0))
2611 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2612 && CONSTANT_P (XEXP (x, 1)))
2614 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2616 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2618 /* The only time we want to replace a PLUS with a REG (this
2619 occurs when the constant operand of the PLUS is the negative
2620 of the offset) is when we are inside a MEM. We won't want
2621 to do so at other times because that would change the
2622 structure of the insn in a way that reload can't handle.
2623 We special-case the commonest situation in
2624 eliminate_regs_in_insn, so just replace a PLUS with a
2625 PLUS here, unless inside a MEM. */
2626 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2627 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2630 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2631 plus_constant (XEXP (x, 1),
2632 ep->previous_offset));
2635 /* If the register is not eliminable, we are done since the other
2636 operand is a constant. */
2640 /* If this is part of an address, we want to bring any constant to the
2641 outermost PLUS. We will do this by doing register replacement in
2642 our operands and seeing if a constant shows up in one of them.
2644 Note that there is no risk of modifying the structure of the insn,
2645 since we only get called for its operands, thus we are either
2646 modifying the address inside a MEM, or something like an address
2647 operand of a load-address insn. */
2650 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2651 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2653 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2655 /* If one side is a PLUS and the other side is a pseudo that
2656 didn't get a hard register but has a reg_equiv_constant,
2657 we must replace the constant here since it may no longer
2658 be in the position of any operand. */
2659 if (GET_CODE (new0) == PLUS && REG_P (new1)
2660 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2661 && reg_renumber[REGNO (new1)] < 0
2662 && reg_equiv_constant != 0
2663 && reg_equiv_constant[REGNO (new1)] != 0)
2664 new1 = reg_equiv_constant[REGNO (new1)];
2665 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2666 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2667 && reg_renumber[REGNO (new0)] < 0
2668 && reg_equiv_constant[REGNO (new0)] != 0)
2669 new0 = reg_equiv_constant[REGNO (new0)];
2671 new_rtx = form_sum (new0, new1);
2673 /* As above, if we are not inside a MEM we do not want to
2674 turn a PLUS into something else. We might try to do so here
2675 for an addition of 0 if we aren't optimizing. */
2676 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2677 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2685 /* If this is the product of an eliminable register and a
2686 constant, apply the distribute law and move the constant out
2687 so that we have (plus (mult ..) ..). This is needed in order
2688 to keep load-address insns valid. This case is pathological.
2689 We ignore the possibility of overflow here. */
2690 if (REG_P (XEXP (x, 0))
2691 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2692 && CONST_INT_P (XEXP (x, 1)))
2693 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2695 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2698 /* Refs inside notes don't count for this purpose. */
2699 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2700 || GET_CODE (insn) == INSN_LIST)))
2701 ep->ref_outside_mem = 1;
2704 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2705 ep->previous_offset * INTVAL (XEXP (x, 1)));
2708 /* ... fall through ... */
2712 /* See comments before PLUS about handling MINUS. */
2714 case DIV: case UDIV:
2715 case MOD: case UMOD:
2716 case AND: case IOR: case XOR:
2717 case ROTATERT: case ROTATE:
2718 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2720 case GE: case GT: case GEU: case GTU:
2721 case LE: case LT: case LEU: case LTU:
2723 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2724 rtx new1 = XEXP (x, 1)
2725 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2727 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2728 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2733 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2736 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2737 if (new_rtx != XEXP (x, 0))
2739 /* If this is a REG_DEAD note, it is not valid anymore.
2740 Using the eliminated version could result in creating a
2741 REG_DEAD note for the stack or frame pointer. */
2742 if (REG_NOTE_KIND (x) == REG_DEAD)
2744 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2747 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2751 /* ... fall through ... */
2754 /* Now do eliminations in the rest of the chain. If this was
2755 an EXPR_LIST, this might result in allocating more memory than is
2756 strictly needed, but it simplifies the code. */
2759 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2760 if (new_rtx != XEXP (x, 1))
2762 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2770 /* We do not support elimination of a register that is modified.
2771 elimination_effects has already make sure that this does not
2777 /* We do not support elimination of a register that is modified.
2778 elimination_effects has already make sure that this does not
2779 happen. The only remaining case we need to consider here is
2780 that the increment value may be an eliminable register. */
2781 if (GET_CODE (XEXP (x, 1)) == PLUS
2782 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2784 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2787 if (new_rtx != XEXP (XEXP (x, 1), 1))
2788 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2789 gen_rtx_PLUS (GET_MODE (x),
2790 XEXP (x, 0), new_rtx));
2794 case STRICT_LOW_PART:
2796 case SIGN_EXTEND: case ZERO_EXTEND:
2797 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2798 case FLOAT: case FIX:
2799 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2808 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2809 if (new_rtx != XEXP (x, 0))
2810 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2814 /* Similar to above processing, but preserve SUBREG_BYTE.
2815 Convert (subreg (mem)) to (mem) if not paradoxical.
2816 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2817 pseudo didn't get a hard reg, we must replace this with the
2818 eliminated version of the memory location because push_reload
2819 may do the replacement in certain circumstances. */
2820 if (REG_P (SUBREG_REG (x))
2821 && (GET_MODE_SIZE (GET_MODE (x))
2822 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2823 && reg_equiv_memory_loc != 0
2824 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2826 new_rtx = SUBREG_REG (x);
2829 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2831 if (new_rtx != SUBREG_REG (x))
2833 int x_size = GET_MODE_SIZE (GET_MODE (x));
2834 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2837 && ((x_size < new_size
2838 #ifdef WORD_REGISTER_OPERATIONS
2839 /* On these machines, combine can create rtl of the form
2840 (set (subreg:m1 (reg:m2 R) 0) ...)
2841 where m1 < m2, and expects something interesting to
2842 happen to the entire word. Moreover, it will use the
2843 (reg:m2 R) later, expecting all bits to be preserved.
2844 So if the number of words is the same, preserve the
2845 subreg so that push_reload can see it. */
2846 && ! ((x_size - 1) / UNITS_PER_WORD
2847 == (new_size -1 ) / UNITS_PER_WORD)
2850 || x_size == new_size)
2852 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2854 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2860 /* Our only special processing is to pass the mode of the MEM to our
2861 recursive call and copy the flags. While we are here, handle this
2862 case more efficiently. */
2864 replace_equiv_address_nv (x,
2865 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2869 /* Handle insn_list USE that a call to a pure function may generate. */
2870 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2871 if (new_rtx != XEXP (x, 0))
2872 return gen_rtx_USE (GET_MODE (x), new_rtx);
2884 /* Process each of our operands recursively. If any have changed, make a
2886 fmt = GET_RTX_FORMAT (code);
2887 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2891 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2892 if (new_rtx != XEXP (x, i) && ! copied)
2894 x = shallow_copy_rtx (x);
2897 XEXP (x, i) = new_rtx;
2899 else if (*fmt == 'E')
2902 for (j = 0; j < XVECLEN (x, i); j++)
2904 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2905 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2907 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2911 x = shallow_copy_rtx (x);
2914 XVEC (x, i) = new_v;
2917 XVECEXP (x, i, j) = new_rtx;
2926 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2928 return eliminate_regs_1 (x, mem_mode, insn, false);
2931 /* Scan rtx X for modifications of elimination target registers. Update
2932 the table of eliminables to reflect the changed state. MEM_MODE is
2933 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2936 elimination_effects (rtx x, enum machine_mode mem_mode)
2938 enum rtx_code code = GET_CODE (x);
2939 struct elim_table *ep;
2964 /* First handle the case where we encounter a bare register that
2965 is eliminable. Replace it with a PLUS. */
2966 if (regno < FIRST_PSEUDO_REGISTER)
2968 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2970 if (ep->from_rtx == x && ep->can_eliminate)
2973 ep->ref_outside_mem = 1;
2978 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2979 && reg_equiv_constant[regno]
2980 && ! function_invariant_p (reg_equiv_constant[regno]))
2981 elimination_effects (reg_equiv_constant[regno], mem_mode);
2990 /* If we modify the source of an elimination rule, disable it. */
2991 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2992 if (ep->from_rtx == XEXP (x, 0))
2993 ep->can_eliminate = 0;
2995 /* If we modify the target of an elimination rule by adding a constant,
2996 update its offset. If we modify the target in any other way, we'll
2997 have to disable the rule as well. */
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2999 if (ep->to_rtx == XEXP (x, 0))
3001 int size = GET_MODE_SIZE (mem_mode);
3003 /* If more bytes than MEM_MODE are pushed, account for them. */
3004 #ifdef PUSH_ROUNDING
3005 if (ep->to_rtx == stack_pointer_rtx)
3006 size = PUSH_ROUNDING (size);
3008 if (code == PRE_DEC || code == POST_DEC)
3010 else if (code == PRE_INC || code == POST_INC)
3012 else if (code == PRE_MODIFY || code == POST_MODIFY)
3014 if (GET_CODE (XEXP (x, 1)) == PLUS
3015 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3016 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3017 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3019 ep->can_eliminate = 0;
3023 /* These two aren't unary operators. */
3024 if (code == POST_MODIFY || code == PRE_MODIFY)
3027 /* Fall through to generic unary operation case. */
3028 case STRICT_LOW_PART:
3030 case SIGN_EXTEND: case ZERO_EXTEND:
3031 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3032 case FLOAT: case FIX:
3033 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3042 elimination_effects (XEXP (x, 0), mem_mode);
3046 if (REG_P (SUBREG_REG (x))
3047 && (GET_MODE_SIZE (GET_MODE (x))
3048 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3049 && reg_equiv_memory_loc != 0
3050 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3053 elimination_effects (SUBREG_REG (x), mem_mode);
3057 /* If using a register that is the source of an eliminate we still
3058 think can be performed, note it cannot be performed since we don't
3059 know how this register is used. */
3060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3061 if (ep->from_rtx == XEXP (x, 0))
3062 ep->can_eliminate = 0;
3064 elimination_effects (XEXP (x, 0), mem_mode);
3068 /* If clobbering a register that is the replacement register for an
3069 elimination we still think can be performed, note that it cannot
3070 be performed. Otherwise, we need not be concerned about it. */
3071 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3072 if (ep->to_rtx == XEXP (x, 0))
3073 ep->can_eliminate = 0;
3075 elimination_effects (XEXP (x, 0), mem_mode);
3079 /* Check for setting a register that we know about. */
3080 if (REG_P (SET_DEST (x)))
3082 /* See if this is setting the replacement register for an
3085 If DEST is the hard frame pointer, we do nothing because we
3086 assume that all assignments to the frame pointer are for
3087 non-local gotos and are being done at a time when they are valid
3088 and do not disturb anything else. Some machines want to
3089 eliminate a fake argument pointer (or even a fake frame pointer)
3090 with either the real frame or the stack pointer. Assignments to
3091 the hard frame pointer must not prevent this elimination. */
3093 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3095 if (ep->to_rtx == SET_DEST (x)
3096 && SET_DEST (x) != hard_frame_pointer_rtx)
3098 /* If it is being incremented, adjust the offset. Otherwise,
3099 this elimination can't be done. */
3100 rtx src = SET_SRC (x);
3102 if (GET_CODE (src) == PLUS
3103 && XEXP (src, 0) == SET_DEST (x)
3104 && CONST_INT_P (XEXP (src, 1)))
3105 ep->offset -= INTVAL (XEXP (src, 1));
3107 ep->can_eliminate = 0;
3111 elimination_effects (SET_DEST (x), VOIDmode);
3112 elimination_effects (SET_SRC (x), VOIDmode);
3116 /* Our only special processing is to pass the mode of the MEM to our
3118 elimination_effects (XEXP (x, 0), GET_MODE (x));
3125 fmt = GET_RTX_FORMAT (code);
3126 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3129 elimination_effects (XEXP (x, i), mem_mode);
3130 else if (*fmt == 'E')
3131 for (j = 0; j < XVECLEN (x, i); j++)
3132 elimination_effects (XVECEXP (x, i, j), mem_mode);
3136 /* Descend through rtx X and verify that no references to eliminable registers
3137 remain. If any do remain, mark the involved register as not
3141 check_eliminable_occurrences (rtx x)
3150 code = GET_CODE (x);
3152 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3154 struct elim_table *ep;
3156 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3157 if (ep->from_rtx == x)
3158 ep->can_eliminate = 0;
3162 fmt = GET_RTX_FORMAT (code);
3163 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3166 check_eliminable_occurrences (XEXP (x, i));
3167 else if (*fmt == 'E')
3170 for (j = 0; j < XVECLEN (x, i); j++)
3171 check_eliminable_occurrences (XVECEXP (x, i, j));
3176 /* Scan INSN and eliminate all eliminable registers in it.
3178 If REPLACE is nonzero, do the replacement destructively. Also
3179 delete the insn as dead it if it is setting an eliminable register.
3181 If REPLACE is zero, do all our allocations in reload_obstack.
3183 If no eliminations were done and this insn doesn't require any elimination
3184 processing (these are not identical conditions: it might be updating sp,
3185 but not referencing fp; this needs to be seen during reload_as_needed so
3186 that the offset between fp and sp can be taken into consideration), zero
3187 is returned. Otherwise, 1 is returned. */
3190 eliminate_regs_in_insn (rtx insn, int replace)
3192 int icode = recog_memoized (insn);
3193 rtx old_body = PATTERN (insn);
3194 int insn_is_asm = asm_noperands (old_body) >= 0;
3195 rtx old_set = single_set (insn);
3199 rtx substed_operand[MAX_RECOG_OPERANDS];
3200 rtx orig_operand[MAX_RECOG_OPERANDS];
3201 struct elim_table *ep;
3202 rtx plus_src, plus_cst_src;
3204 if (! insn_is_asm && icode < 0)
3206 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3207 || GET_CODE (PATTERN (insn)) == CLOBBER
3208 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3209 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3210 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3211 || DEBUG_INSN_P (insn));
3215 if (old_set != 0 && REG_P (SET_DEST (old_set))
3216 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3218 /* Check for setting an eliminable register. */
3219 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3220 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3222 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3223 /* If this is setting the frame pointer register to the
3224 hardware frame pointer register and this is an elimination
3225 that will be done (tested above), this insn is really
3226 adjusting the frame pointer downward to compensate for
3227 the adjustment done before a nonlocal goto. */
3228 if (ep->from == FRAME_POINTER_REGNUM
3229 && ep->to == HARD_FRAME_POINTER_REGNUM)
3231 rtx base = SET_SRC (old_set);
3232 rtx base_insn = insn;
3233 HOST_WIDE_INT offset = 0;
3235 while (base != ep->to_rtx)
3237 rtx prev_insn, prev_set;
3239 if (GET_CODE (base) == PLUS
3240 && CONST_INT_P (XEXP (base, 1)))
3242 offset += INTVAL (XEXP (base, 1));
3243 base = XEXP (base, 0);
3245 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3246 && (prev_set = single_set (prev_insn)) != 0
3247 && rtx_equal_p (SET_DEST (prev_set), base))
3249 base = SET_SRC (prev_set);
3250 base_insn = prev_insn;
3256 if (base == ep->to_rtx)
3259 = plus_constant (ep->to_rtx, offset - ep->offset);
3261 new_body = old_body;
3264 new_body = copy_insn (old_body);
3265 if (REG_NOTES (insn))
3266 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3268 PATTERN (insn) = new_body;
3269 old_set = single_set (insn);
3271 /* First see if this insn remains valid when we
3272 make the change. If not, keep the INSN_CODE
3273 the same and let reload fit it up. */
3274 validate_change (insn, &SET_SRC (old_set), src, 1);
3275 validate_change (insn, &SET_DEST (old_set),
3277 if (! apply_change_group ())
3279 SET_SRC (old_set) = src;
3280 SET_DEST (old_set) = ep->to_rtx;
3289 /* In this case this insn isn't serving a useful purpose. We
3290 will delete it in reload_as_needed once we know that this
3291 elimination is, in fact, being done.
3293 If REPLACE isn't set, we can't delete this insn, but needn't
3294 process it since it won't be used unless something changes. */
3297 delete_dead_insn (insn);
3305 /* We allow one special case which happens to work on all machines we
3306 currently support: a single set with the source or a REG_EQUAL
3307 note being a PLUS of an eliminable register and a constant. */
3308 plus_src = plus_cst_src = 0;
3309 if (old_set && REG_P (SET_DEST (old_set)))
3311 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3312 plus_src = SET_SRC (old_set);
3313 /* First see if the source is of the form (plus (...) CST). */
3315 && CONST_INT_P (XEXP (plus_src, 1)))
3316 plus_cst_src = plus_src;
3317 else if (REG_P (SET_SRC (old_set))
3320 /* Otherwise, see if we have a REG_EQUAL note of the form
3321 (plus (...) CST). */
3323 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3325 if ((REG_NOTE_KIND (links) == REG_EQUAL
3326 || REG_NOTE_KIND (links) == REG_EQUIV)
3327 && GET_CODE (XEXP (links, 0)) == PLUS
3328 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3330 plus_cst_src = XEXP (links, 0);
3336 /* Check that the first operand of the PLUS is a hard reg or
3337 the lowpart subreg of one. */
3340 rtx reg = XEXP (plus_cst_src, 0);
3341 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3342 reg = SUBREG_REG (reg);
3344 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3350 rtx reg = XEXP (plus_cst_src, 0);
3351 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3353 if (GET_CODE (reg) == SUBREG)
3354 reg = SUBREG_REG (reg);
3356 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3357 if (ep->from_rtx == reg && ep->can_eliminate)
3359 rtx to_rtx = ep->to_rtx;
3360 offset += ep->offset;
3361 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3363 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3364 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3366 /* If we have a nonzero offset, and the source is already
3367 a simple REG, the following transformation would
3368 increase the cost of the insn by replacing a simple REG
3369 with (plus (reg sp) CST). So try only when we already
3370 had a PLUS before. */
3371 if (offset == 0 || plus_src)
3373 rtx new_src = plus_constant (to_rtx, offset);
3375 new_body = old_body;
3378 new_body = copy_insn (old_body);
3379 if (REG_NOTES (insn))
3380 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3382 PATTERN (insn) = new_body;
3383 old_set = single_set (insn);
3385 /* First see if this insn remains valid when we make the
3386 change. If not, try to replace the whole pattern with
3387 a simple set (this may help if the original insn was a
3388 PARALLEL that was only recognized as single_set due to
3389 REG_UNUSED notes). If this isn't valid either, keep
3390 the INSN_CODE the same and let reload fix it up. */
3391 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3393 rtx new_pat = gen_rtx_SET (VOIDmode,
3394 SET_DEST (old_set), new_src);
3396 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3397 SET_SRC (old_set) = new_src;
3404 /* This can't have an effect on elimination offsets, so skip right
3410 /* Determine the effects of this insn on elimination offsets. */
3411 elimination_effects (old_body, VOIDmode);
3413 /* Eliminate all eliminable registers occurring in operands that
3414 can be handled by reload. */
3415 extract_insn (insn);
3416 for (i = 0; i < recog_data.n_operands; i++)
3418 orig_operand[i] = recog_data.operand[i];
3419 substed_operand[i] = recog_data.operand[i];
3421 /* For an asm statement, every operand is eliminable. */
3422 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3424 bool is_set_src, in_plus;
3426 /* Check for setting a register that we know about. */
3427 if (recog_data.operand_type[i] != OP_IN
3428 && REG_P (orig_operand[i]))
3430 /* If we are assigning to a register that can be eliminated, it
3431 must be as part of a PARALLEL, since the code above handles
3432 single SETs. We must indicate that we can no longer
3433 eliminate this reg. */
3434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3436 if (ep->from_rtx == orig_operand[i])
3437 ep->can_eliminate = 0;
3440 /* Companion to the above plus substitution, we can allow
3441 invariants as the source of a plain move. */
3443 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3447 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3448 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3452 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3453 replace ? insn : NULL_RTX,
3454 is_set_src || in_plus);
3455 if (substed_operand[i] != orig_operand[i])
3457 /* Terminate the search in check_eliminable_occurrences at
3459 *recog_data.operand_loc[i] = 0;
3461 /* If an output operand changed from a REG to a MEM and INSN is an
3462 insn, write a CLOBBER insn. */
3463 if (recog_data.operand_type[i] != OP_IN
3464 && REG_P (orig_operand[i])
3465 && MEM_P (substed_operand[i])
3467 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3471 for (i = 0; i < recog_data.n_dups; i++)
3472 *recog_data.dup_loc[i]
3473 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3475 /* If any eliminable remain, they aren't eliminable anymore. */
3476 check_eliminable_occurrences (old_body);
3478 /* Substitute the operands; the new values are in the substed_operand
3480 for (i = 0; i < recog_data.n_operands; i++)
3481 *recog_data.operand_loc[i] = substed_operand[i];
3482 for (i = 0; i < recog_data.n_dups; i++)
3483 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3485 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3486 re-recognize the insn. We do this in case we had a simple addition
3487 but now can do this as a load-address. This saves an insn in this
3489 If re-recognition fails, the old insn code number will still be used,
3490 and some register operands may have changed into PLUS expressions.
3491 These will be handled by find_reloads by loading them into a register
3496 /* If we aren't replacing things permanently and we changed something,
3497 make another copy to ensure that all the RTL is new. Otherwise
3498 things can go wrong if find_reload swaps commutative operands
3499 and one is inside RTL that has been copied while the other is not. */
3500 new_body = old_body;
3503 new_body = copy_insn (old_body);
3504 if (REG_NOTES (insn))
3505 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3507 PATTERN (insn) = new_body;
3509 /* If we had a move insn but now we don't, rerecognize it. This will
3510 cause spurious re-recognition if the old move had a PARALLEL since
3511 the new one still will, but we can't call single_set without
3512 having put NEW_BODY into the insn and the re-recognition won't
3513 hurt in this rare case. */
3514 /* ??? Why this huge if statement - why don't we just rerecognize the
3518 && ((REG_P (SET_SRC (old_set))
3519 && (GET_CODE (new_body) != SET
3520 || !REG_P (SET_SRC (new_body))))
3521 /* If this was a load from or store to memory, compare
3522 the MEM in recog_data.operand to the one in the insn.
3523 If they are not equal, then rerecognize the insn. */
3525 && ((MEM_P (SET_SRC (old_set))
3526 && SET_SRC (old_set) != recog_data.operand[1])
3527 || (MEM_P (SET_DEST (old_set))
3528 && SET_DEST (old_set) != recog_data.operand[0])))
3529 /* If this was an add insn before, rerecognize. */
3530 || GET_CODE (SET_SRC (old_set)) == PLUS))
3532 int new_icode = recog (PATTERN (insn), insn, 0);
3534 INSN_CODE (insn) = new_icode;
3538 /* Restore the old body. If there were any changes to it, we made a copy
3539 of it while the changes were still in place, so we'll correctly return
3540 a modified insn below. */
3543 /* Restore the old body. */
3544 for (i = 0; i < recog_data.n_operands; i++)
3545 *recog_data.operand_loc[i] = orig_operand[i];
3546 for (i = 0; i < recog_data.n_dups; i++)
3547 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3550 /* Update all elimination pairs to reflect the status after the current
3551 insn. The changes we make were determined by the earlier call to
3552 elimination_effects.
3554 We also detect cases where register elimination cannot be done,
3555 namely, if a register would be both changed and referenced outside a MEM
3556 in the resulting insn since such an insn is often undefined and, even if
3557 not, we cannot know what meaning will be given to it. Note that it is
3558 valid to have a register used in an address in an insn that changes it
3559 (presumably with a pre- or post-increment or decrement).
3561 If anything changes, return nonzero. */
3563 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3565 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3566 ep->can_eliminate = 0;
3568 ep->ref_outside_mem = 0;
3570 if (ep->previous_offset != ep->offset)
3575 /* If we changed something, perform elimination in REG_NOTES. This is
3576 needed even when REPLACE is zero because a REG_DEAD note might refer
3577 to a register that we eliminate and could cause a different number
3578 of spill registers to be needed in the final reload pass than in
3580 if (val && REG_NOTES (insn) != 0)
3582 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3587 /* Loop through all elimination pairs.
3588 Recalculate the number not at initial offset.
3590 Compute the maximum offset (minimum offset if the stack does not
3591 grow downward) for each elimination pair. */
3594 update_eliminable_offsets (void)
3596 struct elim_table *ep;
3598 num_not_at_initial_offset = 0;
3599 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3601 ep->previous_offset = ep->offset;
3602 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3603 num_not_at_initial_offset++;
3607 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3608 replacement we currently believe is valid, mark it as not eliminable if X
3609 modifies DEST in any way other than by adding a constant integer to it.
3611 If DEST is the frame pointer, we do nothing because we assume that
3612 all assignments to the hard frame pointer are nonlocal gotos and are being
3613 done at a time when they are valid and do not disturb anything else.
3614 Some machines want to eliminate a fake argument pointer with either the
3615 frame or stack pointer. Assignments to the hard frame pointer must not
3616 prevent this elimination.
3618 Called via note_stores from reload before starting its passes to scan
3619 the insns of the function. */
3622 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3626 /* A SUBREG of a hard register here is just changing its mode. We should
3627 not see a SUBREG of an eliminable hard register, but check just in
3629 if (GET_CODE (dest) == SUBREG)
3630 dest = SUBREG_REG (dest);
3632 if (dest == hard_frame_pointer_rtx)
3635 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3636 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3637 && (GET_CODE (x) != SET
3638 || GET_CODE (SET_SRC (x)) != PLUS
3639 || XEXP (SET_SRC (x), 0) != dest
3640 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3642 reg_eliminate[i].can_eliminate_previous
3643 = reg_eliminate[i].can_eliminate = 0;
3648 /* Verify that the initial elimination offsets did not change since the
3649 last call to set_initial_elim_offsets. This is used to catch cases
3650 where something illegal happened during reload_as_needed that could
3651 cause incorrect code to be generated if we did not check for it. */
3654 verify_initial_elim_offsets (void)
3658 if (!num_eliminable)
3661 #ifdef ELIMINABLE_REGS
3663 struct elim_table *ep;
3665 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3667 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3668 if (t != ep->initial_offset)
3673 INITIAL_FRAME_POINTER_OFFSET (t);
3674 if (t != reg_eliminate[0].initial_offset)
3681 /* Reset all offsets on eliminable registers to their initial values. */
3684 set_initial_elim_offsets (void)
3686 struct elim_table *ep = reg_eliminate;
3688 #ifdef ELIMINABLE_REGS
3689 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3691 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3692 ep->previous_offset = ep->offset = ep->initial_offset;
3695 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3696 ep->previous_offset = ep->offset = ep->initial_offset;
3699 num_not_at_initial_offset = 0;
3702 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3705 set_initial_eh_label_offset (rtx label)
3707 set_label_offsets (label, NULL_RTX, 1);
3710 /* Initialize the known label offsets.
3711 Set a known offset for each forced label to be at the initial offset
3712 of each elimination. We do this because we assume that all
3713 computed jumps occur from a location where each elimination is
3714 at its initial offset.
3715 For all other labels, show that we don't know the offsets. */
3718 set_initial_label_offsets (void)
3721 memset (offsets_known_at, 0, num_labels);
3723 for (x = forced_labels; x; x = XEXP (x, 1))
3725 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3727 for_each_eh_label (set_initial_eh_label_offset);
3730 /* Set all elimination offsets to the known values for the code label given
3734 set_offsets_for_label (rtx insn)
3737 int label_nr = CODE_LABEL_NUMBER (insn);
3738 struct elim_table *ep;
3740 num_not_at_initial_offset = 0;
3741 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3743 ep->offset = ep->previous_offset
3744 = offsets_at[label_nr - first_label_num][i];
3745 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3746 num_not_at_initial_offset++;
3750 /* See if anything that happened changes which eliminations are valid.
3751 For example, on the SPARC, whether or not the frame pointer can
3752 be eliminated can depend on what registers have been used. We need
3753 not check some conditions again (such as flag_omit_frame_pointer)
3754 since they can't have changed. */
3757 update_eliminables (HARD_REG_SET *pset)
3759 int previous_frame_pointer_needed = frame_pointer_needed;
3760 struct elim_table *ep;
3762 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3763 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3764 && targetm.frame_pointer_required ())
3765 #ifdef ELIMINABLE_REGS
3766 || ! targetm.can_eliminate (ep->from, ep->to)
3769 ep->can_eliminate = 0;
3771 /* Look for the case where we have discovered that we can't replace
3772 register A with register B and that means that we will now be
3773 trying to replace register A with register C. This means we can
3774 no longer replace register C with register B and we need to disable
3775 such an elimination, if it exists. This occurs often with A == ap,
3776 B == sp, and C == fp. */
3778 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3780 struct elim_table *op;
3783 if (! ep->can_eliminate && ep->can_eliminate_previous)
3785 /* Find the current elimination for ep->from, if there is a
3787 for (op = reg_eliminate;
3788 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3789 if (op->from == ep->from && op->can_eliminate)
3795 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3797 for (op = reg_eliminate;
3798 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3799 if (op->from == new_to && op->to == ep->to)
3800 op->can_eliminate = 0;
3804 /* See if any registers that we thought we could eliminate the previous
3805 time are no longer eliminable. If so, something has changed and we
3806 must spill the register. Also, recompute the number of eliminable
3807 registers and see if the frame pointer is needed; it is if there is
3808 no elimination of the frame pointer that we can perform. */
3810 frame_pointer_needed = 1;
3811 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3813 if (ep->can_eliminate
3814 && ep->from == FRAME_POINTER_REGNUM
3815 && ep->to != HARD_FRAME_POINTER_REGNUM
3816 && (! SUPPORTS_STACK_ALIGNMENT
3817 || ! crtl->stack_realign_needed))
3818 frame_pointer_needed = 0;
3820 if (! ep->can_eliminate && ep->can_eliminate_previous)
3822 ep->can_eliminate_previous = 0;
3823 SET_HARD_REG_BIT (*pset, ep->from);
3828 /* If we didn't need a frame pointer last time, but we do now, spill
3829 the hard frame pointer. */
3830 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3831 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3834 /* Return true if X is used as the target register of an elimination. */
3837 elimination_target_reg_p (rtx x)
3839 struct elim_table *ep;
3841 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3842 if (ep->to_rtx == x && ep->can_eliminate)
3848 /* Initialize the table of registers to eliminate.
3849 Pre-condition: global flag frame_pointer_needed has been set before
3850 calling this function. */
3853 init_elim_table (void)
3855 struct elim_table *ep;
3856 #ifdef ELIMINABLE_REGS
3857 const struct elim_table_1 *ep1;
3861 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3865 #ifdef ELIMINABLE_REGS
3866 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3867 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3869 ep->from = ep1->from;
3871 ep->can_eliminate = ep->can_eliminate_previous
3872 = (targetm.can_eliminate (ep->from, ep->to)
3873 && ! (ep->to == STACK_POINTER_REGNUM
3874 && frame_pointer_needed
3875 && (! SUPPORTS_STACK_ALIGNMENT
3876 || ! stack_realign_fp)));
3879 reg_eliminate[0].from = reg_eliminate_1[0].from;
3880 reg_eliminate[0].to = reg_eliminate_1[0].to;
3881 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3882 = ! frame_pointer_needed;
3885 /* Count the number of eliminable registers and build the FROM and TO
3886 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3887 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3888 We depend on this. */
3889 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3891 num_eliminable += ep->can_eliminate;
3892 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3893 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3897 /* Kick all pseudos out of hard register REGNO.
3899 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3900 because we found we can't eliminate some register. In the case, no pseudos
3901 are allowed to be in the register, even if they are only in a block that
3902 doesn't require spill registers, unlike the case when we are spilling this
3903 hard reg to produce another spill register.
3905 Return nonzero if any pseudos needed to be kicked out. */
3908 spill_hard_reg (unsigned int regno, int cant_eliminate)
3914 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3915 df_set_regs_ever_live (regno, true);
3918 /* Spill every pseudo reg that was allocated to this reg
3919 or to something that overlaps this reg. */
3921 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3922 if (reg_renumber[i] >= 0
3923 && (unsigned int) reg_renumber[i] <= regno
3924 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3925 SET_REGNO_REG_SET (&spilled_pseudos, i);
3928 /* After find_reload_regs has been run for all insn that need reloads,
3929 and/or spill_hard_regs was called, this function is used to actually
3930 spill pseudo registers and try to reallocate them. It also sets up the
3931 spill_regs array for use by choose_reload_regs. */
3934 finish_spills (int global)
3936 struct insn_chain *chain;
3937 int something_changed = 0;
3939 reg_set_iterator rsi;
3941 /* Build the spill_regs array for the function. */
3942 /* If there are some registers still to eliminate and one of the spill regs
3943 wasn't ever used before, additional stack space may have to be
3944 allocated to store this register. Thus, we may have changed the offset
3945 between the stack and frame pointers, so mark that something has changed.
3947 One might think that we need only set VAL to 1 if this is a call-used
3948 register. However, the set of registers that must be saved by the
3949 prologue is not identical to the call-used set. For example, the
3950 register used by the call insn for the return PC is a call-used register,
3951 but must be saved by the prologue. */
3954 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3955 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3957 spill_reg_order[i] = n_spills;
3958 spill_regs[n_spills++] = i;
3959 if (num_eliminable && ! df_regs_ever_live_p (i))
3960 something_changed = 1;
3961 df_set_regs_ever_live (i, true);
3964 spill_reg_order[i] = -1;
3966 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3967 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3969 /* Record the current hard register the pseudo is allocated to
3970 in pseudo_previous_regs so we avoid reallocating it to the
3971 same hard reg in a later pass. */
3972 gcc_assert (reg_renumber[i] >= 0);
3974 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3975 /* Mark it as no longer having a hard register home. */
3976 reg_renumber[i] = -1;
3977 if (ira_conflicts_p)
3978 /* Inform IRA about the change. */
3979 ira_mark_allocation_change (i);
3980 /* We will need to scan everything again. */
3981 something_changed = 1;
3984 /* Retry global register allocation if possible. */
3985 if (global && ira_conflicts_p)
3989 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3990 /* For every insn that needs reloads, set the registers used as spill
3991 regs in pseudo_forbidden_regs for every pseudo live across the
3993 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3995 EXECUTE_IF_SET_IN_REG_SET
3996 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3998 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3999 chain->used_spill_regs);
4001 EXECUTE_IF_SET_IN_REG_SET
4002 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4004 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4005 chain->used_spill_regs);
4009 /* Retry allocating the pseudos spilled in IRA and the
4010 reload. For each reg, merge the various reg sets that
4011 indicate which hard regs can't be used, and call
4012 ira_reassign_pseudos. */
4013 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4014 if (reg_old_renumber[i] != reg_renumber[i])
4016 if (reg_renumber[i] < 0)
4017 temp_pseudo_reg_arr[n++] = i;
4019 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4021 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4022 bad_spill_regs_global,
4023 pseudo_forbidden_regs, pseudo_previous_regs,
4025 something_changed = 1;
4027 /* Fix up the register information in the insn chain.
4028 This involves deleting those of the spilled pseudos which did not get
4029 a new hard register home from the live_{before,after} sets. */
4030 for (chain = reload_insn_chain; chain; chain = chain->next)
4032 HARD_REG_SET used_by_pseudos;
4033 HARD_REG_SET used_by_pseudos2;
4035 if (! ira_conflicts_p)
4037 /* Don't do it for IRA because IRA and the reload still can
4038 assign hard registers to the spilled pseudos on next
4039 reload iterations. */
4040 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4041 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4043 /* Mark any unallocated hard regs as available for spills. That
4044 makes inheritance work somewhat better. */
4045 if (chain->need_reload)
4047 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4048 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4049 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4051 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4052 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4053 /* Value of chain->used_spill_regs from previous iteration
4054 may be not included in the value calculated here because
4055 of possible removing caller-saves insns (see function
4056 delete_caller_save_insns. */
4057 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4058 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4062 CLEAR_REG_SET (&changed_allocation_pseudos);
4063 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4064 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4066 int regno = reg_renumber[i];
4067 if (reg_old_renumber[i] == regno)
4070 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4072 alter_reg (i, reg_old_renumber[i], false);
4073 reg_old_renumber[i] = regno;
4077 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4079 fprintf (dump_file, " Register %d now in %d.\n\n",
4080 i, reg_renumber[i]);
4084 return something_changed;
4087 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4090 scan_paradoxical_subregs (rtx x)
4094 enum rtx_code code = GET_CODE (x);
4105 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4113 if (REG_P (SUBREG_REG (x))
4114 && (GET_MODE_SIZE (GET_MODE (x))
4115 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4117 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4118 = GET_MODE_SIZE (GET_MODE (x));
4119 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4127 fmt = GET_RTX_FORMAT (code);
4128 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4131 scan_paradoxical_subregs (XEXP (x, i));
4132 else if (fmt[i] == 'E')
4135 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4136 scan_paradoxical_subregs (XVECEXP (x, i, j));
4141 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4142 examine all of the reload insns between PREV and NEXT exclusive, and
4143 annotate all that may trap. */
4146 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4148 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4151 if (!insn_could_throw_p (insn))
4152 remove_note (insn, note);
4153 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4156 /* Reload pseudo-registers into hard regs around each insn as needed.
4157 Additional register load insns are output before the insn that needs it
4158 and perhaps store insns after insns that modify the reloaded pseudo reg.
4160 reg_last_reload_reg and reg_reloaded_contents keep track of
4161 which registers are already available in reload registers.
4162 We update these for the reloads that we perform,
4163 as the insns are scanned. */
4166 reload_as_needed (int live_known)
4168 struct insn_chain *chain;
4169 #if defined (AUTO_INC_DEC)
4174 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4175 memset (spill_reg_store, 0, sizeof spill_reg_store);
4176 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4177 INIT_REG_SET (®_has_output_reload);
4178 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4179 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4181 set_initial_elim_offsets ();
4183 for (chain = reload_insn_chain; chain; chain = chain->next)
4186 rtx insn = chain->insn;
4187 rtx old_next = NEXT_INSN (insn);
4189 rtx old_prev = PREV_INSN (insn);
4192 /* If we pass a label, copy the offsets from the label information
4193 into the current offsets of each elimination. */
4195 set_offsets_for_label (insn);
4197 else if (INSN_P (insn))
4199 regset_head regs_to_forget;
4200 INIT_REG_SET (®s_to_forget);
4201 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4203 /* If this is a USE and CLOBBER of a MEM, ensure that any
4204 references to eliminable registers have been removed. */
4206 if ((GET_CODE (PATTERN (insn)) == USE
4207 || GET_CODE (PATTERN (insn)) == CLOBBER)
4208 && MEM_P (XEXP (PATTERN (insn), 0)))
4209 XEXP (XEXP (PATTERN (insn), 0), 0)
4210 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4211 GET_MODE (XEXP (PATTERN (insn), 0)),
4214 /* If we need to do register elimination processing, do so.
4215 This might delete the insn, in which case we are done. */
4216 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4218 eliminate_regs_in_insn (insn, 1);
4221 update_eliminable_offsets ();
4222 CLEAR_REG_SET (®s_to_forget);
4227 /* If need_elim is nonzero but need_reload is zero, one might think
4228 that we could simply set n_reloads to 0. However, find_reloads
4229 could have done some manipulation of the insn (such as swapping
4230 commutative operands), and these manipulations are lost during
4231 the first pass for every insn that needs register elimination.
4232 So the actions of find_reloads must be redone here. */
4234 if (! chain->need_elim && ! chain->need_reload
4235 && ! chain->need_operand_change)
4237 /* First find the pseudo regs that must be reloaded for this insn.
4238 This info is returned in the tables reload_... (see reload.h).
4239 Also modify the body of INSN by substituting RELOAD
4240 rtx's for those pseudo regs. */
4243 CLEAR_REG_SET (®_has_output_reload);
4244 CLEAR_HARD_REG_SET (reg_is_output_reload);
4246 find_reloads (insn, 1, spill_indirect_levels, live_known,
4252 rtx next = NEXT_INSN (insn);
4255 prev = PREV_INSN (insn);
4257 /* Now compute which reload regs to reload them into. Perhaps
4258 reusing reload regs from previous insns, or else output
4259 load insns to reload them. Maybe output store insns too.
4260 Record the choices of reload reg in reload_reg_rtx. */
4261 choose_reload_regs (chain);
4263 /* Merge any reloads that we didn't combine for fear of
4264 increasing the number of spill registers needed but now
4265 discover can be safely merged. */
4266 if (SMALL_REGISTER_CLASSES)
4267 merge_assigned_reloads (insn);
4269 /* Generate the insns to reload operands into or out of
4270 their reload regs. */
4271 emit_reload_insns (chain);
4273 /* Substitute the chosen reload regs from reload_reg_rtx
4274 into the insn's body (or perhaps into the bodies of other
4275 load and store insn that we just made for reloading
4276 and that we moved the structure into). */
4277 subst_reloads (insn);
4279 /* Adjust the exception region notes for loads and stores. */
4280 if (flag_non_call_exceptions && !CALL_P (insn))
4281 fixup_eh_region_note (insn, prev, next);
4283 /* If this was an ASM, make sure that all the reload insns
4284 we have generated are valid. If not, give an error
4286 if (asm_noperands (PATTERN (insn)) >= 0)
4287 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4288 if (p != insn && INSN_P (p)
4289 && GET_CODE (PATTERN (p)) != USE
4290 && (recog_memoized (p) < 0
4291 || (extract_insn (p), ! constrain_operands (1))))
4293 error_for_asm (insn,
4294 "%<asm%> operand requires "
4295 "impossible reload");
4300 if (num_eliminable && chain->need_elim)
4301 update_eliminable_offsets ();
4303 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4304 is no longer validly lying around to save a future reload.
4305 Note that this does not detect pseudos that were reloaded
4306 for this insn in order to be stored in
4307 (obeying register constraints). That is correct; such reload
4308 registers ARE still valid. */
4309 forget_marked_reloads (®s_to_forget);
4310 CLEAR_REG_SET (®s_to_forget);
4312 /* There may have been CLOBBER insns placed after INSN. So scan
4313 between INSN and NEXT and use them to forget old reloads. */
4314 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4315 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4316 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4319 /* Likewise for regs altered by auto-increment in this insn.
4320 REG_INC notes have been changed by reloading:
4321 find_reloads_address_1 records substitutions for them,
4322 which have been performed by subst_reloads above. */
4323 for (i = n_reloads - 1; i >= 0; i--)
4325 rtx in_reg = rld[i].in_reg;
4328 enum rtx_code code = GET_CODE (in_reg);
4329 /* PRE_INC / PRE_DEC will have the reload register ending up
4330 with the same value as the stack slot, but that doesn't
4331 hold true for POST_INC / POST_DEC. Either we have to
4332 convert the memory access to a true POST_INC / POST_DEC,
4333 or we can't use the reload register for inheritance. */
4334 if ((code == POST_INC || code == POST_DEC)
4335 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4336 REGNO (rld[i].reg_rtx))
4337 /* Make sure it is the inc/dec pseudo, and not
4338 some other (e.g. output operand) pseudo. */
4339 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4340 == REGNO (XEXP (in_reg, 0))))
4343 rtx reload_reg = rld[i].reg_rtx;
4344 enum machine_mode mode = GET_MODE (reload_reg);
4348 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4350 /* We really want to ignore REG_INC notes here, so
4351 use PATTERN (p) as argument to reg_set_p . */
4352 if (reg_set_p (reload_reg, PATTERN (p)))
4354 n = count_occurrences (PATTERN (p), reload_reg, 0);
4360 = gen_rtx_fmt_e (code, mode, reload_reg);
4362 validate_replace_rtx_group (reload_reg,
4364 n = verify_changes (0);
4366 /* We must also verify that the constraints
4367 are met after the replacement. Make sure
4368 extract_insn is only called for an insn
4369 where the replacements were found to be
4374 n = constrain_operands (1);
4377 /* If the constraints were not met, then
4378 undo the replacement, else confirm it. */
4382 confirm_change_group ();
4388 add_reg_note (p, REG_INC, reload_reg);
4389 /* Mark this as having an output reload so that the
4390 REG_INC processing code below won't invalidate
4391 the reload for inheritance. */
4392 SET_HARD_REG_BIT (reg_is_output_reload,
4393 REGNO (reload_reg));
4394 SET_REGNO_REG_SET (®_has_output_reload,
4395 REGNO (XEXP (in_reg, 0)));
4398 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4401 else if ((code == PRE_INC || code == PRE_DEC)
4402 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4403 REGNO (rld[i].reg_rtx))
4404 /* Make sure it is the inc/dec pseudo, and not
4405 some other (e.g. output operand) pseudo. */
4406 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4407 == REGNO (XEXP (in_reg, 0))))
4409 SET_HARD_REG_BIT (reg_is_output_reload,
4410 REGNO (rld[i].reg_rtx));
4411 SET_REGNO_REG_SET (®_has_output_reload,
4412 REGNO (XEXP (in_reg, 0)));
4414 else if (code == PRE_INC || code == PRE_DEC
4415 || code == POST_INC || code == POST_DEC)
4417 int in_regno = REGNO (XEXP (in_reg, 0));
4419 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4422 bool forget_p = true;
4424 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4425 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4428 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4431 if (x == reg_reloaded_insn[in_hard_regno])
4437 /* If for some reasons, we didn't set up
4438 reg_last_reload_reg in this insn,
4439 invalidate inheritance from previous
4440 insns for the incremented/decremented
4441 register. Such registers will be not in
4442 reg_has_output_reload. Invalidate it
4443 also if the corresponding element in
4444 reg_reloaded_insn is also
4447 forget_old_reloads_1 (XEXP (in_reg, 0),
4453 /* If a pseudo that got a hard register is auto-incremented,
4454 we must purge records of copying it into pseudos without
4456 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4457 if (REG_NOTE_KIND (x) == REG_INC)
4459 /* See if this pseudo reg was reloaded in this insn.
4460 If so, its last-reload info is still valid
4461 because it is based on this insn's reload. */
4462 for (i = 0; i < n_reloads; i++)
4463 if (rld[i].out == XEXP (x, 0))
4467 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4471 /* A reload reg's contents are unknown after a label. */
4473 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4475 /* Don't assume a reload reg is still good after a call insn
4476 if it is a call-used reg, or if it contains a value that will
4477 be partially clobbered by the call. */
4478 else if (CALL_P (insn))
4480 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4481 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4486 free (reg_last_reload_reg);
4487 CLEAR_REG_SET (®_has_output_reload);
4490 /* Discard all record of any value reloaded from X,
4491 or reloaded in X from someplace else;
4492 unless X is an output reload reg of the current insn.
4494 X may be a hard reg (the reload reg)
4495 or it may be a pseudo reg that was reloaded from.
4497 When DATA is non-NULL just mark the registers in regset
4498 to be forgotten later. */
4501 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4506 regset regs = (regset) data;
4508 /* note_stores does give us subregs of hard regs,
4509 subreg_regno_offset requires a hard reg. */
4510 while (GET_CODE (x) == SUBREG)
4512 /* We ignore the subreg offset when calculating the regno,
4513 because we are using the entire underlying hard register
4523 if (regno >= FIRST_PSEUDO_REGISTER)
4529 nr = hard_regno_nregs[regno][GET_MODE (x)];
4530 /* Storing into a spilled-reg invalidates its contents.
4531 This can happen if a block-local pseudo is allocated to that reg
4532 and it wasn't spilled because this block's total need is 0.
4533 Then some insn might have an optional reload and use this reg. */
4535 for (i = 0; i < nr; i++)
4536 /* But don't do this if the reg actually serves as an output
4537 reload reg in the current instruction. */
4539 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4541 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4542 spill_reg_store[regno + i] = 0;
4548 SET_REGNO_REG_SET (regs, regno + nr);
4551 /* Since value of X has changed,
4552 forget any value previously copied from it. */
4555 /* But don't forget a copy if this is the output reload
4556 that establishes the copy's validity. */
4558 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4559 reg_last_reload_reg[regno + nr] = 0;
4563 /* Forget the reloads marked in regset by previous function. */
4565 forget_marked_reloads (regset regs)
4568 reg_set_iterator rsi;
4569 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4571 if (reg < FIRST_PSEUDO_REGISTER
4572 /* But don't do this if the reg actually serves as an output
4573 reload reg in the current instruction. */
4575 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4577 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4578 spill_reg_store[reg] = 0;
4581 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4582 reg_last_reload_reg[reg] = 0;
4586 /* The following HARD_REG_SETs indicate when each hard register is
4587 used for a reload of various parts of the current insn. */
4589 /* If reg is unavailable for all reloads. */
4590 static HARD_REG_SET reload_reg_unavailable;
4591 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4592 static HARD_REG_SET reload_reg_used;
4593 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4594 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4595 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4596 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4597 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4598 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4599 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4600 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4601 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4602 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4603 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4604 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4605 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4606 static HARD_REG_SET reload_reg_used_in_op_addr;
4607 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4608 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4609 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4610 static HARD_REG_SET reload_reg_used_in_insn;
4611 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4612 static HARD_REG_SET reload_reg_used_in_other_addr;
4614 /* If reg is in use as a reload reg for any sort of reload. */
4615 static HARD_REG_SET reload_reg_used_at_all;
4617 /* If reg is use as an inherited reload. We just mark the first register
4619 static HARD_REG_SET reload_reg_used_for_inherit;
4621 /* Records which hard regs are used in any way, either as explicit use or
4622 by being allocated to a pseudo during any point of the current insn. */
4623 static HARD_REG_SET reg_used_in_insn;
4625 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4626 TYPE. MODE is used to indicate how many consecutive regs are
4630 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4631 enum machine_mode mode)
4633 unsigned int nregs = hard_regno_nregs[regno][mode];
4636 for (i = regno; i < nregs + regno; i++)
4641 SET_HARD_REG_BIT (reload_reg_used, i);
4644 case RELOAD_FOR_INPUT_ADDRESS:
4645 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4648 case RELOAD_FOR_INPADDR_ADDRESS:
4649 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4652 case RELOAD_FOR_OUTPUT_ADDRESS:
4653 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4656 case RELOAD_FOR_OUTADDR_ADDRESS:
4657 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4660 case RELOAD_FOR_OPERAND_ADDRESS:
4661 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4664 case RELOAD_FOR_OPADDR_ADDR:
4665 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4668 case RELOAD_FOR_OTHER_ADDRESS:
4669 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4672 case RELOAD_FOR_INPUT:
4673 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4676 case RELOAD_FOR_OUTPUT:
4677 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4680 case RELOAD_FOR_INSN:
4681 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4685 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4689 /* Similarly, but show REGNO is no longer in use for a reload. */
4692 clear_reload_reg_in_use (unsigned int regno, int opnum,
4693 enum reload_type type, enum machine_mode mode)
4695 unsigned int nregs = hard_regno_nregs[regno][mode];
4696 unsigned int start_regno, end_regno, r;
4698 /* A complication is that for some reload types, inheritance might
4699 allow multiple reloads of the same types to share a reload register.
4700 We set check_opnum if we have to check only reloads with the same
4701 operand number, and check_any if we have to check all reloads. */
4702 int check_opnum = 0;
4704 HARD_REG_SET *used_in_set;
4709 used_in_set = &reload_reg_used;
4712 case RELOAD_FOR_INPUT_ADDRESS:
4713 used_in_set = &reload_reg_used_in_input_addr[opnum];
4716 case RELOAD_FOR_INPADDR_ADDRESS:
4718 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4721 case RELOAD_FOR_OUTPUT_ADDRESS:
4722 used_in_set = &reload_reg_used_in_output_addr[opnum];
4725 case RELOAD_FOR_OUTADDR_ADDRESS:
4727 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4730 case RELOAD_FOR_OPERAND_ADDRESS:
4731 used_in_set = &reload_reg_used_in_op_addr;
4734 case RELOAD_FOR_OPADDR_ADDR:
4736 used_in_set = &reload_reg_used_in_op_addr_reload;
4739 case RELOAD_FOR_OTHER_ADDRESS:
4740 used_in_set = &reload_reg_used_in_other_addr;
4744 case RELOAD_FOR_INPUT:
4745 used_in_set = &reload_reg_used_in_input[opnum];
4748 case RELOAD_FOR_OUTPUT:
4749 used_in_set = &reload_reg_used_in_output[opnum];
4752 case RELOAD_FOR_INSN:
4753 used_in_set = &reload_reg_used_in_insn;
4758 /* We resolve conflicts with remaining reloads of the same type by
4759 excluding the intervals of reload registers by them from the
4760 interval of freed reload registers. Since we only keep track of
4761 one set of interval bounds, we might have to exclude somewhat
4762 more than what would be necessary if we used a HARD_REG_SET here.
4763 But this should only happen very infrequently, so there should
4764 be no reason to worry about it. */
4766 start_regno = regno;
4767 end_regno = regno + nregs;
4768 if (check_opnum || check_any)
4770 for (i = n_reloads - 1; i >= 0; i--)
4772 if (rld[i].when_needed == type
4773 && (check_any || rld[i].opnum == opnum)
4776 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4777 unsigned int conflict_end
4778 = end_hard_regno (rld[i].mode, conflict_start);
4780 /* If there is an overlap with the first to-be-freed register,
4781 adjust the interval start. */
4782 if (conflict_start <= start_regno && conflict_end > start_regno)
4783 start_regno = conflict_end;
4784 /* Otherwise, if there is a conflict with one of the other
4785 to-be-freed registers, adjust the interval end. */
4786 if (conflict_start > start_regno && conflict_start < end_regno)
4787 end_regno = conflict_start;
4792 for (r = start_regno; r < end_regno; r++)
4793 CLEAR_HARD_REG_BIT (*used_in_set, r);
4796 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4797 specified by OPNUM and TYPE. */
4800 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4804 /* In use for a RELOAD_OTHER means it's not available for anything. */
4805 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4806 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4812 /* In use for anything means we can't use it for RELOAD_OTHER. */
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4815 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4816 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4819 for (i = 0; i < reload_n_operands; i++)
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4825 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4830 case RELOAD_FOR_INPUT:
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4835 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4838 /* If it is used for some other input, can't use it. */
4839 for (i = 0; i < reload_n_operands; i++)
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4843 /* If it is used in a later operand's address, can't use it. */
4844 for (i = opnum + 1; i < reload_n_operands; i++)
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4846 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4851 case RELOAD_FOR_INPUT_ADDRESS:
4852 /* Can't use a register if it is used for an input address for this
4853 operand or used as an input in an earlier one. */
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4855 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4858 for (i = 0; i < opnum; i++)
4859 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4864 case RELOAD_FOR_INPADDR_ADDRESS:
4865 /* Can't use a register if it is used for an input address
4866 for this operand or used as an input in an earlier
4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4871 for (i = 0; i < opnum; i++)
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4877 case RELOAD_FOR_OUTPUT_ADDRESS:
4878 /* Can't use a register if it is used for an output address for this
4879 operand or used as an output in this or a later operand. Note
4880 that multiple output operands are emitted in reverse order, so
4881 the conflicting ones are those with lower indices. */
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4885 for (i = 0; i <= opnum; i++)
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4891 case RELOAD_FOR_OUTADDR_ADDRESS:
4892 /* Can't use a register if it is used for an output address
4893 for this operand or used as an output in this or a
4894 later operand. Note that multiple output operands are
4895 emitted in reverse order, so the conflicting ones are
4896 those with lower indices. */
4897 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4900 for (i = 0; i <= opnum; i++)
4901 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4906 case RELOAD_FOR_OPERAND_ADDRESS:
4907 for (i = 0; i < reload_n_operands; i++)
4908 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4911 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4912 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4914 case RELOAD_FOR_OPADDR_ADDR:
4915 for (i = 0; i < reload_n_operands; i++)
4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4919 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4921 case RELOAD_FOR_OUTPUT:
4922 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4923 outputs, or an operand address for this or an earlier output.
4924 Note that multiple output operands are emitted in reverse order,
4925 so the conflicting ones are those with higher indices. */
4926 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4929 for (i = 0; i < reload_n_operands; i++)
4930 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4933 for (i = opnum; i < reload_n_operands; i++)
4934 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4935 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4940 case RELOAD_FOR_INSN:
4941 for (i = 0; i < reload_n_operands; i++)
4942 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4943 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4946 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4947 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4949 case RELOAD_FOR_OTHER_ADDRESS:
4950 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4957 /* Return 1 if the value in reload reg REGNO, as used by a reload
4958 needed for the part of the insn specified by OPNUM and TYPE,
4959 is still available in REGNO at the end of the insn.
4961 We can assume that the reload reg was already tested for availability
4962 at the time it is needed, and we should not check this again,
4963 in case the reg has already been marked in use. */
4966 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4973 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4974 its value must reach the end. */
4977 /* If this use is for part of the insn,
4978 its value reaches if no subsequent part uses the same register.
4979 Just like the above function, don't try to do this with lots
4982 case RELOAD_FOR_OTHER_ADDRESS:
4983 /* Here we check for everything else, since these don't conflict
4984 with anything else and everything comes later. */
4986 for (i = 0; i < reload_n_operands; i++)
4987 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4988 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4989 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4990 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4992 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4995 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4996 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4997 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4998 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5000 case RELOAD_FOR_INPUT_ADDRESS:
5001 case RELOAD_FOR_INPADDR_ADDRESS:
5002 /* Similar, except that we check only for this and subsequent inputs
5003 and the address of only subsequent inputs and we do not need
5004 to check for RELOAD_OTHER objects since they are known not to
5007 for (i = opnum; i < reload_n_operands; i++)
5008 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5011 for (i = opnum + 1; i < reload_n_operands; i++)
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5016 for (i = 0; i < reload_n_operands; i++)
5017 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5018 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5019 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5022 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5025 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5026 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5027 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5029 case RELOAD_FOR_INPUT:
5030 /* Similar to input address, except we start at the next operand for
5031 both input and input address and we do not check for
5032 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5035 for (i = opnum + 1; i < reload_n_operands; i++)
5036 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5041 /* ... fall through ... */
5043 case RELOAD_FOR_OPERAND_ADDRESS:
5044 /* Check outputs and their addresses. */
5046 for (i = 0; i < reload_n_operands; i++)
5047 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5048 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5049 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5052 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5054 case RELOAD_FOR_OPADDR_ADDR:
5055 for (i = 0; i < reload_n_operands; i++)
5056 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5057 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5058 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5061 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5062 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5063 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5065 case RELOAD_FOR_INSN:
5066 /* These conflict with other outputs with RELOAD_OTHER. So
5067 we need only check for output addresses. */
5069 opnum = reload_n_operands;
5071 /* ... fall through ... */
5073 case RELOAD_FOR_OUTPUT:
5074 case RELOAD_FOR_OUTPUT_ADDRESS:
5075 case RELOAD_FOR_OUTADDR_ADDRESS:
5076 /* We already know these can't conflict with a later output. So the
5077 only thing to check are later output addresses.
5078 Note that multiple output operands are emitted in reverse order,
5079 so the conflicting ones are those with lower indices. */
5080 for (i = 0; i < opnum; i++)
5081 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5082 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5092 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5093 every register in the range [REGNO, REGNO + NREGS). */
5096 reload_regs_reach_end_p (unsigned int regno, int nregs,
5097 int opnum, enum reload_type type)
5101 for (i = 0; i < nregs; i++)
5102 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5108 /* Returns whether R1 and R2 are uniquely chained: the value of one
5109 is used by the other, and that value is not used by any other
5110 reload for this insn. This is used to partially undo the decision
5111 made in find_reloads when in the case of multiple
5112 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5113 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5114 reloads. This code tries to avoid the conflict created by that
5115 change. It might be cleaner to explicitly keep track of which
5116 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5117 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5118 this after the fact. */
5120 reloads_unique_chain_p (int r1, int r2)
5124 /* We only check input reloads. */
5125 if (! rld[r1].in || ! rld[r2].in)
5128 /* Avoid anything with output reloads. */
5129 if (rld[r1].out || rld[r2].out)
5132 /* "chained" means one reload is a component of the other reload,
5133 not the same as the other reload. */
5134 if (rld[r1].opnum != rld[r2].opnum
5135 || rtx_equal_p (rld[r1].in, rld[r2].in)
5136 || rld[r1].optional || rld[r2].optional
5137 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5138 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5141 for (i = 0; i < n_reloads; i ++)
5142 /* Look for input reloads that aren't our two */
5143 if (i != r1 && i != r2 && rld[i].in)
5145 /* If our reload is mentioned at all, it isn't a simple chain. */
5146 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5153 /* The recursive function change all occurrences of WHAT in *WHERE
5156 substitute (rtx *where, const_rtx what, rtx repl)
5165 if (*where == what || rtx_equal_p (*where, what))
5171 code = GET_CODE (*where);
5172 fmt = GET_RTX_FORMAT (code);
5173 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5179 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5180 substitute (&XVECEXP (*where, i, j), what, repl);
5182 else if (fmt[i] == 'e')
5183 substitute (&XEXP (*where, i), what, repl);
5187 /* The function returns TRUE if chain of reload R1 and R2 (in any
5188 order) can be evaluated without usage of intermediate register for
5189 the reload containing another reload. It is important to see
5190 gen_reload to understand what the function is trying to do. As an
5191 example, let us have reload chain
5194 r1: <something> + const
5196 and reload R2 got reload reg HR. The function returns true if
5197 there is a correct insn HR = HR + <something>. Otherwise,
5198 gen_reload will use intermediate register (and this is the reload
5199 reg for R1) to reload <something>.
5201 We need this function to find a conflict for chain reloads. In our
5202 example, if HR = HR + <something> is incorrect insn, then we cannot
5203 use HR as a reload register for R2. If we do use it then we get a
5212 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5216 rtx out, in, tem, insn;
5217 rtx last = get_last_insn ();
5219 /* Make r2 a component of r1. */
5220 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5226 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5227 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5228 gcc_assert (regno >= 0);
5229 out = gen_rtx_REG (rld[r1].mode, regno);
5230 in = copy_rtx (rld[r1].in);
5231 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5233 /* If IN is a paradoxical SUBREG, remove it and try to put the
5234 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5235 if (GET_CODE (in) == SUBREG
5236 && (GET_MODE_SIZE (GET_MODE (in))
5237 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5238 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5239 in = SUBREG_REG (in), out = tem;
5241 if (GET_CODE (in) == PLUS
5242 && (REG_P (XEXP (in, 0))
5243 || GET_CODE (XEXP (in, 0)) == SUBREG
5244 || MEM_P (XEXP (in, 0)))
5245 && (REG_P (XEXP (in, 1))
5246 || GET_CODE (XEXP (in, 1)) == SUBREG
5247 || CONSTANT_P (XEXP (in, 1))
5248 || MEM_P (XEXP (in, 1))))
5250 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5251 code = recog_memoized (insn);
5256 extract_insn (insn);
5257 /* We want constrain operands to treat this insn strictly in
5258 its validity determination, i.e., the way it would after
5259 reload has completed. */
5260 result = constrain_operands (1);
5263 delete_insns_since (last);
5267 /* It looks like other cases in gen_reload are not possible for
5268 chain reloads or do need an intermediate hard registers. */
5272 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5275 This function uses the same algorithm as reload_reg_free_p above. */
5278 reloads_conflict (int r1, int r2)
5280 enum reload_type r1_type = rld[r1].when_needed;
5281 enum reload_type r2_type = rld[r2].when_needed;
5282 int r1_opnum = rld[r1].opnum;
5283 int r2_opnum = rld[r2].opnum;
5285 /* RELOAD_OTHER conflicts with everything. */
5286 if (r2_type == RELOAD_OTHER)
5289 /* Otherwise, check conflicts differently for each type. */
5293 case RELOAD_FOR_INPUT:
5294 return (r2_type == RELOAD_FOR_INSN
5295 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5296 || r2_type == RELOAD_FOR_OPADDR_ADDR
5297 || r2_type == RELOAD_FOR_INPUT
5298 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5299 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5300 && r2_opnum > r1_opnum));
5302 case RELOAD_FOR_INPUT_ADDRESS:
5303 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5304 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5306 case RELOAD_FOR_INPADDR_ADDRESS:
5307 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5308 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5310 case RELOAD_FOR_OUTPUT_ADDRESS:
5311 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5312 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5314 case RELOAD_FOR_OUTADDR_ADDRESS:
5315 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5316 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5318 case RELOAD_FOR_OPERAND_ADDRESS:
5319 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5320 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5321 && (!reloads_unique_chain_p (r1, r2)
5322 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5324 case RELOAD_FOR_OPADDR_ADDR:
5325 return (r2_type == RELOAD_FOR_INPUT
5326 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5328 case RELOAD_FOR_OUTPUT:
5329 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5330 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5331 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5332 && r2_opnum >= r1_opnum));
5334 case RELOAD_FOR_INSN:
5335 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5336 || r2_type == RELOAD_FOR_INSN
5337 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5339 case RELOAD_FOR_OTHER_ADDRESS:
5340 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5350 /* Indexed by reload number, 1 if incoming value
5351 inherited from previous insns. */
5352 static char reload_inherited[MAX_RELOADS];
5354 /* For an inherited reload, this is the insn the reload was inherited from,
5355 if we know it. Otherwise, this is 0. */
5356 static rtx reload_inheritance_insn[MAX_RELOADS];
5358 /* If nonzero, this is a place to get the value of the reload,
5359 rather than using reload_in. */
5360 static rtx reload_override_in[MAX_RELOADS];
5362 /* For each reload, the hard register number of the register used,
5363 or -1 if we did not need a register for this reload. */
5364 static int reload_spill_index[MAX_RELOADS];
5366 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5367 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5369 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5370 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5372 /* Subroutine of free_for_value_p, used to check a single register.
5373 START_REGNO is the starting regno of the full reload register
5374 (possibly comprising multiple hard registers) that we are considering. */
5377 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5378 enum reload_type type, rtx value, rtx out,
5379 int reloadnum, int ignore_address_reloads)
5382 /* Set if we see an input reload that must not share its reload register
5383 with any new earlyclobber, but might otherwise share the reload
5384 register with an output or input-output reload. */
5385 int check_earlyclobber = 0;
5389 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5392 if (out == const0_rtx)
5398 /* We use some pseudo 'time' value to check if the lifetimes of the
5399 new register use would overlap with the one of a previous reload
5400 that is not read-only or uses a different value.
5401 The 'time' used doesn't have to be linear in any shape or form, just
5403 Some reload types use different 'buckets' for each operand.
5404 So there are MAX_RECOG_OPERANDS different time values for each
5406 We compute TIME1 as the time when the register for the prospective
5407 new reload ceases to be live, and TIME2 for each existing
5408 reload as the time when that the reload register of that reload
5410 Where there is little to be gained by exact lifetime calculations,
5411 we just make conservative assumptions, i.e. a longer lifetime;
5412 this is done in the 'default:' cases. */
5415 case RELOAD_FOR_OTHER_ADDRESS:
5416 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5417 time1 = copy ? 0 : 1;
5420 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5422 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5423 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5424 respectively, to the time values for these, we get distinct time
5425 values. To get distinct time values for each operand, we have to
5426 multiply opnum by at least three. We round that up to four because
5427 multiply by four is often cheaper. */
5428 case RELOAD_FOR_INPADDR_ADDRESS:
5429 time1 = opnum * 4 + 2;
5431 case RELOAD_FOR_INPUT_ADDRESS:
5432 time1 = opnum * 4 + 3;
5434 case RELOAD_FOR_INPUT:
5435 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5436 executes (inclusive). */
5437 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5439 case RELOAD_FOR_OPADDR_ADDR:
5441 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5442 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5444 case RELOAD_FOR_OPERAND_ADDRESS:
5445 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5447 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5449 case RELOAD_FOR_OUTADDR_ADDRESS:
5450 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5452 case RELOAD_FOR_OUTPUT_ADDRESS:
5453 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5456 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5459 for (i = 0; i < n_reloads; i++)
5461 rtx reg = rld[i].reg_rtx;
5462 if (reg && REG_P (reg)
5463 && ((unsigned) regno - true_regnum (reg)
5464 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5467 rtx other_input = rld[i].in;
5469 /* If the other reload loads the same input value, that
5470 will not cause a conflict only if it's loading it into
5471 the same register. */
5472 if (true_regnum (reg) != start_regno)
5473 other_input = NULL_RTX;
5474 if (! other_input || ! rtx_equal_p (other_input, value)
5475 || rld[i].out || out)
5478 switch (rld[i].when_needed)
5480 case RELOAD_FOR_OTHER_ADDRESS:
5483 case RELOAD_FOR_INPADDR_ADDRESS:
5484 /* find_reloads makes sure that a
5485 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5486 by at most one - the first -
5487 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5488 address reload is inherited, the address address reload
5489 goes away, so we can ignore this conflict. */
5490 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5491 && ignore_address_reloads
5492 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5493 Then the address address is still needed to store
5494 back the new address. */
5495 && ! rld[reloadnum].out)
5497 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5498 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5500 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5501 && ignore_address_reloads
5502 /* Unless we are reloading an auto_inc expression. */
5503 && ! rld[reloadnum].out)
5505 time2 = rld[i].opnum * 4 + 2;
5507 case RELOAD_FOR_INPUT_ADDRESS:
5508 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5509 && ignore_address_reloads
5510 && ! rld[reloadnum].out)
5512 time2 = rld[i].opnum * 4 + 3;
5514 case RELOAD_FOR_INPUT:
5515 time2 = rld[i].opnum * 4 + 4;
5516 check_earlyclobber = 1;
5518 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5519 == MAX_RECOG_OPERAND * 4 */
5520 case RELOAD_FOR_OPADDR_ADDR:
5521 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5522 && ignore_address_reloads
5523 && ! rld[reloadnum].out)
5525 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5527 case RELOAD_FOR_OPERAND_ADDRESS:
5528 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5529 check_earlyclobber = 1;
5531 case RELOAD_FOR_INSN:
5532 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5534 case RELOAD_FOR_OUTPUT:
5535 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5536 instruction is executed. */
5537 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5539 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5540 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5542 case RELOAD_FOR_OUTADDR_ADDRESS:
5543 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5544 && ignore_address_reloads
5545 && ! rld[reloadnum].out)
5547 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5549 case RELOAD_FOR_OUTPUT_ADDRESS:
5550 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5553 /* If there is no conflict in the input part, handle this
5554 like an output reload. */
5555 if (! rld[i].in || rtx_equal_p (other_input, value))
5557 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5558 /* Earlyclobbered outputs must conflict with inputs. */
5559 if (earlyclobber_operand_p (rld[i].out))
5560 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5565 /* RELOAD_OTHER might be live beyond instruction execution,
5566 but this is not obvious when we set time2 = 1. So check
5567 here if there might be a problem with the new reload
5568 clobbering the register used by the RELOAD_OTHER. */
5576 && (! rld[i].in || rld[i].out
5577 || ! rtx_equal_p (other_input, value)))
5578 || (out && rld[reloadnum].out_reg
5579 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5585 /* Earlyclobbered outputs must conflict with inputs. */
5586 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5592 /* Return 1 if the value in reload reg REGNO, as used by a reload
5593 needed for the part of the insn specified by OPNUM and TYPE,
5594 may be used to load VALUE into it.
5596 MODE is the mode in which the register is used, this is needed to
5597 determine how many hard regs to test.
5599 Other read-only reloads with the same value do not conflict
5600 unless OUT is nonzero and these other reloads have to live while
5601 output reloads live.
5602 If OUT is CONST0_RTX, this is a special case: it means that the
5603 test should not be for using register REGNO as reload register, but
5604 for copying from register REGNO into the reload register.
5606 RELOADNUM is the number of the reload we want to load this value for;
5607 a reload does not conflict with itself.
5609 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5610 reloads that load an address for the very reload we are considering.
5612 The caller has to make sure that there is no conflict with the return
5616 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5617 enum reload_type type, rtx value, rtx out, int reloadnum,
5618 int ignore_address_reloads)
5620 int nregs = hard_regno_nregs[regno][mode];
5622 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5623 value, out, reloadnum,
5624 ignore_address_reloads))
5629 /* Return nonzero if the rtx X is invariant over the current function. */
5630 /* ??? Actually, the places where we use this expect exactly what is
5631 tested here, and not everything that is function invariant. In
5632 particular, the frame pointer and arg pointer are special cased;
5633 pic_offset_table_rtx is not, and we must not spill these things to
5637 function_invariant_p (const_rtx x)
5641 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5643 if (GET_CODE (x) == PLUS
5644 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5645 && CONSTANT_P (XEXP (x, 1)))
5650 /* Determine whether the reload reg X overlaps any rtx'es used for
5651 overriding inheritance. Return nonzero if so. */
5654 conflicts_with_override (rtx x)
5657 for (i = 0; i < n_reloads; i++)
5658 if (reload_override_in[i]
5659 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5664 /* Give an error message saying we failed to find a reload for INSN,
5665 and clear out reload R. */
5667 failed_reload (rtx insn, int r)
5669 if (asm_noperands (PATTERN (insn)) < 0)
5670 /* It's the compiler's fault. */
5671 fatal_insn ("could not find a spill register", insn);
5673 /* It's the user's fault; the operand's mode and constraint
5674 don't match. Disable this reload so we don't crash in final. */
5675 error_for_asm (insn,
5676 "%<asm%> operand constraint incompatible with operand size");
5680 rld[r].optional = 1;
5681 rld[r].secondary_p = 1;
5684 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5685 for reload R. If it's valid, get an rtx for it. Return nonzero if
5688 set_reload_reg (int i, int r)
5691 rtx reg = spill_reg_rtx[i];
5693 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5694 spill_reg_rtx[i] = reg
5695 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5697 regno = true_regnum (reg);
5699 /* Detect when the reload reg can't hold the reload mode.
5700 This used to be one `if', but Sequent compiler can't handle that. */
5701 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5703 enum machine_mode test_mode = VOIDmode;
5705 test_mode = GET_MODE (rld[r].in);
5706 /* If rld[r].in has VOIDmode, it means we will load it
5707 in whatever mode the reload reg has: to wit, rld[r].mode.
5708 We have already tested that for validity. */
5709 /* Aside from that, we need to test that the expressions
5710 to reload from or into have modes which are valid for this
5711 reload register. Otherwise the reload insns would be invalid. */
5712 if (! (rld[r].in != 0 && test_mode != VOIDmode
5713 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5714 if (! (rld[r].out != 0
5715 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5717 /* The reg is OK. */
5720 /* Mark as in use for this insn the reload regs we use
5722 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5723 rld[r].when_needed, rld[r].mode);
5725 rld[r].reg_rtx = reg;
5726 reload_spill_index[r] = spill_regs[i];
5733 /* Find a spill register to use as a reload register for reload R.
5734 LAST_RELOAD is nonzero if this is the last reload for the insn being
5737 Set rld[R].reg_rtx to the register allocated.
5739 We return 1 if successful, or 0 if we couldn't find a spill reg and
5740 we didn't change anything. */
5743 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5748 /* If we put this reload ahead, thinking it is a group,
5749 then insist on finding a group. Otherwise we can grab a
5750 reg that some other reload needs.
5751 (That can happen when we have a 68000 DATA_OR_FP_REG
5752 which is a group of data regs or one fp reg.)
5753 We need not be so restrictive if there are no more reloads
5756 ??? Really it would be nicer to have smarter handling
5757 for that kind of reg class, where a problem like this is normal.
5758 Perhaps those classes should be avoided for reloading
5759 by use of more alternatives. */
5761 int force_group = rld[r].nregs > 1 && ! last_reload;
5763 /* If we want a single register and haven't yet found one,
5764 take any reg in the right class and not in use.
5765 If we want a consecutive group, here is where we look for it.
5767 We use two passes so we can first look for reload regs to
5768 reuse, which are already in use for other reloads in this insn,
5769 and only then use additional registers.
5770 I think that maximizing reuse is needed to make sure we don't
5771 run out of reload regs. Suppose we have three reloads, and
5772 reloads A and B can share regs. These need two regs.
5773 Suppose A and B are given different regs.
5774 That leaves none for C. */
5775 for (pass = 0; pass < 2; pass++)
5777 /* I is the index in spill_regs.
5778 We advance it round-robin between insns to use all spill regs
5779 equally, so that inherited reloads have a chance
5780 of leapfrogging each other. */
5784 for (count = 0; count < n_spills; count++)
5786 int rclass = (int) rld[r].rclass;
5792 regnum = spill_regs[i];
5794 if ((reload_reg_free_p (regnum, rld[r].opnum,
5797 /* We check reload_reg_used to make sure we
5798 don't clobber the return register. */
5799 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5800 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5801 rld[r].when_needed, rld[r].in,
5803 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5804 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5805 /* Look first for regs to share, then for unshared. But
5806 don't share regs used for inherited reloads; they are
5807 the ones we want to preserve. */
5809 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5811 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5814 int nr = hard_regno_nregs[regnum][rld[r].mode];
5815 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5816 (on 68000) got us two FP regs. If NR is 1,
5817 we would reject both of them. */
5820 /* If we need only one reg, we have already won. */
5823 /* But reject a single reg if we demand a group. */
5828 /* Otherwise check that as many consecutive regs as we need
5829 are available here. */
5832 int regno = regnum + nr - 1;
5833 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5834 && spill_reg_order[regno] >= 0
5835 && reload_reg_free_p (regno, rld[r].opnum,
5836 rld[r].when_needed)))
5845 /* If we found something on pass 1, omit pass 2. */
5846 if (count < n_spills)
5850 /* We should have found a spill register by now. */
5851 if (count >= n_spills)
5854 /* I is the index in SPILL_REG_RTX of the reload register we are to
5855 allocate. Get an rtx for it and find its register number. */
5857 return set_reload_reg (i, r);
5860 /* Initialize all the tables needed to allocate reload registers.
5861 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5862 is the array we use to restore the reg_rtx field for every reload. */
5865 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5869 for (i = 0; i < n_reloads; i++)
5870 rld[i].reg_rtx = save_reload_reg_rtx[i];
5872 memset (reload_inherited, 0, MAX_RELOADS);
5873 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5874 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5876 CLEAR_HARD_REG_SET (reload_reg_used);
5877 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5878 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5879 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5880 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5881 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5883 CLEAR_HARD_REG_SET (reg_used_in_insn);
5886 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5887 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5888 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5889 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5890 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5891 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5894 for (i = 0; i < reload_n_operands; i++)
5896 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5897 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5898 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5899 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5900 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5901 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5904 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5906 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5908 for (i = 0; i < n_reloads; i++)
5909 /* If we have already decided to use a certain register,
5910 don't use it in another way. */
5912 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5913 rld[i].when_needed, rld[i].mode);
5916 /* Assign hard reg targets for the pseudo-registers we must reload
5917 into hard regs for this insn.
5918 Also output the instructions to copy them in and out of the hard regs.
5920 For machines with register classes, we are responsible for
5921 finding a reload reg in the proper class. */
5924 choose_reload_regs (struct insn_chain *chain)
5926 rtx insn = chain->insn;
5928 unsigned int max_group_size = 1;
5929 enum reg_class group_class = NO_REGS;
5930 int pass, win, inheritance;
5932 rtx save_reload_reg_rtx[MAX_RELOADS];
5934 /* In order to be certain of getting the registers we need,
5935 we must sort the reloads into order of increasing register class.
5936 Then our grabbing of reload registers will parallel the process
5937 that provided the reload registers.
5939 Also note whether any of the reloads wants a consecutive group of regs.
5940 If so, record the maximum size of the group desired and what
5941 register class contains all the groups needed by this insn. */
5943 for (j = 0; j < n_reloads; j++)
5945 reload_order[j] = j;
5946 if (rld[j].reg_rtx != NULL_RTX)
5948 gcc_assert (REG_P (rld[j].reg_rtx)
5949 && HARD_REGISTER_P (rld[j].reg_rtx));
5950 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5953 reload_spill_index[j] = -1;
5955 if (rld[j].nregs > 1)
5957 max_group_size = MAX (rld[j].nregs, max_group_size);
5959 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5962 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5966 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5968 /* If -O, try first with inheritance, then turning it off.
5969 If not -O, don't do inheritance.
5970 Using inheritance when not optimizing leads to paradoxes
5971 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5972 because one side of the comparison might be inherited. */
5974 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5976 choose_reload_regs_init (chain, save_reload_reg_rtx);
5978 /* Process the reloads in order of preference just found.
5979 Beyond this point, subregs can be found in reload_reg_rtx.
5981 This used to look for an existing reloaded home for all of the
5982 reloads, and only then perform any new reloads. But that could lose
5983 if the reloads were done out of reg-class order because a later
5984 reload with a looser constraint might have an old home in a register
5985 needed by an earlier reload with a tighter constraint.
5987 To solve this, we make two passes over the reloads, in the order
5988 described above. In the first pass we try to inherit a reload
5989 from a previous insn. If there is a later reload that needs a
5990 class that is a proper subset of the class being processed, we must
5991 also allocate a spill register during the first pass.
5993 Then make a second pass over the reloads to allocate any reloads
5994 that haven't been given registers yet. */
5996 for (j = 0; j < n_reloads; j++)
5998 int r = reload_order[j];
5999 rtx search_equiv = NULL_RTX;
6001 /* Ignore reloads that got marked inoperative. */
6002 if (rld[r].out == 0 && rld[r].in == 0
6003 && ! rld[r].secondary_p)
6006 /* If find_reloads chose to use reload_in or reload_out as a reload
6007 register, we don't need to chose one. Otherwise, try even if it
6008 found one since we might save an insn if we find the value lying
6010 Try also when reload_in is a pseudo without a hard reg. */
6011 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6012 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6013 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6014 && !MEM_P (rld[r].in)
6015 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6018 #if 0 /* No longer needed for correct operation.
6019 It might give better code, or might not; worth an experiment? */
6020 /* If this is an optional reload, we can't inherit from earlier insns
6021 until we are sure that any non-optional reloads have been allocated.
6022 The following code takes advantage of the fact that optional reloads
6023 are at the end of reload_order. */
6024 if (rld[r].optional != 0)
6025 for (i = 0; i < j; i++)
6026 if ((rld[reload_order[i]].out != 0
6027 || rld[reload_order[i]].in != 0
6028 || rld[reload_order[i]].secondary_p)
6029 && ! rld[reload_order[i]].optional
6030 && rld[reload_order[i]].reg_rtx == 0)
6031 allocate_reload_reg (chain, reload_order[i], 0);
6034 /* First see if this pseudo is already available as reloaded
6035 for a previous insn. We cannot try to inherit for reloads
6036 that are smaller than the maximum number of registers needed
6037 for groups unless the register we would allocate cannot be used
6040 We could check here to see if this is a secondary reload for
6041 an object that is already in a register of the desired class.
6042 This would avoid the need for the secondary reload register.
6043 But this is complex because we can't easily determine what
6044 objects might want to be loaded via this reload. So let a
6045 register be allocated here. In `emit_reload_insns' we suppress
6046 one of the loads in the case described above. */
6052 enum machine_mode mode = VOIDmode;
6056 else if (REG_P (rld[r].in))
6058 regno = REGNO (rld[r].in);
6059 mode = GET_MODE (rld[r].in);
6061 else if (REG_P (rld[r].in_reg))
6063 regno = REGNO (rld[r].in_reg);
6064 mode = GET_MODE (rld[r].in_reg);
6066 else if (GET_CODE (rld[r].in_reg) == SUBREG
6067 && REG_P (SUBREG_REG (rld[r].in_reg)))
6069 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6070 if (regno < FIRST_PSEUDO_REGISTER)
6071 regno = subreg_regno (rld[r].in_reg);
6073 byte = SUBREG_BYTE (rld[r].in_reg);
6074 mode = GET_MODE (rld[r].in_reg);
6077 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6078 && REG_P (XEXP (rld[r].in_reg, 0)))
6080 regno = REGNO (XEXP (rld[r].in_reg, 0));
6081 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6082 rld[r].out = rld[r].in;
6086 /* This won't work, since REGNO can be a pseudo reg number.
6087 Also, it takes much more hair to keep track of all the things
6088 that can invalidate an inherited reload of part of a pseudoreg. */
6089 else if (GET_CODE (rld[r].in) == SUBREG
6090 && REG_P (SUBREG_REG (rld[r].in)))
6091 regno = subreg_regno (rld[r].in);
6095 && reg_last_reload_reg[regno] != 0
6096 #ifdef CANNOT_CHANGE_MODE_CLASS
6097 /* Verify that the register it's in can be used in
6099 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6100 GET_MODE (reg_last_reload_reg[regno]),
6105 enum reg_class rclass = rld[r].rclass, last_class;
6106 rtx last_reg = reg_last_reload_reg[regno];
6107 enum machine_mode need_mode;
6109 i = REGNO (last_reg);
6110 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6111 last_class = REGNO_REG_CLASS (i);
6117 = smallest_mode_for_size
6118 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6119 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6120 ? MODE_INT : GET_MODE_CLASS (mode));
6122 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6123 >= GET_MODE_SIZE (need_mode))
6124 && reg_reloaded_contents[i] == regno
6125 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6126 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6127 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6128 /* Even if we can't use this register as a reload
6129 register, we might use it for reload_override_in,
6130 if copying it to the desired class is cheap
6132 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6133 < MEMORY_MOVE_COST (mode, rclass, 1))
6134 && (secondary_reload_class (1, rclass, mode,
6137 #ifdef SECONDARY_MEMORY_NEEDED
6138 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6143 && (rld[r].nregs == max_group_size
6144 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6146 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6147 rld[r].when_needed, rld[r].in,
6150 /* If a group is needed, verify that all the subsequent
6151 registers still have their values intact. */
6152 int nr = hard_regno_nregs[i][rld[r].mode];
6155 for (k = 1; k < nr; k++)
6156 if (reg_reloaded_contents[i + k] != regno
6157 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6165 last_reg = (GET_MODE (last_reg) == mode
6166 ? last_reg : gen_rtx_REG (mode, i));
6169 for (k = 0; k < nr; k++)
6170 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6173 /* We found a register that contains the
6174 value we need. If this register is the
6175 same as an `earlyclobber' operand of the
6176 current insn, just mark it as a place to
6177 reload from since we can't use it as the
6178 reload register itself. */
6180 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6181 if (reg_overlap_mentioned_for_reload_p
6182 (reg_last_reload_reg[regno],
6183 reload_earlyclobbers[i1]))
6186 if (i1 != n_earlyclobbers
6187 || ! (free_for_value_p (i, rld[r].mode,
6189 rld[r].when_needed, rld[r].in,
6191 /* Don't use it if we'd clobber a pseudo reg. */
6192 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6194 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6195 /* Don't clobber the frame pointer. */
6196 || (i == HARD_FRAME_POINTER_REGNUM
6197 && frame_pointer_needed
6199 /* Don't really use the inherited spill reg
6200 if we need it wider than we've got it. */
6201 || (GET_MODE_SIZE (rld[r].mode)
6202 > GET_MODE_SIZE (mode))
6205 /* If find_reloads chose reload_out as reload
6206 register, stay with it - that leaves the
6207 inherited register for subsequent reloads. */
6208 || (rld[r].out && rld[r].reg_rtx
6209 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6211 if (! rld[r].optional)
6213 reload_override_in[r] = last_reg;
6214 reload_inheritance_insn[r]
6215 = reg_reloaded_insn[i];
6221 /* We can use this as a reload reg. */
6222 /* Mark the register as in use for this part of
6224 mark_reload_reg_in_use (i,
6228 rld[r].reg_rtx = last_reg;
6229 reload_inherited[r] = 1;
6230 reload_inheritance_insn[r]
6231 = reg_reloaded_insn[i];
6232 reload_spill_index[r] = i;
6233 for (k = 0; k < nr; k++)
6234 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6242 /* Here's another way to see if the value is already lying around. */
6245 && ! reload_inherited[r]
6247 && (CONSTANT_P (rld[r].in)
6248 || GET_CODE (rld[r].in) == PLUS
6249 || REG_P (rld[r].in)
6250 || MEM_P (rld[r].in))
6251 && (rld[r].nregs == max_group_size
6252 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6253 search_equiv = rld[r].in;
6254 /* If this is an output reload from a simple move insn, look
6255 if an equivalence for the input is available. */
6256 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6258 rtx set = single_set (insn);
6261 && rtx_equal_p (rld[r].out, SET_DEST (set))
6262 && CONSTANT_P (SET_SRC (set)))
6263 search_equiv = SET_SRC (set);
6269 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6270 -1, NULL, 0, rld[r].mode);
6276 regno = REGNO (equiv);
6279 /* This must be a SUBREG of a hard register.
6280 Make a new REG since this might be used in an
6281 address and not all machines support SUBREGs
6283 gcc_assert (GET_CODE (equiv) == SUBREG);
6284 regno = subreg_regno (equiv);
6285 equiv = gen_rtx_REG (rld[r].mode, regno);
6286 /* If we choose EQUIV as the reload register, but the
6287 loop below decides to cancel the inheritance, we'll
6288 end up reloading EQUIV in rld[r].mode, not the mode
6289 it had originally. That isn't safe when EQUIV isn't
6290 available as a spill register since its value might
6291 still be live at this point. */
6292 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6293 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6298 /* If we found a spill reg, reject it unless it is free
6299 and of the desired class. */
6303 int bad_for_class = 0;
6304 int max_regno = regno + rld[r].nregs;
6306 for (i = regno; i < max_regno; i++)
6308 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6310 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6315 && ! free_for_value_p (regno, rld[r].mode,
6316 rld[r].opnum, rld[r].when_needed,
6317 rld[r].in, rld[r].out, r, 1))
6322 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6325 /* We found a register that contains the value we need.
6326 If this register is the same as an `earlyclobber' operand
6327 of the current insn, just mark it as a place to reload from
6328 since we can't use it as the reload register itself. */
6331 for (i = 0; i < n_earlyclobbers; i++)
6332 if (reg_overlap_mentioned_for_reload_p (equiv,
6333 reload_earlyclobbers[i]))
6335 if (! rld[r].optional)
6336 reload_override_in[r] = equiv;
6341 /* If the equiv register we have found is explicitly clobbered
6342 in the current insn, it depends on the reload type if we
6343 can use it, use it for reload_override_in, or not at all.
6344 In particular, we then can't use EQUIV for a
6345 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6349 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6350 switch (rld[r].when_needed)
6352 case RELOAD_FOR_OTHER_ADDRESS:
6353 case RELOAD_FOR_INPADDR_ADDRESS:
6354 case RELOAD_FOR_INPUT_ADDRESS:
6355 case RELOAD_FOR_OPADDR_ADDR:
6358 case RELOAD_FOR_INPUT:
6359 case RELOAD_FOR_OPERAND_ADDRESS:
6360 if (! rld[r].optional)
6361 reload_override_in[r] = equiv;
6367 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6368 switch (rld[r].when_needed)
6370 case RELOAD_FOR_OTHER_ADDRESS:
6371 case RELOAD_FOR_INPADDR_ADDRESS:
6372 case RELOAD_FOR_INPUT_ADDRESS:
6373 case RELOAD_FOR_OPADDR_ADDR:
6374 case RELOAD_FOR_OPERAND_ADDRESS:
6375 case RELOAD_FOR_INPUT:
6378 if (! rld[r].optional)
6379 reload_override_in[r] = equiv;
6387 /* If we found an equivalent reg, say no code need be generated
6388 to load it, and use it as our reload reg. */
6390 && (regno != HARD_FRAME_POINTER_REGNUM
6391 || !frame_pointer_needed))
6393 int nr = hard_regno_nregs[regno][rld[r].mode];
6395 rld[r].reg_rtx = equiv;
6396 reload_spill_index[r] = regno;
6397 reload_inherited[r] = 1;
6399 /* If reg_reloaded_valid is not set for this register,
6400 there might be a stale spill_reg_store lying around.
6401 We must clear it, since otherwise emit_reload_insns
6402 might delete the store. */
6403 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6404 spill_reg_store[regno] = NULL_RTX;
6405 /* If any of the hard registers in EQUIV are spill
6406 registers, mark them as in use for this insn. */
6407 for (k = 0; k < nr; k++)
6409 i = spill_reg_order[regno + k];
6412 mark_reload_reg_in_use (regno, rld[r].opnum,
6415 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6422 /* If we found a register to use already, or if this is an optional
6423 reload, we are done. */
6424 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6428 /* No longer needed for correct operation. Might or might
6429 not give better code on the average. Want to experiment? */
6431 /* See if there is a later reload that has a class different from our
6432 class that intersects our class or that requires less register
6433 than our reload. If so, we must allocate a register to this
6434 reload now, since that reload might inherit a previous reload
6435 and take the only available register in our class. Don't do this
6436 for optional reloads since they will force all previous reloads
6437 to be allocated. Also don't do this for reloads that have been
6440 for (i = j + 1; i < n_reloads; i++)
6442 int s = reload_order[i];
6444 if ((rld[s].in == 0 && rld[s].out == 0
6445 && ! rld[s].secondary_p)
6449 if ((rld[s].rclass != rld[r].rclass
6450 && reg_classes_intersect_p (rld[r].rclass,
6452 || rld[s].nregs < rld[r].nregs)
6459 allocate_reload_reg (chain, r, j == n_reloads - 1);
6463 /* Now allocate reload registers for anything non-optional that
6464 didn't get one yet. */
6465 for (j = 0; j < n_reloads; j++)
6467 int r = reload_order[j];
6469 /* Ignore reloads that got marked inoperative. */
6470 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6473 /* Skip reloads that already have a register allocated or are
6475 if (rld[r].reg_rtx != 0 || rld[r].optional)
6478 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6482 /* If that loop got all the way, we have won. */
6489 /* Loop around and try without any inheritance. */
6494 /* First undo everything done by the failed attempt
6495 to allocate with inheritance. */
6496 choose_reload_regs_init (chain, save_reload_reg_rtx);
6498 /* Some sanity tests to verify that the reloads found in the first
6499 pass are identical to the ones we have now. */
6500 gcc_assert (chain->n_reloads == n_reloads);
6502 for (i = 0; i < n_reloads; i++)
6504 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6506 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6507 for (j = 0; j < n_spills; j++)
6508 if (spill_regs[j] == chain->rld[i].regno)
6509 if (! set_reload_reg (j, i))
6510 failed_reload (chain->insn, i);
6514 /* If we thought we could inherit a reload, because it seemed that
6515 nothing else wanted the same reload register earlier in the insn,
6516 verify that assumption, now that all reloads have been assigned.
6517 Likewise for reloads where reload_override_in has been set. */
6519 /* If doing expensive optimizations, do one preliminary pass that doesn't
6520 cancel any inheritance, but removes reloads that have been needed only
6521 for reloads that we know can be inherited. */
6522 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6524 for (j = 0; j < n_reloads; j++)
6526 int r = reload_order[j];
6528 if (reload_inherited[r] && rld[r].reg_rtx)
6529 check_reg = rld[r].reg_rtx;
6530 else if (reload_override_in[r]
6531 && (REG_P (reload_override_in[r])
6532 || GET_CODE (reload_override_in[r]) == SUBREG))
6533 check_reg = reload_override_in[r];
6536 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6537 rld[r].opnum, rld[r].when_needed, rld[r].in,
6538 (reload_inherited[r]
6539 ? rld[r].out : const0_rtx),
6544 reload_inherited[r] = 0;
6545 reload_override_in[r] = 0;
6547 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6548 reload_override_in, then we do not need its related
6549 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6550 likewise for other reload types.
6551 We handle this by removing a reload when its only replacement
6552 is mentioned in reload_in of the reload we are going to inherit.
6553 A special case are auto_inc expressions; even if the input is
6554 inherited, we still need the address for the output. We can
6555 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6556 If we succeeded removing some reload and we are doing a preliminary
6557 pass just to remove such reloads, make another pass, since the
6558 removal of one reload might allow us to inherit another one. */
6560 && rld[r].out != rld[r].in
6561 && remove_address_replacements (rld[r].in) && pass)
6566 /* Now that reload_override_in is known valid,
6567 actually override reload_in. */
6568 for (j = 0; j < n_reloads; j++)
6569 if (reload_override_in[j])
6570 rld[j].in = reload_override_in[j];
6572 /* If this reload won't be done because it has been canceled or is
6573 optional and not inherited, clear reload_reg_rtx so other
6574 routines (such as subst_reloads) don't get confused. */
6575 for (j = 0; j < n_reloads; j++)
6576 if (rld[j].reg_rtx != 0
6577 && ((rld[j].optional && ! reload_inherited[j])
6578 || (rld[j].in == 0 && rld[j].out == 0
6579 && ! rld[j].secondary_p)))
6581 int regno = true_regnum (rld[j].reg_rtx);
6583 if (spill_reg_order[regno] >= 0)
6584 clear_reload_reg_in_use (regno, rld[j].opnum,
6585 rld[j].when_needed, rld[j].mode);
6587 reload_spill_index[j] = -1;
6590 /* Record which pseudos and which spill regs have output reloads. */
6591 for (j = 0; j < n_reloads; j++)
6593 int r = reload_order[j];
6595 i = reload_spill_index[r];
6597 /* I is nonneg if this reload uses a register.
6598 If rld[r].reg_rtx is 0, this is an optional reload
6599 that we opted to ignore. */
6600 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6601 && rld[r].reg_rtx != 0)
6603 int nregno = REGNO (rld[r].out_reg);
6606 if (nregno < FIRST_PSEUDO_REGISTER)
6607 nr = hard_regno_nregs[nregno][rld[r].mode];
6610 SET_REGNO_REG_SET (®_has_output_reload,
6615 nr = hard_regno_nregs[i][rld[r].mode];
6617 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6620 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6621 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6622 || rld[r].when_needed == RELOAD_FOR_INSN);
6627 /* Deallocate the reload register for reload R. This is called from
6628 remove_address_replacements. */
6631 deallocate_reload_reg (int r)
6635 if (! rld[r].reg_rtx)
6637 regno = true_regnum (rld[r].reg_rtx);
6639 if (spill_reg_order[regno] >= 0)
6640 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6642 reload_spill_index[r] = -1;
6645 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6646 reloads of the same item for fear that we might not have enough reload
6647 registers. However, normally they will get the same reload register
6648 and hence actually need not be loaded twice.
6650 Here we check for the most common case of this phenomenon: when we have
6651 a number of reloads for the same object, each of which were allocated
6652 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6653 reload, and is not modified in the insn itself. If we find such,
6654 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6655 This will not increase the number of spill registers needed and will
6656 prevent redundant code. */
6659 merge_assigned_reloads (rtx insn)
6663 /* Scan all the reloads looking for ones that only load values and
6664 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6665 assigned and not modified by INSN. */
6667 for (i = 0; i < n_reloads; i++)
6669 int conflicting_input = 0;
6670 int max_input_address_opnum = -1;
6671 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6673 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6674 || rld[i].out != 0 || rld[i].reg_rtx == 0
6675 || reg_set_p (rld[i].reg_rtx, insn))
6678 /* Look at all other reloads. Ensure that the only use of this
6679 reload_reg_rtx is in a reload that just loads the same value
6680 as we do. Note that any secondary reloads must be of the identical
6681 class since the values, modes, and result registers are the
6682 same, so we need not do anything with any secondary reloads. */
6684 for (j = 0; j < n_reloads; j++)
6686 if (i == j || rld[j].reg_rtx == 0
6687 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6691 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6692 && rld[j].opnum > max_input_address_opnum)
6693 max_input_address_opnum = rld[j].opnum;
6695 /* If the reload regs aren't exactly the same (e.g, different modes)
6696 or if the values are different, we can't merge this reload.
6697 But if it is an input reload, we might still merge
6698 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6700 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6701 || rld[j].out != 0 || rld[j].in == 0
6702 || ! rtx_equal_p (rld[i].in, rld[j].in))
6704 if (rld[j].when_needed != RELOAD_FOR_INPUT
6705 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6706 || rld[i].opnum > rld[j].opnum)
6707 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6709 conflicting_input = 1;
6710 if (min_conflicting_input_opnum > rld[j].opnum)
6711 min_conflicting_input_opnum = rld[j].opnum;
6715 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6716 we, in fact, found any matching reloads. */
6719 && max_input_address_opnum <= min_conflicting_input_opnum)
6721 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6723 for (j = 0; j < n_reloads; j++)
6724 if (i != j && rld[j].reg_rtx != 0
6725 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6726 && (! conflicting_input
6727 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6728 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6730 rld[i].when_needed = RELOAD_OTHER;
6732 reload_spill_index[j] = -1;
6733 transfer_replacements (i, j);
6736 /* If this is now RELOAD_OTHER, look for any reloads that
6737 load parts of this operand and set them to
6738 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6739 RELOAD_OTHER for outputs. Note that this test is
6740 equivalent to looking for reloads for this operand
6743 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6744 it may share registers with a RELOAD_FOR_INPUT, so we can
6745 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6746 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6748 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6749 instruction is assigned the same register as the earlier
6750 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6751 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6752 instruction to be deleted later on. */
6754 if (rld[i].when_needed == RELOAD_OTHER)
6755 for (j = 0; j < n_reloads; j++)
6757 && rld[j].when_needed != RELOAD_OTHER
6758 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6759 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6760 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6761 && (! conflicting_input
6762 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6763 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6764 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6770 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6771 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6772 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6774 /* Check to see if we accidentally converted two
6775 reloads that use the same reload register with
6776 different inputs to the same type. If so, the
6777 resulting code won't work. */
6779 for (k = 0; k < j; k++)
6780 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6781 || rld[k].when_needed != rld[j].when_needed
6782 || !rtx_equal_p (rld[k].reg_rtx,
6784 || rtx_equal_p (rld[k].in,
6791 /* These arrays are filled by emit_reload_insns and its subroutines. */
6792 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6793 static rtx other_input_address_reload_insns = 0;
6794 static rtx other_input_reload_insns = 0;
6795 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6796 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6797 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6798 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6799 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6800 static rtx operand_reload_insns = 0;
6801 static rtx other_operand_reload_insns = 0;
6802 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6804 /* Values to be put in spill_reg_store are put here first. */
6805 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6806 static HARD_REG_SET reg_reloaded_died;
6808 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6809 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6810 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6811 adjusted register, and return true. Otherwise, return false. */
6813 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6814 enum reg_class new_class,
6815 enum machine_mode new_mode)
6820 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6822 unsigned regno = REGNO (reg);
6824 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6826 if (GET_MODE (reg) != new_mode)
6828 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6830 if (hard_regno_nregs[regno][new_mode]
6831 > hard_regno_nregs[regno][GET_MODE (reg)])
6833 reg = reload_adjust_reg_for_mode (reg, new_mode);
6841 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6842 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6843 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6844 adjusted register, and return true. Otherwise, return false. */
6846 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6847 enum insn_code icode)
6850 enum reg_class new_class = scratch_reload_class (icode);
6851 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6853 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6854 new_class, new_mode);
6857 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6858 has the number J. OLD contains the value to be used as input. */
6861 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6864 rtx insn = chain->insn;
6866 rtx oldequiv_reg = 0;
6869 enum machine_mode mode;
6872 /* delete_output_reload is only invoked properly if old contains
6873 the original pseudo register. Since this is replaced with a
6874 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6875 find the pseudo in RELOAD_IN_REG. */
6876 if (reload_override_in[j]
6877 && REG_P (rl->in_reg))
6884 else if (REG_P (oldequiv))
6885 oldequiv_reg = oldequiv;
6886 else if (GET_CODE (oldequiv) == SUBREG)
6887 oldequiv_reg = SUBREG_REG (oldequiv);
6889 reloadreg = reload_reg_rtx_for_input[j];
6890 mode = GET_MODE (reloadreg);
6892 /* If we are reloading from a register that was recently stored in
6893 with an output-reload, see if we can prove there was
6894 actually no need to store the old value in it. */
6896 if (optimize && REG_P (oldequiv)
6897 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6898 && spill_reg_store[REGNO (oldequiv)]
6900 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6901 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6903 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6905 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6908 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6909 oldequiv = SUBREG_REG (oldequiv);
6910 if (GET_MODE (oldequiv) != VOIDmode
6911 && mode != GET_MODE (oldequiv))
6912 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6914 /* Switch to the right place to emit the reload insns. */
6915 switch (rl->when_needed)
6918 where = &other_input_reload_insns;
6920 case RELOAD_FOR_INPUT:
6921 where = &input_reload_insns[rl->opnum];
6923 case RELOAD_FOR_INPUT_ADDRESS:
6924 where = &input_address_reload_insns[rl->opnum];
6926 case RELOAD_FOR_INPADDR_ADDRESS:
6927 where = &inpaddr_address_reload_insns[rl->opnum];
6929 case RELOAD_FOR_OUTPUT_ADDRESS:
6930 where = &output_address_reload_insns[rl->opnum];
6932 case RELOAD_FOR_OUTADDR_ADDRESS:
6933 where = &outaddr_address_reload_insns[rl->opnum];
6935 case RELOAD_FOR_OPERAND_ADDRESS:
6936 where = &operand_reload_insns;
6938 case RELOAD_FOR_OPADDR_ADDR:
6939 where = &other_operand_reload_insns;
6941 case RELOAD_FOR_OTHER_ADDRESS:
6942 where = &other_input_address_reload_insns;
6948 push_to_sequence (*where);
6950 /* Auto-increment addresses must be reloaded in a special way. */
6951 if (rl->out && ! rl->out_reg)
6953 /* We are not going to bother supporting the case where a
6954 incremented register can't be copied directly from
6955 OLDEQUIV since this seems highly unlikely. */
6956 gcc_assert (rl->secondary_in_reload < 0);
6958 if (reload_inherited[j])
6959 oldequiv = reloadreg;
6961 old = XEXP (rl->in_reg, 0);
6963 if (optimize && REG_P (oldequiv)
6964 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6965 && spill_reg_store[REGNO (oldequiv)]
6967 && (dead_or_set_p (insn,
6968 spill_reg_stored_to[REGNO (oldequiv)])
6969 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6971 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6973 /* Prevent normal processing of this reload. */
6975 /* Output a special code sequence for this case. */
6976 new_spill_reg_store[REGNO (reloadreg)]
6977 = inc_for_reload (reloadreg, oldequiv, rl->out,
6981 /* If we are reloading a pseudo-register that was set by the previous
6982 insn, see if we can get rid of that pseudo-register entirely
6983 by redirecting the previous insn into our reload register. */
6985 else if (optimize && REG_P (old)
6986 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6987 && dead_or_set_p (insn, old)
6988 /* This is unsafe if some other reload
6989 uses the same reg first. */
6990 && ! conflicts_with_override (reloadreg)
6991 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6992 rl->when_needed, old, rl->out, j, 0))
6994 rtx temp = PREV_INSN (insn);
6995 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
6996 temp = PREV_INSN (temp);
6998 && NONJUMP_INSN_P (temp)
6999 && GET_CODE (PATTERN (temp)) == SET
7000 && SET_DEST (PATTERN (temp)) == old
7001 /* Make sure we can access insn_operand_constraint. */
7002 && asm_noperands (PATTERN (temp)) < 0
7003 /* This is unsafe if operand occurs more than once in current
7004 insn. Perhaps some occurrences aren't reloaded. */
7005 && count_occurrences (PATTERN (insn), old, 0) == 1)
7007 rtx old = SET_DEST (PATTERN (temp));
7008 /* Store into the reload register instead of the pseudo. */
7009 SET_DEST (PATTERN (temp)) = reloadreg;
7011 /* Verify that resulting insn is valid. */
7012 extract_insn (temp);
7013 if (constrain_operands (1))
7015 /* If the previous insn is an output reload, the source is
7016 a reload register, and its spill_reg_store entry will
7017 contain the previous destination. This is now
7019 if (REG_P (SET_SRC (PATTERN (temp)))
7020 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7022 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7023 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7026 /* If these are the only uses of the pseudo reg,
7027 pretend for GDB it lives in the reload reg we used. */
7028 if (REG_N_DEATHS (REGNO (old)) == 1
7029 && REG_N_SETS (REGNO (old)) == 1)
7031 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7032 if (ira_conflicts_p)
7033 /* Inform IRA about the change. */
7034 ira_mark_allocation_change (REGNO (old));
7035 alter_reg (REGNO (old), -1, false);
7039 /* Adjust any debug insns between temp and insn. */
7040 while ((temp = NEXT_INSN (temp)) != insn)
7041 if (DEBUG_INSN_P (temp))
7042 replace_rtx (PATTERN (temp), old, reloadreg);
7044 gcc_assert (NOTE_P (temp));
7048 SET_DEST (PATTERN (temp)) = old;
7053 /* We can't do that, so output an insn to load RELOADREG. */
7055 /* If we have a secondary reload, pick up the secondary register
7056 and icode, if any. If OLDEQUIV and OLD are different or
7057 if this is an in-out reload, recompute whether or not we
7058 still need a secondary register and what the icode should
7059 be. If we still need a secondary register and the class or
7060 icode is different, go back to reloading from OLD if using
7061 OLDEQUIV means that we got the wrong type of register. We
7062 cannot have different class or icode due to an in-out reload
7063 because we don't make such reloads when both the input and
7064 output need secondary reload registers. */
7066 if (! special && rl->secondary_in_reload >= 0)
7068 rtx second_reload_reg = 0;
7069 rtx third_reload_reg = 0;
7070 int secondary_reload = rl->secondary_in_reload;
7071 rtx real_oldequiv = oldequiv;
7074 enum insn_code icode;
7075 enum insn_code tertiary_icode = CODE_FOR_nothing;
7077 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7078 and similarly for OLD.
7079 See comments in get_secondary_reload in reload.c. */
7080 /* If it is a pseudo that cannot be replaced with its
7081 equivalent MEM, we must fall back to reload_in, which
7082 will have all the necessary substitutions registered.
7083 Likewise for a pseudo that can't be replaced with its
7084 equivalent constant.
7086 Take extra care for subregs of such pseudos. Note that
7087 we cannot use reg_equiv_mem in this case because it is
7088 not in the right mode. */
7091 if (GET_CODE (tmp) == SUBREG)
7092 tmp = SUBREG_REG (tmp);
7094 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7095 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7096 || reg_equiv_constant[REGNO (tmp)] != 0))
7098 if (! reg_equiv_mem[REGNO (tmp)]
7099 || num_not_at_initial_offset
7100 || GET_CODE (oldequiv) == SUBREG)
7101 real_oldequiv = rl->in;
7103 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7107 if (GET_CODE (tmp) == SUBREG)
7108 tmp = SUBREG_REG (tmp);
7110 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7111 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7112 || reg_equiv_constant[REGNO (tmp)] != 0))
7114 if (! reg_equiv_mem[REGNO (tmp)]
7115 || num_not_at_initial_offset
7116 || GET_CODE (old) == SUBREG)
7119 real_old = reg_equiv_mem[REGNO (tmp)];
7122 second_reload_reg = rld[secondary_reload].reg_rtx;
7123 if (rld[secondary_reload].secondary_in_reload >= 0)
7125 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7127 third_reload_reg = rld[tertiary_reload].reg_rtx;
7128 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7129 /* We'd have to add more code for quartary reloads. */
7130 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7132 icode = rl->secondary_in_icode;
7134 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7135 || (rl->in != 0 && rl->out != 0))
7137 secondary_reload_info sri, sri2;
7138 enum reg_class new_class, new_t_class;
7140 sri.icode = CODE_FOR_nothing;
7141 sri.prev_sri = NULL;
7142 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7145 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7146 second_reload_reg = 0;
7147 else if (new_class == NO_REGS)
7149 if (reload_adjust_reg_for_icode (&second_reload_reg,
7151 (enum insn_code) sri.icode))
7153 icode = (enum insn_code) sri.icode;
7154 third_reload_reg = 0;
7159 real_oldequiv = real_old;
7162 else if (sri.icode != CODE_FOR_nothing)
7163 /* We currently lack a way to express this in reloads. */
7167 sri2.icode = CODE_FOR_nothing;
7168 sri2.prev_sri = &sri;
7169 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7170 new_class, mode, &sri);
7171 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7173 if (reload_adjust_reg_for_temp (&second_reload_reg,
7177 third_reload_reg = 0;
7178 tertiary_icode = (enum insn_code) sri2.icode;
7183 real_oldequiv = real_old;
7186 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7188 rtx intermediate = second_reload_reg;
7190 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7192 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7196 second_reload_reg = intermediate;
7197 tertiary_icode = (enum insn_code) sri2.icode;
7202 real_oldequiv = real_old;
7205 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7207 rtx intermediate = second_reload_reg;
7209 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7211 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7214 second_reload_reg = intermediate;
7215 tertiary_icode = (enum insn_code) sri2.icode;
7220 real_oldequiv = real_old;
7225 /* This could be handled more intelligently too. */
7227 real_oldequiv = real_old;
7232 /* If we still need a secondary reload register, check
7233 to see if it is being used as a scratch or intermediate
7234 register and generate code appropriately. If we need
7235 a scratch register, use REAL_OLDEQUIV since the form of
7236 the insn may depend on the actual address if it is
7239 if (second_reload_reg)
7241 if (icode != CODE_FOR_nothing)
7243 /* We'd have to add extra code to handle this case. */
7244 gcc_assert (!third_reload_reg);
7246 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7247 second_reload_reg));
7252 /* See if we need a scratch register to load the
7253 intermediate register (a tertiary reload). */
7254 if (tertiary_icode != CODE_FOR_nothing)
7256 emit_insn ((GEN_FCN (tertiary_icode)
7257 (second_reload_reg, real_oldequiv,
7258 third_reload_reg)));
7260 else if (third_reload_reg)
7262 gen_reload (third_reload_reg, real_oldequiv,
7265 gen_reload (second_reload_reg, third_reload_reg,
7270 gen_reload (second_reload_reg, real_oldequiv,
7274 oldequiv = second_reload_reg;
7279 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7281 rtx real_oldequiv = oldequiv;
7283 if ((REG_P (oldequiv)
7284 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7285 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7286 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7287 || (GET_CODE (oldequiv) == SUBREG
7288 && REG_P (SUBREG_REG (oldequiv))
7289 && (REGNO (SUBREG_REG (oldequiv))
7290 >= FIRST_PSEUDO_REGISTER)
7291 && ((reg_equiv_memory_loc
7292 [REGNO (SUBREG_REG (oldequiv))] != 0)
7293 || (reg_equiv_constant
7294 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7295 || (CONSTANT_P (oldequiv)
7296 && (PREFERRED_RELOAD_CLASS (oldequiv,
7297 REGNO_REG_CLASS (REGNO (reloadreg)))
7299 real_oldequiv = rl->in;
7300 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7304 if (flag_non_call_exceptions)
7305 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7307 /* End this sequence. */
7308 *where = get_insns ();
7311 /* Update reload_override_in so that delete_address_reloads_1
7312 can see the actual register usage. */
7314 reload_override_in[j] = oldequiv;
7317 /* Generate insns to for the output reload RL, which is for the insn described
7318 by CHAIN and has the number J. */
7320 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7324 rtx insn = chain->insn;
7327 enum machine_mode mode;
7331 if (rl->when_needed == RELOAD_OTHER)
7334 push_to_sequence (output_reload_insns[rl->opnum]);
7336 rl_reg_rtx = reload_reg_rtx_for_output[j];
7337 mode = GET_MODE (rl_reg_rtx);
7339 reloadreg = rl_reg_rtx;
7341 /* If we need two reload regs, set RELOADREG to the intermediate
7342 one, since it will be stored into OLD. We might need a secondary
7343 register only for an input reload, so check again here. */
7345 if (rl->secondary_out_reload >= 0)
7348 int secondary_reload = rl->secondary_out_reload;
7349 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7351 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7352 && reg_equiv_mem[REGNO (old)] != 0)
7353 real_old = reg_equiv_mem[REGNO (old)];
7355 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7357 rtx second_reloadreg = reloadreg;
7358 reloadreg = rld[secondary_reload].reg_rtx;
7360 /* See if RELOADREG is to be used as a scratch register
7361 or as an intermediate register. */
7362 if (rl->secondary_out_icode != CODE_FOR_nothing)
7364 /* We'd have to add extra code to handle this case. */
7365 gcc_assert (tertiary_reload < 0);
7367 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7368 (real_old, second_reloadreg, reloadreg)));
7373 /* See if we need both a scratch and intermediate reload
7376 enum insn_code tertiary_icode
7377 = rld[secondary_reload].secondary_out_icode;
7379 /* We'd have to add more code for quartary reloads. */
7380 gcc_assert (tertiary_reload < 0
7381 || rld[tertiary_reload].secondary_out_reload < 0);
7383 if (GET_MODE (reloadreg) != mode)
7384 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7386 if (tertiary_icode != CODE_FOR_nothing)
7388 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7391 /* Copy primary reload reg to secondary reload reg.
7392 (Note that these have been swapped above, then
7393 secondary reload reg to OLD using our insn.) */
7395 /* If REAL_OLD is a paradoxical SUBREG, remove it
7396 and try to put the opposite SUBREG on
7398 if (GET_CODE (real_old) == SUBREG
7399 && (GET_MODE_SIZE (GET_MODE (real_old))
7400 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7401 && 0 != (tem = gen_lowpart_common
7402 (GET_MODE (SUBREG_REG (real_old)),
7404 real_old = SUBREG_REG (real_old), reloadreg = tem;
7406 gen_reload (reloadreg, second_reloadreg,
7407 rl->opnum, rl->when_needed);
7408 emit_insn ((GEN_FCN (tertiary_icode)
7409 (real_old, reloadreg, third_reloadreg)));
7415 /* Copy between the reload regs here and then to
7418 gen_reload (reloadreg, second_reloadreg,
7419 rl->opnum, rl->when_needed);
7420 if (tertiary_reload >= 0)
7422 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7424 gen_reload (third_reloadreg, reloadreg,
7425 rl->opnum, rl->when_needed);
7426 reloadreg = third_reloadreg;
7433 /* Output the last reload insn. */
7438 /* Don't output the last reload if OLD is not the dest of
7439 INSN and is in the src and is clobbered by INSN. */
7440 if (! flag_expensive_optimizations
7442 || !(set = single_set (insn))
7443 || rtx_equal_p (old, SET_DEST (set))
7444 || !reg_mentioned_p (old, SET_SRC (set))
7445 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7446 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7447 gen_reload (old, reloadreg, rl->opnum,
7451 /* Look at all insns we emitted, just to be safe. */
7452 for (p = get_insns (); p; p = NEXT_INSN (p))
7455 rtx pat = PATTERN (p);
7457 /* If this output reload doesn't come from a spill reg,
7458 clear any memory of reloaded copies of the pseudo reg.
7459 If this output reload comes from a spill reg,
7460 reg_has_output_reload will make this do nothing. */
7461 note_stores (pat, forget_old_reloads_1, NULL);
7463 if (reg_mentioned_p (rl_reg_rtx, pat))
7465 rtx set = single_set (insn);
7466 if (reload_spill_index[j] < 0
7468 && SET_SRC (set) == rl_reg_rtx)
7470 int src = REGNO (SET_SRC (set));
7472 reload_spill_index[j] = src;
7473 SET_HARD_REG_BIT (reg_is_output_reload, src);
7474 if (find_regno_note (insn, REG_DEAD, src))
7475 SET_HARD_REG_BIT (reg_reloaded_died, src);
7477 if (HARD_REGISTER_P (rl_reg_rtx))
7479 int s = rl->secondary_out_reload;
7480 set = single_set (p);
7481 /* If this reload copies only to the secondary reload
7482 register, the secondary reload does the actual
7484 if (s >= 0 && set == NULL_RTX)
7485 /* We can't tell what function the secondary reload
7486 has and where the actual store to the pseudo is
7487 made; leave new_spill_reg_store alone. */
7490 && SET_SRC (set) == rl_reg_rtx
7491 && SET_DEST (set) == rld[s].reg_rtx)
7493 /* Usually the next instruction will be the
7494 secondary reload insn; if we can confirm
7495 that it is, setting new_spill_reg_store to
7496 that insn will allow an extra optimization. */
7497 rtx s_reg = rld[s].reg_rtx;
7498 rtx next = NEXT_INSN (p);
7499 rld[s].out = rl->out;
7500 rld[s].out_reg = rl->out_reg;
7501 set = single_set (next);
7502 if (set && SET_SRC (set) == s_reg
7503 && ! new_spill_reg_store[REGNO (s_reg)])
7505 SET_HARD_REG_BIT (reg_is_output_reload,
7507 new_spill_reg_store[REGNO (s_reg)] = next;
7511 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7516 if (rl->when_needed == RELOAD_OTHER)
7518 emit_insn (other_output_reload_insns[rl->opnum]);
7519 other_output_reload_insns[rl->opnum] = get_insns ();
7522 output_reload_insns[rl->opnum] = get_insns ();
7524 if (flag_non_call_exceptions)
7525 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7530 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7531 and has the number J. */
7533 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7535 rtx insn = chain->insn;
7536 rtx old = (rl->in && MEM_P (rl->in)
7537 ? rl->in_reg : rl->in);
7538 rtx reg_rtx = rl->reg_rtx;
7542 enum machine_mode mode;
7544 /* Determine the mode to reload in.
7545 This is very tricky because we have three to choose from.
7546 There is the mode the insn operand wants (rl->inmode).
7547 There is the mode of the reload register RELOADREG.
7548 There is the intrinsic mode of the operand, which we could find
7549 by stripping some SUBREGs.
7550 It turns out that RELOADREG's mode is irrelevant:
7551 we can change that arbitrarily.
7553 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7554 then the reload reg may not support QImode moves, so use SImode.
7555 If foo is in memory due to spilling a pseudo reg, this is safe,
7556 because the QImode value is in the least significant part of a
7557 slot big enough for a SImode. If foo is some other sort of
7558 memory reference, then it is impossible to reload this case,
7559 so previous passes had better make sure this never happens.
7561 Then consider a one-word union which has SImode and one of its
7562 members is a float, being fetched as (SUBREG:SF union:SI).
7563 We must fetch that as SFmode because we could be loading into
7564 a float-only register. In this case OLD's mode is correct.
7566 Consider an immediate integer: it has VOIDmode. Here we need
7567 to get a mode from something else.
7569 In some cases, there is a fourth mode, the operand's
7570 containing mode. If the insn specifies a containing mode for
7571 this operand, it overrides all others.
7573 I am not sure whether the algorithm here is always right,
7574 but it does the right things in those cases. */
7576 mode = GET_MODE (old);
7577 if (mode == VOIDmode)
7580 /* We cannot use gen_lowpart_common since it can do the wrong thing
7581 when REG_RTX has a multi-word mode. Note that REG_RTX must
7582 always be a REG here. */
7583 if (GET_MODE (reg_rtx) != mode)
7584 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7586 reload_reg_rtx_for_input[j] = reg_rtx;
7589 /* AUTO_INC reloads need to be handled even if inherited. We got an
7590 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7591 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7592 && ! rtx_equal_p (reg_rtx, old)
7594 emit_input_reload_insns (chain, rld + j, old, j);
7596 /* When inheriting a wider reload, we have a MEM in rl->in,
7597 e.g. inheriting a SImode output reload for
7598 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7599 if (optimize && reload_inherited[j] && rl->in
7601 && MEM_P (rl->in_reg)
7602 && reload_spill_index[j] >= 0
7603 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7604 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7606 /* If we are reloading a register that was recently stored in with an
7607 output-reload, see if we can prove there was
7608 actually no need to store the old value in it. */
7611 && (reload_inherited[j] || reload_override_in[j])
7614 && spill_reg_store[REGNO (reg_rtx)] != 0
7616 /* There doesn't seem to be any reason to restrict this to pseudos
7617 and doing so loses in the case where we are copying from a
7618 register of the wrong class. */
7619 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7621 /* The insn might have already some references to stackslots
7622 replaced by MEMs, while reload_out_reg still names the
7624 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7625 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7626 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7629 /* Do output reloading for reload RL, which is for the insn described by
7630 CHAIN and has the number J.
7631 ??? At some point we need to support handling output reloads of
7632 JUMP_INSNs or insns that set cc0. */
7634 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7637 rtx insn = chain->insn;
7638 /* If this is an output reload that stores something that is
7639 not loaded in this same reload, see if we can eliminate a previous
7641 rtx pseudo = rl->out_reg;
7642 rtx reg_rtx = rl->reg_rtx;
7644 if (rl->out && reg_rtx)
7646 enum machine_mode mode;
7648 /* Determine the mode to reload in.
7649 See comments above (for input reloading). */
7650 mode = GET_MODE (rl->out);
7651 if (mode == VOIDmode)
7653 /* VOIDmode should never happen for an output. */
7654 if (asm_noperands (PATTERN (insn)) < 0)
7655 /* It's the compiler's fault. */
7656 fatal_insn ("VOIDmode on an output", insn);
7657 error_for_asm (insn, "output operand is constant in %<asm%>");
7658 /* Prevent crash--use something we know is valid. */
7660 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7662 if (GET_MODE (reg_rtx) != mode)
7663 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7665 reload_reg_rtx_for_output[j] = reg_rtx;
7670 && ! rtx_equal_p (rl->in_reg, pseudo)
7671 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7672 && reg_last_reload_reg[REGNO (pseudo)])
7674 int pseudo_no = REGNO (pseudo);
7675 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7677 /* We don't need to test full validity of last_regno for
7678 inherit here; we only want to know if the store actually
7679 matches the pseudo. */
7680 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7681 && reg_reloaded_contents[last_regno] == pseudo_no
7682 && spill_reg_store[last_regno]
7683 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7684 delete_output_reload (insn, j, last_regno, reg_rtx);
7690 || rtx_equal_p (old, reg_rtx))
7693 /* An output operand that dies right away does need a reload,
7694 but need not be copied from it. Show the new location in the
7696 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7697 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7699 XEXP (note, 0) = reg_rtx;
7702 /* Likewise for a SUBREG of an operand that dies. */
7703 else if (GET_CODE (old) == SUBREG
7704 && REG_P (SUBREG_REG (old))
7705 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7708 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7711 else if (GET_CODE (old) == SCRATCH)
7712 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7713 but we don't want to make an output reload. */
7716 /* If is a JUMP_INSN, we can't support output reloads yet. */
7717 gcc_assert (NONJUMP_INSN_P (insn));
7719 emit_output_reload_insns (chain, rld + j, j);
7722 /* A reload copies values of MODE from register SRC to register DEST.
7723 Return true if it can be treated for inheritance purposes like a
7724 group of reloads, each one reloading a single hard register. The
7725 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7726 occupy the same number of hard registers. */
7729 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7730 int src ATTRIBUTE_UNUSED,
7731 enum machine_mode mode ATTRIBUTE_UNUSED)
7733 #ifdef CANNOT_CHANGE_MODE_CLASS
7734 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7735 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7741 /* Output insns to reload values in and out of the chosen reload regs. */
7744 emit_reload_insns (struct insn_chain *chain)
7746 rtx insn = chain->insn;
7750 CLEAR_HARD_REG_SET (reg_reloaded_died);
7752 for (j = 0; j < reload_n_operands; j++)
7753 input_reload_insns[j] = input_address_reload_insns[j]
7754 = inpaddr_address_reload_insns[j]
7755 = output_reload_insns[j] = output_address_reload_insns[j]
7756 = outaddr_address_reload_insns[j]
7757 = other_output_reload_insns[j] = 0;
7758 other_input_address_reload_insns = 0;
7759 other_input_reload_insns = 0;
7760 operand_reload_insns = 0;
7761 other_operand_reload_insns = 0;
7763 /* Dump reloads into the dump file. */
7766 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7767 debug_reload_to_stream (dump_file);
7770 /* Now output the instructions to copy the data into and out of the
7771 reload registers. Do these in the order that the reloads were reported,
7772 since reloads of base and index registers precede reloads of operands
7773 and the operands may need the base and index registers reloaded. */
7775 for (j = 0; j < n_reloads; j++)
7777 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7781 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7782 new_spill_reg_store[i] = 0;
7785 do_input_reload (chain, rld + j, j);
7786 do_output_reload (chain, rld + j, j);
7789 /* Now write all the insns we made for reloads in the order expected by
7790 the allocation functions. Prior to the insn being reloaded, we write
7791 the following reloads:
7793 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7795 RELOAD_OTHER reloads.
7797 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7798 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7799 RELOAD_FOR_INPUT reload for the operand.
7801 RELOAD_FOR_OPADDR_ADDRS reloads.
7803 RELOAD_FOR_OPERAND_ADDRESS reloads.
7805 After the insn being reloaded, we write the following:
7807 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7808 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7809 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7810 reloads for the operand. The RELOAD_OTHER output reloads are
7811 output in descending order by reload number. */
7813 emit_insn_before (other_input_address_reload_insns, insn);
7814 emit_insn_before (other_input_reload_insns, insn);
7816 for (j = 0; j < reload_n_operands; j++)
7818 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7819 emit_insn_before (input_address_reload_insns[j], insn);
7820 emit_insn_before (input_reload_insns[j], insn);
7823 emit_insn_before (other_operand_reload_insns, insn);
7824 emit_insn_before (operand_reload_insns, insn);
7826 for (j = 0; j < reload_n_operands; j++)
7828 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7829 x = emit_insn_after (output_address_reload_insns[j], x);
7830 x = emit_insn_after (output_reload_insns[j], x);
7831 emit_insn_after (other_output_reload_insns[j], x);
7834 /* For all the spill regs newly reloaded in this instruction,
7835 record what they were reloaded from, so subsequent instructions
7836 can inherit the reloads.
7838 Update spill_reg_store for the reloads of this insn.
7839 Copy the elements that were updated in the loop above. */
7841 for (j = 0; j < n_reloads; j++)
7843 int r = reload_order[j];
7844 int i = reload_spill_index[r];
7846 /* If this is a non-inherited input reload from a pseudo, we must
7847 clear any memory of a previous store to the same pseudo. Only do
7848 something if there will not be an output reload for the pseudo
7850 if (rld[r].in_reg != 0
7851 && ! (reload_inherited[r] || reload_override_in[r]))
7853 rtx reg = rld[r].in_reg;
7855 if (GET_CODE (reg) == SUBREG)
7856 reg = SUBREG_REG (reg);
7859 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7860 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7862 int nregno = REGNO (reg);
7864 if (reg_last_reload_reg[nregno])
7866 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7868 if (reg_reloaded_contents[last_regno] == nregno)
7869 spill_reg_store[last_regno] = 0;
7874 /* I is nonneg if this reload used a register.
7875 If rld[r].reg_rtx is 0, this is an optional reload
7876 that we opted to ignore. */
7878 if (i >= 0 && rld[r].reg_rtx != 0)
7880 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7883 /* For a multi register reload, we need to check if all or part
7884 of the value lives to the end. */
7885 for (k = 0; k < nr; k++)
7886 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7887 rld[r].when_needed))
7888 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7890 /* Maybe the spill reg contains a copy of reload_out. */
7892 && (REG_P (rld[r].out)
7896 || REG_P (rld[r].out_reg)))
7899 enum machine_mode mode;
7902 reg = reload_reg_rtx_for_output[r];
7903 mode = GET_MODE (reg);
7904 regno = REGNO (reg);
7905 nregs = hard_regno_nregs[regno][mode];
7906 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7907 rld[r].when_needed))
7909 rtx out = (REG_P (rld[r].out)
7913 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7914 int out_regno = REGNO (out);
7915 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7916 : hard_regno_nregs[out_regno][mode]);
7919 spill_reg_store[regno] = new_spill_reg_store[regno];
7920 spill_reg_stored_to[regno] = out;
7921 reg_last_reload_reg[out_regno] = reg;
7923 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7924 && nregs == out_nregs
7925 && inherit_piecemeal_p (out_regno, regno, mode));
7927 /* If OUT_REGNO is a hard register, it may occupy more than
7928 one register. If it does, say what is in the
7929 rest of the registers assuming that both registers
7930 agree on how many words the object takes. If not,
7931 invalidate the subsequent registers. */
7933 if (HARD_REGISTER_NUM_P (out_regno))
7934 for (k = 1; k < out_nregs; k++)
7935 reg_last_reload_reg[out_regno + k]
7936 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7938 /* Now do the inverse operation. */
7939 for (k = 0; k < nregs; k++)
7941 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7942 reg_reloaded_contents[regno + k]
7943 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7946 reg_reloaded_insn[regno + k] = insn;
7947 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7948 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7949 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7952 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7957 /* Maybe the spill reg contains a copy of reload_in. Only do
7958 something if there will not be an output reload for
7959 the register being reloaded. */
7960 else if (rld[r].out_reg == 0
7962 && ((REG_P (rld[r].in)
7963 && !HARD_REGISTER_P (rld[r].in)
7964 && !REGNO_REG_SET_P (®_has_output_reload,
7966 || (REG_P (rld[r].in_reg)
7967 && !REGNO_REG_SET_P (®_has_output_reload,
7968 REGNO (rld[r].in_reg))))
7969 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7972 enum machine_mode mode;
7975 reg = reload_reg_rtx_for_input[r];
7976 mode = GET_MODE (reg);
7977 regno = REGNO (reg);
7978 nregs = hard_regno_nregs[regno][mode];
7979 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7980 rld[r].when_needed))
7987 if (REG_P (rld[r].in)
7988 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7990 else if (REG_P (rld[r].in_reg))
7993 in = XEXP (rld[r].in_reg, 0);
7994 in_regno = REGNO (in);
7996 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7997 : hard_regno_nregs[in_regno][mode]);
7999 reg_last_reload_reg[in_regno] = reg;
8001 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8002 && nregs == in_nregs
8003 && inherit_piecemeal_p (regno, in_regno, mode));
8005 if (HARD_REGISTER_NUM_P (in_regno))
8006 for (k = 1; k < in_nregs; k++)
8007 reg_last_reload_reg[in_regno + k]
8008 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8010 /* Unless we inherited this reload, show we haven't
8011 recently done a store.
8012 Previous stores of inherited auto_inc expressions
8013 also have to be discarded. */
8014 if (! reload_inherited[r]
8015 || (rld[r].out && ! rld[r].out_reg))
8016 spill_reg_store[regno] = 0;
8018 for (k = 0; k < nregs; k++)
8020 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8021 reg_reloaded_contents[regno + k]
8022 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8025 reg_reloaded_insn[regno + k] = insn;
8026 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8027 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8028 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8031 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8038 /* The following if-statement was #if 0'd in 1.34 (or before...).
8039 It's reenabled in 1.35 because supposedly nothing else
8040 deals with this problem. */
8042 /* If a register gets output-reloaded from a non-spill register,
8043 that invalidates any previous reloaded copy of it.
8044 But forget_old_reloads_1 won't get to see it, because
8045 it thinks only about the original insn. So invalidate it here.
8046 Also do the same thing for RELOAD_OTHER constraints where the
8047 output is discarded. */
8049 && ((rld[r].out != 0
8050 && (REG_P (rld[r].out)
8051 || (MEM_P (rld[r].out)
8052 && REG_P (rld[r].out_reg))))
8053 || (rld[r].out == 0 && rld[r].out_reg
8054 && REG_P (rld[r].out_reg))))
8056 rtx out = ((rld[r].out && REG_P (rld[r].out))
8057 ? rld[r].out : rld[r].out_reg);
8058 int out_regno = REGNO (out);
8059 enum machine_mode mode = GET_MODE (out);
8061 /* REG_RTX is now set or clobbered by the main instruction.
8062 As the comment above explains, forget_old_reloads_1 only
8063 sees the original instruction, and there is no guarantee
8064 that the original instruction also clobbered REG_RTX.
8065 For example, if find_reloads sees that the input side of
8066 a matched operand pair dies in this instruction, it may
8067 use the input register as the reload register.
8069 Calling forget_old_reloads_1 is a waste of effort if
8070 REG_RTX is also the output register.
8072 If we know that REG_RTX holds the value of a pseudo
8073 register, the code after the call will record that fact. */
8074 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8075 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8077 if (!HARD_REGISTER_NUM_P (out_regno))
8079 rtx src_reg, store_insn = NULL_RTX;
8081 reg_last_reload_reg[out_regno] = 0;
8083 /* If we can find a hard register that is stored, record
8084 the storing insn so that we may delete this insn with
8085 delete_output_reload. */
8086 src_reg = reload_reg_rtx_for_output[r];
8088 /* If this is an optional reload, try to find the source reg
8089 from an input reload. */
8092 rtx set = single_set (insn);
8093 if (set && SET_DEST (set) == rld[r].out)
8097 src_reg = SET_SRC (set);
8099 for (k = 0; k < n_reloads; k++)
8101 if (rld[k].in == src_reg)
8103 src_reg = reload_reg_rtx_for_input[k];
8110 store_insn = new_spill_reg_store[REGNO (src_reg)];
8111 if (src_reg && REG_P (src_reg)
8112 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8114 int src_regno, src_nregs, k;
8117 gcc_assert (GET_MODE (src_reg) == mode);
8118 src_regno = REGNO (src_reg);
8119 src_nregs = hard_regno_nregs[src_regno][mode];
8120 /* The place where to find a death note varies with
8121 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8122 necessarily checked exactly in the code that moves
8123 notes, so just check both locations. */
8124 note = find_regno_note (insn, REG_DEAD, src_regno);
8125 if (! note && store_insn)
8126 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8127 for (k = 0; k < src_nregs; k++)
8129 spill_reg_store[src_regno + k] = store_insn;
8130 spill_reg_stored_to[src_regno + k] = out;
8131 reg_reloaded_contents[src_regno + k] = out_regno;
8132 reg_reloaded_insn[src_regno + k] = store_insn;
8133 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8134 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8135 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8137 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8140 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8142 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8144 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8146 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8148 reg_last_reload_reg[out_regno] = src_reg;
8149 /* We have to set reg_has_output_reload here, or else
8150 forget_old_reloads_1 will clear reg_last_reload_reg
8152 SET_REGNO_REG_SET (®_has_output_reload,
8158 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8160 for (k = 0; k < out_nregs; k++)
8161 reg_last_reload_reg[out_regno + k] = 0;
8165 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8168 /* Go through the motions to emit INSN and test if it is strictly valid.
8169 Return the emitted insn if valid, else return NULL. */
8172 emit_insn_if_valid_for_reload (rtx insn)
8174 rtx last = get_last_insn ();
8177 insn = emit_insn (insn);
8178 code = recog_memoized (insn);
8182 extract_insn (insn);
8183 /* We want constrain operands to treat this insn strictly in its
8184 validity determination, i.e., the way it would after reload has
8186 if (constrain_operands (1))
8190 delete_insns_since (last);
8194 /* Emit code to perform a reload from IN (which may be a reload register) to
8195 OUT (which may also be a reload register). IN or OUT is from operand
8196 OPNUM with reload type TYPE.
8198 Returns first insn emitted. */
8201 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8203 rtx last = get_last_insn ();
8206 /* If IN is a paradoxical SUBREG, remove it and try to put the
8207 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8208 if (GET_CODE (in) == SUBREG
8209 && (GET_MODE_SIZE (GET_MODE (in))
8210 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8211 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8212 in = SUBREG_REG (in), out = tem;
8213 else if (GET_CODE (out) == SUBREG
8214 && (GET_MODE_SIZE (GET_MODE (out))
8215 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8216 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8217 out = SUBREG_REG (out), in = tem;
8219 /* How to do this reload can get quite tricky. Normally, we are being
8220 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8221 register that didn't get a hard register. In that case we can just
8222 call emit_move_insn.
8224 We can also be asked to reload a PLUS that adds a register or a MEM to
8225 another register, constant or MEM. This can occur during frame pointer
8226 elimination and while reloading addresses. This case is handled by
8227 trying to emit a single insn to perform the add. If it is not valid,
8228 we use a two insn sequence.
8230 Or we can be asked to reload an unary operand that was a fragment of
8231 an addressing mode, into a register. If it isn't recognized as-is,
8232 we try making the unop operand and the reload-register the same:
8233 (set reg:X (unop:X expr:Y))
8234 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8236 Finally, we could be called to handle an 'o' constraint by putting
8237 an address into a register. In that case, we first try to do this
8238 with a named pattern of "reload_load_address". If no such pattern
8239 exists, we just emit a SET insn and hope for the best (it will normally
8240 be valid on machines that use 'o').
8242 This entire process is made complex because reload will never
8243 process the insns we generate here and so we must ensure that
8244 they will fit their constraints and also by the fact that parts of
8245 IN might be being reloaded separately and replaced with spill registers.
8246 Because of this, we are, in some sense, just guessing the right approach
8247 here. The one listed above seems to work.
8249 ??? At some point, this whole thing needs to be rethought. */
8251 if (GET_CODE (in) == PLUS
8252 && (REG_P (XEXP (in, 0))
8253 || GET_CODE (XEXP (in, 0)) == SUBREG
8254 || MEM_P (XEXP (in, 0)))
8255 && (REG_P (XEXP (in, 1))
8256 || GET_CODE (XEXP (in, 1)) == SUBREG
8257 || CONSTANT_P (XEXP (in, 1))
8258 || MEM_P (XEXP (in, 1))))
8260 /* We need to compute the sum of a register or a MEM and another
8261 register, constant, or MEM, and put it into the reload
8262 register. The best possible way of doing this is if the machine
8263 has a three-operand ADD insn that accepts the required operands.
8265 The simplest approach is to try to generate such an insn and see if it
8266 is recognized and matches its constraints. If so, it can be used.
8268 It might be better not to actually emit the insn unless it is valid,
8269 but we need to pass the insn as an operand to `recog' and
8270 `extract_insn' and it is simpler to emit and then delete the insn if
8271 not valid than to dummy things up. */
8273 rtx op0, op1, tem, insn;
8276 op0 = find_replacement (&XEXP (in, 0));
8277 op1 = find_replacement (&XEXP (in, 1));
8279 /* Since constraint checking is strict, commutativity won't be
8280 checked, so we need to do that here to avoid spurious failure
8281 if the add instruction is two-address and the second operand
8282 of the add is the same as the reload reg, which is frequently
8283 the case. If the insn would be A = B + A, rearrange it so
8284 it will be A = A + B as constrain_operands expects. */
8286 if (REG_P (XEXP (in, 1))
8287 && REGNO (out) == REGNO (XEXP (in, 1)))
8288 tem = op0, op0 = op1, op1 = tem;
8290 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8291 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8293 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8297 /* If that failed, we must use a conservative two-insn sequence.
8299 Use a move to copy one operand into the reload register. Prefer
8300 to reload a constant, MEM or pseudo since the move patterns can
8301 handle an arbitrary operand. If OP1 is not a constant, MEM or
8302 pseudo and OP1 is not a valid operand for an add instruction, then
8305 After reloading one of the operands into the reload register, add
8306 the reload register to the output register.
8308 If there is another way to do this for a specific machine, a
8309 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8312 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8314 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8316 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8317 || (code != CODE_FOR_nothing
8318 && ! ((*insn_data[code].operand[2].predicate)
8319 (op1, insn_data[code].operand[2].mode))))
8320 tem = op0, op0 = op1, op1 = tem;
8322 gen_reload (out, op0, opnum, type);
8324 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8325 This fixes a problem on the 32K where the stack pointer cannot
8326 be used as an operand of an add insn. */
8328 if (rtx_equal_p (op0, op1))
8331 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8334 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8335 set_unique_reg_note (insn, REG_EQUIV, in);
8339 /* If that failed, copy the address register to the reload register.
8340 Then add the constant to the reload register. */
8342 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8343 gen_reload (out, op1, opnum, type);
8344 insn = emit_insn (gen_add2_insn (out, op0));
8345 set_unique_reg_note (insn, REG_EQUIV, in);
8348 #ifdef SECONDARY_MEMORY_NEEDED
8349 /* If we need a memory location to do the move, do it that way. */
8350 else if ((REG_P (in)
8351 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8352 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8354 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8355 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8356 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8357 REGNO_REG_CLASS (reg_or_subregno (out)),
8360 /* Get the memory to use and rewrite both registers to its mode. */
8361 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8363 if (GET_MODE (loc) != GET_MODE (out))
8364 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8366 if (GET_MODE (loc) != GET_MODE (in))
8367 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8369 gen_reload (loc, in, opnum, type);
8370 gen_reload (out, loc, opnum, type);
8373 else if (REG_P (out) && UNARY_P (in))
8380 op1 = find_replacement (&XEXP (in, 0));
8381 if (op1 != XEXP (in, 0))
8382 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8384 /* First, try a plain SET. */
8385 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8389 /* If that failed, move the inner operand to the reload
8390 register, and try the same unop with the inner expression
8391 replaced with the reload register. */
8393 if (GET_MODE (op1) != GET_MODE (out))
8394 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8398 gen_reload (out_moded, op1, opnum, type);
8401 = gen_rtx_SET (VOIDmode, out,
8402 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8404 insn = emit_insn_if_valid_for_reload (insn);
8407 set_unique_reg_note (insn, REG_EQUIV, in);
8411 fatal_insn ("Failure trying to reload:", set);
8413 /* If IN is a simple operand, use gen_move_insn. */
8414 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8416 tem = emit_insn (gen_move_insn (out, in));
8417 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8418 mark_jump_label (in, tem, 0);
8421 #ifdef HAVE_reload_load_address
8422 else if (HAVE_reload_load_address)
8423 emit_insn (gen_reload_load_address (out, in));
8426 /* Otherwise, just write (set OUT IN) and hope for the best. */
8428 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8430 /* Return the first insn emitted.
8431 We can not just return get_last_insn, because there may have
8432 been multiple instructions emitted. Also note that gen_move_insn may
8433 emit more than one insn itself, so we can not assume that there is one
8434 insn emitted per emit_insn_before call. */
8436 return last ? NEXT_INSN (last) : get_insns ();
8439 /* Delete a previously made output-reload whose result we now believe
8440 is not needed. First we double-check.
8442 INSN is the insn now being processed.
8443 LAST_RELOAD_REG is the hard register number for which we want to delete
8444 the last output reload.
8445 J is the reload-number that originally used REG. The caller has made
8446 certain that reload J doesn't use REG any longer for input.
8447 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8450 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8452 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8453 rtx reg = spill_reg_stored_to[last_reload_reg];
8456 int n_inherited = 0;
8460 /* It is possible that this reload has been only used to set another reload
8461 we eliminated earlier and thus deleted this instruction too. */
8462 if (INSN_DELETED_P (output_reload_insn))
8465 /* Get the raw pseudo-register referred to. */
8467 while (GET_CODE (reg) == SUBREG)
8468 reg = SUBREG_REG (reg);
8469 substed = reg_equiv_memory_loc[REGNO (reg)];
8471 /* This is unsafe if the operand occurs more often in the current
8472 insn than it is inherited. */
8473 for (k = n_reloads - 1; k >= 0; k--)
8475 rtx reg2 = rld[k].in;
8478 if (MEM_P (reg2) || reload_override_in[k])
8479 reg2 = rld[k].in_reg;
8481 if (rld[k].out && ! rld[k].out_reg)
8482 reg2 = XEXP (rld[k].in_reg, 0);
8484 while (GET_CODE (reg2) == SUBREG)
8485 reg2 = SUBREG_REG (reg2);
8486 if (rtx_equal_p (reg2, reg))
8488 if (reload_inherited[k] || reload_override_in[k] || k == j)
8494 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8495 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8496 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8499 n_occurrences += count_occurrences (PATTERN (insn),
8500 eliminate_regs (substed, VOIDmode,
8502 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8504 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8505 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8507 if (n_occurrences > n_inherited)
8510 /* If the pseudo-reg we are reloading is no longer referenced
8511 anywhere between the store into it and here,
8512 and we're within the same basic block, then the value can only
8513 pass through the reload reg and end up here.
8514 Otherwise, give up--return. */
8515 for (i1 = NEXT_INSN (output_reload_insn);
8516 i1 != insn; i1 = NEXT_INSN (i1))
8518 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8520 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8521 && reg_mentioned_p (reg, PATTERN (i1)))
8523 /* If this is USE in front of INSN, we only have to check that
8524 there are no more references than accounted for by inheritance. */
8525 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8527 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8528 i1 = NEXT_INSN (i1);
8530 if (n_occurrences <= n_inherited && i1 == insn)
8536 /* We will be deleting the insn. Remove the spill reg information. */
8537 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8539 spill_reg_store[last_reload_reg + k] = 0;
8540 spill_reg_stored_to[last_reload_reg + k] = 0;
8543 /* The caller has already checked that REG dies or is set in INSN.
8544 It has also checked that we are optimizing, and thus some
8545 inaccuracies in the debugging information are acceptable.
8546 So we could just delete output_reload_insn. But in some cases
8547 we can improve the debugging information without sacrificing
8548 optimization - maybe even improving the code: See if the pseudo
8549 reg has been completely replaced with reload regs. If so, delete
8550 the store insn and forget we had a stack slot for the pseudo. */
8551 if (rld[j].out != rld[j].in
8552 && REG_N_DEATHS (REGNO (reg)) == 1
8553 && REG_N_SETS (REGNO (reg)) == 1
8554 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8555 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8559 /* We know that it was used only between here and the beginning of
8560 the current basic block. (We also know that the last use before
8561 INSN was the output reload we are thinking of deleting, but never
8562 mind that.) Search that range; see if any ref remains. */
8563 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8565 rtx set = single_set (i2);
8567 /* Uses which just store in the pseudo don't count,
8568 since if they are the only uses, they are dead. */
8569 if (set != 0 && SET_DEST (set) == reg)
8574 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8575 && reg_mentioned_p (reg, PATTERN (i2)))
8577 /* Some other ref remains; just delete the output reload we
8579 delete_address_reloads (output_reload_insn, insn);
8580 delete_insn (output_reload_insn);
8585 /* Delete the now-dead stores into this pseudo. Note that this
8586 loop also takes care of deleting output_reload_insn. */
8587 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8589 rtx set = single_set (i2);
8591 if (set != 0 && SET_DEST (set) == reg)
8593 delete_address_reloads (i2, insn);
8601 /* For the debugging info, say the pseudo lives in this reload reg. */
8602 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8603 if (ira_conflicts_p)
8604 /* Inform IRA about the change. */
8605 ira_mark_allocation_change (REGNO (reg));
8606 alter_reg (REGNO (reg), -1, false);
8610 delete_address_reloads (output_reload_insn, insn);
8611 delete_insn (output_reload_insn);
8615 /* We are going to delete DEAD_INSN. Recursively delete loads of
8616 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8617 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8619 delete_address_reloads (rtx dead_insn, rtx current_insn)
8621 rtx set = single_set (dead_insn);
8622 rtx set2, dst, prev, next;
8625 rtx dst = SET_DEST (set);
8627 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8629 /* If we deleted the store from a reloaded post_{in,de}c expression,
8630 we can delete the matching adds. */
8631 prev = PREV_INSN (dead_insn);
8632 next = NEXT_INSN (dead_insn);
8633 if (! prev || ! next)
8635 set = single_set (next);
8636 set2 = single_set (prev);
8638 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8639 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8640 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8642 dst = SET_DEST (set);
8643 if (! rtx_equal_p (dst, SET_DEST (set2))
8644 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8645 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8646 || (INTVAL (XEXP (SET_SRC (set), 1))
8647 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8649 delete_related_insns (prev);
8650 delete_related_insns (next);
8653 /* Subfunction of delete_address_reloads: process registers found in X. */
8655 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8657 rtx prev, set, dst, i2;
8659 enum rtx_code code = GET_CODE (x);
8663 const char *fmt = GET_RTX_FORMAT (code);
8664 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8667 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8668 else if (fmt[i] == 'E')
8670 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8671 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8678 if (spill_reg_order[REGNO (x)] < 0)
8681 /* Scan backwards for the insn that sets x. This might be a way back due
8683 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8685 code = GET_CODE (prev);
8686 if (code == CODE_LABEL || code == JUMP_INSN)
8690 if (reg_set_p (x, PATTERN (prev)))
8692 if (reg_referenced_p (x, PATTERN (prev)))
8695 if (! prev || INSN_UID (prev) < reload_first_uid)
8697 /* Check that PREV only sets the reload register. */
8698 set = single_set (prev);
8701 dst = SET_DEST (set);
8703 || ! rtx_equal_p (dst, x))
8705 if (! reg_set_p (dst, PATTERN (dead_insn)))
8707 /* Check if DST was used in a later insn -
8708 it might have been inherited. */
8709 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8715 if (reg_referenced_p (dst, PATTERN (i2)))
8717 /* If there is a reference to the register in the current insn,
8718 it might be loaded in a non-inherited reload. If no other
8719 reload uses it, that means the register is set before
8721 if (i2 == current_insn)
8723 for (j = n_reloads - 1; j >= 0; j--)
8724 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8725 || reload_override_in[j] == dst)
8727 for (j = n_reloads - 1; j >= 0; j--)
8728 if (rld[j].in && rld[j].reg_rtx == dst)
8737 /* If DST is still live at CURRENT_INSN, check if it is used for
8738 any reload. Note that even if CURRENT_INSN sets DST, we still
8739 have to check the reloads. */
8740 if (i2 == current_insn)
8742 for (j = n_reloads - 1; j >= 0; j--)
8743 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8744 || reload_override_in[j] == dst)
8746 /* ??? We can't finish the loop here, because dst might be
8747 allocated to a pseudo in this block if no reload in this
8748 block needs any of the classes containing DST - see
8749 spill_hard_reg. There is no easy way to tell this, so we
8750 have to scan till the end of the basic block. */
8752 if (reg_set_p (dst, PATTERN (i2)))
8756 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8757 reg_reloaded_contents[REGNO (dst)] = -1;
8761 /* Output reload-insns to reload VALUE into RELOADREG.
8762 VALUE is an autoincrement or autodecrement RTX whose operand
8763 is a register or memory location;
8764 so reloading involves incrementing that location.
8765 IN is either identical to VALUE, or some cheaper place to reload from.
8767 INC_AMOUNT is the number to increment or decrement by (always positive).
8768 This cannot be deduced from VALUE.
8770 Return the instruction that stores into RELOADREG. */
8773 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8775 /* REG or MEM to be copied and incremented. */
8776 rtx incloc = find_replacement (&XEXP (value, 0));
8777 /* Nonzero if increment after copying. */
8778 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8779 || GET_CODE (value) == POST_MODIFY);
8785 rtx real_in = in == value ? incloc : in;
8787 /* No hard register is equivalent to this register after
8788 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8789 we could inc/dec that register as well (maybe even using it for
8790 the source), but I'm not sure it's worth worrying about. */
8792 reg_last_reload_reg[REGNO (incloc)] = 0;
8794 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8796 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8797 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8801 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8802 inc_amount = -inc_amount;
8804 inc = GEN_INT (inc_amount);
8807 /* If this is post-increment, first copy the location to the reload reg. */
8808 if (post && real_in != reloadreg)
8809 emit_insn (gen_move_insn (reloadreg, real_in));
8813 /* See if we can directly increment INCLOC. Use a method similar to
8814 that in gen_reload. */
8816 last = get_last_insn ();
8817 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8818 gen_rtx_PLUS (GET_MODE (incloc),
8821 code = recog_memoized (add_insn);
8824 extract_insn (add_insn);
8825 if (constrain_operands (1))
8827 /* If this is a pre-increment and we have incremented the value
8828 where it lives, copy the incremented value to RELOADREG to
8829 be used as an address. */
8832 emit_insn (gen_move_insn (reloadreg, incloc));
8837 delete_insns_since (last);
8840 /* If couldn't do the increment directly, must increment in RELOADREG.
8841 The way we do this depends on whether this is pre- or post-increment.
8842 For pre-increment, copy INCLOC to the reload register, increment it
8843 there, then save back. */
8847 if (in != reloadreg)
8848 emit_insn (gen_move_insn (reloadreg, real_in));
8849 emit_insn (gen_add2_insn (reloadreg, inc));
8850 store = emit_insn (gen_move_insn (incloc, reloadreg));
8855 Because this might be a jump insn or a compare, and because RELOADREG
8856 may not be available after the insn in an input reload, we must do
8857 the incrementation before the insn being reloaded for.
8859 We have already copied IN to RELOADREG. Increment the copy in
8860 RELOADREG, save that back, then decrement RELOADREG so it has
8861 the original value. */
8863 emit_insn (gen_add2_insn (reloadreg, inc));
8864 store = emit_insn (gen_move_insn (incloc, reloadreg));
8865 if (CONST_INT_P (inc))
8866 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8868 emit_insn (gen_sub2_insn (reloadreg, inc));
8876 add_auto_inc_notes (rtx insn, rtx x)
8878 enum rtx_code code = GET_CODE (x);
8882 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8884 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8888 /* Scan all the operand sub-expressions. */
8889 fmt = GET_RTX_FORMAT (code);
8890 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8893 add_auto_inc_notes (insn, XEXP (x, i));
8894 else if (fmt[i] == 'E')
8895 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8896 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8901 /* This is used by reload pass, that does emit some instructions after
8902 abnormal calls moving basic block end, but in fact it wants to emit
8903 them on the edge. Looks for abnormal call edges, find backward the
8904 proper call and fix the damage.
8906 Similar handle instructions throwing exceptions internally. */
8908 fixup_abnormal_edges (void)
8910 bool inserted = false;
8918 /* Look for cases we are interested in - calls or instructions causing
8920 FOR_EACH_EDGE (e, ei, bb->succs)
8922 if (e->flags & EDGE_ABNORMAL_CALL)
8924 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8925 == (EDGE_ABNORMAL | EDGE_EH))
8928 if (e && !CALL_P (BB_END (bb))
8929 && !can_throw_internal (BB_END (bb)))
8933 /* Get past the new insns generated. Allow notes, as the insns
8934 may be already deleted. */
8936 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8937 && !can_throw_internal (insn)
8938 && insn != BB_HEAD (bb))
8939 insn = PREV_INSN (insn);
8941 if (CALL_P (insn) || can_throw_internal (insn))
8945 stop = NEXT_INSN (BB_END (bb));
8947 insn = NEXT_INSN (insn);
8949 FOR_EACH_EDGE (e, ei, bb->succs)
8950 if (e->flags & EDGE_FALLTHRU)
8953 while (insn && insn != stop)
8955 next = NEXT_INSN (insn);
8960 /* Sometimes there's still the return value USE.
8961 If it's placed after a trapping call (i.e. that
8962 call is the last insn anyway), we have no fallthru
8963 edge. Simply delete this use and don't try to insert
8964 on the non-existent edge. */
8965 if (GET_CODE (PATTERN (insn)) != USE)
8967 /* We're not deleting it, we're moving it. */
8968 INSN_DELETED_P (insn) = 0;
8969 PREV_INSN (insn) = NULL_RTX;
8970 NEXT_INSN (insn) = NULL_RTX;
8972 insert_insn_on_edge (insn, e);
8976 else if (!BARRIER_P (insn))
8977 set_block_for_insn (insn, NULL);
8982 /* It may be that we don't find any such trapping insn. In this
8983 case we discovered quite late that the insn that had been
8984 marked as can_throw_internal in fact couldn't trap at all.
8985 So we should in fact delete the EH edges out of the block. */
8987 purge_dead_edges (bb);
8991 /* We've possibly turned single trapping insn into multiple ones. */
8992 if (flag_non_call_exceptions)
8995 blocks = sbitmap_alloc (last_basic_block);
8996 sbitmap_ones (blocks);
8997 find_many_sub_basic_blocks (blocks);
8998 sbitmap_free (blocks);
9002 commit_edge_insertions ();
9004 #ifdef ENABLE_CHECKING
9005 /* Verify that we didn't turn one trapping insn into many, and that
9006 we found and corrected all of the problems wrt fixups on the
9008 verify_flow_info ();
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