1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(m, x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void replace_pseudos_in_call_usage PARAMS((rtx *,
376 static void maybe_fix_stack_asms PARAMS ((void));
377 static void copy_reloads PARAMS ((struct insn_chain *));
378 static void calculate_needs_all_insns PARAMS ((int));
379 static int find_reg PARAMS ((struct insn_chain *, int));
380 static void find_reload_regs PARAMS ((struct insn_chain *));
381 static void select_reload_regs PARAMS ((void));
382 static void delete_caller_save_insns PARAMS ((void));
384 static void spill_failure PARAMS ((rtx, enum reg_class));
385 static void count_spilled_pseudo PARAMS ((int, int, int));
386 static void delete_dead_insn PARAMS ((rtx));
387 static void alter_reg PARAMS ((int, int));
388 static void set_label_offsets PARAMS ((rtx, rtx, int));
389 static void check_eliminable_occurrences PARAMS ((rtx));
390 static void elimination_effects PARAMS ((rtx, enum machine_mode));
391 static int eliminate_regs_in_insn PARAMS ((rtx, int));
392 static void update_eliminable_offsets PARAMS ((void));
393 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
394 static void set_initial_elim_offsets PARAMS ((void));
395 static void verify_initial_elim_offsets PARAMS ((void));
396 static void set_initial_label_offsets PARAMS ((void));
397 static void set_offsets_for_label PARAMS ((rtx));
398 static void init_elim_table PARAMS ((void));
399 static void update_eliminables PARAMS ((HARD_REG_SET *));
400 static void spill_hard_reg PARAMS ((unsigned int, int));
401 static int finish_spills PARAMS ((int));
402 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
403 static void scan_paradoxical_subregs PARAMS ((rtx));
404 static void count_pseudo PARAMS ((int));
405 static void order_regs_for_reload PARAMS ((struct insn_chain *));
406 static void reload_as_needed PARAMS ((int));
407 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
408 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
409 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
412 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
415 static int reload_reg_free_p PARAMS ((unsigned int, int,
417 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
419 rtx, rtx, int, int));
420 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
421 enum reload_type, rtx, rtx,
423 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
425 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
427 static int conflicts_with_override PARAMS ((rtx));
428 static void failed_reload PARAMS ((rtx, int));
429 static int set_reload_reg PARAMS ((int, int));
430 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
431 static void choose_reload_regs PARAMS ((struct insn_chain *));
432 static void merge_assigned_reloads PARAMS ((rtx));
433 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
434 struct reload *, rtx, int));
435 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void do_input_reload PARAMS ((struct insn_chain *,
438 struct reload *, int));
439 static void do_output_reload PARAMS ((struct insn_chain *,
440 struct reload *, int));
441 static void emit_reload_insns PARAMS ((struct insn_chain *));
442 static void delete_output_reload PARAMS ((rtx, int, int));
443 static void delete_address_reloads PARAMS ((rtx, rtx));
444 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
445 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
446 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
447 static void reload_cse_regs_1 PARAMS ((rtx));
448 static int reload_cse_noop_set_p PARAMS ((rtx));
449 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
450 static int reload_cse_simplify_operands PARAMS ((rtx));
451 static void reload_combine PARAMS ((void));
452 static void reload_combine_note_use PARAMS ((rtx *, rtx));
453 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
454 static void reload_cse_move2add PARAMS ((rtx));
455 static void move2add_note_store PARAMS ((rtx, rtx, void *));
457 static void add_auto_inc_notes PARAMS ((rtx, rtx));
459 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
461 static void failed_reload PARAMS ((rtx, int));
462 static int set_reload_reg PARAMS ((int, int));
463 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
464 static void reload_cse_simplify PARAMS ((rtx));
465 extern void dump_needs PARAMS ((struct insn_chain *));
467 /* Initialize the reload pass once per compilation. */
474 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
475 Set spill_indirect_levels to the number of levels such addressing is
476 permitted, zero if it is not permitted at all. */
479 = gen_rtx_MEM (Pmode,
482 LAST_VIRTUAL_REGISTER + 1),
484 spill_indirect_levels = 0;
486 while (memory_address_p (QImode, tem))
488 spill_indirect_levels++;
489 tem = gen_rtx_MEM (Pmode, tem);
492 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
494 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
495 indirect_symref_ok = memory_address_p (QImode, tem);
497 /* See if reg+reg is a valid (and offsettable) address. */
499 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
501 tem = gen_rtx_PLUS (Pmode,
502 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
503 gen_rtx_REG (Pmode, i));
505 /* This way, we make sure that reg+reg is an offsettable address. */
506 tem = plus_constant (tem, 4);
508 if (memory_address_p (QImode, tem))
510 double_reg_address_ok = 1;
515 /* Initialize obstack for our rtl allocation. */
516 gcc_obstack_init (&reload_obstack);
517 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
519 INIT_REG_SET (&spilled_pseudos);
520 INIT_REG_SET (&pseudos_counted);
523 /* List of insn chains that are currently unused. */
524 static struct insn_chain *unused_insn_chains = 0;
526 /* Allocate an empty insn_chain structure. */
530 struct insn_chain *c;
532 if (unused_insn_chains == 0)
534 c = (struct insn_chain *)
535 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
536 INIT_REG_SET (&c->live_throughout);
537 INIT_REG_SET (&c->dead_or_set);
541 c = unused_insn_chains;
542 unused_insn_chains = c->next;
544 c->is_caller_save_insn = 0;
545 c->need_operand_change = 0;
551 /* Small utility function to set all regs in hard reg set TO which are
552 allocated to pseudos in regset FROM. */
555 compute_use_by_pseudos (to, from)
561 EXECUTE_IF_SET_IN_REG_SET
562 (from, FIRST_PSEUDO_REGISTER, regno,
564 int r = reg_renumber[regno];
569 /* reload_combine uses the information from
570 BASIC_BLOCK->global_live_at_start, which might still
571 contain registers that have not actually been allocated
572 since they have an equivalence. */
573 if (! reload_completed)
578 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
580 SET_HARD_REG_BIT (*to, r + nregs);
585 /* Replace all pseudos found in LOC with their corresponding
589 replace_pseudos_in_call_usage (loc, mem_mode, usage)
591 enum machine_mode mem_mode;
605 int regno = REGNO (x);
607 if (regno < FIRST_PSEUDO_REGISTER)
610 x = eliminate_regs (x, mem_mode, usage);
614 replace_pseudos_in_call_usage (loc, mem_mode, usage);
618 if (reg_equiv_constant[regno])
619 *loc = reg_equiv_constant[regno];
620 else if (reg_equiv_mem[regno])
621 *loc = reg_equiv_mem[regno];
622 else if (reg_equiv_address[regno])
623 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
624 else if (GET_CODE (regno_reg_rtx[regno]) != REG
625 || REGNO (regno_reg_rtx[regno]) != regno)
626 *loc = regno_reg_rtx[regno];
632 else if (code == MEM)
634 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
638 /* Process each of our operands recursively. */
639 fmt = GET_RTX_FORMAT (code);
640 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
642 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
643 else if (*fmt == 'E')
644 for (j = 0; j < XVECLEN (x, i); j++)
645 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
649 /* Global variables used by reload and its subroutines. */
651 /* Set during calculate_needs if an insn needs register elimination. */
652 static int something_needs_elimination;
653 /* Set during calculate_needs if an insn needs an operand changed. */
654 int something_needs_operands_changed;
656 /* Nonzero means we couldn't get enough spill regs. */
659 /* Main entry point for the reload pass.
661 FIRST is the first insn of the function being compiled.
663 GLOBAL nonzero means we were called from global_alloc
664 and should attempt to reallocate any pseudoregs that we
665 displace from hard regs we will use for reloads.
666 If GLOBAL is zero, we do not have enough information to do that,
667 so any pseudo reg that is spilled must go to the stack.
669 Return value is nonzero if reload failed
670 and we must not do any more for this function. */
673 reload (first, global)
679 register struct elim_table *ep;
681 /* The two pointers used to track the true location of the memory used
682 for label offsets. */
683 char *real_known_ptr = NULL_PTR;
684 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
686 /* Make sure even insns with volatile mem refs are recognizable. */
691 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
693 /* Make sure that the last insn in the chain
694 is not something that needs reloading. */
695 emit_note (NULL_PTR, NOTE_INSN_DELETED);
697 /* Enable find_equiv_reg to distinguish insns made by reload. */
698 reload_first_uid = get_max_uid ();
700 #ifdef SECONDARY_MEMORY_NEEDED
701 /* Initialize the secondary memory table. */
702 clear_secondary_mem ();
705 /* We don't have a stack slot for any spill reg yet. */
706 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
707 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
709 /* Initialize the save area information for caller-save, in case some
713 /* Compute which hard registers are now in use
714 as homes for pseudo registers.
715 This is done here rather than (eg) in global_alloc
716 because this point is reached even if not optimizing. */
717 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
720 /* A function that receives a nonlocal goto must save all call-saved
722 if (current_function_has_nonlocal_label)
723 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
724 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
725 regs_ever_live[i] = 1;
727 /* Find all the pseudo registers that didn't get hard regs
728 but do have known equivalent constants or memory slots.
729 These include parameters (known equivalent to parameter slots)
730 and cse'd or loop-moved constant memory addresses.
732 Record constant equivalents in reg_equiv_constant
733 so they will be substituted by find_reloads.
734 Record memory equivalents in reg_mem_equiv so they can
735 be substituted eventually by altering the REG-rtx's. */
737 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
741 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
742 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
743 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
744 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
745 pseudo_forbidden_regs
746 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
748 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
750 CLEAR_HARD_REG_SET (bad_spill_regs_global);
752 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
753 Also find all paradoxical subregs and find largest such for each pseudo.
754 On machines with small register classes, record hard registers that
755 are used for user variables. These can never be used for spills.
756 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
757 caller-saved registers must be marked live. */
759 num_eliminable_invariants = 0;
760 for (insn = first; insn; insn = NEXT_INSN (insn))
762 rtx set = single_set (insn);
764 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
765 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
767 if (! call_used_regs[i])
768 regs_ever_live[i] = 1;
770 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
772 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
774 #ifdef LEGITIMATE_PIC_OPERAND_P
775 && (! function_invariant_p (XEXP (note, 0))
777 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
781 rtx x = XEXP (note, 0);
782 i = REGNO (SET_DEST (set));
783 if (i > LAST_VIRTUAL_REGISTER)
785 if (GET_CODE (x) == MEM)
787 /* If the operand is a PLUS, the MEM may be shared,
788 so make sure we have an unshared copy here. */
789 if (GET_CODE (XEXP (x, 0)) == PLUS)
792 reg_equiv_memory_loc[i] = x;
794 else if (function_invariant_p (x))
796 if (GET_CODE (x) == PLUS)
798 /* This is PLUS of frame pointer and a constant,
799 and might be shared. Unshare it. */
800 reg_equiv_constant[i] = copy_rtx (x);
801 num_eliminable_invariants++;
803 else if (x == frame_pointer_rtx
804 || x == arg_pointer_rtx)
806 reg_equiv_constant[i] = x;
807 num_eliminable_invariants++;
809 else if (LEGITIMATE_CONSTANT_P (x))
810 reg_equiv_constant[i] = x;
812 reg_equiv_memory_loc[i]
813 = force_const_mem (GET_MODE (SET_DEST (set)), x);
818 /* If this register is being made equivalent to a MEM
819 and the MEM is not SET_SRC, the equivalencing insn
820 is one with the MEM as a SET_DEST and it occurs later.
821 So don't mark this insn now. */
822 if (GET_CODE (x) != MEM
823 || rtx_equal_p (SET_SRC (set), x))
825 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
830 /* If this insn is setting a MEM from a register equivalent to it,
831 this is the equivalencing insn. */
832 else if (set && GET_CODE (SET_DEST (set)) == MEM
833 && GET_CODE (SET_SRC (set)) == REG
834 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
835 && rtx_equal_p (SET_DEST (set),
836 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
837 reg_equiv_init[REGNO (SET_SRC (set))]
838 = gen_rtx_INSN_LIST (VOIDmode, insn,
839 reg_equiv_init[REGNO (SET_SRC (set))]);
842 scan_paradoxical_subregs (PATTERN (insn));
847 num_labels = max_label_num () - get_first_label_num ();
849 /* Allocate the tables used to store offset information at labels. */
850 /* We used to use alloca here, but the size of what it would try to
851 allocate would occasionally cause it to exceed the stack limit and
852 cause a core dump. */
853 real_known_ptr = xmalloc (num_labels);
855 = (int (*)[NUM_ELIMINABLE_REGS])
856 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
858 offsets_known_at = real_known_ptr - get_first_label_num ();
860 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
862 /* Alter each pseudo-reg rtx to contain its hard reg number.
863 Assign stack slots to the pseudos that lack hard regs or equivalents.
864 Do not touch virtual registers. */
866 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
869 /* If we have some registers we think can be eliminated, scan all insns to
870 see if there is an insn that sets one of these registers to something
871 other than itself plus a constant. If so, the register cannot be
872 eliminated. Doing this scan here eliminates an extra pass through the
873 main reload loop in the most common case where register elimination
875 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
876 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
877 || GET_CODE (insn) == CALL_INSN)
878 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
880 maybe_fix_stack_asms ();
882 insns_need_reload = 0;
883 something_needs_elimination = 0;
885 /* Initialize to -1, which means take the first spill register. */
888 /* Spill any hard regs that we know we can't eliminate. */
889 CLEAR_HARD_REG_SET (used_spill_regs);
890 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
891 if (! ep->can_eliminate)
892 spill_hard_reg (ep->from, 1);
894 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
895 if (frame_pointer_needed)
896 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
898 finish_spills (global);
900 /* From now on, we may need to generate moves differently. We may also
901 allow modifications of insns which cause them to not be recognized.
902 Any such modifications will be cleaned up during reload itself. */
903 reload_in_progress = 1;
905 /* This loop scans the entire function each go-round
906 and repeats until one repetition spills no additional hard regs. */
909 int something_changed;
912 HOST_WIDE_INT starting_frame_size;
914 /* Round size of stack frame to stack_alignment_needed. This must be done
915 here because the stack size may be a part of the offset computation
916 for register elimination, and there might have been new stack slots
917 created in the last iteration of this loop. */
918 if (cfun->stack_alignment_needed)
919 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
921 starting_frame_size = get_frame_size ();
923 set_initial_elim_offsets ();
924 set_initial_label_offsets ();
926 /* For each pseudo register that has an equivalent location defined,
927 try to eliminate any eliminable registers (such as the frame pointer)
928 assuming initial offsets for the replacement register, which
931 If the resulting location is directly addressable, substitute
932 the MEM we just got directly for the old REG.
934 If it is not addressable but is a constant or the sum of a hard reg
935 and constant, it is probably not addressable because the constant is
936 out of range, in that case record the address; we will generate
937 hairy code to compute the address in a register each time it is
938 needed. Similarly if it is a hard register, but one that is not
939 valid as an address register.
941 If the location is not addressable, but does not have one of the
942 above forms, assign a stack slot. We have to do this to avoid the
943 potential of producing lots of reloads if, e.g., a location involves
944 a pseudo that didn't get a hard register and has an equivalent memory
945 location that also involves a pseudo that didn't get a hard register.
947 Perhaps at some point we will improve reload_when_needed handling
948 so this problem goes away. But that's very hairy. */
950 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
951 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
953 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
955 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
957 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
958 else if (CONSTANT_P (XEXP (x, 0))
959 || (GET_CODE (XEXP (x, 0)) == REG
960 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
961 || (GET_CODE (XEXP (x, 0)) == PLUS
962 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
963 && (REGNO (XEXP (XEXP (x, 0), 0))
964 < FIRST_PSEUDO_REGISTER)
965 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
966 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
969 /* Make a new stack slot. Then indicate that something
970 changed so we go back and recompute offsets for
971 eliminable registers because the allocation of memory
972 below might change some offset. reg_equiv_{mem,address}
973 will be set up for this pseudo on the next pass around
975 reg_equiv_memory_loc[i] = 0;
976 reg_equiv_init[i] = 0;
981 if (caller_save_needed)
984 /* If we allocated another stack slot, redo elimination bookkeeping. */
985 if (starting_frame_size != get_frame_size ())
988 if (caller_save_needed)
990 save_call_clobbered_regs ();
991 /* That might have allocated new insn_chain structures. */
992 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
995 calculate_needs_all_insns (global);
997 CLEAR_REG_SET (&spilled_pseudos);
1000 something_changed = 0;
1002 /* If we allocated any new memory locations, make another pass
1003 since it might have changed elimination offsets. */
1004 if (starting_frame_size != get_frame_size ())
1005 something_changed = 1;
1008 HARD_REG_SET to_spill;
1009 CLEAR_HARD_REG_SET (to_spill);
1010 update_eliminables (&to_spill);
1011 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1012 if (TEST_HARD_REG_BIT (to_spill, i))
1014 spill_hard_reg (i, 1);
1017 /* Regardless of the state of spills, if we previously had
1018 a register that we thought we could eliminate, but no can
1019 not eliminate, we must run another pass.
1021 Consider pseudos which have an entry in reg_equiv_* which
1022 reference an eliminable register. We must make another pass
1023 to update reg_equiv_* so that we do not substitute in the
1024 old value from when we thought the elimination could be
1026 something_changed = 1;
1030 select_reload_regs ();
1034 if (insns_need_reload != 0 || did_spill)
1035 something_changed |= finish_spills (global);
1037 if (! something_changed)
1040 if (caller_save_needed)
1041 delete_caller_save_insns ();
1043 obstack_free (&reload_obstack, reload_firstobj);
1046 /* If global-alloc was run, notify it of any register eliminations we have
1049 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1050 if (ep->can_eliminate)
1051 mark_elimination (ep->from, ep->to);
1053 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1054 If that insn didn't set the register (i.e., it copied the register to
1055 memory), just delete that insn instead of the equivalencing insn plus
1056 anything now dead. If we call delete_dead_insn on that insn, we may
1057 delete the insn that actually sets the register if the register dies
1058 there and that is incorrect. */
1060 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1062 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1065 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1067 rtx equiv_insn = XEXP (list, 0);
1068 if (GET_CODE (equiv_insn) == NOTE)
1070 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1071 delete_dead_insn (equiv_insn);
1074 PUT_CODE (equiv_insn, NOTE);
1075 NOTE_SOURCE_FILE (equiv_insn) = 0;
1076 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1082 /* Use the reload registers where necessary
1083 by generating move instructions to move the must-be-register
1084 values into or out of the reload registers. */
1086 if (insns_need_reload != 0 || something_needs_elimination
1087 || something_needs_operands_changed)
1089 HOST_WIDE_INT old_frame_size = get_frame_size ();
1091 reload_as_needed (global);
1093 if (old_frame_size != get_frame_size ())
1097 verify_initial_elim_offsets ();
1100 /* If we were able to eliminate the frame pointer, show that it is no
1101 longer live at the start of any basic block. If it ls live by
1102 virtue of being in a pseudo, that pseudo will be marked live
1103 and hence the frame pointer will be known to be live via that
1106 if (! frame_pointer_needed)
1107 for (i = 0; i < n_basic_blocks; i++)
1108 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1109 HARD_FRAME_POINTER_REGNUM);
1111 /* Come here (with failure set nonzero) if we can't get enough spill regs
1112 and we decide not to abort about it. */
1115 CLEAR_REG_SET (&spilled_pseudos);
1116 reload_in_progress = 0;
1118 /* Now eliminate all pseudo regs by modifying them into
1119 their equivalent memory references.
1120 The REG-rtx's for the pseudos are modified in place,
1121 so all insns that used to refer to them now refer to memory.
1123 For a reg that has a reg_equiv_address, all those insns
1124 were changed by reloading so that no insns refer to it any longer;
1125 but the DECL_RTL of a variable decl may refer to it,
1126 and if so this causes the debugging info to mention the variable. */
1128 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1133 int is_readonly = 0;
1135 if (reg_equiv_memory_loc[i])
1137 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1138 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1139 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1142 if (reg_equiv_mem[i])
1143 addr = XEXP (reg_equiv_mem[i], 0);
1145 if (reg_equiv_address[i])
1146 addr = reg_equiv_address[i];
1150 if (reg_renumber[i] < 0)
1152 rtx reg = regno_reg_rtx[i];
1153 PUT_CODE (reg, MEM);
1154 XEXP (reg, 0) = addr;
1155 REG_USERVAR_P (reg) = 0;
1156 RTX_UNCHANGING_P (reg) = is_readonly;
1157 MEM_IN_STRUCT_P (reg) = in_struct;
1158 MEM_SCALAR_P (reg) = is_scalar;
1159 /* We have no alias information about this newly created
1161 MEM_ALIAS_SET (reg) = 0;
1163 else if (reg_equiv_mem[i])
1164 XEXP (reg_equiv_mem[i], 0) = addr;
1168 /* We must set reload_completed now since the cleanup_subreg_operands call
1169 below will re-recognize each insn and reload may have generated insns
1170 which are only valid during and after reload. */
1171 reload_completed = 1;
1173 /* Make a pass over all the insns and delete all USEs which we inserted
1174 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1175 notes. Delete all CLOBBER insns that don't refer to the return value
1176 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1177 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1178 and regenerate REG_INC notes that may have been moved around. */
1180 for (insn = first; insn; insn = NEXT_INSN (insn))
1185 if (GET_CODE (insn) == CALL_INSN)
1186 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1188 CALL_INSN_FUNCTION_USAGE (insn));
1190 if ((GET_CODE (PATTERN (insn)) == USE
1191 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1192 || (GET_CODE (PATTERN (insn)) == CLOBBER
1193 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1196 PUT_CODE (insn, NOTE);
1197 NOTE_SOURCE_FILE (insn) = 0;
1198 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning ("frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning ("try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 reg_equiv_constant = 0;
1249 if (reg_equiv_memory_loc)
1250 free (reg_equiv_memory_loc);
1251 reg_equiv_memory_loc = 0;
1254 free (real_known_ptr);
1258 free (reg_equiv_mem);
1259 free (reg_equiv_init);
1260 free (reg_equiv_address);
1261 free (reg_max_ref_width);
1262 free (reg_old_renumber);
1263 free (pseudo_previous_regs);
1264 free (pseudo_forbidden_regs);
1266 CLEAR_HARD_REG_SET (used_spill_regs);
1267 for (i = 0; i < n_spills; i++)
1268 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1270 /* Free all the insn_chain structures at once. */
1271 obstack_free (&reload_obstack, reload_startobj);
1272 unused_insn_chains = 0;
1277 /* Yet another special case. Unfortunately, reg-stack forces people to
1278 write incorrect clobbers in asm statements. These clobbers must not
1279 cause the register to appear in bad_spill_regs, otherwise we'll call
1280 fatal_insn later. We clear the corresponding regnos in the live
1281 register sets to avoid this.
1282 The whole thing is rather sick, I'm afraid. */
1285 maybe_fix_stack_asms ()
1288 const char *constraints[MAX_RECOG_OPERANDS];
1289 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1290 struct insn_chain *chain;
1292 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1295 HARD_REG_SET clobbered, allowed;
1298 if (! INSN_P (chain->insn)
1299 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1301 pat = PATTERN (chain->insn);
1302 if (GET_CODE (pat) != PARALLEL)
1305 CLEAR_HARD_REG_SET (clobbered);
1306 CLEAR_HARD_REG_SET (allowed);
1308 /* First, make a mask of all stack regs that are clobbered. */
1309 for (i = 0; i < XVECLEN (pat, 0); i++)
1311 rtx t = XVECEXP (pat, 0, i);
1312 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1313 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1316 /* Get the operand values and constraints out of the insn. */
1317 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1318 constraints, operand_mode);
1320 /* For every operand, see what registers are allowed. */
1321 for (i = 0; i < noperands; i++)
1323 const char *p = constraints[i];
1324 /* For every alternative, we compute the class of registers allowed
1325 for reloading in CLS, and merge its contents into the reg set
1327 int cls = (int) NO_REGS;
1333 if (c == '\0' || c == ',' || c == '#')
1335 /* End of one alternative - mark the regs in the current
1336 class, and reset the class. */
1337 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1342 } while (c != '\0' && c != ',');
1350 case '=': case '+': case '*': case '%': case '?': case '!':
1351 case '0': case '1': case '2': case '3': case '4': case 'm':
1352 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1353 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1354 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1359 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1364 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1368 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1373 /* Those of the registers which are clobbered, but allowed by the
1374 constraints, must be usable as reload registers. So clear them
1375 out of the life information. */
1376 AND_HARD_REG_SET (allowed, clobbered);
1377 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1378 if (TEST_HARD_REG_BIT (allowed, i))
1380 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1381 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1388 /* Copy the global variables n_reloads and rld into the corresponding elts
1391 copy_reloads (chain)
1392 struct insn_chain *chain;
1394 chain->n_reloads = n_reloads;
1396 = (struct reload *) obstack_alloc (&reload_obstack,
1397 n_reloads * sizeof (struct reload));
1398 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1399 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1402 /* Walk the chain of insns, and determine for each whether it needs reloads
1403 and/or eliminations. Build the corresponding insns_need_reload list, and
1404 set something_needs_elimination as appropriate. */
1406 calculate_needs_all_insns (global)
1409 struct insn_chain **pprev_reload = &insns_need_reload;
1410 struct insn_chain *chain, *next = 0;
1412 something_needs_elimination = 0;
1414 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1415 for (chain = reload_insn_chain; chain != 0; chain = next)
1417 rtx insn = chain->insn;
1421 /* Clear out the shortcuts. */
1422 chain->n_reloads = 0;
1423 chain->need_elim = 0;
1424 chain->need_reload = 0;
1425 chain->need_operand_change = 0;
1427 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1428 include REG_LABEL), we need to see what effects this has on the
1429 known offsets at labels. */
1431 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1432 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1433 set_label_offsets (insn, insn, 0);
1437 rtx old_body = PATTERN (insn);
1438 int old_code = INSN_CODE (insn);
1439 rtx old_notes = REG_NOTES (insn);
1440 int did_elimination = 0;
1441 int operands_changed = 0;
1442 rtx set = single_set (insn);
1444 /* Skip insns that only set an equivalence. */
1445 if (set && GET_CODE (SET_DEST (set)) == REG
1446 && reg_renumber[REGNO (SET_DEST (set))] < 0
1447 && reg_equiv_constant[REGNO (SET_DEST (set))])
1450 /* If needed, eliminate any eliminable registers. */
1451 if (num_eliminable || num_eliminable_invariants)
1452 did_elimination = eliminate_regs_in_insn (insn, 0);
1454 /* Analyze the instruction. */
1455 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1456 global, spill_reg_order);
1458 /* If a no-op set needs more than one reload, this is likely
1459 to be something that needs input address reloads. We
1460 can't get rid of this cleanly later, and it is of no use
1461 anyway, so discard it now.
1462 We only do this when expensive_optimizations is enabled,
1463 since this complements reload inheritance / output
1464 reload deletion, and it can make debugging harder. */
1465 if (flag_expensive_optimizations && n_reloads > 1)
1467 rtx set = single_set (insn);
1469 && SET_SRC (set) == SET_DEST (set)
1470 && GET_CODE (SET_SRC (set)) == REG
1471 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1473 PUT_CODE (insn, NOTE);
1474 NOTE_SOURCE_FILE (insn) = 0;
1475 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1476 /* Delete it from the reload chain */
1478 chain->prev->next = next;
1480 reload_insn_chain = next;
1482 next->prev = chain->prev;
1483 chain->next = unused_insn_chains;
1484 unused_insn_chains = chain;
1489 update_eliminable_offsets ();
1491 /* Remember for later shortcuts which insns had any reloads or
1492 register eliminations. */
1493 chain->need_elim = did_elimination;
1494 chain->need_reload = n_reloads > 0;
1495 chain->need_operand_change = operands_changed;
1497 /* Discard any register replacements done. */
1498 if (did_elimination)
1500 obstack_free (&reload_obstack, reload_insn_firstobj);
1501 PATTERN (insn) = old_body;
1502 INSN_CODE (insn) = old_code;
1503 REG_NOTES (insn) = old_notes;
1504 something_needs_elimination = 1;
1507 something_needs_operands_changed |= operands_changed;
1511 copy_reloads (chain);
1512 *pprev_reload = chain;
1513 pprev_reload = &chain->next_need_reload;
1520 /* Comparison function for qsort to decide which of two reloads
1521 should be handled first. *P1 and *P2 are the reload numbers. */
1524 reload_reg_class_lower (r1p, r2p)
1528 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1531 /* Consider required reloads before optional ones. */
1532 t = rld[r1].optional - rld[r2].optional;
1536 /* Count all solitary classes before non-solitary ones. */
1537 t = ((reg_class_size[(int) rld[r2].class] == 1)
1538 - (reg_class_size[(int) rld[r1].class] == 1));
1542 /* Aside from solitaires, consider all multi-reg groups first. */
1543 t = rld[r2].nregs - rld[r1].nregs;
1547 /* Consider reloads in order of increasing reg-class number. */
1548 t = (int) rld[r1].class - (int) rld[r2].class;
1552 /* If reloads are equally urgent, sort by reload number,
1553 so that the results of qsort leave nothing to chance. */
1557 /* The cost of spilling each hard reg. */
1558 static int spill_cost[FIRST_PSEUDO_REGISTER];
1560 /* When spilling multiple hard registers, we use SPILL_COST for the first
1561 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1562 only the first hard reg for a multi-reg pseudo. */
1563 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1565 /* Update the spill cost arrays, considering that pseudo REG is live. */
1571 int n_refs = REG_N_REFS (reg);
1572 int r = reg_renumber[reg];
1575 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1576 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1579 SET_REGNO_REG_SET (&pseudos_counted, reg);
1584 spill_add_cost[r] += n_refs;
1586 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1588 spill_cost[r + nregs] += n_refs;
1591 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1592 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1595 order_regs_for_reload (chain)
1596 struct insn_chain *chain;
1599 HARD_REG_SET used_by_pseudos;
1600 HARD_REG_SET used_by_pseudos2;
1602 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1604 memset (spill_cost, 0, sizeof spill_cost);
1605 memset (spill_add_cost, 0, sizeof spill_add_cost);
1607 /* Count number of uses of each hard reg by pseudo regs allocated to it
1608 and then order them by decreasing use. First exclude hard registers
1609 that are live in or across this insn. */
1611 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1612 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1613 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1614 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1616 /* Now find out which pseudos are allocated to it, and update
1618 CLEAR_REG_SET (&pseudos_counted);
1620 EXECUTE_IF_SET_IN_REG_SET
1621 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1625 EXECUTE_IF_SET_IN_REG_SET
1626 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1630 CLEAR_REG_SET (&pseudos_counted);
1633 /* Vector of reload-numbers showing the order in which the reloads should
1635 static short reload_order[MAX_RELOADS];
1637 /* This is used to keep track of the spill regs used in one insn. */
1638 static HARD_REG_SET used_spill_regs_local;
1640 /* We decided to spill hard register SPILLED, which has a size of
1641 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1642 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1643 update SPILL_COST/SPILL_ADD_COST. */
1646 count_spilled_pseudo (spilled, spilled_nregs, reg)
1647 int spilled, spilled_nregs, reg;
1649 int r = reg_renumber[reg];
1650 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1652 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1653 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1656 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1658 spill_add_cost[r] -= REG_N_REFS (reg);
1660 spill_cost[r + nregs] -= REG_N_REFS (reg);
1663 /* Find reload register to use for reload number ORDER. */
1666 find_reg (chain, order)
1667 struct insn_chain *chain;
1670 int rnum = reload_order[order];
1671 struct reload *rl = rld + rnum;
1672 int best_cost = INT_MAX;
1676 HARD_REG_SET not_usable;
1677 HARD_REG_SET used_by_other_reload;
1679 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1680 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1681 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1683 CLEAR_HARD_REG_SET (used_by_other_reload);
1684 for (k = 0; k < order; k++)
1686 int other = reload_order[k];
1688 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1689 for (j = 0; j < rld[other].nregs; j++)
1690 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1693 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1695 unsigned int regno = i;
1697 if (! TEST_HARD_REG_BIT (not_usable, regno)
1698 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1699 && HARD_REGNO_MODE_OK (regno, rl->mode))
1701 int this_cost = spill_cost[regno];
1703 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1705 for (j = 1; j < this_nregs; j++)
1707 this_cost += spill_add_cost[regno + j];
1708 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1709 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1714 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1716 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1718 if (this_cost < best_cost
1719 /* Among registers with equal cost, prefer caller-saved ones, or
1720 use REG_ALLOC_ORDER if it is defined. */
1721 || (this_cost == best_cost
1722 #ifdef REG_ALLOC_ORDER
1723 && (inv_reg_alloc_order[regno]
1724 < inv_reg_alloc_order[best_reg])
1726 && call_used_regs[regno]
1727 && ! call_used_regs[best_reg]
1732 best_cost = this_cost;
1740 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1742 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1743 rl->regno = best_reg;
1745 EXECUTE_IF_SET_IN_REG_SET
1746 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1748 count_spilled_pseudo (best_reg, rl->nregs, j);
1751 EXECUTE_IF_SET_IN_REG_SET
1752 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1754 count_spilled_pseudo (best_reg, rl->nregs, j);
1757 for (i = 0; i < rl->nregs; i++)
1759 if (spill_cost[best_reg + i] != 0
1760 || spill_add_cost[best_reg + i] != 0)
1762 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1767 /* Find more reload regs to satisfy the remaining need of an insn, which
1769 Do it by ascending class number, since otherwise a reg
1770 might be spilled for a big class and might fail to count
1771 for a smaller class even though it belongs to that class. */
1774 find_reload_regs (chain)
1775 struct insn_chain *chain;
1779 /* In order to be certain of getting the registers we need,
1780 we must sort the reloads into order of increasing register class.
1781 Then our grabbing of reload registers will parallel the process
1782 that provided the reload registers. */
1783 for (i = 0; i < chain->n_reloads; i++)
1785 /* Show whether this reload already has a hard reg. */
1786 if (chain->rld[i].reg_rtx)
1788 int regno = REGNO (chain->rld[i].reg_rtx);
1789 chain->rld[i].regno = regno;
1791 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1794 chain->rld[i].regno = -1;
1795 reload_order[i] = i;
1798 n_reloads = chain->n_reloads;
1799 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1801 CLEAR_HARD_REG_SET (used_spill_regs_local);
1804 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1806 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1808 /* Compute the order of preference for hard registers to spill. */
1810 order_regs_for_reload (chain);
1812 for (i = 0; i < n_reloads; i++)
1814 int r = reload_order[i];
1816 /* Ignore reloads that got marked inoperative. */
1817 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1818 && ! rld[r].optional
1819 && rld[r].regno == -1)
1820 if (! find_reg (chain, i))
1822 spill_failure (chain->insn, rld[r].class);
1828 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1829 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1831 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1835 select_reload_regs ()
1837 struct insn_chain *chain;
1839 /* Try to satisfy the needs for each insn. */
1840 for (chain = insns_need_reload; chain != 0;
1841 chain = chain->next_need_reload)
1842 find_reload_regs (chain);
1845 /* Delete all insns that were inserted by emit_caller_save_insns during
1848 delete_caller_save_insns ()
1850 struct insn_chain *c = reload_insn_chain;
1854 while (c != 0 && c->is_caller_save_insn)
1856 struct insn_chain *next = c->next;
1859 if (insn == BLOCK_HEAD (c->block))
1860 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1861 if (insn == BLOCK_END (c->block))
1862 BLOCK_END (c->block) = PREV_INSN (insn);
1863 if (c == reload_insn_chain)
1864 reload_insn_chain = next;
1866 if (NEXT_INSN (insn) != 0)
1867 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1868 if (PREV_INSN (insn) != 0)
1869 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1872 next->prev = c->prev;
1874 c->prev->next = next;
1875 c->next = unused_insn_chains;
1876 unused_insn_chains = c;
1884 /* Handle the failure to find a register to spill.
1885 INSN should be one of the insns which needed this particular spill reg. */
1888 spill_failure (insn, class)
1890 enum reg_class class;
1892 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1893 if (asm_noperands (PATTERN (insn)) >= 0)
1894 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1895 reg_class_names[class]);
1898 error ("Unable to find a register to spill in class `%s'.",
1899 reg_class_names[class]);
1900 fatal_insn ("This is the insn:", insn);
1904 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1905 data that is dead in INSN. */
1908 delete_dead_insn (insn)
1911 rtx prev = prev_real_insn (insn);
1914 /* If the previous insn sets a register that dies in our insn, delete it
1916 if (prev && GET_CODE (PATTERN (prev)) == SET
1917 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1918 && reg_mentioned_p (prev_dest, PATTERN (insn))
1919 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1920 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1921 delete_dead_insn (prev);
1923 PUT_CODE (insn, NOTE);
1924 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1925 NOTE_SOURCE_FILE (insn) = 0;
1928 /* Modify the home of pseudo-reg I.
1929 The new home is present in reg_renumber[I].
1931 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1932 or it may be -1, meaning there is none or it is not relevant.
1933 This is used so that all pseudos spilled from a given hard reg
1934 can share one stack slot. */
1937 alter_reg (i, from_reg)
1941 /* When outputting an inline function, this can happen
1942 for a reg that isn't actually used. */
1943 if (regno_reg_rtx[i] == 0)
1946 /* If the reg got changed to a MEM at rtl-generation time,
1948 if (GET_CODE (regno_reg_rtx[i]) != REG)
1951 /* Modify the reg-rtx to contain the new hard reg
1952 number or else to contain its pseudo reg number. */
1953 REGNO (regno_reg_rtx[i])
1954 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1956 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1957 allocate a stack slot for it. */
1959 if (reg_renumber[i] < 0
1960 && REG_N_REFS (i) > 0
1961 && reg_equiv_constant[i] == 0
1962 && reg_equiv_memory_loc[i] == 0)
1965 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1966 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1969 /* Each pseudo reg has an inherent size which comes from its own mode,
1970 and a total size which provides room for paradoxical subregs
1971 which refer to the pseudo reg in wider modes.
1973 We can use a slot already allocated if it provides both
1974 enough inherent space and enough total space.
1975 Otherwise, we allocate a new slot, making sure that it has no less
1976 inherent space, and no less total space, then the previous slot. */
1979 /* No known place to spill from => no slot to reuse. */
1980 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1981 inherent_size == total_size ? 0 : -1);
1982 if (BYTES_BIG_ENDIAN)
1983 /* Cancel the big-endian correction done in assign_stack_local.
1984 Get the address of the beginning of the slot.
1985 This is so we can do a big-endian correction unconditionally
1987 adjust = inherent_size - total_size;
1989 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1991 /* Nothing can alias this slot except this pseudo. */
1992 MEM_ALIAS_SET (x) = new_alias_set ();
1995 /* Reuse a stack slot if possible. */
1996 else if (spill_stack_slot[from_reg] != 0
1997 && spill_stack_slot_width[from_reg] >= total_size
1998 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2000 x = spill_stack_slot[from_reg];
2002 /* Allocate a bigger slot. */
2005 /* Compute maximum size needed, both for inherent size
2006 and for total size. */
2007 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2010 if (spill_stack_slot[from_reg])
2012 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2014 mode = GET_MODE (spill_stack_slot[from_reg]);
2015 if (spill_stack_slot_width[from_reg] > total_size)
2016 total_size = spill_stack_slot_width[from_reg];
2019 /* Make a slot with that size. */
2020 x = assign_stack_local (mode, total_size,
2021 inherent_size == total_size ? 0 : -1);
2024 /* All pseudos mapped to this slot can alias each other. */
2025 if (spill_stack_slot[from_reg])
2026 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2028 MEM_ALIAS_SET (x) = new_alias_set ();
2030 if (BYTES_BIG_ENDIAN)
2032 /* Cancel the big-endian correction done in assign_stack_local.
2033 Get the address of the beginning of the slot.
2034 This is so we can do a big-endian correction unconditionally
2036 adjust = GET_MODE_SIZE (mode) - total_size;
2038 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2041 plus_constant (XEXP (x, 0), adjust));
2044 spill_stack_slot[from_reg] = stack_slot;
2045 spill_stack_slot_width[from_reg] = total_size;
2048 /* On a big endian machine, the "address" of the slot
2049 is the address of the low part that fits its inherent mode. */
2050 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2051 adjust += (total_size - inherent_size);
2053 /* If we have any adjustment to make, or if the stack slot is the
2054 wrong mode, make a new stack slot. */
2055 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2057 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2058 plus_constant (XEXP (x, 0), adjust));
2060 MEM_COPY_ATTRIBUTES (new, x);
2064 /* Save the stack slot for later. */
2065 reg_equiv_memory_loc[i] = x;
2069 /* Mark the slots in regs_ever_live for the hard regs
2070 used by pseudo-reg number REGNO. */
2073 mark_home_live (regno)
2076 register int i, lim;
2078 i = reg_renumber[regno];
2081 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2083 regs_ever_live[i++] = 1;
2086 /* This function handles the tracking of elimination offsets around branches.
2088 X is a piece of RTL being scanned.
2090 INSN is the insn that it came from, if any.
2092 INITIAL_P is non-zero if we are to set the offset to be the initial
2093 offset and zero if we are setting the offset of the label to be the
2097 set_label_offsets (x, insn, initial_p)
2102 enum rtx_code code = GET_CODE (x);
2105 struct elim_table *p;
2110 if (LABEL_REF_NONLOCAL_P (x))
2115 /* ... fall through ... */
2118 /* If we know nothing about this label, set the desired offsets. Note
2119 that this sets the offset at a label to be the offset before a label
2120 if we don't know anything about the label. This is not correct for
2121 the label after a BARRIER, but is the best guess we can make. If
2122 we guessed wrong, we will suppress an elimination that might have
2123 been possible had we been able to guess correctly. */
2125 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2127 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2128 offsets_at[CODE_LABEL_NUMBER (x)][i]
2129 = (initial_p ? reg_eliminate[i].initial_offset
2130 : reg_eliminate[i].offset);
2131 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2134 /* Otherwise, if this is the definition of a label and it is
2135 preceded by a BARRIER, set our offsets to the known offset of
2139 && (tem = prev_nonnote_insn (insn)) != 0
2140 && GET_CODE (tem) == BARRIER)
2141 set_offsets_for_label (insn);
2143 /* If neither of the above cases is true, compare each offset
2144 with those previously recorded and suppress any eliminations
2145 where the offsets disagree. */
2147 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2148 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2149 != (initial_p ? reg_eliminate[i].initial_offset
2150 : reg_eliminate[i].offset))
2151 reg_eliminate[i].can_eliminate = 0;
2156 set_label_offsets (PATTERN (insn), insn, initial_p);
2158 /* ... fall through ... */
2162 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2163 and hence must have all eliminations at their initial offsets. */
2164 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2165 if (REG_NOTE_KIND (tem) == REG_LABEL)
2166 set_label_offsets (XEXP (tem, 0), insn, 1);
2172 /* Each of the labels in the parallel or address vector must be
2173 at their initial offsets. We want the first field for PARALLEL
2174 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2176 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2177 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2182 /* We only care about setting PC. If the source is not RETURN,
2183 IF_THEN_ELSE, or a label, disable any eliminations not at
2184 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2185 isn't one of those possibilities. For branches to a label,
2186 call ourselves recursively.
2188 Note that this can disable elimination unnecessarily when we have
2189 a non-local goto since it will look like a non-constant jump to
2190 someplace in the current function. This isn't a significant
2191 problem since such jumps will normally be when all elimination
2192 pairs are back to their initial offsets. */
2194 if (SET_DEST (x) != pc_rtx)
2197 switch (GET_CODE (SET_SRC (x)))
2204 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2208 tem = XEXP (SET_SRC (x), 1);
2209 if (GET_CODE (tem) == LABEL_REF)
2210 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2211 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2214 tem = XEXP (SET_SRC (x), 2);
2215 if (GET_CODE (tem) == LABEL_REF)
2216 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2217 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2225 /* If we reach here, all eliminations must be at their initial
2226 offset because we are doing a jump to a variable address. */
2227 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2228 if (p->offset != p->initial_offset)
2229 p->can_eliminate = 0;
2237 /* Scan X and replace any eliminable registers (such as fp) with a
2238 replacement (such as sp), plus an offset.
2240 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2241 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2242 MEM, we are allowed to replace a sum of a register and the constant zero
2243 with the register, which we cannot do outside a MEM. In addition, we need
2244 to record the fact that a register is referenced outside a MEM.
2246 If INSN is an insn, it is the insn containing X. If we replace a REG
2247 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2248 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2249 the REG is being modified.
2251 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2252 That's used when we eliminate in expressions stored in notes.
2253 This means, do not set ref_outside_mem even if the reference
2256 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2257 replacements done assuming all offsets are at their initial values. If
2258 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2259 encounter, return the actual location so that find_reloads will do
2260 the proper thing. */
2263 eliminate_regs (x, mem_mode, insn)
2265 enum machine_mode mem_mode;
2268 enum rtx_code code = GET_CODE (x);
2269 struct elim_table *ep;
2276 if (! current_function_decl)
2295 /* This is only for the benefit of the debugging backends, which call
2296 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2297 removed after CSE. */
2298 new = eliminate_regs (XEXP (x, 0), 0, insn);
2299 if (GET_CODE (new) == MEM)
2300 return XEXP (new, 0);
2306 /* First handle the case where we encounter a bare register that
2307 is eliminable. Replace it with a PLUS. */
2308 if (regno < FIRST_PSEUDO_REGISTER)
2310 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2312 if (ep->from_rtx == x && ep->can_eliminate)
2313 return plus_constant (ep->to_rtx, ep->previous_offset);
2316 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2317 && reg_equiv_constant[regno]
2318 && ! CONSTANT_P (reg_equiv_constant[regno]))
2319 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2323 /* You might think handling MINUS in a manner similar to PLUS is a
2324 good idea. It is not. It has been tried multiple times and every
2325 time the change has had to have been reverted.
2327 Other parts of reload know a PLUS is special (gen_reload for example)
2328 and require special code to handle code a reloaded PLUS operand.
2330 Also consider backends where the flags register is clobbered by a
2331 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2332 lea instruction comes to mind). If we try to reload a MINUS, we
2333 may kill the flags register that was holding a useful value.
2335 So, please before trying to handle MINUS, consider reload as a
2336 whole instead of this little section as well as the backend issues. */
2338 /* If this is the sum of an eliminable register and a constant, rework
2340 if (GET_CODE (XEXP (x, 0)) == REG
2341 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2342 && CONSTANT_P (XEXP (x, 1)))
2344 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2346 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2348 /* The only time we want to replace a PLUS with a REG (this
2349 occurs when the constant operand of the PLUS is the negative
2350 of the offset) is when we are inside a MEM. We won't want
2351 to do so at other times because that would change the
2352 structure of the insn in a way that reload can't handle.
2353 We special-case the commonest situation in
2354 eliminate_regs_in_insn, so just replace a PLUS with a
2355 PLUS here, unless inside a MEM. */
2356 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2357 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2360 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2361 plus_constant (XEXP (x, 1),
2362 ep->previous_offset));
2365 /* If the register is not eliminable, we are done since the other
2366 operand is a constant. */
2370 /* If this is part of an address, we want to bring any constant to the
2371 outermost PLUS. We will do this by doing register replacement in
2372 our operands and seeing if a constant shows up in one of them.
2374 Note that there is no risk of modifying the structure of the insn,
2375 since we only get called for its operands, thus we are either
2376 modifying the address inside a MEM, or something like an address
2377 operand of a load-address insn. */
2380 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2381 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2383 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2385 /* If one side is a PLUS and the other side is a pseudo that
2386 didn't get a hard register but has a reg_equiv_constant,
2387 we must replace the constant here since it may no longer
2388 be in the position of any operand. */
2389 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2390 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2391 && reg_renumber[REGNO (new1)] < 0
2392 && reg_equiv_constant != 0
2393 && reg_equiv_constant[REGNO (new1)] != 0)
2394 new1 = reg_equiv_constant[REGNO (new1)];
2395 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2396 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2397 && reg_renumber[REGNO (new0)] < 0
2398 && reg_equiv_constant[REGNO (new0)] != 0)
2399 new0 = reg_equiv_constant[REGNO (new0)];
2401 new = form_sum (new0, new1);
2403 /* As above, if we are not inside a MEM we do not want to
2404 turn a PLUS into something else. We might try to do so here
2405 for an addition of 0 if we aren't optimizing. */
2406 if (! mem_mode && GET_CODE (new) != PLUS)
2407 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2415 /* If this is the product of an eliminable register and a
2416 constant, apply the distribute law and move the constant out
2417 so that we have (plus (mult ..) ..). This is needed in order
2418 to keep load-address insns valid. This case is pathological.
2419 We ignore the possibility of overflow here. */
2420 if (GET_CODE (XEXP (x, 0)) == REG
2421 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2422 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2423 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2425 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2428 /* Refs inside notes don't count for this purpose. */
2429 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2430 || GET_CODE (insn) == INSN_LIST)))
2431 ep->ref_outside_mem = 1;
2434 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2435 ep->previous_offset * INTVAL (XEXP (x, 1)));
2438 /* ... fall through ... */
2442 /* See comments before PLUS about handling MINUS. */
2444 case DIV: case UDIV:
2445 case MOD: case UMOD:
2446 case AND: case IOR: case XOR:
2447 case ROTATERT: case ROTATE:
2448 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2450 case GE: case GT: case GEU: case GTU:
2451 case LE: case LT: case LEU: case LTU:
2453 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2455 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2457 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2458 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2463 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2466 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2467 if (new != XEXP (x, 0))
2469 /* If this is a REG_DEAD note, it is not valid anymore.
2470 Using the eliminated version could result in creating a
2471 REG_DEAD note for the stack or frame pointer. */
2472 if (GET_MODE (x) == REG_DEAD)
2474 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2477 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2481 /* ... fall through ... */
2484 /* Now do eliminations in the rest of the chain. If this was
2485 an EXPR_LIST, this might result in allocating more memory than is
2486 strictly needed, but it simplifies the code. */
2489 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2490 if (new != XEXP (x, 1))
2491 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2499 case STRICT_LOW_PART:
2501 case SIGN_EXTEND: case ZERO_EXTEND:
2502 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2503 case FLOAT: case FIX:
2504 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2508 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2509 if (new != XEXP (x, 0))
2510 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2514 /* Similar to above processing, but preserve SUBREG_WORD.
2515 Convert (subreg (mem)) to (mem) if not paradoxical.
2516 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2517 pseudo didn't get a hard reg, we must replace this with the
2518 eliminated version of the memory location because push_reloads
2519 may do the replacement in certain circumstances. */
2520 if (GET_CODE (SUBREG_REG (x)) == REG
2521 && (GET_MODE_SIZE (GET_MODE (x))
2522 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2523 && reg_equiv_memory_loc != 0
2524 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2526 new = SUBREG_REG (x);
2529 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2531 if (new != XEXP (x, 0))
2533 int x_size = GET_MODE_SIZE (GET_MODE (x));
2534 int new_size = GET_MODE_SIZE (GET_MODE (new));
2536 if (GET_CODE (new) == MEM
2537 && ((x_size < new_size
2538 #ifdef WORD_REGISTER_OPERATIONS
2539 /* On these machines, combine can create rtl of the form
2540 (set (subreg:m1 (reg:m2 R) 0) ...)
2541 where m1 < m2, and expects something interesting to
2542 happen to the entire word. Moreover, it will use the
2543 (reg:m2 R) later, expecting all bits to be preserved.
2544 So if the number of words is the same, preserve the
2545 subreg so that push_reloads can see it. */
2546 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2549 || (x_size == new_size))
2552 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2553 enum machine_mode mode = GET_MODE (x);
2555 if (BYTES_BIG_ENDIAN)
2556 offset += (MIN (UNITS_PER_WORD,
2557 GET_MODE_SIZE (GET_MODE (new)))
2558 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2560 PUT_MODE (new, mode);
2561 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2565 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2571 /* This is only for the benefit of the debugging backends, which call
2572 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2573 removed after CSE. */
2574 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2575 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2577 /* Our only special processing is to pass the mode of the MEM to our
2578 recursive call and copy the flags. While we are here, handle this
2579 case more efficiently. */
2580 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2581 if (new != XEXP (x, 0))
2583 new = gen_rtx_MEM (GET_MODE (x), new);
2584 MEM_COPY_ATTRIBUTES (new, x);
2600 /* Process each of our operands recursively. If any have changed, make a
2602 fmt = GET_RTX_FORMAT (code);
2603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2607 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2608 if (new != XEXP (x, i) && ! copied)
2610 rtx new_x = rtx_alloc (code);
2612 (sizeof (*new_x) - sizeof (new_x->fld)
2613 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2619 else if (*fmt == 'E')
2622 for (j = 0; j < XVECLEN (x, i); j++)
2624 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2625 if (new != XVECEXP (x, i, j) && ! copied_vec)
2627 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2631 rtx new_x = rtx_alloc (code);
2633 (sizeof (*new_x) - sizeof (new_x->fld)
2634 + (sizeof (new_x->fld[0])
2635 * GET_RTX_LENGTH (code))));
2639 XVEC (x, i) = new_v;
2642 XVECEXP (x, i, j) = new;
2650 /* Scan rtx X for modifications of elimination target registers. Update
2651 the table of eliminables to reflect the changed state. MEM_MODE is
2652 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2655 elimination_effects (x, mem_mode)
2657 enum machine_mode mem_mode;
2660 enum rtx_code code = GET_CODE (x);
2661 struct elim_table *ep;
2687 /* First handle the case where we encounter a bare register that
2688 is eliminable. Replace it with a PLUS. */
2689 if (regno < FIRST_PSEUDO_REGISTER)
2691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2693 if (ep->from_rtx == x && ep->can_eliminate)
2696 ep->ref_outside_mem = 1;
2701 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2702 && reg_equiv_constant[regno]
2703 && ! CONSTANT_P (reg_equiv_constant[regno]))
2704 elimination_effects (reg_equiv_constant[regno], mem_mode);
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2714 if (ep->to_rtx == XEXP (x, 0))
2716 int size = GET_MODE_SIZE (mem_mode);
2718 /* If more bytes than MEM_MODE are pushed, account for them. */
2719 #ifdef PUSH_ROUNDING
2720 if (ep->to_rtx == stack_pointer_rtx)
2721 size = PUSH_ROUNDING (size);
2723 if (code == PRE_DEC || code == POST_DEC)
2725 else if (code == PRE_INC || code == POST_INC)
2727 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2728 && GET_CODE (XEXP (x, 1)) == PLUS
2729 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2730 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2731 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2734 /* These two aren't unary operators. */
2735 if (code == POST_MODIFY || code == PRE_MODIFY)
2738 /* Fall through to generic unary operation case. */
2739 case STRICT_LOW_PART:
2741 case SIGN_EXTEND: case ZERO_EXTEND:
2742 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2743 case FLOAT: case FIX:
2744 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2748 elimination_effects (XEXP (x, 0), mem_mode);
2752 if (GET_CODE (SUBREG_REG (x)) == REG
2753 && (GET_MODE_SIZE (GET_MODE (x))
2754 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2755 && reg_equiv_memory_loc != 0
2756 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2759 elimination_effects (SUBREG_REG (x), mem_mode);
2763 /* If using a register that is the source of an eliminate we still
2764 think can be performed, note it cannot be performed since we don't
2765 know how this register is used. */
2766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2767 if (ep->from_rtx == XEXP (x, 0))
2768 ep->can_eliminate = 0;
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 /* If clobbering a register that is the replacement register for an
2775 elimination we still think can be performed, note that it cannot
2776 be performed. Otherwise, we need not be concerned about it. */
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2778 if (ep->to_rtx == XEXP (x, 0))
2779 ep->can_eliminate = 0;
2781 elimination_effects (XEXP (x, 0), mem_mode);
2785 /* Check for setting a register that we know about. */
2786 if (GET_CODE (SET_DEST (x)) == REG)
2788 /* See if this is setting the replacement register for an
2791 If DEST is the hard frame pointer, we do nothing because we
2792 assume that all assignments to the frame pointer are for
2793 non-local gotos and are being done at a time when they are valid
2794 and do not disturb anything else. Some machines want to
2795 eliminate a fake argument pointer (or even a fake frame pointer)
2796 with either the real frame or the stack pointer. Assignments to
2797 the hard frame pointer must not prevent this elimination. */
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2801 if (ep->to_rtx == SET_DEST (x)
2802 && SET_DEST (x) != hard_frame_pointer_rtx)
2804 /* If it is being incremented, adjust the offset. Otherwise,
2805 this elimination can't be done. */
2806 rtx src = SET_SRC (x);
2808 if (GET_CODE (src) == PLUS
2809 && XEXP (src, 0) == SET_DEST (x)
2810 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2811 ep->offset -= INTVAL (XEXP (src, 1));
2813 ep->can_eliminate = 0;
2817 elimination_effects (SET_DEST (x), 0);
2818 elimination_effects (SET_SRC (x), 0);
2822 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2825 /* Our only special processing is to pass the mode of the MEM to our
2827 elimination_effects (XEXP (x, 0), GET_MODE (x));
2834 fmt = GET_RTX_FORMAT (code);
2835 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2838 elimination_effects (XEXP (x, i), mem_mode);
2839 else if (*fmt == 'E')
2840 for (j = 0; j < XVECLEN (x, i); j++)
2841 elimination_effects (XVECEXP (x, i, j), mem_mode);
2845 /* Descend through rtx X and verify that no references to eliminable registers
2846 remain. If any do remain, mark the involved register as not
2850 check_eliminable_occurrences (x)
2860 code = GET_CODE (x);
2862 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2864 struct elim_table *ep;
2866 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2867 if (ep->from_rtx == x && ep->can_eliminate)
2868 ep->can_eliminate = 0;
2872 fmt = GET_RTX_FORMAT (code);
2873 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2876 check_eliminable_occurrences (XEXP (x, i));
2877 else if (*fmt == 'E')
2880 for (j = 0; j < XVECLEN (x, i); j++)
2881 check_eliminable_occurrences (XVECEXP (x, i, j));
2886 /* Scan INSN and eliminate all eliminable registers in it.
2888 If REPLACE is nonzero, do the replacement destructively. Also
2889 delete the insn as dead it if it is setting an eliminable register.
2891 If REPLACE is zero, do all our allocations in reload_obstack.
2893 If no eliminations were done and this insn doesn't require any elimination
2894 processing (these are not identical conditions: it might be updating sp,
2895 but not referencing fp; this needs to be seen during reload_as_needed so
2896 that the offset between fp and sp can be taken into consideration), zero
2897 is returned. Otherwise, 1 is returned. */
2900 eliminate_regs_in_insn (insn, replace)
2904 int icode = recog_memoized (insn);
2905 rtx old_body = PATTERN (insn);
2906 int insn_is_asm = asm_noperands (old_body) >= 0;
2907 rtx old_set = single_set (insn);
2911 rtx substed_operand[MAX_RECOG_OPERANDS];
2912 rtx orig_operand[MAX_RECOG_OPERANDS];
2913 struct elim_table *ep;
2915 if (! insn_is_asm && icode < 0)
2917 if (GET_CODE (PATTERN (insn)) == USE
2918 || GET_CODE (PATTERN (insn)) == CLOBBER
2919 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2920 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2921 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2926 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2927 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2929 /* Check for setting an eliminable register. */
2930 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2931 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2933 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2934 /* If this is setting the frame pointer register to the
2935 hardware frame pointer register and this is an elimination
2936 that will be done (tested above), this insn is really
2937 adjusting the frame pointer downward to compensate for
2938 the adjustment done before a nonlocal goto. */
2939 if (ep->from == FRAME_POINTER_REGNUM
2940 && ep->to == HARD_FRAME_POINTER_REGNUM)
2942 rtx src = SET_SRC (old_set);
2943 int offset = 0, ok = 0;
2944 rtx prev_insn, prev_set;
2946 if (src == ep->to_rtx)
2948 else if (GET_CODE (src) == PLUS
2949 && GET_CODE (XEXP (src, 0)) == CONST_INT
2950 && XEXP (src, 1) == ep->to_rtx)
2951 offset = INTVAL (XEXP (src, 0)), ok = 1;
2952 else if (GET_CODE (src) == PLUS
2953 && GET_CODE (XEXP (src, 1)) == CONST_INT
2954 && XEXP (src, 0) == ep->to_rtx)
2955 offset = INTVAL (XEXP (src, 1)), ok = 1;
2956 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2957 && (prev_set = single_set (prev_insn)) != 0
2958 && rtx_equal_p (SET_DEST (prev_set), src))
2960 src = SET_SRC (prev_set);
2961 if (src == ep->to_rtx)
2963 else if (GET_CODE (src) == PLUS
2964 && GET_CODE (XEXP (src, 0)) == CONST_INT
2965 && XEXP (src, 1) == ep->to_rtx)
2966 offset = INTVAL (XEXP (src, 0)), ok = 1;
2967 else if (GET_CODE (src) == PLUS
2968 && GET_CODE (XEXP (src, 1)) == CONST_INT
2969 && XEXP (src, 0) == ep->to_rtx)
2970 offset = INTVAL (XEXP (src, 1)), ok = 1;
2978 = plus_constant (ep->to_rtx, offset - ep->offset);
2980 /* First see if this insn remains valid when we
2981 make the change. If not, keep the INSN_CODE
2982 the same and let reload fit it up. */
2983 validate_change (insn, &SET_SRC (old_set), src, 1);
2984 validate_change (insn, &SET_DEST (old_set),
2986 if (! apply_change_group ())
2988 SET_SRC (old_set) = src;
2989 SET_DEST (old_set) = ep->to_rtx;
2999 /* In this case this insn isn't serving a useful purpose. We
3000 will delete it in reload_as_needed once we know that this
3001 elimination is, in fact, being done.
3003 If REPLACE isn't set, we can't delete this insn, but needn't
3004 process it since it won't be used unless something changes. */
3007 delete_dead_insn (insn);
3015 /* We allow one special case which happens to work on all machines we
3016 currently support: a single set with the source being a PLUS of an
3017 eliminable register and a constant. */
3019 && GET_CODE (SET_SRC (old_set)) == PLUS
3020 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3021 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3022 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3024 rtx reg = XEXP (SET_SRC (old_set), 0);
3025 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3028 if (ep->from_rtx == reg && ep->can_eliminate)
3030 offset += ep->offset;
3035 /* We assume here that if we need a PARALLEL with
3036 CLOBBERs for this assignment, we can do with the
3037 MATCH_SCRATCHes that add_clobbers allocates.
3038 There's not much we can do if that doesn't work. */
3039 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3043 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3046 rtvec vec = rtvec_alloc (num_clobbers + 1);
3048 vec->elem[0] = PATTERN (insn);
3049 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3050 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3052 if (INSN_CODE (insn) < 0)
3057 new_body = old_body;
3060 new_body = copy_insn (old_body);
3061 if (REG_NOTES (insn))
3062 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3064 PATTERN (insn) = new_body;
3065 old_set = single_set (insn);
3067 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3068 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3071 /* This can't have an effect on elimination offsets, so skip right
3077 /* Determine the effects of this insn on elimination offsets. */
3078 elimination_effects (old_body, 0);
3080 /* Eliminate all eliminable registers occurring in operands that
3081 can be handled by reload. */
3082 extract_insn (insn);
3084 for (i = 0; i < recog_data.n_operands; i++)
3086 orig_operand[i] = recog_data.operand[i];
3087 substed_operand[i] = recog_data.operand[i];
3089 /* For an asm statement, every operand is eliminable. */
3090 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3092 /* Check for setting a register that we know about. */
3093 if (recog_data.operand_type[i] != OP_IN
3094 && GET_CODE (orig_operand[i]) == REG)
3096 /* If we are assigning to a register that can be eliminated, it
3097 must be as part of a PARALLEL, since the code above handles
3098 single SETs. We must indicate that we can no longer
3099 eliminate this reg. */
3100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3102 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3103 ep->can_eliminate = 0;
3106 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3107 replace ? insn : NULL_RTX);
3108 if (substed_operand[i] != orig_operand[i])
3109 val = any_changes = 1;
3110 /* Terminate the search in check_eliminable_occurrences at
3112 *recog_data.operand_loc[i] = 0;
3114 /* If an output operand changed from a REG to a MEM and INSN is an
3115 insn, write a CLOBBER insn. */
3116 if (recog_data.operand_type[i] != OP_IN
3117 && GET_CODE (orig_operand[i]) == REG
3118 && GET_CODE (substed_operand[i]) == MEM
3120 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3125 for (i = 0; i < recog_data.n_dups; i++)
3126 *recog_data.dup_loc[i]
3127 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3129 /* If any eliminable remain, they aren't eliminable anymore. */
3130 check_eliminable_occurrences (old_body);
3132 /* Substitute the operands; the new values are in the substed_operand
3134 for (i = 0; i < recog_data.n_operands; i++)
3135 *recog_data.operand_loc[i] = substed_operand[i];
3136 for (i = 0; i < recog_data.n_dups; i++)
3137 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3139 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3140 re-recognize the insn. We do this in case we had a simple addition
3141 but now can do this as a load-address. This saves an insn in this
3143 If re-recognition fails, the old insn code number will still be used,
3144 and some register operands may have changed into PLUS expressions.
3145 These will be handled by find_reloads by loading them into a register
3150 /* If we aren't replacing things permanently and we changed something,
3151 make another copy to ensure that all the RTL is new. Otherwise
3152 things can go wrong if find_reload swaps commutative operands
3153 and one is inside RTL that has been copied while the other is not. */
3154 new_body = old_body;
3157 new_body = copy_insn (old_body);
3158 if (REG_NOTES (insn))
3159 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3161 PATTERN (insn) = new_body;
3163 /* If we had a move insn but now we don't, rerecognize it. This will
3164 cause spurious re-recognition if the old move had a PARALLEL since
3165 the new one still will, but we can't call single_set without
3166 having put NEW_BODY into the insn and the re-recognition won't
3167 hurt in this rare case. */
3168 /* ??? Why this huge if statement - why don't we just rerecognize the
3172 && ((GET_CODE (SET_SRC (old_set)) == REG
3173 && (GET_CODE (new_body) != SET
3174 || GET_CODE (SET_SRC (new_body)) != REG))
3175 /* If this was a load from or store to memory, compare
3176 the MEM in recog_data.operand to the one in the insn.
3177 If they are not equal, then rerecognize the insn. */
3179 && ((GET_CODE (SET_SRC (old_set)) == MEM
3180 && SET_SRC (old_set) != recog_data.operand[1])
3181 || (GET_CODE (SET_DEST (old_set)) == MEM
3182 && SET_DEST (old_set) != recog_data.operand[0])))
3183 /* If this was an add insn before, rerecognize. */
3184 || GET_CODE (SET_SRC (old_set)) == PLUS))
3186 int new_icode = recog (PATTERN (insn), insn, 0);
3188 INSN_CODE (insn) = icode;
3192 /* Restore the old body. If there were any changes to it, we made a copy
3193 of it while the changes were still in place, so we'll correctly return
3194 a modified insn below. */
3197 /* Restore the old body. */
3198 for (i = 0; i < recog_data.n_operands; i++)
3199 *recog_data.operand_loc[i] = orig_operand[i];
3200 for (i = 0; i < recog_data.n_dups; i++)
3201 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3204 /* Update all elimination pairs to reflect the status after the current
3205 insn. The changes we make were determined by the earlier call to
3206 elimination_effects.
3208 We also detect a cases where register elimination cannot be done,
3209 namely, if a register would be both changed and referenced outside a MEM
3210 in the resulting insn since such an insn is often undefined and, even if
3211 not, we cannot know what meaning will be given to it. Note that it is
3212 valid to have a register used in an address in an insn that changes it
3213 (presumably with a pre- or post-increment or decrement).
3215 If anything changes, return nonzero. */
3217 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3220 ep->can_eliminate = 0;
3222 ep->ref_outside_mem = 0;
3224 if (ep->previous_offset != ep->offset)
3229 /* If we changed something, perform elimination in REG_NOTES. This is
3230 needed even when REPLACE is zero because a REG_DEAD note might refer
3231 to a register that we eliminate and could cause a different number
3232 of spill registers to be needed in the final reload pass than in
3234 if (val && REG_NOTES (insn) != 0)
3235 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3240 /* Loop through all elimination pairs.
3241 Recalculate the number not at initial offset.
3243 Compute the maximum offset (minimum offset if the stack does not
3244 grow downward) for each elimination pair. */
3247 update_eliminable_offsets ()
3249 struct elim_table *ep;
3251 num_not_at_initial_offset = 0;
3252 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 ep->previous_offset = ep->offset;
3255 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3256 num_not_at_initial_offset++;
3260 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3261 replacement we currently believe is valid, mark it as not eliminable if X
3262 modifies DEST in any way other than by adding a constant integer to it.
3264 If DEST is the frame pointer, we do nothing because we assume that
3265 all assignments to the hard frame pointer are nonlocal gotos and are being
3266 done at a time when they are valid and do not disturb anything else.
3267 Some machines want to eliminate a fake argument pointer with either the
3268 frame or stack pointer. Assignments to the hard frame pointer must not
3269 prevent this elimination.
3271 Called via note_stores from reload before starting its passes to scan
3272 the insns of the function. */
3275 mark_not_eliminable (dest, x, data)
3278 void *data ATTRIBUTE_UNUSED;
3280 register unsigned int i;
3282 /* A SUBREG of a hard register here is just changing its mode. We should
3283 not see a SUBREG of an eliminable hard register, but check just in
3285 if (GET_CODE (dest) == SUBREG)
3286 dest = SUBREG_REG (dest);
3288 if (dest == hard_frame_pointer_rtx)
3291 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3292 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3293 && (GET_CODE (x) != SET
3294 || GET_CODE (SET_SRC (x)) != PLUS
3295 || XEXP (SET_SRC (x), 0) != dest
3296 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3298 reg_eliminate[i].can_eliminate_previous
3299 = reg_eliminate[i].can_eliminate = 0;
3304 /* Verify that the initial elimination offsets did not change since the
3305 last call to set_initial_elim_offsets. This is used to catch cases
3306 where something illegal happened during reload_as_needed that could
3307 cause incorrect code to be generated if we did not check for it. */
3310 verify_initial_elim_offsets ()
3314 #ifdef ELIMINABLE_REGS
3315 struct elim_table *ep;
3317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3319 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3320 if (t != ep->initial_offset)
3324 INITIAL_FRAME_POINTER_OFFSET (t);
3325 if (t != reg_eliminate[0].initial_offset)
3330 /* Reset all offsets on eliminable registers to their initial values. */
3333 set_initial_elim_offsets ()
3335 struct elim_table *ep = reg_eliminate;
3337 #ifdef ELIMINABLE_REGS
3338 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3340 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3341 ep->previous_offset = ep->offset = ep->initial_offset;
3344 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3345 ep->previous_offset = ep->offset = ep->initial_offset;
3348 num_not_at_initial_offset = 0;
3351 /* Initialize the known label offsets.
3352 Set a known offset for each forced label to be at the initial offset
3353 of each elimination. We do this because we assume that all
3354 computed jumps occur from a location where each elimination is
3355 at its initial offset.
3356 For all other labels, show that we don't know the offsets. */
3359 set_initial_label_offsets ()
3362 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3364 for (x = forced_labels; x; x = XEXP (x, 1))
3366 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3369 /* Set all elimination offsets to the known values for the code label given
3373 set_offsets_for_label (insn)
3377 int label_nr = CODE_LABEL_NUMBER (insn);
3378 struct elim_table *ep;
3380 num_not_at_initial_offset = 0;
3381 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3383 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3384 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3385 num_not_at_initial_offset++;
3389 /* See if anything that happened changes which eliminations are valid.
3390 For example, on the Sparc, whether or not the frame pointer can
3391 be eliminated can depend on what registers have been used. We need
3392 not check some conditions again (such as flag_omit_frame_pointer)
3393 since they can't have changed. */
3396 update_eliminables (pset)
3399 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3400 int previous_frame_pointer_needed = frame_pointer_needed;
3402 struct elim_table *ep;
3404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3405 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3406 #ifdef ELIMINABLE_REGS
3407 || ! CAN_ELIMINATE (ep->from, ep->to)
3410 ep->can_eliminate = 0;
3412 /* Look for the case where we have discovered that we can't replace
3413 register A with register B and that means that we will now be
3414 trying to replace register A with register C. This means we can
3415 no longer replace register C with register B and we need to disable
3416 such an elimination, if it exists. This occurs often with A == ap,
3417 B == sp, and C == fp. */
3419 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3421 struct elim_table *op;
3422 register int new_to = -1;
3424 if (! ep->can_eliminate && ep->can_eliminate_previous)
3426 /* Find the current elimination for ep->from, if there is a
3428 for (op = reg_eliminate;
3429 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3430 if (op->from == ep->from && op->can_eliminate)
3436 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3438 for (op = reg_eliminate;
3439 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3440 if (op->from == new_to && op->to == ep->to)
3441 op->can_eliminate = 0;
3445 /* See if any registers that we thought we could eliminate the previous
3446 time are no longer eliminable. If so, something has changed and we
3447 must spill the register. Also, recompute the number of eliminable
3448 registers and see if the frame pointer is needed; it is if there is
3449 no elimination of the frame pointer that we can perform. */
3451 frame_pointer_needed = 1;
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3455 && ep->to != HARD_FRAME_POINTER_REGNUM)
3456 frame_pointer_needed = 0;
3458 if (! ep->can_eliminate && ep->can_eliminate_previous)
3460 ep->can_eliminate_previous = 0;
3461 SET_HARD_REG_BIT (*pset, ep->from);
3466 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3467 /* If we didn't need a frame pointer last time, but we do now, spill
3468 the hard frame pointer. */
3469 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3470 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3474 /* Initialize the table of registers to eliminate. */
3479 struct elim_table *ep;
3480 #ifdef ELIMINABLE_REGS
3481 struct elim_table_1 *ep1;
3485 reg_eliminate = (struct elim_table *)
3486 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3488 /* Does this function require a frame pointer? */
3490 frame_pointer_needed = (! flag_omit_frame_pointer
3491 #ifdef EXIT_IGNORE_STACK
3492 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3493 and restore sp for alloca. So we can't eliminate
3494 the frame pointer in that case. At some point,
3495 we should improve this by emitting the
3496 sp-adjusting insns for this case. */
3497 || (current_function_calls_alloca
3498 && EXIT_IGNORE_STACK)
3500 || FRAME_POINTER_REQUIRED);
3504 #ifdef ELIMINABLE_REGS
3505 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3506 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3508 ep->from = ep1->from;
3510 ep->can_eliminate = ep->can_eliminate_previous
3511 = (CAN_ELIMINATE (ep->from, ep->to)
3512 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3515 reg_eliminate[0].from = reg_eliminate_1[0].from;
3516 reg_eliminate[0].to = reg_eliminate_1[0].to;
3517 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3518 = ! frame_pointer_needed;
3521 /* Count the number of eliminable registers and build the FROM and TO
3522 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3523 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3524 We depend on this. */
3525 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3527 num_eliminable += ep->can_eliminate;
3528 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3529 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3533 /* Kick all pseudos out of hard register REGNO.
3535 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3536 because we found we can't eliminate some register. In the case, no pseudos
3537 are allowed to be in the register, even if they are only in a block that
3538 doesn't require spill registers, unlike the case when we are spilling this
3539 hard reg to produce another spill register.
3541 Return nonzero if any pseudos needed to be kicked out. */
3544 spill_hard_reg (regno, cant_eliminate)
3552 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3553 regs_ever_live[regno] = 1;
3556 /* Spill every pseudo reg that was allocated to this reg
3557 or to something that overlaps this reg. */
3559 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3560 if (reg_renumber[i] >= 0
3561 && (unsigned int) reg_renumber[i] <= regno
3562 && ((unsigned int) reg_renumber[i]
3563 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3564 PSEUDO_REGNO_MODE (i))
3566 SET_REGNO_REG_SET (&spilled_pseudos, i);
3569 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3570 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3573 ior_hard_reg_set (set1, set2)
3574 HARD_REG_SET *set1, *set2;
3576 IOR_HARD_REG_SET (*set1, *set2);
3579 /* After find_reload_regs has been run for all insn that need reloads,
3580 and/or spill_hard_regs was called, this function is used to actually
3581 spill pseudo registers and try to reallocate them. It also sets up the
3582 spill_regs array for use by choose_reload_regs. */
3585 finish_spills (global)
3588 struct insn_chain *chain;
3589 int something_changed = 0;
3592 /* Build the spill_regs array for the function. */
3593 /* If there are some registers still to eliminate and one of the spill regs
3594 wasn't ever used before, additional stack space may have to be
3595 allocated to store this register. Thus, we may have changed the offset
3596 between the stack and frame pointers, so mark that something has changed.
3598 One might think that we need only set VAL to 1 if this is a call-used
3599 register. However, the set of registers that must be saved by the
3600 prologue is not identical to the call-used set. For example, the
3601 register used by the call insn for the return PC is a call-used register,
3602 but must be saved by the prologue. */
3605 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3606 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3608 spill_reg_order[i] = n_spills;
3609 spill_regs[n_spills++] = i;
3610 if (num_eliminable && ! regs_ever_live[i])
3611 something_changed = 1;
3612 regs_ever_live[i] = 1;
3615 spill_reg_order[i] = -1;
3617 EXECUTE_IF_SET_IN_REG_SET
3618 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3620 /* Record the current hard register the pseudo is allocated to in
3621 pseudo_previous_regs so we avoid reallocating it to the same
3622 hard reg in a later pass. */
3623 if (reg_renumber[i] < 0)
3626 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3627 /* Mark it as no longer having a hard register home. */
3628 reg_renumber[i] = -1;
3629 /* We will need to scan everything again. */
3630 something_changed = 1;
3633 /* Retry global register allocation if possible. */
3636 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3637 /* For every insn that needs reloads, set the registers used as spill
3638 regs in pseudo_forbidden_regs for every pseudo live across the
3640 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3642 EXECUTE_IF_SET_IN_REG_SET
3643 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3645 ior_hard_reg_set (pseudo_forbidden_regs + i,
3646 &chain->used_spill_regs);
3648 EXECUTE_IF_SET_IN_REG_SET
3649 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3651 ior_hard_reg_set (pseudo_forbidden_regs + i,
3652 &chain->used_spill_regs);
3656 /* Retry allocating the spilled pseudos. For each reg, merge the
3657 various reg sets that indicate which hard regs can't be used,
3658 and call retry_global_alloc.
3659 We change spill_pseudos here to only contain pseudos that did not
3660 get a new hard register. */
3661 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3662 if (reg_old_renumber[i] != reg_renumber[i])
3664 HARD_REG_SET forbidden;
3665 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3666 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3667 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3668 retry_global_alloc (i, forbidden);
3669 if (reg_renumber[i] >= 0)
3670 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3674 /* Fix up the register information in the insn chain.
3675 This involves deleting those of the spilled pseudos which did not get
3676 a new hard register home from the live_{before,after} sets. */
3677 for (chain = reload_insn_chain; chain; chain = chain->next)
3679 HARD_REG_SET used_by_pseudos;
3680 HARD_REG_SET used_by_pseudos2;
3682 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3683 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3685 /* Mark any unallocated hard regs as available for spills. That
3686 makes inheritance work somewhat better. */
3687 if (chain->need_reload)
3689 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3691 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3693 /* Save the old value for the sanity test below. */
3694 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3696 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3698 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3699 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3701 /* Make sure we only enlarge the set. */
3702 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3708 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3709 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3711 int regno = reg_renumber[i];
3712 if (reg_old_renumber[i] == regno)
3715 alter_reg (i, reg_old_renumber[i]);
3716 reg_old_renumber[i] = regno;
3720 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3722 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3723 i, reg_renumber[i]);
3727 return something_changed;
3730 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3731 Also mark any hard registers used to store user variables as
3732 forbidden from being used for spill registers. */
3735 scan_paradoxical_subregs (x)
3739 register const char *fmt;
3740 register enum rtx_code code = GET_CODE (x);
3746 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3747 && REG_USERVAR_P (x))
3748 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3764 if (GET_CODE (SUBREG_REG (x)) == REG
3765 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3766 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3767 = GET_MODE_SIZE (GET_MODE (x));
3774 fmt = GET_RTX_FORMAT (code);
3775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3778 scan_paradoxical_subregs (XEXP (x, i));
3779 else if (fmt[i] == 'E')
3782 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3783 scan_paradoxical_subregs (XVECEXP (x, i, j));
3788 /* Reload pseudo-registers into hard regs around each insn as needed.
3789 Additional register load insns are output before the insn that needs it
3790 and perhaps store insns after insns that modify the reloaded pseudo reg.
3792 reg_last_reload_reg and reg_reloaded_contents keep track of
3793 which registers are already available in reload registers.
3794 We update these for the reloads that we perform,
3795 as the insns are scanned. */
3798 reload_as_needed (live_known)
3801 struct insn_chain *chain;
3802 #if defined (AUTO_INC_DEC)
3807 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3808 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3809 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3810 reg_has_output_reload = (char *) xmalloc (max_regno);
3811 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3813 set_initial_elim_offsets ();
3815 for (chain = reload_insn_chain; chain; chain = chain->next)
3818 rtx insn = chain->insn;
3819 rtx old_next = NEXT_INSN (insn);
3821 /* If we pass a label, copy the offsets from the label information
3822 into the current offsets of each elimination. */
3823 if (GET_CODE (insn) == CODE_LABEL)
3824 set_offsets_for_label (insn);
3826 else if (INSN_P (insn))
3828 rtx oldpat = PATTERN (insn);
3830 /* If this is a USE and CLOBBER of a MEM, ensure that any
3831 references to eliminable registers have been removed. */
3833 if ((GET_CODE (PATTERN (insn)) == USE
3834 || GET_CODE (PATTERN (insn)) == CLOBBER)
3835 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3836 XEXP (XEXP (PATTERN (insn), 0), 0)
3837 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3838 GET_MODE (XEXP (PATTERN (insn), 0)),
3841 /* If we need to do register elimination processing, do so.
3842 This might delete the insn, in which case we are done. */
3843 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3845 eliminate_regs_in_insn (insn, 1);
3846 if (GET_CODE (insn) == NOTE)
3848 update_eliminable_offsets ();
3853 /* If need_elim is nonzero but need_reload is zero, one might think
3854 that we could simply set n_reloads to 0. However, find_reloads
3855 could have done some manipulation of the insn (such as swapping
3856 commutative operands), and these manipulations are lost during
3857 the first pass for every insn that needs register elimination.
3858 So the actions of find_reloads must be redone here. */
3860 if (! chain->need_elim && ! chain->need_reload
3861 && ! chain->need_operand_change)
3863 /* First find the pseudo regs that must be reloaded for this insn.
3864 This info is returned in the tables reload_... (see reload.h).
3865 Also modify the body of INSN by substituting RELOAD
3866 rtx's for those pseudo regs. */
3869 memset (reg_has_output_reload, 0, max_regno);
3870 CLEAR_HARD_REG_SET (reg_is_output_reload);
3872 find_reloads (insn, 1, spill_indirect_levels, live_known,
3876 if (num_eliminable && chain->need_elim)
3877 update_eliminable_offsets ();
3881 rtx next = NEXT_INSN (insn);
3884 prev = PREV_INSN (insn);
3886 /* Now compute which reload regs to reload them into. Perhaps
3887 reusing reload regs from previous insns, or else output
3888 load insns to reload them. Maybe output store insns too.
3889 Record the choices of reload reg in reload_reg_rtx. */
3890 choose_reload_regs (chain);
3892 /* Merge any reloads that we didn't combine for fear of
3893 increasing the number of spill registers needed but now
3894 discover can be safely merged. */
3895 if (SMALL_REGISTER_CLASSES)
3896 merge_assigned_reloads (insn);
3898 /* Generate the insns to reload operands into or out of
3899 their reload regs. */
3900 emit_reload_insns (chain);
3902 /* Substitute the chosen reload regs from reload_reg_rtx
3903 into the insn's body (or perhaps into the bodies of other
3904 load and store insn that we just made for reloading
3905 and that we moved the structure into). */
3906 subst_reloads (insn);
3908 /* If this was an ASM, make sure that all the reload insns
3909 we have generated are valid. If not, give an error
3912 if (asm_noperands (PATTERN (insn)) >= 0)
3913 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3914 if (p != insn && INSN_P (p)
3915 && (recog_memoized (p) < 0
3916 || (extract_insn (p), ! constrain_operands (1))))
3918 error_for_asm (insn,
3919 "`asm' operand requires impossible reload");
3921 NOTE_SOURCE_FILE (p) = 0;
3922 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3925 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3926 is no longer validly lying around to save a future reload.
3927 Note that this does not detect pseudos that were reloaded
3928 for this insn in order to be stored in
3929 (obeying register constraints). That is correct; such reload
3930 registers ARE still valid. */
3931 note_stores (oldpat, forget_old_reloads_1, NULL);
3933 /* There may have been CLOBBER insns placed after INSN. So scan
3934 between INSN and NEXT and use them to forget old reloads. */
3935 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3936 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3937 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3940 /* Likewise for regs altered by auto-increment in this insn.
3941 REG_INC notes have been changed by reloading:
3942 find_reloads_address_1 records substitutions for them,
3943 which have been performed by subst_reloads above. */
3944 for (i = n_reloads - 1; i >= 0; i--)
3946 rtx in_reg = rld[i].in_reg;
3949 enum rtx_code code = GET_CODE (in_reg);
3950 /* PRE_INC / PRE_DEC will have the reload register ending up
3951 with the same value as the stack slot, but that doesn't
3952 hold true for POST_INC / POST_DEC. Either we have to
3953 convert the memory access to a true POST_INC / POST_DEC,
3954 or we can't use the reload register for inheritance. */
3955 if ((code == POST_INC || code == POST_DEC)
3956 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3957 REGNO (rld[i].reg_rtx))
3958 /* Make sure it is the inc/dec pseudo, and not
3959 some other (e.g. output operand) pseudo. */
3960 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3961 == REGNO (XEXP (in_reg, 0))))
3964 rtx reload_reg = rld[i].reg_rtx;
3965 enum machine_mode mode = GET_MODE (reload_reg);
3969 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3971 /* We really want to ignore REG_INC notes here, so
3972 use PATTERN (p) as argument to reg_set_p . */
3973 if (reg_set_p (reload_reg, PATTERN (p)))
3975 n = count_occurrences (PATTERN (p), reload_reg, 0);
3980 n = validate_replace_rtx (reload_reg,
3981 gen_rtx (code, mode,
3985 /* We must also verify that the constraints
3986 are met after the replacement. */
3989 n = constrain_operands (1);
3993 /* If the constraints were not met, then
3994 undo the replacement. */
3997 validate_replace_rtx (gen_rtx (code, mode,
4009 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4011 /* Mark this as having an output reload so that the
4012 REG_INC processing code below won't invalidate
4013 the reload for inheritance. */
4014 SET_HARD_REG_BIT (reg_is_output_reload,
4015 REGNO (reload_reg));
4016 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4019 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4022 else if ((code == PRE_INC || code == PRE_DEC)
4023 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4024 REGNO (rld[i].reg_rtx))
4025 /* Make sure it is the inc/dec pseudo, and not
4026 some other (e.g. output operand) pseudo. */
4027 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4028 == REGNO (XEXP (in_reg, 0))))
4030 SET_HARD_REG_BIT (reg_is_output_reload,
4031 REGNO (rld[i].reg_rtx));
4032 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4036 /* If a pseudo that got a hard register is auto-incremented,
4037 we must purge records of copying it into pseudos without
4039 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4040 if (REG_NOTE_KIND (x) == REG_INC)
4042 /* See if this pseudo reg was reloaded in this insn.
4043 If so, its last-reload info is still valid
4044 because it is based on this insn's reload. */
4045 for (i = 0; i < n_reloads; i++)
4046 if (rld[i].out == XEXP (x, 0))
4050 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4054 /* A reload reg's contents are unknown after a label. */
4055 if (GET_CODE (insn) == CODE_LABEL)
4056 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4058 /* Don't assume a reload reg is still good after a call insn
4059 if it is a call-used reg. */
4060 else if (GET_CODE (insn) == CALL_INSN)
4061 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4065 free (reg_last_reload_reg);
4066 free (reg_has_output_reload);
4069 /* Discard all record of any value reloaded from X,
4070 or reloaded in X from someplace else;
4071 unless X is an output reload reg of the current insn.
4073 X may be a hard reg (the reload reg)
4074 or it may be a pseudo reg that was reloaded from. */
4077 forget_old_reloads_1 (x, ignored, data)
4079 rtx ignored ATTRIBUTE_UNUSED;
4080 void *data ATTRIBUTE_UNUSED;
4086 /* note_stores does give us subregs of hard regs. */
4087 while (GET_CODE (x) == SUBREG)
4089 offset += SUBREG_WORD (x);
4093 if (GET_CODE (x) != REG)
4096 regno = REGNO (x) + offset;
4098 if (regno >= FIRST_PSEUDO_REGISTER)
4104 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4105 /* Storing into a spilled-reg invalidates its contents.
4106 This can happen if a block-local pseudo is allocated to that reg
4107 and it wasn't spilled because this block's total need is 0.
4108 Then some insn might have an optional reload and use this reg. */
4109 for (i = 0; i < nr; i++)
4110 /* But don't do this if the reg actually serves as an output
4111 reload reg in the current instruction. */
4113 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4115 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4116 spill_reg_store[regno + i] = 0;
4120 /* Since value of X has changed,
4121 forget any value previously copied from it. */
4124 /* But don't forget a copy if this is the output reload
4125 that establishes the copy's validity. */
4126 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4127 reg_last_reload_reg[regno + nr] = 0;
4130 /* The following HARD_REG_SETs indicate when each hard register is
4131 used for a reload of various parts of the current insn. */
4133 /* If reg is unavailable for all reloads. */
4134 static HARD_REG_SET reload_reg_unavailable;
4135 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4136 static HARD_REG_SET reload_reg_used;
4137 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4146 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4147 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4148 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4149 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4150 static HARD_REG_SET reload_reg_used_in_op_addr;
4151 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4152 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4153 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4154 static HARD_REG_SET reload_reg_used_in_insn;
4155 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4156 static HARD_REG_SET reload_reg_used_in_other_addr;
4158 /* If reg is in use as a reload reg for any sort of reload. */
4159 static HARD_REG_SET reload_reg_used_at_all;
4161 /* If reg is use as an inherited reload. We just mark the first register
4163 static HARD_REG_SET reload_reg_used_for_inherit;
4165 /* Records which hard regs are used in any way, either as explicit use or
4166 by being allocated to a pseudo during any point of the current insn. */
4167 static HARD_REG_SET reg_used_in_insn;
4169 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4170 TYPE. MODE is used to indicate how many consecutive regs are
4174 mark_reload_reg_in_use (regno, opnum, type, mode)
4177 enum reload_type type;
4178 enum machine_mode mode;
4180 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4183 for (i = regno; i < nregs + regno; i++)
4188 SET_HARD_REG_BIT (reload_reg_used, i);
4191 case RELOAD_FOR_INPUT_ADDRESS:
4192 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4195 case RELOAD_FOR_INPADDR_ADDRESS:
4196 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4199 case RELOAD_FOR_OUTPUT_ADDRESS:
4200 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4203 case RELOAD_FOR_OUTADDR_ADDRESS:
4204 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4207 case RELOAD_FOR_OPERAND_ADDRESS:
4208 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4211 case RELOAD_FOR_OPADDR_ADDR:
4212 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4215 case RELOAD_FOR_OTHER_ADDRESS:
4216 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4219 case RELOAD_FOR_INPUT:
4220 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4223 case RELOAD_FOR_OUTPUT:
4224 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4227 case RELOAD_FOR_INSN:
4228 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4232 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4236 /* Similarly, but show REGNO is no longer in use for a reload. */
4239 clear_reload_reg_in_use (regno, opnum, type, mode)
4242 enum reload_type type;
4243 enum machine_mode mode;
4245 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4246 unsigned int start_regno, end_regno, r;
4248 /* A complication is that for some reload types, inheritance might
4249 allow multiple reloads of the same types to share a reload register.
4250 We set check_opnum if we have to check only reloads with the same
4251 operand number, and check_any if we have to check all reloads. */
4252 int check_opnum = 0;
4254 HARD_REG_SET *used_in_set;
4259 used_in_set = &reload_reg_used;
4262 case RELOAD_FOR_INPUT_ADDRESS:
4263 used_in_set = &reload_reg_used_in_input_addr[opnum];
4266 case RELOAD_FOR_INPADDR_ADDRESS:
4268 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4271 case RELOAD_FOR_OUTPUT_ADDRESS:
4272 used_in_set = &reload_reg_used_in_output_addr[opnum];
4275 case RELOAD_FOR_OUTADDR_ADDRESS:
4277 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4280 case RELOAD_FOR_OPERAND_ADDRESS:
4281 used_in_set = &reload_reg_used_in_op_addr;
4284 case RELOAD_FOR_OPADDR_ADDR:
4286 used_in_set = &reload_reg_used_in_op_addr_reload;
4289 case RELOAD_FOR_OTHER_ADDRESS:
4290 used_in_set = &reload_reg_used_in_other_addr;
4294 case RELOAD_FOR_INPUT:
4295 used_in_set = &reload_reg_used_in_input[opnum];
4298 case RELOAD_FOR_OUTPUT:
4299 used_in_set = &reload_reg_used_in_output[opnum];
4302 case RELOAD_FOR_INSN:
4303 used_in_set = &reload_reg_used_in_insn;
4308 /* We resolve conflicts with remaining reloads of the same type by
4309 excluding the intervals of of reload registers by them from the
4310 interval of freed reload registers. Since we only keep track of
4311 one set of interval bounds, we might have to exclude somewhat
4312 more then what would be necessary if we used a HARD_REG_SET here.
4313 But this should only happen very infrequently, so there should
4314 be no reason to worry about it. */
4316 start_regno = regno;
4317 end_regno = regno + nregs;
4318 if (check_opnum || check_any)
4320 for (i = n_reloads - 1; i >= 0; i--)
4322 if (rld[i].when_needed == type
4323 && (check_any || rld[i].opnum == opnum)
4326 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4327 unsigned int conflict_end
4329 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4331 /* If there is an overlap with the first to-be-freed register,
4332 adjust the interval start. */
4333 if (conflict_start <= start_regno && conflict_end > start_regno)
4334 start_regno = conflict_end;
4335 /* Otherwise, if there is a conflict with one of the other
4336 to-be-freed registers, adjust the interval end. */
4337 if (conflict_start > start_regno && conflict_start < end_regno)
4338 end_regno = conflict_start;
4343 for (r = start_regno; r < end_regno; r++)
4344 CLEAR_HARD_REG_BIT (*used_in_set, r);
4347 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4348 specified by OPNUM and TYPE. */
4351 reload_reg_free_p (regno, opnum, type)
4354 enum reload_type type;
4358 /* In use for a RELOAD_OTHER means it's not available for anything. */
4359 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4360 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4366 /* In use for anything means we can't use it for RELOAD_OTHER. */
4367 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4368 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4372 for (i = 0; i < reload_n_operands; i++)
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4375 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4376 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4377 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4383 case RELOAD_FOR_INPUT:
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4391 /* If it is used for some other input, can't use it. */
4392 for (i = 0; i < reload_n_operands; i++)
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4396 /* If it is used in a later operand's address, can't use it. */
4397 for (i = opnum + 1; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4404 case RELOAD_FOR_INPUT_ADDRESS:
4405 /* Can't use a register if it is used for an input address for this
4406 operand or used as an input in an earlier one. */
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4408 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4411 for (i = 0; i < opnum; i++)
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4417 case RELOAD_FOR_INPADDR_ADDRESS:
4418 /* Can't use a register if it is used for an input address
4419 for this operand or used as an input in an earlier
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4424 for (i = 0; i < opnum; i++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4430 case RELOAD_FOR_OUTPUT_ADDRESS:
4431 /* Can't use a register if it is used for an output address for this
4432 operand or used as an output in this or a later operand. */
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4436 for (i = opnum; i < reload_n_operands; i++)
4437 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4442 case RELOAD_FOR_OUTADDR_ADDRESS:
4443 /* Can't use a register if it is used for an output address
4444 for this operand or used as an output in this or a
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4449 for (i = opnum; i < reload_n_operands; i++)
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4455 case RELOAD_FOR_OPERAND_ADDRESS:
4456 for (i = 0; i < reload_n_operands; i++)
4457 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4460 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4461 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4463 case RELOAD_FOR_OPADDR_ADDR:
4464 for (i = 0; i < reload_n_operands; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4468 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4470 case RELOAD_FOR_OUTPUT:
4471 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4472 outputs, or an operand address for this or an earlier output. */
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4476 for (i = 0; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4480 for (i = 0; i <= opnum; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4487 case RELOAD_FOR_INSN:
4488 for (i = 0; i < reload_n_operands; i++)
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4494 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4496 case RELOAD_FOR_OTHER_ADDRESS:
4497 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4502 /* Return 1 if the value in reload reg REGNO, as used by a reload
4503 needed for the part of the insn specified by OPNUM and TYPE,
4504 is still available in REGNO at the end of the insn.
4506 We can assume that the reload reg was already tested for availability
4507 at the time it is needed, and we should not check this again,
4508 in case the reg has already been marked in use. */
4511 reload_reg_reaches_end_p (regno, opnum, type)
4514 enum reload_type type;
4521 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4522 its value must reach the end. */
4525 /* If this use is for part of the insn,
4526 its value reaches if no subsequent part uses the same register.
4527 Just like the above function, don't try to do this with lots
4530 case RELOAD_FOR_OTHER_ADDRESS:
4531 /* Here we check for everything else, since these don't conflict
4532 with anything else and everything comes later. */
4534 for (i = 0; i < reload_n_operands; i++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4543 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4544 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4545 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4547 case RELOAD_FOR_INPUT_ADDRESS:
4548 case RELOAD_FOR_INPADDR_ADDRESS:
4549 /* Similar, except that we check only for this and subsequent inputs
4550 and the address of only subsequent inputs and we do not need
4551 to check for RELOAD_OTHER objects since they are known not to
4554 for (i = opnum; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4558 for (i = opnum + 1; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4563 for (i = 0; i < reload_n_operands; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4572 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4573 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4574 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4576 case RELOAD_FOR_INPUT:
4577 /* Similar to input address, except we start at the next operand for
4578 both input and input address and we do not check for
4579 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4582 for (i = opnum + 1; i < reload_n_operands; i++)
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4584 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4585 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4588 /* ... fall through ... */
4590 case RELOAD_FOR_OPERAND_ADDRESS:
4591 /* Check outputs and their addresses. */
4593 for (i = 0; i < reload_n_operands; i++)
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4599 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4601 case RELOAD_FOR_OPADDR_ADDR:
4602 for (i = 0; i < reload_n_operands; i++)
4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4608 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4609 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4610 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4612 case RELOAD_FOR_INSN:
4613 /* These conflict with other outputs with RELOAD_OTHER. So
4614 we need only check for output addresses. */
4618 /* ... fall through ... */
4620 case RELOAD_FOR_OUTPUT:
4621 case RELOAD_FOR_OUTPUT_ADDRESS:
4622 case RELOAD_FOR_OUTADDR_ADDRESS:
4623 /* We already know these can't conflict with a later output. So the
4624 only thing to check are later output addresses. */
4625 for (i = opnum + 1; i < reload_n_operands; i++)
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4627 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4636 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4639 This function uses the same algorithm as reload_reg_free_p above. */
4642 reloads_conflict (r1, r2)
4645 enum reload_type r1_type = rld[r1].when_needed;
4646 enum reload_type r2_type = rld[r2].when_needed;
4647 int r1_opnum = rld[r1].opnum;
4648 int r2_opnum = rld[r2].opnum;
4650 /* RELOAD_OTHER conflicts with everything. */
4651 if (r2_type == RELOAD_OTHER)
4654 /* Otherwise, check conflicts differently for each type. */
4658 case RELOAD_FOR_INPUT:
4659 return (r2_type == RELOAD_FOR_INSN
4660 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4661 || r2_type == RELOAD_FOR_OPADDR_ADDR
4662 || r2_type == RELOAD_FOR_INPUT
4663 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4664 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4665 && r2_opnum > r1_opnum));
4667 case RELOAD_FOR_INPUT_ADDRESS:
4668 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4669 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4671 case RELOAD_FOR_INPADDR_ADDRESS:
4672 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4673 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4675 case RELOAD_FOR_OUTPUT_ADDRESS:
4676 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4677 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4679 case RELOAD_FOR_OUTADDR_ADDRESS:
4680 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4681 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4683 case RELOAD_FOR_OPERAND_ADDRESS:
4684 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4685 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4687 case RELOAD_FOR_OPADDR_ADDR:
4688 return (r2_type == RELOAD_FOR_INPUT
4689 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4691 case RELOAD_FOR_OUTPUT:
4692 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4693 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4694 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4695 && r2_opnum <= r1_opnum));
4697 case RELOAD_FOR_INSN:
4698 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4699 || r2_type == RELOAD_FOR_INSN
4700 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4702 case RELOAD_FOR_OTHER_ADDRESS:
4703 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4713 /* Indexed by reload number, 1 if incoming value
4714 inherited from previous insns. */
4715 char reload_inherited[MAX_RELOADS];
4717 /* For an inherited reload, this is the insn the reload was inherited from,
4718 if we know it. Otherwise, this is 0. */
4719 rtx reload_inheritance_insn[MAX_RELOADS];
4721 /* If non-zero, this is a place to get the value of the reload,
4722 rather than using reload_in. */
4723 rtx reload_override_in[MAX_RELOADS];
4725 /* For each reload, the hard register number of the register used,
4726 or -1 if we did not need a register for this reload. */
4727 int reload_spill_index[MAX_RELOADS];
4729 /* Subroutine of free_for_value_p, used to check a single register.
4730 START_REGNO is the starting regno of the full reload register
4731 (possibly comprising multiple hard registers) that we are considering. */
4734 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4735 reloadnum, ignore_address_reloads)
4736 int start_regno, regno;
4738 enum reload_type type;
4741 int ignore_address_reloads;
4744 /* Set if we see an input reload that must not share its reload register
4745 with any new earlyclobber, but might otherwise share the reload
4746 register with an output or input-output reload. */
4747 int check_earlyclobber = 0;
4751 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4754 if (out == const0_rtx)
4760 /* We use some pseudo 'time' value to check if the lifetimes of the
4761 new register use would overlap with the one of a previous reload
4762 that is not read-only or uses a different value.
4763 The 'time' used doesn't have to be linear in any shape or form, just
4765 Some reload types use different 'buckets' for each operand.
4766 So there are MAX_RECOG_OPERANDS different time values for each
4768 We compute TIME1 as the time when the register for the prospective
4769 new reload ceases to be live, and TIME2 for each existing
4770 reload as the time when that the reload register of that reload
4772 Where there is little to be gained by exact lifetime calculations,
4773 we just make conservative assumptions, i.e. a longer lifetime;
4774 this is done in the 'default:' cases. */
4777 case RELOAD_FOR_OTHER_ADDRESS:
4778 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4779 time1 = copy ? 0 : 1;
4782 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4784 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4785 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4786 respectively, to the time values for these, we get distinct time
4787 values. To get distinct time values for each operand, we have to
4788 multiply opnum by at least three. We round that up to four because
4789 multiply by four is often cheaper. */
4790 case RELOAD_FOR_INPADDR_ADDRESS:
4791 time1 = opnum * 4 + 2;
4793 case RELOAD_FOR_INPUT_ADDRESS:
4794 time1 = opnum * 4 + 3;
4796 case RELOAD_FOR_INPUT:
4797 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4798 executes (inclusive). */
4799 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4801 case RELOAD_FOR_OPADDR_ADDR:
4803 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4804 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4806 case RELOAD_FOR_OPERAND_ADDRESS:
4807 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4809 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4811 case RELOAD_FOR_OUTADDR_ADDRESS:
4812 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4814 case RELOAD_FOR_OUTPUT_ADDRESS:
4815 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4818 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4821 for (i = 0; i < n_reloads; i++)
4823 rtx reg = rld[i].reg_rtx;
4824 if (reg && GET_CODE (reg) == REG
4825 && ((unsigned) regno - true_regnum (reg)
4826 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4829 rtx other_input = rld[i].in;
4831 /* If the other reload loads the same input value, that
4832 will not cause a conflict only if it's loading it into
4833 the same register. */
4834 if (true_regnum (reg) != start_regno)
4835 other_input = NULL_RTX;
4836 if (! other_input || ! rtx_equal_p (other_input, value)
4837 || rld[i].out || out)
4840 switch (rld[i].when_needed)
4842 case RELOAD_FOR_OTHER_ADDRESS:
4845 case RELOAD_FOR_INPADDR_ADDRESS:
4846 /* find_reloads makes sure that a
4847 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4848 by at most one - the first -
4849 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4850 address reload is inherited, the address address reload
4851 goes away, so we can ignore this conflict. */
4852 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4853 && ignore_address_reloads
4854 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4855 Then the address address is still needed to store
4856 back the new address. */
4857 && ! rld[reloadnum].out)
4859 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4860 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4862 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4863 && ignore_address_reloads
4864 /* Unless we are reloading an auto_inc expression. */
4865 && ! rld[reloadnum].out)
4867 time2 = rld[i].opnum * 4 + 2;
4869 case RELOAD_FOR_INPUT_ADDRESS:
4870 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4871 && ignore_address_reloads
4872 && ! rld[reloadnum].out)
4874 time2 = rld[i].opnum * 4 + 3;
4876 case RELOAD_FOR_INPUT:
4877 time2 = rld[i].opnum * 4 + 4;
4878 check_earlyclobber = 1;
4880 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4881 == MAX_RECOG_OPERAND * 4 */
4882 case RELOAD_FOR_OPADDR_ADDR:
4883 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4884 && ignore_address_reloads
4885 && ! rld[reloadnum].out)
4887 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4889 case RELOAD_FOR_OPERAND_ADDRESS:
4890 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4891 check_earlyclobber = 1;
4893 case RELOAD_FOR_INSN:
4894 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4896 case RELOAD_FOR_OUTPUT:
4897 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4898 instruction is executed. */
4899 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4901 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4902 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4904 case RELOAD_FOR_OUTADDR_ADDRESS:
4905 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4906 && ignore_address_reloads
4907 && ! rld[reloadnum].out)
4909 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4911 case RELOAD_FOR_OUTPUT_ADDRESS:
4912 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4915 /* If there is no conflict in the input part, handle this
4916 like an output reload. */
4917 if (! rld[i].in || rtx_equal_p (other_input, value))
4919 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4920 /* Earlyclobbered outputs must conflict with inputs. */
4921 if (earlyclobber_operand_p (rld[i].out))
4922 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4927 /* RELOAD_OTHER might be live beyond instruction execution,
4928 but this is not obvious when we set time2 = 1. So check
4929 here if there might be a problem with the new reload
4930 clobbering the register used by the RELOAD_OTHER. */
4938 && (! rld[i].in || rld[i].out
4939 || ! rtx_equal_p (other_input, value)))
4940 || (out && rld[reloadnum].out_reg
4941 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4947 /* Earlyclobbered outputs must conflict with inputs. */
4948 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4954 /* Return 1 if the value in reload reg REGNO, as used by a reload
4955 needed for the part of the insn specified by OPNUM and TYPE,
4956 may be used to load VALUE into it.
4958 MODE is the mode in which the register is used, this is needed to
4959 determine how many hard regs to test.
4961 Other read-only reloads with the same value do not conflict
4962 unless OUT is non-zero and these other reloads have to live while
4963 output reloads live.
4964 If OUT is CONST0_RTX, this is a special case: it means that the
4965 test should not be for using register REGNO as reload register, but
4966 for copying from register REGNO into the reload register.
4968 RELOADNUM is the number of the reload we want to load this value for;
4969 a reload does not conflict with itself.
4971 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4972 reloads that load an address for the very reload we are considering.
4974 The caller has to make sure that there is no conflict with the return
4978 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4979 ignore_address_reloads)
4981 enum machine_mode mode;
4983 enum reload_type type;
4986 int ignore_address_reloads;
4988 int nregs = HARD_REGNO_NREGS (regno, mode);
4990 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4991 value, out, reloadnum,
4992 ignore_address_reloads))
4997 /* Determine whether the reload reg X overlaps any rtx'es used for
4998 overriding inheritance. Return nonzero if so. */
5001 conflicts_with_override (x)
5005 for (i = 0; i < n_reloads; i++)
5006 if (reload_override_in[i]
5007 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5012 /* Give an error message saying we failed to find a reload for INSN,
5013 and clear out reload R. */
5015 failed_reload (insn, r)
5019 if (asm_noperands (PATTERN (insn)) < 0)
5020 /* It's the compiler's fault. */
5021 fatal_insn ("Could not find a spill register", insn);
5023 /* It's the user's fault; the operand's mode and constraint
5024 don't match. Disable this reload so we don't crash in final. */
5025 error_for_asm (insn,
5026 "`asm' operand constraint incompatible with operand size");
5030 rld[r].optional = 1;
5031 rld[r].secondary_p = 1;
5034 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5035 for reload R. If it's valid, get an rtx for it. Return nonzero if
5038 set_reload_reg (i, r)
5042 rtx reg = spill_reg_rtx[i];
5044 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5045 spill_reg_rtx[i] = reg
5046 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5048 regno = true_regnum (reg);
5050 /* Detect when the reload reg can't hold the reload mode.
5051 This used to be one `if', but Sequent compiler can't handle that. */
5052 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5054 enum machine_mode test_mode = VOIDmode;
5056 test_mode = GET_MODE (rld[r].in);
5057 /* If rld[r].in has VOIDmode, it means we will load it
5058 in whatever mode the reload reg has: to wit, rld[r].mode.
5059 We have already tested that for validity. */
5060 /* Aside from that, we need to test that the expressions
5061 to reload from or into have modes which are valid for this
5062 reload register. Otherwise the reload insns would be invalid. */
5063 if (! (rld[r].in != 0 && test_mode != VOIDmode
5064 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5065 if (! (rld[r].out != 0
5066 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5068 /* The reg is OK. */
5071 /* Mark as in use for this insn the reload regs we use
5073 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5074 rld[r].when_needed, rld[r].mode);
5076 rld[r].reg_rtx = reg;
5077 reload_spill_index[r] = spill_regs[i];
5084 /* Find a spill register to use as a reload register for reload R.
5085 LAST_RELOAD is non-zero if this is the last reload for the insn being
5088 Set rld[R].reg_rtx to the register allocated.
5090 We return 1 if successful, or 0 if we couldn't find a spill reg and
5091 we didn't change anything. */
5094 allocate_reload_reg (chain, r, last_reload)
5095 struct insn_chain *chain ATTRIBUTE_UNUSED;
5101 /* If we put this reload ahead, thinking it is a group,
5102 then insist on finding a group. Otherwise we can grab a
5103 reg that some other reload needs.
5104 (That can happen when we have a 68000 DATA_OR_FP_REG
5105 which is a group of data regs or one fp reg.)
5106 We need not be so restrictive if there are no more reloads
5109 ??? Really it would be nicer to have smarter handling
5110 for that kind of reg class, where a problem like this is normal.
5111 Perhaps those classes should be avoided for reloading
5112 by use of more alternatives. */
5114 int force_group = rld[r].nregs > 1 && ! last_reload;
5116 /* If we want a single register and haven't yet found one,
5117 take any reg in the right class and not in use.
5118 If we want a consecutive group, here is where we look for it.
5120 We use two passes so we can first look for reload regs to
5121 reuse, which are already in use for other reloads in this insn,
5122 and only then use additional registers.
5123 I think that maximizing reuse is needed to make sure we don't
5124 run out of reload regs. Suppose we have three reloads, and
5125 reloads A and B can share regs. These need two regs.
5126 Suppose A and B are given different regs.
5127 That leaves none for C. */
5128 for (pass = 0; pass < 2; pass++)
5130 /* I is the index in spill_regs.
5131 We advance it round-robin between insns to use all spill regs
5132 equally, so that inherited reloads have a chance
5133 of leapfrogging each other. */
5137 for (count = 0; count < n_spills; count++)
5139 int class = (int) rld[r].class;
5145 regnum = spill_regs[i];
5147 if ((reload_reg_free_p (regnum, rld[r].opnum,
5150 /* We check reload_reg_used to make sure we
5151 don't clobber the return register. */
5152 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5153 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5154 rld[r].when_needed, rld[r].in,
5156 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5157 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5158 /* Look first for regs to share, then for unshared. But
5159 don't share regs used for inherited reloads; they are
5160 the ones we want to preserve. */
5162 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5164 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5167 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5168 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5169 (on 68000) got us two FP regs. If NR is 1,
5170 we would reject both of them. */
5173 /* If we need only one reg, we have already won. */
5176 /* But reject a single reg if we demand a group. */
5181 /* Otherwise check that as many consecutive regs as we need
5182 are available here. */
5185 int regno = regnum + nr - 1;
5186 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5187 && spill_reg_order[regno] >= 0
5188 && reload_reg_free_p (regno, rld[r].opnum,
5189 rld[r].when_needed)))
5198 /* If we found something on pass 1, omit pass 2. */
5199 if (count < n_spills)
5203 /* We should have found a spill register by now. */
5204 if (count >= n_spills)
5207 /* I is the index in SPILL_REG_RTX of the reload register we are to
5208 allocate. Get an rtx for it and find its register number. */
5210 return set_reload_reg (i, r);
5213 /* Initialize all the tables needed to allocate reload registers.
5214 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5215 is the array we use to restore the reg_rtx field for every reload. */
5218 choose_reload_regs_init (chain, save_reload_reg_rtx)
5219 struct insn_chain *chain;
5220 rtx *save_reload_reg_rtx;
5224 for (i = 0; i < n_reloads; i++)
5225 rld[i].reg_rtx = save_reload_reg_rtx[i];
5227 memset (reload_inherited, 0, MAX_RELOADS);
5228 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5229 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5231 CLEAR_HARD_REG_SET (reload_reg_used);
5232 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5233 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5238 CLEAR_HARD_REG_SET (reg_used_in_insn);
5241 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5242 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5243 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5244 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5245 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5246 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5249 for (i = 0; i < reload_n_operands; i++)
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5259 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5261 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5263 for (i = 0; i < n_reloads; i++)
5264 /* If we have already decided to use a certain register,
5265 don't use it in another way. */
5267 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5268 rld[i].when_needed, rld[i].mode);
5271 /* Assign hard reg targets for the pseudo-registers we must reload
5272 into hard regs for this insn.
5273 Also output the instructions to copy them in and out of the hard regs.
5275 For machines with register classes, we are responsible for
5276 finding a reload reg in the proper class. */
5279 choose_reload_regs (chain)
5280 struct insn_chain *chain;
5282 rtx insn = chain->insn;
5284 unsigned int max_group_size = 1;
5285 enum reg_class group_class = NO_REGS;
5286 int pass, win, inheritance;
5288 rtx save_reload_reg_rtx[MAX_RELOADS];
5290 /* In order to be certain of getting the registers we need,
5291 we must sort the reloads into order of increasing register class.
5292 Then our grabbing of reload registers will parallel the process
5293 that provided the reload registers.
5295 Also note whether any of the reloads wants a consecutive group of regs.
5296 If so, record the maximum size of the group desired and what
5297 register class contains all the groups needed by this insn. */
5299 for (j = 0; j < n_reloads; j++)
5301 reload_order[j] = j;
5302 reload_spill_index[j] = -1;
5304 if (rld[j].nregs > 1)
5306 max_group_size = MAX (rld[j].nregs, max_group_size);
5308 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5311 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5315 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5317 /* If -O, try first with inheritance, then turning it off.
5318 If not -O, don't do inheritance.
5319 Using inheritance when not optimizing leads to paradoxes
5320 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5321 because one side of the comparison might be inherited. */
5323 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5325 choose_reload_regs_init (chain, save_reload_reg_rtx);
5327 /* Process the reloads in order of preference just found.
5328 Beyond this point, subregs can be found in reload_reg_rtx.
5330 This used to look for an existing reloaded home for all of the
5331 reloads, and only then perform any new reloads. But that could lose
5332 if the reloads were done out of reg-class order because a later
5333 reload with a looser constraint might have an old home in a register
5334 needed by an earlier reload with a tighter constraint.
5336 To solve this, we make two passes over the reloads, in the order
5337 described above. In the first pass we try to inherit a reload
5338 from a previous insn. If there is a later reload that needs a
5339 class that is a proper subset of the class being processed, we must
5340 also allocate a spill register during the first pass.
5342 Then make a second pass over the reloads to allocate any reloads
5343 that haven't been given registers yet. */
5345 for (j = 0; j < n_reloads; j++)
5347 register int r = reload_order[j];
5348 rtx search_equiv = NULL_RTX;
5350 /* Ignore reloads that got marked inoperative. */
5351 if (rld[r].out == 0 && rld[r].in == 0
5352 && ! rld[r].secondary_p)
5355 /* If find_reloads chose to use reload_in or reload_out as a reload
5356 register, we don't need to chose one. Otherwise, try even if it
5357 found one since we might save an insn if we find the value lying
5359 Try also when reload_in is a pseudo without a hard reg. */
5360 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5361 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5362 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5363 && GET_CODE (rld[r].in) != MEM
5364 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5367 #if 0 /* No longer needed for correct operation.
5368 It might give better code, or might not; worth an experiment? */
5369 /* If this is an optional reload, we can't inherit from earlier insns
5370 until we are sure that any non-optional reloads have been allocated.
5371 The following code takes advantage of the fact that optional reloads
5372 are at the end of reload_order. */
5373 if (rld[r].optional != 0)
5374 for (i = 0; i < j; i++)
5375 if ((rld[reload_order[i]].out != 0
5376 || rld[reload_order[i]].in != 0
5377 || rld[reload_order[i]].secondary_p)
5378 && ! rld[reload_order[i]].optional
5379 && rld[reload_order[i]].reg_rtx == 0)
5380 allocate_reload_reg (chain, reload_order[i], 0);
5383 /* First see if this pseudo is already available as reloaded
5384 for a previous insn. We cannot try to inherit for reloads
5385 that are smaller than the maximum number of registers needed
5386 for groups unless the register we would allocate cannot be used
5389 We could check here to see if this is a secondary reload for
5390 an object that is already in a register of the desired class.
5391 This would avoid the need for the secondary reload register.
5392 But this is complex because we can't easily determine what
5393 objects might want to be loaded via this reload. So let a
5394 register be allocated here. In `emit_reload_insns' we suppress
5395 one of the loads in the case described above. */
5400 register int regno = -1;
5401 enum machine_mode mode = VOIDmode;
5405 else if (GET_CODE (rld[r].in) == REG)
5407 regno = REGNO (rld[r].in);
5408 mode = GET_MODE (rld[r].in);
5410 else if (GET_CODE (rld[r].in_reg) == REG)
5412 regno = REGNO (rld[r].in_reg);
5413 mode = GET_MODE (rld[r].in_reg);
5415 else if (GET_CODE (rld[r].in_reg) == SUBREG
5416 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5418 word = SUBREG_WORD (rld[r].in_reg);
5419 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5420 if (regno < FIRST_PSEUDO_REGISTER)
5422 mode = GET_MODE (rld[r].in_reg);
5425 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5426 || GET_CODE (rld[r].in_reg) == PRE_DEC
5427 || GET_CODE (rld[r].in_reg) == POST_INC
5428 || GET_CODE (rld[r].in_reg) == POST_DEC)
5429 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5431 regno = REGNO (XEXP (rld[r].in_reg, 0));
5432 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5433 rld[r].out = rld[r].in;
5437 /* This won't work, since REGNO can be a pseudo reg number.
5438 Also, it takes much more hair to keep track of all the things
5439 that can invalidate an inherited reload of part of a pseudoreg. */
5440 else if (GET_CODE (rld[r].in) == SUBREG
5441 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5442 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5445 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5447 enum reg_class class = rld[r].class, last_class;
5448 rtx last_reg = reg_last_reload_reg[regno];
5449 enum machine_mode need_mode;
5451 i = REGNO (last_reg) + word;
5452 last_class = REGNO_REG_CLASS (i);
5458 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5459 + word * UNITS_PER_WORD,
5460 GET_MODE_CLASS (mode));
5463 #ifdef CLASS_CANNOT_CHANGE_MODE
5465 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5466 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5468 : (GET_MODE_SIZE (GET_MODE (last_reg))
5469 >= GET_MODE_SIZE (need_mode)))
5471 (GET_MODE_SIZE (GET_MODE (last_reg))
5472 >= GET_MODE_SIZE (need_mode))
5474 && reg_reloaded_contents[i] == regno
5475 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5476 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5477 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5478 /* Even if we can't use this register as a reload
5479 register, we might use it for reload_override_in,
5480 if copying it to the desired class is cheap
5482 || ((REGISTER_MOVE_COST (mode, last_class, class)
5483 < MEMORY_MOVE_COST (mode, class, 1))
5484 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5485 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5489 #ifdef SECONDARY_MEMORY_NEEDED
5490 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5495 && (rld[r].nregs == max_group_size
5496 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5498 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5499 rld[r].when_needed, rld[r].in,
5502 /* If a group is needed, verify that all the subsequent
5503 registers still have their values intact. */
5504 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5507 for (k = 1; k < nr; k++)
5508 if (reg_reloaded_contents[i + k] != regno
5509 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5516 last_reg = (GET_MODE (last_reg) == mode
5517 ? last_reg : gen_rtx_REG (mode, i));
5519 /* We found a register that contains the
5520 value we need. If this register is the
5521 same as an `earlyclobber' operand of the
5522 current insn, just mark it as a place to
5523 reload from since we can't use it as the
5524 reload register itself. */
5526 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5527 if (reg_overlap_mentioned_for_reload_p
5528 (reg_last_reload_reg[regno],
5529 reload_earlyclobbers[i1]))
5532 if (i1 != n_earlyclobbers
5533 || ! (free_for_value_p (i, rld[r].mode,
5535 rld[r].when_needed, rld[r].in,
5537 /* Don't use it if we'd clobber a pseudo reg. */
5538 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5540 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5541 /* Don't clobber the frame pointer. */
5542 || (i == HARD_FRAME_POINTER_REGNUM
5544 /* Don't really use the inherited spill reg
5545 if we need it wider than we've got it. */
5546 || (GET_MODE_SIZE (rld[r].mode)
5547 > GET_MODE_SIZE (mode))
5548 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5551 /* If find_reloads chose reload_out as reload
5552 register, stay with it - that leaves the
5553 inherited register for subsequent reloads. */
5554 || (rld[r].out && rld[r].reg_rtx
5555 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5557 if (! rld[r].optional)
5559 reload_override_in[r] = last_reg;
5560 reload_inheritance_insn[r]
5561 = reg_reloaded_insn[i];
5567 /* We can use this as a reload reg. */
5568 /* Mark the register as in use for this part of
5570 mark_reload_reg_in_use (i,
5574 rld[r].reg_rtx = last_reg;
5575 reload_inherited[r] = 1;
5576 reload_inheritance_insn[r]
5577 = reg_reloaded_insn[i];
5578 reload_spill_index[r] = i;
5579 for (k = 0; k < nr; k++)
5580 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5588 /* Here's another way to see if the value is already lying around. */
5591 && ! reload_inherited[r]
5593 && (CONSTANT_P (rld[r].in)
5594 || GET_CODE (rld[r].in) == PLUS
5595 || GET_CODE (rld[r].in) == REG
5596 || GET_CODE (rld[r].in) == MEM)
5597 && (rld[r].nregs == max_group_size
5598 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5599 search_equiv = rld[r].in;
5600 /* If this is an output reload from a simple move insn, look
5601 if an equivalence for the input is available. */
5602 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5604 rtx set = single_set (insn);
5607 && rtx_equal_p (rld[r].out, SET_DEST (set))
5608 && CONSTANT_P (SET_SRC (set)))
5609 search_equiv = SET_SRC (set);
5615 = find_equiv_reg (search_equiv, insn, rld[r].class,
5616 -1, NULL_PTR, 0, rld[r].mode);
5621 if (GET_CODE (equiv) == REG)
5622 regno = REGNO (equiv);
5623 else if (GET_CODE (equiv) == SUBREG)
5625 /* This must be a SUBREG of a hard register.
5626 Make a new REG since this might be used in an
5627 address and not all machines support SUBREGs
5629 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5630 equiv = gen_rtx_REG (rld[r].mode, regno);
5636 /* If we found a spill reg, reject it unless it is free
5637 and of the desired class. */
5639 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5640 && ! free_for_value_p (regno, rld[r].mode,
5641 rld[r].opnum, rld[r].when_needed,
5642 rld[r].in, rld[r].out, r, 1))
5643 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5647 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5650 /* We found a register that contains the value we need.
5651 If this register is the same as an `earlyclobber' operand
5652 of the current insn, just mark it as a place to reload from
5653 since we can't use it as the reload register itself. */
5656 for (i = 0; i < n_earlyclobbers; i++)
5657 if (reg_overlap_mentioned_for_reload_p (equiv,
5658 reload_earlyclobbers[i]))
5660 if (! rld[r].optional)
5661 reload_override_in[r] = equiv;
5666 /* If the equiv register we have found is explicitly clobbered
5667 in the current insn, it depends on the reload type if we
5668 can use it, use it for reload_override_in, or not at all.
5669 In particular, we then can't use EQUIV for a
5670 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5674 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5675 switch (rld[r].when_needed)
5677 case RELOAD_FOR_OTHER_ADDRESS:
5678 case RELOAD_FOR_INPADDR_ADDRESS:
5679 case RELOAD_FOR_INPUT_ADDRESS:
5680 case RELOAD_FOR_OPADDR_ADDR:
5683 case RELOAD_FOR_INPUT:
5684 case RELOAD_FOR_OPERAND_ADDRESS:
5685 if (! rld[r].optional)
5686 reload_override_in[r] = equiv;
5692 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5693 switch (rld[r].when_needed)
5695 case RELOAD_FOR_OTHER_ADDRESS:
5696 case RELOAD_FOR_INPADDR_ADDRESS:
5697 case RELOAD_FOR_INPUT_ADDRESS:
5698 case RELOAD_FOR_OPADDR_ADDR:
5699 case RELOAD_FOR_OPERAND_ADDRESS:
5700 case RELOAD_FOR_INPUT:
5703 if (! rld[r].optional)
5704 reload_override_in[r] = equiv;
5712 /* If we found an equivalent reg, say no code need be generated
5713 to load it, and use it as our reload reg. */
5714 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5716 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5718 rld[r].reg_rtx = equiv;
5719 reload_inherited[r] = 1;
5721 /* If reg_reloaded_valid is not set for this register,
5722 there might be a stale spill_reg_store lying around.
5723 We must clear it, since otherwise emit_reload_insns
5724 might delete the store. */
5725 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5726 spill_reg_store[regno] = NULL_RTX;
5727 /* If any of the hard registers in EQUIV are spill
5728 registers, mark them as in use for this insn. */
5729 for (k = 0; k < nr; k++)
5731 i = spill_reg_order[regno + k];
5734 mark_reload_reg_in_use (regno, rld[r].opnum,
5737 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5744 /* If we found a register to use already, or if this is an optional
5745 reload, we are done. */
5746 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5750 /* No longer needed for correct operation. Might or might
5751 not give better code on the average. Want to experiment? */
5753 /* See if there is a later reload that has a class different from our
5754 class that intersects our class or that requires less register
5755 than our reload. If so, we must allocate a register to this
5756 reload now, since that reload might inherit a previous reload
5757 and take the only available register in our class. Don't do this
5758 for optional reloads since they will force all previous reloads
5759 to be allocated. Also don't do this for reloads that have been
5762 for (i = j + 1; i < n_reloads; i++)
5764 int s = reload_order[i];
5766 if ((rld[s].in == 0 && rld[s].out == 0
5767 && ! rld[s].secondary_p)
5771 if ((rld[s].class != rld[r].class
5772 && reg_classes_intersect_p (rld[r].class,
5774 || rld[s].nregs < rld[r].nregs)
5781 allocate_reload_reg (chain, r, j == n_reloads - 1);
5785 /* Now allocate reload registers for anything non-optional that
5786 didn't get one yet. */
5787 for (j = 0; j < n_reloads; j++)
5789 register int r = reload_order[j];
5791 /* Ignore reloads that got marked inoperative. */
5792 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5795 /* Skip reloads that already have a register allocated or are
5797 if (rld[r].reg_rtx != 0 || rld[r].optional)
5800 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5804 /* If that loop got all the way, we have won. */
5811 /* Loop around and try without any inheritance. */
5816 /* First undo everything done by the failed attempt
5817 to allocate with inheritance. */
5818 choose_reload_regs_init (chain, save_reload_reg_rtx);
5820 /* Some sanity tests to verify that the reloads found in the first
5821 pass are identical to the ones we have now. */
5822 if (chain->n_reloads != n_reloads)
5825 for (i = 0; i < n_reloads; i++)
5827 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5829 if (chain->rld[i].when_needed != rld[i].when_needed)
5831 for (j = 0; j < n_spills; j++)
5832 if (spill_regs[j] == chain->rld[i].regno)
5833 if (! set_reload_reg (j, i))
5834 failed_reload (chain->insn, i);
5838 /* If we thought we could inherit a reload, because it seemed that
5839 nothing else wanted the same reload register earlier in the insn,
5840 verify that assumption, now that all reloads have been assigned.
5841 Likewise for reloads where reload_override_in has been set. */
5843 /* If doing expensive optimizations, do one preliminary pass that doesn't
5844 cancel any inheritance, but removes reloads that have been needed only
5845 for reloads that we know can be inherited. */
5846 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5848 for (j = 0; j < n_reloads; j++)
5850 register int r = reload_order[j];
5852 if (reload_inherited[r] && rld[r].reg_rtx)
5853 check_reg = rld[r].reg_rtx;
5854 else if (reload_override_in[r]
5855 && (GET_CODE (reload_override_in[r]) == REG
5856 || GET_CODE (reload_override_in[r]) == SUBREG))
5857 check_reg = reload_override_in[r];
5860 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5861 rld[r].opnum, rld[r].when_needed, rld[r].in,
5862 (reload_inherited[r]
5863 ? rld[r].out : const0_rtx),
5868 reload_inherited[r] = 0;
5869 reload_override_in[r] = 0;
5871 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5872 reload_override_in, then we do not need its related
5873 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5874 likewise for other reload types.
5875 We handle this by removing a reload when its only replacement
5876 is mentioned in reload_in of the reload we are going to inherit.
5877 A special case are auto_inc expressions; even if the input is
5878 inherited, we still need the address for the output. We can
5879 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5880 If we suceeded removing some reload and we are doing a preliminary
5881 pass just to remove such reloads, make another pass, since the
5882 removal of one reload might allow us to inherit another one. */
5884 && rld[r].out != rld[r].in
5885 && remove_address_replacements (rld[r].in) && pass)
5890 /* Now that reload_override_in is known valid,
5891 actually override reload_in. */
5892 for (j = 0; j < n_reloads; j++)
5893 if (reload_override_in[j])
5894 rld[j].in = reload_override_in[j];
5896 /* If this reload won't be done because it has been cancelled or is
5897 optional and not inherited, clear reload_reg_rtx so other
5898 routines (such as subst_reloads) don't get confused. */
5899 for (j = 0; j < n_reloads; j++)
5900 if (rld[j].reg_rtx != 0
5901 && ((rld[j].optional && ! reload_inherited[j])
5902 || (rld[j].in == 0 && rld[j].out == 0
5903 && ! rld[j].secondary_p)))
5905 int regno = true_regnum (rld[j].reg_rtx);
5907 if (spill_reg_order[regno] >= 0)
5908 clear_reload_reg_in_use (regno, rld[j].opnum,
5909 rld[j].when_needed, rld[j].mode);
5911 reload_spill_index[j] = -1;
5914 /* Record which pseudos and which spill regs have output reloads. */
5915 for (j = 0; j < n_reloads; j++)
5917 register int r = reload_order[j];
5919 i = reload_spill_index[r];
5921 /* I is nonneg if this reload uses a register.
5922 If rld[r].reg_rtx is 0, this is an optional reload
5923 that we opted to ignore. */
5924 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5925 && rld[r].reg_rtx != 0)
5927 register int nregno = REGNO (rld[r].out_reg);
5930 if (nregno < FIRST_PSEUDO_REGISTER)
5931 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5934 reg_has_output_reload[nregno + nr] = 1;
5938 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5940 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5943 if (rld[r].when_needed != RELOAD_OTHER
5944 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5945 && rld[r].when_needed != RELOAD_FOR_INSN)
5951 /* Deallocate the reload register for reload R. This is called from
5952 remove_address_replacements. */
5955 deallocate_reload_reg (r)
5960 if (! rld[r].reg_rtx)
5962 regno = true_regnum (rld[r].reg_rtx);
5964 if (spill_reg_order[regno] >= 0)
5965 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5967 reload_spill_index[r] = -1;
5970 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5971 reloads of the same item for fear that we might not have enough reload
5972 registers. However, normally they will get the same reload register
5973 and hence actually need not be loaded twice.
5975 Here we check for the most common case of this phenomenon: when we have
5976 a number of reloads for the same object, each of which were allocated
5977 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5978 reload, and is not modified in the insn itself. If we find such,
5979 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5980 This will not increase the number of spill registers needed and will
5981 prevent redundant code. */
5984 merge_assigned_reloads (insn)
5989 /* Scan all the reloads looking for ones that only load values and
5990 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5991 assigned and not modified by INSN. */
5993 for (i = 0; i < n_reloads; i++)
5995 int conflicting_input = 0;
5996 int max_input_address_opnum = -1;
5997 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5999 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6000 || rld[i].out != 0 || rld[i].reg_rtx == 0
6001 || reg_set_p (rld[i].reg_rtx, insn))
6004 /* Look at all other reloads. Ensure that the only use of this
6005 reload_reg_rtx is in a reload that just loads the same value
6006 as we do. Note that any secondary reloads must be of the identical
6007 class since the values, modes, and result registers are the
6008 same, so we need not do anything with any secondary reloads. */
6010 for (j = 0; j < n_reloads; j++)
6012 if (i == j || rld[j].reg_rtx == 0
6013 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6017 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6018 && rld[j].opnum > max_input_address_opnum)
6019 max_input_address_opnum = rld[j].opnum;
6021 /* If the reload regs aren't exactly the same (e.g, different modes)
6022 or if the values are different, we can't merge this reload.
6023 But if it is an input reload, we might still merge
6024 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6026 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6027 || rld[j].out != 0 || rld[j].in == 0
6028 || ! rtx_equal_p (rld[i].in, rld[j].in))
6030 if (rld[j].when_needed != RELOAD_FOR_INPUT
6031 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6032 || rld[i].opnum > rld[j].opnum)
6033 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6035 conflicting_input = 1;
6036 if (min_conflicting_input_opnum > rld[j].opnum)
6037 min_conflicting_input_opnum = rld[j].opnum;
6041 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6042 we, in fact, found any matching reloads. */
6045 && max_input_address_opnum <= min_conflicting_input_opnum)
6047 for (j = 0; j < n_reloads; j++)
6048 if (i != j && rld[j].reg_rtx != 0
6049 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6050 && (! conflicting_input
6051 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6052 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6054 rld[i].when_needed = RELOAD_OTHER;
6056 reload_spill_index[j] = -1;
6057 transfer_replacements (i, j);
6060 /* If this is now RELOAD_OTHER, look for any reloads that load
6061 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6062 if they were for inputs, RELOAD_OTHER for outputs. Note that
6063 this test is equivalent to looking for reloads for this operand
6066 if (rld[i].when_needed == RELOAD_OTHER)
6067 for (j = 0; j < n_reloads; j++)
6069 && rld[i].when_needed != RELOAD_OTHER
6070 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6073 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6074 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6075 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6080 /* These arrays are filled by emit_reload_insns and its subroutines. */
6081 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6082 static rtx other_input_address_reload_insns = 0;
6083 static rtx other_input_reload_insns = 0;
6084 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6085 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6086 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6088 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx operand_reload_insns = 0;
6090 static rtx other_operand_reload_insns = 0;
6091 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6093 /* Values to be put in spill_reg_store are put here first. */
6094 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6095 static HARD_REG_SET reg_reloaded_died;
6097 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6098 has the number J. OLD contains the value to be used as input. */
6101 emit_input_reload_insns (chain, rl, old, j)
6102 struct insn_chain *chain;
6107 rtx insn = chain->insn;
6108 register rtx reloadreg = rl->reg_rtx;
6109 rtx oldequiv_reg = 0;
6112 enum machine_mode mode;
6115 /* Determine the mode to reload in.
6116 This is very tricky because we have three to choose from.
6117 There is the mode the insn operand wants (rl->inmode).
6118 There is the mode of the reload register RELOADREG.
6119 There is the intrinsic mode of the operand, which we could find
6120 by stripping some SUBREGs.
6121 It turns out that RELOADREG's mode is irrelevant:
6122 we can change that arbitrarily.
6124 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6125 then the reload reg may not support QImode moves, so use SImode.
6126 If foo is in memory due to spilling a pseudo reg, this is safe,
6127 because the QImode value is in the least significant part of a
6128 slot big enough for a SImode. If foo is some other sort of
6129 memory reference, then it is impossible to reload this case,
6130 so previous passes had better make sure this never happens.
6132 Then consider a one-word union which has SImode and one of its
6133 members is a float, being fetched as (SUBREG:SF union:SI).
6134 We must fetch that as SFmode because we could be loading into
6135 a float-only register. In this case OLD's mode is correct.
6137 Consider an immediate integer: it has VOIDmode. Here we need
6138 to get a mode from something else.
6140 In some cases, there is a fourth mode, the operand's
6141 containing mode. If the insn specifies a containing mode for
6142 this operand, it overrides all others.
6144 I am not sure whether the algorithm here is always right,
6145 but it does the right things in those cases. */
6147 mode = GET_MODE (old);
6148 if (mode == VOIDmode)
6151 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6152 /* If we need a secondary register for this operation, see if
6153 the value is already in a register in that class. Don't
6154 do this if the secondary register will be used as a scratch
6157 if (rl->secondary_in_reload >= 0
6158 && rl->secondary_in_icode == CODE_FOR_nothing
6161 = find_equiv_reg (old, insn,
6162 rld[rl->secondary_in_reload].class,
6163 -1, NULL_PTR, 0, mode);
6166 /* If reloading from memory, see if there is a register
6167 that already holds the same value. If so, reload from there.
6168 We can pass 0 as the reload_reg_p argument because
6169 any other reload has either already been emitted,
6170 in which case find_equiv_reg will see the reload-insn,
6171 or has yet to be emitted, in which case it doesn't matter
6172 because we will use this equiv reg right away. */
6174 if (oldequiv == 0 && optimize
6175 && (GET_CODE (old) == MEM
6176 || (GET_CODE (old) == REG
6177 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6178 && reg_renumber[REGNO (old)] < 0)))
6179 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6180 -1, NULL_PTR, 0, mode);
6184 unsigned int regno = true_regnum (oldequiv);
6186 /* Don't use OLDEQUIV if any other reload changes it at an
6187 earlier stage of this insn or at this stage. */
6188 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6189 rl->in, const0_rtx, j, 0))
6192 /* If it is no cheaper to copy from OLDEQUIV into the
6193 reload register than it would be to move from memory,
6194 don't use it. Likewise, if we need a secondary register
6198 && ((REGNO_REG_CLASS (regno) != rl->class
6199 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6201 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6202 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6203 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6207 #ifdef SECONDARY_MEMORY_NEEDED
6208 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6216 /* delete_output_reload is only invoked properly if old contains
6217 the original pseudo register. Since this is replaced with a
6218 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6219 find the pseudo in RELOAD_IN_REG. */
6221 && reload_override_in[j]
6222 && GET_CODE (rl->in_reg) == REG)
6229 else if (GET_CODE (oldequiv) == REG)
6230 oldequiv_reg = oldequiv;
6231 else if (GET_CODE (oldequiv) == SUBREG)
6232 oldequiv_reg = SUBREG_REG (oldequiv);
6234 /* If we are reloading from a register that was recently stored in
6235 with an output-reload, see if we can prove there was
6236 actually no need to store the old value in it. */
6238 if (optimize && GET_CODE (oldequiv) == REG
6239 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6240 && spill_reg_store[REGNO (oldequiv)]
6241 && GET_CODE (old) == REG
6242 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6243 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6245 delete_output_reload (insn, j, REGNO (oldequiv));
6247 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6248 then load RELOADREG from OLDEQUIV. Note that we cannot use
6249 gen_lowpart_common since it can do the wrong thing when
6250 RELOADREG has a multi-word mode. Note that RELOADREG
6251 must always be a REG here. */
6253 if (GET_MODE (reloadreg) != mode)
6254 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6255 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6256 oldequiv = SUBREG_REG (oldequiv);
6257 if (GET_MODE (oldequiv) != VOIDmode
6258 && mode != GET_MODE (oldequiv))
6259 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6261 /* Switch to the right place to emit the reload insns. */
6262 switch (rl->when_needed)
6265 where = &other_input_reload_insns;
6267 case RELOAD_FOR_INPUT:
6268 where = &input_reload_insns[rl->opnum];
6270 case RELOAD_FOR_INPUT_ADDRESS:
6271 where = &input_address_reload_insns[rl->opnum];
6273 case RELOAD_FOR_INPADDR_ADDRESS:
6274 where = &inpaddr_address_reload_insns[rl->opnum];
6276 case RELOAD_FOR_OUTPUT_ADDRESS:
6277 where = &output_address_reload_insns[rl->opnum];
6279 case RELOAD_FOR_OUTADDR_ADDRESS:
6280 where = &outaddr_address_reload_insns[rl->opnum];
6282 case RELOAD_FOR_OPERAND_ADDRESS:
6283 where = &operand_reload_insns;
6285 case RELOAD_FOR_OPADDR_ADDR:
6286 where = &other_operand_reload_insns;
6288 case RELOAD_FOR_OTHER_ADDRESS:
6289 where = &other_input_address_reload_insns;
6295 push_to_sequence (*where);
6297 /* Auto-increment addresses must be reloaded in a special way. */
6298 if (rl->out && ! rl->out_reg)
6300 /* We are not going to bother supporting the case where a
6301 incremented register can't be copied directly from
6302 OLDEQUIV since this seems highly unlikely. */
6303 if (rl->secondary_in_reload >= 0)
6306 if (reload_inherited[j])
6307 oldequiv = reloadreg;
6309 old = XEXP (rl->in_reg, 0);
6311 if (optimize && GET_CODE (oldequiv) == REG
6312 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6313 && spill_reg_store[REGNO (oldequiv)]
6314 && GET_CODE (old) == REG
6315 && (dead_or_set_p (insn,
6316 spill_reg_stored_to[REGNO (oldequiv)])
6317 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6319 delete_output_reload (insn, j, REGNO (oldequiv));
6321 /* Prevent normal processing of this reload. */
6323 /* Output a special code sequence for this case. */
6324 new_spill_reg_store[REGNO (reloadreg)]
6325 = inc_for_reload (reloadreg, oldequiv, rl->out,
6329 /* If we are reloading a pseudo-register that was set by the previous
6330 insn, see if we can get rid of that pseudo-register entirely
6331 by redirecting the previous insn into our reload register. */
6333 else if (optimize && GET_CODE (old) == REG
6334 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6335 && dead_or_set_p (insn, old)
6336 /* This is unsafe if some other reload
6337 uses the same reg first. */
6338 && ! conflicts_with_override (reloadreg)
6339 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6340 rl->when_needed, old, rl->out, j, 0))
6342 rtx temp = PREV_INSN (insn);
6343 while (temp && GET_CODE (temp) == NOTE)
6344 temp = PREV_INSN (temp);
6346 && GET_CODE (temp) == INSN
6347 && GET_CODE (PATTERN (temp)) == SET
6348 && SET_DEST (PATTERN (temp)) == old
6349 /* Make sure we can access insn_operand_constraint. */
6350 && asm_noperands (PATTERN (temp)) < 0
6351 /* This is unsafe if prev insn rejects our reload reg. */
6352 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6354 /* This is unsafe if operand occurs more than once in current
6355 insn. Perhaps some occurrences aren't reloaded. */
6356 && count_occurrences (PATTERN (insn), old, 0) == 1
6357 /* Don't risk splitting a matching pair of operands. */
6358 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6360 /* Store into the reload register instead of the pseudo. */
6361 SET_DEST (PATTERN (temp)) = reloadreg;
6363 /* If the previous insn is an output reload, the source is
6364 a reload register, and its spill_reg_store entry will
6365 contain the previous destination. This is now
6367 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6368 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6370 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6371 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6374 /* If these are the only uses of the pseudo reg,
6375 pretend for GDB it lives in the reload reg we used. */
6376 if (REG_N_DEATHS (REGNO (old)) == 1
6377 && REG_N_SETS (REGNO (old)) == 1)
6379 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6380 alter_reg (REGNO (old), -1);
6386 /* We can't do that, so output an insn to load RELOADREG. */
6388 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6389 /* If we have a secondary reload, pick up the secondary register
6390 and icode, if any. If OLDEQUIV and OLD are different or
6391 if this is an in-out reload, recompute whether or not we
6392 still need a secondary register and what the icode should
6393 be. If we still need a secondary register and the class or
6394 icode is different, go back to reloading from OLD if using
6395 OLDEQUIV means that we got the wrong type of register. We
6396 cannot have different class or icode due to an in-out reload
6397 because we don't make such reloads when both the input and
6398 output need secondary reload registers. */
6400 if (! special && rl->secondary_in_reload >= 0)
6402 rtx second_reload_reg = 0;
6403 int secondary_reload = rl->secondary_in_reload;
6404 rtx real_oldequiv = oldequiv;
6407 enum insn_code icode;
6409 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6410 and similarly for OLD.
6411 See comments in get_secondary_reload in reload.c. */
6412 /* If it is a pseudo that cannot be replaced with its
6413 equivalent MEM, we must fall back to reload_in, which
6414 will have all the necessary substitutions registered.
6415 Likewise for a pseudo that can't be replaced with its
6416 equivalent constant.
6418 Take extra care for subregs of such pseudos. Note that
6419 we cannot use reg_equiv_mem in this case because it is
6420 not in the right mode. */
6423 if (GET_CODE (tmp) == SUBREG)
6424 tmp = SUBREG_REG (tmp);
6425 if (GET_CODE (tmp) == REG
6426 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6427 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6428 || reg_equiv_constant[REGNO (tmp)] != 0))
6430 if (! reg_equiv_mem[REGNO (tmp)]
6431 || num_not_at_initial_offset
6432 || GET_CODE (oldequiv) == SUBREG)
6433 real_oldequiv = rl->in;
6435 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6439 if (GET_CODE (tmp) == SUBREG)
6440 tmp = SUBREG_REG (tmp);
6441 if (GET_CODE (tmp) == REG
6442 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6443 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6444 || reg_equiv_constant[REGNO (tmp)] != 0))
6446 if (! reg_equiv_mem[REGNO (tmp)]
6447 || num_not_at_initial_offset
6448 || GET_CODE (old) == SUBREG)
6451 real_old = reg_equiv_mem[REGNO (tmp)];
6454 second_reload_reg = rld[secondary_reload].reg_rtx;
6455 icode = rl->secondary_in_icode;
6457 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6458 || (rl->in != 0 && rl->out != 0))
6460 enum reg_class new_class
6461 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6462 mode, real_oldequiv);
6464 if (new_class == NO_REGS)
6465 second_reload_reg = 0;
6468 enum insn_code new_icode;
6469 enum machine_mode new_mode;
6471 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6472 REGNO (second_reload_reg)))
6473 oldequiv = old, real_oldequiv = real_old;
6476 new_icode = reload_in_optab[(int) mode];
6477 if (new_icode != CODE_FOR_nothing
6478 && ((insn_data[(int) new_icode].operand[0].predicate
6479 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6481 || (insn_data[(int) new_icode].operand[1].predicate
6482 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6483 (real_oldequiv, mode)))))
6484 new_icode = CODE_FOR_nothing;
6486 if (new_icode == CODE_FOR_nothing)
6489 new_mode = insn_data[(int) new_icode].operand[2].mode;
6491 if (GET_MODE (second_reload_reg) != new_mode)
6493 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6495 oldequiv = old, real_oldequiv = real_old;
6498 = gen_rtx_REG (new_mode,
6499 REGNO (second_reload_reg));
6505 /* If we still need a secondary reload register, check
6506 to see if it is being used as a scratch or intermediate
6507 register and generate code appropriately. If we need
6508 a scratch register, use REAL_OLDEQUIV since the form of
6509 the insn may depend on the actual address if it is
6512 if (second_reload_reg)
6514 if (icode != CODE_FOR_nothing)
6516 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6517 second_reload_reg));
6522 /* See if we need a scratch register to load the
6523 intermediate register (a tertiary reload). */
6524 enum insn_code tertiary_icode
6525 = rld[secondary_reload].secondary_in_icode;
6527 if (tertiary_icode != CODE_FOR_nothing)
6529 rtx third_reload_reg
6530 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6532 emit_insn ((GEN_FCN (tertiary_icode)
6533 (second_reload_reg, real_oldequiv,
6534 third_reload_reg)));
6537 gen_reload (second_reload_reg, real_oldequiv,
6541 oldequiv = second_reload_reg;
6547 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6549 rtx real_oldequiv = oldequiv;
6551 if ((GET_CODE (oldequiv) == REG
6552 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6553 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6554 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6555 || (GET_CODE (oldequiv) == SUBREG
6556 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6557 && (REGNO (SUBREG_REG (oldequiv))
6558 >= FIRST_PSEUDO_REGISTER)
6559 && ((reg_equiv_memory_loc
6560 [REGNO (SUBREG_REG (oldequiv))] != 0)
6561 || (reg_equiv_constant
6562 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6563 || (CONSTANT_P (oldequiv)
6564 && PREFERRED_RELOAD_CLASS (oldequiv,
6565 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6566 real_oldequiv = rl->in;
6567 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6571 /* End this sequence. */
6572 *where = get_insns ();
6575 /* Update reload_override_in so that delete_address_reloads_1
6576 can see the actual register usage. */
6578 reload_override_in[j] = oldequiv;
6581 /* Generate insns to for the output reload RL, which is for the insn described
6582 by CHAIN and has the number J. */
6584 emit_output_reload_insns (chain, rl, j)
6585 struct insn_chain *chain;
6589 rtx reloadreg = rl->reg_rtx;
6590 rtx insn = chain->insn;
6593 enum machine_mode mode = GET_MODE (old);
6596 if (rl->when_needed == RELOAD_OTHER)
6599 push_to_sequence (output_reload_insns[rl->opnum]);
6601 /* Determine the mode to reload in.
6602 See comments above (for input reloading). */
6604 if (mode == VOIDmode)
6606 /* VOIDmode should never happen for an output. */
6607 if (asm_noperands (PATTERN (insn)) < 0)
6608 /* It's the compiler's fault. */
6609 fatal_insn ("VOIDmode on an output", insn);
6610 error_for_asm (insn, "output operand is constant in `asm'");
6611 /* Prevent crash--use something we know is valid. */
6613 old = gen_rtx_REG (mode, REGNO (reloadreg));
6616 if (GET_MODE (reloadreg) != mode)
6617 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6619 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6621 /* If we need two reload regs, set RELOADREG to the intermediate
6622 one, since it will be stored into OLD. We might need a secondary
6623 register only for an input reload, so check again here. */
6625 if (rl->secondary_out_reload >= 0)
6629 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6630 && reg_equiv_mem[REGNO (old)] != 0)
6631 real_old = reg_equiv_mem[REGNO (old)];
6633 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6637 rtx second_reloadreg = reloadreg;
6638 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6640 /* See if RELOADREG is to be used as a scratch register
6641 or as an intermediate register. */
6642 if (rl->secondary_out_icode != CODE_FOR_nothing)
6644 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6645 (real_old, second_reloadreg, reloadreg)));
6650 /* See if we need both a scratch and intermediate reload
6653 int secondary_reload = rl->secondary_out_reload;
6654 enum insn_code tertiary_icode
6655 = rld[secondary_reload].secondary_out_icode;
6657 if (GET_MODE (reloadreg) != mode)
6658 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6660 if (tertiary_icode != CODE_FOR_nothing)
6663 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6666 /* Copy primary reload reg to secondary reload reg.
6667 (Note that these have been swapped above, then
6668 secondary reload reg to OLD using our insn. */
6670 /* If REAL_OLD is a paradoxical SUBREG, remove it
6671 and try to put the opposite SUBREG on
6673 if (GET_CODE (real_old) == SUBREG
6674 && (GET_MODE_SIZE (GET_MODE (real_old))
6675 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6676 && 0 != (tem = gen_lowpart_common
6677 (GET_MODE (SUBREG_REG (real_old)),
6679 real_old = SUBREG_REG (real_old), reloadreg = tem;
6681 gen_reload (reloadreg, second_reloadreg,
6682 rl->opnum, rl->when_needed);
6683 emit_insn ((GEN_FCN (tertiary_icode)
6684 (real_old, reloadreg, third_reloadreg)));
6689 /* Copy between the reload regs here and then to
6692 gen_reload (reloadreg, second_reloadreg,
6693 rl->opnum, rl->when_needed);
6699 /* Output the last reload insn. */
6704 /* Don't output the last reload if OLD is not the dest of
6705 INSN and is in the src and is clobbered by INSN. */
6706 if (! flag_expensive_optimizations
6707 || GET_CODE (old) != REG
6708 || !(set = single_set (insn))
6709 || rtx_equal_p (old, SET_DEST (set))
6710 || !reg_mentioned_p (old, SET_SRC (set))
6711 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6712 gen_reload (old, reloadreg, rl->opnum,
6716 /* Look at all insns we emitted, just to be safe. */
6717 for (p = get_insns (); p; p = NEXT_INSN (p))
6720 rtx pat = PATTERN (p);
6722 /* If this output reload doesn't come from a spill reg,
6723 clear any memory of reloaded copies of the pseudo reg.
6724 If this output reload comes from a spill reg,
6725 reg_has_output_reload will make this do nothing. */
6726 note_stores (pat, forget_old_reloads_1, NULL);
6728 if (reg_mentioned_p (rl->reg_rtx, pat))
6730 rtx set = single_set (insn);
6731 if (reload_spill_index[j] < 0
6733 && SET_SRC (set) == rl->reg_rtx)
6735 int src = REGNO (SET_SRC (set));
6737 reload_spill_index[j] = src;
6738 SET_HARD_REG_BIT (reg_is_output_reload, src);
6739 if (find_regno_note (insn, REG_DEAD, src))
6740 SET_HARD_REG_BIT (reg_reloaded_died, src);
6742 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6744 int s = rl->secondary_out_reload;
6745 set = single_set (p);
6746 /* If this reload copies only to the secondary reload
6747 register, the secondary reload does the actual
6749 if (s >= 0 && set == NULL_RTX)
6750 /* We can't tell what function the secondary reload
6751 has and where the actual store to the pseudo is
6752 made; leave new_spill_reg_store alone. */
6755 && SET_SRC (set) == rl->reg_rtx
6756 && SET_DEST (set) == rld[s].reg_rtx)
6758 /* Usually the next instruction will be the
6759 secondary reload insn; if we can confirm
6760 that it is, setting new_spill_reg_store to
6761 that insn will allow an extra optimization. */
6762 rtx s_reg = rld[s].reg_rtx;
6763 rtx next = NEXT_INSN (p);
6764 rld[s].out = rl->out;
6765 rld[s].out_reg = rl->out_reg;
6766 set = single_set (next);
6767 if (set && SET_SRC (set) == s_reg
6768 && ! new_spill_reg_store[REGNO (s_reg)])
6770 SET_HARD_REG_BIT (reg_is_output_reload,
6772 new_spill_reg_store[REGNO (s_reg)] = next;
6776 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6781 if (rl->when_needed == RELOAD_OTHER)
6783 emit_insns (other_output_reload_insns[rl->opnum]);
6784 other_output_reload_insns[rl->opnum] = get_insns ();
6787 output_reload_insns[rl->opnum] = get_insns ();
6792 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6793 and has the number J. */
6795 do_input_reload (chain, rl, j)
6796 struct insn_chain *chain;
6800 int expect_occurrences = 1;
6801 rtx insn = chain->insn;
6802 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6803 ? rl->in_reg : rl->in);
6806 /* AUTO_INC reloads need to be handled even if inherited. We got an
6807 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6808 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6809 && ! rtx_equal_p (rl->reg_rtx, old)
6810 && rl->reg_rtx != 0)
6811 emit_input_reload_insns (chain, rld + j, old, j);
6813 /* When inheriting a wider reload, we have a MEM in rl->in,
6814 e.g. inheriting a SImode output reload for
6815 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6816 if (optimize && reload_inherited[j] && rl->in
6817 && GET_CODE (rl->in) == MEM
6818 && GET_CODE (rl->in_reg) == MEM
6819 && reload_spill_index[j] >= 0
6820 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6823 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6824 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6827 /* If we are reloading a register that was recently stored in with an
6828 output-reload, see if we can prove there was
6829 actually no need to store the old value in it. */
6832 && (reload_inherited[j] || reload_override_in[j])
6834 && GET_CODE (rl->reg_rtx) == REG
6835 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6837 /* There doesn't seem to be any reason to restrict this to pseudos
6838 and doing so loses in the case where we are copying from a
6839 register of the wrong class. */
6840 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6841 >= FIRST_PSEUDO_REGISTER)
6843 /* The insn might have already some references to stackslots
6844 replaced by MEMs, while reload_out_reg still names the
6846 && (dead_or_set_p (insn,
6847 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6848 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6850 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6853 /* Do output reloading for reload RL, which is for the insn described by
6854 CHAIN and has the number J.
6855 ??? At some point we need to support handling output reloads of
6856 JUMP_INSNs or insns that set cc0. */
6858 do_output_reload (chain, rl, j)
6859 struct insn_chain *chain;
6864 rtx insn = chain->insn;
6865 /* If this is an output reload that stores something that is
6866 not loaded in this same reload, see if we can eliminate a previous
6868 rtx pseudo = rl->out_reg;
6871 && GET_CODE (pseudo) == REG
6872 && ! rtx_equal_p (rl->in_reg, pseudo)
6873 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6874 && reg_last_reload_reg[REGNO (pseudo)])
6876 int pseudo_no = REGNO (pseudo);
6877 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6879 /* We don't need to test full validity of last_regno for
6880 inherit here; we only want to know if the store actually
6881 matches the pseudo. */
6882 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6883 && reg_reloaded_contents[last_regno] == pseudo_no
6884 && spill_reg_store[last_regno]
6885 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6886 delete_output_reload (insn, j, last_regno);
6891 || rl->reg_rtx == old
6892 || rl->reg_rtx == 0)
6895 /* An output operand that dies right away does need a reload,
6896 but need not be copied from it. Show the new location in the
6898 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6899 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6901 XEXP (note, 0) = rl->reg_rtx;
6904 /* Likewise for a SUBREG of an operand that dies. */
6905 else if (GET_CODE (old) == SUBREG
6906 && GET_CODE (SUBREG_REG (old)) == REG
6907 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6910 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6914 else if (GET_CODE (old) == SCRATCH)
6915 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6916 but we don't want to make an output reload. */
6919 /* If is a JUMP_INSN, we can't support output reloads yet. */
6920 if (GET_CODE (insn) == JUMP_INSN)
6923 emit_output_reload_insns (chain, rld + j, j);
6926 /* Output insns to reload values in and out of the chosen reload regs. */
6929 emit_reload_insns (chain)
6930 struct insn_chain *chain;
6932 rtx insn = chain->insn;
6935 rtx following_insn = NEXT_INSN (insn);
6936 rtx before_insn = PREV_INSN (insn);
6938 CLEAR_HARD_REG_SET (reg_reloaded_died);
6940 for (j = 0; j < reload_n_operands; j++)
6941 input_reload_insns[j] = input_address_reload_insns[j]
6942 = inpaddr_address_reload_insns[j]
6943 = output_reload_insns[j] = output_address_reload_insns[j]
6944 = outaddr_address_reload_insns[j]
6945 = other_output_reload_insns[j] = 0;
6946 other_input_address_reload_insns = 0;
6947 other_input_reload_insns = 0;
6948 operand_reload_insns = 0;
6949 other_operand_reload_insns = 0;
6951 /* Dump reloads into the dump file. */
6954 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6955 debug_reload_to_stream (rtl_dump_file);
6958 /* Now output the instructions to copy the data into and out of the
6959 reload registers. Do these in the order that the reloads were reported,
6960 since reloads of base and index registers precede reloads of operands
6961 and the operands may need the base and index registers reloaded. */
6963 for (j = 0; j < n_reloads; j++)
6966 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6967 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6969 do_input_reload (chain, rld + j, j);
6970 do_output_reload (chain, rld + j, j);
6973 /* Now write all the insns we made for reloads in the order expected by
6974 the allocation functions. Prior to the insn being reloaded, we write
6975 the following reloads:
6977 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6979 RELOAD_OTHER reloads.
6981 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6982 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6983 RELOAD_FOR_INPUT reload for the operand.
6985 RELOAD_FOR_OPADDR_ADDRS reloads.
6987 RELOAD_FOR_OPERAND_ADDRESS reloads.
6989 After the insn being reloaded, we write the following:
6991 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6992 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6993 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6994 reloads for the operand. The RELOAD_OTHER output reloads are
6995 output in descending order by reload number. */
6997 emit_insns_before (other_input_address_reload_insns, insn);
6998 emit_insns_before (other_input_reload_insns, insn);
7000 for (j = 0; j < reload_n_operands; j++)
7002 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7003 emit_insns_before (input_address_reload_insns[j], insn);
7004 emit_insns_before (input_reload_insns[j], insn);
7007 emit_insns_before (other_operand_reload_insns, insn);
7008 emit_insns_before (operand_reload_insns, insn);
7010 for (j = 0; j < reload_n_operands; j++)
7012 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7013 emit_insns_before (output_address_reload_insns[j], following_insn);
7014 emit_insns_before (output_reload_insns[j], following_insn);
7015 emit_insns_before (other_output_reload_insns[j], following_insn);
7018 /* Keep basic block info up to date. */
7021 if (BLOCK_HEAD (chain->block) == insn)
7022 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7023 if (BLOCK_END (chain->block) == insn)
7024 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7027 /* For all the spill regs newly reloaded in this instruction,
7028 record what they were reloaded from, so subsequent instructions
7029 can inherit the reloads.
7031 Update spill_reg_store for the reloads of this insn.
7032 Copy the elements that were updated in the loop above. */
7034 for (j = 0; j < n_reloads; j++)
7036 register int r = reload_order[j];
7037 register int i = reload_spill_index[r];
7039 /* If this is a non-inherited input reload from a pseudo, we must
7040 clear any memory of a previous store to the same pseudo. Only do
7041 something if there will not be an output reload for the pseudo
7043 if (rld[r].in_reg != 0
7044 && ! (reload_inherited[r] || reload_override_in[r]))
7046 rtx reg = rld[r].in_reg;
7048 if (GET_CODE (reg) == SUBREG)
7049 reg = SUBREG_REG (reg);
7051 if (GET_CODE (reg) == REG
7052 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7053 && ! reg_has_output_reload[REGNO (reg)])
7055 int nregno = REGNO (reg);
7057 if (reg_last_reload_reg[nregno])
7059 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7061 if (reg_reloaded_contents[last_regno] == nregno)
7062 spill_reg_store[last_regno] = 0;
7067 /* I is nonneg if this reload used a register.
7068 If rld[r].reg_rtx is 0, this is an optional reload
7069 that we opted to ignore. */
7071 if (i >= 0 && rld[r].reg_rtx != 0)
7073 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7075 int part_reaches_end = 0;
7076 int all_reaches_end = 1;
7078 /* For a multi register reload, we need to check if all or part
7079 of the value lives to the end. */
7080 for (k = 0; k < nr; k++)
7082 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7083 rld[r].when_needed))
7084 part_reaches_end = 1;
7086 all_reaches_end = 0;
7089 /* Ignore reloads that don't reach the end of the insn in
7091 if (all_reaches_end)
7093 /* First, clear out memory of what used to be in this spill reg.
7094 If consecutive registers are used, clear them all. */
7096 for (k = 0; k < nr; k++)
7097 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7099 /* Maybe the spill reg contains a copy of reload_out. */
7101 && (GET_CODE (rld[r].out) == REG
7105 || GET_CODE (rld[r].out_reg) == REG))
7107 rtx out = (GET_CODE (rld[r].out) == REG
7111 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7112 register int nregno = REGNO (out);
7113 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7114 : HARD_REGNO_NREGS (nregno,
7115 GET_MODE (rld[r].reg_rtx)));
7117 spill_reg_store[i] = new_spill_reg_store[i];
7118 spill_reg_stored_to[i] = out;
7119 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7121 /* If NREGNO is a hard register, it may occupy more than
7122 one register. If it does, say what is in the
7123 rest of the registers assuming that both registers
7124 agree on how many words the object takes. If not,
7125 invalidate the subsequent registers. */
7127 if (nregno < FIRST_PSEUDO_REGISTER)
7128 for (k = 1; k < nnr; k++)
7129 reg_last_reload_reg[nregno + k]
7131 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7132 REGNO (rld[r].reg_rtx) + k)
7135 /* Now do the inverse operation. */
7136 for (k = 0; k < nr; k++)
7138 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7139 reg_reloaded_contents[i + k]
7140 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7143 reg_reloaded_insn[i + k] = insn;
7144 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7148 /* Maybe the spill reg contains a copy of reload_in. Only do
7149 something if there will not be an output reload for
7150 the register being reloaded. */
7151 else if (rld[r].out_reg == 0
7153 && ((GET_CODE (rld[r].in) == REG
7154 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7155 && ! reg_has_output_reload[REGNO (rld[r].in)])
7156 || (GET_CODE (rld[r].in_reg) == REG
7157 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7158 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7160 register int nregno;
7163 if (GET_CODE (rld[r].in) == REG
7164 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7165 nregno = REGNO (rld[r].in);
7166 else if (GET_CODE (rld[r].in_reg) == REG)
7167 nregno = REGNO (rld[r].in_reg);
7169 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7171 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7172 : HARD_REGNO_NREGS (nregno,
7173 GET_MODE (rld[r].reg_rtx)));
7175 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7177 if (nregno < FIRST_PSEUDO_REGISTER)
7178 for (k = 1; k < nnr; k++)
7179 reg_last_reload_reg[nregno + k]
7181 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7182 REGNO (rld[r].reg_rtx) + k)
7185 /* Unless we inherited this reload, show we haven't
7186 recently done a store.
7187 Previous stores of inherited auto_inc expressions
7188 also have to be discarded. */
7189 if (! reload_inherited[r]
7190 || (rld[r].out && ! rld[r].out_reg))
7191 spill_reg_store[i] = 0;
7193 for (k = 0; k < nr; k++)
7195 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7196 reg_reloaded_contents[i + k]
7197 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7200 reg_reloaded_insn[i + k] = insn;
7201 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7206 /* However, if part of the reload reaches the end, then we must
7207 invalidate the old info for the part that survives to the end. */
7208 else if (part_reaches_end)
7210 for (k = 0; k < nr; k++)
7211 if (reload_reg_reaches_end_p (i + k,
7213 rld[r].when_needed))
7214 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7218 /* The following if-statement was #if 0'd in 1.34 (or before...).
7219 It's reenabled in 1.35 because supposedly nothing else
7220 deals with this problem. */
7222 /* If a register gets output-reloaded from a non-spill register,
7223 that invalidates any previous reloaded copy of it.
7224 But forget_old_reloads_1 won't get to see it, because
7225 it thinks only about the original insn. So invalidate it here. */
7226 if (i < 0 && rld[r].out != 0
7227 && (GET_CODE (rld[r].out) == REG
7228 || (GET_CODE (rld[r].out) == MEM
7229 && GET_CODE (rld[r].out_reg) == REG)))
7231 rtx out = (GET_CODE (rld[r].out) == REG
7232 ? rld[r].out : rld[r].out_reg);
7233 register int nregno = REGNO (out);
7234 if (nregno >= FIRST_PSEUDO_REGISTER)
7236 rtx src_reg, store_insn = NULL_RTX;
7238 reg_last_reload_reg[nregno] = 0;
7240 /* If we can find a hard register that is stored, record
7241 the storing insn so that we may delete this insn with
7242 delete_output_reload. */
7243 src_reg = rld[r].reg_rtx;
7245 /* If this is an optional reload, try to find the source reg
7246 from an input reload. */
7249 rtx set = single_set (insn);
7250 if (set && SET_DEST (set) == rld[r].out)
7254 src_reg = SET_SRC (set);
7256 for (k = 0; k < n_reloads; k++)
7258 if (rld[k].in == src_reg)
7260 src_reg = rld[k].reg_rtx;
7267 store_insn = new_spill_reg_store[REGNO (src_reg)];
7268 if (src_reg && GET_CODE (src_reg) == REG
7269 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7271 int src_regno = REGNO (src_reg);
7272 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7273 /* The place where to find a death note varies with
7274 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7275 necessarily checked exactly in the code that moves
7276 notes, so just check both locations. */
7277 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7279 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7282 spill_reg_store[src_regno + nr] = store_insn;
7283 spill_reg_stored_to[src_regno + nr] = out;
7284 reg_reloaded_contents[src_regno + nr] = nregno;
7285 reg_reloaded_insn[src_regno + nr] = store_insn;
7286 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7287 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7288 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7290 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7292 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7294 reg_last_reload_reg[nregno] = src_reg;
7299 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7301 while (num_regs-- > 0)
7302 reg_last_reload_reg[nregno + num_regs] = 0;
7306 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7309 /* Emit code to perform a reload from IN (which may be a reload register) to
7310 OUT (which may also be a reload register). IN or OUT is from operand
7311 OPNUM with reload type TYPE.
7313 Returns first insn emitted. */
7316 gen_reload (out, in, opnum, type)
7320 enum reload_type type;
7322 rtx last = get_last_insn ();
7325 /* If IN is a paradoxical SUBREG, remove it and try to put the
7326 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7327 if (GET_CODE (in) == SUBREG
7328 && (GET_MODE_SIZE (GET_MODE (in))
7329 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7330 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7331 in = SUBREG_REG (in), out = tem;
7332 else if (GET_CODE (out) == SUBREG
7333 && (GET_MODE_SIZE (GET_MODE (out))
7334 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7335 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7336 out = SUBREG_REG (out), in = tem;
7338 /* How to do this reload can get quite tricky. Normally, we are being
7339 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7340 register that didn't get a hard register. In that case we can just
7341 call emit_move_insn.
7343 We can also be asked to reload a PLUS that adds a register or a MEM to
7344 another register, constant or MEM. This can occur during frame pointer
7345 elimination and while reloading addresses. This case is handled by
7346 trying to emit a single insn to perform the add. If it is not valid,
7347 we use a two insn sequence.
7349 Finally, we could be called to handle an 'o' constraint by putting
7350 an address into a register. In that case, we first try to do this
7351 with a named pattern of "reload_load_address". If no such pattern
7352 exists, we just emit a SET insn and hope for the best (it will normally
7353 be valid on machines that use 'o').
7355 This entire process is made complex because reload will never
7356 process the insns we generate here and so we must ensure that
7357 they will fit their constraints and also by the fact that parts of
7358 IN might be being reloaded separately and replaced with spill registers.
7359 Because of this, we are, in some sense, just guessing the right approach
7360 here. The one listed above seems to work.
7362 ??? At some point, this whole thing needs to be rethought. */
7364 if (GET_CODE (in) == PLUS
7365 && (GET_CODE (XEXP (in, 0)) == REG
7366 || GET_CODE (XEXP (in, 0)) == SUBREG
7367 || GET_CODE (XEXP (in, 0)) == MEM)
7368 && (GET_CODE (XEXP (in, 1)) == REG
7369 || GET_CODE (XEXP (in, 1)) == SUBREG
7370 || CONSTANT_P (XEXP (in, 1))
7371 || GET_CODE (XEXP (in, 1)) == MEM))
7373 /* We need to compute the sum of a register or a MEM and another
7374 register, constant, or MEM, and put it into the reload
7375 register. The best possible way of doing this is if the machine
7376 has a three-operand ADD insn that accepts the required operands.
7378 The simplest approach is to try to generate such an insn and see if it
7379 is recognized and matches its constraints. If so, it can be used.
7381 It might be better not to actually emit the insn unless it is valid,
7382 but we need to pass the insn as an operand to `recog' and
7383 `extract_insn' and it is simpler to emit and then delete the insn if
7384 not valid than to dummy things up. */
7386 rtx op0, op1, tem, insn;
7389 op0 = find_replacement (&XEXP (in, 0));
7390 op1 = find_replacement (&XEXP (in, 1));
7392 /* Since constraint checking is strict, commutativity won't be
7393 checked, so we need to do that here to avoid spurious failure
7394 if the add instruction is two-address and the second operand
7395 of the add is the same as the reload reg, which is frequently
7396 the case. If the insn would be A = B + A, rearrange it so
7397 it will be A = A + B as constrain_operands expects. */
7399 if (GET_CODE (XEXP (in, 1)) == REG
7400 && REGNO (out) == REGNO (XEXP (in, 1)))
7401 tem = op0, op0 = op1, op1 = tem;
7403 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7404 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7406 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7407 code = recog_memoized (insn);
7411 extract_insn (insn);
7412 /* We want constrain operands to treat this insn strictly in
7413 its validity determination, i.e., the way it would after reload
7415 if (constrain_operands (1))
7419 delete_insns_since (last);
7421 /* If that failed, we must use a conservative two-insn sequence.
7423 Use a move to copy one operand into the reload register. Prefer
7424 to reload a constant, MEM or pseudo since the move patterns can
7425 handle an arbitrary operand. If OP1 is not a constant, MEM or
7426 pseudo and OP1 is not a valid operand for an add instruction, then
7429 After reloading one of the operands into the reload register, add
7430 the reload register to the output register.
7432 If there is another way to do this for a specific machine, a
7433 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7436 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7438 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7439 || (GET_CODE (op1) == REG
7440 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7441 || (code != CODE_FOR_nothing
7442 && ! ((*insn_data[code].operand[2].predicate)
7443 (op1, insn_data[code].operand[2].mode))))
7444 tem = op0, op0 = op1, op1 = tem;
7446 gen_reload (out, op0, opnum, type);
7448 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7449 This fixes a problem on the 32K where the stack pointer cannot
7450 be used as an operand of an add insn. */
7452 if (rtx_equal_p (op0, op1))
7455 insn = emit_insn (gen_add2_insn (out, op1));
7457 /* If that failed, copy the address register to the reload register.
7458 Then add the constant to the reload register. */
7460 code = recog_memoized (insn);
7464 extract_insn (insn);
7465 /* We want constrain operands to treat this insn strictly in
7466 its validity determination, i.e., the way it would after reload
7468 if (constrain_operands (1))
7470 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7472 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7477 delete_insns_since (last);
7479 gen_reload (out, op1, opnum, type);
7480 insn = emit_insn (gen_add2_insn (out, op0));
7481 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7484 #ifdef SECONDARY_MEMORY_NEEDED
7485 /* If we need a memory location to do the move, do it that way. */
7486 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7487 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7488 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7489 REGNO_REG_CLASS (REGNO (out)),
7492 /* Get the memory to use and rewrite both registers to its mode. */
7493 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7495 if (GET_MODE (loc) != GET_MODE (out))
7496 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7498 if (GET_MODE (loc) != GET_MODE (in))
7499 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7501 gen_reload (loc, in, opnum, type);
7502 gen_reload (out, loc, opnum, type);
7506 /* If IN is a simple operand, use gen_move_insn. */
7507 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7508 emit_insn (gen_move_insn (out, in));
7510 #ifdef HAVE_reload_load_address
7511 else if (HAVE_reload_load_address)
7512 emit_insn (gen_reload_load_address (out, in));
7515 /* Otherwise, just write (set OUT IN) and hope for the best. */
7517 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7519 /* Return the first insn emitted.
7520 We can not just return get_last_insn, because there may have
7521 been multiple instructions emitted. Also note that gen_move_insn may
7522 emit more than one insn itself, so we can not assume that there is one
7523 insn emitted per emit_insn_before call. */
7525 return last ? NEXT_INSN (last) : get_insns ();
7528 /* Delete a previously made output-reload
7529 whose result we now believe is not needed.
7530 First we double-check.
7532 INSN is the insn now being processed.
7533 LAST_RELOAD_REG is the hard register number for which we want to delete
7534 the last output reload.
7535 J is the reload-number that originally used REG. The caller has made
7536 certain that reload J doesn't use REG any longer for input. */
7539 delete_output_reload (insn, j, last_reload_reg)
7542 int last_reload_reg;
7544 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7545 rtx reg = spill_reg_stored_to[last_reload_reg];
7548 int n_inherited = 0;
7552 /* Get the raw pseudo-register referred to. */
7554 while (GET_CODE (reg) == SUBREG)
7555 reg = SUBREG_REG (reg);
7556 substed = reg_equiv_memory_loc[REGNO (reg)];
7558 /* This is unsafe if the operand occurs more often in the current
7559 insn than it is inherited. */
7560 for (k = n_reloads - 1; k >= 0; k--)
7562 rtx reg2 = rld[k].in;
7565 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7566 reg2 = rld[k].in_reg;
7568 if (rld[k].out && ! rld[k].out_reg)
7569 reg2 = XEXP (rld[k].in_reg, 0);
7571 while (GET_CODE (reg2) == SUBREG)
7572 reg2 = SUBREG_REG (reg2);
7573 if (rtx_equal_p (reg2, reg))
7575 if (reload_inherited[k] || reload_override_in[k] || k == j)
7578 reg2 = rld[k].out_reg;
7581 while (GET_CODE (reg2) == SUBREG)
7582 reg2 = XEXP (reg2, 0);
7583 if (rtx_equal_p (reg2, reg))
7590 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7592 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7593 if (n_occurrences > n_inherited)
7596 /* If the pseudo-reg we are reloading is no longer referenced
7597 anywhere between the store into it and here,
7598 and no jumps or labels intervene, then the value can get
7599 here through the reload reg alone.
7600 Otherwise, give up--return. */
7601 for (i1 = NEXT_INSN (output_reload_insn);
7602 i1 != insn; i1 = NEXT_INSN (i1))
7604 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7606 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7607 && reg_mentioned_p (reg, PATTERN (i1)))
7609 /* If this is USE in front of INSN, we only have to check that
7610 there are no more references than accounted for by inheritance. */
7611 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7613 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7614 i1 = NEXT_INSN (i1);
7616 if (n_occurrences <= n_inherited && i1 == insn)
7622 /* The caller has already checked that REG dies or is set in INSN.
7623 It has also checked that we are optimizing, and thus some inaccurancies
7624 in the debugging information are acceptable.
7625 So we could just delete output_reload_insn.
7626 But in some cases we can improve the debugging information without
7627 sacrificing optimization - maybe even improving the code:
7628 See if the pseudo reg has been completely replaced
7629 with reload regs. If so, delete the store insn
7630 and forget we had a stack slot for the pseudo. */
7631 if (rld[j].out != rld[j].in
7632 && REG_N_DEATHS (REGNO (reg)) == 1
7633 && REG_N_SETS (REGNO (reg)) == 1
7634 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7635 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7639 /* We know that it was used only between here
7640 and the beginning of the current basic block.
7641 (We also know that the last use before INSN was
7642 the output reload we are thinking of deleting, but never mind that.)
7643 Search that range; see if any ref remains. */
7644 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7646 rtx set = single_set (i2);
7648 /* Uses which just store in the pseudo don't count,
7649 since if they are the only uses, they are dead. */
7650 if (set != 0 && SET_DEST (set) == reg)
7652 if (GET_CODE (i2) == CODE_LABEL
7653 || GET_CODE (i2) == JUMP_INSN)
7655 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7656 && reg_mentioned_p (reg, PATTERN (i2)))
7658 /* Some other ref remains; just delete the output reload we
7660 delete_address_reloads (output_reload_insn, insn);
7661 PUT_CODE (output_reload_insn, NOTE);
7662 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7663 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7668 /* Delete the now-dead stores into this pseudo. */
7669 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7671 rtx set = single_set (i2);
7673 if (set != 0 && SET_DEST (set) == reg)
7675 delete_address_reloads (i2, insn);
7676 /* This might be a basic block head,
7677 thus don't use delete_insn. */
7678 PUT_CODE (i2, NOTE);
7679 NOTE_SOURCE_FILE (i2) = 0;
7680 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7682 if (GET_CODE (i2) == CODE_LABEL
7683 || GET_CODE (i2) == JUMP_INSN)
7687 /* For the debugging info,
7688 say the pseudo lives in this reload reg. */
7689 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7690 alter_reg (REGNO (reg), -1);
7692 delete_address_reloads (output_reload_insn, insn);
7693 PUT_CODE (output_reload_insn, NOTE);
7694 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7695 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7699 /* We are going to delete DEAD_INSN. Recursively delete loads of
7700 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7701 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7703 delete_address_reloads (dead_insn, current_insn)
7704 rtx dead_insn, current_insn;
7706 rtx set = single_set (dead_insn);
7707 rtx set2, dst, prev, next;
7710 rtx dst = SET_DEST (set);
7711 if (GET_CODE (dst) == MEM)
7712 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7714 /* If we deleted the store from a reloaded post_{in,de}c expression,
7715 we can delete the matching adds. */
7716 prev = PREV_INSN (dead_insn);
7717 next = NEXT_INSN (dead_insn);
7718 if (! prev || ! next)
7720 set = single_set (next);
7721 set2 = single_set (prev);
7723 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7724 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7725 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7727 dst = SET_DEST (set);
7728 if (! rtx_equal_p (dst, SET_DEST (set2))
7729 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7730 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7731 || (INTVAL (XEXP (SET_SRC (set), 1))
7732 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7738 /* Subfunction of delete_address_reloads: process registers found in X. */
7740 delete_address_reloads_1 (dead_insn, x, current_insn)
7741 rtx dead_insn, x, current_insn;
7743 rtx prev, set, dst, i2;
7745 enum rtx_code code = GET_CODE (x);
7749 const char *fmt = GET_RTX_FORMAT (code);
7750 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7753 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7754 else if (fmt[i] == 'E')
7756 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7757 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7764 if (spill_reg_order[REGNO (x)] < 0)
7767 /* Scan backwards for the insn that sets x. This might be a way back due
7769 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7771 code = GET_CODE (prev);
7772 if (code == CODE_LABEL || code == JUMP_INSN)
7774 if (GET_RTX_CLASS (code) != 'i')
7776 if (reg_set_p (x, PATTERN (prev)))
7778 if (reg_referenced_p (x, PATTERN (prev)))
7781 if (! prev || INSN_UID (prev) < reload_first_uid)
7783 /* Check that PREV only sets the reload register. */
7784 set = single_set (prev);
7787 dst = SET_DEST (set);
7788 if (GET_CODE (dst) != REG
7789 || ! rtx_equal_p (dst, x))
7791 if (! reg_set_p (dst, PATTERN (dead_insn)))
7793 /* Check if DST was used in a later insn -
7794 it might have been inherited. */
7795 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7797 if (GET_CODE (i2) == CODE_LABEL)
7801 if (reg_referenced_p (dst, PATTERN (i2)))
7803 /* If there is a reference to the register in the current insn,
7804 it might be loaded in a non-inherited reload. If no other
7805 reload uses it, that means the register is set before
7807 if (i2 == current_insn)
7809 for (j = n_reloads - 1; j >= 0; j--)
7810 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7811 || reload_override_in[j] == dst)
7813 for (j = n_reloads - 1; j >= 0; j--)
7814 if (rld[j].in && rld[j].reg_rtx == dst)
7821 if (GET_CODE (i2) == JUMP_INSN)
7823 /* If DST is still live at CURRENT_INSN, check if it is used for
7824 any reload. Note that even if CURRENT_INSN sets DST, we still
7825 have to check the reloads. */
7826 if (i2 == current_insn)
7828 for (j = n_reloads - 1; j >= 0; j--)
7829 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7830 || reload_override_in[j] == dst)
7832 /* ??? We can't finish the loop here, because dst might be
7833 allocated to a pseudo in this block if no reload in this
7834 block needs any of the clsses containing DST - see
7835 spill_hard_reg. There is no easy way to tell this, so we
7836 have to scan till the end of the basic block. */
7838 if (reg_set_p (dst, PATTERN (i2)))
7842 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7843 reg_reloaded_contents[REGNO (dst)] = -1;
7844 /* Can't use delete_insn here because PREV might be a basic block head. */
7845 PUT_CODE (prev, NOTE);
7846 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7847 NOTE_SOURCE_FILE (prev) = 0;
7850 /* Output reload-insns to reload VALUE into RELOADREG.
7851 VALUE is an autoincrement or autodecrement RTX whose operand
7852 is a register or memory location;
7853 so reloading involves incrementing that location.
7854 IN is either identical to VALUE, or some cheaper place to reload from.
7856 INC_AMOUNT is the number to increment or decrement by (always positive).
7857 This cannot be deduced from VALUE.
7859 Return the instruction that stores into RELOADREG. */
7862 inc_for_reload (reloadreg, in, value, inc_amount)
7867 /* REG or MEM to be copied and incremented. */
7868 rtx incloc = XEXP (value, 0);
7869 /* Nonzero if increment after copying. */
7870 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7876 rtx real_in = in == value ? XEXP (in, 0) : in;
7878 /* No hard register is equivalent to this register after
7879 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7880 we could inc/dec that register as well (maybe even using it for
7881 the source), but I'm not sure it's worth worrying about. */
7882 if (GET_CODE (incloc) == REG)
7883 reg_last_reload_reg[REGNO (incloc)] = 0;
7885 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7886 inc_amount = -inc_amount;
7888 inc = GEN_INT (inc_amount);
7890 /* If this is post-increment, first copy the location to the reload reg. */
7891 if (post && real_in != reloadreg)
7892 emit_insn (gen_move_insn (reloadreg, real_in));
7896 /* See if we can directly increment INCLOC. Use a method similar to
7897 that in gen_reload. */
7899 last = get_last_insn ();
7900 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7901 gen_rtx_PLUS (GET_MODE (incloc),
7904 code = recog_memoized (add_insn);
7907 extract_insn (add_insn);
7908 if (constrain_operands (1))
7910 /* If this is a pre-increment and we have incremented the value
7911 where it lives, copy the incremented value to RELOADREG to
7912 be used as an address. */
7915 emit_insn (gen_move_insn (reloadreg, incloc));
7920 delete_insns_since (last);
7923 /* If couldn't do the increment directly, must increment in RELOADREG.
7924 The way we do this depends on whether this is pre- or post-increment.
7925 For pre-increment, copy INCLOC to the reload register, increment it
7926 there, then save back. */
7930 if (in != reloadreg)
7931 emit_insn (gen_move_insn (reloadreg, real_in));
7932 emit_insn (gen_add2_insn (reloadreg, inc));
7933 store = emit_insn (gen_move_insn (incloc, reloadreg));
7938 Because this might be a jump insn or a compare, and because RELOADREG
7939 may not be available after the insn in an input reload, we must do
7940 the incrementation before the insn being reloaded for.
7942 We have already copied IN to RELOADREG. Increment the copy in
7943 RELOADREG, save that back, then decrement RELOADREG so it has
7944 the original value. */
7946 emit_insn (gen_add2_insn (reloadreg, inc));
7947 store = emit_insn (gen_move_insn (incloc, reloadreg));
7948 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7954 /* Return 1 if we are certain that the constraint-string STRING allows
7955 the hard register REG. Return 0 if we can't be sure of this. */
7958 constraint_accepts_reg_p (string, reg)
7963 int regno = true_regnum (reg);
7966 /* Initialize for first alternative. */
7968 /* Check that each alternative contains `g' or `r'. */
7970 switch (c = *string++)
7973 /* If an alternative lacks `g' or `r', we lose. */
7976 /* If an alternative lacks `g' or `r', we lose. */
7979 /* Initialize for next alternative. */
7984 /* Any general reg wins for this alternative. */
7985 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7989 /* Any reg in specified class wins for this alternative. */
7991 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7993 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7999 /* INSN is a no-op; delete it.
8000 If this sets the return value of the function, we must keep a USE around,
8001 in case this is in a different basic block than the final USE. Otherwise,
8002 we could loose important register lifeness information on
8003 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8004 spills: subsequent passes assume that spill registers are dead at the end
8006 VALUE must be the return value in such a case, NULL otherwise. */
8008 reload_cse_delete_noop_set (insn, value)
8013 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8014 INSN_CODE (insn) = -1;
8015 REG_NOTES (insn) = NULL_RTX;
8019 PUT_CODE (insn, NOTE);
8020 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8021 NOTE_SOURCE_FILE (insn) = 0;
8025 /* See whether a single set SET is a noop. */
8027 reload_cse_noop_set_p (set)
8030 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8033 /* Try to simplify INSN. */
8035 reload_cse_simplify (insn)
8038 rtx body = PATTERN (insn);
8040 if (GET_CODE (body) == SET)
8043 if (reload_cse_noop_set_p (body))
8045 rtx value = SET_DEST (body);
8046 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8048 reload_cse_delete_noop_set (insn, value);
8052 /* It's not a no-op, but we can try to simplify it. */
8053 count += reload_cse_simplify_set (body, insn);
8056 apply_change_group ();
8058 reload_cse_simplify_operands (insn);
8060 else if (GET_CODE (body) == PARALLEL)
8064 rtx value = NULL_RTX;
8066 /* If every action in a PARALLEL is a noop, we can delete
8067 the entire PARALLEL. */
8068 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8070 rtx part = XVECEXP (body, 0, i);
8071 if (GET_CODE (part) == SET)
8073 if (! reload_cse_noop_set_p (part))
8075 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8079 value = SET_DEST (part);
8082 else if (GET_CODE (part) != CLOBBER)
8088 reload_cse_delete_noop_set (insn, value);
8089 /* We're done with this insn. */
8093 /* It's not a no-op, but we can try to simplify it. */
8094 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8095 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8096 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8099 apply_change_group ();
8101 reload_cse_simplify_operands (insn);
8105 /* Do a very simple CSE pass over the hard registers.
8107 This function detects no-op moves where we happened to assign two
8108 different pseudo-registers to the same hard register, and then
8109 copied one to the other. Reload will generate a useless
8110 instruction copying a register to itself.
8112 This function also detects cases where we load a value from memory
8113 into two different registers, and (if memory is more expensive than
8114 registers) changes it to simply copy the first register into the
8117 Another optimization is performed that scans the operands of each
8118 instruction to see whether the value is already available in a
8119 hard register. It then replaces the operand with the hard register
8120 if possible, much like an optional reload would. */
8123 reload_cse_regs_1 (first)
8129 init_alias_analysis ();
8131 for (insn = first; insn; insn = NEXT_INSN (insn))
8134 reload_cse_simplify (insn);
8136 cselib_process_insn (insn);
8140 end_alias_analysis ();
8144 /* Call cse / combine like post-reload optimization phases.
8145 FIRST is the first instruction. */
8147 reload_cse_regs (first)
8150 reload_cse_regs_1 (first);
8152 reload_cse_move2add (first);
8153 if (flag_expensive_optimizations)
8154 reload_cse_regs_1 (first);
8157 /* Try to simplify a single SET instruction. SET is the set pattern.
8158 INSN is the instruction it came from.
8159 This function only handles one case: if we set a register to a value
8160 which is not a register, we try to find that value in some other register
8161 and change the set into a register copy. */
8164 reload_cse_simplify_set (set, insn)
8171 enum reg_class dclass;
8174 struct elt_loc_list *l;
8176 dreg = true_regnum (SET_DEST (set));
8180 src = SET_SRC (set);
8181 if (side_effects_p (src) || true_regnum (src) >= 0)
8184 dclass = REGNO_REG_CLASS (dreg);
8186 /* If memory loads are cheaper than register copies, don't change them. */
8187 if (GET_CODE (src) == MEM)
8188 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8189 else if (CONSTANT_P (src))
8190 old_cost = rtx_cost (src, SET);
8191 else if (GET_CODE (src) == REG)
8192 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8193 REGNO_REG_CLASS (REGNO (src)), dclass);
8196 old_cost = rtx_cost (src, SET);
8198 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8201 for (l = val->locs; l; l = l->next)
8204 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8205 this_cost = rtx_cost (l->loc, SET);
8206 else if (GET_CODE (l->loc) == REG)
8207 this_cost = REGISTER_MOVE_COST (GET_MODE (l->loc),
8208 REGNO_REG_CLASS (REGNO (l->loc)),
8212 /* If equal costs, prefer registers over anything else. That tends to
8213 lead to smaller instructions on some machines. */
8214 if ((this_cost < old_cost
8215 || (this_cost == old_cost
8216 && GET_CODE (l->loc) == REG
8217 && GET_CODE (SET_SRC (set)) != REG))
8218 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8219 old_cost = this_cost, did_change = 1;
8225 /* Try to replace operands in INSN with equivalent values that are already
8226 in registers. This can be viewed as optional reloading.
8228 For each non-register operand in the insn, see if any hard regs are
8229 known to be equivalent to that operand. Record the alternatives which
8230 can accept these hard registers. Among all alternatives, select the
8231 ones which are better or equal to the one currently matching, where
8232 "better" is in terms of '?' and '!' constraints. Among the remaining
8233 alternatives, select the one which replaces most operands with
8237 reload_cse_simplify_operands (insn)
8242 /* For each operand, all registers that are equivalent to it. */
8243 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8245 const char *constraints[MAX_RECOG_OPERANDS];
8247 /* Vector recording how bad an alternative is. */
8248 int *alternative_reject;
8249 /* Vector recording how many registers can be introduced by choosing
8250 this alternative. */
8251 int *alternative_nregs;
8252 /* Array of vectors recording, for each operand and each alternative,
8253 which hard register to substitute, or -1 if the operand should be
8255 int *op_alt_regno[MAX_RECOG_OPERANDS];
8256 /* Array of alternatives, sorted in order of decreasing desirability. */
8257 int *alternative_order;
8258 rtx reg = gen_rtx_REG (VOIDmode, -1);
8260 extract_insn (insn);
8262 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8265 /* Figure out which alternative currently matches. */
8266 if (! constrain_operands (1))
8267 fatal_insn_not_found (insn);
8269 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8270 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8271 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8272 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8273 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8275 /* For each operand, find out which regs are equivalent. */
8276 for (i = 0; i < recog_data.n_operands; i++)
8279 struct elt_loc_list *l;
8281 CLEAR_HARD_REG_SET (equiv_regs[i]);
8283 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8284 right, so avoid the problem here. Likewise if we have a constant
8285 and the insn pattern doesn't tell us the mode we need. */
8286 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8287 || (CONSTANT_P (recog_data.operand[i])
8288 && recog_data.operand_mode[i] == VOIDmode))
8291 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8295 for (l = v->locs; l; l = l->next)
8296 if (GET_CODE (l->loc) == REG)
8297 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8300 for (i = 0; i < recog_data.n_operands; i++)
8302 enum machine_mode mode;
8306 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8307 for (j = 0; j < recog_data.n_alternatives; j++)
8308 op_alt_regno[i][j] = -1;
8310 p = constraints[i] = recog_data.constraints[i];
8311 mode = recog_data.operand_mode[i];
8313 /* Add the reject values for each alternative given by the constraints
8314 for this operand. */
8322 alternative_reject[j] += 3;
8324 alternative_reject[j] += 300;
8327 /* We won't change operands which are already registers. We
8328 also don't want to modify output operands. */
8329 regno = true_regnum (recog_data.operand[i]);
8331 || constraints[i][0] == '='
8332 || constraints[i][0] == '+')
8335 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8337 int class = (int) NO_REGS;
8339 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8342 REGNO (reg) = regno;
8343 PUT_MODE (reg, mode);
8345 /* We found a register equal to this operand. Now look for all
8346 alternatives that can accept this register and have not been
8347 assigned a register they can use yet. */
8356 case '=': case '+': case '?':
8357 case '#': case '&': case '!':
8359 case '0': case '1': case '2': case '3': case '4':
8360 case '5': case '6': case '7': case '8': case '9':
8361 case 'm': case '<': case '>': case 'V': case 'o':
8362 case 'E': case 'F': case 'G': case 'H':
8363 case 's': case 'i': case 'n':
8364 case 'I': case 'J': case 'K': case 'L':
8365 case 'M': case 'N': case 'O': case 'P':
8367 /* These don't say anything we care about. */
8371 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8376 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8379 case ',': case '\0':
8380 /* See if REGNO fits this alternative, and set it up as the
8381 replacement register if we don't have one for this
8382 alternative yet and the operand being replaced is not
8383 a cheap CONST_INT. */
8384 if (op_alt_regno[i][j] == -1
8385 && reg_fits_class_p (reg, class, 0, mode)
8386 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8387 || (rtx_cost (recog_data.operand[i], SET)
8388 > rtx_cost (reg, SET))))
8390 alternative_nregs[j]++;
8391 op_alt_regno[i][j] = regno;
8403 /* Record all alternatives which are better or equal to the currently
8404 matching one in the alternative_order array. */
8405 for (i = j = 0; i < recog_data.n_alternatives; i++)
8406 if (alternative_reject[i] <= alternative_reject[which_alternative])
8407 alternative_order[j++] = i;
8408 recog_data.n_alternatives = j;
8410 /* Sort it. Given a small number of alternatives, a dumb algorithm
8411 won't hurt too much. */
8412 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8415 int best_reject = alternative_reject[alternative_order[i]];
8416 int best_nregs = alternative_nregs[alternative_order[i]];
8419 for (j = i + 1; j < recog_data.n_alternatives; j++)
8421 int this_reject = alternative_reject[alternative_order[j]];
8422 int this_nregs = alternative_nregs[alternative_order[j]];
8424 if (this_reject < best_reject
8425 || (this_reject == best_reject && this_nregs < best_nregs))
8428 best_reject = this_reject;
8429 best_nregs = this_nregs;
8433 tmp = alternative_order[best];
8434 alternative_order[best] = alternative_order[i];
8435 alternative_order[i] = tmp;
8438 /* Substitute the operands as determined by op_alt_regno for the best
8440 j = alternative_order[0];
8442 for (i = 0; i < recog_data.n_operands; i++)
8444 enum machine_mode mode = recog_data.operand_mode[i];
8445 if (op_alt_regno[i][j] == -1)
8448 validate_change (insn, recog_data.operand_loc[i],
8449 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8452 for (i = recog_data.n_dups - 1; i >= 0; i--)
8454 int op = recog_data.dup_num[i];
8455 enum machine_mode mode = recog_data.operand_mode[op];
8457 if (op_alt_regno[op][j] == -1)
8460 validate_change (insn, recog_data.dup_loc[i],
8461 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8464 return apply_change_group ();
8467 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8469 This code might also be useful when reload gave up on reg+reg addresssing
8470 because of clashes between the return register and INDEX_REG_CLASS. */
8472 /* The maximum number of uses of a register we can keep track of to
8473 replace them with reg+reg addressing. */
8474 #define RELOAD_COMBINE_MAX_USES 6
8476 /* INSN is the insn where a register has ben used, and USEP points to the
8477 location of the register within the rtl. */
8478 struct reg_use { rtx insn, *usep; };
8480 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8481 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8482 indicates where it becomes live again.
8483 Otherwise, USE_INDEX is the index of the last encountered use of the
8484 register (which is first among these we have seen since we scan backwards),
8485 OFFSET contains the constant offset that is added to the register in
8486 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8487 last, of these uses.
8488 STORE_RUID is always meaningful if we only want to use a value in a
8489 register in a different place: it denotes the next insn in the insn
8490 stream (i.e. the last ecountered) that sets or clobbers the register. */
8493 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8498 } reg_state[FIRST_PSEUDO_REGISTER];
8500 /* Reverse linear uid. This is increased in reload_combine while scanning
8501 the instructions from last to first. It is used to set last_label_ruid
8502 and the store_ruid / use_ruid fields in reg_state. */
8503 static int reload_combine_ruid;
8505 #define LABEL_LIVE(LABEL) \
8506 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8512 int first_index_reg = -1, last_index_reg;
8515 int last_label_ruid;
8516 int min_labelno, n_labels;
8517 HARD_REG_SET ever_live_at_start, *label_live;
8519 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8520 reload has already used it where appropriate, so there is no use in
8521 trying to generate it now. */
8522 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8525 /* To avoid wasting too much time later searching for an index register,
8526 determine the minimum and maximum index register numbers. */
8527 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8528 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8530 if (first_index_reg == -1)
8531 first_index_reg = r;
8536 /* If no index register is available, we can quit now. */
8537 if (first_index_reg == -1)
8540 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8541 information is a bit fuzzy immediately after reload, but it's
8542 still good enough to determine which registers are live at a jump
8544 min_labelno = get_first_label_num ();
8545 n_labels = max_label_num () - min_labelno;
8546 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8547 CLEAR_HARD_REG_SET (ever_live_at_start);
8549 for (i = n_basic_blocks - 1; i >= 0; i--)
8551 insn = BLOCK_HEAD (i);
8552 if (GET_CODE (insn) == CODE_LABEL)
8556 REG_SET_TO_HARD_REG_SET (live,
8557 BASIC_BLOCK (i)->global_live_at_start);
8558 compute_use_by_pseudos (&live,
8559 BASIC_BLOCK (i)->global_live_at_start);
8560 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8561 IOR_HARD_REG_SET (ever_live_at_start, live);
8565 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8566 last_label_ruid = reload_combine_ruid = 0;
8567 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8569 reg_state[r].store_ruid = reload_combine_ruid;
8571 reg_state[r].use_index = -1;
8573 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8576 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8580 /* We cannot do our optimization across labels. Invalidating all the use
8581 information we have would be costly, so we just note where the label
8582 is and then later disable any optimization that would cross it. */
8583 if (GET_CODE (insn) == CODE_LABEL)
8584 last_label_ruid = reload_combine_ruid;
8585 else if (GET_CODE (insn) == BARRIER)
8586 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8587 if (! fixed_regs[r])
8588 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8590 if (! INSN_P (insn))
8593 reload_combine_ruid++;
8595 /* Look for (set (REGX) (CONST_INT))
8596 (set (REGX) (PLUS (REGX) (REGY)))
8598 ... (MEM (REGX)) ...
8600 (set (REGZ) (CONST_INT))
8602 ... (MEM (PLUS (REGZ) (REGY)))... .
8604 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8605 and that we know all uses of REGX before it dies. */
8606 set = single_set (insn);
8608 && GET_CODE (SET_DEST (set)) == REG
8609 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8610 GET_MODE (SET_DEST (set)))
8612 && GET_CODE (SET_SRC (set)) == PLUS
8613 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8614 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8615 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8617 rtx reg = SET_DEST (set);
8618 rtx plus = SET_SRC (set);
8619 rtx base = XEXP (plus, 1);
8620 rtx prev = prev_nonnote_insn (insn);
8621 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8622 unsigned int regno = REGNO (reg);
8623 rtx const_reg = NULL_RTX;
8624 rtx reg_sum = NULL_RTX;
8626 /* Now, we need an index register.
8627 We'll set index_reg to this index register, const_reg to the
8628 register that is to be loaded with the constant
8629 (denoted as REGZ in the substitution illustration above),
8630 and reg_sum to the register-register that we want to use to
8631 substitute uses of REG (typically in MEMs) with.
8632 First check REG and BASE for being index registers;
8633 we can use them even if they are not dead. */
8634 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8635 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8643 /* Otherwise, look for a free index register. Since we have
8644 checked above that neiter REG nor BASE are index registers,
8645 if we find anything at all, it will be different from these
8647 for (i = first_index_reg; i <= last_index_reg; i++)
8649 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8651 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8652 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8653 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8655 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8657 const_reg = index_reg;
8658 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8664 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8665 (REGY), i.e. BASE, is not clobbered before the last use we'll
8668 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8669 && rtx_equal_p (SET_DEST (prev_set), reg)
8670 && reg_state[regno].use_index >= 0
8671 && (reg_state[REGNO (base)].store_ruid
8672 <= reg_state[regno].use_ruid)
8677 /* Change destination register and, if necessary, the
8678 constant value in PREV, the constant loading instruction. */
8679 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8680 if (reg_state[regno].offset != const0_rtx)
8681 validate_change (prev,
8682 &SET_SRC (prev_set),
8683 GEN_INT (INTVAL (SET_SRC (prev_set))
8684 + INTVAL (reg_state[regno].offset)),
8687 /* Now for every use of REG that we have recorded, replace REG
8689 for (i = reg_state[regno].use_index;
8690 i < RELOAD_COMBINE_MAX_USES; i++)
8691 validate_change (reg_state[regno].reg_use[i].insn,
8692 reg_state[regno].reg_use[i].usep,
8695 if (apply_change_group ())
8699 /* Delete the reg-reg addition. */
8700 PUT_CODE (insn, NOTE);
8701 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8702 NOTE_SOURCE_FILE (insn) = 0;
8704 if (reg_state[regno].offset != const0_rtx)
8705 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8707 for (np = ®_NOTES (prev); *np;)
8709 if (REG_NOTE_KIND (*np) == REG_EQUAL
8710 || REG_NOTE_KIND (*np) == REG_EQUIV)
8711 *np = XEXP (*np, 1);
8713 np = &XEXP (*np, 1);
8716 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8717 reg_state[REGNO (const_reg)].store_ruid
8718 = reload_combine_ruid;
8724 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8726 if (GET_CODE (insn) == CALL_INSN)
8730 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8731 if (call_used_regs[r])
8733 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8734 reg_state[r].store_ruid = reload_combine_ruid;
8737 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8738 link = XEXP (link, 1))
8740 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8741 if (GET_CODE (usage_rtx) == REG)
8744 unsigned int start_reg = REGNO (usage_rtx);
8745 unsigned int num_regs =
8746 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8747 unsigned int end_reg = start_reg + num_regs - 1;
8748 for (i = start_reg; i <= end_reg; i++)
8749 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8751 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8752 reg_state[i].store_ruid = reload_combine_ruid;
8755 reg_state[i].use_index = -1;
8760 else if (GET_CODE (insn) == JUMP_INSN
8761 && GET_CODE (PATTERN (insn)) != RETURN)
8763 /* Non-spill registers might be used at the call destination in
8764 some unknown fashion, so we have to mark the unknown use. */
8767 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8768 && JUMP_LABEL (insn))
8769 live = &LABEL_LIVE (JUMP_LABEL (insn));
8771 live = &ever_live_at_start;
8773 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8774 if (TEST_HARD_REG_BIT (*live, i))
8775 reg_state[i].use_index = -1;
8778 reload_combine_note_use (&PATTERN (insn), insn);
8779 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8781 if (REG_NOTE_KIND (note) == REG_INC
8782 && GET_CODE (XEXP (note, 0)) == REG)
8784 int regno = REGNO (XEXP (note, 0));
8786 reg_state[regno].store_ruid = reload_combine_ruid;
8787 reg_state[regno].use_index = -1;
8795 /* Check if DST is a register or a subreg of a register; if it is,
8796 update reg_state[regno].store_ruid and reg_state[regno].use_index
8797 accordingly. Called via note_stores from reload_combine. */
8800 reload_combine_note_store (dst, set, data)
8802 void *data ATTRIBUTE_UNUSED;
8806 enum machine_mode mode = GET_MODE (dst);
8808 if (GET_CODE (dst) == SUBREG)
8810 regno = SUBREG_WORD (dst);
8811 dst = SUBREG_REG (dst);
8813 if (GET_CODE (dst) != REG)
8815 regno += REGNO (dst);
8817 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8818 careful with registers / register parts that are not full words.
8820 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8821 if (GET_CODE (set) != SET
8822 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8823 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8824 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8826 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8828 reg_state[i].use_index = -1;
8829 reg_state[i].store_ruid = reload_combine_ruid;
8834 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8836 reg_state[i].store_ruid = reload_combine_ruid;
8837 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8842 /* XP points to a piece of rtl that has to be checked for any uses of
8844 *XP is the pattern of INSN, or a part of it.
8845 Called from reload_combine, and recursively by itself. */
8847 reload_combine_note_use (xp, insn)
8851 enum rtx_code code = x->code;
8854 rtx offset = const0_rtx; /* For the REG case below. */
8859 if (GET_CODE (SET_DEST (x)) == REG)
8861 reload_combine_note_use (&SET_SRC (x), insn);
8867 /* If this is the USE of a return value, we can't change it. */
8868 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8870 /* Mark the return register as used in an unknown fashion. */
8871 rtx reg = XEXP (x, 0);
8872 int regno = REGNO (reg);
8873 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8875 while (--nregs >= 0)
8876 reg_state[regno + nregs].use_index = -1;
8882 if (GET_CODE (SET_DEST (x)) == REG)
8887 /* We are interested in (plus (reg) (const_int)) . */
8888 if (GET_CODE (XEXP (x, 0)) != REG
8889 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8891 offset = XEXP (x, 1);
8896 int regno = REGNO (x);
8900 /* Some spurious USEs of pseudo registers might remain.
8901 Just ignore them. */
8902 if (regno >= FIRST_PSEUDO_REGISTER)
8905 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8907 /* We can't substitute into multi-hard-reg uses. */
8910 while (--nregs >= 0)
8911 reg_state[regno + nregs].use_index = -1;
8915 /* If this register is already used in some unknown fashion, we
8917 If we decrement the index from zero to -1, we can't store more
8918 uses, so this register becomes used in an unknown fashion. */
8919 use_index = --reg_state[regno].use_index;
8923 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8925 /* We have found another use for a register that is already
8926 used later. Check if the offsets match; if not, mark the
8927 register as used in an unknown fashion. */
8928 if (! rtx_equal_p (offset, reg_state[regno].offset))
8930 reg_state[regno].use_index = -1;
8936 /* This is the first use of this register we have seen since we
8937 marked it as dead. */
8938 reg_state[regno].offset = offset;
8939 reg_state[regno].use_ruid = reload_combine_ruid;
8941 reg_state[regno].reg_use[use_index].insn = insn;
8942 reg_state[regno].reg_use[use_index].usep = xp;
8950 /* Recursively process the components of X. */
8951 fmt = GET_RTX_FORMAT (code);
8952 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8955 reload_combine_note_use (&XEXP (x, i), insn);
8956 else if (fmt[i] == 'E')
8958 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8959 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8964 /* See if we can reduce the cost of a constant by replacing a move
8965 with an add. We track situations in which a register is set to a
8966 constant or to a register plus a constant. */
8967 /* We cannot do our optimization across labels. Invalidating all the
8968 information about register contents we have would be costly, so we
8969 use move2add_last_label_luid to note where the label is and then
8970 later disable any optimization that would cross it.
8971 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8972 reg_set_luid[n] is greater than last_label_luid[n] . */
8973 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8975 /* If reg_base_reg[n] is negative, register n has been set to
8976 reg_offset[n] in mode reg_mode[n] .
8977 If reg_base_reg[n] is non-negative, register n has been set to the
8978 sum of reg_offset[n] and the value of register reg_base_reg[n]
8979 before reg_set_luid[n], calculated in mode reg_mode[n] . */
8980 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
8981 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8982 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8984 /* move2add_luid is linearily increased while scanning the instructions
8985 from first to last. It is used to set reg_set_luid in
8986 reload_cse_move2add and move2add_note_store. */
8987 static int move2add_luid;
8989 /* move2add_last_label_luid is set whenever a label is found. Labels
8990 invalidate all previously collected reg_offset data. */
8991 static int move2add_last_label_luid;
8993 /* Generate a CONST_INT and force it in the range of MODE. */
8995 static HOST_WIDE_INT
8996 sext_for_mode (mode, value)
8997 enum machine_mode mode;
8998 HOST_WIDE_INT value;
9000 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9001 int width = GET_MODE_BITSIZE (mode);
9003 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9005 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9006 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9007 cval |= (HOST_WIDE_INT) -1 << width;
9012 /* ??? We don't know how zero / sign extension is handled, hence we
9013 can't go from a narrower to a wider mode. */
9014 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9015 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9016 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9017 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9018 GET_MODE_BITSIZE (INMODE))))
9021 reload_cse_move2add (first)
9027 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9028 reg_set_luid[i] = 0;
9030 move2add_last_label_luid = 0;
9032 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9036 if (GET_CODE (insn) == CODE_LABEL)
9038 move2add_last_label_luid = move2add_luid;
9039 /* We're going to increment move2add_luid twice after a
9040 label, so that we can use move2add_last_label_luid + 1 as
9041 the luid for constants. */
9045 if (! INSN_P (insn))
9047 pat = PATTERN (insn);
9048 /* For simplicity, we only perform this optimization on
9049 straightforward SETs. */
9050 if (GET_CODE (pat) == SET
9051 && GET_CODE (SET_DEST (pat)) == REG)
9053 rtx reg = SET_DEST (pat);
9054 int regno = REGNO (reg);
9055 rtx src = SET_SRC (pat);
9057 /* Check if we have valid information on the contents of this
9058 register in the mode of REG. */
9059 if (reg_set_luid[regno] > move2add_last_label_luid
9060 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9062 /* Try to transform (set (REGX) (CONST_INT A))
9064 (set (REGX) (CONST_INT B))
9066 (set (REGX) (CONST_INT A))
9068 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9070 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9073 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9075 - reg_offset[regno]));
9076 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9077 use (set (reg) (reg)) instead.
9078 We don't delete this insn, nor do we convert it into a
9079 note, to avoid losing register notes or the return
9080 value flag. jump2 already knowns how to get rid of
9082 if (new_src == const0_rtx)
9083 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9084 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9085 && have_add2_insn (GET_MODE (reg)))
9086 success = validate_change (insn, &PATTERN (insn),
9087 gen_add2_insn (reg, new_src), 0);
9088 reg_set_luid[regno] = move2add_luid;
9089 reg_mode[regno] = GET_MODE (reg);
9090 reg_offset[regno] = INTVAL (src);
9094 /* Try to transform (set (REGX) (REGY))
9095 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9098 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9101 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9103 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9104 else if (GET_CODE (src) == REG
9105 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9106 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9107 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9108 reg_mode[REGNO (src)]))
9110 rtx next = next_nonnote_insn (insn);
9113 set = single_set (next);
9115 && SET_DEST (set) == reg
9116 && GET_CODE (SET_SRC (set)) == PLUS
9117 && XEXP (SET_SRC (set), 0) == reg
9118 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9120 rtx src3 = XEXP (SET_SRC (set), 1);
9121 HOST_WIDE_INT added_offset = INTVAL (src3);
9122 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9123 HOST_WIDE_INT regno_offset = reg_offset[regno];
9124 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9130 if (new_src == const0_rtx)
9131 /* See above why we create (set (reg) (reg)) here. */
9133 = validate_change (next, &SET_SRC (set), reg, 0);
9134 else if ((rtx_cost (new_src, PLUS)
9135 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9136 && have_add2_insn (GET_MODE (reg)))
9138 = validate_change (next, &PATTERN (next),
9139 gen_add2_insn (reg, new_src), 0);
9142 /* INSN might be the first insn in a basic block
9143 if the preceding insn is a conditional jump
9144 or a possible-throwing call. */
9145 PUT_CODE (insn, NOTE);
9146 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9147 NOTE_SOURCE_FILE (insn) = 0;
9150 reg_mode[regno] = GET_MODE (reg);
9151 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9160 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9162 if (REG_NOTE_KIND (note) == REG_INC
9163 && GET_CODE (XEXP (note, 0)) == REG)
9165 /* Reset the information about this register. */
9166 int regno = REGNO (XEXP (note, 0));
9167 if (regno < FIRST_PSEUDO_REGISTER)
9168 reg_set_luid[regno] = 0;
9171 note_stores (PATTERN (insn), move2add_note_store, NULL);
9172 /* If this is a CALL_INSN, all call used registers are stored with
9174 if (GET_CODE (insn) == CALL_INSN)
9176 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9178 if (call_used_regs[i])
9179 /* Reset the information about this register. */
9180 reg_set_luid[i] = 0;
9186 /* SET is a SET or CLOBBER that sets DST.
9187 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9188 Called from reload_cse_move2add via note_stores. */
9191 move2add_note_store (dst, set, data)
9193 void *data ATTRIBUTE_UNUSED;
9195 unsigned int regno = 0;
9197 enum machine_mode mode = GET_MODE (dst);
9199 if (GET_CODE (dst) == SUBREG)
9201 regno = SUBREG_WORD (dst);
9202 dst = SUBREG_REG (dst);
9205 /* Some targets do argument pushes without adding REG_INC notes. */
9207 if (GET_CODE (dst) == MEM)
9209 dst = XEXP (dst, 0);
9210 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9211 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9212 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9215 if (GET_CODE (dst) != REG)
9218 regno += REGNO (dst);
9220 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9221 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9222 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9223 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9225 rtx src = SET_SRC (set);
9227 HOST_WIDE_INT offset;
9229 /* This may be different from mode, if SET_DEST (set) is a
9231 enum machine_mode dst_mode = GET_MODE (dst);
9233 switch (GET_CODE (src))
9236 if (GET_CODE (XEXP (src, 0)) == REG)
9238 base_reg = XEXP (src, 0);
9240 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9241 offset = INTVAL (XEXP (src, 1));
9242 else if (GET_CODE (XEXP (src, 1)) == REG
9243 && (reg_set_luid[REGNO (XEXP (src, 1))]
9244 > move2add_last_label_luid)
9245 && (MODES_OK_FOR_MOVE2ADD
9246 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9248 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9249 offset = reg_offset[REGNO (XEXP (src, 1))];
9250 /* Maybe the first register is known to be a
9252 else if (reg_set_luid[REGNO (base_reg)]
9253 > move2add_last_label_luid
9254 && (MODES_OK_FOR_MOVE2ADD
9255 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9256 && reg_base_reg[REGNO (base_reg)] < 0)
9258 offset = reg_offset[REGNO (base_reg)];
9259 base_reg = XEXP (src, 1);
9278 /* Start tracking the register as a constant. */
9279 reg_base_reg[regno] = -1;
9280 reg_offset[regno] = INTVAL (SET_SRC (set));
9281 /* We assign the same luid to all registers set to constants. */
9282 reg_set_luid[regno] = move2add_last_label_luid + 1;
9283 reg_mode[regno] = mode;
9288 /* Invalidate the contents of the register. */
9289 reg_set_luid[regno] = 0;
9293 base_regno = REGNO (base_reg);
9294 /* If information about the base register is not valid, set it
9295 up as a new base register, pretending its value is known
9296 starting from the current insn. */
9297 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9299 reg_base_reg[base_regno] = base_regno;
9300 reg_offset[base_regno] = 0;
9301 reg_set_luid[base_regno] = move2add_luid;
9302 reg_mode[base_regno] = mode;
9304 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9305 reg_mode[base_regno]))
9308 reg_mode[regno] = mode;
9310 /* Copy base information from our base register. */
9311 reg_set_luid[regno] = reg_set_luid[base_regno];
9312 reg_base_reg[regno] = reg_base_reg[base_regno];
9314 /* Compute the sum of the offsets or constants. */
9315 reg_offset[regno] = sext_for_mode (dst_mode,
9317 + reg_offset[base_regno]);
9321 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9323 for (i = regno; i < endregno; i++)
9324 /* Reset the information about this register. */
9325 reg_set_luid[i] = 0;
9331 add_auto_inc_notes (insn, x)
9335 enum rtx_code code = GET_CODE (x);
9339 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9342 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9346 /* Scan all the operand sub-expressions. */
9347 fmt = GET_RTX_FORMAT (code);
9348 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9351 add_auto_inc_notes (insn, XEXP (x, i));
9352 else if (fmt[i] == 'E')
9353 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9354 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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