1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
124 int reg_equiv_init_size;
126 /* Vector to remember old contents of reg_renumber before spilling. */
127 static short *reg_old_renumber;
129 /* During reload_as_needed, element N contains the last pseudo regno reloaded
130 into hard register N. If that pseudo reg occupied more than one register,
131 reg_reloaded_contents points to that pseudo for each spill register in
132 use; all of these must remain set for an inheritance to occur. */
133 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
135 /* During reload_as_needed, element N contains the insn for which
136 hard register N was last used. Its contents are significant only
137 when reg_reloaded_valid is set for this register. */
138 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
140 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
141 static HARD_REG_SET reg_reloaded_valid;
142 /* Indicate if the register was dead at the end of the reload.
143 This is only valid if reg_reloaded_contents is set and valid. */
144 static HARD_REG_SET reg_reloaded_dead;
146 /* Indicate whether the register's current value is one that is not
147 safe to retain across a call, even for registers that are normally
149 static HARD_REG_SET reg_reloaded_call_part_clobbered;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 static struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 static char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 static char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
290 /* List of all insns needing reloads. */
291 static struct insn_chain *insns_need_reload;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
300 int from; /* Register number to be eliminated. */
301 int to; /* Register number used as replacement. */
302 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
303 int can_eliminate; /* Nonzero if this elimination can be done. */
304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 HOST_WIDE_INT offset; /* Current offset between the two regs. */
307 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
308 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
309 rtx from_rtx; /* REG rtx for the register to be eliminated.
310 We cannot simply compare the number since
311 we might then spuriously replace a hard
312 register corresponding to a pseudo
313 assigned to the reg to be eliminated. */
314 rtx to_rtx; /* REG rtx for the replacement. */
317 static struct elim_table *reg_eliminate = 0;
319 /* This is an intermediate structure to initialize the table. It has
320 exactly the members provided by ELIMINABLE_REGS. */
321 static const struct elim_table_1
325 } reg_eliminate_1[] =
327 /* If a set of eliminable registers was specified, define the table from it.
328 Otherwise, default to the normal case of the frame pointer being
329 replaced by the stack pointer. */
331 #ifdef ELIMINABLE_REGS
334 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
337 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
339 /* Record the number of pending eliminations that have an offset not equal
340 to their initial offset. If nonzero, we use a new copy of each
341 replacement result in any insns encountered. */
342 int num_not_at_initial_offset;
344 /* Count the number of registers that we may be able to eliminate. */
345 static int num_eliminable;
346 /* And the number of registers that are equivalent to a constant that
347 can be eliminated to frame_pointer / arg_pointer + constant. */
348 static int num_eliminable_invariants;
350 /* For each label, we record the offset of each elimination. If we reach
351 a label by more than one path and an offset differs, we cannot do the
352 elimination. This information is indexed by the difference of the
353 number of the label and the first label number. We can't offset the
354 pointer itself as this can cause problems on machines with segmented
355 memory. The first table is an array of flags that records whether we
356 have yet encountered a label and the second table is an array of arrays,
357 one entry in the latter array for each elimination. */
359 static int first_label_num;
360 static char *offsets_known_at;
361 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
363 /* Number of labels in the current function. */
365 static int num_labels;
367 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
368 static void maybe_fix_stack_asms (void);
369 static void copy_reloads (struct insn_chain *);
370 static void calculate_needs_all_insns (int);
371 static int find_reg (struct insn_chain *, int);
372 static void find_reload_regs (struct insn_chain *);
373 static void select_reload_regs (void);
374 static void delete_caller_save_insns (void);
376 static void spill_failure (rtx, enum reg_class);
377 static void count_spilled_pseudo (int, int, int);
378 static void delete_dead_insn (rtx);
379 static void alter_reg (int, int);
380 static void set_label_offsets (rtx, rtx, int);
381 static void check_eliminable_occurrences (rtx);
382 static void elimination_effects (rtx, enum machine_mode);
383 static int eliminate_regs_in_insn (rtx, int);
384 static void update_eliminable_offsets (void);
385 static void mark_not_eliminable (rtx, rtx, void *);
386 static void set_initial_elim_offsets (void);
387 static bool verify_initial_elim_offsets (void);
388 static void set_initial_label_offsets (void);
389 static void set_offsets_for_label (rtx);
390 static void init_elim_table (void);
391 static void update_eliminables (HARD_REG_SET *);
392 static void spill_hard_reg (unsigned int, int);
393 static int finish_spills (int);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
698 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
699 reg_old_renumber = xcalloc (max_regno, sizeof (short));
700 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
701 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
702 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
704 CLEAR_HARD_REG_SET (bad_spill_regs_global);
706 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
707 to. Also find all paradoxical subregs and find largest such for
710 num_eliminable_invariants = 0;
711 for (insn = first; insn; insn = NEXT_INSN (insn))
713 rtx set = single_set (insn);
715 /* We may introduce USEs that we want to remove at the end, so
716 we'll mark them with QImode. Make sure there are no
717 previously-marked insns left by say regmove. */
718 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
719 && GET_MODE (insn) != VOIDmode)
720 PUT_MODE (insn, VOIDmode);
723 scan_paradoxical_subregs (PATTERN (insn));
725 if (set != 0 && REG_P (SET_DEST (set)))
727 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
733 i = REGNO (SET_DEST (set));
736 if (i <= LAST_VIRTUAL_REGISTER)
739 if (! function_invariant_p (x)
741 /* A function invariant is often CONSTANT_P but may
742 include a register. We promise to only pass
743 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
745 && LEGITIMATE_PIC_OPERAND_P (x)))
747 /* It can happen that a REG_EQUIV note contains a MEM
748 that is not a legitimate memory operand. As later
749 stages of reload assume that all addresses found
750 in the reg_equiv_* arrays were originally legitimate,
751 we ignore such REG_EQUIV notes. */
752 if (memory_operand (x, VOIDmode))
754 /* Always unshare the equivalence, so we can
755 substitute into this insn without touching the
757 reg_equiv_memory_loc[i] = copy_rtx (x);
759 else if (function_invariant_p (x))
761 if (GET_CODE (x) == PLUS)
763 /* This is PLUS of frame pointer and a constant,
764 and might be shared. Unshare it. */
765 reg_equiv_constant[i] = copy_rtx (x);
766 num_eliminable_invariants++;
768 else if (x == frame_pointer_rtx
769 || x == arg_pointer_rtx)
771 reg_equiv_constant[i] = x;
772 num_eliminable_invariants++;
774 else if (LEGITIMATE_CONSTANT_P (x))
775 reg_equiv_constant[i] = x;
778 reg_equiv_memory_loc[i]
779 = force_const_mem (GET_MODE (SET_DEST (set)), x);
780 if (! reg_equiv_memory_loc[i])
781 reg_equiv_init[i] = NULL_RTX;
786 reg_equiv_init[i] = NULL_RTX;
791 reg_equiv_init[i] = NULL_RTX;
796 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
797 if (reg_equiv_init[i])
799 fprintf (dump_file, "init_insns for %u: ", i);
800 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
801 fprintf (dump_file, "\n");
806 first_label_num = get_first_label_num ();
807 num_labels = max_label_num () - first_label_num;
809 /* Allocate the tables used to store offset information at labels. */
810 /* We used to use alloca here, but the size of what it would try to
811 allocate would occasionally cause it to exceed the stack limit and
812 cause a core dump. */
813 offsets_known_at = xmalloc (num_labels);
814 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
816 /* Alter each pseudo-reg rtx to contain its hard reg number.
817 Assign stack slots to the pseudos that lack hard regs or equivalents.
818 Do not touch virtual registers. */
820 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
823 /* If we have some registers we think can be eliminated, scan all insns to
824 see if there is an insn that sets one of these registers to something
825 other than itself plus a constant. If so, the register cannot be
826 eliminated. Doing this scan here eliminates an extra pass through the
827 main reload loop in the most common case where register elimination
829 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
831 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
833 maybe_fix_stack_asms ();
835 insns_need_reload = 0;
836 something_needs_elimination = 0;
838 /* Initialize to -1, which means take the first spill register. */
841 /* Spill any hard regs that we know we can't eliminate. */
842 CLEAR_HARD_REG_SET (used_spill_regs);
843 /* There can be multiple ways to eliminate a register;
844 they should be listed adjacently.
845 Elimination for any register fails only if all possible ways fail. */
846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
849 int can_eliminate = 0;
852 can_eliminate |= ep->can_eliminate;
855 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
857 spill_hard_reg (from, 1);
860 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
861 if (frame_pointer_needed)
862 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
864 finish_spills (global);
866 /* From now on, we may need to generate moves differently. We may also
867 allow modifications of insns which cause them to not be recognized.
868 Any such modifications will be cleaned up during reload itself. */
869 reload_in_progress = 1;
871 /* This loop scans the entire function each go-round
872 and repeats until one repetition spills no additional hard regs. */
875 int something_changed;
878 HOST_WIDE_INT starting_frame_size;
880 /* Round size of stack frame to stack_alignment_needed. This must be done
881 here because the stack size may be a part of the offset computation
882 for register elimination, and there might have been new stack slots
883 created in the last iteration of this loop. */
884 if (cfun->stack_alignment_needed)
885 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
887 starting_frame_size = get_frame_size ();
889 set_initial_elim_offsets ();
890 set_initial_label_offsets ();
892 /* For each pseudo register that has an equivalent location defined,
893 try to eliminate any eliminable registers (such as the frame pointer)
894 assuming initial offsets for the replacement register, which
897 If the resulting location is directly addressable, substitute
898 the MEM we just got directly for the old REG.
900 If it is not addressable but is a constant or the sum of a hard reg
901 and constant, it is probably not addressable because the constant is
902 out of range, in that case record the address; we will generate
903 hairy code to compute the address in a register each time it is
904 needed. Similarly if it is a hard register, but one that is not
905 valid as an address register.
907 If the location is not addressable, but does not have one of the
908 above forms, assign a stack slot. We have to do this to avoid the
909 potential of producing lots of reloads if, e.g., a location involves
910 a pseudo that didn't get a hard register and has an equivalent memory
911 location that also involves a pseudo that didn't get a hard register.
913 Perhaps at some point we will improve reload_when_needed handling
914 so this problem goes away. But that's very hairy. */
916 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
917 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
919 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
921 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
923 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
924 else if (CONSTANT_P (XEXP (x, 0))
925 || (REG_P (XEXP (x, 0))
926 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
927 || (GET_CODE (XEXP (x, 0)) == PLUS
928 && REG_P (XEXP (XEXP (x, 0), 0))
929 && (REGNO (XEXP (XEXP (x, 0), 0))
930 < FIRST_PSEUDO_REGISTER)
931 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
932 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
935 /* Make a new stack slot. Then indicate that something
936 changed so we go back and recompute offsets for
937 eliminable registers because the allocation of memory
938 below might change some offset. reg_equiv_{mem,address}
939 will be set up for this pseudo on the next pass around
941 reg_equiv_memory_loc[i] = 0;
942 reg_equiv_init[i] = 0;
947 if (caller_save_needed)
950 /* If we allocated another stack slot, redo elimination bookkeeping. */
951 if (starting_frame_size != get_frame_size ())
954 if (caller_save_needed)
956 save_call_clobbered_regs ();
957 /* That might have allocated new insn_chain structures. */
958 reload_firstobj = obstack_alloc (&reload_obstack, 0);
961 calculate_needs_all_insns (global);
963 CLEAR_REG_SET (&spilled_pseudos);
966 something_changed = 0;
968 /* If we allocated any new memory locations, make another pass
969 since it might have changed elimination offsets. */
970 if (starting_frame_size != get_frame_size ())
971 something_changed = 1;
973 /* Even if the frame size remained the same, we might still have
974 changed elimination offsets, e.g. if find_reloads called
975 force_const_mem requiring the back end to allocate a constant
976 pool base register that needs to be saved on the stack. */
977 else if (!verify_initial_elim_offsets ())
978 something_changed = 1;
981 HARD_REG_SET to_spill;
982 CLEAR_HARD_REG_SET (to_spill);
983 update_eliminables (&to_spill);
984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
985 if (TEST_HARD_REG_BIT (to_spill, i))
987 spill_hard_reg (i, 1);
990 /* Regardless of the state of spills, if we previously had
991 a register that we thought we could eliminate, but now can
992 not eliminate, we must run another pass.
994 Consider pseudos which have an entry in reg_equiv_* which
995 reference an eliminable register. We must make another pass
996 to update reg_equiv_* so that we do not substitute in the
997 old value from when we thought the elimination could be
999 something_changed = 1;
1003 select_reload_regs ();
1007 if (insns_need_reload != 0 || did_spill)
1008 something_changed |= finish_spills (global);
1010 if (! something_changed)
1013 if (caller_save_needed)
1014 delete_caller_save_insns ();
1016 obstack_free (&reload_obstack, reload_firstobj);
1019 /* If global-alloc was run, notify it of any register eliminations we have
1022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1023 if (ep->can_eliminate)
1024 mark_elimination (ep->from, ep->to);
1026 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1027 If that insn didn't set the register (i.e., it copied the register to
1028 memory), just delete that insn instead of the equivalencing insn plus
1029 anything now dead. If we call delete_dead_insn on that insn, we may
1030 delete the insn that actually sets the register if the register dies
1031 there and that is incorrect. */
1033 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1035 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1038 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1040 rtx equiv_insn = XEXP (list, 0);
1042 /* If we already deleted the insn or if it may trap, we can't
1043 delete it. The latter case shouldn't happen, but can
1044 if an insn has a variable address, gets a REG_EH_REGION
1045 note added to it, and then gets converted into a load
1046 from a constant address. */
1047 if (NOTE_P (equiv_insn)
1048 || can_throw_internal (equiv_insn))
1050 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1051 delete_dead_insn (equiv_insn);
1053 SET_INSN_DELETED (equiv_insn);
1058 /* Use the reload registers where necessary
1059 by generating move instructions to move the must-be-register
1060 values into or out of the reload registers. */
1062 if (insns_need_reload != 0 || something_needs_elimination
1063 || something_needs_operands_changed)
1065 HOST_WIDE_INT old_frame_size = get_frame_size ();
1067 reload_as_needed (global);
1069 gcc_assert (old_frame_size == get_frame_size ());
1071 gcc_assert (verify_initial_elim_offsets ());
1074 /* If we were able to eliminate the frame pointer, show that it is no
1075 longer live at the start of any basic block. If it ls live by
1076 virtue of being in a pseudo, that pseudo will be marked live
1077 and hence the frame pointer will be known to be live via that
1080 if (! frame_pointer_needed)
1082 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1083 HARD_FRAME_POINTER_REGNUM);
1085 /* Come here (with failure set nonzero) if we can't get enough spill
1089 CLEAR_REG_SET (&spilled_pseudos);
1090 reload_in_progress = 0;
1092 /* Now eliminate all pseudo regs by modifying them into
1093 their equivalent memory references.
1094 The REG-rtx's for the pseudos are modified in place,
1095 so all insns that used to refer to them now refer to memory.
1097 For a reg that has a reg_equiv_address, all those insns
1098 were changed by reloading so that no insns refer to it any longer;
1099 but the DECL_RTL of a variable decl may refer to it,
1100 and if so this causes the debugging info to mention the variable. */
1102 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1106 if (reg_equiv_mem[i])
1107 addr = XEXP (reg_equiv_mem[i], 0);
1109 if (reg_equiv_address[i])
1110 addr = reg_equiv_address[i];
1114 if (reg_renumber[i] < 0)
1116 rtx reg = regno_reg_rtx[i];
1118 REG_USERVAR_P (reg) = 0;
1119 PUT_CODE (reg, MEM);
1120 XEXP (reg, 0) = addr;
1121 if (reg_equiv_memory_loc[i])
1122 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1125 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1126 MEM_ATTRS (reg) = 0;
1128 MEM_NOTRAP_P (reg) = 1;
1130 else if (reg_equiv_mem[i])
1131 XEXP (reg_equiv_mem[i], 0) = addr;
1135 /* We must set reload_completed now since the cleanup_subreg_operands call
1136 below will re-recognize each insn and reload may have generated insns
1137 which are only valid during and after reload. */
1138 reload_completed = 1;
1140 /* Make a pass over all the insns and delete all USEs which we inserted
1141 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1142 notes. Delete all CLOBBER insns, except those that refer to the return
1143 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1144 from misarranging variable-array code, and simplify (subreg (reg))
1145 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1146 are no longer useful or accurate. Strip and regenerate REG_INC notes
1147 that may have been moved around. */
1149 for (insn = first; insn; insn = NEXT_INSN (insn))
1155 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1156 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1158 if ((GET_CODE (PATTERN (insn)) == USE
1159 /* We mark with QImode USEs introduced by reload itself. */
1160 && (GET_MODE (insn) == QImode
1161 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1162 || (GET_CODE (PATTERN (insn)) == CLOBBER
1163 && (!MEM_P (XEXP (PATTERN (insn), 0))
1164 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1165 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1166 && XEXP (XEXP (PATTERN (insn), 0), 0)
1167 != stack_pointer_rtx))
1168 && (!REG_P (XEXP (PATTERN (insn), 0))
1169 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1175 /* Some CLOBBERs may survive until here and still reference unassigned
1176 pseudos with const equivalent, which may in turn cause ICE in later
1177 passes if the reference remains in place. */
1178 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1179 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1180 VOIDmode, PATTERN (insn));
1182 /* Discard obvious no-ops, even without -O. This optimization
1183 is fast and doesn't interfere with debugging. */
1184 if (NONJUMP_INSN_P (insn)
1185 && GET_CODE (PATTERN (insn)) == SET
1186 && REG_P (SET_SRC (PATTERN (insn)))
1187 && REG_P (SET_DEST (PATTERN (insn)))
1188 && (REGNO (SET_SRC (PATTERN (insn)))
1189 == REGNO (SET_DEST (PATTERN (insn)))))
1195 pnote = ®_NOTES (insn);
1198 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1199 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1200 || REG_NOTE_KIND (*pnote) == REG_INC
1201 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1202 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1203 *pnote = XEXP (*pnote, 1);
1205 pnote = &XEXP (*pnote, 1);
1209 add_auto_inc_notes (insn, PATTERN (insn));
1212 /* And simplify (subreg (reg)) if it appears as an operand. */
1213 cleanup_subreg_operands (insn);
1216 /* If we are doing stack checking, give a warning if this function's
1217 frame size is larger than we expect. */
1218 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1220 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1221 static int verbose_warned = 0;
1223 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1224 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1225 size += UNITS_PER_WORD;
1227 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1229 warning (0, "frame size too large for reliable stack checking");
1230 if (! verbose_warned)
1232 warning (0, "try reducing the number of local variables");
1238 /* Indicate that we no longer have known memory locations or constants. */
1239 if (reg_equiv_constant)
1240 free (reg_equiv_constant);
1241 reg_equiv_constant = 0;
1242 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1243 reg_equiv_memory_loc = 0;
1245 if (offsets_known_at)
1246 free (offsets_known_at);
1250 free (reg_equiv_mem);
1252 free (reg_equiv_address);
1253 free (reg_max_ref_width);
1254 free (reg_old_renumber);
1255 free (pseudo_previous_regs);
1256 free (pseudo_forbidden_regs);
1258 CLEAR_HARD_REG_SET (used_spill_regs);
1259 for (i = 0; i < n_spills; i++)
1260 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1262 /* Free all the insn_chain structures at once. */
1263 obstack_free (&reload_obstack, reload_startobj);
1264 unused_insn_chains = 0;
1265 fixup_abnormal_edges ();
1267 /* Replacing pseudos with their memory equivalents might have
1268 created shared rtx. Subsequent passes would get confused
1269 by this, so unshare everything here. */
1270 unshare_all_rtl_again (first);
1272 #ifdef STACK_BOUNDARY
1273 /* init_emit has set the alignment of the hard frame pointer
1274 to STACK_BOUNDARY. It is very likely no longer valid if
1275 the hard frame pointer was used for register allocation. */
1276 if (!frame_pointer_needed)
1277 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1283 /* Yet another special case. Unfortunately, reg-stack forces people to
1284 write incorrect clobbers in asm statements. These clobbers must not
1285 cause the register to appear in bad_spill_regs, otherwise we'll call
1286 fatal_insn later. We clear the corresponding regnos in the live
1287 register sets to avoid this.
1288 The whole thing is rather sick, I'm afraid. */
1291 maybe_fix_stack_asms (void)
1294 const char *constraints[MAX_RECOG_OPERANDS];
1295 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1296 struct insn_chain *chain;
1298 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1301 HARD_REG_SET clobbered, allowed;
1304 if (! INSN_P (chain->insn)
1305 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1307 pat = PATTERN (chain->insn);
1308 if (GET_CODE (pat) != PARALLEL)
1311 CLEAR_HARD_REG_SET (clobbered);
1312 CLEAR_HARD_REG_SET (allowed);
1314 /* First, make a mask of all stack regs that are clobbered. */
1315 for (i = 0; i < XVECLEN (pat, 0); i++)
1317 rtx t = XVECEXP (pat, 0, i);
1318 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1319 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1322 /* Get the operand values and constraints out of the insn. */
1323 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1324 constraints, operand_mode);
1326 /* For every operand, see what registers are allowed. */
1327 for (i = 0; i < noperands; i++)
1329 const char *p = constraints[i];
1330 /* For every alternative, we compute the class of registers allowed
1331 for reloading in CLS, and merge its contents into the reg set
1333 int cls = (int) NO_REGS;
1339 if (c == '\0' || c == ',' || c == '#')
1341 /* End of one alternative - mark the regs in the current
1342 class, and reset the class. */
1343 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1349 } while (c != '\0' && c != ',');
1357 case '=': case '+': case '*': case '%': case '?': case '!':
1358 case '0': case '1': case '2': case '3': case '4': case 'm':
1359 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1360 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1361 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1366 cls = (int) reg_class_subunion[cls]
1367 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1372 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1376 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1377 cls = (int) reg_class_subunion[cls]
1378 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1380 cls = (int) reg_class_subunion[cls]
1381 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1383 p += CONSTRAINT_LEN (c, p);
1386 /* Those of the registers which are clobbered, but allowed by the
1387 constraints, must be usable as reload registers. So clear them
1388 out of the life information. */
1389 AND_HARD_REG_SET (allowed, clobbered);
1390 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1391 if (TEST_HARD_REG_BIT (allowed, i))
1393 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1394 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1401 /* Copy the global variables n_reloads and rld into the corresponding elts
1404 copy_reloads (struct insn_chain *chain)
1406 chain->n_reloads = n_reloads;
1407 chain->rld = obstack_alloc (&reload_obstack,
1408 n_reloads * sizeof (struct reload));
1409 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1410 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1413 /* Walk the chain of insns, and determine for each whether it needs reloads
1414 and/or eliminations. Build the corresponding insns_need_reload list, and
1415 set something_needs_elimination as appropriate. */
1417 calculate_needs_all_insns (int global)
1419 struct insn_chain **pprev_reload = &insns_need_reload;
1420 struct insn_chain *chain, *next = 0;
1422 something_needs_elimination = 0;
1424 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1425 for (chain = reload_insn_chain; chain != 0; chain = next)
1427 rtx insn = chain->insn;
1431 /* Clear out the shortcuts. */
1432 chain->n_reloads = 0;
1433 chain->need_elim = 0;
1434 chain->need_reload = 0;
1435 chain->need_operand_change = 0;
1437 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1438 include REG_LABEL), we need to see what effects this has on the
1439 known offsets at labels. */
1441 if (LABEL_P (insn) || JUMP_P (insn)
1442 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1443 set_label_offsets (insn, insn, 0);
1447 rtx old_body = PATTERN (insn);
1448 int old_code = INSN_CODE (insn);
1449 rtx old_notes = REG_NOTES (insn);
1450 int did_elimination = 0;
1451 int operands_changed = 0;
1452 rtx set = single_set (insn);
1454 /* Skip insns that only set an equivalence. */
1455 if (set && REG_P (SET_DEST (set))
1456 && reg_renumber[REGNO (SET_DEST (set))] < 0
1457 && reg_equiv_constant[REGNO (SET_DEST (set))])
1460 /* If needed, eliminate any eliminable registers. */
1461 if (num_eliminable || num_eliminable_invariants)
1462 did_elimination = eliminate_regs_in_insn (insn, 0);
1464 /* Analyze the instruction. */
1465 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1466 global, spill_reg_order);
1468 /* If a no-op set needs more than one reload, this is likely
1469 to be something that needs input address reloads. We
1470 can't get rid of this cleanly later, and it is of no use
1471 anyway, so discard it now.
1472 We only do this when expensive_optimizations is enabled,
1473 since this complements reload inheritance / output
1474 reload deletion, and it can make debugging harder. */
1475 if (flag_expensive_optimizations && n_reloads > 1)
1477 rtx set = single_set (insn);
1479 && SET_SRC (set) == SET_DEST (set)
1480 && REG_P (SET_SRC (set))
1481 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1484 /* Delete it from the reload chain. */
1486 chain->prev->next = next;
1488 reload_insn_chain = next;
1490 next->prev = chain->prev;
1491 chain->next = unused_insn_chains;
1492 unused_insn_chains = chain;
1497 update_eliminable_offsets ();
1499 /* Remember for later shortcuts which insns had any reloads or
1500 register eliminations. */
1501 chain->need_elim = did_elimination;
1502 chain->need_reload = n_reloads > 0;
1503 chain->need_operand_change = operands_changed;
1505 /* Discard any register replacements done. */
1506 if (did_elimination)
1508 obstack_free (&reload_obstack, reload_insn_firstobj);
1509 PATTERN (insn) = old_body;
1510 INSN_CODE (insn) = old_code;
1511 REG_NOTES (insn) = old_notes;
1512 something_needs_elimination = 1;
1515 something_needs_operands_changed |= operands_changed;
1519 copy_reloads (chain);
1520 *pprev_reload = chain;
1521 pprev_reload = &chain->next_need_reload;
1528 /* Comparison function for qsort to decide which of two reloads
1529 should be handled first. *P1 and *P2 are the reload numbers. */
1532 reload_reg_class_lower (const void *r1p, const void *r2p)
1534 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1537 /* Consider required reloads before optional ones. */
1538 t = rld[r1].optional - rld[r2].optional;
1542 /* Count all solitary classes before non-solitary ones. */
1543 t = ((reg_class_size[(int) rld[r2].class] == 1)
1544 - (reg_class_size[(int) rld[r1].class] == 1));
1548 /* Aside from solitaires, consider all multi-reg groups first. */
1549 t = rld[r2].nregs - rld[r1].nregs;
1553 /* Consider reloads in order of increasing reg-class number. */
1554 t = (int) rld[r1].class - (int) rld[r2].class;
1558 /* If reloads are equally urgent, sort by reload number,
1559 so that the results of qsort leave nothing to chance. */
1563 /* The cost of spilling each hard reg. */
1564 static int spill_cost[FIRST_PSEUDO_REGISTER];
1566 /* When spilling multiple hard registers, we use SPILL_COST for the first
1567 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1568 only the first hard reg for a multi-reg pseudo. */
1569 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1571 /* Update the spill cost arrays, considering that pseudo REG is live. */
1574 count_pseudo (int reg)
1576 int freq = REG_FREQ (reg);
1577 int r = reg_renumber[reg];
1580 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1581 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1584 SET_REGNO_REG_SET (&pseudos_counted, reg);
1586 gcc_assert (r >= 0);
1588 spill_add_cost[r] += freq;
1590 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1592 spill_cost[r + nregs] += freq;
1595 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1596 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1599 order_regs_for_reload (struct insn_chain *chain)
1602 HARD_REG_SET used_by_pseudos;
1603 HARD_REG_SET used_by_pseudos2;
1604 reg_set_iterator rsi;
1606 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1608 memset (spill_cost, 0, sizeof spill_cost);
1609 memset (spill_add_cost, 0, sizeof spill_add_cost);
1611 /* Count number of uses of each hard reg by pseudo regs allocated to it
1612 and then order them by decreasing use. First exclude hard registers
1613 that are live in or across this insn. */
1615 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1616 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1617 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1618 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1620 /* Now find out which pseudos are allocated to it, and update
1622 CLEAR_REG_SET (&pseudos_counted);
1624 EXECUTE_IF_SET_IN_REG_SET
1625 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1629 EXECUTE_IF_SET_IN_REG_SET
1630 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1634 CLEAR_REG_SET (&pseudos_counted);
1637 /* Vector of reload-numbers showing the order in which the reloads should
1639 static short reload_order[MAX_RELOADS];
1641 /* This is used to keep track of the spill regs used in one insn. */
1642 static HARD_REG_SET used_spill_regs_local;
1644 /* We decided to spill hard register SPILLED, which has a size of
1645 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1646 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1647 update SPILL_COST/SPILL_ADD_COST. */
1650 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1652 int r = reg_renumber[reg];
1653 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1655 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1656 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1659 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1661 spill_add_cost[r] -= REG_FREQ (reg);
1663 spill_cost[r + nregs] -= REG_FREQ (reg);
1666 /* Find reload register to use for reload number ORDER. */
1669 find_reg (struct insn_chain *chain, int order)
1671 int rnum = reload_order[order];
1672 struct reload *rl = rld + rnum;
1673 int best_cost = INT_MAX;
1677 HARD_REG_SET not_usable;
1678 HARD_REG_SET used_by_other_reload;
1679 reg_set_iterator rsi;
1681 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1682 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1683 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1685 CLEAR_HARD_REG_SET (used_by_other_reload);
1686 for (k = 0; k < order; k++)
1688 int other = reload_order[k];
1690 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1691 for (j = 0; j < rld[other].nregs; j++)
1692 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1695 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1697 unsigned int regno = i;
1699 if (! TEST_HARD_REG_BIT (not_usable, regno)
1700 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1701 && HARD_REGNO_MODE_OK (regno, rl->mode))
1703 int this_cost = spill_cost[regno];
1705 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1707 for (j = 1; j < this_nregs; j++)
1709 this_cost += spill_add_cost[regno + j];
1710 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1711 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1716 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1718 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1720 if (this_cost < best_cost
1721 /* Among registers with equal cost, prefer caller-saved ones, or
1722 use REG_ALLOC_ORDER if it is defined. */
1723 || (this_cost == best_cost
1724 #ifdef REG_ALLOC_ORDER
1725 && (inv_reg_alloc_order[regno]
1726 < inv_reg_alloc_order[best_reg])
1728 && call_used_regs[regno]
1729 && ! call_used_regs[best_reg]
1734 best_cost = this_cost;
1742 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1744 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1745 rl->regno = best_reg;
1747 EXECUTE_IF_SET_IN_REG_SET
1748 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1750 count_spilled_pseudo (best_reg, rl->nregs, j);
1753 EXECUTE_IF_SET_IN_REG_SET
1754 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1756 count_spilled_pseudo (best_reg, rl->nregs, j);
1759 for (i = 0; i < rl->nregs; i++)
1761 gcc_assert (spill_cost[best_reg + i] == 0);
1762 gcc_assert (spill_add_cost[best_reg + i] == 0);
1763 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1768 /* Find more reload regs to satisfy the remaining need of an insn, which
1770 Do it by ascending class number, since otherwise a reg
1771 might be spilled for a big class and might fail to count
1772 for a smaller class even though it belongs to that class. */
1775 find_reload_regs (struct insn_chain *chain)
1779 /* In order to be certain of getting the registers we need,
1780 we must sort the reloads into order of increasing register class.
1781 Then our grabbing of reload registers will parallel the process
1782 that provided the reload registers. */
1783 for (i = 0; i < chain->n_reloads; i++)
1785 /* Show whether this reload already has a hard reg. */
1786 if (chain->rld[i].reg_rtx)
1788 int regno = REGNO (chain->rld[i].reg_rtx);
1789 chain->rld[i].regno = regno;
1791 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1794 chain->rld[i].regno = -1;
1795 reload_order[i] = i;
1798 n_reloads = chain->n_reloads;
1799 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1801 CLEAR_HARD_REG_SET (used_spill_regs_local);
1804 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1806 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1808 /* Compute the order of preference for hard registers to spill. */
1810 order_regs_for_reload (chain);
1812 for (i = 0; i < n_reloads; i++)
1814 int r = reload_order[i];
1816 /* Ignore reloads that got marked inoperative. */
1817 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1818 && ! rld[r].optional
1819 && rld[r].regno == -1)
1820 if (! find_reg (chain, i))
1822 spill_failure (chain->insn, rld[r].class);
1828 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1829 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1831 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1835 select_reload_regs (void)
1837 struct insn_chain *chain;
1839 /* Try to satisfy the needs for each insn. */
1840 for (chain = insns_need_reload; chain != 0;
1841 chain = chain->next_need_reload)
1842 find_reload_regs (chain);
1845 /* Delete all insns that were inserted by emit_caller_save_insns during
1848 delete_caller_save_insns (void)
1850 struct insn_chain *c = reload_insn_chain;
1854 while (c != 0 && c->is_caller_save_insn)
1856 struct insn_chain *next = c->next;
1859 if (c == reload_insn_chain)
1860 reload_insn_chain = next;
1864 next->prev = c->prev;
1866 c->prev->next = next;
1867 c->next = unused_insn_chains;
1868 unused_insn_chains = c;
1876 /* Handle the failure to find a register to spill.
1877 INSN should be one of the insns which needed this particular spill reg. */
1880 spill_failure (rtx insn, enum reg_class class)
1882 if (asm_noperands (PATTERN (insn)) >= 0)
1883 error_for_asm (insn, "can't find a register in class %qs while "
1884 "reloading %<asm%>",
1885 reg_class_names[class]);
1888 error ("unable to find a register to spill in class %qs",
1889 reg_class_names[class]);
1890 fatal_insn ("this is the insn:", insn);
1894 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1895 data that is dead in INSN. */
1898 delete_dead_insn (rtx insn)
1900 rtx prev = prev_real_insn (insn);
1903 /* If the previous insn sets a register that dies in our insn, delete it
1905 if (prev && GET_CODE (PATTERN (prev)) == SET
1906 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1907 && reg_mentioned_p (prev_dest, PATTERN (insn))
1908 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1909 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1910 delete_dead_insn (prev);
1912 SET_INSN_DELETED (insn);
1915 /* Modify the home of pseudo-reg I.
1916 The new home is present in reg_renumber[I].
1918 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1919 or it may be -1, meaning there is none or it is not relevant.
1920 This is used so that all pseudos spilled from a given hard reg
1921 can share one stack slot. */
1924 alter_reg (int i, int from_reg)
1926 /* When outputting an inline function, this can happen
1927 for a reg that isn't actually used. */
1928 if (regno_reg_rtx[i] == 0)
1931 /* If the reg got changed to a MEM at rtl-generation time,
1933 if (!REG_P (regno_reg_rtx[i]))
1936 /* Modify the reg-rtx to contain the new hard reg
1937 number or else to contain its pseudo reg number. */
1938 REGNO (regno_reg_rtx[i])
1939 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1941 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1942 allocate a stack slot for it. */
1944 if (reg_renumber[i] < 0
1945 && REG_N_REFS (i) > 0
1946 && reg_equiv_constant[i] == 0
1947 && reg_equiv_memory_loc[i] == 0)
1950 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1951 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1954 /* Each pseudo reg has an inherent size which comes from its own mode,
1955 and a total size which provides room for paradoxical subregs
1956 which refer to the pseudo reg in wider modes.
1958 We can use a slot already allocated if it provides both
1959 enough inherent space and enough total space.
1960 Otherwise, we allocate a new slot, making sure that it has no less
1961 inherent space, and no less total space, then the previous slot. */
1964 /* No known place to spill from => no slot to reuse. */
1965 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1966 inherent_size == total_size ? 0 : -1);
1967 if (BYTES_BIG_ENDIAN)
1968 /* Cancel the big-endian correction done in assign_stack_local.
1969 Get the address of the beginning of the slot.
1970 This is so we can do a big-endian correction unconditionally
1972 adjust = inherent_size - total_size;
1974 /* Nothing can alias this slot except this pseudo. */
1975 set_mem_alias_set (x, new_alias_set ());
1978 /* Reuse a stack slot if possible. */
1979 else if (spill_stack_slot[from_reg] != 0
1980 && spill_stack_slot_width[from_reg] >= total_size
1981 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1983 x = spill_stack_slot[from_reg];
1985 /* Allocate a bigger slot. */
1988 /* Compute maximum size needed, both for inherent size
1989 and for total size. */
1990 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1993 if (spill_stack_slot[from_reg])
1995 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1997 mode = GET_MODE (spill_stack_slot[from_reg]);
1998 if (spill_stack_slot_width[from_reg] > total_size)
1999 total_size = spill_stack_slot_width[from_reg];
2002 /* Make a slot with that size. */
2003 x = assign_stack_local (mode, total_size,
2004 inherent_size == total_size ? 0 : -1);
2007 /* All pseudos mapped to this slot can alias each other. */
2008 if (spill_stack_slot[from_reg])
2009 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2011 set_mem_alias_set (x, new_alias_set ());
2013 if (BYTES_BIG_ENDIAN)
2015 /* Cancel the big-endian correction done in assign_stack_local.
2016 Get the address of the beginning of the slot.
2017 This is so we can do a big-endian correction unconditionally
2019 adjust = GET_MODE_SIZE (mode) - total_size;
2022 = adjust_address_nv (x, mode_for_size (total_size
2028 spill_stack_slot[from_reg] = stack_slot;
2029 spill_stack_slot_width[from_reg] = total_size;
2032 /* On a big endian machine, the "address" of the slot
2033 is the address of the low part that fits its inherent mode. */
2034 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2035 adjust += (total_size - inherent_size);
2037 /* If we have any adjustment to make, or if the stack slot is the
2038 wrong mode, make a new stack slot. */
2039 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2041 /* If we have a decl for the original register, set it for the
2042 memory. If this is a shared MEM, make a copy. */
2043 if (REG_EXPR (regno_reg_rtx[i])
2044 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2046 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2048 /* We can do this only for the DECLs home pseudo, not for
2049 any copies of it, since otherwise when the stack slot
2050 is reused, nonoverlapping_memrefs_p might think they
2052 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2054 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2057 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2061 /* Save the stack slot for later. */
2062 reg_equiv_memory_loc[i] = x;
2066 /* Mark the slots in regs_ever_live for the hard regs
2067 used by pseudo-reg number REGNO. */
2070 mark_home_live (int regno)
2074 i = reg_renumber[regno];
2077 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2079 regs_ever_live[i++] = 1;
2082 /* This function handles the tracking of elimination offsets around branches.
2084 X is a piece of RTL being scanned.
2086 INSN is the insn that it came from, if any.
2088 INITIAL_P is nonzero if we are to set the offset to be the initial
2089 offset and zero if we are setting the offset of the label to be the
2093 set_label_offsets (rtx x, rtx insn, int initial_p)
2095 enum rtx_code code = GET_CODE (x);
2098 struct elim_table *p;
2103 if (LABEL_REF_NONLOCAL_P (x))
2108 /* ... fall through ... */
2111 /* If we know nothing about this label, set the desired offsets. Note
2112 that this sets the offset at a label to be the offset before a label
2113 if we don't know anything about the label. This is not correct for
2114 the label after a BARRIER, but is the best guess we can make. If
2115 we guessed wrong, we will suppress an elimination that might have
2116 been possible had we been able to guess correctly. */
2118 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2120 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2121 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2122 = (initial_p ? reg_eliminate[i].initial_offset
2123 : reg_eliminate[i].offset);
2124 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2127 /* Otherwise, if this is the definition of a label and it is
2128 preceded by a BARRIER, set our offsets to the known offset of
2132 && (tem = prev_nonnote_insn (insn)) != 0
2134 set_offsets_for_label (insn);
2136 /* If neither of the above cases is true, compare each offset
2137 with those previously recorded and suppress any eliminations
2138 where the offsets disagree. */
2140 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2141 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2142 != (initial_p ? reg_eliminate[i].initial_offset
2143 : reg_eliminate[i].offset))
2144 reg_eliminate[i].can_eliminate = 0;
2149 set_label_offsets (PATTERN (insn), insn, initial_p);
2151 /* ... fall through ... */
2155 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2156 and hence must have all eliminations at their initial offsets. */
2157 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2158 if (REG_NOTE_KIND (tem) == REG_LABEL)
2159 set_label_offsets (XEXP (tem, 0), insn, 1);
2165 /* Each of the labels in the parallel or address vector must be
2166 at their initial offsets. We want the first field for PARALLEL
2167 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2169 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2170 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2175 /* We only care about setting PC. If the source is not RETURN,
2176 IF_THEN_ELSE, or a label, disable any eliminations not at
2177 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2178 isn't one of those possibilities. For branches to a label,
2179 call ourselves recursively.
2181 Note that this can disable elimination unnecessarily when we have
2182 a non-local goto since it will look like a non-constant jump to
2183 someplace in the current function. This isn't a significant
2184 problem since such jumps will normally be when all elimination
2185 pairs are back to their initial offsets. */
2187 if (SET_DEST (x) != pc_rtx)
2190 switch (GET_CODE (SET_SRC (x)))
2197 set_label_offsets (SET_SRC (x), insn, initial_p);
2201 tem = XEXP (SET_SRC (x), 1);
2202 if (GET_CODE (tem) == LABEL_REF)
2203 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2204 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2207 tem = XEXP (SET_SRC (x), 2);
2208 if (GET_CODE (tem) == LABEL_REF)
2209 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2210 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2218 /* If we reach here, all eliminations must be at their initial
2219 offset because we are doing a jump to a variable address. */
2220 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2221 if (p->offset != p->initial_offset)
2222 p->can_eliminate = 0;
2230 /* Scan X and replace any eliminable registers (such as fp) with a
2231 replacement (such as sp), plus an offset.
2233 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2234 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2235 MEM, we are allowed to replace a sum of a register and the constant zero
2236 with the register, which we cannot do outside a MEM. In addition, we need
2237 to record the fact that a register is referenced outside a MEM.
2239 If INSN is an insn, it is the insn containing X. If we replace a REG
2240 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2241 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2242 the REG is being modified.
2244 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2245 That's used when we eliminate in expressions stored in notes.
2246 This means, do not set ref_outside_mem even if the reference
2249 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2250 replacements done assuming all offsets are at their initial values. If
2251 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2252 encounter, return the actual location so that find_reloads will do
2253 the proper thing. */
2256 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2258 enum rtx_code code = GET_CODE (x);
2259 struct elim_table *ep;
2266 if (! current_function_decl)
2288 /* First handle the case where we encounter a bare register that
2289 is eliminable. Replace it with a PLUS. */
2290 if (regno < FIRST_PSEUDO_REGISTER)
2292 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2294 if (ep->from_rtx == x && ep->can_eliminate)
2295 return plus_constant (ep->to_rtx, ep->previous_offset);
2298 else if (reg_renumber && reg_renumber[regno] < 0
2299 && reg_equiv_constant && reg_equiv_constant[regno]
2300 && ! CONSTANT_P (reg_equiv_constant[regno]))
2301 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2305 /* You might think handling MINUS in a manner similar to PLUS is a
2306 good idea. It is not. It has been tried multiple times and every
2307 time the change has had to have been reverted.
2309 Other parts of reload know a PLUS is special (gen_reload for example)
2310 and require special code to handle code a reloaded PLUS operand.
2312 Also consider backends where the flags register is clobbered by a
2313 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2314 lea instruction comes to mind). If we try to reload a MINUS, we
2315 may kill the flags register that was holding a useful value.
2317 So, please before trying to handle MINUS, consider reload as a
2318 whole instead of this little section as well as the backend issues. */
2320 /* If this is the sum of an eliminable register and a constant, rework
2322 if (REG_P (XEXP (x, 0))
2323 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2324 && CONSTANT_P (XEXP (x, 1)))
2326 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2328 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2330 /* The only time we want to replace a PLUS with a REG (this
2331 occurs when the constant operand of the PLUS is the negative
2332 of the offset) is when we are inside a MEM. We won't want
2333 to do so at other times because that would change the
2334 structure of the insn in a way that reload can't handle.
2335 We special-case the commonest situation in
2336 eliminate_regs_in_insn, so just replace a PLUS with a
2337 PLUS here, unless inside a MEM. */
2338 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2339 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2342 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2343 plus_constant (XEXP (x, 1),
2344 ep->previous_offset));
2347 /* If the register is not eliminable, we are done since the other
2348 operand is a constant. */
2352 /* If this is part of an address, we want to bring any constant to the
2353 outermost PLUS. We will do this by doing register replacement in
2354 our operands and seeing if a constant shows up in one of them.
2356 Note that there is no risk of modifying the structure of the insn,
2357 since we only get called for its operands, thus we are either
2358 modifying the address inside a MEM, or something like an address
2359 operand of a load-address insn. */
2362 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2363 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2365 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2367 /* If one side is a PLUS and the other side is a pseudo that
2368 didn't get a hard register but has a reg_equiv_constant,
2369 we must replace the constant here since it may no longer
2370 be in the position of any operand. */
2371 if (GET_CODE (new0) == PLUS && REG_P (new1)
2372 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2373 && reg_renumber[REGNO (new1)] < 0
2374 && reg_equiv_constant != 0
2375 && reg_equiv_constant[REGNO (new1)] != 0)
2376 new1 = reg_equiv_constant[REGNO (new1)];
2377 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2378 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2379 && reg_renumber[REGNO (new0)] < 0
2380 && reg_equiv_constant[REGNO (new0)] != 0)
2381 new0 = reg_equiv_constant[REGNO (new0)];
2383 new = form_sum (new0, new1);
2385 /* As above, if we are not inside a MEM we do not want to
2386 turn a PLUS into something else. We might try to do so here
2387 for an addition of 0 if we aren't optimizing. */
2388 if (! mem_mode && GET_CODE (new) != PLUS)
2389 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2397 /* If this is the product of an eliminable register and a
2398 constant, apply the distribute law and move the constant out
2399 so that we have (plus (mult ..) ..). This is needed in order
2400 to keep load-address insns valid. This case is pathological.
2401 We ignore the possibility of overflow here. */
2402 if (REG_P (XEXP (x, 0))
2403 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2404 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2407 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2410 /* Refs inside notes don't count for this purpose. */
2411 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2412 || GET_CODE (insn) == INSN_LIST)))
2413 ep->ref_outside_mem = 1;
2416 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2417 ep->previous_offset * INTVAL (XEXP (x, 1)));
2420 /* ... fall through ... */
2424 /* See comments before PLUS about handling MINUS. */
2426 case DIV: case UDIV:
2427 case MOD: case UMOD:
2428 case AND: case IOR: case XOR:
2429 case ROTATERT: case ROTATE:
2430 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2432 case GE: case GT: case GEU: case GTU:
2433 case LE: case LT: case LEU: case LTU:
2435 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2437 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2439 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2440 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2445 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2448 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2449 if (new != XEXP (x, 0))
2451 /* If this is a REG_DEAD note, it is not valid anymore.
2452 Using the eliminated version could result in creating a
2453 REG_DEAD note for the stack or frame pointer. */
2454 if (GET_MODE (x) == REG_DEAD)
2456 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2459 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2463 /* ... fall through ... */
2466 /* Now do eliminations in the rest of the chain. If this was
2467 an EXPR_LIST, this might result in allocating more memory than is
2468 strictly needed, but it simplifies the code. */
2471 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2472 if (new != XEXP (x, 1))
2474 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2482 case STRICT_LOW_PART:
2484 case SIGN_EXTEND: case ZERO_EXTEND:
2485 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2486 case FLOAT: case FIX:
2487 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2495 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2496 if (new != XEXP (x, 0))
2497 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2501 /* Similar to above processing, but preserve SUBREG_BYTE.
2502 Convert (subreg (mem)) to (mem) if not paradoxical.
2503 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2504 pseudo didn't get a hard reg, we must replace this with the
2505 eliminated version of the memory location because push_reload
2506 may do the replacement in certain circumstances. */
2507 if (REG_P (SUBREG_REG (x))
2508 && (GET_MODE_SIZE (GET_MODE (x))
2509 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2510 && reg_equiv_memory_loc != 0
2511 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2513 new = SUBREG_REG (x);
2516 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2518 if (new != SUBREG_REG (x))
2520 int x_size = GET_MODE_SIZE (GET_MODE (x));
2521 int new_size = GET_MODE_SIZE (GET_MODE (new));
2524 && ((x_size < new_size
2525 #ifdef WORD_REGISTER_OPERATIONS
2526 /* On these machines, combine can create rtl of the form
2527 (set (subreg:m1 (reg:m2 R) 0) ...)
2528 where m1 < m2, and expects something interesting to
2529 happen to the entire word. Moreover, it will use the
2530 (reg:m2 R) later, expecting all bits to be preserved.
2531 So if the number of words is the same, preserve the
2532 subreg so that push_reload can see it. */
2533 && ! ((x_size - 1) / UNITS_PER_WORD
2534 == (new_size -1 ) / UNITS_PER_WORD)
2537 || x_size == new_size)
2539 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2541 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2547 /* Our only special processing is to pass the mode of the MEM to our
2548 recursive call and copy the flags. While we are here, handle this
2549 case more efficiently. */
2551 replace_equiv_address_nv (x,
2552 eliminate_regs (XEXP (x, 0),
2553 GET_MODE (x), insn));
2556 /* Handle insn_list USE that a call to a pure function may generate. */
2557 new = eliminate_regs (XEXP (x, 0), 0, insn);
2558 if (new != XEXP (x, 0))
2559 return gen_rtx_USE (GET_MODE (x), new);
2571 /* Process each of our operands recursively. If any have changed, make a
2573 fmt = GET_RTX_FORMAT (code);
2574 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2578 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2579 if (new != XEXP (x, i) && ! copied)
2581 rtx new_x = rtx_alloc (code);
2582 memcpy (new_x, x, RTX_SIZE (code));
2588 else if (*fmt == 'E')
2591 for (j = 0; j < XVECLEN (x, i); j++)
2593 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2594 if (new != XVECEXP (x, i, j) && ! copied_vec)
2596 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2600 rtx new_x = rtx_alloc (code);
2601 memcpy (new_x, x, RTX_SIZE (code));
2605 XVEC (x, i) = new_v;
2608 XVECEXP (x, i, j) = new;
2616 /* Scan rtx X for modifications of elimination target registers. Update
2617 the table of eliminables to reflect the changed state. MEM_MODE is
2618 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2621 elimination_effects (rtx x, enum machine_mode mem_mode)
2623 enum rtx_code code = GET_CODE (x);
2624 struct elim_table *ep;
2648 /* First handle the case where we encounter a bare register that
2649 is eliminable. Replace it with a PLUS. */
2650 if (regno < FIRST_PSEUDO_REGISTER)
2652 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2654 if (ep->from_rtx == x && ep->can_eliminate)
2657 ep->ref_outside_mem = 1;
2662 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2663 && reg_equiv_constant[regno]
2664 && ! function_invariant_p (reg_equiv_constant[regno]))
2665 elimination_effects (reg_equiv_constant[regno], mem_mode);
2674 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2675 if (ep->to_rtx == XEXP (x, 0))
2677 int size = GET_MODE_SIZE (mem_mode);
2679 /* If more bytes than MEM_MODE are pushed, account for them. */
2680 #ifdef PUSH_ROUNDING
2681 if (ep->to_rtx == stack_pointer_rtx)
2682 size = PUSH_ROUNDING (size);
2684 if (code == PRE_DEC || code == POST_DEC)
2686 else if (code == PRE_INC || code == POST_INC)
2688 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2689 && GET_CODE (XEXP (x, 1)) == PLUS
2690 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2691 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2692 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2695 /* These two aren't unary operators. */
2696 if (code == POST_MODIFY || code == PRE_MODIFY)
2699 /* Fall through to generic unary operation case. */
2700 case STRICT_LOW_PART:
2702 case SIGN_EXTEND: case ZERO_EXTEND:
2703 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2704 case FLOAT: case FIX:
2705 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2713 elimination_effects (XEXP (x, 0), mem_mode);
2717 if (REG_P (SUBREG_REG (x))
2718 && (GET_MODE_SIZE (GET_MODE (x))
2719 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2720 && reg_equiv_memory_loc != 0
2721 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2724 elimination_effects (SUBREG_REG (x), mem_mode);
2728 /* If using a register that is the source of an eliminate we still
2729 think can be performed, note it cannot be performed since we don't
2730 know how this register is used. */
2731 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2732 if (ep->from_rtx == XEXP (x, 0))
2733 ep->can_eliminate = 0;
2735 elimination_effects (XEXP (x, 0), mem_mode);
2739 /* If clobbering a register that is the replacement register for an
2740 elimination we still think can be performed, note that it cannot
2741 be performed. Otherwise, we need not be concerned about it. */
2742 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2743 if (ep->to_rtx == XEXP (x, 0))
2744 ep->can_eliminate = 0;
2746 elimination_effects (XEXP (x, 0), mem_mode);
2750 /* Check for setting a register that we know about. */
2751 if (REG_P (SET_DEST (x)))
2753 /* See if this is setting the replacement register for an
2756 If DEST is the hard frame pointer, we do nothing because we
2757 assume that all assignments to the frame pointer are for
2758 non-local gotos and are being done at a time when they are valid
2759 and do not disturb anything else. Some machines want to
2760 eliminate a fake argument pointer (or even a fake frame pointer)
2761 with either the real frame or the stack pointer. Assignments to
2762 the hard frame pointer must not prevent this elimination. */
2764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2766 if (ep->to_rtx == SET_DEST (x)
2767 && SET_DEST (x) != hard_frame_pointer_rtx)
2769 /* If it is being incremented, adjust the offset. Otherwise,
2770 this elimination can't be done. */
2771 rtx src = SET_SRC (x);
2773 if (GET_CODE (src) == PLUS
2774 && XEXP (src, 0) == SET_DEST (x)
2775 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2776 ep->offset -= INTVAL (XEXP (src, 1));
2778 ep->can_eliminate = 0;
2782 elimination_effects (SET_DEST (x), 0);
2783 elimination_effects (SET_SRC (x), 0);
2787 /* Our only special processing is to pass the mode of the MEM to our
2789 elimination_effects (XEXP (x, 0), GET_MODE (x));
2796 fmt = GET_RTX_FORMAT (code);
2797 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2800 elimination_effects (XEXP (x, i), mem_mode);
2801 else if (*fmt == 'E')
2802 for (j = 0; j < XVECLEN (x, i); j++)
2803 elimination_effects (XVECEXP (x, i, j), mem_mode);
2807 /* Descend through rtx X and verify that no references to eliminable registers
2808 remain. If any do remain, mark the involved register as not
2812 check_eliminable_occurrences (rtx x)
2821 code = GET_CODE (x);
2823 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2825 struct elim_table *ep;
2827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2828 if (ep->from_rtx == x)
2829 ep->can_eliminate = 0;
2833 fmt = GET_RTX_FORMAT (code);
2834 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2837 check_eliminable_occurrences (XEXP (x, i));
2838 else if (*fmt == 'E')
2841 for (j = 0; j < XVECLEN (x, i); j++)
2842 check_eliminable_occurrences (XVECEXP (x, i, j));
2847 /* Scan INSN and eliminate all eliminable registers in it.
2849 If REPLACE is nonzero, do the replacement destructively. Also
2850 delete the insn as dead it if it is setting an eliminable register.
2852 If REPLACE is zero, do all our allocations in reload_obstack.
2854 If no eliminations were done and this insn doesn't require any elimination
2855 processing (these are not identical conditions: it might be updating sp,
2856 but not referencing fp; this needs to be seen during reload_as_needed so
2857 that the offset between fp and sp can be taken into consideration), zero
2858 is returned. Otherwise, 1 is returned. */
2861 eliminate_regs_in_insn (rtx insn, int replace)
2863 int icode = recog_memoized (insn);
2864 rtx old_body = PATTERN (insn);
2865 int insn_is_asm = asm_noperands (old_body) >= 0;
2866 rtx old_set = single_set (insn);
2870 rtx substed_operand[MAX_RECOG_OPERANDS];
2871 rtx orig_operand[MAX_RECOG_OPERANDS];
2872 struct elim_table *ep;
2875 if (! insn_is_asm && icode < 0)
2877 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2878 || GET_CODE (PATTERN (insn)) == CLOBBER
2879 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2880 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2881 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2885 if (old_set != 0 && REG_P (SET_DEST (old_set))
2886 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2888 /* Check for setting an eliminable register. */
2889 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2890 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2892 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2893 /* If this is setting the frame pointer register to the
2894 hardware frame pointer register and this is an elimination
2895 that will be done (tested above), this insn is really
2896 adjusting the frame pointer downward to compensate for
2897 the adjustment done before a nonlocal goto. */
2898 if (ep->from == FRAME_POINTER_REGNUM
2899 && ep->to == HARD_FRAME_POINTER_REGNUM)
2901 rtx base = SET_SRC (old_set);
2902 rtx base_insn = insn;
2903 HOST_WIDE_INT offset = 0;
2905 while (base != ep->to_rtx)
2907 rtx prev_insn, prev_set;
2909 if (GET_CODE (base) == PLUS
2910 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2912 offset += INTVAL (XEXP (base, 1));
2913 base = XEXP (base, 0);
2915 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2916 && (prev_set = single_set (prev_insn)) != 0
2917 && rtx_equal_p (SET_DEST (prev_set), base))
2919 base = SET_SRC (prev_set);
2920 base_insn = prev_insn;
2926 if (base == ep->to_rtx)
2929 = plus_constant (ep->to_rtx, offset - ep->offset);
2931 new_body = old_body;
2934 new_body = copy_insn (old_body);
2935 if (REG_NOTES (insn))
2936 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2938 PATTERN (insn) = new_body;
2939 old_set = single_set (insn);
2941 /* First see if this insn remains valid when we
2942 make the change. If not, keep the INSN_CODE
2943 the same and let reload fit it up. */
2944 validate_change (insn, &SET_SRC (old_set), src, 1);
2945 validate_change (insn, &SET_DEST (old_set),
2947 if (! apply_change_group ())
2949 SET_SRC (old_set) = src;
2950 SET_DEST (old_set) = ep->to_rtx;
2959 /* In this case this insn isn't serving a useful purpose. We
2960 will delete it in reload_as_needed once we know that this
2961 elimination is, in fact, being done.
2963 If REPLACE isn't set, we can't delete this insn, but needn't
2964 process it since it won't be used unless something changes. */
2967 delete_dead_insn (insn);
2975 /* We allow one special case which happens to work on all machines we
2976 currently support: a single set with the source or a REG_EQUAL
2977 note being a PLUS of an eliminable register and a constant. */
2979 if (old_set && REG_P (SET_DEST (old_set)))
2981 /* First see if the source is of the form (plus (reg) CST). */
2982 if (GET_CODE (SET_SRC (old_set)) == PLUS
2983 && REG_P (XEXP (SET_SRC (old_set), 0))
2984 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2985 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2986 plus_src = SET_SRC (old_set);
2987 else if (REG_P (SET_SRC (old_set)))
2989 /* Otherwise, see if we have a REG_EQUAL note of the form
2990 (plus (reg) CST). */
2992 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2994 if (REG_NOTE_KIND (links) == REG_EQUAL
2995 && GET_CODE (XEXP (links, 0)) == PLUS
2996 && REG_P (XEXP (XEXP (links, 0), 0))
2997 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2998 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3000 plus_src = XEXP (links, 0);
3008 rtx reg = XEXP (plus_src, 0);
3009 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3011 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3012 if (ep->from_rtx == reg && ep->can_eliminate)
3014 offset += ep->offset;
3019 /* We assume here that if we need a PARALLEL with
3020 CLOBBERs for this assignment, we can do with the
3021 MATCH_SCRATCHes that add_clobbers allocates.
3022 There's not much we can do if that doesn't work. */
3023 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3027 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3030 rtvec vec = rtvec_alloc (num_clobbers + 1);
3032 vec->elem[0] = PATTERN (insn);
3033 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3034 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3036 gcc_assert (INSN_CODE (insn) >= 0);
3038 /* If we have a nonzero offset, and the source is already
3039 a simple REG, the following transformation would
3040 increase the cost of the insn by replacing a simple REG
3041 with (plus (reg sp) CST). So try only when plus_src
3042 comes from old_set proper, not REG_NOTES. */
3043 else if (SET_SRC (old_set) == plus_src)
3045 new_body = old_body;
3048 new_body = copy_insn (old_body);
3049 if (REG_NOTES (insn))
3050 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3052 PATTERN (insn) = new_body;
3053 old_set = single_set (insn);
3055 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3056 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3062 /* This can't have an effect on elimination offsets, so skip right
3068 /* Determine the effects of this insn on elimination offsets. */
3069 elimination_effects (old_body, 0);
3071 /* Eliminate all eliminable registers occurring in operands that
3072 can be handled by reload. */
3073 extract_insn (insn);
3074 for (i = 0; i < recog_data.n_operands; i++)
3076 orig_operand[i] = recog_data.operand[i];
3077 substed_operand[i] = recog_data.operand[i];
3079 /* For an asm statement, every operand is eliminable. */
3080 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3082 /* Check for setting a register that we know about. */
3083 if (recog_data.operand_type[i] != OP_IN
3084 && REG_P (orig_operand[i]))
3086 /* If we are assigning to a register that can be eliminated, it
3087 must be as part of a PARALLEL, since the code above handles
3088 single SETs. We must indicate that we can no longer
3089 eliminate this reg. */
3090 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3092 if (ep->from_rtx == orig_operand[i])
3093 ep->can_eliminate = 0;
3096 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3097 replace ? insn : NULL_RTX);
3098 if (substed_operand[i] != orig_operand[i])
3100 /* Terminate the search in check_eliminable_occurrences at
3102 *recog_data.operand_loc[i] = 0;
3104 /* If an output operand changed from a REG to a MEM and INSN is an
3105 insn, write a CLOBBER insn. */
3106 if (recog_data.operand_type[i] != OP_IN
3107 && REG_P (orig_operand[i])
3108 && MEM_P (substed_operand[i])
3110 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3115 for (i = 0; i < recog_data.n_dups; i++)
3116 *recog_data.dup_loc[i]
3117 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3119 /* If any eliminable remain, they aren't eliminable anymore. */
3120 check_eliminable_occurrences (old_body);
3122 /* Substitute the operands; the new values are in the substed_operand
3124 for (i = 0; i < recog_data.n_operands; i++)
3125 *recog_data.operand_loc[i] = substed_operand[i];
3126 for (i = 0; i < recog_data.n_dups; i++)
3127 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3129 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3130 re-recognize the insn. We do this in case we had a simple addition
3131 but now can do this as a load-address. This saves an insn in this
3133 If re-recognition fails, the old insn code number will still be used,
3134 and some register operands may have changed into PLUS expressions.
3135 These will be handled by find_reloads by loading them into a register
3140 /* If we aren't replacing things permanently and we changed something,
3141 make another copy to ensure that all the RTL is new. Otherwise
3142 things can go wrong if find_reload swaps commutative operands
3143 and one is inside RTL that has been copied while the other is not. */
3144 new_body = old_body;
3147 new_body = copy_insn (old_body);
3148 if (REG_NOTES (insn))
3149 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3151 PATTERN (insn) = new_body;
3153 /* If we had a move insn but now we don't, rerecognize it. This will
3154 cause spurious re-recognition if the old move had a PARALLEL since
3155 the new one still will, but we can't call single_set without
3156 having put NEW_BODY into the insn and the re-recognition won't
3157 hurt in this rare case. */
3158 /* ??? Why this huge if statement - why don't we just rerecognize the
3162 && ((REG_P (SET_SRC (old_set))
3163 && (GET_CODE (new_body) != SET
3164 || !REG_P (SET_SRC (new_body))))
3165 /* If this was a load from or store to memory, compare
3166 the MEM in recog_data.operand to the one in the insn.
3167 If they are not equal, then rerecognize the insn. */
3169 && ((MEM_P (SET_SRC (old_set))
3170 && SET_SRC (old_set) != recog_data.operand[1])
3171 || (MEM_P (SET_DEST (old_set))
3172 && SET_DEST (old_set) != recog_data.operand[0])))
3173 /* If this was an add insn before, rerecognize. */
3174 || GET_CODE (SET_SRC (old_set)) == PLUS))
3176 int new_icode = recog (PATTERN (insn), insn, 0);
3178 INSN_CODE (insn) = icode;
3182 /* Restore the old body. If there were any changes to it, we made a copy
3183 of it while the changes were still in place, so we'll correctly return
3184 a modified insn below. */
3187 /* Restore the old body. */
3188 for (i = 0; i < recog_data.n_operands; i++)
3189 *recog_data.operand_loc[i] = orig_operand[i];
3190 for (i = 0; i < recog_data.n_dups; i++)
3191 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3194 /* Update all elimination pairs to reflect the status after the current
3195 insn. The changes we make were determined by the earlier call to
3196 elimination_effects.
3198 We also detect cases where register elimination cannot be done,
3199 namely, if a register would be both changed and referenced outside a MEM
3200 in the resulting insn since such an insn is often undefined and, even if
3201 not, we cannot know what meaning will be given to it. Note that it is
3202 valid to have a register used in an address in an insn that changes it
3203 (presumably with a pre- or post-increment or decrement).
3205 If anything changes, return nonzero. */
3207 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3209 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3210 ep->can_eliminate = 0;
3212 ep->ref_outside_mem = 0;
3214 if (ep->previous_offset != ep->offset)
3219 /* If we changed something, perform elimination in REG_NOTES. This is
3220 needed even when REPLACE is zero because a REG_DEAD note might refer
3221 to a register that we eliminate and could cause a different number
3222 of spill registers to be needed in the final reload pass than in
3224 if (val && REG_NOTES (insn) != 0)
3225 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3230 /* Loop through all elimination pairs.
3231 Recalculate the number not at initial offset.
3233 Compute the maximum offset (minimum offset if the stack does not
3234 grow downward) for each elimination pair. */
3237 update_eliminable_offsets (void)
3239 struct elim_table *ep;
3241 num_not_at_initial_offset = 0;
3242 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3244 ep->previous_offset = ep->offset;
3245 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3246 num_not_at_initial_offset++;
3250 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3251 replacement we currently believe is valid, mark it as not eliminable if X
3252 modifies DEST in any way other than by adding a constant integer to it.
3254 If DEST is the frame pointer, we do nothing because we assume that
3255 all assignments to the hard frame pointer are nonlocal gotos and are being
3256 done at a time when they are valid and do not disturb anything else.
3257 Some machines want to eliminate a fake argument pointer with either the
3258 frame or stack pointer. Assignments to the hard frame pointer must not
3259 prevent this elimination.
3261 Called via note_stores from reload before starting its passes to scan
3262 the insns of the function. */
3265 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3269 /* A SUBREG of a hard register here is just changing its mode. We should
3270 not see a SUBREG of an eliminable hard register, but check just in
3272 if (GET_CODE (dest) == SUBREG)
3273 dest = SUBREG_REG (dest);
3275 if (dest == hard_frame_pointer_rtx)
3278 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3279 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3280 && (GET_CODE (x) != SET
3281 || GET_CODE (SET_SRC (x)) != PLUS
3282 || XEXP (SET_SRC (x), 0) != dest
3283 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3285 reg_eliminate[i].can_eliminate_previous
3286 = reg_eliminate[i].can_eliminate = 0;
3291 /* Verify that the initial elimination offsets did not change since the
3292 last call to set_initial_elim_offsets. This is used to catch cases
3293 where something illegal happened during reload_as_needed that could
3294 cause incorrect code to be generated if we did not check for it. */
3297 verify_initial_elim_offsets (void)
3301 if (!num_eliminable)
3304 #ifdef ELIMINABLE_REGS
3306 struct elim_table *ep;
3308 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3310 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3311 if (t != ep->initial_offset)
3316 INITIAL_FRAME_POINTER_OFFSET (t);
3317 if (t != reg_eliminate[0].initial_offset)
3324 /* Reset all offsets on eliminable registers to their initial values. */
3327 set_initial_elim_offsets (void)
3329 struct elim_table *ep = reg_eliminate;
3331 #ifdef ELIMINABLE_REGS
3332 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3334 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3335 ep->previous_offset = ep->offset = ep->initial_offset;
3338 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3339 ep->previous_offset = ep->offset = ep->initial_offset;
3342 num_not_at_initial_offset = 0;
3345 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3348 set_initial_eh_label_offset (rtx label)
3350 set_label_offsets (label, NULL_RTX, 1);
3353 /* Initialize the known label offsets.
3354 Set a known offset for each forced label to be at the initial offset
3355 of each elimination. We do this because we assume that all
3356 computed jumps occur from a location where each elimination is
3357 at its initial offset.
3358 For all other labels, show that we don't know the offsets. */
3361 set_initial_label_offsets (void)
3364 memset (offsets_known_at, 0, num_labels);
3366 for (x = forced_labels; x; x = XEXP (x, 1))
3368 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3370 for_each_eh_label (set_initial_eh_label_offset);
3373 /* Set all elimination offsets to the known values for the code label given
3377 set_offsets_for_label (rtx insn)
3380 int label_nr = CODE_LABEL_NUMBER (insn);
3381 struct elim_table *ep;
3383 num_not_at_initial_offset = 0;
3384 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3386 ep->offset = ep->previous_offset
3387 = offsets_at[label_nr - first_label_num][i];
3388 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3389 num_not_at_initial_offset++;
3393 /* See if anything that happened changes which eliminations are valid.
3394 For example, on the SPARC, whether or not the frame pointer can
3395 be eliminated can depend on what registers have been used. We need
3396 not check some conditions again (such as flag_omit_frame_pointer)
3397 since they can't have changed. */
3400 update_eliminables (HARD_REG_SET *pset)
3402 int previous_frame_pointer_needed = frame_pointer_needed;
3403 struct elim_table *ep;
3405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3406 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3407 #ifdef ELIMINABLE_REGS
3408 || ! CAN_ELIMINATE (ep->from, ep->to)
3411 ep->can_eliminate = 0;
3413 /* Look for the case where we have discovered that we can't replace
3414 register A with register B and that means that we will now be
3415 trying to replace register A with register C. This means we can
3416 no longer replace register C with register B and we need to disable
3417 such an elimination, if it exists. This occurs often with A == ap,
3418 B == sp, and C == fp. */
3420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3422 struct elim_table *op;
3425 if (! ep->can_eliminate && ep->can_eliminate_previous)
3427 /* Find the current elimination for ep->from, if there is a
3429 for (op = reg_eliminate;
3430 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3431 if (op->from == ep->from && op->can_eliminate)
3437 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3439 for (op = reg_eliminate;
3440 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3441 if (op->from == new_to && op->to == ep->to)
3442 op->can_eliminate = 0;
3446 /* See if any registers that we thought we could eliminate the previous
3447 time are no longer eliminable. If so, something has changed and we
3448 must spill the register. Also, recompute the number of eliminable
3449 registers and see if the frame pointer is needed; it is if there is
3450 no elimination of the frame pointer that we can perform. */
3452 frame_pointer_needed = 1;
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3456 && ep->to != HARD_FRAME_POINTER_REGNUM)
3457 frame_pointer_needed = 0;
3459 if (! ep->can_eliminate && ep->can_eliminate_previous)
3461 ep->can_eliminate_previous = 0;
3462 SET_HARD_REG_BIT (*pset, ep->from);
3467 /* If we didn't need a frame pointer last time, but we do now, spill
3468 the hard frame pointer. */
3469 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3470 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3473 /* Initialize the table of registers to eliminate. */
3476 init_elim_table (void)
3478 struct elim_table *ep;
3479 #ifdef ELIMINABLE_REGS
3480 const struct elim_table_1 *ep1;
3484 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3486 /* Does this function require a frame pointer? */
3488 frame_pointer_needed = (! flag_omit_frame_pointer
3489 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3490 and restore sp for alloca. So we can't eliminate
3491 the frame pointer in that case. At some point,
3492 we should improve this by emitting the
3493 sp-adjusting insns for this case. */
3494 || (current_function_calls_alloca
3495 && EXIT_IGNORE_STACK)
3496 || current_function_accesses_prior_frames
3497 || FRAME_POINTER_REQUIRED);
3501 #ifdef ELIMINABLE_REGS
3502 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3503 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3505 ep->from = ep1->from;
3507 ep->can_eliminate = ep->can_eliminate_previous
3508 = (CAN_ELIMINATE (ep->from, ep->to)
3509 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3512 reg_eliminate[0].from = reg_eliminate_1[0].from;
3513 reg_eliminate[0].to = reg_eliminate_1[0].to;
3514 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3515 = ! frame_pointer_needed;
3518 /* Count the number of eliminable registers and build the FROM and TO
3519 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3520 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3521 We depend on this. */
3522 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3524 num_eliminable += ep->can_eliminate;
3525 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3526 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3530 /* Kick all pseudos out of hard register REGNO.
3532 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3533 because we found we can't eliminate some register. In the case, no pseudos
3534 are allowed to be in the register, even if they are only in a block that
3535 doesn't require spill registers, unlike the case when we are spilling this
3536 hard reg to produce another spill register.
3538 Return nonzero if any pseudos needed to be kicked out. */
3541 spill_hard_reg (unsigned int regno, int cant_eliminate)
3547 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3548 regs_ever_live[regno] = 1;
3551 /* Spill every pseudo reg that was allocated to this reg
3552 or to something that overlaps this reg. */
3554 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3555 if (reg_renumber[i] >= 0
3556 && (unsigned int) reg_renumber[i] <= regno
3557 && ((unsigned int) reg_renumber[i]
3558 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3559 [PSEUDO_REGNO_MODE (i)]
3561 SET_REGNO_REG_SET (&spilled_pseudos, i);
3564 /* After find_reload_regs has been run for all insn that need reloads,
3565 and/or spill_hard_regs was called, this function is used to actually
3566 spill pseudo registers and try to reallocate them. It also sets up the
3567 spill_regs array for use by choose_reload_regs. */
3570 finish_spills (int global)
3572 struct insn_chain *chain;
3573 int something_changed = 0;
3575 reg_set_iterator rsi;
3577 /* Build the spill_regs array for the function. */
3578 /* If there are some registers still to eliminate and one of the spill regs
3579 wasn't ever used before, additional stack space may have to be
3580 allocated to store this register. Thus, we may have changed the offset
3581 between the stack and frame pointers, so mark that something has changed.
3583 One might think that we need only set VAL to 1 if this is a call-used
3584 register. However, the set of registers that must be saved by the
3585 prologue is not identical to the call-used set. For example, the
3586 register used by the call insn for the return PC is a call-used register,
3587 but must be saved by the prologue. */
3590 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3591 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3593 spill_reg_order[i] = n_spills;
3594 spill_regs[n_spills++] = i;
3595 if (num_eliminable && ! regs_ever_live[i])
3596 something_changed = 1;
3597 regs_ever_live[i] = 1;
3600 spill_reg_order[i] = -1;
3602 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3604 /* Record the current hard register the pseudo is allocated to in
3605 pseudo_previous_regs so we avoid reallocating it to the same
3606 hard reg in a later pass. */
3607 gcc_assert (reg_renumber[i] >= 0);
3609 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3610 /* Mark it as no longer having a hard register home. */
3611 reg_renumber[i] = -1;
3612 /* We will need to scan everything again. */
3613 something_changed = 1;
3616 /* Retry global register allocation if possible. */
3619 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3620 /* For every insn that needs reloads, set the registers used as spill
3621 regs in pseudo_forbidden_regs for every pseudo live across the
3623 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3625 EXECUTE_IF_SET_IN_REG_SET
3626 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3628 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3629 chain->used_spill_regs);
3631 EXECUTE_IF_SET_IN_REG_SET
3632 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3634 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3635 chain->used_spill_regs);
3639 /* Retry allocating the spilled pseudos. For each reg, merge the
3640 various reg sets that indicate which hard regs can't be used,
3641 and call retry_global_alloc.
3642 We change spill_pseudos here to only contain pseudos that did not
3643 get a new hard register. */
3644 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3645 if (reg_old_renumber[i] != reg_renumber[i])
3647 HARD_REG_SET forbidden;
3648 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3649 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3650 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3651 retry_global_alloc (i, forbidden);
3652 if (reg_renumber[i] >= 0)
3653 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3657 /* Fix up the register information in the insn chain.
3658 This involves deleting those of the spilled pseudos which did not get
3659 a new hard register home from the live_{before,after} sets. */
3660 for (chain = reload_insn_chain; chain; chain = chain->next)
3662 HARD_REG_SET used_by_pseudos;
3663 HARD_REG_SET used_by_pseudos2;
3665 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3666 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3668 /* Mark any unallocated hard regs as available for spills. That
3669 makes inheritance work somewhat better. */
3670 if (chain->need_reload)
3672 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3673 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3674 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3676 /* Save the old value for the sanity test below. */
3677 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3679 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3680 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3681 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3682 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3684 /* Make sure we only enlarge the set. */
3685 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3691 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3692 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3694 int regno = reg_renumber[i];
3695 if (reg_old_renumber[i] == regno)
3698 alter_reg (i, reg_old_renumber[i]);
3699 reg_old_renumber[i] = regno;
3703 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3705 fprintf (dump_file, " Register %d now in %d.\n\n",
3706 i, reg_renumber[i]);
3710 return something_changed;
3713 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3716 scan_paradoxical_subregs (rtx x)
3720 enum rtx_code code = GET_CODE (x);
3730 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3738 if (REG_P (SUBREG_REG (x))
3739 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3740 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3741 = GET_MODE_SIZE (GET_MODE (x));
3748 fmt = GET_RTX_FORMAT (code);
3749 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3752 scan_paradoxical_subregs (XEXP (x, i));
3753 else if (fmt[i] == 'E')
3756 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3757 scan_paradoxical_subregs (XVECEXP (x, i, j));
3762 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3763 examine all of the reload insns between PREV and NEXT exclusive, and
3764 annotate all that may trap. */
3767 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3769 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3770 unsigned int trap_count;
3776 if (may_trap_p (PATTERN (insn)))
3780 remove_note (insn, note);
3784 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3785 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3789 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3793 /* Reload pseudo-registers into hard regs around each insn as needed.
3794 Additional register load insns are output before the insn that needs it
3795 and perhaps store insns after insns that modify the reloaded pseudo reg.
3797 reg_last_reload_reg and reg_reloaded_contents keep track of
3798 which registers are already available in reload registers.
3799 We update these for the reloads that we perform,
3800 as the insns are scanned. */
3803 reload_as_needed (int live_known)
3805 struct insn_chain *chain;
3806 #if defined (AUTO_INC_DEC)
3811 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3812 memset (spill_reg_store, 0, sizeof spill_reg_store);
3813 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3814 reg_has_output_reload = xmalloc (max_regno);
3815 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3816 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3818 set_initial_elim_offsets ();
3820 for (chain = reload_insn_chain; chain; chain = chain->next)
3823 rtx insn = chain->insn;
3824 rtx old_next = NEXT_INSN (insn);
3826 /* If we pass a label, copy the offsets from the label information
3827 into the current offsets of each elimination. */
3829 set_offsets_for_label (insn);
3831 else if (INSN_P (insn))
3833 rtx oldpat = copy_rtx (PATTERN (insn));
3835 /* If this is a USE and CLOBBER of a MEM, ensure that any
3836 references to eliminable registers have been removed. */
3838 if ((GET_CODE (PATTERN (insn)) == USE
3839 || GET_CODE (PATTERN (insn)) == CLOBBER)
3840 && MEM_P (XEXP (PATTERN (insn), 0)))
3841 XEXP (XEXP (PATTERN (insn), 0), 0)
3842 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3843 GET_MODE (XEXP (PATTERN (insn), 0)),
3846 /* If we need to do register elimination processing, do so.
3847 This might delete the insn, in which case we are done. */
3848 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3850 eliminate_regs_in_insn (insn, 1);
3853 update_eliminable_offsets ();
3858 /* If need_elim is nonzero but need_reload is zero, one might think
3859 that we could simply set n_reloads to 0. However, find_reloads
3860 could have done some manipulation of the insn (such as swapping
3861 commutative operands), and these manipulations are lost during
3862 the first pass for every insn that needs register elimination.
3863 So the actions of find_reloads must be redone here. */
3865 if (! chain->need_elim && ! chain->need_reload
3866 && ! chain->need_operand_change)
3868 /* First find the pseudo regs that must be reloaded for this insn.
3869 This info is returned in the tables reload_... (see reload.h).
3870 Also modify the body of INSN by substituting RELOAD
3871 rtx's for those pseudo regs. */
3874 memset (reg_has_output_reload, 0, max_regno);
3875 CLEAR_HARD_REG_SET (reg_is_output_reload);
3877 find_reloads (insn, 1, spill_indirect_levels, live_known,
3883 rtx next = NEXT_INSN (insn);
3886 prev = PREV_INSN (insn);
3888 /* Now compute which reload regs to reload them into. Perhaps
3889 reusing reload regs from previous insns, or else output
3890 load insns to reload them. Maybe output store insns too.
3891 Record the choices of reload reg in reload_reg_rtx. */
3892 choose_reload_regs (chain);
3894 /* Merge any reloads that we didn't combine for fear of
3895 increasing the number of spill registers needed but now
3896 discover can be safely merged. */
3897 if (SMALL_REGISTER_CLASSES)
3898 merge_assigned_reloads (insn);
3900 /* Generate the insns to reload operands into or out of
3901 their reload regs. */
3902 emit_reload_insns (chain);
3904 /* Substitute the chosen reload regs from reload_reg_rtx
3905 into the insn's body (or perhaps into the bodies of other
3906 load and store insn that we just made for reloading
3907 and that we moved the structure into). */
3908 subst_reloads (insn);
3910 /* Adjust the exception region notes for loads and stores. */
3911 if (flag_non_call_exceptions && !CALL_P (insn))
3912 fixup_eh_region_note (insn, prev, next);
3914 /* If this was an ASM, make sure that all the reload insns
3915 we have generated are valid. If not, give an error
3917 if (asm_noperands (PATTERN (insn)) >= 0)
3918 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3919 if (p != insn && INSN_P (p)
3920 && GET_CODE (PATTERN (p)) != USE
3921 && (recog_memoized (p) < 0
3922 || (extract_insn (p), ! constrain_operands (1))))
3924 error_for_asm (insn,
3925 "%<asm%> operand requires "
3926 "impossible reload");
3931 if (num_eliminable && chain->need_elim)
3932 update_eliminable_offsets ();
3934 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3935 is no longer validly lying around to save a future reload.
3936 Note that this does not detect pseudos that were reloaded
3937 for this insn in order to be stored in
3938 (obeying register constraints). That is correct; such reload
3939 registers ARE still valid. */
3940 note_stores (oldpat, forget_old_reloads_1, NULL);
3942 /* There may have been CLOBBER insns placed after INSN. So scan
3943 between INSN and NEXT and use them to forget old reloads. */
3944 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3945 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3946 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3949 /* Likewise for regs altered by auto-increment in this insn.
3950 REG_INC notes have been changed by reloading:
3951 find_reloads_address_1 records substitutions for them,
3952 which have been performed by subst_reloads above. */
3953 for (i = n_reloads - 1; i >= 0; i--)
3955 rtx in_reg = rld[i].in_reg;
3958 enum rtx_code code = GET_CODE (in_reg);
3959 /* PRE_INC / PRE_DEC will have the reload register ending up
3960 with the same value as the stack slot, but that doesn't
3961 hold true for POST_INC / POST_DEC. Either we have to
3962 convert the memory access to a true POST_INC / POST_DEC,
3963 or we can't use the reload register for inheritance. */
3964 if ((code == POST_INC || code == POST_DEC)
3965 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3966 REGNO (rld[i].reg_rtx))
3967 /* Make sure it is the inc/dec pseudo, and not
3968 some other (e.g. output operand) pseudo. */
3969 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3970 == REGNO (XEXP (in_reg, 0))))
3973 rtx reload_reg = rld[i].reg_rtx;
3974 enum machine_mode mode = GET_MODE (reload_reg);
3978 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3980 /* We really want to ignore REG_INC notes here, so
3981 use PATTERN (p) as argument to reg_set_p . */
3982 if (reg_set_p (reload_reg, PATTERN (p)))
3984 n = count_occurrences (PATTERN (p), reload_reg, 0);
3989 n = validate_replace_rtx (reload_reg,
3990 gen_rtx_fmt_e (code,
3995 /* We must also verify that the constraints
3996 are met after the replacement. */
3999 n = constrain_operands (1);
4003 /* If the constraints were not met, then
4004 undo the replacement. */
4007 validate_replace_rtx (gen_rtx_fmt_e (code,
4020 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4022 /* Mark this as having an output reload so that the
4023 REG_INC processing code below won't invalidate
4024 the reload for inheritance. */
4025 SET_HARD_REG_BIT (reg_is_output_reload,
4026 REGNO (reload_reg));
4027 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4030 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4033 else if ((code == PRE_INC || code == PRE_DEC)
4034 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4035 REGNO (rld[i].reg_rtx))
4036 /* Make sure it is the inc/dec pseudo, and not
4037 some other (e.g. output operand) pseudo. */
4038 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4039 == REGNO (XEXP (in_reg, 0))))
4041 SET_HARD_REG_BIT (reg_is_output_reload,
4042 REGNO (rld[i].reg_rtx));
4043 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4047 /* If a pseudo that got a hard register is auto-incremented,
4048 we must purge records of copying it into pseudos without
4050 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4051 if (REG_NOTE_KIND (x) == REG_INC)
4053 /* See if this pseudo reg was reloaded in this insn.
4054 If so, its last-reload info is still valid
4055 because it is based on this insn's reload. */
4056 for (i = 0; i < n_reloads; i++)
4057 if (rld[i].out == XEXP (x, 0))
4061 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4065 /* A reload reg's contents are unknown after a label. */
4067 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4069 /* Don't assume a reload reg is still good after a call insn
4070 if it is a call-used reg, or if it contains a value that will
4071 be partially clobbered by the call. */
4072 else if (CALL_P (insn))
4074 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4075 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4080 free (reg_last_reload_reg);
4081 free (reg_has_output_reload);
4084 /* Discard all record of any value reloaded from X,
4085 or reloaded in X from someplace else;
4086 unless X is an output reload reg of the current insn.
4088 X may be a hard reg (the reload reg)
4089 or it may be a pseudo reg that was reloaded from. */
4092 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4093 void *data ATTRIBUTE_UNUSED)
4098 /* note_stores does give us subregs of hard regs,
4099 subreg_regno_offset requires a hard reg. */
4100 while (GET_CODE (x) == SUBREG)
4102 /* We ignore the subreg offset when calculating the regno,
4103 because we are using the entire underlying hard register
4113 if (regno >= FIRST_PSEUDO_REGISTER)
4119 nr = hard_regno_nregs[regno][GET_MODE (x)];
4120 /* Storing into a spilled-reg invalidates its contents.
4121 This can happen if a block-local pseudo is allocated to that reg
4122 and it wasn't spilled because this block's total need is 0.
4123 Then some insn might have an optional reload and use this reg. */
4124 for (i = 0; i < nr; i++)
4125 /* But don't do this if the reg actually serves as an output
4126 reload reg in the current instruction. */
4128 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4130 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4131 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4132 spill_reg_store[regno + i] = 0;
4136 /* Since value of X has changed,
4137 forget any value previously copied from it. */
4140 /* But don't forget a copy if this is the output reload
4141 that establishes the copy's validity. */
4142 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4143 reg_last_reload_reg[regno + nr] = 0;
4146 /* The following HARD_REG_SETs indicate when each hard register is
4147 used for a reload of various parts of the current insn. */
4149 /* If reg is unavailable for all reloads. */
4150 static HARD_REG_SET reload_reg_unavailable;
4151 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4152 static HARD_REG_SET reload_reg_used;
4153 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4154 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4155 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4156 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4157 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4158 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4159 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4160 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4161 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4162 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4163 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4164 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4165 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4166 static HARD_REG_SET reload_reg_used_in_op_addr;
4167 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4168 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4169 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4170 static HARD_REG_SET reload_reg_used_in_insn;
4171 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4172 static HARD_REG_SET reload_reg_used_in_other_addr;
4174 /* If reg is in use as a reload reg for any sort of reload. */
4175 static HARD_REG_SET reload_reg_used_at_all;
4177 /* If reg is use as an inherited reload. We just mark the first register
4179 static HARD_REG_SET reload_reg_used_for_inherit;
4181 /* Records which hard regs are used in any way, either as explicit use or
4182 by being allocated to a pseudo during any point of the current insn. */
4183 static HARD_REG_SET reg_used_in_insn;
4185 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4186 TYPE. MODE is used to indicate how many consecutive regs are
4190 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4191 enum machine_mode mode)
4193 unsigned int nregs = hard_regno_nregs[regno][mode];
4196 for (i = regno; i < nregs + regno; i++)
4201 SET_HARD_REG_BIT (reload_reg_used, i);
4204 case RELOAD_FOR_INPUT_ADDRESS:
4205 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4208 case RELOAD_FOR_INPADDR_ADDRESS:
4209 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4212 case RELOAD_FOR_OUTPUT_ADDRESS:
4213 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4216 case RELOAD_FOR_OUTADDR_ADDRESS:
4217 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4220 case RELOAD_FOR_OPERAND_ADDRESS:
4221 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4224 case RELOAD_FOR_OPADDR_ADDR:
4225 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4228 case RELOAD_FOR_OTHER_ADDRESS:
4229 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4232 case RELOAD_FOR_INPUT:
4233 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4236 case RELOAD_FOR_OUTPUT:
4237 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4240 case RELOAD_FOR_INSN:
4241 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4245 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4249 /* Similarly, but show REGNO is no longer in use for a reload. */
4252 clear_reload_reg_in_use (unsigned int regno, int opnum,
4253 enum reload_type type, enum machine_mode mode)
4255 unsigned int nregs = hard_regno_nregs[regno][mode];
4256 unsigned int start_regno, end_regno, r;
4258 /* A complication is that for some reload types, inheritance might
4259 allow multiple reloads of the same types to share a reload register.
4260 We set check_opnum if we have to check only reloads with the same
4261 operand number, and check_any if we have to check all reloads. */
4262 int check_opnum = 0;
4264 HARD_REG_SET *used_in_set;
4269 used_in_set = &reload_reg_used;
4272 case RELOAD_FOR_INPUT_ADDRESS:
4273 used_in_set = &reload_reg_used_in_input_addr[opnum];
4276 case RELOAD_FOR_INPADDR_ADDRESS:
4278 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4281 case RELOAD_FOR_OUTPUT_ADDRESS:
4282 used_in_set = &reload_reg_used_in_output_addr[opnum];
4285 case RELOAD_FOR_OUTADDR_ADDRESS:
4287 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4290 case RELOAD_FOR_OPERAND_ADDRESS:
4291 used_in_set = &reload_reg_used_in_op_addr;
4294 case RELOAD_FOR_OPADDR_ADDR:
4296 used_in_set = &reload_reg_used_in_op_addr_reload;
4299 case RELOAD_FOR_OTHER_ADDRESS:
4300 used_in_set = &reload_reg_used_in_other_addr;
4304 case RELOAD_FOR_INPUT:
4305 used_in_set = &reload_reg_used_in_input[opnum];
4308 case RELOAD_FOR_OUTPUT:
4309 used_in_set = &reload_reg_used_in_output[opnum];
4312 case RELOAD_FOR_INSN:
4313 used_in_set = &reload_reg_used_in_insn;
4318 /* We resolve conflicts with remaining reloads of the same type by
4319 excluding the intervals of reload registers by them from the
4320 interval of freed reload registers. Since we only keep track of
4321 one set of interval bounds, we might have to exclude somewhat
4322 more than what would be necessary if we used a HARD_REG_SET here.
4323 But this should only happen very infrequently, so there should
4324 be no reason to worry about it. */
4326 start_regno = regno;
4327 end_regno = regno + nregs;
4328 if (check_opnum || check_any)
4330 for (i = n_reloads - 1; i >= 0; i--)
4332 if (rld[i].when_needed == type
4333 && (check_any || rld[i].opnum == opnum)
4336 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4337 unsigned int conflict_end
4339 + hard_regno_nregs[conflict_start][rld[i].mode]);
4341 /* If there is an overlap with the first to-be-freed register,
4342 adjust the interval start. */
4343 if (conflict_start <= start_regno && conflict_end > start_regno)
4344 start_regno = conflict_end;
4345 /* Otherwise, if there is a conflict with one of the other
4346 to-be-freed registers, adjust the interval end. */
4347 if (conflict_start > start_regno && conflict_start < end_regno)
4348 end_regno = conflict_start;
4353 for (r = start_regno; r < end_regno; r++)
4354 CLEAR_HARD_REG_BIT (*used_in_set, r);
4357 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4358 specified by OPNUM and TYPE. */
4361 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4365 /* In use for a RELOAD_OTHER means it's not available for anything. */
4366 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4367 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4373 /* In use for anything means we can't use it for RELOAD_OTHER. */
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4375 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4376 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4377 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4380 for (i = 0; i < reload_n_operands; i++)
4381 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4384 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4386 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4391 case RELOAD_FOR_INPUT:
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4399 /* If it is used for some other input, can't use it. */
4400 for (i = 0; i < reload_n_operands; i++)
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4404 /* If it is used in a later operand's address, can't use it. */
4405 for (i = opnum + 1; i < reload_n_operands; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4407 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4412 case RELOAD_FOR_INPUT_ADDRESS:
4413 /* Can't use a register if it is used for an input address for this
4414 operand or used as an input in an earlier one. */
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4416 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4419 for (i = 0; i < opnum; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4425 case RELOAD_FOR_INPADDR_ADDRESS:
4426 /* Can't use a register if it is used for an input address
4427 for this operand or used as an input in an earlier
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4432 for (i = 0; i < opnum; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4438 case RELOAD_FOR_OUTPUT_ADDRESS:
4439 /* Can't use a register if it is used for an output address for this
4440 operand or used as an output in this or a later operand. Note
4441 that multiple output operands are emitted in reverse order, so
4442 the conflicting ones are those with lower indices. */
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4446 for (i = 0; i <= opnum; i++)
4447 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4452 case RELOAD_FOR_OUTADDR_ADDRESS:
4453 /* Can't use a register if it is used for an output address
4454 for this operand or used as an output in this or a
4455 later operand. Note that multiple output operands are
4456 emitted in reverse order, so the conflicting ones are
4457 those with lower indices. */
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4461 for (i = 0; i <= opnum; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4467 case RELOAD_FOR_OPERAND_ADDRESS:
4468 for (i = 0; i < reload_n_operands; i++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4472 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4473 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4475 case RELOAD_FOR_OPADDR_ADDR:
4476 for (i = 0; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4480 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4482 case RELOAD_FOR_OUTPUT:
4483 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4484 outputs, or an operand address for this or an earlier output.
4485 Note that multiple output operands are emitted in reverse order,
4486 so the conflicting ones are those with higher indices. */
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4490 for (i = 0; i < reload_n_operands; i++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4494 for (i = opnum; i < reload_n_operands; i++)
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4501 case RELOAD_FOR_INSN:
4502 for (i = 0; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4507 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4508 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4510 case RELOAD_FOR_OTHER_ADDRESS:
4511 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4518 /* Return 1 if the value in reload reg REGNO, as used by a reload
4519 needed for the part of the insn specified by OPNUM and TYPE,
4520 is still available in REGNO at the end of the insn.
4522 We can assume that the reload reg was already tested for availability
4523 at the time it is needed, and we should not check this again,
4524 in case the reg has already been marked in use. */
4527 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4534 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4535 its value must reach the end. */
4538 /* If this use is for part of the insn,
4539 its value reaches if no subsequent part uses the same register.
4540 Just like the above function, don't try to do this with lots
4543 case RELOAD_FOR_OTHER_ADDRESS:
4544 /* Here we check for everything else, since these don't conflict
4545 with anything else and everything comes later. */
4547 for (i = 0; i < reload_n_operands; i++)
4548 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4551 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4556 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4557 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4558 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4559 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4561 case RELOAD_FOR_INPUT_ADDRESS:
4562 case RELOAD_FOR_INPADDR_ADDRESS:
4563 /* Similar, except that we check only for this and subsequent inputs
4564 and the address of only subsequent inputs and we do not need
4565 to check for RELOAD_OTHER objects since they are known not to
4568 for (i = opnum; i < reload_n_operands; i++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4572 for (i = opnum + 1; i < reload_n_operands; i++)
4573 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4577 for (i = 0; i < reload_n_operands; i++)
4578 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4586 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4587 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4588 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4590 case RELOAD_FOR_INPUT:
4591 /* Similar to input address, except we start at the next operand for
4592 both input and input address and we do not check for
4593 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4596 for (i = opnum + 1; i < reload_n_operands; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4598 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4599 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4602 /* ... fall through ... */
4604 case RELOAD_FOR_OPERAND_ADDRESS:
4605 /* Check outputs and their addresses. */
4607 for (i = 0; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4613 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4615 case RELOAD_FOR_OPADDR_ADDR:
4616 for (i = 0; i < reload_n_operands; i++)
4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4622 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4623 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4624 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4626 case RELOAD_FOR_INSN:
4627 /* These conflict with other outputs with RELOAD_OTHER. So
4628 we need only check for output addresses. */
4630 opnum = reload_n_operands;
4632 /* ... fall through ... */
4634 case RELOAD_FOR_OUTPUT:
4635 case RELOAD_FOR_OUTPUT_ADDRESS:
4636 case RELOAD_FOR_OUTADDR_ADDRESS:
4637 /* We already know these can't conflict with a later output. So the
4638 only thing to check are later output addresses.
4639 Note that multiple output operands are emitted in reverse order,
4640 so the conflicting ones are those with lower indices. */
4641 for (i = 0; i < opnum; i++)
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4653 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4656 This function uses the same algorithm as reload_reg_free_p above. */
4659 reloads_conflict (int r1, int r2)
4661 enum reload_type r1_type = rld[r1].when_needed;
4662 enum reload_type r2_type = rld[r2].when_needed;
4663 int r1_opnum = rld[r1].opnum;
4664 int r2_opnum = rld[r2].opnum;
4666 /* RELOAD_OTHER conflicts with everything. */
4667 if (r2_type == RELOAD_OTHER)
4670 /* Otherwise, check conflicts differently for each type. */
4674 case RELOAD_FOR_INPUT:
4675 return (r2_type == RELOAD_FOR_INSN
4676 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4677 || r2_type == RELOAD_FOR_OPADDR_ADDR
4678 || r2_type == RELOAD_FOR_INPUT
4679 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4680 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4681 && r2_opnum > r1_opnum));
4683 case RELOAD_FOR_INPUT_ADDRESS:
4684 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4685 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4687 case RELOAD_FOR_INPADDR_ADDRESS:
4688 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4689 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4691 case RELOAD_FOR_OUTPUT_ADDRESS:
4692 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4693 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4695 case RELOAD_FOR_OUTADDR_ADDRESS:
4696 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4697 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4699 case RELOAD_FOR_OPERAND_ADDRESS:
4700 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4701 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4703 case RELOAD_FOR_OPADDR_ADDR:
4704 return (r2_type == RELOAD_FOR_INPUT
4705 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4707 case RELOAD_FOR_OUTPUT:
4708 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4709 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4710 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4711 && r2_opnum >= r1_opnum));
4713 case RELOAD_FOR_INSN:
4714 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4715 || r2_type == RELOAD_FOR_INSN
4716 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4718 case RELOAD_FOR_OTHER_ADDRESS:
4719 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4729 /* Indexed by reload number, 1 if incoming value
4730 inherited from previous insns. */
4731 static char reload_inherited[MAX_RELOADS];
4733 /* For an inherited reload, this is the insn the reload was inherited from,
4734 if we know it. Otherwise, this is 0. */
4735 static rtx reload_inheritance_insn[MAX_RELOADS];
4737 /* If nonzero, this is a place to get the value of the reload,
4738 rather than using reload_in. */
4739 static rtx reload_override_in[MAX_RELOADS];
4741 /* For each reload, the hard register number of the register used,
4742 or -1 if we did not need a register for this reload. */
4743 static int reload_spill_index[MAX_RELOADS];
4745 /* Subroutine of free_for_value_p, used to check a single register.
4746 START_REGNO is the starting regno of the full reload register
4747 (possibly comprising multiple hard registers) that we are considering. */
4750 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4751 enum reload_type type, rtx value, rtx out,
4752 int reloadnum, int ignore_address_reloads)
4755 /* Set if we see an input reload that must not share its reload register
4756 with any new earlyclobber, but might otherwise share the reload
4757 register with an output or input-output reload. */
4758 int check_earlyclobber = 0;
4762 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4765 if (out == const0_rtx)
4771 /* We use some pseudo 'time' value to check if the lifetimes of the
4772 new register use would overlap with the one of a previous reload
4773 that is not read-only or uses a different value.
4774 The 'time' used doesn't have to be linear in any shape or form, just
4776 Some reload types use different 'buckets' for each operand.
4777 So there are MAX_RECOG_OPERANDS different time values for each
4779 We compute TIME1 as the time when the register for the prospective
4780 new reload ceases to be live, and TIME2 for each existing
4781 reload as the time when that the reload register of that reload
4783 Where there is little to be gained by exact lifetime calculations,
4784 we just make conservative assumptions, i.e. a longer lifetime;
4785 this is done in the 'default:' cases. */
4788 case RELOAD_FOR_OTHER_ADDRESS:
4789 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4790 time1 = copy ? 0 : 1;
4793 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4795 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4796 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4797 respectively, to the time values for these, we get distinct time
4798 values. To get distinct time values for each operand, we have to
4799 multiply opnum by at least three. We round that up to four because
4800 multiply by four is often cheaper. */
4801 case RELOAD_FOR_INPADDR_ADDRESS:
4802 time1 = opnum * 4 + 2;
4804 case RELOAD_FOR_INPUT_ADDRESS:
4805 time1 = opnum * 4 + 3;
4807 case RELOAD_FOR_INPUT:
4808 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4809 executes (inclusive). */
4810 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4812 case RELOAD_FOR_OPADDR_ADDR:
4814 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4815 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4817 case RELOAD_FOR_OPERAND_ADDRESS:
4818 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4820 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4822 case RELOAD_FOR_OUTADDR_ADDRESS:
4823 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4825 case RELOAD_FOR_OUTPUT_ADDRESS:
4826 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4829 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4832 for (i = 0; i < n_reloads; i++)
4834 rtx reg = rld[i].reg_rtx;
4835 if (reg && REG_P (reg)
4836 && ((unsigned) regno - true_regnum (reg)
4837 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4840 rtx other_input = rld[i].in;
4842 /* If the other reload loads the same input value, that
4843 will not cause a conflict only if it's loading it into
4844 the same register. */
4845 if (true_regnum (reg) != start_regno)
4846 other_input = NULL_RTX;
4847 if (! other_input || ! rtx_equal_p (other_input, value)
4848 || rld[i].out || out)
4851 switch (rld[i].when_needed)
4853 case RELOAD_FOR_OTHER_ADDRESS:
4856 case RELOAD_FOR_INPADDR_ADDRESS:
4857 /* find_reloads makes sure that a
4858 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4859 by at most one - the first -
4860 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4861 address reload is inherited, the address address reload
4862 goes away, so we can ignore this conflict. */
4863 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4864 && ignore_address_reloads
4865 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4866 Then the address address is still needed to store
4867 back the new address. */
4868 && ! rld[reloadnum].out)
4870 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4871 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4873 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4874 && ignore_address_reloads
4875 /* Unless we are reloading an auto_inc expression. */
4876 && ! rld[reloadnum].out)
4878 time2 = rld[i].opnum * 4 + 2;
4880 case RELOAD_FOR_INPUT_ADDRESS:
4881 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4882 && ignore_address_reloads
4883 && ! rld[reloadnum].out)
4885 time2 = rld[i].opnum * 4 + 3;
4887 case RELOAD_FOR_INPUT:
4888 time2 = rld[i].opnum * 4 + 4;
4889 check_earlyclobber = 1;
4891 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4892 == MAX_RECOG_OPERAND * 4 */
4893 case RELOAD_FOR_OPADDR_ADDR:
4894 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4895 && ignore_address_reloads
4896 && ! rld[reloadnum].out)
4898 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4900 case RELOAD_FOR_OPERAND_ADDRESS:
4901 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4902 check_earlyclobber = 1;
4904 case RELOAD_FOR_INSN:
4905 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4907 case RELOAD_FOR_OUTPUT:
4908 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4909 instruction is executed. */
4910 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4912 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4913 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4915 case RELOAD_FOR_OUTADDR_ADDRESS:
4916 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4917 && ignore_address_reloads
4918 && ! rld[reloadnum].out)
4920 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4922 case RELOAD_FOR_OUTPUT_ADDRESS:
4923 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4926 /* If there is no conflict in the input part, handle this
4927 like an output reload. */
4928 if (! rld[i].in || rtx_equal_p (other_input, value))
4930 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4931 /* Earlyclobbered outputs must conflict with inputs. */
4932 if (earlyclobber_operand_p (rld[i].out))
4933 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4938 /* RELOAD_OTHER might be live beyond instruction execution,
4939 but this is not obvious when we set time2 = 1. So check
4940 here if there might be a problem with the new reload
4941 clobbering the register used by the RELOAD_OTHER. */
4949 && (! rld[i].in || rld[i].out
4950 || ! rtx_equal_p (other_input, value)))
4951 || (out && rld[reloadnum].out_reg
4952 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4958 /* Earlyclobbered outputs must conflict with inputs. */
4959 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4965 /* Return 1 if the value in reload reg REGNO, as used by a reload
4966 needed for the part of the insn specified by OPNUM and TYPE,
4967 may be used to load VALUE into it.
4969 MODE is the mode in which the register is used, this is needed to
4970 determine how many hard regs to test.
4972 Other read-only reloads with the same value do not conflict
4973 unless OUT is nonzero and these other reloads have to live while
4974 output reloads live.
4975 If OUT is CONST0_RTX, this is a special case: it means that the
4976 test should not be for using register REGNO as reload register, but
4977 for copying from register REGNO into the reload register.
4979 RELOADNUM is the number of the reload we want to load this value for;
4980 a reload does not conflict with itself.
4982 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4983 reloads that load an address for the very reload we are considering.
4985 The caller has to make sure that there is no conflict with the return
4989 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4990 enum reload_type type, rtx value, rtx out, int reloadnum,
4991 int ignore_address_reloads)
4993 int nregs = hard_regno_nregs[regno][mode];
4995 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4996 value, out, reloadnum,
4997 ignore_address_reloads))
5002 /* Return nonzero if the rtx X is invariant over the current function. */
5003 /* ??? Actually, the places where we use this expect exactly what is
5004 tested here, and not everything that is function invariant. In
5005 particular, the frame pointer and arg pointer are special cased;
5006 pic_offset_table_rtx is not, and we must not spill these things to
5010 function_invariant_p (rtx x)
5014 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5016 if (GET_CODE (x) == PLUS
5017 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5018 && CONSTANT_P (XEXP (x, 1)))
5023 /* Determine whether the reload reg X overlaps any rtx'es used for
5024 overriding inheritance. Return nonzero if so. */
5027 conflicts_with_override (rtx x)
5030 for (i = 0; i < n_reloads; i++)
5031 if (reload_override_in[i]
5032 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5037 /* Give an error message saying we failed to find a reload for INSN,
5038 and clear out reload R. */
5040 failed_reload (rtx insn, int r)
5042 if (asm_noperands (PATTERN (insn)) < 0)
5043 /* It's the compiler's fault. */
5044 fatal_insn ("could not find a spill register", insn);
5046 /* It's the user's fault; the operand's mode and constraint
5047 don't match. Disable this reload so we don't crash in final. */
5048 error_for_asm (insn,
5049 "%<asm%> operand constraint incompatible with operand size");
5053 rld[r].optional = 1;
5054 rld[r].secondary_p = 1;
5057 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5058 for reload R. If it's valid, get an rtx for it. Return nonzero if
5061 set_reload_reg (int i, int r)
5064 rtx reg = spill_reg_rtx[i];
5066 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5067 spill_reg_rtx[i] = reg
5068 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5070 regno = true_regnum (reg);
5072 /* Detect when the reload reg can't hold the reload mode.
5073 This used to be one `if', but Sequent compiler can't handle that. */
5074 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5076 enum machine_mode test_mode = VOIDmode;
5078 test_mode = GET_MODE (rld[r].in);
5079 /* If rld[r].in has VOIDmode, it means we will load it
5080 in whatever mode the reload reg has: to wit, rld[r].mode.
5081 We have already tested that for validity. */
5082 /* Aside from that, we need to test that the expressions
5083 to reload from or into have modes which are valid for this
5084 reload register. Otherwise the reload insns would be invalid. */
5085 if (! (rld[r].in != 0 && test_mode != VOIDmode
5086 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5087 if (! (rld[r].out != 0
5088 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5090 /* The reg is OK. */
5093 /* Mark as in use for this insn the reload regs we use
5095 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5096 rld[r].when_needed, rld[r].mode);
5098 rld[r].reg_rtx = reg;
5099 reload_spill_index[r] = spill_regs[i];
5106 /* Find a spill register to use as a reload register for reload R.
5107 LAST_RELOAD is nonzero if this is the last reload for the insn being
5110 Set rld[R].reg_rtx to the register allocated.
5112 We return 1 if successful, or 0 if we couldn't find a spill reg and
5113 we didn't change anything. */
5116 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5121 /* If we put this reload ahead, thinking it is a group,
5122 then insist on finding a group. Otherwise we can grab a
5123 reg that some other reload needs.
5124 (That can happen when we have a 68000 DATA_OR_FP_REG
5125 which is a group of data regs or one fp reg.)
5126 We need not be so restrictive if there are no more reloads
5129 ??? Really it would be nicer to have smarter handling
5130 for that kind of reg class, where a problem like this is normal.
5131 Perhaps those classes should be avoided for reloading
5132 by use of more alternatives. */
5134 int force_group = rld[r].nregs > 1 && ! last_reload;
5136 /* If we want a single register and haven't yet found one,
5137 take any reg in the right class and not in use.
5138 If we want a consecutive group, here is where we look for it.
5140 We use two passes so we can first look for reload regs to
5141 reuse, which are already in use for other reloads in this insn,
5142 and only then use additional registers.
5143 I think that maximizing reuse is needed to make sure we don't
5144 run out of reload regs. Suppose we have three reloads, and
5145 reloads A and B can share regs. These need two regs.
5146 Suppose A and B are given different regs.
5147 That leaves none for C. */
5148 for (pass = 0; pass < 2; pass++)
5150 /* I is the index in spill_regs.
5151 We advance it round-robin between insns to use all spill regs
5152 equally, so that inherited reloads have a chance
5153 of leapfrogging each other. */
5157 for (count = 0; count < n_spills; count++)
5159 int class = (int) rld[r].class;
5165 regnum = spill_regs[i];
5167 if ((reload_reg_free_p (regnum, rld[r].opnum,
5170 /* We check reload_reg_used to make sure we
5171 don't clobber the return register. */
5172 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5173 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5174 rld[r].when_needed, rld[r].in,
5176 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5177 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5178 /* Look first for regs to share, then for unshared. But
5179 don't share regs used for inherited reloads; they are
5180 the ones we want to preserve. */
5182 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5184 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5187 int nr = hard_regno_nregs[regnum][rld[r].mode];
5188 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5189 (on 68000) got us two FP regs. If NR is 1,
5190 we would reject both of them. */
5193 /* If we need only one reg, we have already won. */
5196 /* But reject a single reg if we demand a group. */
5201 /* Otherwise check that as many consecutive regs as we need
5202 are available here. */
5205 int regno = regnum + nr - 1;
5206 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5207 && spill_reg_order[regno] >= 0
5208 && reload_reg_free_p (regno, rld[r].opnum,
5209 rld[r].when_needed)))
5218 /* If we found something on pass 1, omit pass 2. */
5219 if (count < n_spills)
5223 /* We should have found a spill register by now. */
5224 if (count >= n_spills)
5227 /* I is the index in SPILL_REG_RTX of the reload register we are to
5228 allocate. Get an rtx for it and find its register number. */
5230 return set_reload_reg (i, r);
5233 /* Initialize all the tables needed to allocate reload registers.
5234 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5235 is the array we use to restore the reg_rtx field for every reload. */
5238 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5242 for (i = 0; i < n_reloads; i++)
5243 rld[i].reg_rtx = save_reload_reg_rtx[i];
5245 memset (reload_inherited, 0, MAX_RELOADS);
5246 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5247 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5249 CLEAR_HARD_REG_SET (reload_reg_used);
5250 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5256 CLEAR_HARD_REG_SET (reg_used_in_insn);
5259 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5260 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5261 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5262 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5263 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5264 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5267 for (i = 0; i < reload_n_operands; i++)
5269 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5272 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5273 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5274 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5277 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5279 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5281 for (i = 0; i < n_reloads; i++)
5282 /* If we have already decided to use a certain register,
5283 don't use it in another way. */
5285 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5286 rld[i].when_needed, rld[i].mode);
5289 /* Assign hard reg targets for the pseudo-registers we must reload
5290 into hard regs for this insn.
5291 Also output the instructions to copy them in and out of the hard regs.
5293 For machines with register classes, we are responsible for
5294 finding a reload reg in the proper class. */
5297 choose_reload_regs (struct insn_chain *chain)
5299 rtx insn = chain->insn;
5301 unsigned int max_group_size = 1;
5302 enum reg_class group_class = NO_REGS;
5303 int pass, win, inheritance;
5305 rtx save_reload_reg_rtx[MAX_RELOADS];
5307 /* In order to be certain of getting the registers we need,
5308 we must sort the reloads into order of increasing register class.
5309 Then our grabbing of reload registers will parallel the process
5310 that provided the reload registers.
5312 Also note whether any of the reloads wants a consecutive group of regs.
5313 If so, record the maximum size of the group desired and what
5314 register class contains all the groups needed by this insn. */
5316 for (j = 0; j < n_reloads; j++)
5318 reload_order[j] = j;
5319 reload_spill_index[j] = -1;
5321 if (rld[j].nregs > 1)
5323 max_group_size = MAX (rld[j].nregs, max_group_size);
5325 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5328 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5332 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5334 /* If -O, try first with inheritance, then turning it off.
5335 If not -O, don't do inheritance.
5336 Using inheritance when not optimizing leads to paradoxes
5337 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5338 because one side of the comparison might be inherited. */
5340 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5342 choose_reload_regs_init (chain, save_reload_reg_rtx);
5344 /* Process the reloads in order of preference just found.
5345 Beyond this point, subregs can be found in reload_reg_rtx.
5347 This used to look for an existing reloaded home for all of the
5348 reloads, and only then perform any new reloads. But that could lose
5349 if the reloads were done out of reg-class order because a later
5350 reload with a looser constraint might have an old home in a register
5351 needed by an earlier reload with a tighter constraint.
5353 To solve this, we make two passes over the reloads, in the order
5354 described above. In the first pass we try to inherit a reload
5355 from a previous insn. If there is a later reload that needs a
5356 class that is a proper subset of the class being processed, we must
5357 also allocate a spill register during the first pass.
5359 Then make a second pass over the reloads to allocate any reloads
5360 that haven't been given registers yet. */
5362 for (j = 0; j < n_reloads; j++)
5364 int r = reload_order[j];
5365 rtx search_equiv = NULL_RTX;
5367 /* Ignore reloads that got marked inoperative. */
5368 if (rld[r].out == 0 && rld[r].in == 0
5369 && ! rld[r].secondary_p)
5372 /* If find_reloads chose to use reload_in or reload_out as a reload
5373 register, we don't need to chose one. Otherwise, try even if it
5374 found one since we might save an insn if we find the value lying
5376 Try also when reload_in is a pseudo without a hard reg. */
5377 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5378 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5379 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5380 && !MEM_P (rld[r].in)
5381 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5384 #if 0 /* No longer needed for correct operation.
5385 It might give better code, or might not; worth an experiment? */
5386 /* If this is an optional reload, we can't inherit from earlier insns
5387 until we are sure that any non-optional reloads have been allocated.
5388 The following code takes advantage of the fact that optional reloads
5389 are at the end of reload_order. */
5390 if (rld[r].optional != 0)
5391 for (i = 0; i < j; i++)
5392 if ((rld[reload_order[i]].out != 0
5393 || rld[reload_order[i]].in != 0
5394 || rld[reload_order[i]].secondary_p)
5395 && ! rld[reload_order[i]].optional
5396 && rld[reload_order[i]].reg_rtx == 0)
5397 allocate_reload_reg (chain, reload_order[i], 0);
5400 /* First see if this pseudo is already available as reloaded
5401 for a previous insn. We cannot try to inherit for reloads
5402 that are smaller than the maximum number of registers needed
5403 for groups unless the register we would allocate cannot be used
5406 We could check here to see if this is a secondary reload for
5407 an object that is already in a register of the desired class.
5408 This would avoid the need for the secondary reload register.
5409 But this is complex because we can't easily determine what
5410 objects might want to be loaded via this reload. So let a
5411 register be allocated here. In `emit_reload_insns' we suppress
5412 one of the loads in the case described above. */
5418 enum machine_mode mode = VOIDmode;
5422 else if (REG_P (rld[r].in))
5424 regno = REGNO (rld[r].in);
5425 mode = GET_MODE (rld[r].in);
5427 else if (REG_P (rld[r].in_reg))
5429 regno = REGNO (rld[r].in_reg);
5430 mode = GET_MODE (rld[r].in_reg);
5432 else if (GET_CODE (rld[r].in_reg) == SUBREG
5433 && REG_P (SUBREG_REG (rld[r].in_reg)))
5435 byte = SUBREG_BYTE (rld[r].in_reg);
5436 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5437 if (regno < FIRST_PSEUDO_REGISTER)
5438 regno = subreg_regno (rld[r].in_reg);
5439 mode = GET_MODE (rld[r].in_reg);
5442 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5443 || GET_CODE (rld[r].in_reg) == PRE_DEC
5444 || GET_CODE (rld[r].in_reg) == POST_INC
5445 || GET_CODE (rld[r].in_reg) == POST_DEC)
5446 && REG_P (XEXP (rld[r].in_reg, 0)))
5448 regno = REGNO (XEXP (rld[r].in_reg, 0));
5449 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5450 rld[r].out = rld[r].in;
5454 /* This won't work, since REGNO can be a pseudo reg number.
5455 Also, it takes much more hair to keep track of all the things
5456 that can invalidate an inherited reload of part of a pseudoreg. */
5457 else if (GET_CODE (rld[r].in) == SUBREG
5458 && REG_P (SUBREG_REG (rld[r].in)))
5459 regno = subreg_regno (rld[r].in);
5462 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5464 enum reg_class class = rld[r].class, last_class;
5465 rtx last_reg = reg_last_reload_reg[regno];
5466 enum machine_mode need_mode;
5468 i = REGNO (last_reg);
5469 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5470 last_class = REGNO_REG_CLASS (i);
5476 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5477 + byte * BITS_PER_UNIT,
5478 GET_MODE_CLASS (mode));
5480 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5481 >= GET_MODE_SIZE (need_mode))
5482 #ifdef CANNOT_CHANGE_MODE_CLASS
5483 /* Verify that the register in "i" can be obtained
5485 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5486 GET_MODE (last_reg),
5489 && reg_reloaded_contents[i] == regno
5490 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5491 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5492 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5493 /* Even if we can't use this register as a reload
5494 register, we might use it for reload_override_in,
5495 if copying it to the desired class is cheap
5497 || ((REGISTER_MOVE_COST (mode, last_class, class)
5498 < MEMORY_MOVE_COST (mode, class, 1))
5499 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5500 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5504 #ifdef SECONDARY_MEMORY_NEEDED
5505 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5510 && (rld[r].nregs == max_group_size
5511 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5513 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5514 rld[r].when_needed, rld[r].in,
5517 /* If a group is needed, verify that all the subsequent
5518 registers still have their values intact. */
5519 int nr = hard_regno_nregs[i][rld[r].mode];
5522 for (k = 1; k < nr; k++)
5523 if (reg_reloaded_contents[i + k] != regno
5524 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5532 last_reg = (GET_MODE (last_reg) == mode
5533 ? last_reg : gen_rtx_REG (mode, i));
5536 for (k = 0; k < nr; k++)
5537 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5540 /* We found a register that contains the
5541 value we need. If this register is the
5542 same as an `earlyclobber' operand of the
5543 current insn, just mark it as a place to
5544 reload from since we can't use it as the
5545 reload register itself. */
5547 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5548 if (reg_overlap_mentioned_for_reload_p
5549 (reg_last_reload_reg[regno],
5550 reload_earlyclobbers[i1]))
5553 if (i1 != n_earlyclobbers
5554 || ! (free_for_value_p (i, rld[r].mode,
5556 rld[r].when_needed, rld[r].in,
5558 /* Don't use it if we'd clobber a pseudo reg. */
5559 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5561 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5562 /* Don't clobber the frame pointer. */
5563 || (i == HARD_FRAME_POINTER_REGNUM
5564 && frame_pointer_needed
5566 /* Don't really use the inherited spill reg
5567 if we need it wider than we've got it. */
5568 || (GET_MODE_SIZE (rld[r].mode)
5569 > GET_MODE_SIZE (mode))
5572 /* If find_reloads chose reload_out as reload
5573 register, stay with it - that leaves the
5574 inherited register for subsequent reloads. */
5575 || (rld[r].out && rld[r].reg_rtx
5576 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5578 if (! rld[r].optional)
5580 reload_override_in[r] = last_reg;
5581 reload_inheritance_insn[r]
5582 = reg_reloaded_insn[i];
5588 /* We can use this as a reload reg. */
5589 /* Mark the register as in use for this part of
5591 mark_reload_reg_in_use (i,
5595 rld[r].reg_rtx = last_reg;
5596 reload_inherited[r] = 1;
5597 reload_inheritance_insn[r]
5598 = reg_reloaded_insn[i];
5599 reload_spill_index[r] = i;
5600 for (k = 0; k < nr; k++)
5601 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5609 /* Here's another way to see if the value is already lying around. */
5612 && ! reload_inherited[r]
5614 && (CONSTANT_P (rld[r].in)
5615 || GET_CODE (rld[r].in) == PLUS
5616 || REG_P (rld[r].in)
5617 || MEM_P (rld[r].in))
5618 && (rld[r].nregs == max_group_size
5619 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5620 search_equiv = rld[r].in;
5621 /* If this is an output reload from a simple move insn, look
5622 if an equivalence for the input is available. */
5623 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5625 rtx set = single_set (insn);
5628 && rtx_equal_p (rld[r].out, SET_DEST (set))
5629 && CONSTANT_P (SET_SRC (set)))
5630 search_equiv = SET_SRC (set);
5636 = find_equiv_reg (search_equiv, insn, rld[r].class,
5637 -1, NULL, 0, rld[r].mode);
5643 regno = REGNO (equiv);
5646 /* This must be a SUBREG of a hard register.
5647 Make a new REG since this might be used in an
5648 address and not all machines support SUBREGs
5650 gcc_assert (GET_CODE (equiv) == SUBREG);
5651 regno = subreg_regno (equiv);
5652 equiv = gen_rtx_REG (rld[r].mode, regno);
5653 /* If we choose EQUIV as the reload register, but the
5654 loop below decides to cancel the inheritance, we'll
5655 end up reloading EQUIV in rld[r].mode, not the mode
5656 it had originally. That isn't safe when EQUIV isn't
5657 available as a spill register since its value might
5658 still be live at this point. */
5659 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5660 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5665 /* If we found a spill reg, reject it unless it is free
5666 and of the desired class. */
5670 int bad_for_class = 0;
5671 int max_regno = regno + rld[r].nregs;
5673 for (i = regno; i < max_regno; i++)
5675 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5677 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5682 && ! free_for_value_p (regno, rld[r].mode,
5683 rld[r].opnum, rld[r].when_needed,
5684 rld[r].in, rld[r].out, r, 1))
5689 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5692 /* We found a register that contains the value we need.
5693 If this register is the same as an `earlyclobber' operand
5694 of the current insn, just mark it as a place to reload from
5695 since we can't use it as the reload register itself. */
5698 for (i = 0; i < n_earlyclobbers; i++)
5699 if (reg_overlap_mentioned_for_reload_p (equiv,
5700 reload_earlyclobbers[i]))
5702 if (! rld[r].optional)
5703 reload_override_in[r] = equiv;
5708 /* If the equiv register we have found is explicitly clobbered
5709 in the current insn, it depends on the reload type if we
5710 can use it, use it for reload_override_in, or not at all.
5711 In particular, we then can't use EQUIV for a
5712 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5716 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5717 switch (rld[r].when_needed)
5719 case RELOAD_FOR_OTHER_ADDRESS:
5720 case RELOAD_FOR_INPADDR_ADDRESS:
5721 case RELOAD_FOR_INPUT_ADDRESS:
5722 case RELOAD_FOR_OPADDR_ADDR:
5725 case RELOAD_FOR_INPUT:
5726 case RELOAD_FOR_OPERAND_ADDRESS:
5727 if (! rld[r].optional)
5728 reload_override_in[r] = equiv;
5734 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5735 switch (rld[r].when_needed)
5737 case RELOAD_FOR_OTHER_ADDRESS:
5738 case RELOAD_FOR_INPADDR_ADDRESS:
5739 case RELOAD_FOR_INPUT_ADDRESS:
5740 case RELOAD_FOR_OPADDR_ADDR:
5741 case RELOAD_FOR_OPERAND_ADDRESS:
5742 case RELOAD_FOR_INPUT:
5745 if (! rld[r].optional)
5746 reload_override_in[r] = equiv;
5754 /* If we found an equivalent reg, say no code need be generated
5755 to load it, and use it as our reload reg. */
5757 && (regno != HARD_FRAME_POINTER_REGNUM
5758 || !frame_pointer_needed))
5760 int nr = hard_regno_nregs[regno][rld[r].mode];
5762 rld[r].reg_rtx = equiv;
5763 reload_inherited[r] = 1;
5765 /* If reg_reloaded_valid is not set for this register,
5766 there might be a stale spill_reg_store lying around.
5767 We must clear it, since otherwise emit_reload_insns
5768 might delete the store. */
5769 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5770 spill_reg_store[regno] = NULL_RTX;
5771 /* If any of the hard registers in EQUIV are spill
5772 registers, mark them as in use for this insn. */
5773 for (k = 0; k < nr; k++)
5775 i = spill_reg_order[regno + k];
5778 mark_reload_reg_in_use (regno, rld[r].opnum,
5781 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5788 /* If we found a register to use already, or if this is an optional
5789 reload, we are done. */
5790 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5794 /* No longer needed for correct operation. Might or might
5795 not give better code on the average. Want to experiment? */
5797 /* See if there is a later reload that has a class different from our
5798 class that intersects our class or that requires less register
5799 than our reload. If so, we must allocate a register to this
5800 reload now, since that reload might inherit a previous reload
5801 and take the only available register in our class. Don't do this
5802 for optional reloads since they will force all previous reloads
5803 to be allocated. Also don't do this for reloads that have been
5806 for (i = j + 1; i < n_reloads; i++)
5808 int s = reload_order[i];
5810 if ((rld[s].in == 0 && rld[s].out == 0
5811 && ! rld[s].secondary_p)
5815 if ((rld[s].class != rld[r].class
5816 && reg_classes_intersect_p (rld[r].class,
5818 || rld[s].nregs < rld[r].nregs)
5825 allocate_reload_reg (chain, r, j == n_reloads - 1);
5829 /* Now allocate reload registers for anything non-optional that
5830 didn't get one yet. */
5831 for (j = 0; j < n_reloads; j++)
5833 int r = reload_order[j];
5835 /* Ignore reloads that got marked inoperative. */
5836 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5839 /* Skip reloads that already have a register allocated or are
5841 if (rld[r].reg_rtx != 0 || rld[r].optional)
5844 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5848 /* If that loop got all the way, we have won. */
5855 /* Loop around and try without any inheritance. */
5860 /* First undo everything done by the failed attempt
5861 to allocate with inheritance. */
5862 choose_reload_regs_init (chain, save_reload_reg_rtx);
5864 /* Some sanity tests to verify that the reloads found in the first
5865 pass are identical to the ones we have now. */
5866 gcc_assert (chain->n_reloads == n_reloads);
5868 for (i = 0; i < n_reloads; i++)
5870 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5872 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5873 for (j = 0; j < n_spills; j++)
5874 if (spill_regs[j] == chain->rld[i].regno)
5875 if (! set_reload_reg (j, i))
5876 failed_reload (chain->insn, i);
5880 /* If we thought we could inherit a reload, because it seemed that
5881 nothing else wanted the same reload register earlier in the insn,
5882 verify that assumption, now that all reloads have been assigned.
5883 Likewise for reloads where reload_override_in has been set. */
5885 /* If doing expensive optimizations, do one preliminary pass that doesn't
5886 cancel any inheritance, but removes reloads that have been needed only
5887 for reloads that we know can be inherited. */
5888 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5890 for (j = 0; j < n_reloads; j++)
5892 int r = reload_order[j];
5894 if (reload_inherited[r] && rld[r].reg_rtx)
5895 check_reg = rld[r].reg_rtx;
5896 else if (reload_override_in[r]
5897 && (REG_P (reload_override_in[r])
5898 || GET_CODE (reload_override_in[r]) == SUBREG))
5899 check_reg = reload_override_in[r];
5902 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5903 rld[r].opnum, rld[r].when_needed, rld[r].in,
5904 (reload_inherited[r]
5905 ? rld[r].out : const0_rtx),
5910 reload_inherited[r] = 0;
5911 reload_override_in[r] = 0;
5913 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5914 reload_override_in, then we do not need its related
5915 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5916 likewise for other reload types.
5917 We handle this by removing a reload when its only replacement
5918 is mentioned in reload_in of the reload we are going to inherit.
5919 A special case are auto_inc expressions; even if the input is
5920 inherited, we still need the address for the output. We can
5921 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5922 If we succeeded removing some reload and we are doing a preliminary
5923 pass just to remove such reloads, make another pass, since the
5924 removal of one reload might allow us to inherit another one. */
5926 && rld[r].out != rld[r].in
5927 && remove_address_replacements (rld[r].in) && pass)
5932 /* Now that reload_override_in is known valid,
5933 actually override reload_in. */
5934 for (j = 0; j < n_reloads; j++)
5935 if (reload_override_in[j])
5936 rld[j].in = reload_override_in[j];
5938 /* If this reload won't be done because it has been canceled or is
5939 optional and not inherited, clear reload_reg_rtx so other
5940 routines (such as subst_reloads) don't get confused. */
5941 for (j = 0; j < n_reloads; j++)
5942 if (rld[j].reg_rtx != 0
5943 && ((rld[j].optional && ! reload_inherited[j])
5944 || (rld[j].in == 0 && rld[j].out == 0
5945 && ! rld[j].secondary_p)))
5947 int regno = true_regnum (rld[j].reg_rtx);
5949 if (spill_reg_order[regno] >= 0)
5950 clear_reload_reg_in_use (regno, rld[j].opnum,
5951 rld[j].when_needed, rld[j].mode);
5953 reload_spill_index[j] = -1;
5956 /* Record which pseudos and which spill regs have output reloads. */
5957 for (j = 0; j < n_reloads; j++)
5959 int r = reload_order[j];
5961 i = reload_spill_index[r];
5963 /* I is nonneg if this reload uses a register.
5964 If rld[r].reg_rtx is 0, this is an optional reload
5965 that we opted to ignore. */
5966 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5967 && rld[r].reg_rtx != 0)
5969 int nregno = REGNO (rld[r].out_reg);
5972 if (nregno < FIRST_PSEUDO_REGISTER)
5973 nr = hard_regno_nregs[nregno][rld[r].mode];
5976 reg_has_output_reload[nregno + nr] = 1;
5980 nr = hard_regno_nregs[i][rld[r].mode];
5982 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5985 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5986 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5987 || rld[r].when_needed == RELOAD_FOR_INSN);
5992 /* Deallocate the reload register for reload R. This is called from
5993 remove_address_replacements. */
5996 deallocate_reload_reg (int r)
6000 if (! rld[r].reg_rtx)
6002 regno = true_regnum (rld[r].reg_rtx);
6004 if (spill_reg_order[regno] >= 0)
6005 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6007 reload_spill_index[r] = -1;
6010 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6011 reloads of the same item for fear that we might not have enough reload
6012 registers. However, normally they will get the same reload register
6013 and hence actually need not be loaded twice.
6015 Here we check for the most common case of this phenomenon: when we have
6016 a number of reloads for the same object, each of which were allocated
6017 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6018 reload, and is not modified in the insn itself. If we find such,
6019 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6020 This will not increase the number of spill registers needed and will
6021 prevent redundant code. */
6024 merge_assigned_reloads (rtx insn)
6028 /* Scan all the reloads looking for ones that only load values and
6029 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6030 assigned and not modified by INSN. */
6032 for (i = 0; i < n_reloads; i++)
6034 int conflicting_input = 0;
6035 int max_input_address_opnum = -1;
6036 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6038 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6039 || rld[i].out != 0 || rld[i].reg_rtx == 0
6040 || reg_set_p (rld[i].reg_rtx, insn))
6043 /* Look at all other reloads. Ensure that the only use of this
6044 reload_reg_rtx is in a reload that just loads the same value
6045 as we do. Note that any secondary reloads must be of the identical
6046 class since the values, modes, and result registers are the
6047 same, so we need not do anything with any secondary reloads. */
6049 for (j = 0; j < n_reloads; j++)
6051 if (i == j || rld[j].reg_rtx == 0
6052 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6056 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6057 && rld[j].opnum > max_input_address_opnum)
6058 max_input_address_opnum = rld[j].opnum;
6060 /* If the reload regs aren't exactly the same (e.g, different modes)
6061 or if the values are different, we can't merge this reload.
6062 But if it is an input reload, we might still merge
6063 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6065 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6066 || rld[j].out != 0 || rld[j].in == 0
6067 || ! rtx_equal_p (rld[i].in, rld[j].in))
6069 if (rld[j].when_needed != RELOAD_FOR_INPUT
6070 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6071 || rld[i].opnum > rld[j].opnum)
6072 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6074 conflicting_input = 1;
6075 if (min_conflicting_input_opnum > rld[j].opnum)
6076 min_conflicting_input_opnum = rld[j].opnum;
6080 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6081 we, in fact, found any matching reloads. */
6084 && max_input_address_opnum <= min_conflicting_input_opnum)
6086 for (j = 0; j < n_reloads; j++)
6087 if (i != j && rld[j].reg_rtx != 0
6088 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6089 && (! conflicting_input
6090 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6091 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6093 rld[i].when_needed = RELOAD_OTHER;
6095 reload_spill_index[j] = -1;
6096 transfer_replacements (i, j);
6099 /* If this is now RELOAD_OTHER, look for any reloads that load
6100 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6101 if they were for inputs, RELOAD_OTHER for outputs. Note that
6102 this test is equivalent to looking for reloads for this operand
6104 /* We must take special care when there are two or more reloads to
6105 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6106 same value or a part of it; we must not change its type if there
6107 is a conflicting input. */
6109 if (rld[i].when_needed == RELOAD_OTHER)
6110 for (j = 0; j < n_reloads; j++)
6112 && rld[j].when_needed != RELOAD_OTHER
6113 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6114 && (! conflicting_input
6115 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6116 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6117 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6123 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6124 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6125 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6127 /* Check to see if we accidentally converted two
6128 reloads that use the same reload register with
6129 different inputs to the same type. If so, the
6130 resulting code won't work. */
6132 for (k = 0; k < j; k++)
6133 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6134 || rld[k].when_needed != rld[j].when_needed
6135 || !rtx_equal_p (rld[k].reg_rtx,
6137 || rtx_equal_p (rld[k].in,
6144 /* These arrays are filled by emit_reload_insns and its subroutines. */
6145 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6146 static rtx other_input_address_reload_insns = 0;
6147 static rtx other_input_reload_insns = 0;
6148 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6149 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6150 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6151 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6152 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6153 static rtx operand_reload_insns = 0;
6154 static rtx other_operand_reload_insns = 0;
6155 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6157 /* Values to be put in spill_reg_store are put here first. */
6158 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6159 static HARD_REG_SET reg_reloaded_died;
6161 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6162 has the number J. OLD contains the value to be used as input. */
6165 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6168 rtx insn = chain->insn;
6169 rtx reloadreg = rl->reg_rtx;
6170 rtx oldequiv_reg = 0;
6173 enum machine_mode mode;
6176 /* Determine the mode to reload in.
6177 This is very tricky because we have three to choose from.
6178 There is the mode the insn operand wants (rl->inmode).
6179 There is the mode of the reload register RELOADREG.
6180 There is the intrinsic mode of the operand, which we could find
6181 by stripping some SUBREGs.
6182 It turns out that RELOADREG's mode is irrelevant:
6183 we can change that arbitrarily.
6185 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6186 then the reload reg may not support QImode moves, so use SImode.
6187 If foo is in memory due to spilling a pseudo reg, this is safe,
6188 because the QImode value is in the least significant part of a
6189 slot big enough for a SImode. If foo is some other sort of
6190 memory reference, then it is impossible to reload this case,
6191 so previous passes had better make sure this never happens.
6193 Then consider a one-word union which has SImode and one of its
6194 members is a float, being fetched as (SUBREG:SF union:SI).
6195 We must fetch that as SFmode because we could be loading into
6196 a float-only register. In this case OLD's mode is correct.
6198 Consider an immediate integer: it has VOIDmode. Here we need
6199 to get a mode from something else.
6201 In some cases, there is a fourth mode, the operand's
6202 containing mode. If the insn specifies a containing mode for
6203 this operand, it overrides all others.
6205 I am not sure whether the algorithm here is always right,
6206 but it does the right things in those cases. */
6208 mode = GET_MODE (old);
6209 if (mode == VOIDmode)
6212 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6213 /* If we need a secondary register for this operation, see if
6214 the value is already in a register in that class. Don't
6215 do this if the secondary register will be used as a scratch
6218 if (rl->secondary_in_reload >= 0
6219 && rl->secondary_in_icode == CODE_FOR_nothing
6222 = find_equiv_reg (old, insn,
6223 rld[rl->secondary_in_reload].class,
6227 /* If reloading from memory, see if there is a register
6228 that already holds the same value. If so, reload from there.
6229 We can pass 0 as the reload_reg_p argument because
6230 any other reload has either already been emitted,
6231 in which case find_equiv_reg will see the reload-insn,
6232 or has yet to be emitted, in which case it doesn't matter
6233 because we will use this equiv reg right away. */
6235 if (oldequiv == 0 && optimize
6238 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6239 && reg_renumber[REGNO (old)] < 0)))
6240 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6244 unsigned int regno = true_regnum (oldequiv);
6246 /* Don't use OLDEQUIV if any other reload changes it at an
6247 earlier stage of this insn or at this stage. */
6248 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6249 rl->in, const0_rtx, j, 0))
6252 /* If it is no cheaper to copy from OLDEQUIV into the
6253 reload register than it would be to move from memory,
6254 don't use it. Likewise, if we need a secondary register
6258 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6259 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6261 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6262 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6263 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6267 #ifdef SECONDARY_MEMORY_NEEDED
6268 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6276 /* delete_output_reload is only invoked properly if old contains
6277 the original pseudo register. Since this is replaced with a
6278 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6279 find the pseudo in RELOAD_IN_REG. */
6281 && reload_override_in[j]
6282 && REG_P (rl->in_reg))
6289 else if (REG_P (oldequiv))
6290 oldequiv_reg = oldequiv;
6291 else if (GET_CODE (oldequiv) == SUBREG)
6292 oldequiv_reg = SUBREG_REG (oldequiv);
6294 /* If we are reloading from a register that was recently stored in
6295 with an output-reload, see if we can prove there was
6296 actually no need to store the old value in it. */
6298 if (optimize && REG_P (oldequiv)
6299 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6300 && spill_reg_store[REGNO (oldequiv)]
6302 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6303 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6305 delete_output_reload (insn, j, REGNO (oldequiv));
6307 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6308 then load RELOADREG from OLDEQUIV. Note that we cannot use
6309 gen_lowpart_common since it can do the wrong thing when
6310 RELOADREG has a multi-word mode. Note that RELOADREG
6311 must always be a REG here. */
6313 if (GET_MODE (reloadreg) != mode)
6314 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6315 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6316 oldequiv = SUBREG_REG (oldequiv);
6317 if (GET_MODE (oldequiv) != VOIDmode
6318 && mode != GET_MODE (oldequiv))
6319 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6321 /* Switch to the right place to emit the reload insns. */
6322 switch (rl->when_needed)
6325 where = &other_input_reload_insns;
6327 case RELOAD_FOR_INPUT:
6328 where = &input_reload_insns[rl->opnum];
6330 case RELOAD_FOR_INPUT_ADDRESS:
6331 where = &input_address_reload_insns[rl->opnum];
6333 case RELOAD_FOR_INPADDR_ADDRESS:
6334 where = &inpaddr_address_reload_insns[rl->opnum];
6336 case RELOAD_FOR_OUTPUT_ADDRESS:
6337 where = &output_address_reload_insns[rl->opnum];
6339 case RELOAD_FOR_OUTADDR_ADDRESS:
6340 where = &outaddr_address_reload_insns[rl->opnum];
6342 case RELOAD_FOR_OPERAND_ADDRESS:
6343 where = &operand_reload_insns;
6345 case RELOAD_FOR_OPADDR_ADDR:
6346 where = &other_operand_reload_insns;
6348 case RELOAD_FOR_OTHER_ADDRESS:
6349 where = &other_input_address_reload_insns;
6355 push_to_sequence (*where);
6357 /* Auto-increment addresses must be reloaded in a special way. */
6358 if (rl->out && ! rl->out_reg)
6360 /* We are not going to bother supporting the case where a
6361 incremented register can't be copied directly from
6362 OLDEQUIV since this seems highly unlikely. */
6363 gcc_assert (rl->secondary_in_reload < 0);
6365 if (reload_inherited[j])
6366 oldequiv = reloadreg;
6368 old = XEXP (rl->in_reg, 0);
6370 if (optimize && REG_P (oldequiv)
6371 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6372 && spill_reg_store[REGNO (oldequiv)]
6374 && (dead_or_set_p (insn,
6375 spill_reg_stored_to[REGNO (oldequiv)])
6376 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6378 delete_output_reload (insn, j, REGNO (oldequiv));
6380 /* Prevent normal processing of this reload. */
6382 /* Output a special code sequence for this case. */
6383 new_spill_reg_store[REGNO (reloadreg)]
6384 = inc_for_reload (reloadreg, oldequiv, rl->out,
6388 /* If we are reloading a pseudo-register that was set by the previous
6389 insn, see if we can get rid of that pseudo-register entirely
6390 by redirecting the previous insn into our reload register. */
6392 else if (optimize && REG_P (old)
6393 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6394 && dead_or_set_p (insn, old)
6395 /* This is unsafe if some other reload
6396 uses the same reg first. */
6397 && ! conflicts_with_override (reloadreg)
6398 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6399 rl->when_needed, old, rl->out, j, 0))
6401 rtx temp = PREV_INSN (insn);
6402 while (temp && NOTE_P (temp))
6403 temp = PREV_INSN (temp);
6405 && NONJUMP_INSN_P (temp)
6406 && GET_CODE (PATTERN (temp)) == SET
6407 && SET_DEST (PATTERN (temp)) == old
6408 /* Make sure we can access insn_operand_constraint. */
6409 && asm_noperands (PATTERN (temp)) < 0
6410 /* This is unsafe if operand occurs more than once in current
6411 insn. Perhaps some occurrences aren't reloaded. */
6412 && count_occurrences (PATTERN (insn), old, 0) == 1)
6414 rtx old = SET_DEST (PATTERN (temp));
6415 /* Store into the reload register instead of the pseudo. */
6416 SET_DEST (PATTERN (temp)) = reloadreg;
6418 /* Verify that resulting insn is valid. */
6419 extract_insn (temp);
6420 if (constrain_operands (1))
6422 /* If the previous insn is an output reload, the source is
6423 a reload register, and its spill_reg_store entry will
6424 contain the previous destination. This is now
6426 if (REG_P (SET_SRC (PATTERN (temp)))
6427 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6429 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6430 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6433 /* If these are the only uses of the pseudo reg,
6434 pretend for GDB it lives in the reload reg we used. */
6435 if (REG_N_DEATHS (REGNO (old)) == 1
6436 && REG_N_SETS (REGNO (old)) == 1)
6438 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6439 alter_reg (REGNO (old), -1);
6445 SET_DEST (PATTERN (temp)) = old;
6450 /* We can't do that, so output an insn to load RELOADREG. */
6452 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6453 /* If we have a secondary reload, pick up the secondary register
6454 and icode, if any. If OLDEQUIV and OLD are different or
6455 if this is an in-out reload, recompute whether or not we
6456 still need a secondary register and what the icode should
6457 be. If we still need a secondary register and the class or
6458 icode is different, go back to reloading from OLD if using
6459 OLDEQUIV means that we got the wrong type of register. We
6460 cannot have different class or icode due to an in-out reload
6461 because we don't make such reloads when both the input and
6462 output need secondary reload registers. */
6464 if (! special && rl->secondary_in_reload >= 0)
6466 rtx second_reload_reg = 0;
6467 int secondary_reload = rl->secondary_in_reload;
6468 rtx real_oldequiv = oldequiv;
6471 enum insn_code icode;
6473 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6474 and similarly for OLD.
6475 See comments in get_secondary_reload in reload.c. */
6476 /* If it is a pseudo that cannot be replaced with its
6477 equivalent MEM, we must fall back to reload_in, which
6478 will have all the necessary substitutions registered.
6479 Likewise for a pseudo that can't be replaced with its
6480 equivalent constant.
6482 Take extra care for subregs of such pseudos. Note that
6483 we cannot use reg_equiv_mem in this case because it is
6484 not in the right mode. */
6487 if (GET_CODE (tmp) == SUBREG)
6488 tmp = SUBREG_REG (tmp);
6490 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6491 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6492 || reg_equiv_constant[REGNO (tmp)] != 0))
6494 if (! reg_equiv_mem[REGNO (tmp)]
6495 || num_not_at_initial_offset
6496 || GET_CODE (oldequiv) == SUBREG)
6497 real_oldequiv = rl->in;
6499 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6503 if (GET_CODE (tmp) == SUBREG)
6504 tmp = SUBREG_REG (tmp);
6506 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6507 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6508 || reg_equiv_constant[REGNO (tmp)] != 0))
6510 if (! reg_equiv_mem[REGNO (tmp)]
6511 || num_not_at_initial_offset
6512 || GET_CODE (old) == SUBREG)
6515 real_old = reg_equiv_mem[REGNO (tmp)];
6518 second_reload_reg = rld[secondary_reload].reg_rtx;
6519 icode = rl->secondary_in_icode;
6521 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6522 || (rl->in != 0 && rl->out != 0))
6524 enum reg_class new_class
6525 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6526 mode, real_oldequiv);
6528 if (new_class == NO_REGS)
6529 second_reload_reg = 0;
6532 enum insn_code new_icode;
6533 enum machine_mode new_mode;
6535 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6536 REGNO (second_reload_reg)))
6537 oldequiv = old, real_oldequiv = real_old;
6540 new_icode = reload_in_optab[(int) mode];
6541 if (new_icode != CODE_FOR_nothing
6542 && ((insn_data[(int) new_icode].operand[0].predicate
6543 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6545 || (insn_data[(int) new_icode].operand[1].predicate
6546 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6547 (real_oldequiv, mode)))))
6548 new_icode = CODE_FOR_nothing;
6550 if (new_icode == CODE_FOR_nothing)
6553 new_mode = insn_data[(int) new_icode].operand[2].mode;
6555 if (GET_MODE (second_reload_reg) != new_mode)
6557 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6559 oldequiv = old, real_oldequiv = real_old;
6562 = reload_adjust_reg_for_mode (second_reload_reg,
6569 /* If we still need a secondary reload register, check
6570 to see if it is being used as a scratch or intermediate
6571 register and generate code appropriately. If we need
6572 a scratch register, use REAL_OLDEQUIV since the form of
6573 the insn may depend on the actual address if it is
6576 if (second_reload_reg)
6578 if (icode != CODE_FOR_nothing)
6580 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6581 second_reload_reg));
6586 /* See if we need a scratch register to load the
6587 intermediate register (a tertiary reload). */
6588 enum insn_code tertiary_icode
6589 = rld[secondary_reload].secondary_in_icode;
6591 if (tertiary_icode != CODE_FOR_nothing)
6593 rtx third_reload_reg
6594 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6596 emit_insn ((GEN_FCN (tertiary_icode)
6597 (second_reload_reg, real_oldequiv,
6598 third_reload_reg)));
6601 gen_reload (second_reload_reg, real_oldequiv,
6605 oldequiv = second_reload_reg;
6611 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6613 rtx real_oldequiv = oldequiv;
6615 if ((REG_P (oldequiv)
6616 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6617 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6618 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6619 || (GET_CODE (oldequiv) == SUBREG
6620 && REG_P (SUBREG_REG (oldequiv))
6621 && (REGNO (SUBREG_REG (oldequiv))
6622 >= FIRST_PSEUDO_REGISTER)
6623 && ((reg_equiv_memory_loc
6624 [REGNO (SUBREG_REG (oldequiv))] != 0)
6625 || (reg_equiv_constant
6626 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6627 || (CONSTANT_P (oldequiv)
6628 && (PREFERRED_RELOAD_CLASS (oldequiv,
6629 REGNO_REG_CLASS (REGNO (reloadreg)))
6631 real_oldequiv = rl->in;
6632 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6636 if (flag_non_call_exceptions)
6637 copy_eh_notes (insn, get_insns ());
6639 /* End this sequence. */
6640 *where = get_insns ();
6643 /* Update reload_override_in so that delete_address_reloads_1
6644 can see the actual register usage. */
6646 reload_override_in[j] = oldequiv;
6649 /* Generate insns to for the output reload RL, which is for the insn described
6650 by CHAIN and has the number J. */
6652 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6655 rtx reloadreg = rl->reg_rtx;
6656 rtx insn = chain->insn;
6659 enum machine_mode mode = GET_MODE (old);
6662 if (rl->when_needed == RELOAD_OTHER)
6665 push_to_sequence (output_reload_insns[rl->opnum]);
6667 /* Determine the mode to reload in.
6668 See comments above (for input reloading). */
6670 if (mode == VOIDmode)
6672 /* VOIDmode should never happen for an output. */
6673 if (asm_noperands (PATTERN (insn)) < 0)
6674 /* It's the compiler's fault. */
6675 fatal_insn ("VOIDmode on an output", insn);
6676 error_for_asm (insn, "output operand is constant in %<asm%>");
6677 /* Prevent crash--use something we know is valid. */
6679 old = gen_rtx_REG (mode, REGNO (reloadreg));
6682 if (GET_MODE (reloadreg) != mode)
6683 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6685 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6687 /* If we need two reload regs, set RELOADREG to the intermediate
6688 one, since it will be stored into OLD. We might need a secondary
6689 register only for an input reload, so check again here. */
6691 if (rl->secondary_out_reload >= 0)
6695 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6696 && reg_equiv_mem[REGNO (old)] != 0)
6697 real_old = reg_equiv_mem[REGNO (old)];
6699 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6703 rtx second_reloadreg = reloadreg;
6704 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6706 /* See if RELOADREG is to be used as a scratch register
6707 or as an intermediate register. */
6708 if (rl->secondary_out_icode != CODE_FOR_nothing)
6710 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6711 (real_old, second_reloadreg, reloadreg)));
6716 /* See if we need both a scratch and intermediate reload
6719 int secondary_reload = rl->secondary_out_reload;
6720 enum insn_code tertiary_icode
6721 = rld[secondary_reload].secondary_out_icode;
6723 if (GET_MODE (reloadreg) != mode)
6724 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6726 if (tertiary_icode != CODE_FOR_nothing)
6729 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6732 /* Copy primary reload reg to secondary reload reg.
6733 (Note that these have been swapped above, then
6734 secondary reload reg to OLD using our insn.) */
6736 /* If REAL_OLD is a paradoxical SUBREG, remove it
6737 and try to put the opposite SUBREG on
6739 if (GET_CODE (real_old) == SUBREG
6740 && (GET_MODE_SIZE (GET_MODE (real_old))
6741 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6742 && 0 != (tem = gen_lowpart_common
6743 (GET_MODE (SUBREG_REG (real_old)),
6745 real_old = SUBREG_REG (real_old), reloadreg = tem;
6747 gen_reload (reloadreg, second_reloadreg,
6748 rl->opnum, rl->when_needed);
6749 emit_insn ((GEN_FCN (tertiary_icode)
6750 (real_old, reloadreg, third_reloadreg)));
6755 /* Copy between the reload regs here and then to
6758 gen_reload (reloadreg, second_reloadreg,
6759 rl->opnum, rl->when_needed);
6765 /* Output the last reload insn. */
6770 /* Don't output the last reload if OLD is not the dest of
6771 INSN and is in the src and is clobbered by INSN. */
6772 if (! flag_expensive_optimizations
6774 || !(set = single_set (insn))
6775 || rtx_equal_p (old, SET_DEST (set))
6776 || !reg_mentioned_p (old, SET_SRC (set))
6777 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6778 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6779 gen_reload (old, reloadreg, rl->opnum,
6783 /* Look at all insns we emitted, just to be safe. */
6784 for (p = get_insns (); p; p = NEXT_INSN (p))
6787 rtx pat = PATTERN (p);
6789 /* If this output reload doesn't come from a spill reg,
6790 clear any memory of reloaded copies of the pseudo reg.
6791 If this output reload comes from a spill reg,
6792 reg_has_output_reload will make this do nothing. */
6793 note_stores (pat, forget_old_reloads_1, NULL);
6795 if (reg_mentioned_p (rl->reg_rtx, pat))
6797 rtx set = single_set (insn);
6798 if (reload_spill_index[j] < 0
6800 && SET_SRC (set) == rl->reg_rtx)
6802 int src = REGNO (SET_SRC (set));
6804 reload_spill_index[j] = src;
6805 SET_HARD_REG_BIT (reg_is_output_reload, src);
6806 if (find_regno_note (insn, REG_DEAD, src))
6807 SET_HARD_REG_BIT (reg_reloaded_died, src);
6809 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6811 int s = rl->secondary_out_reload;
6812 set = single_set (p);
6813 /* If this reload copies only to the secondary reload
6814 register, the secondary reload does the actual
6816 if (s >= 0 && set == NULL_RTX)
6817 /* We can't tell what function the secondary reload
6818 has and where the actual store to the pseudo is
6819 made; leave new_spill_reg_store alone. */
6822 && SET_SRC (set) == rl->reg_rtx
6823 && SET_DEST (set) == rld[s].reg_rtx)
6825 /* Usually the next instruction will be the
6826 secondary reload insn; if we can confirm
6827 that it is, setting new_spill_reg_store to
6828 that insn will allow an extra optimization. */
6829 rtx s_reg = rld[s].reg_rtx;
6830 rtx next = NEXT_INSN (p);
6831 rld[s].out = rl->out;
6832 rld[s].out_reg = rl->out_reg;
6833 set = single_set (next);
6834 if (set && SET_SRC (set) == s_reg
6835 && ! new_spill_reg_store[REGNO (s_reg)])
6837 SET_HARD_REG_BIT (reg_is_output_reload,
6839 new_spill_reg_store[REGNO (s_reg)] = next;
6843 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6848 if (rl->when_needed == RELOAD_OTHER)
6850 emit_insn (other_output_reload_insns[rl->opnum]);
6851 other_output_reload_insns[rl->opnum] = get_insns ();
6854 output_reload_insns[rl->opnum] = get_insns ();
6856 if (flag_non_call_exceptions)
6857 copy_eh_notes (insn, get_insns ());
6862 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6863 and has the number J. */
6865 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6867 rtx insn = chain->insn;
6868 rtx old = (rl->in && MEM_P (rl->in)
6869 ? rl->in_reg : rl->in);
6872 /* AUTO_INC reloads need to be handled even if inherited. We got an
6873 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6874 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6875 && ! rtx_equal_p (rl->reg_rtx, old)
6876 && rl->reg_rtx != 0)
6877 emit_input_reload_insns (chain, rld + j, old, j);
6879 /* When inheriting a wider reload, we have a MEM in rl->in,
6880 e.g. inheriting a SImode output reload for
6881 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6882 if (optimize && reload_inherited[j] && rl->in
6884 && MEM_P (rl->in_reg)
6885 && reload_spill_index[j] >= 0
6886 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6887 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6889 /* If we are reloading a register that was recently stored in with an
6890 output-reload, see if we can prove there was
6891 actually no need to store the old value in it. */
6894 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6895 that there may be multiple uses of the previous output reload.
6896 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6897 && rl->when_needed == RELOAD_FOR_INPUT
6898 && (reload_inherited[j] || reload_override_in[j])
6900 && REG_P (rl->reg_rtx)
6901 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6903 /* There doesn't seem to be any reason to restrict this to pseudos
6904 and doing so loses in the case where we are copying from a
6905 register of the wrong class. */
6906 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6907 >= FIRST_PSEUDO_REGISTER)
6909 /* The insn might have already some references to stackslots
6910 replaced by MEMs, while reload_out_reg still names the
6912 && (dead_or_set_p (insn,
6913 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6914 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6916 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6919 /* Do output reloading for reload RL, which is for the insn described by
6920 CHAIN and has the number J.
6921 ??? At some point we need to support handling output reloads of
6922 JUMP_INSNs or insns that set cc0. */
6924 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6927 rtx insn = chain->insn;
6928 /* If this is an output reload that stores something that is
6929 not loaded in this same reload, see if we can eliminate a previous
6931 rtx pseudo = rl->out_reg;
6936 && ! rtx_equal_p (rl->in_reg, pseudo)
6937 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6938 && reg_last_reload_reg[REGNO (pseudo)])
6940 int pseudo_no = REGNO (pseudo);
6941 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6943 /* We don't need to test full validity of last_regno for
6944 inherit here; we only want to know if the store actually
6945 matches the pseudo. */
6946 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6947 && reg_reloaded_contents[last_regno] == pseudo_no
6948 && spill_reg_store[last_regno]
6949 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6950 delete_output_reload (insn, j, last_regno);
6955 || rl->reg_rtx == old
6956 || rl->reg_rtx == 0)
6959 /* An output operand that dies right away does need a reload,
6960 but need not be copied from it. Show the new location in the
6962 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6963 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6965 XEXP (note, 0) = rl->reg_rtx;
6968 /* Likewise for a SUBREG of an operand that dies. */
6969 else if (GET_CODE (old) == SUBREG
6970 && REG_P (SUBREG_REG (old))
6971 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6974 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6978 else if (GET_CODE (old) == SCRATCH)
6979 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6980 but we don't want to make an output reload. */
6983 /* If is a JUMP_INSN, we can't support output reloads yet. */
6984 gcc_assert (!JUMP_P (insn));
6986 emit_output_reload_insns (chain, rld + j, j);
6989 /* Reload number R reloads from or to a group of hard registers starting at
6990 register REGNO. Return true if it can be treated for inheritance purposes
6991 like a group of reloads, each one reloading a single hard register.
6992 The caller has already checked that the spill register and REGNO use
6993 the same number of registers to store the reload value. */
6996 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6998 #ifdef CANNOT_CHANGE_MODE_CLASS
6999 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7000 GET_MODE (rld[r].reg_rtx),
7001 reg_raw_mode[reload_spill_index[r]])
7002 && !REG_CANNOT_CHANGE_MODE_P (regno,
7003 GET_MODE (rld[r].reg_rtx),
7004 reg_raw_mode[regno]));
7010 /* Output insns to reload values in and out of the chosen reload regs. */
7013 emit_reload_insns (struct insn_chain *chain)
7015 rtx insn = chain->insn;
7019 CLEAR_HARD_REG_SET (reg_reloaded_died);
7021 for (j = 0; j < reload_n_operands; j++)
7022 input_reload_insns[j] = input_address_reload_insns[j]
7023 = inpaddr_address_reload_insns[j]
7024 = output_reload_insns[j] = output_address_reload_insns[j]
7025 = outaddr_address_reload_insns[j]
7026 = other_output_reload_insns[j] = 0;
7027 other_input_address_reload_insns = 0;
7028 other_input_reload_insns = 0;
7029 operand_reload_insns = 0;
7030 other_operand_reload_insns = 0;
7032 /* Dump reloads into the dump file. */
7035 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7036 debug_reload_to_stream (dump_file);
7039 /* Now output the instructions to copy the data into and out of the
7040 reload registers. Do these in the order that the reloads were reported,
7041 since reloads of base and index registers precede reloads of operands
7042 and the operands may need the base and index registers reloaded. */
7044 for (j = 0; j < n_reloads; j++)
7047 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7048 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7050 do_input_reload (chain, rld + j, j);
7051 do_output_reload (chain, rld + j, j);
7054 /* Now write all the insns we made for reloads in the order expected by
7055 the allocation functions. Prior to the insn being reloaded, we write
7056 the following reloads:
7058 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7060 RELOAD_OTHER reloads.
7062 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7063 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7064 RELOAD_FOR_INPUT reload for the operand.
7066 RELOAD_FOR_OPADDR_ADDRS reloads.
7068 RELOAD_FOR_OPERAND_ADDRESS reloads.
7070 After the insn being reloaded, we write the following:
7072 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7073 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7074 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7075 reloads for the operand. The RELOAD_OTHER output reloads are
7076 output in descending order by reload number. */
7078 emit_insn_before (other_input_address_reload_insns, insn);
7079 emit_insn_before (other_input_reload_insns, insn);
7081 for (j = 0; j < reload_n_operands; j++)
7083 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7084 emit_insn_before (input_address_reload_insns[j], insn);
7085 emit_insn_before (input_reload_insns[j], insn);
7088 emit_insn_before (other_operand_reload_insns, insn);
7089 emit_insn_before (operand_reload_insns, insn);
7091 for (j = 0; j < reload_n_operands; j++)
7093 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7094 x = emit_insn_after (output_address_reload_insns[j], x);
7095 x = emit_insn_after (output_reload_insns[j], x);
7096 emit_insn_after (other_output_reload_insns[j], x);
7099 /* For all the spill regs newly reloaded in this instruction,
7100 record what they were reloaded from, so subsequent instructions
7101 can inherit the reloads.
7103 Update spill_reg_store for the reloads of this insn.
7104 Copy the elements that were updated in the loop above. */
7106 for (j = 0; j < n_reloads; j++)
7108 int r = reload_order[j];
7109 int i = reload_spill_index[r];
7111 /* If this is a non-inherited input reload from a pseudo, we must
7112 clear any memory of a previous store to the same pseudo. Only do
7113 something if there will not be an output reload for the pseudo
7115 if (rld[r].in_reg != 0
7116 && ! (reload_inherited[r] || reload_override_in[r]))
7118 rtx reg = rld[r].in_reg;
7120 if (GET_CODE (reg) == SUBREG)
7121 reg = SUBREG_REG (reg);
7124 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7125 && ! reg_has_output_reload[REGNO (reg)])
7127 int nregno = REGNO (reg);
7129 if (reg_last_reload_reg[nregno])
7131 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7133 if (reg_reloaded_contents[last_regno] == nregno)
7134 spill_reg_store[last_regno] = 0;
7139 /* I is nonneg if this reload used a register.
7140 If rld[r].reg_rtx is 0, this is an optional reload
7141 that we opted to ignore. */
7143 if (i >= 0 && rld[r].reg_rtx != 0)
7145 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7147 int part_reaches_end = 0;
7148 int all_reaches_end = 1;
7150 /* For a multi register reload, we need to check if all or part
7151 of the value lives to the end. */
7152 for (k = 0; k < nr; k++)
7154 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7155 rld[r].when_needed))
7156 part_reaches_end = 1;
7158 all_reaches_end = 0;
7161 /* Ignore reloads that don't reach the end of the insn in
7163 if (all_reaches_end)
7165 /* First, clear out memory of what used to be in this spill reg.
7166 If consecutive registers are used, clear them all. */
7168 for (k = 0; k < nr; k++)
7170 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7171 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7174 /* Maybe the spill reg contains a copy of reload_out. */
7176 && (REG_P (rld[r].out)
7180 || REG_P (rld[r].out_reg)))
7182 rtx out = (REG_P (rld[r].out)
7186 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7187 int nregno = REGNO (out);
7188 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7189 : hard_regno_nregs[nregno]
7190 [GET_MODE (rld[r].reg_rtx)]);
7193 spill_reg_store[i] = new_spill_reg_store[i];
7194 spill_reg_stored_to[i] = out;
7195 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7197 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7199 && inherit_piecemeal_p (r, nregno));
7201 /* If NREGNO is a hard register, it may occupy more than
7202 one register. If it does, say what is in the
7203 rest of the registers assuming that both registers
7204 agree on how many words the object takes. If not,
7205 invalidate the subsequent registers. */
7207 if (nregno < FIRST_PSEUDO_REGISTER)
7208 for (k = 1; k < nnr; k++)
7209 reg_last_reload_reg[nregno + k]
7211 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7214 /* Now do the inverse operation. */
7215 for (k = 0; k < nr; k++)
7217 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7218 reg_reloaded_contents[i + k]
7219 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7222 reg_reloaded_insn[i + k] = insn;
7223 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7224 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7225 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7229 /* Maybe the spill reg contains a copy of reload_in. Only do
7230 something if there will not be an output reload for
7231 the register being reloaded. */
7232 else if (rld[r].out_reg == 0
7234 && ((REG_P (rld[r].in)
7235 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7236 && ! reg_has_output_reload[REGNO (rld[r].in)])
7237 || (REG_P (rld[r].in_reg)
7238 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7239 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7246 if (REG_P (rld[r].in)
7247 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7249 else if (REG_P (rld[r].in_reg))
7252 in = XEXP (rld[r].in_reg, 0);
7253 nregno = REGNO (in);
7255 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7256 : hard_regno_nregs[nregno]
7257 [GET_MODE (rld[r].reg_rtx)]);
7259 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7261 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7263 && inherit_piecemeal_p (r, nregno));
7265 if (nregno < FIRST_PSEUDO_REGISTER)
7266 for (k = 1; k < nnr; k++)
7267 reg_last_reload_reg[nregno + k]
7269 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7272 /* Unless we inherited this reload, show we haven't
7273 recently done a store.
7274 Previous stores of inherited auto_inc expressions
7275 also have to be discarded. */
7276 if (! reload_inherited[r]
7277 || (rld[r].out && ! rld[r].out_reg))
7278 spill_reg_store[i] = 0;
7280 for (k = 0; k < nr; k++)
7282 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7283 reg_reloaded_contents[i + k]
7284 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7287 reg_reloaded_insn[i + k] = insn;
7288 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7289 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7290 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7295 /* However, if part of the reload reaches the end, then we must
7296 invalidate the old info for the part that survives to the end. */
7297 else if (part_reaches_end)
7299 for (k = 0; k < nr; k++)
7300 if (reload_reg_reaches_end_p (i + k,
7302 rld[r].when_needed))
7303 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7307 /* The following if-statement was #if 0'd in 1.34 (or before...).
7308 It's reenabled in 1.35 because supposedly nothing else
7309 deals with this problem. */
7311 /* If a register gets output-reloaded from a non-spill register,
7312 that invalidates any previous reloaded copy of it.
7313 But forget_old_reloads_1 won't get to see it, because
7314 it thinks only about the original insn. So invalidate it here. */
7315 if (i < 0 && rld[r].out != 0
7316 && (REG_P (rld[r].out)
7317 || (MEM_P (rld[r].out)
7318 && REG_P (rld[r].out_reg))))
7320 rtx out = (REG_P (rld[r].out)
7321 ? rld[r].out : rld[r].out_reg);
7322 int nregno = REGNO (out);
7323 if (nregno >= FIRST_PSEUDO_REGISTER)
7325 rtx src_reg, store_insn = NULL_RTX;
7327 reg_last_reload_reg[nregno] = 0;
7329 /* If we can find a hard register that is stored, record
7330 the storing insn so that we may delete this insn with
7331 delete_output_reload. */
7332 src_reg = rld[r].reg_rtx;
7334 /* If this is an optional reload, try to find the source reg
7335 from an input reload. */
7338 rtx set = single_set (insn);
7339 if (set && SET_DEST (set) == rld[r].out)
7343 src_reg = SET_SRC (set);
7345 for (k = 0; k < n_reloads; k++)
7347 if (rld[k].in == src_reg)
7349 src_reg = rld[k].reg_rtx;
7356 store_insn = new_spill_reg_store[REGNO (src_reg)];
7357 if (src_reg && REG_P (src_reg)
7358 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7360 int src_regno = REGNO (src_reg);
7361 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7362 /* The place where to find a death note varies with
7363 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7364 necessarily checked exactly in the code that moves
7365 notes, so just check both locations. */
7366 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7367 if (! note && store_insn)
7368 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7371 spill_reg_store[src_regno + nr] = store_insn;
7372 spill_reg_stored_to[src_regno + nr] = out;
7373 reg_reloaded_contents[src_regno + nr] = nregno;
7374 reg_reloaded_insn[src_regno + nr] = store_insn;
7375 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7376 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7377 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7378 GET_MODE (src_reg)))
7379 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7381 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7383 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7385 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7387 reg_last_reload_reg[nregno] = src_reg;
7388 /* We have to set reg_has_output_reload here, or else
7389 forget_old_reloads_1 will clear reg_last_reload_reg
7391 reg_has_output_reload[nregno] = 1;
7396 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7398 while (num_regs-- > 0)
7399 reg_last_reload_reg[nregno + num_regs] = 0;
7403 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7406 /* Emit code to perform a reload from IN (which may be a reload register) to
7407 OUT (which may also be a reload register). IN or OUT is from operand
7408 OPNUM with reload type TYPE.
7410 Returns first insn emitted. */
7413 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7415 rtx last = get_last_insn ();
7418 /* If IN is a paradoxical SUBREG, remove it and try to put the
7419 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7420 if (GET_CODE (in) == SUBREG
7421 && (GET_MODE_SIZE (GET_MODE (in))
7422 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7423 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7424 in = SUBREG_REG (in), out = tem;
7425 else if (GET_CODE (out) == SUBREG
7426 && (GET_MODE_SIZE (GET_MODE (out))
7427 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7428 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7429 out = SUBREG_REG (out), in = tem;
7431 /* How to do this reload can get quite tricky. Normally, we are being
7432 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7433 register that didn't get a hard register. In that case we can just
7434 call emit_move_insn.
7436 We can also be asked to reload a PLUS that adds a register or a MEM to
7437 another register, constant or MEM. This can occur during frame pointer
7438 elimination and while reloading addresses. This case is handled by
7439 trying to emit a single insn to perform the add. If it is not valid,
7440 we use a two insn sequence.
7442 Finally, we could be called to handle an 'o' constraint by putting
7443 an address into a register. In that case, we first try to do this
7444 with a named pattern of "reload_load_address". If no such pattern
7445 exists, we just emit a SET insn and hope for the best (it will normally
7446 be valid on machines that use 'o').
7448 This entire process is made complex because reload will never
7449 process the insns we generate here and so we must ensure that
7450 they will fit their constraints and also by the fact that parts of
7451 IN might be being reloaded separately and replaced with spill registers.
7452 Because of this, we are, in some sense, just guessing the right approach
7453 here. The one listed above seems to work.
7455 ??? At some point, this whole thing needs to be rethought. */
7457 if (GET_CODE (in) == PLUS
7458 && (REG_P (XEXP (in, 0))
7459 || GET_CODE (XEXP (in, 0)) == SUBREG
7460 || MEM_P (XEXP (in, 0)))
7461 && (REG_P (XEXP (in, 1))
7462 || GET_CODE (XEXP (in, 1)) == SUBREG
7463 || CONSTANT_P (XEXP (in, 1))
7464 || MEM_P (XEXP (in, 1))))
7466 /* We need to compute the sum of a register or a MEM and another
7467 register, constant, or MEM, and put it into the reload
7468 register. The best possible way of doing this is if the machine
7469 has a three-operand ADD insn that accepts the required operands.
7471 The simplest approach is to try to generate such an insn and see if it
7472 is recognized and matches its constraints. If so, it can be used.
7474 It might be better not to actually emit the insn unless it is valid,
7475 but we need to pass the insn as an operand to `recog' and
7476 `extract_insn' and it is simpler to emit and then delete the insn if
7477 not valid than to dummy things up. */
7479 rtx op0, op1, tem, insn;
7482 op0 = find_replacement (&XEXP (in, 0));
7483 op1 = find_replacement (&XEXP (in, 1));
7485 /* Since constraint checking is strict, commutativity won't be
7486 checked, so we need to do that here to avoid spurious failure
7487 if the add instruction is two-address and the second operand
7488 of the add is the same as the reload reg, which is frequently
7489 the case. If the insn would be A = B + A, rearrange it so
7490 it will be A = A + B as constrain_operands expects. */
7492 if (REG_P (XEXP (in, 1))
7493 && REGNO (out) == REGNO (XEXP (in, 1)))
7494 tem = op0, op0 = op1, op1 = tem;
7496 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7497 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7499 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7500 code = recog_memoized (insn);
7504 extract_insn (insn);
7505 /* We want constrain operands to treat this insn strictly in
7506 its validity determination, i.e., the way it would after reload
7508 if (constrain_operands (1))
7512 delete_insns_since (last);
7514 /* If that failed, we must use a conservative two-insn sequence.
7516 Use a move to copy one operand into the reload register. Prefer
7517 to reload a constant, MEM or pseudo since the move patterns can
7518 handle an arbitrary operand. If OP1 is not a constant, MEM or
7519 pseudo and OP1 is not a valid operand for an add instruction, then
7522 After reloading one of the operands into the reload register, add
7523 the reload register to the output register.
7525 If there is another way to do this for a specific machine, a
7526 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7529 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7531 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7533 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7534 || (code != CODE_FOR_nothing
7535 && ! ((*insn_data[code].operand[2].predicate)
7536 (op1, insn_data[code].operand[2].mode))))
7537 tem = op0, op0 = op1, op1 = tem;
7539 gen_reload (out, op0, opnum, type);
7541 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7542 This fixes a problem on the 32K where the stack pointer cannot
7543 be used as an operand of an add insn. */
7545 if (rtx_equal_p (op0, op1))
7548 insn = emit_insn (gen_add2_insn (out, op1));
7550 /* If that failed, copy the address register to the reload register.
7551 Then add the constant to the reload register. */
7553 code = recog_memoized (insn);
7557 extract_insn (insn);
7558 /* We want constrain operands to treat this insn strictly in
7559 its validity determination, i.e., the way it would after reload
7561 if (constrain_operands (1))
7563 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7565 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7570 delete_insns_since (last);
7572 gen_reload (out, op1, opnum, type);
7573 insn = emit_insn (gen_add2_insn (out, op0));
7574 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7577 #ifdef SECONDARY_MEMORY_NEEDED
7578 /* If we need a memory location to do the move, do it that way. */
7579 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7580 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7581 && (REG_P (out) || GET_CODE (out) == SUBREG)
7582 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7583 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7584 REGNO_REG_CLASS (reg_or_subregno (out)),
7587 /* Get the memory to use and rewrite both registers to its mode. */
7588 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7590 if (GET_MODE (loc) != GET_MODE (out))
7591 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7593 if (GET_MODE (loc) != GET_MODE (in))
7594 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7596 gen_reload (loc, in, opnum, type);
7597 gen_reload (out, loc, opnum, type);
7601 /* If IN is a simple operand, use gen_move_insn. */
7602 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7603 emit_insn (gen_move_insn (out, in));
7605 #ifdef HAVE_reload_load_address
7606 else if (HAVE_reload_load_address)
7607 emit_insn (gen_reload_load_address (out, in));
7610 /* Otherwise, just write (set OUT IN) and hope for the best. */
7612 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7614 /* Return the first insn emitted.
7615 We can not just return get_last_insn, because there may have
7616 been multiple instructions emitted. Also note that gen_move_insn may
7617 emit more than one insn itself, so we can not assume that there is one
7618 insn emitted per emit_insn_before call. */
7620 return last ? NEXT_INSN (last) : get_insns ();
7623 /* Delete a previously made output-reload whose result we now believe
7624 is not needed. First we double-check.
7626 INSN is the insn now being processed.
7627 LAST_RELOAD_REG is the hard register number for which we want to delete
7628 the last output reload.
7629 J is the reload-number that originally used REG. The caller has made
7630 certain that reload J doesn't use REG any longer for input. */
7633 delete_output_reload (rtx insn, int j, int last_reload_reg)
7635 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7636 rtx reg = spill_reg_stored_to[last_reload_reg];
7639 int n_inherited = 0;
7643 /* It is possible that this reload has been only used to set another reload
7644 we eliminated earlier and thus deleted this instruction too. */
7645 if (INSN_DELETED_P (output_reload_insn))
7648 /* Get the raw pseudo-register referred to. */
7650 while (GET_CODE (reg) == SUBREG)
7651 reg = SUBREG_REG (reg);
7652 substed = reg_equiv_memory_loc[REGNO (reg)];
7654 /* This is unsafe if the operand occurs more often in the current
7655 insn than it is inherited. */
7656 for (k = n_reloads - 1; k >= 0; k--)
7658 rtx reg2 = rld[k].in;
7661 if (MEM_P (reg2) || reload_override_in[k])
7662 reg2 = rld[k].in_reg;
7664 if (rld[k].out && ! rld[k].out_reg)
7665 reg2 = XEXP (rld[k].in_reg, 0);
7667 while (GET_CODE (reg2) == SUBREG)
7668 reg2 = SUBREG_REG (reg2);
7669 if (rtx_equal_p (reg2, reg))
7671 if (reload_inherited[k] || reload_override_in[k] || k == j)
7674 reg2 = rld[k].out_reg;
7677 while (GET_CODE (reg2) == SUBREG)
7678 reg2 = XEXP (reg2, 0);
7679 if (rtx_equal_p (reg2, reg))
7686 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7688 n_occurrences += count_occurrences (PATTERN (insn),
7689 eliminate_regs (substed, 0,
7691 if (n_occurrences > n_inherited)
7694 /* If the pseudo-reg we are reloading is no longer referenced
7695 anywhere between the store into it and here,
7696 and we're within the same basic block, then the value can only
7697 pass through the reload reg and end up here.
7698 Otherwise, give up--return. */
7699 for (i1 = NEXT_INSN (output_reload_insn);
7700 i1 != insn; i1 = NEXT_INSN (i1))
7702 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7704 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7705 && reg_mentioned_p (reg, PATTERN (i1)))
7707 /* If this is USE in front of INSN, we only have to check that
7708 there are no more references than accounted for by inheritance. */
7709 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7711 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7712 i1 = NEXT_INSN (i1);
7714 if (n_occurrences <= n_inherited && i1 == insn)
7720 /* We will be deleting the insn. Remove the spill reg information. */
7721 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7723 spill_reg_store[last_reload_reg + k] = 0;
7724 spill_reg_stored_to[last_reload_reg + k] = 0;
7727 /* The caller has already checked that REG dies or is set in INSN.
7728 It has also checked that we are optimizing, and thus some
7729 inaccuracies in the debugging information are acceptable.
7730 So we could just delete output_reload_insn. But in some cases
7731 we can improve the debugging information without sacrificing
7732 optimization - maybe even improving the code: See if the pseudo
7733 reg has been completely replaced with reload regs. If so, delete
7734 the store insn and forget we had a stack slot for the pseudo. */
7735 if (rld[j].out != rld[j].in
7736 && REG_N_DEATHS (REGNO (reg)) == 1
7737 && REG_N_SETS (REGNO (reg)) == 1
7738 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7739 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7743 /* We know that it was used only between here and the beginning of
7744 the current basic block. (We also know that the last use before
7745 INSN was the output reload we are thinking of deleting, but never
7746 mind that.) Search that range; see if any ref remains. */
7747 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7749 rtx set = single_set (i2);
7751 /* Uses which just store in the pseudo don't count,
7752 since if they are the only uses, they are dead. */
7753 if (set != 0 && SET_DEST (set) == reg)
7758 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7759 && reg_mentioned_p (reg, PATTERN (i2)))
7761 /* Some other ref remains; just delete the output reload we
7763 delete_address_reloads (output_reload_insn, insn);
7764 delete_insn (output_reload_insn);
7769 /* Delete the now-dead stores into this pseudo. Note that this
7770 loop also takes care of deleting output_reload_insn. */
7771 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7773 rtx set = single_set (i2);
7775 if (set != 0 && SET_DEST (set) == reg)
7777 delete_address_reloads (i2, insn);
7785 /* For the debugging info, say the pseudo lives in this reload reg. */
7786 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7787 alter_reg (REGNO (reg), -1);
7791 delete_address_reloads (output_reload_insn, insn);
7792 delete_insn (output_reload_insn);
7796 /* We are going to delete DEAD_INSN. Recursively delete loads of
7797 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7798 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7800 delete_address_reloads (rtx dead_insn, rtx current_insn)
7802 rtx set = single_set (dead_insn);
7803 rtx set2, dst, prev, next;
7806 rtx dst = SET_DEST (set);
7808 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7810 /* If we deleted the store from a reloaded post_{in,de}c expression,
7811 we can delete the matching adds. */
7812 prev = PREV_INSN (dead_insn);
7813 next = NEXT_INSN (dead_insn);
7814 if (! prev || ! next)
7816 set = single_set (next);
7817 set2 = single_set (prev);
7819 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7820 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7821 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7823 dst = SET_DEST (set);
7824 if (! rtx_equal_p (dst, SET_DEST (set2))
7825 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7826 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7827 || (INTVAL (XEXP (SET_SRC (set), 1))
7828 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7830 delete_related_insns (prev);
7831 delete_related_insns (next);
7834 /* Subfunction of delete_address_reloads: process registers found in X. */
7836 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7838 rtx prev, set, dst, i2;
7840 enum rtx_code code = GET_CODE (x);
7844 const char *fmt = GET_RTX_FORMAT (code);
7845 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7848 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7849 else if (fmt[i] == 'E')
7851 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7852 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7859 if (spill_reg_order[REGNO (x)] < 0)
7862 /* Scan backwards for the insn that sets x. This might be a way back due
7864 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7866 code = GET_CODE (prev);
7867 if (code == CODE_LABEL || code == JUMP_INSN)
7871 if (reg_set_p (x, PATTERN (prev)))
7873 if (reg_referenced_p (x, PATTERN (prev)))
7876 if (! prev || INSN_UID (prev) < reload_first_uid)
7878 /* Check that PREV only sets the reload register. */
7879 set = single_set (prev);
7882 dst = SET_DEST (set);
7884 || ! rtx_equal_p (dst, x))
7886 if (! reg_set_p (dst, PATTERN (dead_insn)))
7888 /* Check if DST was used in a later insn -
7889 it might have been inherited. */
7890 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7896 if (reg_referenced_p (dst, PATTERN (i2)))
7898 /* If there is a reference to the register in the current insn,
7899 it might be loaded in a non-inherited reload. If no other
7900 reload uses it, that means the register is set before
7902 if (i2 == current_insn)
7904 for (j = n_reloads - 1; j >= 0; j--)
7905 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7906 || reload_override_in[j] == dst)
7908 for (j = n_reloads - 1; j >= 0; j--)
7909 if (rld[j].in && rld[j].reg_rtx == dst)
7918 /* If DST is still live at CURRENT_INSN, check if it is used for
7919 any reload. Note that even if CURRENT_INSN sets DST, we still
7920 have to check the reloads. */
7921 if (i2 == current_insn)
7923 for (j = n_reloads - 1; j >= 0; j--)
7924 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7925 || reload_override_in[j] == dst)
7927 /* ??? We can't finish the loop here, because dst might be
7928 allocated to a pseudo in this block if no reload in this
7929 block needs any of the classes containing DST - see
7930 spill_hard_reg. There is no easy way to tell this, so we
7931 have to scan till the end of the basic block. */
7933 if (reg_set_p (dst, PATTERN (i2)))
7937 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7938 reg_reloaded_contents[REGNO (dst)] = -1;
7942 /* Output reload-insns to reload VALUE into RELOADREG.
7943 VALUE is an autoincrement or autodecrement RTX whose operand
7944 is a register or memory location;
7945 so reloading involves incrementing that location.
7946 IN is either identical to VALUE, or some cheaper place to reload from.
7948 INC_AMOUNT is the number to increment or decrement by (always positive).
7949 This cannot be deduced from VALUE.
7951 Return the instruction that stores into RELOADREG. */
7954 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7956 /* REG or MEM to be copied and incremented. */
7957 rtx incloc = XEXP (value, 0);
7958 /* Nonzero if increment after copying. */
7959 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7965 rtx real_in = in == value ? XEXP (in, 0) : in;
7967 /* No hard register is equivalent to this register after
7968 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7969 we could inc/dec that register as well (maybe even using it for
7970 the source), but I'm not sure it's worth worrying about. */
7972 reg_last_reload_reg[REGNO (incloc)] = 0;
7974 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7975 inc_amount = -inc_amount;
7977 inc = GEN_INT (inc_amount);
7979 /* If this is post-increment, first copy the location to the reload reg. */
7980 if (post && real_in != reloadreg)
7981 emit_insn (gen_move_insn (reloadreg, real_in));
7985 /* See if we can directly increment INCLOC. Use a method similar to
7986 that in gen_reload. */
7988 last = get_last_insn ();
7989 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7990 gen_rtx_PLUS (GET_MODE (incloc),
7993 code = recog_memoized (add_insn);
7996 extract_insn (add_insn);
7997 if (constrain_operands (1))
7999 /* If this is a pre-increment and we have incremented the value
8000 where it lives, copy the incremented value to RELOADREG to
8001 be used as an address. */
8004 emit_insn (gen_move_insn (reloadreg, incloc));
8009 delete_insns_since (last);
8012 /* If couldn't do the increment directly, must increment in RELOADREG.
8013 The way we do this depends on whether this is pre- or post-increment.
8014 For pre-increment, copy INCLOC to the reload register, increment it
8015 there, then save back. */
8019 if (in != reloadreg)
8020 emit_insn (gen_move_insn (reloadreg, real_in));
8021 emit_insn (gen_add2_insn (reloadreg, inc));
8022 store = emit_insn (gen_move_insn (incloc, reloadreg));
8027 Because this might be a jump insn or a compare, and because RELOADREG
8028 may not be available after the insn in an input reload, we must do
8029 the incrementation before the insn being reloaded for.
8031 We have already copied IN to RELOADREG. Increment the copy in
8032 RELOADREG, save that back, then decrement RELOADREG so it has
8033 the original value. */
8035 emit_insn (gen_add2_insn (reloadreg, inc));
8036 store = emit_insn (gen_move_insn (incloc, reloadreg));
8037 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8045 add_auto_inc_notes (rtx insn, rtx x)
8047 enum rtx_code code = GET_CODE (x);
8051 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8054 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8058 /* Scan all the operand sub-expressions. */
8059 fmt = GET_RTX_FORMAT (code);
8060 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8063 add_auto_inc_notes (insn, XEXP (x, i));
8064 else if (fmt[i] == 'E')
8065 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8066 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8071 /* Copy EH notes from an insn to its reloads. */
8073 copy_eh_notes (rtx insn, rtx x)
8075 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8078 for (; x != 0; x = NEXT_INSN (x))
8080 if (may_trap_p (PATTERN (x)))
8082 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8088 /* This is used by reload pass, that does emit some instructions after
8089 abnormal calls moving basic block end, but in fact it wants to emit
8090 them on the edge. Looks for abnormal call edges, find backward the
8091 proper call and fix the damage.
8093 Similar handle instructions throwing exceptions internally. */
8095 fixup_abnormal_edges (void)
8097 bool inserted = false;
8105 /* Look for cases we are interested in - calls or instructions causing
8107 FOR_EACH_EDGE (e, ei, bb->succs)
8109 if (e->flags & EDGE_ABNORMAL_CALL)
8111 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8112 == (EDGE_ABNORMAL | EDGE_EH))
8115 if (e && !CALL_P (BB_END (bb))
8116 && !can_throw_internal (BB_END (bb)))
8120 /* Get past the new insns generated. Allow notes, as the insns
8121 may be already deleted. */
8123 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8124 && !can_throw_internal (insn)
8125 && insn != BB_HEAD (bb))
8126 insn = PREV_INSN (insn);
8128 if (CALL_P (insn) || can_throw_internal (insn))
8132 stop = NEXT_INSN (BB_END (bb));
8134 insn = NEXT_INSN (insn);
8136 FOR_EACH_EDGE (e, ei, bb->succs)
8137 if (e->flags & EDGE_FALLTHRU)
8140 while (insn && insn != stop)
8142 next = NEXT_INSN (insn);
8147 /* Sometimes there's still the return value USE.
8148 If it's placed after a trapping call (i.e. that
8149 call is the last insn anyway), we have no fallthru
8150 edge. Simply delete this use and don't try to insert
8151 on the non-existent edge. */
8152 if (GET_CODE (PATTERN (insn)) != USE)
8154 /* We're not deleting it, we're moving it. */
8155 INSN_DELETED_P (insn) = 0;
8156 PREV_INSN (insn) = NULL_RTX;
8157 NEXT_INSN (insn) = NULL_RTX;
8159 insert_insn_on_edge (insn, e);
8167 /* It may be that we don't find any such trapping insn. In this
8168 case we discovered quite late that the insn that had been
8169 marked as can_throw_internal in fact couldn't trap at all.
8170 So we should in fact delete the EH edges out of the block. */
8172 purge_dead_edges (bb);
8176 /* We've possibly turned single trapping insn into multiple ones. */
8177 if (flag_non_call_exceptions)
8180 blocks = sbitmap_alloc (last_basic_block);
8181 sbitmap_ones (blocks);
8182 find_many_sub_basic_blocks (blocks);
8186 commit_edge_insertions ();
8188 #ifdef ENABLE_CHECKING
8189 /* Verify that we didn't turn one trapping insn into many, and that
8190 we found and corrected all of the problems wrt fixups on the
8192 verify_flow_info ();
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