1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-flags.h"
33 #include "insn-codes.h"
38 #include "basic-block.h"
46 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
47 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
85 #ifndef REGISTER_MOVE_COST
86 #define REGISTER_MOVE_COST(x, y) 2
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx *reg_equiv_constant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx *reg_equiv_address;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx *reg_equiv_init;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs[FIRST_PSEUDO_REGISTER];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET *pseudo_previous_regs;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET *pseudo_forbidden_regs;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table * reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 static void maybe_fix_stack_asms PARAMS ((void));
372 static void copy_reloads PARAMS ((struct insn_chain *));
373 static void calculate_needs_all_insns PARAMS ((int));
374 static int find_reg PARAMS ((struct insn_chain *, int,
376 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
377 static void select_reload_regs PARAMS ((FILE *));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, FILE *, int));
397 static int finish_spills PARAMS ((int, FILE *));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
414 rtx, rtx, int, int));
415 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
417 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
419 static void failed_reload PARAMS ((rtx, int));
420 static int set_reload_reg PARAMS ((int, int));
421 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
422 static void choose_reload_regs PARAMS ((struct insn_chain *));
423 static void merge_assigned_reloads PARAMS ((rtx));
424 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
425 struct reload *, rtx, int));
426 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
427 struct reload *, int));
428 static void do_input_reload PARAMS ((struct insn_chain *,
429 struct reload *, int));
430 static void do_output_reload PARAMS ((struct insn_chain *,
431 struct reload *, int));
432 static void emit_reload_insns PARAMS ((struct insn_chain *));
433 static void delete_output_reload PARAMS ((rtx, int, int));
434 static void delete_address_reloads PARAMS ((rtx, rtx));
435 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
436 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
437 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
438 static void reload_cse_regs_1 PARAMS ((rtx));
439 static int reload_cse_noop_set_p PARAMS ((rtx));
440 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
441 static int reload_cse_simplify_operands PARAMS ((rtx));
442 static void reload_combine PARAMS ((void));
443 static void reload_combine_note_use PARAMS ((rtx *, rtx));
444 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
445 static void reload_cse_move2add PARAMS ((rtx));
446 static void move2add_note_store PARAMS ((rtx, rtx, void *));
448 static void add_auto_inc_notes PARAMS ((rtx, rtx));
450 static rtx gen_mode_int PARAMS ((enum machine_mode,
452 static void failed_reload PARAMS ((rtx, int));
453 static int set_reload_reg PARAMS ((int, int));
454 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
455 static void reload_cse_simplify PARAMS ((rtx));
456 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
458 /* Initialize the reload pass once per compilation. */
465 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
466 Set spill_indirect_levels to the number of levels such addressing is
467 permitted, zero if it is not permitted at all. */
470 = gen_rtx_MEM (Pmode,
473 LAST_VIRTUAL_REGISTER + 1),
475 spill_indirect_levels = 0;
477 while (memory_address_p (QImode, tem))
479 spill_indirect_levels++;
480 tem = gen_rtx_MEM (Pmode, tem);
483 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
485 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
486 indirect_symref_ok = memory_address_p (QImode, tem);
488 /* See if reg+reg is a valid (and offsettable) address. */
490 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
492 tem = gen_rtx_PLUS (Pmode,
493 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
494 gen_rtx_REG (Pmode, i));
496 /* This way, we make sure that reg+reg is an offsettable address. */
497 tem = plus_constant (tem, 4);
499 if (memory_address_p (QImode, tem))
501 double_reg_address_ok = 1;
506 /* Initialize obstack for our rtl allocation. */
507 gcc_obstack_init (&reload_obstack);
508 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
510 INIT_REG_SET (&spilled_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = (struct insn_chain *)
526 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
527 INIT_REG_SET (&c->live_throughout);
528 INIT_REG_SET (&c->dead_or_set);
532 c = unused_insn_chains;
533 unused_insn_chains = c->next;
535 c->is_caller_save_insn = 0;
536 c->need_operand_change = 0;
542 /* Small utility function to set all regs in hard reg set TO which are
543 allocated to pseudos in regset FROM. */
546 compute_use_by_pseudos (to, from)
552 EXECUTE_IF_SET_IN_REG_SET
553 (from, FIRST_PSEUDO_REGISTER, regno,
555 int r = reg_renumber[regno];
560 /* reload_combine uses the information from
561 BASIC_BLOCK->global_live_at_start, which might still
562 contain registers that have not actually been allocated
563 since they have an equivalence. */
564 if (! reload_completed)
569 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
571 SET_HARD_REG_BIT (*to, r + nregs);
576 /* Global variables used by reload and its subroutines. */
578 /* Set during calculate_needs if an insn needs register elimination. */
579 static int something_needs_elimination;
580 /* Set during calculate_needs if an insn needs an operand changed. */
581 int something_needs_operands_changed;
583 /* Nonzero means we couldn't get enough spill regs. */
586 /* Main entry point for the reload pass.
588 FIRST is the first insn of the function being compiled.
590 GLOBAL nonzero means we were called from global_alloc
591 and should attempt to reallocate any pseudoregs that we
592 displace from hard regs we will use for reloads.
593 If GLOBAL is zero, we do not have enough information to do that,
594 so any pseudo reg that is spilled must go to the stack.
596 DUMPFILE is the global-reg debugging dump file stream, or 0.
597 If it is nonzero, messages are written to it to describe
598 which registers are seized as reload regs, which pseudo regs
599 are spilled from them, and where the pseudo regs are reallocated to.
601 Return value is nonzero if reload failed
602 and we must not do any more for this function. */
605 reload (first, global, dumpfile)
612 register struct elim_table *ep;
614 /* The two pointers used to track the true location of the memory used
615 for label offsets. */
616 char *real_known_ptr = NULL_PTR;
617 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
619 /* Make sure even insns with volatile mem refs are recognizable. */
624 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
626 /* Make sure that the last insn in the chain
627 is not something that needs reloading. */
628 emit_note (NULL_PTR, NOTE_INSN_DELETED);
630 /* Enable find_equiv_reg to distinguish insns made by reload. */
631 reload_first_uid = get_max_uid ();
633 #ifdef SECONDARY_MEMORY_NEEDED
634 /* Initialize the secondary memory table. */
635 clear_secondary_mem ();
638 /* We don't have a stack slot for any spill reg yet. */
639 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
640 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
642 /* Initialize the save area information for caller-save, in case some
646 /* Compute which hard registers are now in use
647 as homes for pseudo registers.
648 This is done here rather than (eg) in global_alloc
649 because this point is reached even if not optimizing. */
650 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
653 /* A function that receives a nonlocal goto must save all call-saved
655 if (current_function_has_nonlocal_label)
656 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
658 if (! call_used_regs[i] && ! fixed_regs[i])
659 regs_ever_live[i] = 1;
662 /* Find all the pseudo registers that didn't get hard regs
663 but do have known equivalent constants or memory slots.
664 These include parameters (known equivalent to parameter slots)
665 and cse'd or loop-moved constant memory addresses.
667 Record constant equivalents in reg_equiv_constant
668 so they will be substituted by find_reloads.
669 Record memory equivalents in reg_mem_equiv so they can
670 be substituted eventually by altering the REG-rtx's. */
672 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
674 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
675 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
676 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
677 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
678 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
679 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
680 pseudo_forbidden_regs
681 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
683 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
685 CLEAR_HARD_REG_SET (bad_spill_regs_global);
687 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
688 Also find all paradoxical subregs and find largest such for each pseudo.
689 On machines with small register classes, record hard registers that
690 are used for user variables. These can never be used for spills.
691 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
692 caller-saved registers must be marked live. */
694 num_eliminable_invariants = 0;
695 for (insn = first; insn; insn = NEXT_INSN (insn))
697 rtx set = single_set (insn);
699 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
700 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
701 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
702 if (! call_used_regs[i])
703 regs_ever_live[i] = 1;
705 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
707 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
709 #ifdef LEGITIMATE_PIC_OPERAND_P
710 && (! function_invariant_p (XEXP (note, 0))
712 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
716 rtx x = XEXP (note, 0);
717 i = REGNO (SET_DEST (set));
718 if (i > LAST_VIRTUAL_REGISTER)
720 if (GET_CODE (x) == MEM)
722 /* If the operand is a PLUS, the MEM may be shared,
723 so make sure we have an unshared copy here. */
724 if (GET_CODE (XEXP (x, 0)) == PLUS)
727 reg_equiv_memory_loc[i] = x;
729 else if (function_invariant_p (x))
731 if (GET_CODE (x) == PLUS)
733 /* This is PLUS of frame pointer and a constant,
734 and might be shared. Unshare it. */
735 reg_equiv_constant[i] = copy_rtx (x);
736 num_eliminable_invariants++;
738 else if (x == frame_pointer_rtx
739 || x == arg_pointer_rtx)
741 reg_equiv_constant[i] = x;
742 num_eliminable_invariants++;
744 else if (LEGITIMATE_CONSTANT_P (x))
745 reg_equiv_constant[i] = x;
747 reg_equiv_memory_loc[i]
748 = force_const_mem (GET_MODE (SET_DEST (set)), x);
753 /* If this register is being made equivalent to a MEM
754 and the MEM is not SET_SRC, the equivalencing insn
755 is one with the MEM as a SET_DEST and it occurs later.
756 So don't mark this insn now. */
757 if (GET_CODE (x) != MEM
758 || rtx_equal_p (SET_SRC (set), x))
760 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
765 /* If this insn is setting a MEM from a register equivalent to it,
766 this is the equivalencing insn. */
767 else if (set && GET_CODE (SET_DEST (set)) == MEM
768 && GET_CODE (SET_SRC (set)) == REG
769 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
770 && rtx_equal_p (SET_DEST (set),
771 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
772 reg_equiv_init[REGNO (SET_SRC (set))]
773 = gen_rtx_INSN_LIST (VOIDmode, insn,
774 reg_equiv_init[REGNO (SET_SRC (set))]);
776 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
777 scan_paradoxical_subregs (PATTERN (insn));
782 num_labels = max_label_num () - get_first_label_num ();
784 /* Allocate the tables used to store offset information at labels. */
785 /* We used to use alloca here, but the size of what it would try to
786 allocate would occasionally cause it to exceed the stack limit and
787 cause a core dump. */
788 real_known_ptr = xmalloc (num_labels);
790 = (int (*)[NUM_ELIMINABLE_REGS])
791 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
793 offsets_known_at = real_known_ptr - get_first_label_num ();
795 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
797 /* Alter each pseudo-reg rtx to contain its hard reg number.
798 Assign stack slots to the pseudos that lack hard regs or equivalents.
799 Do not touch virtual registers. */
801 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
804 /* If we have some registers we think can be eliminated, scan all insns to
805 see if there is an insn that sets one of these registers to something
806 other than itself plus a constant. If so, the register cannot be
807 eliminated. Doing this scan here eliminates an extra pass through the
808 main reload loop in the most common case where register elimination
810 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
811 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
812 || GET_CODE (insn) == CALL_INSN)
813 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
815 maybe_fix_stack_asms ();
817 insns_need_reload = 0;
818 something_needs_elimination = 0;
820 /* Initialize to -1, which means take the first spill register. */
823 /* Spill any hard regs that we know we can't eliminate. */
824 CLEAR_HARD_REG_SET (used_spill_regs);
825 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
826 if (! ep->can_eliminate)
827 spill_hard_reg (ep->from, dumpfile, 1);
829 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
830 if (frame_pointer_needed)
831 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
833 finish_spills (global, dumpfile);
835 /* From now on, we may need to generate moves differently. We may also
836 allow modifications of insns which cause them to not be recognized.
837 Any such modifications will be cleaned up during reload itself. */
838 reload_in_progress = 1;
840 /* This loop scans the entire function each go-round
841 and repeats until one repetition spills no additional hard regs. */
844 int something_changed;
847 HOST_WIDE_INT starting_frame_size;
849 /* Round size of stack frame to stack_alignment_needed. This must be done
850 here because the stack size may be a part of the offset computation
851 for register elimination, and there might have been new stack slots
852 created in the last iteration of this loop. */
853 if (cfun->stack_alignment_needed)
854 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
856 starting_frame_size = get_frame_size ();
858 set_initial_elim_offsets ();
859 set_initial_label_offsets ();
861 /* For each pseudo register that has an equivalent location defined,
862 try to eliminate any eliminable registers (such as the frame pointer)
863 assuming initial offsets for the replacement register, which
866 If the resulting location is directly addressable, substitute
867 the MEM we just got directly for the old REG.
869 If it is not addressable but is a constant or the sum of a hard reg
870 and constant, it is probably not addressable because the constant is
871 out of range, in that case record the address; we will generate
872 hairy code to compute the address in a register each time it is
873 needed. Similarly if it is a hard register, but one that is not
874 valid as an address register.
876 If the location is not addressable, but does not have one of the
877 above forms, assign a stack slot. We have to do this to avoid the
878 potential of producing lots of reloads if, e.g., a location involves
879 a pseudo that didn't get a hard register and has an equivalent memory
880 location that also involves a pseudo that didn't get a hard register.
882 Perhaps at some point we will improve reload_when_needed handling
883 so this problem goes away. But that's very hairy. */
885 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
886 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
888 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
890 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
892 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
893 else if (CONSTANT_P (XEXP (x, 0))
894 || (GET_CODE (XEXP (x, 0)) == REG
895 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 || (GET_CODE (XEXP (x, 0)) == PLUS
897 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
898 && (REGNO (XEXP (XEXP (x, 0), 0))
899 < FIRST_PSEUDO_REGISTER)
900 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc[i] = 0;
911 reg_equiv_init[i] = 0;
916 if (caller_save_needed)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (starting_frame_size != get_frame_size ())
923 if (caller_save_needed)
925 save_call_clobbered_regs ();
926 /* That might have allocated new insn_chain structures. */
927 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
930 calculate_needs_all_insns (global);
932 CLEAR_REG_SET (&spilled_pseudos);
935 something_changed = 0;
937 /* If we allocated any new memory locations, make another pass
938 since it might have changed elimination offsets. */
939 if (starting_frame_size != get_frame_size ())
940 something_changed = 1;
943 HARD_REG_SET to_spill;
944 CLEAR_HARD_REG_SET (to_spill);
945 update_eliminables (&to_spill);
946 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
947 if (TEST_HARD_REG_BIT (to_spill, i))
949 spill_hard_reg (i, dumpfile, 1);
952 /* Regardless of the state of spills, if we previously had
953 a register that we thought we could eliminate, but no can
954 not eliminate, we must run another pass.
956 Consider pseudos which have an entry in reg_equiv_* which
957 reference an eliminable register. We must make another pass
958 to update reg_equiv_* so that we do not substitute in the
959 old value from when we thought the elimination could be
961 something_changed = 1;
965 select_reload_regs (dumpfile);
969 if (insns_need_reload != 0 || did_spill)
970 something_changed |= finish_spills (global, dumpfile);
972 if (! something_changed)
975 if (caller_save_needed)
976 delete_caller_save_insns ();
978 obstack_free (&reload_obstack, reload_firstobj);
981 /* If global-alloc was run, notify it of any register eliminations we have
984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
985 if (ep->can_eliminate)
986 mark_elimination (ep->from, ep->to);
988 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
989 If that insn didn't set the register (i.e., it copied the register to
990 memory), just delete that insn instead of the equivalencing insn plus
991 anything now dead. If we call delete_dead_insn on that insn, we may
992 delete the insn that actually sets the register if the register dies
993 there and that is incorrect. */
995 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
997 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1000 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1002 rtx equiv_insn = XEXP (list, 0);
1003 if (GET_CODE (equiv_insn) == NOTE)
1005 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1006 delete_dead_insn (equiv_insn);
1009 PUT_CODE (equiv_insn, NOTE);
1010 NOTE_SOURCE_FILE (equiv_insn) = 0;
1011 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1017 /* Use the reload registers where necessary
1018 by generating move instructions to move the must-be-register
1019 values into or out of the reload registers. */
1021 if (insns_need_reload != 0 || something_needs_elimination
1022 || something_needs_operands_changed)
1024 int old_frame_size = get_frame_size ();
1026 reload_as_needed (global);
1028 if (old_frame_size != get_frame_size ())
1032 verify_initial_elim_offsets ();
1035 /* If we were able to eliminate the frame pointer, show that it is no
1036 longer live at the start of any basic block. If it ls live by
1037 virtue of being in a pseudo, that pseudo will be marked live
1038 and hence the frame pointer will be known to be live via that
1041 if (! frame_pointer_needed)
1042 for (i = 0; i < n_basic_blocks; i++)
1043 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1044 HARD_FRAME_POINTER_REGNUM);
1046 /* Come here (with failure set nonzero) if we can't get enough spill regs
1047 and we decide not to abort about it. */
1050 CLEAR_REG_SET (&spilled_pseudos);
1051 reload_in_progress = 0;
1053 /* Now eliminate all pseudo regs by modifying them into
1054 their equivalent memory references.
1055 The REG-rtx's for the pseudos are modified in place,
1056 so all insns that used to refer to them now refer to memory.
1058 For a reg that has a reg_equiv_address, all those insns
1059 were changed by reloading so that no insns refer to it any longer;
1060 but the DECL_RTL of a variable decl may refer to it,
1061 and if so this causes the debugging info to mention the variable. */
1063 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1068 int is_readonly = 0;
1070 if (reg_equiv_memory_loc[i])
1072 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1073 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1074 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1077 if (reg_equiv_mem[i])
1078 addr = XEXP (reg_equiv_mem[i], 0);
1080 if (reg_equiv_address[i])
1081 addr = reg_equiv_address[i];
1085 if (reg_renumber[i] < 0)
1087 rtx reg = regno_reg_rtx[i];
1088 PUT_CODE (reg, MEM);
1089 XEXP (reg, 0) = addr;
1090 REG_USERVAR_P (reg) = 0;
1091 RTX_UNCHANGING_P (reg) = is_readonly;
1092 MEM_IN_STRUCT_P (reg) = in_struct;
1093 MEM_SCALAR_P (reg) = is_scalar;
1094 /* We have no alias information about this newly created
1096 MEM_ALIAS_SET (reg) = 0;
1098 else if (reg_equiv_mem[i])
1099 XEXP (reg_equiv_mem[i], 0) = addr;
1103 /* We must set reload_completed now since the cleanup_subreg_operands call
1104 below will re-recognize each insn and reload may have generated insns
1105 which are only valid during and after reload. */
1106 reload_completed = 1;
1108 /* Make a pass over all the insns and delete all USEs which we inserted
1109 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1110 notes. Delete all CLOBBER insns that don't refer to the return value
1111 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1112 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1113 and regenerate REG_INC notes that may have been moved around. */
1115 for (insn = first; insn; insn = NEXT_INSN (insn))
1116 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1120 if ((GET_CODE (PATTERN (insn)) == USE
1121 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1122 || (GET_CODE (PATTERN (insn)) == CLOBBER
1123 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1124 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1126 PUT_CODE (insn, NOTE);
1127 NOTE_SOURCE_FILE (insn) = 0;
1128 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1132 pnote = ®_NOTES (insn);
1135 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1136 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1137 || REG_NOTE_KIND (*pnote) == REG_INC
1138 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1139 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1140 *pnote = XEXP (*pnote, 1);
1142 pnote = &XEXP (*pnote, 1);
1146 add_auto_inc_notes (insn, PATTERN (insn));
1149 /* And simplify (subreg (reg)) if it appears as an operand. */
1150 cleanup_subreg_operands (insn);
1153 /* If we are doing stack checking, give a warning if this function's
1154 frame size is larger than we expect. */
1155 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1157 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1158 static int verbose_warned = 0;
1160 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1161 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1162 size += UNITS_PER_WORD;
1164 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1166 warning ("frame size too large for reliable stack checking");
1167 if (! verbose_warned)
1169 warning ("try reducing the number of local variables");
1175 /* Indicate that we no longer have known memory locations or constants. */
1176 if (reg_equiv_constant)
1177 free (reg_equiv_constant);
1178 reg_equiv_constant = 0;
1179 if (reg_equiv_memory_loc)
1180 free (reg_equiv_memory_loc);
1181 reg_equiv_memory_loc = 0;
1184 free (real_known_ptr);
1188 free (reg_equiv_mem);
1189 free (reg_equiv_init);
1190 free (reg_equiv_address);
1191 free (reg_max_ref_width);
1192 free (reg_old_renumber);
1193 free (pseudo_previous_regs);
1194 free (pseudo_forbidden_regs);
1196 CLEAR_HARD_REG_SET (used_spill_regs);
1197 for (i = 0; i < n_spills; i++)
1198 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1200 /* Free all the insn_chain structures at once. */
1201 obstack_free (&reload_obstack, reload_startobj);
1202 unused_insn_chains = 0;
1207 /* Yet another special case. Unfortunately, reg-stack forces people to
1208 write incorrect clobbers in asm statements. These clobbers must not
1209 cause the register to appear in bad_spill_regs, otherwise we'll call
1210 fatal_insn later. We clear the corresponding regnos in the live
1211 register sets to avoid this.
1212 The whole thing is rather sick, I'm afraid. */
1215 maybe_fix_stack_asms ()
1218 const char *constraints[MAX_RECOG_OPERANDS];
1219 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1220 struct insn_chain *chain;
1222 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1225 HARD_REG_SET clobbered, allowed;
1228 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1229 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1231 pat = PATTERN (chain->insn);
1232 if (GET_CODE (pat) != PARALLEL)
1235 CLEAR_HARD_REG_SET (clobbered);
1236 CLEAR_HARD_REG_SET (allowed);
1238 /* First, make a mask of all stack regs that are clobbered. */
1239 for (i = 0; i < XVECLEN (pat, 0); i++)
1241 rtx t = XVECEXP (pat, 0, i);
1242 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1243 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1246 /* Get the operand values and constraints out of the insn. */
1247 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1248 constraints, operand_mode);
1250 /* For every operand, see what registers are allowed. */
1251 for (i = 0; i < noperands; i++)
1253 const char *p = constraints[i];
1254 /* For every alternative, we compute the class of registers allowed
1255 for reloading in CLS, and merge its contents into the reg set
1257 int cls = (int) NO_REGS;
1263 if (c == '\0' || c == ',' || c == '#')
1265 /* End of one alternative - mark the regs in the current
1266 class, and reset the class. */
1267 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1272 } while (c != '\0' && c != ',');
1280 case '=': case '+': case '*': case '%': case '?': case '!':
1281 case '0': case '1': case '2': case '3': case '4': case 'm':
1282 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1283 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1284 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1286 #ifdef EXTRA_CONSTRAINT
1287 case 'Q': case 'R': case 'S': case 'T': case 'U':
1292 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1297 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1301 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1306 /* Those of the registers which are clobbered, but allowed by the
1307 constraints, must be usable as reload registers. So clear them
1308 out of the life information. */
1309 AND_HARD_REG_SET (allowed, clobbered);
1310 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1311 if (TEST_HARD_REG_BIT (allowed, i))
1313 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1314 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1321 /* Copy the global variables n_reloads and rld into the corresponding elts
1324 copy_reloads (chain)
1325 struct insn_chain *chain;
1327 chain->n_reloads = n_reloads;
1329 = (struct reload *) obstack_alloc (&reload_obstack,
1330 n_reloads * sizeof (struct reload));
1331 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1332 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1335 /* Walk the chain of insns, and determine for each whether it needs reloads
1336 and/or eliminations. Build the corresponding insns_need_reload list, and
1337 set something_needs_elimination as appropriate. */
1339 calculate_needs_all_insns (global)
1342 struct insn_chain **pprev_reload = &insns_need_reload;
1343 struct insn_chain *chain;
1345 something_needs_elimination = 0;
1347 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1348 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1350 rtx insn = chain->insn;
1352 /* Clear out the shortcuts. */
1353 chain->n_reloads = 0;
1354 chain->need_elim = 0;
1355 chain->need_reload = 0;
1356 chain->need_operand_change = 0;
1358 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1359 include REG_LABEL), we need to see what effects this has on the
1360 known offsets at labels. */
1362 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1363 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1364 && REG_NOTES (insn) != 0))
1365 set_label_offsets (insn, insn, 0);
1367 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1369 rtx old_body = PATTERN (insn);
1370 int old_code = INSN_CODE (insn);
1371 rtx old_notes = REG_NOTES (insn);
1372 int did_elimination = 0;
1373 int operands_changed = 0;
1374 rtx set = single_set (insn);
1376 /* Skip insns that only set an equivalence. */
1377 if (set && GET_CODE (SET_DEST (set)) == REG
1378 && reg_renumber[REGNO (SET_DEST (set))] < 0
1379 && reg_equiv_constant[REGNO (SET_DEST (set))])
1382 /* If needed, eliminate any eliminable registers. */
1383 if (num_eliminable || num_eliminable_invariants)
1384 did_elimination = eliminate_regs_in_insn (insn, 0);
1386 /* Analyze the instruction. */
1387 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1388 global, spill_reg_order);
1390 /* If a no-op set needs more than one reload, this is likely
1391 to be something that needs input address reloads. We
1392 can't get rid of this cleanly later, and it is of no use
1393 anyway, so discard it now.
1394 We only do this when expensive_optimizations is enabled,
1395 since this complements reload inheritance / output
1396 reload deletion, and it can make debugging harder. */
1397 if (flag_expensive_optimizations && n_reloads > 1)
1399 rtx set = single_set (insn);
1401 && SET_SRC (set) == SET_DEST (set)
1402 && GET_CODE (SET_SRC (set)) == REG
1403 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1405 PUT_CODE (insn, NOTE);
1406 NOTE_SOURCE_FILE (insn) = 0;
1407 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1412 update_eliminable_offsets ();
1414 /* Remember for later shortcuts which insns had any reloads or
1415 register eliminations. */
1416 chain->need_elim = did_elimination;
1417 chain->need_reload = n_reloads > 0;
1418 chain->need_operand_change = operands_changed;
1420 /* Discard any register replacements done. */
1421 if (did_elimination)
1423 obstack_free (&reload_obstack, reload_insn_firstobj);
1424 PATTERN (insn) = old_body;
1425 INSN_CODE (insn) = old_code;
1426 REG_NOTES (insn) = old_notes;
1427 something_needs_elimination = 1;
1430 something_needs_operands_changed |= operands_changed;
1434 copy_reloads (chain);
1435 *pprev_reload = chain;
1436 pprev_reload = &chain->next_need_reload;
1443 /* Comparison function for qsort to decide which of two reloads
1444 should be handled first. *P1 and *P2 are the reload numbers. */
1447 reload_reg_class_lower (r1p, r2p)
1451 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1454 /* Consider required reloads before optional ones. */
1455 t = rld[r1].optional - rld[r2].optional;
1459 /* Count all solitary classes before non-solitary ones. */
1460 t = ((reg_class_size[(int) rld[r2].class] == 1)
1461 - (reg_class_size[(int) rld[r1].class] == 1));
1465 /* Aside from solitaires, consider all multi-reg groups first. */
1466 t = rld[r2].nregs - rld[r1].nregs;
1470 /* Consider reloads in order of increasing reg-class number. */
1471 t = (int) rld[r1].class - (int) rld[r2].class;
1475 /* If reloads are equally urgent, sort by reload number,
1476 so that the results of qsort leave nothing to chance. */
1480 /* The cost of spilling each hard reg. */
1481 static int spill_cost[FIRST_PSEUDO_REGISTER];
1483 /* When spilling multiple hard registers, we use SPILL_COST for the first
1484 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1485 only the first hard reg for a multi-reg pseudo. */
1486 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1488 /* Update the spill cost arrays, considering that pseudo REG is live. */
1494 int n_refs = REG_N_REFS (reg);
1495 int r = reg_renumber[reg];
1498 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1499 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1502 SET_REGNO_REG_SET (&pseudos_counted, reg);
1507 spill_add_cost[r] += n_refs;
1509 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1511 spill_cost[r + nregs] += n_refs;
1514 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1515 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1518 order_regs_for_reload (chain)
1519 struct insn_chain *chain;
1522 HARD_REG_SET used_by_pseudos;
1523 HARD_REG_SET used_by_pseudos2;
1525 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1527 memset (spill_cost, 0, sizeof spill_cost);
1528 memset (spill_add_cost, 0, sizeof spill_add_cost);
1530 /* Count number of uses of each hard reg by pseudo regs allocated to it
1531 and then order them by decreasing use. First exclude hard registers
1532 that are live in or across this insn. */
1534 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1535 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1536 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1537 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1539 /* Now find out which pseudos are allocated to it, and update
1541 CLEAR_REG_SET (&pseudos_counted);
1543 EXECUTE_IF_SET_IN_REG_SET
1544 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1548 EXECUTE_IF_SET_IN_REG_SET
1549 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1553 CLEAR_REG_SET (&pseudos_counted);
1556 /* Vector of reload-numbers showing the order in which the reloads should
1558 static short reload_order[MAX_RELOADS];
1560 /* This is used to keep track of the spill regs used in one insn. */
1561 static HARD_REG_SET used_spill_regs_local;
1563 /* We decided to spill hard register SPILLED, which has a size of
1564 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1565 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1566 update SPILL_COST/SPILL_ADD_COST. */
1569 count_spilled_pseudo (spilled, spilled_nregs, reg)
1570 int spilled, spilled_nregs, reg;
1572 int r = reg_renumber[reg];
1573 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1575 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1576 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1579 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1581 spill_add_cost[r] -= REG_N_REFS (reg);
1583 spill_cost[r + nregs] -= REG_N_REFS (reg);
1586 /* Find reload register to use for reload number ORDER. */
1589 find_reg (chain, order, dumpfile)
1590 struct insn_chain *chain;
1594 int rnum = reload_order[order];
1595 struct reload *rl = rld + rnum;
1596 int best_cost = INT_MAX;
1600 HARD_REG_SET not_usable;
1601 HARD_REG_SET used_by_other_reload;
1603 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1604 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1605 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1607 CLEAR_HARD_REG_SET (used_by_other_reload);
1608 for (k = 0; k < order; k++)
1610 int other = reload_order[k];
1612 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1613 for (j = 0; j < rld[other].nregs; j++)
1614 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1617 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1619 unsigned int regno = i;
1621 if (! TEST_HARD_REG_BIT (not_usable, regno)
1622 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1623 && HARD_REGNO_MODE_OK (regno, rl->mode))
1625 int this_cost = spill_cost[regno];
1627 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1629 for (j = 1; j < this_nregs; j++)
1631 this_cost += spill_add_cost[regno + j];
1632 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1633 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1638 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1640 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1642 if (this_cost < best_cost
1643 /* Among registers with equal cost, prefer caller-saved ones, or
1644 use REG_ALLOC_ORDER if it is defined. */
1645 || (this_cost == best_cost
1646 #ifdef REG_ALLOC_ORDER
1647 && (inv_reg_alloc_order[regno]
1648 < inv_reg_alloc_order[best_reg])
1650 && call_used_regs[regno]
1651 && ! call_used_regs[best_reg]
1656 best_cost = this_cost;
1664 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1666 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1667 rl->regno = best_reg;
1669 EXECUTE_IF_SET_IN_REG_SET
1670 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1672 count_spilled_pseudo (best_reg, rl->nregs, j);
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1678 count_spilled_pseudo (best_reg, rl->nregs, j);
1681 for (i = 0; i < rl->nregs; i++)
1683 if (spill_cost[best_reg + i] != 0
1684 || spill_add_cost[best_reg + i] != 0)
1686 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1691 /* Find more reload regs to satisfy the remaining need of an insn, which
1693 Do it by ascending class number, since otherwise a reg
1694 might be spilled for a big class and might fail to count
1695 for a smaller class even though it belongs to that class. */
1698 find_reload_regs (chain, dumpfile)
1699 struct insn_chain *chain;
1704 /* In order to be certain of getting the registers we need,
1705 we must sort the reloads into order of increasing register class.
1706 Then our grabbing of reload registers will parallel the process
1707 that provided the reload registers. */
1708 for (i = 0; i < chain->n_reloads; i++)
1710 /* Show whether this reload already has a hard reg. */
1711 if (chain->rld[i].reg_rtx)
1713 int regno = REGNO (chain->rld[i].reg_rtx);
1714 chain->rld[i].regno = regno;
1716 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1719 chain->rld[i].regno = -1;
1720 reload_order[i] = i;
1723 n_reloads = chain->n_reloads;
1724 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1726 CLEAR_HARD_REG_SET (used_spill_regs_local);
1729 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1731 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1733 /* Compute the order of preference for hard registers to spill. */
1735 order_regs_for_reload (chain);
1737 for (i = 0; i < n_reloads; i++)
1739 int r = reload_order[i];
1741 /* Ignore reloads that got marked inoperative. */
1742 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1743 && ! rld[r].optional
1744 && rld[r].regno == -1)
1745 if (! find_reg (chain, i, dumpfile))
1747 spill_failure (chain->insn, rld[r].class);
1753 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1754 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1756 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1760 select_reload_regs (dumpfile)
1763 struct insn_chain *chain;
1765 /* Try to satisfy the needs for each insn. */
1766 for (chain = insns_need_reload; chain != 0;
1767 chain = chain->next_need_reload)
1768 find_reload_regs (chain, dumpfile);
1771 /* Delete all insns that were inserted by emit_caller_save_insns during
1774 delete_caller_save_insns ()
1776 struct insn_chain *c = reload_insn_chain;
1780 while (c != 0 && c->is_caller_save_insn)
1782 struct insn_chain *next = c->next;
1785 if (insn == BLOCK_HEAD (c->block))
1786 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1787 if (insn == BLOCK_END (c->block))
1788 BLOCK_END (c->block) = PREV_INSN (insn);
1789 if (c == reload_insn_chain)
1790 reload_insn_chain = next;
1792 if (NEXT_INSN (insn) != 0)
1793 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1794 if (PREV_INSN (insn) != 0)
1795 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1798 next->prev = c->prev;
1800 c->prev->next = next;
1801 c->next = unused_insn_chains;
1802 unused_insn_chains = c;
1810 /* Handle the failure to find a register to spill.
1811 INSN should be one of the insns which needed this particular spill reg. */
1814 spill_failure (insn, class)
1816 enum reg_class class;
1818 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1819 if (asm_noperands (PATTERN (insn)) >= 0)
1820 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1821 reg_class_names[class]);
1824 error ("Unable to find a register to spill in class `%s'.",
1825 reg_class_names[class]);
1826 fatal_insn ("This is the insn:", insn);
1830 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1831 data that is dead in INSN. */
1834 delete_dead_insn (insn)
1837 rtx prev = prev_real_insn (insn);
1840 /* If the previous insn sets a register that dies in our insn, delete it
1842 if (prev && GET_CODE (PATTERN (prev)) == SET
1843 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1844 && reg_mentioned_p (prev_dest, PATTERN (insn))
1845 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1846 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1847 delete_dead_insn (prev);
1849 PUT_CODE (insn, NOTE);
1850 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1851 NOTE_SOURCE_FILE (insn) = 0;
1854 /* Modify the home of pseudo-reg I.
1855 The new home is present in reg_renumber[I].
1857 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1858 or it may be -1, meaning there is none or it is not relevant.
1859 This is used so that all pseudos spilled from a given hard reg
1860 can share one stack slot. */
1863 alter_reg (i, from_reg)
1867 /* When outputting an inline function, this can happen
1868 for a reg that isn't actually used. */
1869 if (regno_reg_rtx[i] == 0)
1872 /* If the reg got changed to a MEM at rtl-generation time,
1874 if (GET_CODE (regno_reg_rtx[i]) != REG)
1877 /* Modify the reg-rtx to contain the new hard reg
1878 number or else to contain its pseudo reg number. */
1879 REGNO (regno_reg_rtx[i])
1880 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1882 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1883 allocate a stack slot for it. */
1885 if (reg_renumber[i] < 0
1886 && REG_N_REFS (i) > 0
1887 && reg_equiv_constant[i] == 0
1888 && reg_equiv_memory_loc[i] == 0)
1891 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1892 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1895 /* Each pseudo reg has an inherent size which comes from its own mode,
1896 and a total size which provides room for paradoxical subregs
1897 which refer to the pseudo reg in wider modes.
1899 We can use a slot already allocated if it provides both
1900 enough inherent space and enough total space.
1901 Otherwise, we allocate a new slot, making sure that it has no less
1902 inherent space, and no less total space, then the previous slot. */
1905 /* No known place to spill from => no slot to reuse. */
1906 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1907 inherent_size == total_size ? 0 : -1);
1908 if (BYTES_BIG_ENDIAN)
1909 /* Cancel the big-endian correction done in assign_stack_local.
1910 Get the address of the beginning of the slot.
1911 This is so we can do a big-endian correction unconditionally
1913 adjust = inherent_size - total_size;
1915 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1917 /* Nothing can alias this slot except this pseudo. */
1918 MEM_ALIAS_SET (x) = new_alias_set ();
1921 /* Reuse a stack slot if possible. */
1922 else if (spill_stack_slot[from_reg] != 0
1923 && spill_stack_slot_width[from_reg] >= total_size
1924 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1926 x = spill_stack_slot[from_reg];
1928 /* Allocate a bigger slot. */
1931 /* Compute maximum size needed, both for inherent size
1932 and for total size. */
1933 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1936 if (spill_stack_slot[from_reg])
1938 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1940 mode = GET_MODE (spill_stack_slot[from_reg]);
1941 if (spill_stack_slot_width[from_reg] > total_size)
1942 total_size = spill_stack_slot_width[from_reg];
1945 /* Make a slot with that size. */
1946 x = assign_stack_local (mode, total_size,
1947 inherent_size == total_size ? 0 : -1);
1950 /* All pseudos mapped to this slot can alias each other. */
1951 if (spill_stack_slot[from_reg])
1952 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1954 MEM_ALIAS_SET (x) = new_alias_set ();
1956 if (BYTES_BIG_ENDIAN)
1958 /* Cancel the big-endian correction done in assign_stack_local.
1959 Get the address of the beginning of the slot.
1960 This is so we can do a big-endian correction unconditionally
1962 adjust = GET_MODE_SIZE (mode) - total_size;
1964 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1967 plus_constant (XEXP (x, 0), adjust));
1970 spill_stack_slot[from_reg] = stack_slot;
1971 spill_stack_slot_width[from_reg] = total_size;
1974 /* On a big endian machine, the "address" of the slot
1975 is the address of the low part that fits its inherent mode. */
1976 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1977 adjust += (total_size - inherent_size);
1979 /* If we have any adjustment to make, or if the stack slot is the
1980 wrong mode, make a new stack slot. */
1981 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1983 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1984 plus_constant (XEXP (x, 0), adjust));
1986 MEM_COPY_ATTRIBUTES (new, x);
1990 /* Save the stack slot for later. */
1991 reg_equiv_memory_loc[i] = x;
1995 /* Mark the slots in regs_ever_live for the hard regs
1996 used by pseudo-reg number REGNO. */
1999 mark_home_live (regno)
2002 register int i, lim;
2004 i = reg_renumber[regno];
2007 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2009 regs_ever_live[i++] = 1;
2012 /* This function handles the tracking of elimination offsets around branches.
2014 X is a piece of RTL being scanned.
2016 INSN is the insn that it came from, if any.
2018 INITIAL_P is non-zero if we are to set the offset to be the initial
2019 offset and zero if we are setting the offset of the label to be the
2023 set_label_offsets (x, insn, initial_p)
2028 enum rtx_code code = GET_CODE (x);
2031 struct elim_table *p;
2036 if (LABEL_REF_NONLOCAL_P (x))
2041 /* ... fall through ... */
2044 /* If we know nothing about this label, set the desired offsets. Note
2045 that this sets the offset at a label to be the offset before a label
2046 if we don't know anything about the label. This is not correct for
2047 the label after a BARRIER, but is the best guess we can make. If
2048 we guessed wrong, we will suppress an elimination that might have
2049 been possible had we been able to guess correctly. */
2051 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2053 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2054 offsets_at[CODE_LABEL_NUMBER (x)][i]
2055 = (initial_p ? reg_eliminate[i].initial_offset
2056 : reg_eliminate[i].offset);
2057 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2060 /* Otherwise, if this is the definition of a label and it is
2061 preceded by a BARRIER, set our offsets to the known offset of
2065 && (tem = prev_nonnote_insn (insn)) != 0
2066 && GET_CODE (tem) == BARRIER)
2067 set_offsets_for_label (insn);
2069 /* If neither of the above cases is true, compare each offset
2070 with those previously recorded and suppress any eliminations
2071 where the offsets disagree. */
2073 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2074 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2075 != (initial_p ? reg_eliminate[i].initial_offset
2076 : reg_eliminate[i].offset))
2077 reg_eliminate[i].can_eliminate = 0;
2082 set_label_offsets (PATTERN (insn), insn, initial_p);
2084 /* ... fall through ... */
2088 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2089 and hence must have all eliminations at their initial offsets. */
2090 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2091 if (REG_NOTE_KIND (tem) == REG_LABEL)
2092 set_label_offsets (XEXP (tem, 0), insn, 1);
2097 /* Each of the labels in the address vector must be at their initial
2098 offsets. We want the first field for ADDR_VEC and the second
2099 field for ADDR_DIFF_VEC. */
2101 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2102 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2107 /* We only care about setting PC. If the source is not RETURN,
2108 IF_THEN_ELSE, or a label, disable any eliminations not at
2109 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2110 isn't one of those possibilities. For branches to a label,
2111 call ourselves recursively.
2113 Note that this can disable elimination unnecessarily when we have
2114 a non-local goto since it will look like a non-constant jump to
2115 someplace in the current function. This isn't a significant
2116 problem since such jumps will normally be when all elimination
2117 pairs are back to their initial offsets. */
2119 if (SET_DEST (x) != pc_rtx)
2122 switch (GET_CODE (SET_SRC (x)))
2129 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2133 tem = XEXP (SET_SRC (x), 1);
2134 if (GET_CODE (tem) == LABEL_REF)
2135 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2136 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2139 tem = XEXP (SET_SRC (x), 2);
2140 if (GET_CODE (tem) == LABEL_REF)
2141 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2142 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2150 /* If we reach here, all eliminations must be at their initial
2151 offset because we are doing a jump to a variable address. */
2152 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2153 if (p->offset != p->initial_offset)
2154 p->can_eliminate = 0;
2162 /* Scan X and replace any eliminable registers (such as fp) with a
2163 replacement (such as sp), plus an offset.
2165 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2166 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2167 MEM, we are allowed to replace a sum of a register and the constant zero
2168 with the register, which we cannot do outside a MEM. In addition, we need
2169 to record the fact that a register is referenced outside a MEM.
2171 If INSN is an insn, it is the insn containing X. If we replace a REG
2172 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2173 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2174 the REG is being modified.
2176 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2177 That's used when we eliminate in expressions stored in notes.
2178 This means, do not set ref_outside_mem even if the reference
2181 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2182 replacements done assuming all offsets are at their initial values. If
2183 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2184 encounter, return the actual location so that find_reloads will do
2185 the proper thing. */
2188 eliminate_regs (x, mem_mode, insn)
2190 enum machine_mode mem_mode;
2193 enum rtx_code code = GET_CODE (x);
2194 struct elim_table *ep;
2201 if (! current_function_decl)
2220 /* This is only for the benefit of the debugging backends, which call
2221 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2222 removed after CSE. */
2223 new = eliminate_regs (XEXP (x, 0), 0, insn);
2224 if (GET_CODE (new) == MEM)
2225 return XEXP (new, 0);
2231 /* First handle the case where we encounter a bare register that
2232 is eliminable. Replace it with a PLUS. */
2233 if (regno < FIRST_PSEUDO_REGISTER)
2235 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2237 if (ep->from_rtx == x && ep->can_eliminate)
2238 return plus_constant (ep->to_rtx, ep->previous_offset);
2241 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2242 && reg_equiv_constant[regno]
2243 && ! CONSTANT_P (reg_equiv_constant[regno]))
2244 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2248 /* You might think handling MINUS in a manner similar to PLUS is a
2249 good idea. It is not. It has been tried multiple times and every
2250 time the change has had to have been reverted.
2252 Other parts of reload know a PLUS is special (gen_reload for example)
2253 and require special code to handle code a reloaded PLUS operand.
2255 Also consider backends where the flags register is clobbered by a
2256 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2257 lea instruction comes to mind). If we try to reload a MINUS, we
2258 may kill the flags register that was holding a useful value.
2260 So, please before trying to handle MINUS, consider reload as a
2261 whole instead of this little section as well as the backend issues. */
2263 /* If this is the sum of an eliminable register and a constant, rework
2265 if (GET_CODE (XEXP (x, 0)) == REG
2266 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2267 && CONSTANT_P (XEXP (x, 1)))
2269 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2271 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2273 /* The only time we want to replace a PLUS with a REG (this
2274 occurs when the constant operand of the PLUS is the negative
2275 of the offset) is when we are inside a MEM. We won't want
2276 to do so at other times because that would change the
2277 structure of the insn in a way that reload can't handle.
2278 We special-case the commonest situation in
2279 eliminate_regs_in_insn, so just replace a PLUS with a
2280 PLUS here, unless inside a MEM. */
2281 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2282 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2285 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2286 plus_constant (XEXP (x, 1),
2287 ep->previous_offset));
2290 /* If the register is not eliminable, we are done since the other
2291 operand is a constant. */
2295 /* If this is part of an address, we want to bring any constant to the
2296 outermost PLUS. We will do this by doing register replacement in
2297 our operands and seeing if a constant shows up in one of them.
2299 Note that there is no risk of modifying the structure of the insn,
2300 since we only get called for its operands, thus we are either
2301 modifying the address inside a MEM, or something like an address
2302 operand of a load-address insn. */
2305 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2306 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2308 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2310 /* If one side is a PLUS and the other side is a pseudo that
2311 didn't get a hard register but has a reg_equiv_constant,
2312 we must replace the constant here since it may no longer
2313 be in the position of any operand. */
2314 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2315 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2316 && reg_renumber[REGNO (new1)] < 0
2317 && reg_equiv_constant != 0
2318 && reg_equiv_constant[REGNO (new1)] != 0)
2319 new1 = reg_equiv_constant[REGNO (new1)];
2320 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2321 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2322 && reg_renumber[REGNO (new0)] < 0
2323 && reg_equiv_constant[REGNO (new0)] != 0)
2324 new0 = reg_equiv_constant[REGNO (new0)];
2326 new = form_sum (new0, new1);
2328 /* As above, if we are not inside a MEM we do not want to
2329 turn a PLUS into something else. We might try to do so here
2330 for an addition of 0 if we aren't optimizing. */
2331 if (! mem_mode && GET_CODE (new) != PLUS)
2332 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2340 /* If this is the product of an eliminable register and a
2341 constant, apply the distribute law and move the constant out
2342 so that we have (plus (mult ..) ..). This is needed in order
2343 to keep load-address insns valid. This case is pathological.
2344 We ignore the possibility of overflow here. */
2345 if (GET_CODE (XEXP (x, 0)) == REG
2346 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2347 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2348 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2350 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2353 /* Refs inside notes don't count for this purpose. */
2354 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2355 || GET_CODE (insn) == INSN_LIST)))
2356 ep->ref_outside_mem = 1;
2359 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2360 ep->previous_offset * INTVAL (XEXP (x, 1)));
2363 /* ... fall through ... */
2367 /* See comments before PLUS about handling MINUS. */
2369 case DIV: case UDIV:
2370 case MOD: case UMOD:
2371 case AND: case IOR: case XOR:
2372 case ROTATERT: case ROTATE:
2373 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2375 case GE: case GT: case GEU: case GTU:
2376 case LE: case LT: case LEU: case LTU:
2378 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2380 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2382 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2383 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2388 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2391 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2392 if (new != XEXP (x, 0))
2394 /* If this is a REG_DEAD note, it is not valid anymore.
2395 Using the eliminated version could result in creating a
2396 REG_DEAD note for the stack or frame pointer. */
2397 if (GET_MODE (x) == REG_DEAD)
2399 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2402 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2406 /* ... fall through ... */
2409 /* Now do eliminations in the rest of the chain. If this was
2410 an EXPR_LIST, this might result in allocating more memory than is
2411 strictly needed, but it simplifies the code. */
2414 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2415 if (new != XEXP (x, 1))
2416 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2424 case STRICT_LOW_PART:
2426 case SIGN_EXTEND: case ZERO_EXTEND:
2427 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2428 case FLOAT: case FIX:
2429 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2433 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2434 if (new != XEXP (x, 0))
2435 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2439 /* Similar to above processing, but preserve SUBREG_WORD.
2440 Convert (subreg (mem)) to (mem) if not paradoxical.
2441 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2442 pseudo didn't get a hard reg, we must replace this with the
2443 eliminated version of the memory location because push_reloads
2444 may do the replacement in certain circumstances. */
2445 if (GET_CODE (SUBREG_REG (x)) == REG
2446 && (GET_MODE_SIZE (GET_MODE (x))
2447 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2448 && reg_equiv_memory_loc != 0
2449 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2451 new = SUBREG_REG (x);
2454 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2456 if (new != XEXP (x, 0))
2458 int x_size = GET_MODE_SIZE (GET_MODE (x));
2459 int new_size = GET_MODE_SIZE (GET_MODE (new));
2461 if (GET_CODE (new) == MEM
2462 && ((x_size < new_size
2463 #ifdef WORD_REGISTER_OPERATIONS
2464 /* On these machines, combine can create rtl of the form
2465 (set (subreg:m1 (reg:m2 R) 0) ...)
2466 where m1 < m2, and expects something interesting to
2467 happen to the entire word. Moreover, it will use the
2468 (reg:m2 R) later, expecting all bits to be preserved.
2469 So if the number of words is the same, preserve the
2470 subreg so that push_reloads can see it. */
2471 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2474 || (x_size == new_size))
2477 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2478 enum machine_mode mode = GET_MODE (x);
2480 if (BYTES_BIG_ENDIAN)
2481 offset += (MIN (UNITS_PER_WORD,
2482 GET_MODE_SIZE (GET_MODE (new)))
2483 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2485 PUT_MODE (new, mode);
2486 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2490 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2496 /* This is only for the benefit of the debugging backends, which call
2497 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2498 removed after CSE. */
2499 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2500 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2502 /* Our only special processing is to pass the mode of the MEM to our
2503 recursive call and copy the flags. While we are here, handle this
2504 case more efficiently. */
2505 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2506 if (new != XEXP (x, 0))
2508 new = gen_rtx_MEM (GET_MODE (x), new);
2509 MEM_COPY_ATTRIBUTES (new, x);
2525 /* Process each of our operands recursively. If any have changed, make a
2527 fmt = GET_RTX_FORMAT (code);
2528 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2532 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2533 if (new != XEXP (x, i) && ! copied)
2535 rtx new_x = rtx_alloc (code);
2536 bcopy ((char *) x, (char *) new_x,
2537 (sizeof (*new_x) - sizeof (new_x->fld)
2538 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2544 else if (*fmt == 'E')
2547 for (j = 0; j < XVECLEN (x, i); j++)
2549 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2550 if (new != XVECEXP (x, i, j) && ! copied_vec)
2552 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2556 rtx new_x = rtx_alloc (code);
2557 bcopy ((char *) x, (char *) new_x,
2558 (sizeof (*new_x) - sizeof (new_x->fld)
2559 + (sizeof (new_x->fld[0])
2560 * GET_RTX_LENGTH (code))));
2564 XVEC (x, i) = new_v;
2567 XVECEXP (x, i, j) = new;
2575 /* Scan rtx X for modifications of elimination target registers. Update
2576 the table of eliminables to reflect the changed state. MEM_MODE is
2577 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2580 elimination_effects (x, mem_mode)
2582 enum machine_mode mem_mode;
2585 enum rtx_code code = GET_CODE (x);
2586 struct elim_table *ep;
2612 /* First handle the case where we encounter a bare register that
2613 is eliminable. Replace it with a PLUS. */
2614 if (regno < FIRST_PSEUDO_REGISTER)
2616 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2618 if (ep->from_rtx == x && ep->can_eliminate)
2621 ep->ref_outside_mem = 1;
2626 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2627 && reg_equiv_constant[regno]
2628 && ! CONSTANT_P (reg_equiv_constant[regno]))
2629 elimination_effects (reg_equiv_constant[regno], mem_mode);
2636 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2637 if (ep->to_rtx == XEXP (x, 0))
2639 int size = GET_MODE_SIZE (mem_mode);
2641 /* If more bytes than MEM_MODE are pushed, account for them. */
2642 #ifdef PUSH_ROUNDING
2643 if (ep->to_rtx == stack_pointer_rtx)
2644 size = PUSH_ROUNDING (size);
2646 if (code == PRE_DEC || code == POST_DEC)
2652 /* Fall through to generic unary operation case. */
2653 case STRICT_LOW_PART:
2655 case SIGN_EXTEND: case ZERO_EXTEND:
2656 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2657 case FLOAT: case FIX:
2658 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2662 elimination_effects (XEXP (x, 0), mem_mode);
2666 if (GET_CODE (SUBREG_REG (x)) == REG
2667 && (GET_MODE_SIZE (GET_MODE (x))
2668 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2669 && reg_equiv_memory_loc != 0
2670 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2673 elimination_effects (SUBREG_REG (x), mem_mode);
2677 /* If using a register that is the source of an eliminate we still
2678 think can be performed, note it cannot be performed since we don't
2679 know how this register is used. */
2680 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2681 if (ep->from_rtx == XEXP (x, 0))
2682 ep->can_eliminate = 0;
2684 elimination_effects (XEXP (x, 0), mem_mode);
2688 /* If clobbering a register that is the replacement register for an
2689 elimination we still think can be performed, note that it cannot
2690 be performed. Otherwise, we need not be concerned about it. */
2691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2692 if (ep->to_rtx == XEXP (x, 0))
2693 ep->can_eliminate = 0;
2695 elimination_effects (XEXP (x, 0), mem_mode);
2699 /* Check for setting a register that we know about. */
2700 if (GET_CODE (SET_DEST (x)) == REG)
2702 /* See if this is setting the replacement register for an
2705 If DEST is the hard frame pointer, we do nothing because we
2706 assume that all assignments to the frame pointer are for
2707 non-local gotos and are being done at a time when they are valid
2708 and do not disturb anything else. Some machines want to
2709 eliminate a fake argument pointer (or even a fake frame pointer)
2710 with either the real frame or the stack pointer. Assignments to
2711 the hard frame pointer must not prevent this elimination. */
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2715 if (ep->to_rtx == SET_DEST (x)
2716 && SET_DEST (x) != hard_frame_pointer_rtx)
2718 /* If it is being incremented, adjust the offset. Otherwise,
2719 this elimination can't be done. */
2720 rtx src = SET_SRC (x);
2722 if (GET_CODE (src) == PLUS
2723 && XEXP (src, 0) == SET_DEST (x)
2724 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2725 ep->offset -= INTVAL (XEXP (src, 1));
2727 ep->can_eliminate = 0;
2731 elimination_effects (SET_DEST (x), 0);
2732 elimination_effects (SET_SRC (x), 0);
2736 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2739 /* Our only special processing is to pass the mode of the MEM to our
2741 elimination_effects (XEXP (x, 0), GET_MODE (x));
2748 fmt = GET_RTX_FORMAT (code);
2749 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2752 elimination_effects (XEXP (x, i), mem_mode);
2753 else if (*fmt == 'E')
2754 for (j = 0; j < XVECLEN (x, i); j++)
2755 elimination_effects (XVECEXP (x, i, j), mem_mode);
2759 /* Descend through rtx X and verify that no references to eliminable registers
2760 remain. If any do remain, mark the involved register as not
2764 check_eliminable_occurrences (x)
2774 code = GET_CODE (x);
2776 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2778 struct elim_table *ep;
2780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2781 if (ep->from_rtx == x && ep->can_eliminate)
2782 ep->can_eliminate = 0;
2786 fmt = GET_RTX_FORMAT (code);
2787 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2790 check_eliminable_occurrences (XEXP (x, i));
2791 else if (*fmt == 'E')
2794 for (j = 0; j < XVECLEN (x, i); j++)
2795 check_eliminable_occurrences (XVECEXP (x, i, j));
2800 /* Scan INSN and eliminate all eliminable registers in it.
2802 If REPLACE is nonzero, do the replacement destructively. Also
2803 delete the insn as dead it if it is setting an eliminable register.
2805 If REPLACE is zero, do all our allocations in reload_obstack.
2807 If no eliminations were done and this insn doesn't require any elimination
2808 processing (these are not identical conditions: it might be updating sp,
2809 but not referencing fp; this needs to be seen during reload_as_needed so
2810 that the offset between fp and sp can be taken into consideration), zero
2811 is returned. Otherwise, 1 is returned. */
2814 eliminate_regs_in_insn (insn, replace)
2818 int icode = recog_memoized (insn);
2819 rtx old_body = PATTERN (insn);
2820 int insn_is_asm = asm_noperands (old_body) >= 0;
2821 rtx old_set = single_set (insn);
2825 rtx substed_operand[MAX_RECOG_OPERANDS];
2826 rtx orig_operand[MAX_RECOG_OPERANDS];
2827 struct elim_table *ep;
2829 if (! insn_is_asm && icode < 0)
2831 if (GET_CODE (PATTERN (insn)) == USE
2832 || GET_CODE (PATTERN (insn)) == CLOBBER
2833 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2834 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2835 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2841 push_obstacks (&reload_obstack, &reload_obstack);
2843 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2844 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2846 /* Check for setting an eliminable register. */
2847 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2848 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2850 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2851 /* If this is setting the frame pointer register to the
2852 hardware frame pointer register and this is an elimination
2853 that will be done (tested above), this insn is really
2854 adjusting the frame pointer downward to compensate for
2855 the adjustment done before a nonlocal goto. */
2856 if (ep->from == FRAME_POINTER_REGNUM
2857 && ep->to == HARD_FRAME_POINTER_REGNUM)
2859 rtx src = SET_SRC (old_set);
2860 int offset = 0, ok = 0;
2861 rtx prev_insn, prev_set;
2863 if (src == ep->to_rtx)
2865 else if (GET_CODE (src) == PLUS
2866 && GET_CODE (XEXP (src, 0)) == CONST_INT
2867 && XEXP (src, 1) == ep->to_rtx)
2868 offset = INTVAL (XEXP (src, 0)), ok = 1;
2869 else if (GET_CODE (src) == PLUS
2870 && GET_CODE (XEXP (src, 1)) == CONST_INT
2871 && XEXP (src, 0) == ep->to_rtx)
2872 offset = INTVAL (XEXP (src, 1)), ok = 1;
2873 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2874 && (prev_set = single_set (prev_insn)) != 0
2875 && rtx_equal_p (SET_DEST (prev_set), src))
2877 src = SET_SRC (prev_set);
2878 if (src == ep->to_rtx)
2880 else if (GET_CODE (src) == PLUS
2881 && GET_CODE (XEXP (src, 0)) == CONST_INT
2882 && XEXP (src, 1) == ep->to_rtx)
2883 offset = INTVAL (XEXP (src, 0)), ok = 1;
2884 else if (GET_CODE (src) == PLUS
2885 && GET_CODE (XEXP (src, 1)) == CONST_INT
2886 && XEXP (src, 0) == ep->to_rtx)
2887 offset = INTVAL (XEXP (src, 1)), ok = 1;
2895 = plus_constant (ep->to_rtx, offset - ep->offset);
2897 /* First see if this insn remains valid when we
2898 make the change. If not, keep the INSN_CODE
2899 the same and let reload fit it up. */
2900 validate_change (insn, &SET_SRC (old_set), src, 1);
2901 validate_change (insn, &SET_DEST (old_set),
2903 if (! apply_change_group ())
2905 SET_SRC (old_set) = src;
2906 SET_DEST (old_set) = ep->to_rtx;
2916 /* In this case this insn isn't serving a useful purpose. We
2917 will delete it in reload_as_needed once we know that this
2918 elimination is, in fact, being done.
2920 If REPLACE isn't set, we can't delete this insn, but needn't
2921 process it since it won't be used unless something changes. */
2924 delete_dead_insn (insn);
2932 /* We allow one special case which happens to work on all machines we
2933 currently support: a single set with the source being a PLUS of an
2934 eliminable register and a constant. */
2936 && GET_CODE (SET_SRC (old_set)) == PLUS
2937 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2938 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2939 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2941 rtx reg = XEXP (SET_SRC (old_set), 0);
2942 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2944 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2945 if (ep->from_rtx == reg && ep->can_eliminate)
2947 offset += ep->offset;
2951 /* We assume here that we don't need a PARALLEL of
2952 any CLOBBERs for this assignment. There's not
2953 much we can do if we do need it. */
2954 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2957 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2958 if (INSN_CODE (insn) < 0)
2963 new_body = old_body;
2966 new_body = copy_insn (old_body);
2967 if (REG_NOTES (insn))
2968 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2970 PATTERN (insn) = new_body;
2971 old_set = single_set (insn);
2973 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2974 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2977 /* This can't have an effect on elimination offsets, so skip right
2983 /* Determine the effects of this insn on elimination offsets. */
2984 elimination_effects (old_body, 0);
2986 /* Eliminate all eliminable registers occurring in operands that
2987 can be handled by reload. */
2988 extract_insn (insn);
2990 for (i = 0; i < recog_data.n_operands; i++)
2992 orig_operand[i] = recog_data.operand[i];
2993 substed_operand[i] = recog_data.operand[i];
2995 /* For an asm statement, every operand is eliminable. */
2996 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2998 /* Check for setting a register that we know about. */
2999 if (recog_data.operand_type[i] != OP_IN
3000 && GET_CODE (orig_operand[i]) == REG)
3002 /* If we are assigning to a register that can be eliminated, it
3003 must be as part of a PARALLEL, since the code above handles
3004 single SETs. We must indicate that we can no longer
3005 eliminate this reg. */
3006 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3008 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3009 ep->can_eliminate = 0;
3012 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3013 replace ? insn : NULL_RTX);
3014 if (substed_operand[i] != orig_operand[i])
3015 val = any_changes = 1;
3016 /* Terminate the search in check_eliminable_occurrences at
3018 *recog_data.operand_loc[i] = 0;
3020 /* If an output operand changed from a REG to a MEM and INSN is an
3021 insn, write a CLOBBER insn. */
3022 if (recog_data.operand_type[i] != OP_IN
3023 && GET_CODE (orig_operand[i]) == REG
3024 && GET_CODE (substed_operand[i]) == MEM
3026 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3031 for (i = 0; i < recog_data.n_dups; i++)
3032 *recog_data.dup_loc[i]
3033 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3035 /* If any eliminable remain, they aren't eliminable anymore. */
3036 check_eliminable_occurrences (old_body);
3038 /* Substitute the operands; the new values are in the substed_operand
3040 for (i = 0; i < recog_data.n_operands; i++)
3041 *recog_data.operand_loc[i] = substed_operand[i];
3042 for (i = 0; i < recog_data.n_dups; i++)
3043 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3045 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3046 re-recognize the insn. We do this in case we had a simple addition
3047 but now can do this as a load-address. This saves an insn in this
3049 If re-recognition fails, the old insn code number will still be used,
3050 and some register operands may have changed into PLUS expressions.
3051 These will be handled by find_reloads by loading them into a register
3056 /* If we aren't replacing things permanently and we changed something,
3057 make another copy to ensure that all the RTL is new. Otherwise
3058 things can go wrong if find_reload swaps commutative operands
3059 and one is inside RTL that has been copied while the other is not. */
3060 new_body = old_body;
3063 new_body = copy_insn (old_body);
3064 if (REG_NOTES (insn))
3065 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3067 PATTERN (insn) = new_body;
3069 /* If we had a move insn but now we don't, rerecognize it. This will
3070 cause spurious re-recognition if the old move had a PARALLEL since
3071 the new one still will, but we can't call single_set without
3072 having put NEW_BODY into the insn and the re-recognition won't
3073 hurt in this rare case. */
3074 /* ??? Why this huge if statement - why don't we just rerecognize the
3078 && ((GET_CODE (SET_SRC (old_set)) == REG
3079 && (GET_CODE (new_body) != SET
3080 || GET_CODE (SET_SRC (new_body)) != REG))
3081 /* If this was a load from or store to memory, compare
3082 the MEM in recog_data.operand to the one in the insn.
3083 If they are not equal, then rerecognize the insn. */
3085 && ((GET_CODE (SET_SRC (old_set)) == MEM
3086 && SET_SRC (old_set) != recog_data.operand[1])
3087 || (GET_CODE (SET_DEST (old_set)) == MEM
3088 && SET_DEST (old_set) != recog_data.operand[0])))
3089 /* If this was an add insn before, rerecognize. */
3090 || GET_CODE (SET_SRC (old_set)) == PLUS))
3092 int new_icode = recog (PATTERN (insn), insn, 0);
3094 INSN_CODE (insn) = icode;
3098 /* Restore the old body. If there were any changes to it, we made a copy
3099 of it while the changes were still in place, so we'll correctly return
3100 a modified insn below. */
3103 /* Restore the old body. */
3104 for (i = 0; i < recog_data.n_operands; i++)
3105 *recog_data.operand_loc[i] = orig_operand[i];
3106 for (i = 0; i < recog_data.n_dups; i++)
3107 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3110 /* Update all elimination pairs to reflect the status after the current
3111 insn. The changes we make were determined by the earlier call to
3112 elimination_effects.
3114 We also detect a cases where register elimination cannot be done,
3115 namely, if a register would be both changed and referenced outside a MEM
3116 in the resulting insn since such an insn is often undefined and, even if
3117 not, we cannot know what meaning will be given to it. Note that it is
3118 valid to have a register used in an address in an insn that changes it
3119 (presumably with a pre- or post-increment or decrement).
3121 If anything changes, return nonzero. */
3123 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3125 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3126 ep->can_eliminate = 0;
3128 ep->ref_outside_mem = 0;
3130 if (ep->previous_offset != ep->offset)
3135 /* If we changed something, perform elimination in REG_NOTES. This is
3136 needed even when REPLACE is zero because a REG_DEAD note might refer
3137 to a register that we eliminate and could cause a different number
3138 of spill registers to be needed in the final reload pass than in
3140 if (val && REG_NOTES (insn) != 0)
3141 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3149 /* Loop through all elimination pairs.
3150 Recalculate the number not at initial offset.
3152 Compute the maximum offset (minimum offset if the stack does not
3153 grow downward) for each elimination pair. */
3156 update_eliminable_offsets ()
3158 struct elim_table *ep;
3160 num_not_at_initial_offset = 0;
3161 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3163 ep->previous_offset = ep->offset;
3164 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3165 num_not_at_initial_offset++;
3169 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3170 replacement we currently believe is valid, mark it as not eliminable if X
3171 modifies DEST in any way other than by adding a constant integer to it.
3173 If DEST is the frame pointer, we do nothing because we assume that
3174 all assignments to the hard frame pointer are nonlocal gotos and are being
3175 done at a time when they are valid and do not disturb anything else.
3176 Some machines want to eliminate a fake argument pointer with either the
3177 frame or stack pointer. Assignments to the hard frame pointer must not
3178 prevent this elimination.
3180 Called via note_stores from reload before starting its passes to scan
3181 the insns of the function. */
3184 mark_not_eliminable (dest, x, data)
3187 void *data ATTRIBUTE_UNUSED;
3189 register unsigned int i;
3191 /* A SUBREG of a hard register here is just changing its mode. We should
3192 not see a SUBREG of an eliminable hard register, but check just in
3194 if (GET_CODE (dest) == SUBREG)
3195 dest = SUBREG_REG (dest);
3197 if (dest == hard_frame_pointer_rtx)
3200 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3201 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3202 && (GET_CODE (x) != SET
3203 || GET_CODE (SET_SRC (x)) != PLUS
3204 || XEXP (SET_SRC (x), 0) != dest
3205 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3207 reg_eliminate[i].can_eliminate_previous
3208 = reg_eliminate[i].can_eliminate = 0;
3213 /* Verify that the initial elimination offsets did not change since the
3214 last call to set_initial_elim_offsets. This is used to catch cases
3215 where something illegal happened during reload_as_needed that could
3216 cause incorrect code to be generated if we did not check for it. */
3219 verify_initial_elim_offsets ()
3223 #ifdef ELIMINABLE_REGS
3224 struct elim_table *ep;
3226 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3228 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3229 if (t != ep->initial_offset)
3233 INITIAL_FRAME_POINTER_OFFSET (t);
3234 if (t != reg_eliminate[0].initial_offset)
3239 /* Reset all offsets on eliminable registers to their initial values. */
3242 set_initial_elim_offsets ()
3244 struct elim_table *ep = reg_eliminate;
3246 #ifdef ELIMINABLE_REGS
3247 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3249 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3250 ep->previous_offset = ep->offset = ep->initial_offset;
3253 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3254 ep->previous_offset = ep->offset = ep->initial_offset;
3257 num_not_at_initial_offset = 0;
3260 /* Initialize the known label offsets.
3261 Set a known offset for each forced label to be at the initial offset
3262 of each elimination. We do this because we assume that all
3263 computed jumps occur from a location where each elimination is
3264 at its initial offset.
3265 For all other labels, show that we don't know the offsets. */
3268 set_initial_label_offsets ()
3271 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3273 for (x = forced_labels; x; x = XEXP (x, 1))
3275 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3278 /* Set all elimination offsets to the known values for the code label given
3282 set_offsets_for_label (insn)
3286 int label_nr = CODE_LABEL_NUMBER (insn);
3287 struct elim_table *ep;
3289 num_not_at_initial_offset = 0;
3290 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3292 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3293 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3294 num_not_at_initial_offset++;
3298 /* See if anything that happened changes which eliminations are valid.
3299 For example, on the Sparc, whether or not the frame pointer can
3300 be eliminated can depend on what registers have been used. We need
3301 not check some conditions again (such as flag_omit_frame_pointer)
3302 since they can't have changed. */
3305 update_eliminables (pset)
3308 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3309 int previous_frame_pointer_needed = frame_pointer_needed;
3311 struct elim_table *ep;
3313 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3314 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3315 #ifdef ELIMINABLE_REGS
3316 || ! CAN_ELIMINATE (ep->from, ep->to)
3319 ep->can_eliminate = 0;
3321 /* Look for the case where we have discovered that we can't replace
3322 register A with register B and that means that we will now be
3323 trying to replace register A with register C. This means we can
3324 no longer replace register C with register B and we need to disable
3325 such an elimination, if it exists. This occurs often with A == ap,
3326 B == sp, and C == fp. */
3328 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3330 struct elim_table *op;
3331 register int new_to = -1;
3333 if (! ep->can_eliminate && ep->can_eliminate_previous)
3335 /* Find the current elimination for ep->from, if there is a
3337 for (op = reg_eliminate;
3338 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3339 if (op->from == ep->from && op->can_eliminate)
3345 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3347 for (op = reg_eliminate;
3348 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3349 if (op->from == new_to && op->to == ep->to)
3350 op->can_eliminate = 0;
3354 /* See if any registers that we thought we could eliminate the previous
3355 time are no longer eliminable. If so, something has changed and we
3356 must spill the register. Also, recompute the number of eliminable
3357 registers and see if the frame pointer is needed; it is if there is
3358 no elimination of the frame pointer that we can perform. */
3360 frame_pointer_needed = 1;
3361 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3363 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3364 && ep->to != HARD_FRAME_POINTER_REGNUM)
3365 frame_pointer_needed = 0;
3367 if (! ep->can_eliminate && ep->can_eliminate_previous)
3369 ep->can_eliminate_previous = 0;
3370 SET_HARD_REG_BIT (*pset, ep->from);
3375 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3376 /* If we didn't need a frame pointer last time, but we do now, spill
3377 the hard frame pointer. */
3378 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3379 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3383 /* Initialize the table of registers to eliminate. */
3388 struct elim_table *ep;
3389 #ifdef ELIMINABLE_REGS
3390 struct elim_table_1 *ep1;
3394 reg_eliminate = (struct elim_table *)
3395 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3397 /* Does this function require a frame pointer? */
3399 frame_pointer_needed = (! flag_omit_frame_pointer
3400 #ifdef EXIT_IGNORE_STACK
3401 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3402 and restore sp for alloca. So we can't eliminate
3403 the frame pointer in that case. At some point,
3404 we should improve this by emitting the
3405 sp-adjusting insns for this case. */
3406 || (current_function_calls_alloca
3407 && EXIT_IGNORE_STACK)
3409 || FRAME_POINTER_REQUIRED);
3413 #ifdef ELIMINABLE_REGS
3414 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3415 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3417 ep->from = ep1->from;
3419 ep->can_eliminate = ep->can_eliminate_previous
3420 = (CAN_ELIMINATE (ep->from, ep->to)
3421 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3424 reg_eliminate[0].from = reg_eliminate_1[0].from;
3425 reg_eliminate[0].to = reg_eliminate_1[0].to;
3426 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3427 = ! frame_pointer_needed;
3430 /* Count the number of eliminable registers and build the FROM and TO
3431 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3432 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3433 We depend on this. */
3434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3436 num_eliminable += ep->can_eliminate;
3437 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3438 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3442 /* Kick all pseudos out of hard register REGNO.
3443 If DUMPFILE is nonzero, log actions taken on that file.
3445 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3446 because we found we can't eliminate some register. In the case, no pseudos
3447 are allowed to be in the register, even if they are only in a block that
3448 doesn't require spill registers, unlike the case when we are spilling this
3449 hard reg to produce another spill register.
3451 Return nonzero if any pseudos needed to be kicked out. */
3454 spill_hard_reg (regno, dumpfile, cant_eliminate)
3456 FILE *dumpfile ATTRIBUTE_UNUSED;
3463 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3464 regs_ever_live[regno] = 1;
3467 /* Spill every pseudo reg that was allocated to this reg
3468 or to something that overlaps this reg. */
3470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3471 if (reg_renumber[i] >= 0
3472 && (unsigned int) reg_renumber[i] <= regno
3473 && ((unsigned int) reg_renumber[i]
3474 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3475 PSEUDO_REGNO_MODE (i))
3477 SET_REGNO_REG_SET (&spilled_pseudos, i);
3480 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3481 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3484 ior_hard_reg_set (set1, set2)
3485 HARD_REG_SET *set1, *set2;
3487 IOR_HARD_REG_SET (*set1, *set2);
3490 /* After find_reload_regs has been run for all insn that need reloads,
3491 and/or spill_hard_regs was called, this function is used to actually
3492 spill pseudo registers and try to reallocate them. It also sets up the
3493 spill_regs array for use by choose_reload_regs. */
3496 finish_spills (global, dumpfile)
3500 struct insn_chain *chain;
3501 int something_changed = 0;
3504 /* Build the spill_regs array for the function. */
3505 /* If there are some registers still to eliminate and one of the spill regs
3506 wasn't ever used before, additional stack space may have to be
3507 allocated to store this register. Thus, we may have changed the offset
3508 between the stack and frame pointers, so mark that something has changed.
3510 One might think that we need only set VAL to 1 if this is a call-used
3511 register. However, the set of registers that must be saved by the
3512 prologue is not identical to the call-used set. For example, the
3513 register used by the call insn for the return PC is a call-used register,
3514 but must be saved by the prologue. */
3517 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3518 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3520 spill_reg_order[i] = n_spills;
3521 spill_regs[n_spills++] = i;
3522 if (num_eliminable && ! regs_ever_live[i])
3523 something_changed = 1;
3524 regs_ever_live[i] = 1;
3527 spill_reg_order[i] = -1;
3529 EXECUTE_IF_SET_IN_REG_SET
3530 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3532 /* Record the current hard register the pseudo is allocated to in
3533 pseudo_previous_regs so we avoid reallocating it to the same
3534 hard reg in a later pass. */
3535 if (reg_renumber[i] < 0)
3538 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3539 /* Mark it as no longer having a hard register home. */
3540 reg_renumber[i] = -1;
3541 /* We will need to scan everything again. */
3542 something_changed = 1;
3545 /* Retry global register allocation if possible. */
3548 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3549 /* For every insn that needs reloads, set the registers used as spill
3550 regs in pseudo_forbidden_regs for every pseudo live across the
3552 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3554 EXECUTE_IF_SET_IN_REG_SET
3555 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3557 ior_hard_reg_set (pseudo_forbidden_regs + i,
3558 &chain->used_spill_regs);
3560 EXECUTE_IF_SET_IN_REG_SET
3561 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3563 ior_hard_reg_set (pseudo_forbidden_regs + i,
3564 &chain->used_spill_regs);
3568 /* Retry allocating the spilled pseudos. For each reg, merge the
3569 various reg sets that indicate which hard regs can't be used,
3570 and call retry_global_alloc.
3571 We change spill_pseudos here to only contain pseudos that did not
3572 get a new hard register. */
3573 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3574 if (reg_old_renumber[i] != reg_renumber[i])
3576 HARD_REG_SET forbidden;
3577 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3578 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3579 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3580 retry_global_alloc (i, forbidden);
3581 if (reg_renumber[i] >= 0)
3582 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3586 /* Fix up the register information in the insn chain.
3587 This involves deleting those of the spilled pseudos which did not get
3588 a new hard register home from the live_{before,after} sets. */
3589 for (chain = reload_insn_chain; chain; chain = chain->next)
3591 HARD_REG_SET used_by_pseudos;
3592 HARD_REG_SET used_by_pseudos2;
3594 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3595 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3597 /* Mark any unallocated hard regs as available for spills. That
3598 makes inheritance work somewhat better. */
3599 if (chain->need_reload)
3601 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3602 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3603 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3605 /* Save the old value for the sanity test below. */
3606 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3608 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3609 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3610 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3611 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3613 /* Make sure we only enlarge the set. */
3614 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3620 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3621 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3623 int regno = reg_renumber[i];
3624 if (reg_old_renumber[i] == regno)
3627 alter_reg (i, reg_old_renumber[i]);
3628 reg_old_renumber[i] = regno;
3632 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3634 fprintf (dumpfile, " Register %d now in %d.\n\n",
3635 i, reg_renumber[i]);
3639 return something_changed;
3642 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3643 Also mark any hard registers used to store user variables as
3644 forbidden from being used for spill registers. */
3647 scan_paradoxical_subregs (x)
3651 register const char *fmt;
3652 register enum rtx_code code = GET_CODE (x);
3658 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3659 && REG_USERVAR_P (x))
3660 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3676 if (GET_CODE (SUBREG_REG (x)) == REG
3677 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3678 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3679 = GET_MODE_SIZE (GET_MODE (x));
3686 fmt = GET_RTX_FORMAT (code);
3687 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3690 scan_paradoxical_subregs (XEXP (x, i));
3691 else if (fmt[i] == 'E')
3694 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3695 scan_paradoxical_subregs (XVECEXP (x, i, j));
3700 /* Reload pseudo-registers into hard regs around each insn as needed.
3701 Additional register load insns are output before the insn that needs it
3702 and perhaps store insns after insns that modify the reloaded pseudo reg.
3704 reg_last_reload_reg and reg_reloaded_contents keep track of
3705 which registers are already available in reload registers.
3706 We update these for the reloads that we perform,
3707 as the insns are scanned. */
3710 reload_as_needed (live_known)
3713 struct insn_chain *chain;
3714 #if defined (AUTO_INC_DEC)
3719 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3720 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3721 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3722 reg_has_output_reload = (char *) xmalloc (max_regno);
3723 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3725 set_initial_elim_offsets ();
3727 for (chain = reload_insn_chain; chain; chain = chain->next)
3730 rtx insn = chain->insn;
3731 rtx old_next = NEXT_INSN (insn);
3733 /* If we pass a label, copy the offsets from the label information
3734 into the current offsets of each elimination. */
3735 if (GET_CODE (insn) == CODE_LABEL)
3736 set_offsets_for_label (insn);
3738 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3740 rtx oldpat = PATTERN (insn);
3742 /* If this is a USE and CLOBBER of a MEM, ensure that any
3743 references to eliminable registers have been removed. */
3745 if ((GET_CODE (PATTERN (insn)) == USE
3746 || GET_CODE (PATTERN (insn)) == CLOBBER)
3747 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3748 XEXP (XEXP (PATTERN (insn), 0), 0)
3749 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3750 GET_MODE (XEXP (PATTERN (insn), 0)),
3753 /* If we need to do register elimination processing, do so.
3754 This might delete the insn, in which case we are done. */
3755 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3757 eliminate_regs_in_insn (insn, 1);
3758 if (GET_CODE (insn) == NOTE)
3760 update_eliminable_offsets ();
3765 /* If need_elim is nonzero but need_reload is zero, one might think
3766 that we could simply set n_reloads to 0. However, find_reloads
3767 could have done some manipulation of the insn (such as swapping
3768 commutative operands), and these manipulations are lost during
3769 the first pass for every insn that needs register elimination.
3770 So the actions of find_reloads must be redone here. */
3772 if (! chain->need_elim && ! chain->need_reload
3773 && ! chain->need_operand_change)
3775 /* First find the pseudo regs that must be reloaded for this insn.
3776 This info is returned in the tables reload_... (see reload.h).
3777 Also modify the body of INSN by substituting RELOAD
3778 rtx's for those pseudo regs. */
3781 bzero (reg_has_output_reload, max_regno);
3782 CLEAR_HARD_REG_SET (reg_is_output_reload);
3784 find_reloads (insn, 1, spill_indirect_levels, live_known,
3788 if (num_eliminable && chain->need_elim)
3789 update_eliminable_offsets ();
3793 rtx next = NEXT_INSN (insn);
3796 prev = PREV_INSN (insn);
3798 /* Now compute which reload regs to reload them into. Perhaps
3799 reusing reload regs from previous insns, or else output
3800 load insns to reload them. Maybe output store insns too.
3801 Record the choices of reload reg in reload_reg_rtx. */
3802 choose_reload_regs (chain);
3804 /* Merge any reloads that we didn't combine for fear of
3805 increasing the number of spill registers needed but now
3806 discover can be safely merged. */
3807 if (SMALL_REGISTER_CLASSES)
3808 merge_assigned_reloads (insn);
3810 /* Generate the insns to reload operands into or out of
3811 their reload regs. */
3812 emit_reload_insns (chain);
3814 /* Substitute the chosen reload regs from reload_reg_rtx
3815 into the insn's body (or perhaps into the bodies of other
3816 load and store insn that we just made for reloading
3817 and that we moved the structure into). */
3820 /* If this was an ASM, make sure that all the reload insns
3821 we have generated are valid. If not, give an error
3824 if (asm_noperands (PATTERN (insn)) >= 0)
3825 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3826 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3827 && (recog_memoized (p) < 0
3828 || (extract_insn (p), ! constrain_operands (1))))
3830 error_for_asm (insn,
3831 "`asm' operand requires impossible reload");
3833 NOTE_SOURCE_FILE (p) = 0;
3834 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3837 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3838 is no longer validly lying around to save a future reload.
3839 Note that this does not detect pseudos that were reloaded
3840 for this insn in order to be stored in
3841 (obeying register constraints). That is correct; such reload
3842 registers ARE still valid. */
3843 note_stores (oldpat, forget_old_reloads_1, NULL);
3845 /* There may have been CLOBBER insns placed after INSN. So scan
3846 between INSN and NEXT and use them to forget old reloads. */
3847 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3848 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3849 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3852 /* Likewise for regs altered by auto-increment in this insn.
3853 REG_INC notes have been changed by reloading:
3854 find_reloads_address_1 records substitutions for them,
3855 which have been performed by subst_reloads above. */
3856 for (i = n_reloads - 1; i >= 0; i--)
3858 rtx in_reg = rld[i].in_reg;
3861 enum rtx_code code = GET_CODE (in_reg);
3862 /* PRE_INC / PRE_DEC will have the reload register ending up
3863 with the same value as the stack slot, but that doesn't
3864 hold true for POST_INC / POST_DEC. Either we have to
3865 convert the memory access to a true POST_INC / POST_DEC,
3866 or we can't use the reload register for inheritance. */
3867 if ((code == POST_INC || code == POST_DEC)
3868 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3869 REGNO (rld[i].reg_rtx))
3870 /* Make sure it is the inc/dec pseudo, and not
3871 some other (e.g. output operand) pseudo. */
3872 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3873 == REGNO (XEXP (in_reg, 0))))
3876 rtx reload_reg = rld[i].reg_rtx;
3877 enum machine_mode mode = GET_MODE (reload_reg);
3881 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3883 /* We really want to ignore REG_INC notes here, so
3884 use PATTERN (p) as argument to reg_set_p . */
3885 if (reg_set_p (reload_reg, PATTERN (p)))
3887 n = count_occurrences (PATTERN (p), reload_reg);
3892 n = validate_replace_rtx (reload_reg,
3893 gen_rtx (code, mode,
3897 /* We must also verify that the constraints
3898 are met after the replacement. */
3901 n = constrain_operands (1);
3905 /* If the constraints were not met, then
3906 undo the replacement. */
3909 validate_replace_rtx (gen_rtx (code, mode,
3921 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3923 /* Mark this as having an output reload so that the
3924 REG_INC processing code below won't invalidate
3925 the reload for inheritance. */
3926 SET_HARD_REG_BIT (reg_is_output_reload,
3927 REGNO (reload_reg));
3928 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3931 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3934 else if ((code == PRE_INC || code == PRE_DEC)
3935 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3936 REGNO (rld[i].reg_rtx))
3937 /* Make sure it is the inc/dec pseudo, and not
3938 some other (e.g. output operand) pseudo. */
3939 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3940 == REGNO (XEXP (in_reg, 0))))
3942 SET_HARD_REG_BIT (reg_is_output_reload,
3943 REGNO (rld[i].reg_rtx));
3944 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3948 /* If a pseudo that got a hard register is auto-incremented,
3949 we must purge records of copying it into pseudos without
3951 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3952 if (REG_NOTE_KIND (x) == REG_INC)
3954 /* See if this pseudo reg was reloaded in this insn.
3955 If so, its last-reload info is still valid
3956 because it is based on this insn's reload. */
3957 for (i = 0; i < n_reloads; i++)
3958 if (rld[i].out == XEXP (x, 0))
3962 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3966 /* A reload reg's contents are unknown after a label. */
3967 if (GET_CODE (insn) == CODE_LABEL)
3968 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3970 /* Don't assume a reload reg is still good after a call insn
3971 if it is a call-used reg. */
3972 else if (GET_CODE (insn) == CALL_INSN)
3973 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3977 free (reg_last_reload_reg);
3978 free (reg_has_output_reload);
3981 /* Discard all record of any value reloaded from X,
3982 or reloaded in X from someplace else;
3983 unless X is an output reload reg of the current insn.
3985 X may be a hard reg (the reload reg)
3986 or it may be a pseudo reg that was reloaded from. */
3989 forget_old_reloads_1 (x, ignored, data)
3991 rtx ignored ATTRIBUTE_UNUSED;
3992 void *data ATTRIBUTE_UNUSED;
3998 /* note_stores does give us subregs of hard regs. */
3999 while (GET_CODE (x) == SUBREG)
4001 offset += SUBREG_WORD (x);
4005 if (GET_CODE (x) != REG)
4008 regno = REGNO (x) + offset;
4010 if (regno >= FIRST_PSEUDO_REGISTER)
4016 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4017 /* Storing into a spilled-reg invalidates its contents.
4018 This can happen if a block-local pseudo is allocated to that reg
4019 and it wasn't spilled because this block's total need is 0.
4020 Then some insn might have an optional reload and use this reg. */
4021 for (i = 0; i < nr; i++)
4022 /* But don't do this if the reg actually serves as an output
4023 reload reg in the current instruction. */
4025 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4026 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4029 /* Since value of X has changed,
4030 forget any value previously copied from it. */
4033 /* But don't forget a copy if this is the output reload
4034 that establishes the copy's validity. */
4035 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4036 reg_last_reload_reg[regno + nr] = 0;
4039 /* The following HARD_REG_SETs indicate when each hard register is
4040 used for a reload of various parts of the current insn. */
4042 /* If reg is unavailable for all reloads. */
4043 static HARD_REG_SET reload_reg_unavailable;
4044 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4045 static HARD_REG_SET reload_reg_used;
4046 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4047 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4048 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4049 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4050 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4051 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4052 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4053 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4054 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4055 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4056 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4057 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4058 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4059 static HARD_REG_SET reload_reg_used_in_op_addr;
4060 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4061 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4062 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4063 static HARD_REG_SET reload_reg_used_in_insn;
4064 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4065 static HARD_REG_SET reload_reg_used_in_other_addr;
4067 /* If reg is in use as a reload reg for any sort of reload. */
4068 static HARD_REG_SET reload_reg_used_at_all;
4070 /* If reg is use as an inherited reload. We just mark the first register
4072 static HARD_REG_SET reload_reg_used_for_inherit;
4074 /* Records which hard regs are used in any way, either as explicit use or
4075 by being allocated to a pseudo during any point of the current insn. */
4076 static HARD_REG_SET reg_used_in_insn;
4078 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4079 TYPE. MODE is used to indicate how many consecutive regs are
4083 mark_reload_reg_in_use (regno, opnum, type, mode)
4086 enum reload_type type;
4087 enum machine_mode mode;
4089 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4092 for (i = regno; i < nregs + regno; i++)
4097 SET_HARD_REG_BIT (reload_reg_used, i);
4100 case RELOAD_FOR_INPUT_ADDRESS:
4101 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4104 case RELOAD_FOR_INPADDR_ADDRESS:
4105 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4108 case RELOAD_FOR_OUTPUT_ADDRESS:
4109 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4112 case RELOAD_FOR_OUTADDR_ADDRESS:
4113 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4116 case RELOAD_FOR_OPERAND_ADDRESS:
4117 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4120 case RELOAD_FOR_OPADDR_ADDR:
4121 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4124 case RELOAD_FOR_OTHER_ADDRESS:
4125 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4128 case RELOAD_FOR_INPUT:
4129 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4132 case RELOAD_FOR_OUTPUT:
4133 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4136 case RELOAD_FOR_INSN:
4137 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4141 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4145 /* Similarly, but show REGNO is no longer in use for a reload. */
4148 clear_reload_reg_in_use (regno, opnum, type, mode)
4151 enum reload_type type;
4152 enum machine_mode mode;
4154 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4155 unsigned int start_regno, end_regno, r;
4157 /* A complication is that for some reload types, inheritance might
4158 allow multiple reloads of the same types to share a reload register.
4159 We set check_opnum if we have to check only reloads with the same
4160 operand number, and check_any if we have to check all reloads. */
4161 int check_opnum = 0;
4163 HARD_REG_SET *used_in_set;
4168 used_in_set = &reload_reg_used;
4171 case RELOAD_FOR_INPUT_ADDRESS:
4172 used_in_set = &reload_reg_used_in_input_addr[opnum];
4175 case RELOAD_FOR_INPADDR_ADDRESS:
4177 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4180 case RELOAD_FOR_OUTPUT_ADDRESS:
4181 used_in_set = &reload_reg_used_in_output_addr[opnum];
4184 case RELOAD_FOR_OUTADDR_ADDRESS:
4186 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4189 case RELOAD_FOR_OPERAND_ADDRESS:
4190 used_in_set = &reload_reg_used_in_op_addr;
4193 case RELOAD_FOR_OPADDR_ADDR:
4195 used_in_set = &reload_reg_used_in_op_addr_reload;
4198 case RELOAD_FOR_OTHER_ADDRESS:
4199 used_in_set = &reload_reg_used_in_other_addr;
4203 case RELOAD_FOR_INPUT:
4204 used_in_set = &reload_reg_used_in_input[opnum];
4207 case RELOAD_FOR_OUTPUT:
4208 used_in_set = &reload_reg_used_in_output[opnum];
4211 case RELOAD_FOR_INSN:
4212 used_in_set = &reload_reg_used_in_insn;
4217 /* We resolve conflicts with remaining reloads of the same type by
4218 excluding the intervals of of reload registers by them from the
4219 interval of freed reload registers. Since we only keep track of
4220 one set of interval bounds, we might have to exclude somewhat
4221 more then what would be necessary if we used a HARD_REG_SET here.
4222 But this should only happen very infrequently, so there should
4223 be no reason to worry about it. */
4225 start_regno = regno;
4226 end_regno = regno + nregs;
4227 if (check_opnum || check_any)
4229 for (i = n_reloads - 1; i >= 0; i--)
4231 if (rld[i].when_needed == type
4232 && (check_any || rld[i].opnum == opnum)
4235 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4236 unsigned int conflict_end
4238 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4240 /* If there is an overlap with the first to-be-freed register,
4241 adjust the interval start. */
4242 if (conflict_start <= start_regno && conflict_end > start_regno)
4243 start_regno = conflict_end;
4244 /* Otherwise, if there is a conflict with one of the other
4245 to-be-freed registers, adjust the interval end. */
4246 if (conflict_start > start_regno && conflict_start < end_regno)
4247 end_regno = conflict_start;
4252 for (r = start_regno; r < end_regno; r++)
4253 CLEAR_HARD_REG_BIT (*used_in_set, r);
4256 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4257 specified by OPNUM and TYPE. */
4260 reload_reg_free_p (regno, opnum, type)
4263 enum reload_type type;
4267 /* In use for a RELOAD_OTHER means it's not available for anything. */
4268 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4269 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4275 /* In use for anything means we can't use it for RELOAD_OTHER. */
4276 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4277 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4278 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4281 for (i = 0; i < reload_n_operands; i++)
4282 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4283 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4284 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4285 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4286 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4287 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4292 case RELOAD_FOR_INPUT:
4293 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4294 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4297 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4300 /* If it is used for some other input, can't use it. */
4301 for (i = 0; i < reload_n_operands; i++)
4302 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4305 /* If it is used in a later operand's address, can't use it. */
4306 for (i = opnum + 1; i < reload_n_operands; i++)
4307 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4308 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4313 case RELOAD_FOR_INPUT_ADDRESS:
4314 /* Can't use a register if it is used for an input address for this
4315 operand or used as an input in an earlier one. */
4316 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4317 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4320 for (i = 0; i < opnum; i++)
4321 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4326 case RELOAD_FOR_INPADDR_ADDRESS:
4327 /* Can't use a register if it is used for an input address
4328 for this operand or used as an input in an earlier
4330 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4333 for (i = 0; i < opnum; i++)
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4339 case RELOAD_FOR_OUTPUT_ADDRESS:
4340 /* Can't use a register if it is used for an output address for this
4341 operand or used as an output in this or a later operand. */
4342 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4345 for (i = opnum; i < reload_n_operands; i++)
4346 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4351 case RELOAD_FOR_OUTADDR_ADDRESS:
4352 /* Can't use a register if it is used for an output address
4353 for this operand or used as an output in this or a
4355 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4358 for (i = opnum; i < reload_n_operands; i++)
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4364 case RELOAD_FOR_OPERAND_ADDRESS:
4365 for (i = 0; i < reload_n_operands; i++)
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4369 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4370 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4372 case RELOAD_FOR_OPADDR_ADDR:
4373 for (i = 0; i < reload_n_operands; i++)
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4377 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4379 case RELOAD_FOR_OUTPUT:
4380 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4381 outputs, or an operand address for this or an earlier output. */
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4385 for (i = 0; i < reload_n_operands; i++)
4386 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4389 for (i = 0; i <= opnum; i++)
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4391 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4396 case RELOAD_FOR_INSN:
4397 for (i = 0; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4402 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4403 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4405 case RELOAD_FOR_OTHER_ADDRESS:
4406 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4411 /* Return 1 if the value in reload reg REGNO, as used by a reload
4412 needed for the part of the insn specified by OPNUM and TYPE,
4413 is still available in REGNO at the end of the insn.
4415 We can assume that the reload reg was already tested for availability
4416 at the time it is needed, and we should not check this again,
4417 in case the reg has already been marked in use. */
4420 reload_reg_reaches_end_p (regno, opnum, type)
4423 enum reload_type type;
4430 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4431 its value must reach the end. */
4434 /* If this use is for part of the insn,
4435 its value reaches if no subsequent part uses the same register.
4436 Just like the above function, don't try to do this with lots
4439 case RELOAD_FOR_OTHER_ADDRESS:
4440 /* Here we check for everything else, since these don't conflict
4441 with anything else and everything comes later. */
4443 for (i = 0; i < reload_n_operands; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4446 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4447 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4448 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4449 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4452 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4453 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4454 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4456 case RELOAD_FOR_INPUT_ADDRESS:
4457 case RELOAD_FOR_INPADDR_ADDRESS:
4458 /* Similar, except that we check only for this and subsequent inputs
4459 and the address of only subsequent inputs and we do not need
4460 to check for RELOAD_OTHER objects since they are known not to
4463 for (i = opnum; i < reload_n_operands; i++)
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4467 for (i = opnum + 1; i < reload_n_operands; i++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4469 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4472 for (i = 0; i < reload_n_operands; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4474 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4475 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4481 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4482 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4484 case RELOAD_FOR_INPUT:
4485 /* Similar to input address, except we start at the next operand for
4486 both input and input address and we do not check for
4487 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4490 for (i = opnum + 1; i < reload_n_operands; i++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4492 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4496 /* ... fall through ... */
4498 case RELOAD_FOR_OPERAND_ADDRESS:
4499 /* Check outputs and their addresses. */
4501 for (i = 0; i < reload_n_operands; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4509 case RELOAD_FOR_OPADDR_ADDR:
4510 for (i = 0; i < reload_n_operands; i++)
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4512 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4516 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4517 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4519 case RELOAD_FOR_INSN:
4520 /* These conflict with other outputs with RELOAD_OTHER. So
4521 we need only check for output addresses. */
4525 /* ... fall through ... */
4527 case RELOAD_FOR_OUTPUT:
4528 case RELOAD_FOR_OUTPUT_ADDRESS:
4529 case RELOAD_FOR_OUTADDR_ADDRESS:
4530 /* We already know these can't conflict with a later output. So the
4531 only thing to check are later output addresses. */
4532 for (i = opnum + 1; i < reload_n_operands; i++)
4533 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4543 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4546 This function uses the same algorithm as reload_reg_free_p above. */
4549 reloads_conflict (r1, r2)
4552 enum reload_type r1_type = rld[r1].when_needed;
4553 enum reload_type r2_type = rld[r2].when_needed;
4554 int r1_opnum = rld[r1].opnum;
4555 int r2_opnum = rld[r2].opnum;
4557 /* RELOAD_OTHER conflicts with everything. */
4558 if (r2_type == RELOAD_OTHER)
4561 /* Otherwise, check conflicts differently for each type. */
4565 case RELOAD_FOR_INPUT:
4566 return (r2_type == RELOAD_FOR_INSN
4567 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4568 || r2_type == RELOAD_FOR_OPADDR_ADDR
4569 || r2_type == RELOAD_FOR_INPUT
4570 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4571 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4572 && r2_opnum > r1_opnum));
4574 case RELOAD_FOR_INPUT_ADDRESS:
4575 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4576 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4578 case RELOAD_FOR_INPADDR_ADDRESS:
4579 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4580 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4582 case RELOAD_FOR_OUTPUT_ADDRESS:
4583 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4584 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4586 case RELOAD_FOR_OUTADDR_ADDRESS:
4587 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4588 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4590 case RELOAD_FOR_OPERAND_ADDRESS:
4591 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4592 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4594 case RELOAD_FOR_OPADDR_ADDR:
4595 return (r2_type == RELOAD_FOR_INPUT
4596 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4598 case RELOAD_FOR_OUTPUT:
4599 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4600 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4601 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4602 && r2_opnum <= r1_opnum));
4604 case RELOAD_FOR_INSN:
4605 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4606 || r2_type == RELOAD_FOR_INSN
4607 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4609 case RELOAD_FOR_OTHER_ADDRESS:
4610 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4620 /* Indexed by reload number, 1 if incoming value
4621 inherited from previous insns. */
4622 char reload_inherited[MAX_RELOADS];
4624 /* For an inherited reload, this is the insn the reload was inherited from,
4625 if we know it. Otherwise, this is 0. */
4626 rtx reload_inheritance_insn[MAX_RELOADS];
4628 /* If non-zero, this is a place to get the value of the reload,
4629 rather than using reload_in. */
4630 rtx reload_override_in[MAX_RELOADS];
4632 /* For each reload, the hard register number of the register used,
4633 or -1 if we did not need a register for this reload. */
4634 int reload_spill_index[MAX_RELOADS];
4636 /* Return 1 if the value in reload reg REGNO, as used by a reload
4637 needed for the part of the insn specified by OPNUM and TYPE,
4638 may be used to load VALUE into it.
4640 Other read-only reloads with the same value do not conflict
4641 unless OUT is non-zero and these other reloads have to live while
4642 output reloads live.
4643 If OUT is CONST0_RTX, this is a special case: it means that the
4644 test should not be for using register REGNO as reload register, but
4645 for copying from register REGNO into the reload register.
4647 RELOADNUM is the number of the reload we want to load this value for;
4648 a reload does not conflict with itself.
4650 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4651 reloads that load an address for the very reload we are considering.
4653 The caller has to make sure that there is no conflict with the return
4656 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4657 ignore_address_reloads)
4660 enum reload_type type;
4663 int ignore_address_reloads;
4666 /* Set if we see an input reload that must not share its reload register
4667 with any new earlyclobber, but might otherwise share the reload
4668 register with an output or input-output reload. */
4669 int check_earlyclobber = 0;
4673 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4676 if (out == const0_rtx)
4682 /* We use some pseudo 'time' value to check if the lifetimes of the
4683 new register use would overlap with the one of a previous reload
4684 that is not read-only or uses a different value.
4685 The 'time' used doesn't have to be linear in any shape or form, just
4687 Some reload types use different 'buckets' for each operand.
4688 So there are MAX_RECOG_OPERANDS different time values for each
4690 We compute TIME1 as the time when the register for the prospective
4691 new reload ceases to be live, and TIME2 for each existing
4692 reload as the time when that the reload register of that reload
4694 Where there is little to be gained by exact lifetime calculations,
4695 we just make conservative assumptions, i.e. a longer lifetime;
4696 this is done in the 'default:' cases. */
4699 case RELOAD_FOR_OTHER_ADDRESS:
4700 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4701 time1 = copy ? 0 : 1;
4704 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4706 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4707 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4708 respectively, to the time values for these, we get distinct time
4709 values. To get distinct time values for each operand, we have to
4710 multiply opnum by at least three. We round that up to four because
4711 multiply by four is often cheaper. */
4712 case RELOAD_FOR_INPADDR_ADDRESS:
4713 time1 = opnum * 4 + 2;
4715 case RELOAD_FOR_INPUT_ADDRESS:
4716 time1 = opnum * 4 + 3;
4718 case RELOAD_FOR_INPUT:
4719 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4720 executes (inclusive). */
4721 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4723 case RELOAD_FOR_OPADDR_ADDR:
4725 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4726 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4728 case RELOAD_FOR_OPERAND_ADDRESS:
4729 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4731 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4733 case RELOAD_FOR_OUTADDR_ADDRESS:
4734 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4736 case RELOAD_FOR_OUTPUT_ADDRESS:
4737 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4740 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4743 for (i = 0; i < n_reloads; i++)
4745 rtx reg = rld[i].reg_rtx;
4746 if (reg && GET_CODE (reg) == REG
4747 && ((unsigned) regno - true_regnum (reg)
4748 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4751 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4752 || rld[i].out || out)
4755 switch (rld[i].when_needed)
4757 case RELOAD_FOR_OTHER_ADDRESS:
4760 case RELOAD_FOR_INPADDR_ADDRESS:
4761 /* find_reloads makes sure that a
4762 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4763 by at most one - the first -
4764 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4765 address reload is inherited, the address address reload
4766 goes away, so we can ignore this conflict. */
4767 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4768 && ignore_address_reloads
4769 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4770 Then the address address is still needed to store
4771 back the new address. */
4772 && ! rld[reloadnum].out)
4774 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4775 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4777 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4778 && ignore_address_reloads
4779 /* Unless we are reloading an auto_inc expression. */
4780 && ! rld[reloadnum].out)
4782 time2 = rld[i].opnum * 4 + 2;
4784 case RELOAD_FOR_INPUT_ADDRESS:
4785 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4786 && ignore_address_reloads
4787 && ! rld[reloadnum].out)
4789 time2 = rld[i].opnum * 4 + 3;
4791 case RELOAD_FOR_INPUT:
4792 time2 = rld[i].opnum * 4 + 4;
4793 check_earlyclobber = 1;
4795 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4796 == MAX_RECOG_OPERAND * 4 */
4797 case RELOAD_FOR_OPADDR_ADDR:
4798 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4799 && ignore_address_reloads
4800 && ! rld[reloadnum].out)
4802 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4804 case RELOAD_FOR_OPERAND_ADDRESS:
4805 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4806 check_earlyclobber = 1;
4808 case RELOAD_FOR_INSN:
4809 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4811 case RELOAD_FOR_OUTPUT:
4812 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4813 instruction is executed. */
4814 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4816 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4817 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4819 case RELOAD_FOR_OUTADDR_ADDRESS:
4820 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4821 && ignore_address_reloads
4822 && ! rld[reloadnum].out)
4824 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4826 case RELOAD_FOR_OUTPUT_ADDRESS:
4827 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4830 /* If there is no conflict in the input part, handle this
4831 like an output reload. */
4832 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4834 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4835 /* Earlyclobbered outputs must conflict with inputs. */
4836 if (earlyclobber_operand_p (rld[i].out))
4837 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4842 /* RELOAD_OTHER might be live beyond instruction execution,
4843 but this is not obvious when we set time2 = 1. So check
4844 here if there might be a problem with the new reload
4845 clobbering the register used by the RELOAD_OTHER. */
4853 && (! rld[i].in || rld[i].out
4854 || ! rtx_equal_p (rld[i].in, value)))
4855 || (out && rld[reloadnum].out_reg
4856 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4862 /* Earlyclobbered outputs must conflict with inputs. */
4863 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4869 /* Give an error message saying we failed to find a reload for INSN,
4870 and clear out reload R. */
4872 failed_reload (insn, r)
4876 if (asm_noperands (PATTERN (insn)) < 0)
4877 /* It's the compiler's fault. */
4878 fatal_insn ("Could not find a spill register", insn);
4880 /* It's the user's fault; the operand's mode and constraint
4881 don't match. Disable this reload so we don't crash in final. */
4882 error_for_asm (insn,
4883 "`asm' operand constraint incompatible with operand size");
4887 rld[r].optional = 1;
4888 rld[r].secondary_p = 1;
4891 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4892 for reload R. If it's valid, get an rtx for it. Return nonzero if
4895 set_reload_reg (i, r)
4899 rtx reg = spill_reg_rtx[i];
4901 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4902 spill_reg_rtx[i] = reg
4903 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4905 regno = true_regnum (reg);
4907 /* Detect when the reload reg can't hold the reload mode.
4908 This used to be one `if', but Sequent compiler can't handle that. */
4909 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4911 enum machine_mode test_mode = VOIDmode;
4913 test_mode = GET_MODE (rld[r].in);
4914 /* If rld[r].in has VOIDmode, it means we will load it
4915 in whatever mode the reload reg has: to wit, rld[r].mode.
4916 We have already tested that for validity. */
4917 /* Aside from that, we need to test that the expressions
4918 to reload from or into have modes which are valid for this
4919 reload register. Otherwise the reload insns would be invalid. */
4920 if (! (rld[r].in != 0 && test_mode != VOIDmode
4921 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4922 if (! (rld[r].out != 0
4923 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4925 /* The reg is OK. */
4928 /* Mark as in use for this insn the reload regs we use
4930 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4931 rld[r].when_needed, rld[r].mode);
4933 rld[r].reg_rtx = reg;
4934 reload_spill_index[r] = spill_regs[i];
4941 /* Find a spill register to use as a reload register for reload R.
4942 LAST_RELOAD is non-zero if this is the last reload for the insn being
4945 Set rld[R].reg_rtx to the register allocated.
4947 We return 1 if successful, or 0 if we couldn't find a spill reg and
4948 we didn't change anything. */
4951 allocate_reload_reg (chain, r, last_reload)
4952 struct insn_chain *chain ATTRIBUTE_UNUSED;
4958 /* If we put this reload ahead, thinking it is a group,
4959 then insist on finding a group. Otherwise we can grab a
4960 reg that some other reload needs.
4961 (That can happen when we have a 68000 DATA_OR_FP_REG
4962 which is a group of data regs or one fp reg.)
4963 We need not be so restrictive if there are no more reloads
4966 ??? Really it would be nicer to have smarter handling
4967 for that kind of reg class, where a problem like this is normal.
4968 Perhaps those classes should be avoided for reloading
4969 by use of more alternatives. */
4971 int force_group = rld[r].nregs > 1 && ! last_reload;
4973 /* If we want a single register and haven't yet found one,
4974 take any reg in the right class and not in use.
4975 If we want a consecutive group, here is where we look for it.
4977 We use two passes so we can first look for reload regs to
4978 reuse, which are already in use for other reloads in this insn,
4979 and only then use additional registers.
4980 I think that maximizing reuse is needed to make sure we don't
4981 run out of reload regs. Suppose we have three reloads, and
4982 reloads A and B can share regs. These need two regs.
4983 Suppose A and B are given different regs.
4984 That leaves none for C. */
4985 for (pass = 0; pass < 2; pass++)
4987 /* I is the index in spill_regs.
4988 We advance it round-robin between insns to use all spill regs
4989 equally, so that inherited reloads have a chance
4990 of leapfrogging each other. */
4994 for (count = 0; count < n_spills; count++)
4996 int class = (int) rld[r].class;
5002 regnum = spill_regs[i];
5004 if ((reload_reg_free_p (regnum, rld[r].opnum,
5007 /* We check reload_reg_used to make sure we
5008 don't clobber the return register. */
5009 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5010 && reload_reg_free_for_value_p (regnum,
5015 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5016 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5017 /* Look first for regs to share, then for unshared. But
5018 don't share regs used for inherited reloads; they are
5019 the ones we want to preserve. */
5021 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5023 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5026 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5027 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5028 (on 68000) got us two FP regs. If NR is 1,
5029 we would reject both of them. */
5032 /* If we need only one reg, we have already won. */
5035 /* But reject a single reg if we demand a group. */
5040 /* Otherwise check that as many consecutive regs as we need
5041 are available here. */
5044 int regno = regnum + nr - 1;
5045 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5046 && spill_reg_order[regno] >= 0
5047 && reload_reg_free_p (regno, rld[r].opnum,
5048 rld[r].when_needed)))
5057 /* If we found something on pass 1, omit pass 2. */
5058 if (count < n_spills)
5062 /* We should have found a spill register by now. */
5063 if (count >= n_spills)
5066 /* I is the index in SPILL_REG_RTX of the reload register we are to
5067 allocate. Get an rtx for it and find its register number. */
5069 return set_reload_reg (i, r);
5072 /* Initialize all the tables needed to allocate reload registers.
5073 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5074 is the array we use to restore the reg_rtx field for every reload. */
5077 choose_reload_regs_init (chain, save_reload_reg_rtx)
5078 struct insn_chain *chain;
5079 rtx *save_reload_reg_rtx;
5083 for (i = 0; i < n_reloads; i++)
5084 rld[i].reg_rtx = save_reload_reg_rtx[i];
5086 bzero (reload_inherited, MAX_RELOADS);
5087 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5088 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5090 CLEAR_HARD_REG_SET (reload_reg_used);
5091 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5092 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5093 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5094 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5095 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5097 CLEAR_HARD_REG_SET (reg_used_in_insn);
5100 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5101 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5102 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5103 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5104 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5105 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5108 for (i = 0; i < reload_n_operands; i++)
5110 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5111 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5112 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5113 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5114 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5115 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5118 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5120 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5122 for (i = 0; i < n_reloads; i++)
5123 /* If we have already decided to use a certain register,
5124 don't use it in another way. */
5126 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5127 rld[i].when_needed, rld[i].mode);
5130 /* Assign hard reg targets for the pseudo-registers we must reload
5131 into hard regs for this insn.
5132 Also output the instructions to copy them in and out of the hard regs.
5134 For machines with register classes, we are responsible for
5135 finding a reload reg in the proper class. */
5138 choose_reload_regs (chain)
5139 struct insn_chain *chain;
5141 rtx insn = chain->insn;
5143 unsigned int max_group_size = 1;
5144 enum reg_class group_class = NO_REGS;
5145 int pass, win, inheritance;
5147 rtx save_reload_reg_rtx[MAX_RELOADS];
5149 /* In order to be certain of getting the registers we need,
5150 we must sort the reloads into order of increasing register class.
5151 Then our grabbing of reload registers will parallel the process
5152 that provided the reload registers.
5154 Also note whether any of the reloads wants a consecutive group of regs.
5155 If so, record the maximum size of the group desired and what
5156 register class contains all the groups needed by this insn. */
5158 for (j = 0; j < n_reloads; j++)
5160 reload_order[j] = j;
5161 reload_spill_index[j] = -1;
5163 if (rld[j].nregs > 1)
5165 max_group_size = MAX (rld[j].nregs, max_group_size);
5167 = reg_class_superunion[(int)rld[j].class][(int)group_class];
5170 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5174 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5176 /* If -O, try first with inheritance, then turning it off.
5177 If not -O, don't do inheritance.
5178 Using inheritance when not optimizing leads to paradoxes
5179 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5180 because one side of the comparison might be inherited. */
5182 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5184 choose_reload_regs_init (chain, save_reload_reg_rtx);
5186 /* Process the reloads in order of preference just found.
5187 Beyond this point, subregs can be found in reload_reg_rtx.
5189 This used to look for an existing reloaded home for all of the
5190 reloads, and only then perform any new reloads. But that could lose
5191 if the reloads were done out of reg-class order because a later
5192 reload with a looser constraint might have an old home in a register
5193 needed by an earlier reload with a tighter constraint.
5195 To solve this, we make two passes over the reloads, in the order
5196 described above. In the first pass we try to inherit a reload
5197 from a previous insn. If there is a later reload that needs a
5198 class that is a proper subset of the class being processed, we must
5199 also allocate a spill register during the first pass.
5201 Then make a second pass over the reloads to allocate any reloads
5202 that haven't been given registers yet. */
5204 for (j = 0; j < n_reloads; j++)
5206 register int r = reload_order[j];
5207 rtx search_equiv = NULL_RTX;
5209 /* Ignore reloads that got marked inoperative. */
5210 if (rld[r].out == 0 && rld[r].in == 0
5211 && ! rld[r].secondary_p)
5214 /* If find_reloads chose to use reload_in or reload_out as a reload
5215 register, we don't need to chose one. Otherwise, try even if it
5216 found one since we might save an insn if we find the value lying
5218 Try also when reload_in is a pseudo without a hard reg. */
5219 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5220 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5221 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5222 && GET_CODE (rld[r].in) != MEM
5223 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5226 #if 0 /* No longer needed for correct operation.
5227 It might give better code, or might not; worth an experiment? */
5228 /* If this is an optional reload, we can't inherit from earlier insns
5229 until we are sure that any non-optional reloads have been allocated.
5230 The following code takes advantage of the fact that optional reloads
5231 are at the end of reload_order. */
5232 if (rld[r].optional != 0)
5233 for (i = 0; i < j; i++)
5234 if ((rld[reload_order[i]].out != 0
5235 || rld[reload_order[i]].in != 0
5236 || rld[reload_order[i]].secondary_p)
5237 && ! rld[reload_order[i]].optional
5238 && rld[reload_order[i]].reg_rtx == 0)
5239 allocate_reload_reg (chain, reload_order[i], 0);
5242 /* First see if this pseudo is already available as reloaded
5243 for a previous insn. We cannot try to inherit for reloads
5244 that are smaller than the maximum number of registers needed
5245 for groups unless the register we would allocate cannot be used
5248 We could check here to see if this is a secondary reload for
5249 an object that is already in a register of the desired class.
5250 This would avoid the need for the secondary reload register.
5251 But this is complex because we can't easily determine what
5252 objects might want to be loaded via this reload. So let a
5253 register be allocated here. In `emit_reload_insns' we suppress
5254 one of the loads in the case described above. */
5259 register int regno = -1;
5260 enum machine_mode mode = VOIDmode;
5264 else if (GET_CODE (rld[r].in) == REG)
5266 regno = REGNO (rld[r].in);
5267 mode = GET_MODE (rld[r].in);
5269 else if (GET_CODE (rld[r].in_reg) == REG)
5271 regno = REGNO (rld[r].in_reg);
5272 mode = GET_MODE (rld[r].in_reg);
5274 else if (GET_CODE (rld[r].in_reg) == SUBREG
5275 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5277 word = SUBREG_WORD (rld[r].in_reg);
5278 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5279 if (regno < FIRST_PSEUDO_REGISTER)
5281 mode = GET_MODE (rld[r].in_reg);
5284 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5285 || GET_CODE (rld[r].in_reg) == PRE_DEC
5286 || GET_CODE (rld[r].in_reg) == POST_INC
5287 || GET_CODE (rld[r].in_reg) == POST_DEC)
5288 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5290 regno = REGNO (XEXP (rld[r].in_reg, 0));
5291 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5292 rld[r].out = rld[r].in;
5296 /* This won't work, since REGNO can be a pseudo reg number.
5297 Also, it takes much more hair to keep track of all the things
5298 that can invalidate an inherited reload of part of a pseudoreg. */
5299 else if (GET_CODE (rld[r].in) == SUBREG
5300 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5301 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5304 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5306 enum reg_class class = rld[r].class, last_class;
5307 rtx last_reg = reg_last_reload_reg[regno];
5309 i = REGNO (last_reg) + word;
5310 last_class = REGNO_REG_CLASS (i);
5311 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5312 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5313 && reg_reloaded_contents[i] == regno
5314 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5315 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5316 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5317 /* Even if we can't use this register as a reload
5318 register, we might use it for reload_override_in,
5319 if copying it to the desired class is cheap
5321 || ((REGISTER_MOVE_COST (last_class, class)
5322 < MEMORY_MOVE_COST (mode, class, 1))
5323 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5324 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5328 #ifdef SECONDARY_MEMORY_NEEDED
5329 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5334 && (rld[r].nregs == max_group_size
5335 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5337 && reload_reg_free_for_value_p (i, rld[r].opnum,
5342 /* If a group is needed, verify that all the subsequent
5343 registers still have their values intact. */
5345 = HARD_REGNO_NREGS (i, rld[r].mode);
5348 for (k = 1; k < nr; k++)
5349 if (reg_reloaded_contents[i + k] != regno
5350 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5357 last_reg = (GET_MODE (last_reg) == mode
5358 ? last_reg : gen_rtx_REG (mode, i));
5360 /* We found a register that contains the
5361 value we need. If this register is the
5362 same as an `earlyclobber' operand of the
5363 current insn, just mark it as a place to
5364 reload from since we can't use it as the
5365 reload register itself. */
5367 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5368 if (reg_overlap_mentioned_for_reload_p
5369 (reg_last_reload_reg[regno],
5370 reload_earlyclobbers[i1]))
5373 if (i1 != n_earlyclobbers
5374 || ! (reload_reg_free_for_value_p
5375 (i, rld[r].opnum, rld[r].when_needed,
5376 rld[r].in, rld[r].out, r, 1))
5377 /* Don't use it if we'd clobber a pseudo reg. */
5378 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5380 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5381 /* Don't clobber the frame pointer. */
5382 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5383 /* Don't really use the inherited spill reg
5384 if we need it wider than we've got it. */
5385 || (GET_MODE_SIZE (rld[r].mode)
5386 > GET_MODE_SIZE (mode))
5387 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5390 /* If find_reloads chose reload_out as reload
5391 register, stay with it - that leaves the
5392 inherited register for subsequent reloads. */
5393 || (rld[r].out && rld[r].reg_rtx
5394 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5396 reload_override_in[r] = last_reg;
5397 reload_inheritance_insn[r]
5398 = reg_reloaded_insn[i];
5403 /* We can use this as a reload reg. */
5404 /* Mark the register as in use for this part of
5406 mark_reload_reg_in_use (i,
5410 rld[r].reg_rtx = last_reg;
5411 reload_inherited[r] = 1;
5412 reload_inheritance_insn[r]
5413 = reg_reloaded_insn[i];
5414 reload_spill_index[r] = i;
5415 for (k = 0; k < nr; k++)
5416 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5424 /* Here's another way to see if the value is already lying around. */
5427 && ! reload_inherited[r]
5429 && (CONSTANT_P (rld[r].in)
5430 || GET_CODE (rld[r].in) == PLUS
5431 || GET_CODE (rld[r].in) == REG
5432 || GET_CODE (rld[r].in) == MEM)
5433 && (rld[r].nregs == max_group_size
5434 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5435 search_equiv = rld[r].in;
5436 /* If this is an output reload from a simple move insn, look
5437 if an equivalence for the input is available. */
5438 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5440 rtx set = single_set (insn);
5443 && rtx_equal_p (rld[r].out, SET_DEST (set))
5444 && CONSTANT_P (SET_SRC (set)))
5445 search_equiv = SET_SRC (set);
5451 = find_equiv_reg (search_equiv, insn, rld[r].class,
5452 -1, NULL_PTR, 0, rld[r].mode);
5457 if (GET_CODE (equiv) == REG)
5458 regno = REGNO (equiv);
5459 else if (GET_CODE (equiv) == SUBREG)
5461 /* This must be a SUBREG of a hard register.
5462 Make a new REG since this might be used in an
5463 address and not all machines support SUBREGs
5465 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5466 equiv = gen_rtx_REG (rld[r].mode, regno);
5472 /* If we found a spill reg, reject it unless it is free
5473 and of the desired class. */
5475 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5476 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5480 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5484 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5487 /* We found a register that contains the value we need.
5488 If this register is the same as an `earlyclobber' operand
5489 of the current insn, just mark it as a place to reload from
5490 since we can't use it as the reload register itself. */
5493 for (i = 0; i < n_earlyclobbers; i++)
5494 if (reg_overlap_mentioned_for_reload_p (equiv,
5495 reload_earlyclobbers[i]))
5497 reload_override_in[r] = equiv;
5502 /* If the equiv register we have found is explicitly clobbered
5503 in the current insn, it depends on the reload type if we
5504 can use it, use it for reload_override_in, or not at all.
5505 In particular, we then can't use EQUIV for a
5506 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5508 if (equiv != 0 && regno_clobbered_p (regno, insn))
5510 switch (rld[r].when_needed)
5512 case RELOAD_FOR_OTHER_ADDRESS:
5513 case RELOAD_FOR_INPADDR_ADDRESS:
5514 case RELOAD_FOR_INPUT_ADDRESS:
5515 case RELOAD_FOR_OPADDR_ADDR:
5518 case RELOAD_FOR_INPUT:
5519 case RELOAD_FOR_OPERAND_ADDRESS:
5520 reload_override_in[r] = equiv;
5528 /* If we found an equivalent reg, say no code need be generated
5529 to load it, and use it as our reload reg. */
5530 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5532 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5534 rld[r].reg_rtx = equiv;
5535 reload_inherited[r] = 1;
5537 /* If reg_reloaded_valid is not set for this register,
5538 there might be a stale spill_reg_store lying around.
5539 We must clear it, since otherwise emit_reload_insns
5540 might delete the store. */
5541 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5542 spill_reg_store[regno] = NULL_RTX;
5543 /* If any of the hard registers in EQUIV are spill
5544 registers, mark them as in use for this insn. */
5545 for (k = 0; k < nr; k++)
5547 i = spill_reg_order[regno + k];
5550 mark_reload_reg_in_use (regno, rld[r].opnum,
5553 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5560 /* If we found a register to use already, or if this is an optional
5561 reload, we are done. */
5562 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5565 #if 0 /* No longer needed for correct operation. Might or might not
5566 give better code on the average. Want to experiment? */
5568 /* See if there is a later reload that has a class different from our
5569 class that intersects our class or that requires less register
5570 than our reload. If so, we must allocate a register to this
5571 reload now, since that reload might inherit a previous reload
5572 and take the only available register in our class. Don't do this
5573 for optional reloads since they will force all previous reloads
5574 to be allocated. Also don't do this for reloads that have been
5577 for (i = j + 1; i < n_reloads; i++)
5579 int s = reload_order[i];
5581 if ((rld[s].in == 0 && rld[s].out == 0
5582 && ! rld[s].secondary_p)
5586 if ((rld[s].class != rld[r].class
5587 && reg_classes_intersect_p (rld[r].class,
5589 || rld[s].nregs < rld[r].nregs)
5596 allocate_reload_reg (chain, r, j == n_reloads - 1);
5600 /* Now allocate reload registers for anything non-optional that
5601 didn't get one yet. */
5602 for (j = 0; j < n_reloads; j++)
5604 register int r = reload_order[j];
5606 /* Ignore reloads that got marked inoperative. */
5607 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5610 /* Skip reloads that already have a register allocated or are
5612 if (rld[r].reg_rtx != 0 || rld[r].optional)
5615 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5619 /* If that loop got all the way, we have won. */
5626 /* Loop around and try without any inheritance. */
5631 /* First undo everything done by the failed attempt
5632 to allocate with inheritance. */
5633 choose_reload_regs_init (chain, save_reload_reg_rtx);
5635 /* Some sanity tests to verify that the reloads found in the first
5636 pass are identical to the ones we have now. */
5637 if (chain->n_reloads != n_reloads)
5640 for (i = 0; i < n_reloads; i++)
5642 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5644 if (chain->rld[i].when_needed != rld[i].when_needed)
5646 for (j = 0; j < n_spills; j++)
5647 if (spill_regs[j] == chain->rld[i].regno)
5648 if (! set_reload_reg (j, i))
5649 failed_reload (chain->insn, i);
5653 /* If we thought we could inherit a reload, because it seemed that
5654 nothing else wanted the same reload register earlier in the insn,
5655 verify that assumption, now that all reloads have been assigned.
5656 Likewise for reloads where reload_override_in has been set. */
5658 /* If doing expensive optimizations, do one preliminary pass that doesn't
5659 cancel any inheritance, but removes reloads that have been needed only
5660 for reloads that we know can be inherited. */
5661 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5663 for (j = 0; j < n_reloads; j++)
5665 register int r = reload_order[j];
5667 if (reload_inherited[r] && rld[r].reg_rtx)
5668 check_reg = rld[r].reg_rtx;
5669 else if (reload_override_in[r]
5670 && (GET_CODE (reload_override_in[r]) == REG
5671 || GET_CODE (reload_override_in[r]) == SUBREG))
5672 check_reg = reload_override_in[r];
5675 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5679 (reload_inherited[r]
5680 ? rld[r].out : const0_rtx),
5685 reload_inherited[r] = 0;
5686 reload_override_in[r] = 0;
5688 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5689 reload_override_in, then we do not need its related
5690 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5691 likewise for other reload types.
5692 We handle this by removing a reload when its only replacement
5693 is mentioned in reload_in of the reload we are going to inherit.
5694 A special case are auto_inc expressions; even if the input is
5695 inherited, we still need the address for the output. We can
5696 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5697 If we suceeded removing some reload and we are doing a preliminary
5698 pass just to remove such reloads, make another pass, since the
5699 removal of one reload might allow us to inherit another one. */
5701 && rld[r].out != rld[r].in
5702 && remove_address_replacements (rld[r].in) && pass)
5707 /* Now that reload_override_in is known valid,
5708 actually override reload_in. */
5709 for (j = 0; j < n_reloads; j++)
5710 if (reload_override_in[j])
5711 rld[j].in = reload_override_in[j];
5713 /* If this reload won't be done because it has been cancelled or is
5714 optional and not inherited, clear reload_reg_rtx so other
5715 routines (such as subst_reloads) don't get confused. */
5716 for (j = 0; j < n_reloads; j++)
5717 if (rld[j].reg_rtx != 0
5718 && ((rld[j].optional && ! reload_inherited[j])
5719 || (rld[j].in == 0 && rld[j].out == 0
5720 && ! rld[j].secondary_p)))
5722 int regno = true_regnum (rld[j].reg_rtx);
5724 if (spill_reg_order[regno] >= 0)
5725 clear_reload_reg_in_use (regno, rld[j].opnum,
5726 rld[j].when_needed, rld[j].mode);
5728 reload_spill_index[j] = -1;
5731 /* Record which pseudos and which spill regs have output reloads. */
5732 for (j = 0; j < n_reloads; j++)
5734 register int r = reload_order[j];
5736 i = reload_spill_index[r];
5738 /* I is nonneg if this reload uses a register.
5739 If rld[r].reg_rtx is 0, this is an optional reload
5740 that we opted to ignore. */
5741 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5742 && rld[r].reg_rtx != 0)
5744 register int nregno = REGNO (rld[r].out_reg);
5747 if (nregno < FIRST_PSEUDO_REGISTER)
5748 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5751 reg_has_output_reload[nregno + nr] = 1;
5755 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5757 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5760 if (rld[r].when_needed != RELOAD_OTHER
5761 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5762 && rld[r].when_needed != RELOAD_FOR_INSN)
5768 /* Deallocate the reload register for reload R. This is called from
5769 remove_address_replacements. */
5772 deallocate_reload_reg (r)
5777 if (! rld[r].reg_rtx)
5779 regno = true_regnum (rld[r].reg_rtx);
5781 if (spill_reg_order[regno] >= 0)
5782 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5784 reload_spill_index[r] = -1;
5787 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5788 reloads of the same item for fear that we might not have enough reload
5789 registers. However, normally they will get the same reload register
5790 and hence actually need not be loaded twice.
5792 Here we check for the most common case of this phenomenon: when we have
5793 a number of reloads for the same object, each of which were allocated
5794 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5795 reload, and is not modified in the insn itself. If we find such,
5796 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5797 This will not increase the number of spill registers needed and will
5798 prevent redundant code. */
5801 merge_assigned_reloads (insn)
5806 /* Scan all the reloads looking for ones that only load values and
5807 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5808 assigned and not modified by INSN. */
5810 for (i = 0; i < n_reloads; i++)
5812 int conflicting_input = 0;
5813 int max_input_address_opnum = -1;
5814 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5816 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5817 || rld[i].out != 0 || rld[i].reg_rtx == 0
5818 || reg_set_p (rld[i].reg_rtx, insn))
5821 /* Look at all other reloads. Ensure that the only use of this
5822 reload_reg_rtx is in a reload that just loads the same value
5823 as we do. Note that any secondary reloads must be of the identical
5824 class since the values, modes, and result registers are the
5825 same, so we need not do anything with any secondary reloads. */
5827 for (j = 0; j < n_reloads; j++)
5829 if (i == j || rld[j].reg_rtx == 0
5830 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5834 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5835 && rld[j].opnum > max_input_address_opnum)
5836 max_input_address_opnum = rld[j].opnum;
5838 /* If the reload regs aren't exactly the same (e.g, different modes)
5839 or if the values are different, we can't merge this reload.
5840 But if it is an input reload, we might still merge
5841 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5843 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5844 || rld[j].out != 0 || rld[j].in == 0
5845 || ! rtx_equal_p (rld[i].in, rld[j].in))
5847 if (rld[j].when_needed != RELOAD_FOR_INPUT
5848 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5849 || rld[i].opnum > rld[j].opnum)
5850 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5852 conflicting_input = 1;
5853 if (min_conflicting_input_opnum > rld[j].opnum)
5854 min_conflicting_input_opnum = rld[j].opnum;
5858 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5859 we, in fact, found any matching reloads. */
5862 && max_input_address_opnum <= min_conflicting_input_opnum)
5864 for (j = 0; j < n_reloads; j++)
5865 if (i != j && rld[j].reg_rtx != 0
5866 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5867 && (! conflicting_input
5868 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5869 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5871 rld[i].when_needed = RELOAD_OTHER;
5873 reload_spill_index[j] = -1;
5874 transfer_replacements (i, j);
5877 /* If this is now RELOAD_OTHER, look for any reloads that load
5878 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5879 if they were for inputs, RELOAD_OTHER for outputs. Note that
5880 this test is equivalent to looking for reloads for this operand
5883 if (rld[i].when_needed == RELOAD_OTHER)
5884 for (j = 0; j < n_reloads; j++)
5886 && rld[i].when_needed != RELOAD_OTHER
5887 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5890 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5891 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5892 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5898 /* These arrays are filled by emit_reload_insns and its subroutines. */
5899 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5900 static rtx other_input_address_reload_insns = 0;
5901 static rtx other_input_reload_insns = 0;
5902 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5903 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5904 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5905 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5906 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5907 static rtx operand_reload_insns = 0;
5908 static rtx other_operand_reload_insns = 0;
5909 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5911 /* Values to be put in spill_reg_store are put here first. */
5912 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5913 static HARD_REG_SET reg_reloaded_died;
5915 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5916 has the number J. OLD contains the value to be used as input. */
5919 emit_input_reload_insns (chain, rl, old, j)
5920 struct insn_chain *chain;
5925 rtx insn = chain->insn;
5926 register rtx reloadreg = rl->reg_rtx;
5927 rtx oldequiv_reg = 0;
5930 enum machine_mode mode;
5933 /* Determine the mode to reload in.
5934 This is very tricky because we have three to choose from.
5935 There is the mode the insn operand wants (rl->inmode).
5936 There is the mode of the reload register RELOADREG.
5937 There is the intrinsic mode of the operand, which we could find
5938 by stripping some SUBREGs.
5939 It turns out that RELOADREG's mode is irrelevant:
5940 we can change that arbitrarily.
5942 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5943 then the reload reg may not support QImode moves, so use SImode.
5944 If foo is in memory due to spilling a pseudo reg, this is safe,
5945 because the QImode value is in the least significant part of a
5946 slot big enough for a SImode. If foo is some other sort of
5947 memory reference, then it is impossible to reload this case,
5948 so previous passes had better make sure this never happens.
5950 Then consider a one-word union which has SImode and one of its
5951 members is a float, being fetched as (SUBREG:SF union:SI).
5952 We must fetch that as SFmode because we could be loading into
5953 a float-only register. In this case OLD's mode is correct.
5955 Consider an immediate integer: it has VOIDmode. Here we need
5956 to get a mode from something else.
5958 In some cases, there is a fourth mode, the operand's
5959 containing mode. If the insn specifies a containing mode for
5960 this operand, it overrides all others.
5962 I am not sure whether the algorithm here is always right,
5963 but it does the right things in those cases. */
5965 mode = GET_MODE (old);
5966 if (mode == VOIDmode)
5969 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5970 /* If we need a secondary register for this operation, see if
5971 the value is already in a register in that class. Don't
5972 do this if the secondary register will be used as a scratch
5975 if (rl->secondary_in_reload >= 0
5976 && rl->secondary_in_icode == CODE_FOR_nothing
5979 = find_equiv_reg (old, insn,
5980 rld[rl->secondary_in_reload].class,
5981 -1, NULL_PTR, 0, mode);
5984 /* If reloading from memory, see if there is a register
5985 that already holds the same value. If so, reload from there.
5986 We can pass 0 as the reload_reg_p argument because
5987 any other reload has either already been emitted,
5988 in which case find_equiv_reg will see the reload-insn,
5989 or has yet to be emitted, in which case it doesn't matter
5990 because we will use this equiv reg right away. */
5992 if (oldequiv == 0 && optimize
5993 && (GET_CODE (old) == MEM
5994 || (GET_CODE (old) == REG
5995 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5996 && reg_renumber[REGNO (old)] < 0)))
5997 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5998 -1, NULL_PTR, 0, mode);
6002 unsigned int regno = true_regnum (oldequiv);
6004 /* Don't use OLDEQUIV if any other reload changes it at an
6005 earlier stage of this insn or at this stage. */
6006 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6008 rl->in, const0_rtx, j,
6012 /* If it is no cheaper to copy from OLDEQUIV into the
6013 reload register than it would be to move from memory,
6014 don't use it. Likewise, if we need a secondary register
6018 && ((REGNO_REG_CLASS (regno) != rl->class
6019 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6021 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6022 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6023 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6027 #ifdef SECONDARY_MEMORY_NEEDED
6028 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6036 /* delete_output_reload is only invoked properly if old contains
6037 the original pseudo register. Since this is replaced with a
6038 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6039 find the pseudo in RELOAD_IN_REG. */
6041 && reload_override_in[j]
6042 && GET_CODE (rl->in_reg) == REG)
6049 else if (GET_CODE (oldequiv) == REG)
6050 oldequiv_reg = oldequiv;
6051 else if (GET_CODE (oldequiv) == SUBREG)
6052 oldequiv_reg = SUBREG_REG (oldequiv);
6054 /* If we are reloading from a register that was recently stored in
6055 with an output-reload, see if we can prove there was
6056 actually no need to store the old value in it. */
6058 if (optimize && GET_CODE (oldequiv) == REG
6059 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6060 && spill_reg_store[REGNO (oldequiv)]
6061 && GET_CODE (old) == REG
6062 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6063 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6065 delete_output_reload (insn, j, REGNO (oldequiv));
6067 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6068 then load RELOADREG from OLDEQUIV. Note that we cannot use
6069 gen_lowpart_common since it can do the wrong thing when
6070 RELOADREG has a multi-word mode. Note that RELOADREG
6071 must always be a REG here. */
6073 if (GET_MODE (reloadreg) != mode)
6074 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6075 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6076 oldequiv = SUBREG_REG (oldequiv);
6077 if (GET_MODE (oldequiv) != VOIDmode
6078 && mode != GET_MODE (oldequiv))
6079 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6081 /* Switch to the right place to emit the reload insns. */
6082 switch (rl->when_needed)
6085 where = &other_input_reload_insns;
6087 case RELOAD_FOR_INPUT:
6088 where = &input_reload_insns[rl->opnum];
6090 case RELOAD_FOR_INPUT_ADDRESS:
6091 where = &input_address_reload_insns[rl->opnum];
6093 case RELOAD_FOR_INPADDR_ADDRESS:
6094 where = &inpaddr_address_reload_insns[rl->opnum];
6096 case RELOAD_FOR_OUTPUT_ADDRESS:
6097 where = &output_address_reload_insns[rl->opnum];
6099 case RELOAD_FOR_OUTADDR_ADDRESS:
6100 where = &outaddr_address_reload_insns[rl->opnum];
6102 case RELOAD_FOR_OPERAND_ADDRESS:
6103 where = &operand_reload_insns;
6105 case RELOAD_FOR_OPADDR_ADDR:
6106 where = &other_operand_reload_insns;
6108 case RELOAD_FOR_OTHER_ADDRESS:
6109 where = &other_input_address_reload_insns;
6115 push_to_sequence (*where);
6117 /* Auto-increment addresses must be reloaded in a special way. */
6118 if (rl->out && ! rl->out_reg)
6120 /* We are not going to bother supporting the case where a
6121 incremented register can't be copied directly from
6122 OLDEQUIV since this seems highly unlikely. */
6123 if (rl->secondary_in_reload >= 0)
6126 if (reload_inherited[j])
6127 oldequiv = reloadreg;
6129 old = XEXP (rl->in_reg, 0);
6131 if (optimize && GET_CODE (oldequiv) == REG
6132 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6133 && spill_reg_store[REGNO (oldequiv)]
6134 && GET_CODE (old) == REG
6135 && (dead_or_set_p (insn,
6136 spill_reg_stored_to[REGNO (oldequiv)])
6137 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6139 delete_output_reload (insn, j, REGNO (oldequiv));
6141 /* Prevent normal processing of this reload. */
6143 /* Output a special code sequence for this case. */
6144 new_spill_reg_store[REGNO (reloadreg)]
6145 = inc_for_reload (reloadreg, oldequiv, rl->out,
6149 /* If we are reloading a pseudo-register that was set by the previous
6150 insn, see if we can get rid of that pseudo-register entirely
6151 by redirecting the previous insn into our reload register. */
6153 else if (optimize && GET_CODE (old) == REG
6154 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6155 && dead_or_set_p (insn, old)
6156 /* This is unsafe if some other reload
6157 uses the same reg first. */
6158 && reload_reg_free_for_value_p (REGNO (reloadreg),
6164 rtx temp = PREV_INSN (insn);
6165 while (temp && GET_CODE (temp) == NOTE)
6166 temp = PREV_INSN (temp);
6168 && GET_CODE (temp) == INSN
6169 && GET_CODE (PATTERN (temp)) == SET
6170 && SET_DEST (PATTERN (temp)) == old
6171 /* Make sure we can access insn_operand_constraint. */
6172 && asm_noperands (PATTERN (temp)) < 0
6173 /* This is unsafe if prev insn rejects our reload reg. */
6174 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6176 /* This is unsafe if operand occurs more than once in current
6177 insn. Perhaps some occurrences aren't reloaded. */
6178 && count_occurrences (PATTERN (insn), old) == 1
6179 /* Don't risk splitting a matching pair of operands. */
6180 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6182 /* Store into the reload register instead of the pseudo. */
6183 SET_DEST (PATTERN (temp)) = reloadreg;
6185 /* If the previous insn is an output reload, the source is
6186 a reload register, and its spill_reg_store entry will
6187 contain the previous destination. This is now
6189 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6190 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6192 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6193 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6196 /* If these are the only uses of the pseudo reg,
6197 pretend for GDB it lives in the reload reg we used. */
6198 if (REG_N_DEATHS (REGNO (old)) == 1
6199 && REG_N_SETS (REGNO (old)) == 1)
6201 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6202 alter_reg (REGNO (old), -1);
6208 /* We can't do that, so output an insn to load RELOADREG. */
6210 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6211 /* If we have a secondary reload, pick up the secondary register
6212 and icode, if any. If OLDEQUIV and OLD are different or
6213 if this is an in-out reload, recompute whether or not we
6214 still need a secondary register and what the icode should
6215 be. If we still need a secondary register and the class or
6216 icode is different, go back to reloading from OLD if using
6217 OLDEQUIV means that we got the wrong type of register. We
6218 cannot have different class or icode due to an in-out reload
6219 because we don't make such reloads when both the input and
6220 output need secondary reload registers. */
6222 if (! special && rl->secondary_in_reload >= 0)
6224 rtx second_reload_reg = 0;
6225 int secondary_reload = rl->secondary_in_reload;
6226 rtx real_oldequiv = oldequiv;
6229 enum insn_code icode;
6231 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6232 and similarly for OLD.
6233 See comments in get_secondary_reload in reload.c. */
6234 /* If it is a pseudo that cannot be replaced with its
6235 equivalent MEM, we must fall back to reload_in, which
6236 will have all the necessary substitutions registered.
6237 Likewise for a pseudo that can't be replaced with its
6238 equivalent constant.
6240 Take extra care for subregs of such pseudos. Note that
6241 we cannot use reg_equiv_mem in this case because it is
6242 not in the right mode. */
6245 if (GET_CODE (tmp) == SUBREG)
6246 tmp = SUBREG_REG (tmp);
6247 if (GET_CODE (tmp) == REG
6248 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6249 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6250 || reg_equiv_constant[REGNO (tmp)] != 0))
6252 if (! reg_equiv_mem[REGNO (tmp)]
6253 || num_not_at_initial_offset
6254 || GET_CODE (oldequiv) == SUBREG)
6255 real_oldequiv = rl->in;
6257 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6261 if (GET_CODE (tmp) == SUBREG)
6262 tmp = SUBREG_REG (tmp);
6263 if (GET_CODE (tmp) == REG
6264 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6265 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6266 || reg_equiv_constant[REGNO (tmp)] != 0))
6268 if (! reg_equiv_mem[REGNO (tmp)]
6269 || num_not_at_initial_offset
6270 || GET_CODE (old) == SUBREG)
6273 real_old = reg_equiv_mem[REGNO (tmp)];
6276 second_reload_reg = rld[secondary_reload].reg_rtx;
6277 icode = rl->secondary_in_icode;
6279 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6280 || (rl->in != 0 && rl->out != 0))
6282 enum reg_class new_class
6283 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6284 mode, real_oldequiv);
6286 if (new_class == NO_REGS)
6287 second_reload_reg = 0;
6290 enum insn_code new_icode;
6291 enum machine_mode new_mode;
6293 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6294 REGNO (second_reload_reg)))
6295 oldequiv = old, real_oldequiv = real_old;
6298 new_icode = reload_in_optab[(int) mode];
6299 if (new_icode != CODE_FOR_nothing
6300 && ((insn_data[(int) new_icode].operand[0].predicate
6301 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6303 || (insn_data[(int) new_icode].operand[1].predicate
6304 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6305 (real_oldequiv, mode)))))
6306 new_icode = CODE_FOR_nothing;
6308 if (new_icode == CODE_FOR_nothing)
6311 new_mode = insn_data[(int) new_icode].operand[2].mode;
6313 if (GET_MODE (second_reload_reg) != new_mode)
6315 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6317 oldequiv = old, real_oldequiv = real_old;
6320 = gen_rtx_REG (new_mode,
6321 REGNO (second_reload_reg));
6327 /* If we still need a secondary reload register, check
6328 to see if it is being used as a scratch or intermediate
6329 register and generate code appropriately. If we need
6330 a scratch register, use REAL_OLDEQUIV since the form of
6331 the insn may depend on the actual address if it is
6334 if (second_reload_reg)
6336 if (icode != CODE_FOR_nothing)
6338 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6339 second_reload_reg));
6344 /* See if we need a scratch register to load the
6345 intermediate register (a tertiary reload). */
6346 enum insn_code tertiary_icode
6347 = rld[secondary_reload].secondary_in_icode;
6349 if (tertiary_icode != CODE_FOR_nothing)
6351 rtx third_reload_reg
6352 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6354 emit_insn ((GEN_FCN (tertiary_icode)
6355 (second_reload_reg, real_oldequiv,
6356 third_reload_reg)));
6359 gen_reload (second_reload_reg, real_oldequiv,
6363 oldequiv = second_reload_reg;
6369 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6371 rtx real_oldequiv = oldequiv;
6373 if ((GET_CODE (oldequiv) == REG
6374 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6375 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6376 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6377 || (GET_CODE (oldequiv) == SUBREG
6378 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6379 && (REGNO (SUBREG_REG (oldequiv))
6380 >= FIRST_PSEUDO_REGISTER)
6381 && ((reg_equiv_memory_loc
6382 [REGNO (SUBREG_REG (oldequiv))] != 0)
6383 || (reg_equiv_constant
6384 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6385 real_oldequiv = rl->in;
6386 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6390 /* End this sequence. */
6391 *where = get_insns ();
6394 /* Update reload_override_in so that delete_address_reloads_1
6395 can see the actual register usage. */
6397 reload_override_in[j] = oldequiv;
6400 /* Generate insns to for the output reload RL, which is for the insn described
6401 by CHAIN and has the number J. */
6403 emit_output_reload_insns (chain, rl, j)
6404 struct insn_chain *chain;
6408 rtx reloadreg = rl->reg_rtx;
6409 rtx insn = chain->insn;
6412 enum machine_mode mode = GET_MODE (old);
6415 if (rl->when_needed == RELOAD_OTHER)
6418 push_to_sequence (output_reload_insns[rl->opnum]);
6420 /* Determine the mode to reload in.
6421 See comments above (for input reloading). */
6423 if (mode == VOIDmode)
6425 /* VOIDmode should never happen for an output. */
6426 if (asm_noperands (PATTERN (insn)) < 0)
6427 /* It's the compiler's fault. */
6428 fatal_insn ("VOIDmode on an output", insn);
6429 error_for_asm (insn, "output operand is constant in `asm'");
6430 /* Prevent crash--use something we know is valid. */
6432 old = gen_rtx_REG (mode, REGNO (reloadreg));
6435 if (GET_MODE (reloadreg) != mode)
6436 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6438 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6440 /* If we need two reload regs, set RELOADREG to the intermediate
6441 one, since it will be stored into OLD. We might need a secondary
6442 register only for an input reload, so check again here. */
6444 if (rl->secondary_out_reload >= 0)
6448 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6449 && reg_equiv_mem[REGNO (old)] != 0)
6450 real_old = reg_equiv_mem[REGNO (old)];
6452 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6456 rtx second_reloadreg = reloadreg;
6457 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6459 /* See if RELOADREG is to be used as a scratch register
6460 or as an intermediate register. */
6461 if (rl->secondary_out_icode != CODE_FOR_nothing)
6463 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6464 (real_old, second_reloadreg, reloadreg)));
6469 /* See if we need both a scratch and intermediate reload
6472 int secondary_reload = rl->secondary_out_reload;
6473 enum insn_code tertiary_icode
6474 = rld[secondary_reload].secondary_out_icode;
6476 if (GET_MODE (reloadreg) != mode)
6477 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6479 if (tertiary_icode != CODE_FOR_nothing)
6482 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6485 /* Copy primary reload reg to secondary reload reg.
6486 (Note that these have been swapped above, then
6487 secondary reload reg to OLD using our insn. */
6489 /* If REAL_OLD is a paradoxical SUBREG, remove it
6490 and try to put the opposite SUBREG on
6492 if (GET_CODE (real_old) == SUBREG
6493 && (GET_MODE_SIZE (GET_MODE (real_old))
6494 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6495 && 0 != (tem = gen_lowpart_common
6496 (GET_MODE (SUBREG_REG (real_old)),
6498 real_old = SUBREG_REG (real_old), reloadreg = tem;
6500 gen_reload (reloadreg, second_reloadreg,
6501 rl->opnum, rl->when_needed);
6502 emit_insn ((GEN_FCN (tertiary_icode)
6503 (real_old, reloadreg, third_reloadreg)));
6508 /* Copy between the reload regs here and then to
6511 gen_reload (reloadreg, second_reloadreg,
6512 rl->opnum, rl->when_needed);
6518 /* Output the last reload insn. */
6523 /* Don't output the last reload if OLD is not the dest of
6524 INSN and is in the src and is clobbered by INSN. */
6525 if (! flag_expensive_optimizations
6526 || GET_CODE (old) != REG
6527 || !(set = single_set (insn))
6528 || rtx_equal_p (old, SET_DEST (set))
6529 || !reg_mentioned_p (old, SET_SRC (set))
6530 || !regno_clobbered_p (REGNO (old), insn))
6531 gen_reload (old, reloadreg, rl->opnum,
6535 /* Look at all insns we emitted, just to be safe. */
6536 for (p = get_insns (); p; p = NEXT_INSN (p))
6537 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6539 rtx pat = PATTERN (p);
6541 /* If this output reload doesn't come from a spill reg,
6542 clear any memory of reloaded copies of the pseudo reg.
6543 If this output reload comes from a spill reg,
6544 reg_has_output_reload will make this do nothing. */
6545 note_stores (pat, forget_old_reloads_1, NULL);
6547 if (reg_mentioned_p (rl->reg_rtx, pat))
6549 rtx set = single_set (insn);
6550 if (reload_spill_index[j] < 0
6552 && SET_SRC (set) == rl->reg_rtx)
6554 int src = REGNO (SET_SRC (set));
6556 reload_spill_index[j] = src;
6557 SET_HARD_REG_BIT (reg_is_output_reload, src);
6558 if (find_regno_note (insn, REG_DEAD, src))
6559 SET_HARD_REG_BIT (reg_reloaded_died, src);
6561 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6563 int s = rl->secondary_out_reload;
6564 set = single_set (p);
6565 /* If this reload copies only to the secondary reload
6566 register, the secondary reload does the actual
6568 if (s >= 0 && set == NULL_RTX)
6569 ; /* We can't tell what function the secondary reload
6570 has and where the actual store to the pseudo is
6571 made; leave new_spill_reg_store alone. */
6573 && SET_SRC (set) == rl->reg_rtx
6574 && SET_DEST (set) == rld[s].reg_rtx)
6576 /* Usually the next instruction will be the
6577 secondary reload insn; if we can confirm
6578 that it is, setting new_spill_reg_store to
6579 that insn will allow an extra optimization. */
6580 rtx s_reg = rld[s].reg_rtx;
6581 rtx next = NEXT_INSN (p);
6582 rld[s].out = rl->out;
6583 rld[s].out_reg = rl->out_reg;
6584 set = single_set (next);
6585 if (set && SET_SRC (set) == s_reg
6586 && ! new_spill_reg_store[REGNO (s_reg)])
6588 SET_HARD_REG_BIT (reg_is_output_reload,
6590 new_spill_reg_store[REGNO (s_reg)] = next;
6594 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6599 if (rl->when_needed == RELOAD_OTHER)
6601 emit_insns (other_output_reload_insns[rl->opnum]);
6602 other_output_reload_insns[rl->opnum] = get_insns ();
6605 output_reload_insns[rl->opnum] = get_insns ();
6610 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6611 and has the number J. */
6613 do_input_reload (chain, rl, j)
6614 struct insn_chain *chain;
6618 int expect_occurrences = 1;
6619 rtx insn = chain->insn;
6620 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6621 ? rl->in_reg : rl->in);
6624 /* AUTO_INC reloads need to be handled even if inherited. We got an
6625 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6626 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6627 && ! rtx_equal_p (rl->reg_rtx, old)
6628 && rl->reg_rtx != 0)
6629 emit_input_reload_insns (chain, rld + j, old, j);
6631 /* When inheriting a wider reload, we have a MEM in rl->in,
6632 e.g. inheriting a SImode output reload for
6633 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6634 if (optimize && reload_inherited[j] && rl->in
6635 && GET_CODE (rl->in) == MEM
6636 && GET_CODE (rl->in_reg) == MEM
6637 && reload_spill_index[j] >= 0
6638 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6641 = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1;
6643 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6646 /* If we are reloading a register that was recently stored in with an
6647 output-reload, see if we can prove there was
6648 actually no need to store the old value in it. */
6651 && (reload_inherited[j] || reload_override_in[j])
6653 && GET_CODE (rl->reg_rtx) == REG
6654 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6656 /* There doesn't seem to be any reason to restrict this to pseudos
6657 and doing so loses in the case where we are copying from a
6658 register of the wrong class. */
6659 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6660 >= FIRST_PSEUDO_REGISTER)
6662 /* The insn might have already some references to stackslots
6663 replaced by MEMs, while reload_out_reg still names the
6665 && (dead_or_set_p (insn,
6666 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6667 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6669 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6672 /* Do output reloading for reload RL, which is for the insn described by
6673 CHAIN and has the number J.
6674 ??? At some point we need to support handling output reloads of
6675 JUMP_INSNs or insns that set cc0. */
6677 do_output_reload (chain, rl, j)
6678 struct insn_chain *chain;
6683 rtx insn = chain->insn;
6684 /* If this is an output reload that stores something that is
6685 not loaded in this same reload, see if we can eliminate a previous
6687 rtx pseudo = rl->out_reg;
6690 && GET_CODE (pseudo) == REG
6691 && ! rtx_equal_p (rl->in_reg, pseudo)
6692 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6693 && reg_last_reload_reg[REGNO (pseudo)])
6695 int pseudo_no = REGNO (pseudo);
6696 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6698 /* We don't need to test full validity of last_regno for
6699 inherit here; we only want to know if the store actually
6700 matches the pseudo. */
6701 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6702 && reg_reloaded_contents[last_regno] == pseudo_no
6703 && spill_reg_store[last_regno]
6704 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6705 delete_output_reload (insn, j, last_regno);
6710 || rl->reg_rtx == old
6711 || rl->reg_rtx == 0)
6714 /* An output operand that dies right away does need a reload,
6715 but need not be copied from it. Show the new location in the
6717 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6718 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6720 XEXP (note, 0) = rl->reg_rtx;
6723 /* Likewise for a SUBREG of an operand that dies. */
6724 else if (GET_CODE (old) == SUBREG
6725 && GET_CODE (SUBREG_REG (old)) == REG
6726 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6729 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6733 else if (GET_CODE (old) == SCRATCH)
6734 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6735 but we don't want to make an output reload. */
6738 /* If is a JUMP_INSN, we can't support output reloads yet. */
6739 if (GET_CODE (insn) == JUMP_INSN)
6742 emit_output_reload_insns (chain, rld + j, j);
6745 /* Output insns to reload values in and out of the chosen reload regs. */
6748 emit_reload_insns (chain)
6749 struct insn_chain *chain;
6751 rtx insn = chain->insn;
6754 rtx following_insn = NEXT_INSN (insn);
6755 rtx before_insn = PREV_INSN (insn);
6757 CLEAR_HARD_REG_SET (reg_reloaded_died);
6759 for (j = 0; j < reload_n_operands; j++)
6760 input_reload_insns[j] = input_address_reload_insns[j]
6761 = inpaddr_address_reload_insns[j]
6762 = output_reload_insns[j] = output_address_reload_insns[j]
6763 = outaddr_address_reload_insns[j]
6764 = other_output_reload_insns[j] = 0;
6765 other_input_address_reload_insns = 0;
6766 other_input_reload_insns = 0;
6767 operand_reload_insns = 0;
6768 other_operand_reload_insns = 0;
6770 /* Now output the instructions to copy the data into and out of the
6771 reload registers. Do these in the order that the reloads were reported,
6772 since reloads of base and index registers precede reloads of operands
6773 and the operands may need the base and index registers reloaded. */
6775 for (j = 0; j < n_reloads; j++)
6778 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6779 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6781 do_input_reload (chain, rld + j, j);
6782 do_output_reload (chain, rld + j, j);
6785 /* Now write all the insns we made for reloads in the order expected by
6786 the allocation functions. Prior to the insn being reloaded, we write
6787 the following reloads:
6789 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6791 RELOAD_OTHER reloads.
6793 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6794 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6795 RELOAD_FOR_INPUT reload for the operand.
6797 RELOAD_FOR_OPADDR_ADDRS reloads.
6799 RELOAD_FOR_OPERAND_ADDRESS reloads.
6801 After the insn being reloaded, we write the following:
6803 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6804 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6805 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6806 reloads for the operand. The RELOAD_OTHER output reloads are
6807 output in descending order by reload number. */
6809 emit_insns_before (other_input_address_reload_insns, insn);
6810 emit_insns_before (other_input_reload_insns, insn);
6812 for (j = 0; j < reload_n_operands; j++)
6814 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6815 emit_insns_before (input_address_reload_insns[j], insn);
6816 emit_insns_before (input_reload_insns[j], insn);
6819 emit_insns_before (other_operand_reload_insns, insn);
6820 emit_insns_before (operand_reload_insns, insn);
6822 for (j = 0; j < reload_n_operands; j++)
6824 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6825 emit_insns_before (output_address_reload_insns[j], following_insn);
6826 emit_insns_before (output_reload_insns[j], following_insn);
6827 emit_insns_before (other_output_reload_insns[j], following_insn);
6830 /* Keep basic block info up to date. */
6833 if (BLOCK_HEAD (chain->block) == insn)
6834 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6835 if (BLOCK_END (chain->block) == insn)
6836 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6839 /* For all the spill regs newly reloaded in this instruction,
6840 record what they were reloaded from, so subsequent instructions
6841 can inherit the reloads.
6843 Update spill_reg_store for the reloads of this insn.
6844 Copy the elements that were updated in the loop above. */
6846 for (j = 0; j < n_reloads; j++)
6848 register int r = reload_order[j];
6849 register int i = reload_spill_index[r];
6851 /* If this is a non-inherited input reload from a pseudo, we must
6852 clear any memory of a previous store to the same pseudo. Only do
6853 something if there will not be an output reload for the pseudo
6855 if (rld[r].in_reg != 0
6856 && ! (reload_inherited[r] || reload_override_in[r]))
6858 rtx reg = rld[r].in_reg;
6860 if (GET_CODE (reg) == SUBREG)
6861 reg = SUBREG_REG (reg);
6863 if (GET_CODE (reg) == REG
6864 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6865 && ! reg_has_output_reload[REGNO (reg)])
6867 int nregno = REGNO (reg);
6869 if (reg_last_reload_reg[nregno])
6871 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6873 if (reg_reloaded_contents[last_regno] == nregno)
6874 spill_reg_store[last_regno] = 0;
6879 /* I is nonneg if this reload used a register.
6880 If rld[r].reg_rtx is 0, this is an optional reload
6881 that we opted to ignore. */
6883 if (i >= 0 && rld[r].reg_rtx != 0)
6886 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6888 int part_reaches_end = 0;
6889 int all_reaches_end = 1;
6891 /* For a multi register reload, we need to check if all or part
6892 of the value lives to the end. */
6893 for (k = 0; k < nr; k++)
6895 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6896 rld[r].when_needed))
6897 part_reaches_end = 1;
6899 all_reaches_end = 0;
6902 /* Ignore reloads that don't reach the end of the insn in
6904 if (all_reaches_end)
6906 /* First, clear out memory of what used to be in this spill reg.
6907 If consecutive registers are used, clear them all. */
6909 for (k = 0; k < nr; k++)
6910 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6912 /* Maybe the spill reg contains a copy of reload_out. */
6914 && (GET_CODE (rld[r].out) == REG
6918 || GET_CODE (rld[r].out_reg) == REG))
6920 rtx out = (GET_CODE (rld[r].out) == REG
6924 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6925 register int nregno = REGNO (out);
6926 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6927 : HARD_REGNO_NREGS (nregno,
6928 GET_MODE (rld[r].reg_rtx)));
6930 spill_reg_store[i] = new_spill_reg_store[i];
6931 spill_reg_stored_to[i] = out;
6932 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6934 /* If NREGNO is a hard register, it may occupy more than
6935 one register. If it does, say what is in the
6936 rest of the registers assuming that both registers
6937 agree on how many words the object takes. If not,
6938 invalidate the subsequent registers. */
6940 if (nregno < FIRST_PSEUDO_REGISTER)
6941 for (k = 1; k < nnr; k++)
6942 reg_last_reload_reg[nregno + k]
6944 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6945 REGNO (rld[r].reg_rtx) + k)
6948 /* Now do the inverse operation. */
6949 for (k = 0; k < nr; k++)
6951 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6952 reg_reloaded_contents[i + k]
6953 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6956 reg_reloaded_insn[i + k] = insn;
6957 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6961 /* Maybe the spill reg contains a copy of reload_in. Only do
6962 something if there will not be an output reload for
6963 the register being reloaded. */
6964 else if (rld[r].out_reg == 0
6966 && ((GET_CODE (rld[r].in) == REG
6967 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6968 && ! reg_has_output_reload[REGNO (rld[r].in)])
6969 || (GET_CODE (rld[r].in_reg) == REG
6970 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6971 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6973 register int nregno;
6976 if (GET_CODE (rld[r].in) == REG
6977 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6978 nregno = REGNO (rld[r].in);
6979 else if (GET_CODE (rld[r].in_reg) == REG)
6980 nregno = REGNO (rld[r].in_reg);
6982 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6984 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6985 : HARD_REGNO_NREGS (nregno,
6986 GET_MODE (rld[r].reg_rtx)));
6988 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6990 if (nregno < FIRST_PSEUDO_REGISTER)
6991 for (k = 1; k < nnr; k++)
6992 reg_last_reload_reg[nregno + k]
6994 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6995 REGNO (rld[r].reg_rtx) + k)
6998 /* Unless we inherited this reload, show we haven't
6999 recently done a store.
7000 Previous stores of inherited auto_inc expressions
7001 also have to be discarded. */
7002 if (! reload_inherited[r]
7003 || (rld[r].out && ! rld[r].out_reg))
7004 spill_reg_store[i] = 0;
7006 for (k = 0; k < nr; k++)
7008 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7009 reg_reloaded_contents[i + k]
7010 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7013 reg_reloaded_insn[i + k] = insn;
7014 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7019 /* However, if part of the reload reaches the end, then we must
7020 invalidate the old info for the part that survives to the end. */
7021 else if (part_reaches_end)
7023 for (k = 0; k < nr; k++)
7024 if (reload_reg_reaches_end_p (i + k,
7026 rld[r].when_needed))
7027 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7031 /* The following if-statement was #if 0'd in 1.34 (or before...).
7032 It's reenabled in 1.35 because supposedly nothing else
7033 deals with this problem. */
7035 /* If a register gets output-reloaded from a non-spill register,
7036 that invalidates any previous reloaded copy of it.
7037 But forget_old_reloads_1 won't get to see it, because
7038 it thinks only about the original insn. So invalidate it here. */
7039 if (i < 0 && rld[r].out != 0
7040 && (GET_CODE (rld[r].out) == REG
7041 || (GET_CODE (rld[r].out) == MEM
7042 && GET_CODE (rld[r].out_reg) == REG)))
7044 rtx out = (GET_CODE (rld[r].out) == REG
7045 ? rld[r].out : rld[r].out_reg);
7046 register int nregno = REGNO (out);
7047 if (nregno >= FIRST_PSEUDO_REGISTER)
7049 rtx src_reg, store_insn = NULL_RTX;
7051 reg_last_reload_reg[nregno] = 0;
7053 /* If we can find a hard register that is stored, record
7054 the storing insn so that we may delete this insn with
7055 delete_output_reload. */
7056 src_reg = rld[r].reg_rtx;
7058 /* If this is an optional reload, try to find the source reg
7059 from an input reload. */
7062 rtx set = single_set (insn);
7063 if (set && SET_DEST (set) == rld[r].out)
7067 src_reg = SET_SRC (set);
7069 for (k = 0; k < n_reloads; k++)
7071 if (rld[k].in == src_reg)
7073 src_reg = rld[k].reg_rtx;
7080 store_insn = new_spill_reg_store[REGNO (src_reg)];
7081 if (src_reg && GET_CODE (src_reg) == REG
7082 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7084 int src_regno = REGNO (src_reg);
7085 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7086 /* The place where to find a death note varies with
7087 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7088 necessarily checked exactly in the code that moves
7089 notes, so just check both locations. */
7090 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7092 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7095 spill_reg_store[src_regno + nr] = store_insn;
7096 spill_reg_stored_to[src_regno + nr] = out;
7097 reg_reloaded_contents[src_regno + nr] = nregno;
7098 reg_reloaded_insn[src_regno + nr] = store_insn;
7099 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7100 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7101 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7103 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7105 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7107 reg_last_reload_reg[nregno] = src_reg;
7112 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7114 while (num_regs-- > 0)
7115 reg_last_reload_reg[nregno + num_regs] = 0;
7119 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7122 /* Emit code to perform a reload from IN (which may be a reload register) to
7123 OUT (which may also be a reload register). IN or OUT is from operand
7124 OPNUM with reload type TYPE.
7126 Returns first insn emitted. */
7129 gen_reload (out, in, opnum, type)
7133 enum reload_type type;
7135 rtx last = get_last_insn ();
7138 /* If IN is a paradoxical SUBREG, remove it and try to put the
7139 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7140 if (GET_CODE (in) == SUBREG
7141 && (GET_MODE_SIZE (GET_MODE (in))
7142 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7143 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7144 in = SUBREG_REG (in), out = tem;
7145 else if (GET_CODE (out) == SUBREG
7146 && (GET_MODE_SIZE (GET_MODE (out))
7147 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7148 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7149 out = SUBREG_REG (out), in = tem;
7151 /* How to do this reload can get quite tricky. Normally, we are being
7152 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7153 register that didn't get a hard register. In that case we can just
7154 call emit_move_insn.
7156 We can also be asked to reload a PLUS that adds a register or a MEM to
7157 another register, constant or MEM. This can occur during frame pointer
7158 elimination and while reloading addresses. This case is handled by
7159 trying to emit a single insn to perform the add. If it is not valid,
7160 we use a two insn sequence.
7162 Finally, we could be called to handle an 'o' constraint by putting
7163 an address into a register. In that case, we first try to do this
7164 with a named pattern of "reload_load_address". If no such pattern
7165 exists, we just emit a SET insn and hope for the best (it will normally
7166 be valid on machines that use 'o').
7168 This entire process is made complex because reload will never
7169 process the insns we generate here and so we must ensure that
7170 they will fit their constraints and also by the fact that parts of
7171 IN might be being reloaded separately and replaced with spill registers.
7172 Because of this, we are, in some sense, just guessing the right approach
7173 here. The one listed above seems to work.
7175 ??? At some point, this whole thing needs to be rethought. */
7177 if (GET_CODE (in) == PLUS
7178 && (GET_CODE (XEXP (in, 0)) == REG
7179 || GET_CODE (XEXP (in, 0)) == SUBREG
7180 || GET_CODE (XEXP (in, 0)) == MEM)
7181 && (GET_CODE (XEXP (in, 1)) == REG
7182 || GET_CODE (XEXP (in, 1)) == SUBREG
7183 || CONSTANT_P (XEXP (in, 1))
7184 || GET_CODE (XEXP (in, 1)) == MEM))
7186 /* We need to compute the sum of a register or a MEM and another
7187 register, constant, or MEM, and put it into the reload
7188 register. The best possible way of doing this is if the machine
7189 has a three-operand ADD insn that accepts the required operands.
7191 The simplest approach is to try to generate such an insn and see if it
7192 is recognized and matches its constraints. If so, it can be used.
7194 It might be better not to actually emit the insn unless it is valid,
7195 but we need to pass the insn as an operand to `recog' and
7196 `extract_insn' and it is simpler to emit and then delete the insn if
7197 not valid than to dummy things up. */
7199 rtx op0, op1, tem, insn;
7202 op0 = find_replacement (&XEXP (in, 0));
7203 op1 = find_replacement (&XEXP (in, 1));
7205 /* Since constraint checking is strict, commutativity won't be
7206 checked, so we need to do that here to avoid spurious failure
7207 if the add instruction is two-address and the second operand
7208 of the add is the same as the reload reg, which is frequently
7209 the case. If the insn would be A = B + A, rearrange it so
7210 it will be A = A + B as constrain_operands expects. */
7212 if (GET_CODE (XEXP (in, 1)) == REG
7213 && REGNO (out) == REGNO (XEXP (in, 1)))
7214 tem = op0, op0 = op1, op1 = tem;
7216 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7217 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7219 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7220 code = recog_memoized (insn);
7224 extract_insn (insn);
7225 /* We want constrain operands to treat this insn strictly in
7226 its validity determination, i.e., the way it would after reload
7228 if (constrain_operands (1))
7232 delete_insns_since (last);
7234 /* If that failed, we must use a conservative two-insn sequence.
7236 Use a move to copy one operand into the reload register. Prefer
7237 to reload a constant, MEM or pseudo since the move patterns can
7238 handle an arbitrary operand. If OP1 is not a constant, MEM or
7239 pseudo and OP1 is not a valid operand for an add instruction, then
7242 After reloading one of the operands into the reload register, add
7243 the reload register to the output register.
7245 If there is another way to do this for a specific machine, a
7246 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7249 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7251 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7252 || (GET_CODE (op1) == REG
7253 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7254 || (code != CODE_FOR_nothing
7255 && ! ((*insn_data[code].operand[2].predicate)
7256 (op1, insn_data[code].operand[2].mode))))
7257 tem = op0, op0 = op1, op1 = tem;
7259 gen_reload (out, op0, opnum, type);
7261 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7262 This fixes a problem on the 32K where the stack pointer cannot
7263 be used as an operand of an add insn. */
7265 if (rtx_equal_p (op0, op1))
7268 insn = emit_insn (gen_add2_insn (out, op1));
7270 /* If that failed, copy the address register to the reload register.
7271 Then add the constant to the reload register. */
7273 code = recog_memoized (insn);
7277 extract_insn (insn);
7278 /* We want constrain operands to treat this insn strictly in
7279 its validity determination, i.e., the way it would after reload
7281 if (constrain_operands (1))
7283 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7285 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7290 delete_insns_since (last);
7292 gen_reload (out, op1, opnum, type);
7293 insn = emit_insn (gen_add2_insn (out, op0));
7294 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7297 #ifdef SECONDARY_MEMORY_NEEDED
7298 /* If we need a memory location to do the move, do it that way. */
7299 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7300 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7301 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7302 REGNO_REG_CLASS (REGNO (out)),
7305 /* Get the memory to use and rewrite both registers to its mode. */
7306 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7308 if (GET_MODE (loc) != GET_MODE (out))
7309 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7311 if (GET_MODE (loc) != GET_MODE (in))
7312 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7314 gen_reload (loc, in, opnum, type);
7315 gen_reload (out, loc, opnum, type);
7319 /* If IN is a simple operand, use gen_move_insn. */
7320 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7321 emit_insn (gen_move_insn (out, in));
7323 #ifdef HAVE_reload_load_address
7324 else if (HAVE_reload_load_address)
7325 emit_insn (gen_reload_load_address (out, in));
7328 /* Otherwise, just write (set OUT IN) and hope for the best. */
7330 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7332 /* Return the first insn emitted.
7333 We can not just return get_last_insn, because there may have
7334 been multiple instructions emitted. Also note that gen_move_insn may
7335 emit more than one insn itself, so we can not assume that there is one
7336 insn emitted per emit_insn_before call. */
7338 return last ? NEXT_INSN (last) : get_insns ();
7341 /* Delete a previously made output-reload
7342 whose result we now believe is not needed.
7343 First we double-check.
7345 INSN is the insn now being processed.
7346 LAST_RELOAD_REG is the hard register number for which we want to delete
7347 the last output reload.
7348 J is the reload-number that originally used REG. The caller has made
7349 certain that reload J doesn't use REG any longer for input. */
7352 delete_output_reload (insn, j, last_reload_reg)
7355 int last_reload_reg;
7357 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7358 rtx reg = spill_reg_stored_to[last_reload_reg];
7361 int n_inherited = 0;
7365 /* Get the raw pseudo-register referred to. */
7367 while (GET_CODE (reg) == SUBREG)
7368 reg = SUBREG_REG (reg);
7369 substed = reg_equiv_memory_loc[REGNO (reg)];
7371 /* This is unsafe if the operand occurs more often in the current
7372 insn than it is inherited. */
7373 for (k = n_reloads - 1; k >= 0; k--)
7375 rtx reg2 = rld[k].in;
7378 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7379 reg2 = rld[k].in_reg;
7381 if (rld[k].out && ! rld[k].out_reg)
7382 reg2 = XEXP (rld[k].in_reg, 0);
7384 while (GET_CODE (reg2) == SUBREG)
7385 reg2 = SUBREG_REG (reg2);
7386 if (rtx_equal_p (reg2, reg))
7388 if (reload_inherited[k] || reload_override_in[k] || k == j)
7391 reg2 = rld[k].out_reg;
7394 while (GET_CODE (reg2) == SUBREG)
7395 reg2 = XEXP (reg2, 0);
7396 if (rtx_equal_p (reg2, reg))
7403 n_occurrences = count_occurrences (PATTERN (insn), reg);
7405 n_occurrences += count_occurrences (PATTERN (insn), substed);
7406 if (n_occurrences > n_inherited)
7409 /* If the pseudo-reg we are reloading is no longer referenced
7410 anywhere between the store into it and here,
7411 and no jumps or labels intervene, then the value can get
7412 here through the reload reg alone.
7413 Otherwise, give up--return. */
7414 for (i1 = NEXT_INSN (output_reload_insn);
7415 i1 != insn; i1 = NEXT_INSN (i1))
7417 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7419 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7420 && reg_mentioned_p (reg, PATTERN (i1)))
7422 /* If this is USE in front of INSN, we only have to check that
7423 there are no more references than accounted for by inheritance. */
7424 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7426 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7427 i1 = NEXT_INSN (i1);
7429 if (n_occurrences <= n_inherited && i1 == insn)
7435 /* The caller has already checked that REG dies or is set in INSN.
7436 It has also checked that we are optimizing, and thus some inaccurancies
7437 in the debugging information are acceptable.
7438 So we could just delete output_reload_insn.
7439 But in some cases we can improve the debugging information without
7440 sacrificing optimization - maybe even improving the code:
7441 See if the pseudo reg has been completely replaced
7442 with reload regs. If so, delete the store insn
7443 and forget we had a stack slot for the pseudo. */
7444 if (rld[j].out != rld[j].in
7445 && REG_N_DEATHS (REGNO (reg)) == 1
7446 && REG_N_SETS (REGNO (reg)) == 1
7447 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7448 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7452 /* We know that it was used only between here
7453 and the beginning of the current basic block.
7454 (We also know that the last use before INSN was
7455 the output reload we are thinking of deleting, but never mind that.)
7456 Search that range; see if any ref remains. */
7457 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7459 rtx set = single_set (i2);
7461 /* Uses which just store in the pseudo don't count,
7462 since if they are the only uses, they are dead. */
7463 if (set != 0 && SET_DEST (set) == reg)
7465 if (GET_CODE (i2) == CODE_LABEL
7466 || GET_CODE (i2) == JUMP_INSN)
7468 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7469 && reg_mentioned_p (reg, PATTERN (i2)))
7471 /* Some other ref remains; just delete the output reload we
7473 delete_address_reloads (output_reload_insn, insn);
7474 PUT_CODE (output_reload_insn, NOTE);
7475 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7476 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7481 /* Delete the now-dead stores into this pseudo. */
7482 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7484 rtx set = single_set (i2);
7486 if (set != 0 && SET_DEST (set) == reg)
7488 delete_address_reloads (i2, insn);
7489 /* This might be a basic block head,
7490 thus don't use delete_insn. */
7491 PUT_CODE (i2, NOTE);
7492 NOTE_SOURCE_FILE (i2) = 0;
7493 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7495 if (GET_CODE (i2) == CODE_LABEL
7496 || GET_CODE (i2) == JUMP_INSN)
7500 /* For the debugging info,
7501 say the pseudo lives in this reload reg. */
7502 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7503 alter_reg (REGNO (reg), -1);
7505 delete_address_reloads (output_reload_insn, insn);
7506 PUT_CODE (output_reload_insn, NOTE);
7507 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7508 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7512 /* We are going to delete DEAD_INSN. Recursively delete loads of
7513 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7514 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7516 delete_address_reloads (dead_insn, current_insn)
7517 rtx dead_insn, current_insn;
7519 rtx set = single_set (dead_insn);
7520 rtx set2, dst, prev, next;
7523 rtx dst = SET_DEST (set);
7524 if (GET_CODE (dst) == MEM)
7525 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7527 /* If we deleted the store from a reloaded post_{in,de}c expression,
7528 we can delete the matching adds. */
7529 prev = PREV_INSN (dead_insn);
7530 next = NEXT_INSN (dead_insn);
7531 if (! prev || ! next)
7533 set = single_set (next);
7534 set2 = single_set (prev);
7536 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7537 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7538 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7540 dst = SET_DEST (set);
7541 if (! rtx_equal_p (dst, SET_DEST (set2))
7542 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7543 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7544 || (INTVAL (XEXP (SET_SRC (set), 1))
7545 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7551 /* Subfunction of delete_address_reloads: process registers found in X. */
7553 delete_address_reloads_1 (dead_insn, x, current_insn)
7554 rtx dead_insn, x, current_insn;
7556 rtx prev, set, dst, i2;
7558 enum rtx_code code = GET_CODE (x);
7562 const char *fmt= GET_RTX_FORMAT (code);
7563 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7566 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7567 else if (fmt[i] == 'E')
7569 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7570 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7577 if (spill_reg_order[REGNO (x)] < 0)
7580 /* Scan backwards for the insn that sets x. This might be a way back due
7582 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7584 code = GET_CODE (prev);
7585 if (code == CODE_LABEL || code == JUMP_INSN)
7587 if (GET_RTX_CLASS (code) != 'i')
7589 if (reg_set_p (x, PATTERN (prev)))
7591 if (reg_referenced_p (x, PATTERN (prev)))
7594 if (! prev || INSN_UID (prev) < reload_first_uid)
7596 /* Check that PREV only sets the reload register. */
7597 set = single_set (prev);
7600 dst = SET_DEST (set);
7601 if (GET_CODE (dst) != REG
7602 || ! rtx_equal_p (dst, x))
7604 if (! reg_set_p (dst, PATTERN (dead_insn)))
7606 /* Check if DST was used in a later insn -
7607 it might have been inherited. */
7608 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7610 if (GET_CODE (i2) == CODE_LABEL)
7612 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7614 if (reg_referenced_p (dst, PATTERN (i2)))
7616 /* If there is a reference to the register in the current insn,
7617 it might be loaded in a non-inherited reload. If no other
7618 reload uses it, that means the register is set before
7620 if (i2 == current_insn)
7622 for (j = n_reloads - 1; j >= 0; j--)
7623 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7624 || reload_override_in[j] == dst)
7626 for (j = n_reloads - 1; j >= 0; j--)
7627 if (rld[j].in && rld[j].reg_rtx == dst)
7634 if (GET_CODE (i2) == JUMP_INSN)
7636 /* If DST is still live at CURRENT_INSN, check if it is used for
7637 any reload. Note that even if CURRENT_INSN sets DST, we still
7638 have to check the reloads. */
7639 if (i2 == current_insn)
7641 for (j = n_reloads - 1; j >= 0; j--)
7642 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7643 || reload_override_in[j] == dst)
7645 /* ??? We can't finish the loop here, because dst might be
7646 allocated to a pseudo in this block if no reload in this
7647 block needs any of the clsses containing DST - see
7648 spill_hard_reg. There is no easy way to tell this, so we
7649 have to scan till the end of the basic block. */
7651 if (reg_set_p (dst, PATTERN (i2)))
7655 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7656 reg_reloaded_contents[REGNO (dst)] = -1;
7657 /* Can't use delete_insn here because PREV might be a basic block head. */
7658 PUT_CODE (prev, NOTE);
7659 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7660 NOTE_SOURCE_FILE (prev) = 0;
7663 /* Output reload-insns to reload VALUE into RELOADREG.
7664 VALUE is an autoincrement or autodecrement RTX whose operand
7665 is a register or memory location;
7666 so reloading involves incrementing that location.
7667 IN is either identical to VALUE, or some cheaper place to reload from.
7669 INC_AMOUNT is the number to increment or decrement by (always positive).
7670 This cannot be deduced from VALUE.
7672 Return the instruction that stores into RELOADREG. */
7675 inc_for_reload (reloadreg, in, value, inc_amount)
7680 /* REG or MEM to be copied and incremented. */
7681 rtx incloc = XEXP (value, 0);
7682 /* Nonzero if increment after copying. */
7683 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7689 rtx real_in = in == value ? XEXP (in, 0) : in;
7691 /* No hard register is equivalent to this register after
7692 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7693 we could inc/dec that register as well (maybe even using it for
7694 the source), but I'm not sure it's worth worrying about. */
7695 if (GET_CODE (incloc) == REG)
7696 reg_last_reload_reg[REGNO (incloc)] = 0;
7698 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7699 inc_amount = - inc_amount;
7701 inc = GEN_INT (inc_amount);
7703 /* If this is post-increment, first copy the location to the reload reg. */
7704 if (post && real_in != reloadreg)
7705 emit_insn (gen_move_insn (reloadreg, real_in));
7709 /* See if we can directly increment INCLOC. Use a method similar to
7710 that in gen_reload. */
7712 last = get_last_insn ();
7713 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7714 gen_rtx_PLUS (GET_MODE (incloc),
7717 code = recog_memoized (add_insn);
7720 extract_insn (add_insn);
7721 if (constrain_operands (1))
7723 /* If this is a pre-increment and we have incremented the value
7724 where it lives, copy the incremented value to RELOADREG to
7725 be used as an address. */
7728 emit_insn (gen_move_insn (reloadreg, incloc));
7733 delete_insns_since (last);
7736 /* If couldn't do the increment directly, must increment in RELOADREG.
7737 The way we do this depends on whether this is pre- or post-increment.
7738 For pre-increment, copy INCLOC to the reload register, increment it
7739 there, then save back. */
7743 if (in != reloadreg)
7744 emit_insn (gen_move_insn (reloadreg, real_in));
7745 emit_insn (gen_add2_insn (reloadreg, inc));
7746 store = emit_insn (gen_move_insn (incloc, reloadreg));
7751 Because this might be a jump insn or a compare, and because RELOADREG
7752 may not be available after the insn in an input reload, we must do
7753 the incrementation before the insn being reloaded for.
7755 We have already copied IN to RELOADREG. Increment the copy in
7756 RELOADREG, save that back, then decrement RELOADREG so it has
7757 the original value. */
7759 emit_insn (gen_add2_insn (reloadreg, inc));
7760 store = emit_insn (gen_move_insn (incloc, reloadreg));
7761 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7767 /* Return 1 if we are certain that the constraint-string STRING allows
7768 the hard register REG. Return 0 if we can't be sure of this. */
7771 constraint_accepts_reg_p (string, reg)
7776 int regno = true_regnum (reg);
7779 /* Initialize for first alternative. */
7781 /* Check that each alternative contains `g' or `r'. */
7783 switch (c = *string++)
7786 /* If an alternative lacks `g' or `r', we lose. */
7789 /* If an alternative lacks `g' or `r', we lose. */
7792 /* Initialize for next alternative. */
7797 /* Any general reg wins for this alternative. */
7798 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7802 /* Any reg in specified class wins for this alternative. */
7804 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7806 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7812 /* Return the number of places FIND appears within X, but don't count
7813 an occurrence if some SET_DEST is FIND. */
7816 count_occurrences (x, find)
7817 register rtx x, find;
7820 register enum rtx_code code;
7821 register const char *format_ptr;
7829 code = GET_CODE (x);
7844 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7848 if (SET_DEST (x) == find)
7849 return count_occurrences (SET_SRC (x), find);
7856 format_ptr = GET_RTX_FORMAT (code);
7859 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7861 switch (*format_ptr++)
7864 count += count_occurrences (XEXP (x, i), find);
7868 if (XVEC (x, i) != NULL)
7870 for (j = 0; j < XVECLEN (x, i); j++)
7871 count += count_occurrences (XVECEXP (x, i, j), find);
7879 /* INSN is a no-op; delete it.
7880 If this sets the return value of the function, we must keep a USE around,
7881 in case this is in a different basic block than the final USE. Otherwise,
7882 we could loose important register lifeness information on
7883 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7884 spills: subsequent passes assume that spill registers are dead at the end
7886 VALUE must be the return value in such a case, NULL otherwise. */
7888 reload_cse_delete_noop_set (insn, value)
7893 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7894 INSN_CODE (insn) = -1;
7895 REG_NOTES (insn) = NULL_RTX;
7899 PUT_CODE (insn, NOTE);
7900 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7901 NOTE_SOURCE_FILE (insn) = 0;
7905 /* See whether a single set SET is a noop. */
7907 reload_cse_noop_set_p (set)
7910 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7913 /* Try to simplify INSN. */
7915 reload_cse_simplify (insn)
7918 rtx body = PATTERN (insn);
7920 if (GET_CODE (body) == SET)
7923 if (reload_cse_noop_set_p (body))
7925 rtx value = SET_DEST (body);
7926 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7928 reload_cse_delete_noop_set (insn, value);
7932 /* It's not a no-op, but we can try to simplify it. */
7933 count += reload_cse_simplify_set (body, insn);
7936 apply_change_group ();
7938 reload_cse_simplify_operands (insn);
7940 else if (GET_CODE (body) == PARALLEL)
7944 rtx value = NULL_RTX;
7946 /* If every action in a PARALLEL is a noop, we can delete
7947 the entire PARALLEL. */
7948 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7950 rtx part = XVECEXP (body, 0, i);
7951 if (GET_CODE (part) == SET)
7953 if (! reload_cse_noop_set_p (part))
7955 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7959 value = SET_DEST (part);
7962 else if (GET_CODE (part) != CLOBBER)
7968 reload_cse_delete_noop_set (insn, value);
7969 /* We're done with this insn. */
7973 /* It's not a no-op, but we can try to simplify it. */
7974 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7975 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7976 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7979 apply_change_group ();
7981 reload_cse_simplify_operands (insn);
7985 /* Do a very simple CSE pass over the hard registers.
7987 This function detects no-op moves where we happened to assign two
7988 different pseudo-registers to the same hard register, and then
7989 copied one to the other. Reload will generate a useless
7990 instruction copying a register to itself.
7992 This function also detects cases where we load a value from memory
7993 into two different registers, and (if memory is more expensive than
7994 registers) changes it to simply copy the first register into the
7997 Another optimization is performed that scans the operands of each
7998 instruction to see whether the value is already available in a
7999 hard register. It then replaces the operand with the hard register
8000 if possible, much like an optional reload would. */
8003 reload_cse_regs_1 (first)
8009 init_alias_analysis ();
8011 for (insn = first; insn; insn = NEXT_INSN (insn))
8013 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
8014 reload_cse_simplify (insn);
8016 cselib_process_insn (insn);
8020 end_alias_analysis ();
8024 /* Call cse / combine like post-reload optimization phases.
8025 FIRST is the first instruction. */
8027 reload_cse_regs (first)
8030 reload_cse_regs_1 (first);
8032 reload_cse_move2add (first);
8033 if (flag_expensive_optimizations)
8034 reload_cse_regs_1 (first);
8037 /* Try to simplify a single SET instruction. SET is the set pattern.
8038 INSN is the instruction it came from.
8039 This function only handles one case: if we set a register to a value
8040 which is not a register, we try to find that value in some other register
8041 and change the set into a register copy. */
8044 reload_cse_simplify_set (set, insn)
8051 enum reg_class dclass;
8054 struct elt_loc_list *l;
8056 dreg = true_regnum (SET_DEST (set));
8060 src = SET_SRC (set);
8061 if (side_effects_p (src) || true_regnum (src) >= 0)
8064 dclass = REGNO_REG_CLASS (dreg);
8066 /* If memory loads are cheaper than register copies, don't change them. */
8067 if (GET_CODE (src) == MEM)
8068 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8069 else if (CONSTANT_P (src))
8070 old_cost = rtx_cost (src, SET);
8071 else if (GET_CODE (src) == REG)
8072 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8075 old_cost = rtx_cost (src, SET);
8077 val = cselib_lookup (src, VOIDmode, 0);
8080 for (l = val->locs; l; l = l->next)
8083 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8084 this_cost = rtx_cost (l->loc, SET);
8085 else if (GET_CODE (l->loc) == REG)
8086 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8090 /* If equal costs, prefer registers over anything else. That tends to
8091 lead to smaller instructions on some machines. */
8092 if ((this_cost < old_cost
8093 || (this_cost == old_cost
8094 && GET_CODE (l->loc) == REG
8095 && GET_CODE (SET_SRC (set)) != REG))
8096 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8097 old_cost = this_cost, did_change = 1;
8103 /* Try to replace operands in INSN with equivalent values that are already
8104 in registers. This can be viewed as optional reloading.
8106 For each non-register operand in the insn, see if any hard regs are
8107 known to be equivalent to that operand. Record the alternatives which
8108 can accept these hard registers. Among all alternatives, select the
8109 ones which are better or equal to the one currently matching, where
8110 "better" is in terms of '?' and '!' constraints. Among the remaining
8111 alternatives, select the one which replaces most operands with
8115 reload_cse_simplify_operands (insn)
8120 /* For each operand, all registers that are equivalent to it. */
8121 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8123 const char *constraints[MAX_RECOG_OPERANDS];
8125 /* Vector recording how bad an alternative is. */
8126 int *alternative_reject;
8127 /* Vector recording how many registers can be introduced by choosing
8128 this alternative. */
8129 int *alternative_nregs;
8130 /* Array of vectors recording, for each operand and each alternative,
8131 which hard register to substitute, or -1 if the operand should be
8133 int *op_alt_regno[MAX_RECOG_OPERANDS];
8134 /* Array of alternatives, sorted in order of decreasing desirability. */
8135 int *alternative_order;
8136 rtx reg = gen_rtx_REG (VOIDmode, -1);
8138 extract_insn (insn);
8140 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8143 /* Figure out which alternative currently matches. */
8144 if (! constrain_operands (1))
8145 fatal_insn_not_found (insn);
8147 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8148 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8149 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8150 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8151 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8153 /* For each operand, find out which regs are equivalent. */
8154 for (i = 0; i < recog_data.n_operands; i++)
8157 struct elt_loc_list *l;
8159 CLEAR_HARD_REG_SET (equiv_regs[i]);
8161 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8162 right, so avoid the problem here. */
8163 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8166 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8170 for (l = v->locs; l; l = l->next)
8171 if (GET_CODE (l->loc) == REG)
8172 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8175 for (i = 0; i < recog_data.n_operands; i++)
8177 enum machine_mode mode;
8181 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8182 for (j = 0; j < recog_data.n_alternatives; j++)
8183 op_alt_regno[i][j] = -1;
8185 p = constraints[i] = recog_data.constraints[i];
8186 mode = recog_data.operand_mode[i];
8188 /* Add the reject values for each alternative given by the constraints
8189 for this operand. */
8197 alternative_reject[j] += 3;
8199 alternative_reject[j] += 300;
8202 /* We won't change operands which are already registers. We
8203 also don't want to modify output operands. */
8204 regno = true_regnum (recog_data.operand[i]);
8206 || constraints[i][0] == '='
8207 || constraints[i][0] == '+')
8210 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8212 int class = (int) NO_REGS;
8214 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8217 REGNO (reg) = regno;
8218 PUT_MODE (reg, mode);
8220 /* We found a register equal to this operand. Now look for all
8221 alternatives that can accept this register and have not been
8222 assigned a register they can use yet. */
8231 case '=': case '+': case '?':
8232 case '#': case '&': case '!':
8234 case '0': case '1': case '2': case '3': case '4':
8235 case '5': case '6': case '7': case '8': case '9':
8236 case 'm': case '<': case '>': case 'V': case 'o':
8237 case 'E': case 'F': case 'G': case 'H':
8238 case 's': case 'i': case 'n':
8239 case 'I': case 'J': case 'K': case 'L':
8240 case 'M': case 'N': case 'O': case 'P':
8241 #ifdef EXTRA_CONSTRAINT
8242 case 'Q': case 'R': case 'S': case 'T': case 'U':
8245 /* These don't say anything we care about. */
8249 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8254 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8257 case ',': case '\0':
8258 /* See if REGNO fits this alternative, and set it up as the
8259 replacement register if we don't have one for this
8260 alternative yet and the operand being replaced is not
8261 a cheap CONST_INT. */
8262 if (op_alt_regno[i][j] == -1
8263 && reg_fits_class_p (reg, class, 0, mode)
8264 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8265 || (rtx_cost (recog_data.operand[i], SET)
8266 > rtx_cost (reg, SET))))
8268 alternative_nregs[j]++;
8269 op_alt_regno[i][j] = regno;
8281 /* Record all alternatives which are better or equal to the currently
8282 matching one in the alternative_order array. */
8283 for (i = j = 0; i < recog_data.n_alternatives; i++)
8284 if (alternative_reject[i] <= alternative_reject[which_alternative])
8285 alternative_order[j++] = i;
8286 recog_data.n_alternatives = j;
8288 /* Sort it. Given a small number of alternatives, a dumb algorithm
8289 won't hurt too much. */
8290 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8293 int best_reject = alternative_reject[alternative_order[i]];
8294 int best_nregs = alternative_nregs[alternative_order[i]];
8297 for (j = i + 1; j < recog_data.n_alternatives; j++)
8299 int this_reject = alternative_reject[alternative_order[j]];
8300 int this_nregs = alternative_nregs[alternative_order[j]];
8302 if (this_reject < best_reject
8303 || (this_reject == best_reject && this_nregs < best_nregs))
8306 best_reject = this_reject;
8307 best_nregs = this_nregs;
8311 tmp = alternative_order[best];
8312 alternative_order[best] = alternative_order[i];
8313 alternative_order[i] = tmp;
8316 /* Substitute the operands as determined by op_alt_regno for the best
8318 j = alternative_order[0];
8320 for (i = 0; i < recog_data.n_operands; i++)
8322 enum machine_mode mode = recog_data.operand_mode[i];
8323 if (op_alt_regno[i][j] == -1)
8326 validate_change (insn, recog_data.operand_loc[i],
8327 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8330 for (i = recog_data.n_dups - 1; i >= 0; i--)
8332 int op = recog_data.dup_num[i];
8333 enum machine_mode mode = recog_data.operand_mode[op];
8335 if (op_alt_regno[op][j] == -1)
8338 validate_change (insn, recog_data.dup_loc[i],
8339 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8342 return apply_change_group ();
8345 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8347 This code might also be useful when reload gave up on reg+reg addresssing
8348 because of clashes between the return register and INDEX_REG_CLASS. */
8350 /* The maximum number of uses of a register we can keep track of to
8351 replace them with reg+reg addressing. */
8352 #define RELOAD_COMBINE_MAX_USES 6
8354 /* INSN is the insn where a register has ben used, and USEP points to the
8355 location of the register within the rtl. */
8356 struct reg_use { rtx insn, *usep; };
8358 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8359 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8360 indicates where it becomes live again.
8361 Otherwise, USE_INDEX is the index of the last encountered use of the
8362 register (which is first among these we have seen since we scan backwards),
8363 OFFSET contains the constant offset that is added to the register in
8364 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8365 last, of these uses.
8366 STORE_RUID is always meaningful if we only want to use a value in a
8367 register in a different place: it denotes the next insn in the insn
8368 stream (i.e. the last ecountered) that sets or clobbers the register. */
8371 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8376 } reg_state[FIRST_PSEUDO_REGISTER];
8378 /* Reverse linear uid. This is increased in reload_combine while scanning
8379 the instructions from last to first. It is used to set last_label_ruid
8380 and the store_ruid / use_ruid fields in reg_state. */
8381 static int reload_combine_ruid;
8383 #define LABEL_LIVE(LABEL) \
8384 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8390 int first_index_reg = 1, last_index_reg = 0;
8393 int last_label_ruid;
8394 int min_labelno, n_labels;
8395 HARD_REG_SET ever_live_at_start, *label_live;
8397 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8398 reload has already used it where appropriate, so there is no use in
8399 trying to generate it now. */
8400 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8403 /* To avoid wasting too much time later searching for an index register,
8404 determine the minimum and maximum index register numbers. */
8405 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8406 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8408 if (! first_index_reg)
8409 first_index_reg = r;
8414 /* If no index register is available, we can quit now. */
8415 if (first_index_reg > last_index_reg)
8418 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8419 information is a bit fuzzy immediately after reload, but it's
8420 still good enough to determine which registers are live at a jump
8422 min_labelno = get_first_label_num ();
8423 n_labels = max_label_num () - min_labelno;
8424 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8425 CLEAR_HARD_REG_SET (ever_live_at_start);
8427 for (i = n_basic_blocks - 1; i >= 0; i--)
8429 insn = BLOCK_HEAD (i);
8430 if (GET_CODE (insn) == CODE_LABEL)
8434 REG_SET_TO_HARD_REG_SET (live,
8435 BASIC_BLOCK (i)->global_live_at_start);
8436 compute_use_by_pseudos (&live,
8437 BASIC_BLOCK (i)->global_live_at_start);
8438 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8439 IOR_HARD_REG_SET (ever_live_at_start, live);
8443 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8444 last_label_ruid = reload_combine_ruid = 0;
8445 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8447 reg_state[r].store_ruid = reload_combine_ruid;
8449 reg_state[r].use_index = -1;
8451 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8454 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8458 /* We cannot do our optimization across labels. Invalidating all the use
8459 information we have would be costly, so we just note where the label
8460 is and then later disable any optimization that would cross it. */
8461 if (GET_CODE (insn) == CODE_LABEL)
8462 last_label_ruid = reload_combine_ruid;
8463 else if (GET_CODE (insn) == BARRIER)
8464 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8465 if (! fixed_regs[r])
8466 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8468 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8471 reload_combine_ruid++;
8473 /* Look for (set (REGX) (CONST_INT))
8474 (set (REGX) (PLUS (REGX) (REGY)))
8476 ... (MEM (REGX)) ...
8478 (set (REGZ) (CONST_INT))
8480 ... (MEM (PLUS (REGZ) (REGY)))... .
8482 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8483 and that we know all uses of REGX before it dies. */
8484 set = single_set (insn);
8486 && GET_CODE (SET_DEST (set)) == REG
8487 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8488 GET_MODE (SET_DEST (set)))
8490 && GET_CODE (SET_SRC (set)) == PLUS
8491 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8492 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8493 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8495 rtx reg = SET_DEST (set);
8496 rtx plus = SET_SRC (set);
8497 rtx base = XEXP (plus, 1);
8498 rtx prev = prev_nonnote_insn (insn);
8499 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8500 unsigned int regno = REGNO (reg);
8501 rtx const_reg = NULL_RTX;
8502 rtx reg_sum = NULL_RTX;
8504 /* Now, we need an index register.
8505 We'll set index_reg to this index register, const_reg to the
8506 register that is to be loaded with the constant
8507 (denoted as REGZ in the substitution illustration above),
8508 and reg_sum to the register-register that we want to use to
8509 substitute uses of REG (typically in MEMs) with.
8510 First check REG and BASE for being index registers;
8511 we can use them even if they are not dead. */
8512 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8513 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8521 /* Otherwise, look for a free index register. Since we have
8522 checked above that neiter REG nor BASE are index registers,
8523 if we find anything at all, it will be different from these
8525 for (i = first_index_reg; i <= last_index_reg; i++)
8527 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8529 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8530 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8531 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8533 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8535 const_reg = index_reg;
8536 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8542 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8543 (REGY), i.e. BASE, is not clobbered before the last use we'll
8546 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8547 && rtx_equal_p (SET_DEST (prev_set), reg)
8548 && reg_state[regno].use_index >= 0
8549 && (reg_state[REGNO (base)].store_ruid
8550 <= reg_state[regno].use_ruid)
8555 /* Change destination register and, if necessary, the
8556 constant value in PREV, the constant loading instruction. */
8557 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8558 if (reg_state[regno].offset != const0_rtx)
8559 validate_change (prev,
8560 &SET_SRC (prev_set),
8561 GEN_INT (INTVAL (SET_SRC (prev_set))
8562 + INTVAL (reg_state[regno].offset)),
8565 /* Now for every use of REG that we have recorded, replace REG
8567 for (i = reg_state[regno].use_index;
8568 i < RELOAD_COMBINE_MAX_USES; i++)
8569 validate_change (reg_state[regno].reg_use[i].insn,
8570 reg_state[regno].reg_use[i].usep,
8573 if (apply_change_group ())
8577 /* Delete the reg-reg addition. */
8578 PUT_CODE (insn, NOTE);
8579 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8580 NOTE_SOURCE_FILE (insn) = 0;
8582 if (reg_state[regno].offset != const0_rtx)
8583 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8585 for (np = ®_NOTES (prev); *np; )
8587 if (REG_NOTE_KIND (*np) == REG_EQUAL
8588 || REG_NOTE_KIND (*np) == REG_EQUIV)
8589 *np = XEXP (*np, 1);
8591 np = &XEXP (*np, 1);
8594 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8595 reg_state[REGNO (const_reg)].store_ruid
8596 = reload_combine_ruid;
8602 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8604 if (GET_CODE (insn) == CALL_INSN)
8608 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8609 if (call_used_regs[r])
8611 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8612 reg_state[r].store_ruid = reload_combine_ruid;
8615 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8616 link = XEXP (link, 1))
8617 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8619 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8621 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8623 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8624 reg_state[regno].store_ruid = reload_combine_ruid;
8627 reg_state[regno].use_index = -1;
8631 else if (GET_CODE (insn) == JUMP_INSN
8632 && GET_CODE (PATTERN (insn)) != RETURN)
8634 /* Non-spill registers might be used at the call destination in
8635 some unknown fashion, so we have to mark the unknown use. */
8638 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8639 && JUMP_LABEL (insn))
8640 live = &LABEL_LIVE (JUMP_LABEL (insn));
8642 live = &ever_live_at_start;
8644 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8645 if (TEST_HARD_REG_BIT (*live, i))
8646 reg_state[i].use_index = -1;
8649 reload_combine_note_use (&PATTERN (insn), insn);
8650 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8652 if (REG_NOTE_KIND (note) == REG_INC
8653 && GET_CODE (XEXP (note, 0)) == REG)
8655 int regno = REGNO (XEXP (note, 0));
8657 reg_state[regno].store_ruid = reload_combine_ruid;
8658 reg_state[regno].use_index = -1;
8666 /* Check if DST is a register or a subreg of a register; if it is,
8667 update reg_state[regno].store_ruid and reg_state[regno].use_index
8668 accordingly. Called via note_stores from reload_combine. */
8671 reload_combine_note_store (dst, set, data)
8673 void *data ATTRIBUTE_UNUSED;
8677 enum machine_mode mode = GET_MODE (dst);
8679 if (GET_CODE (dst) == SUBREG)
8681 regno = SUBREG_WORD (dst);
8682 dst = SUBREG_REG (dst);
8684 if (GET_CODE (dst) != REG)
8686 regno += REGNO (dst);
8688 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8689 careful with registers / register parts that are not full words.
8691 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8692 if (GET_CODE (set) != SET
8693 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8694 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8695 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8697 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8699 reg_state[i].use_index = -1;
8700 reg_state[i].store_ruid = reload_combine_ruid;
8705 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8707 reg_state[i].store_ruid = reload_combine_ruid;
8708 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8713 /* XP points to a piece of rtl that has to be checked for any uses of
8715 *XP is the pattern of INSN, or a part of it.
8716 Called from reload_combine, and recursively by itself. */
8718 reload_combine_note_use (xp, insn)
8722 enum rtx_code code = x->code;
8725 rtx offset = const0_rtx; /* For the REG case below. */
8730 if (GET_CODE (SET_DEST (x)) == REG)
8732 reload_combine_note_use (&SET_SRC (x), insn);
8738 /* If this is the USE of a return value, we can't change it. */
8739 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8741 /* Mark the return register as used in an unknown fashion. */
8742 rtx reg = XEXP (x, 0);
8743 int regno = REGNO (reg);
8744 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8746 while (--nregs >= 0)
8747 reg_state[regno + nregs].use_index = -1;
8753 if (GET_CODE (SET_DEST (x)) == REG)
8758 /* We are interested in (plus (reg) (const_int)) . */
8759 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
8761 offset = XEXP (x, 1);
8766 int regno = REGNO (x);
8770 /* Some spurious USEs of pseudo registers might remain.
8771 Just ignore them. */
8772 if (regno >= FIRST_PSEUDO_REGISTER)
8775 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8777 /* We can't substitute into multi-hard-reg uses. */
8780 while (--nregs >= 0)
8781 reg_state[regno + nregs].use_index = -1;
8785 /* If this register is already used in some unknown fashion, we
8787 If we decrement the index from zero to -1, we can't store more
8788 uses, so this register becomes used in an unknown fashion. */
8789 use_index = --reg_state[regno].use_index;
8793 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8795 /* We have found another use for a register that is already
8796 used later. Check if the offsets match; if not, mark the
8797 register as used in an unknown fashion. */
8798 if (! rtx_equal_p (offset, reg_state[regno].offset))
8800 reg_state[regno].use_index = -1;
8806 /* This is the first use of this register we have seen since we
8807 marked it as dead. */
8808 reg_state[regno].offset = offset;
8809 reg_state[regno].use_ruid = reload_combine_ruid;
8811 reg_state[regno].reg_use[use_index].insn = insn;
8812 reg_state[regno].reg_use[use_index].usep = xp;
8820 /* Recursively process the components of X. */
8821 fmt = GET_RTX_FORMAT (code);
8822 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8825 reload_combine_note_use (&XEXP (x, i), insn);
8826 else if (fmt[i] == 'E')
8828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8829 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8834 /* See if we can reduce the cost of a constant by replacing a move with
8836 /* We cannot do our optimization across labels. Invalidating all the
8837 information about register contents we have would be costly, so we
8838 use last_label_luid (local variable of reload_cse_move2add) to note
8839 where the label is and then later disable any optimization that would
8841 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8842 reg_set_luid[n] is larger than last_label_luid[n] . */
8843 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8845 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8846 reg_mode[n] to be valid.
8847 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8848 has been set to reg_offset[n] in mode reg_mode[n] .
8849 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8850 register n has been set to the sum of reg_offset[n] and register
8851 reg_base_reg[n], calculated in mode reg_mode[n] . */
8852 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8853 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8854 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8856 /* move2add_luid is linearily increased while scanning the instructions
8857 from first to last. It is used to set reg_set_luid in
8858 reload_cse_move2add and move2add_note_store. */
8859 static int move2add_luid;
8861 /* Generate a CONST_INT and force it in the range of MODE. */
8864 gen_mode_int (mode, value)
8865 enum machine_mode mode;
8866 HOST_WIDE_INT value;
8868 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8869 int width = GET_MODE_BITSIZE (mode);
8871 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8873 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8874 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8875 cval |= (HOST_WIDE_INT) -1 << width;
8877 return GEN_INT (cval);
8881 reload_cse_move2add (first)
8886 int last_label_luid;
8888 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
8889 reg_set_luid[i] = 0;
8891 last_label_luid = 0;
8893 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8897 if (GET_CODE (insn) == CODE_LABEL)
8898 last_label_luid = move2add_luid;
8899 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8901 pat = PATTERN (insn);
8902 /* For simplicity, we only perform this optimization on
8903 straightforward SETs. */
8904 if (GET_CODE (pat) == SET
8905 && GET_CODE (SET_DEST (pat)) == REG)
8907 rtx reg = SET_DEST (pat);
8908 int regno = REGNO (reg);
8909 rtx src = SET_SRC (pat);
8911 /* Check if we have valid information on the contents of this
8912 register in the mode of REG. */
8913 /* ??? We don't know how zero / sign extension is handled, hence
8914 we can't go from a narrower to a wider mode. */
8915 if (reg_set_luid[regno] > last_label_luid
8916 && ((GET_MODE_SIZE (GET_MODE (reg))
8917 == GET_MODE_SIZE (reg_mode[regno]))
8918 || ((GET_MODE_SIZE (GET_MODE (reg))
8919 <= GET_MODE_SIZE (reg_mode[regno]))
8920 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8921 GET_MODE_BITSIZE (reg_mode[regno]))))
8922 && GET_CODE (reg_offset[regno]) == CONST_INT)
8924 /* Try to transform (set (REGX) (CONST_INT A))
8926 (set (REGX) (CONST_INT B))
8928 (set (REGX) (CONST_INT A))
8930 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8932 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8936 = gen_mode_int (GET_MODE (reg),
8937 INTVAL (src) - INTVAL (reg_offset[regno]));
8938 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8939 use (set (reg) (reg)) instead.
8940 We don't delete this insn, nor do we convert it into a
8941 note, to avoid losing register notes or the return
8942 value flag. jump2 already knowns how to get rid of
8944 if (new_src == const0_rtx)
8945 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8946 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8947 && have_add2_insn (GET_MODE (reg)))
8948 success = validate_change (insn, &PATTERN (insn),
8949 gen_add2_insn (reg, new_src), 0);
8950 reg_set_luid[regno] = move2add_luid;
8951 reg_mode[regno] = GET_MODE (reg);
8952 reg_offset[regno] = src;
8956 /* Try to transform (set (REGX) (REGY))
8957 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8960 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8963 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8965 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8966 else if (GET_CODE (src) == REG
8967 && reg_base_reg[regno] == (int) REGNO (src)
8968 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8970 rtx next = next_nonnote_insn (insn);
8973 set = single_set (next);
8976 && SET_DEST (set) == reg
8977 && GET_CODE (SET_SRC (set)) == PLUS
8978 && XEXP (SET_SRC (set), 0) == reg
8979 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8981 rtx src3 = XEXP (SET_SRC (set), 1);
8983 = gen_mode_int (GET_MODE (reg),
8985 - INTVAL (reg_offset[regno]));
8988 if (new_src == const0_rtx)
8989 /* See above why we create (set (reg) (reg)) here. */
8991 = validate_change (next, &SET_SRC (set), reg, 0);
8992 else if ((rtx_cost (new_src, PLUS)
8993 < 2 + rtx_cost (src3, SET))
8994 && have_add2_insn (GET_MODE (reg)))
8996 = validate_change (next, &PATTERN (next),
8997 gen_add2_insn (reg, new_src), 0);
9000 /* INSN might be the first insn in a basic block
9001 if the preceding insn is a conditional jump
9002 or a possible-throwing call. */
9003 PUT_CODE (insn, NOTE);
9004 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9005 NOTE_SOURCE_FILE (insn) = 0;
9008 reg_set_luid[regno] = move2add_luid;
9009 reg_mode[regno] = GET_MODE (reg);
9010 reg_offset[regno] = src3;
9017 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9019 if (REG_NOTE_KIND (note) == REG_INC
9020 && GET_CODE (XEXP (note, 0)) == REG)
9022 /* Indicate that this register has been recently written to,
9023 but the exact contents are not available. */
9024 int regno = REGNO (XEXP (note, 0));
9025 if (regno < FIRST_PSEUDO_REGISTER)
9027 reg_set_luid[regno] = move2add_luid;
9028 reg_offset[regno] = note;
9032 note_stores (PATTERN (insn), move2add_note_store, NULL);
9033 /* If this is a CALL_INSN, all call used registers are stored with
9035 if (GET_CODE (insn) == CALL_INSN)
9037 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9039 if (call_used_regs[i])
9041 reg_set_luid[i] = move2add_luid;
9042 reg_offset[i] = insn; /* Invalidate contents. */
9049 /* SET is a SET or CLOBBER that sets DST.
9050 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9051 Called from reload_cse_move2add via note_stores. */
9054 move2add_note_store (dst, set, data)
9056 void *data ATTRIBUTE_UNUSED;
9058 unsigned int regno = 0;
9060 enum machine_mode mode = GET_MODE (dst);
9062 if (GET_CODE (dst) == SUBREG)
9064 regno = SUBREG_WORD (dst);
9065 dst = SUBREG_REG (dst);
9068 if (GET_CODE (dst) != REG)
9071 regno += REGNO (dst);
9073 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9074 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9075 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9076 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9078 rtx src = SET_SRC (set);
9080 reg_mode[regno] = mode;
9081 switch (GET_CODE (src))
9085 rtx src0 = XEXP (src, 0);
9087 if (GET_CODE (src0) == REG)
9089 if (REGNO (src0) != regno
9090 || reg_offset[regno] != const0_rtx)
9092 reg_base_reg[regno] = REGNO (src0);
9093 reg_set_luid[regno] = move2add_luid;
9096 reg_offset[regno] = XEXP (src, 1);
9100 reg_set_luid[regno] = move2add_luid;
9101 reg_offset[regno] = set; /* Invalidate contents. */
9106 reg_base_reg[regno] = REGNO (SET_SRC (set));
9107 reg_offset[regno] = const0_rtx;
9108 reg_set_luid[regno] = move2add_luid;
9112 reg_base_reg[regno] = -1;
9113 reg_offset[regno] = SET_SRC (set);
9114 reg_set_luid[regno] = move2add_luid;
9120 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9122 for (i = regno; i < endregno; i++)
9124 /* Indicate that this register has been recently written to,
9125 but the exact contents are not available. */
9126 reg_set_luid[i] = move2add_luid;
9127 reg_offset[i] = dst;
9134 add_auto_inc_notes (insn, x)
9138 enum rtx_code code = GET_CODE (x);
9142 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9145 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9149 /* Scan all the operand sub-expressions. */
9150 fmt = GET_RTX_FORMAT (code);
9151 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9154 add_auto_inc_notes (insn, XEXP (x, i));
9155 else if (fmt[i] == 'E')
9156 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9157 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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