1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Indexed by pseudo reg number N,
208 says may not delete stores into the real (memory) home of pseudo N.
209 This is set if we already substituted a memory equivalent in some uses,
210 which happens when we have to eliminate the fp from it. */
211 static char *cannot_omit_stores;
213 /* Nonzero if indirect addressing is supported on the machine; this means
214 that spilling (REG n) does not require reloading it into a register in
215 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
216 value indicates the level of indirect addressing supported, e.g., two
217 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
220 static char spill_indirect_levels;
222 /* Nonzero if indirect addressing is supported when the innermost MEM is
223 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
224 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
245 char *basic_block_needs[N_REG_CLASSES];
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* The register class to use for a base register when reloading an
257 address. This is normally BASE_REG_CLASS, but it may be different
258 when using SMALL_REGISTER_CLASSES and passing parameters in
260 enum reg_class reload_address_base_reg_class;
262 /* The register class to use for an index register when reloading an
263 address. This is normally INDEX_REG_CLASS, but it may be different
264 when using SMALL_REGISTER_CLASSES and passing parameters in
266 enum reg_class reload_address_index_reg_class;
268 /* Set to 1 while reload_as_needed is operating.
269 Required by some machines to handle any generated moves differently. */
271 int reload_in_progress = 0;
273 /* These arrays record the insn_code of insns that may be needed to
274 perform input and output reloads of special objects. They provide a
275 place to pass a scratch register. */
277 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
278 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
280 /* This obstack is used for allocation of rtl during register elimination.
281 The allocated storage can be freed once find_reloads has processed the
284 struct obstack reload_obstack;
285 char *reload_firstobj;
287 #define obstack_chunk_alloc xmalloc
288 #define obstack_chunk_free free
290 /* List of labels that must never be deleted. */
291 extern rtx forced_labels;
293 /* Allocation number table from global register allocation. */
294 extern int *reg_allocno;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
301 static struct elim_table
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int max_offset; /* Maximum offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If non-zero, we use a new copy of each
335 replacement result in any insns encountered. */
336 static int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
341 /* For each label, we record the offset of each elimination. If we reach
342 a label by more than one path and an offset differs, we cannot do the
343 elimination. This information is indexed by the number of the label.
344 The first table is an array of flags that records whether we have yet
345 encountered a label and the second table is an array of arrays, one
346 entry in the latter array for each elimination. */
348 static char *offsets_known_at;
349 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
351 /* Number of labels in the current function. */
353 static int num_labels;
355 struct hard_reg_n_uses { int regno; int uses; };
357 static int possible_group_p PROTO((int, int *));
358 static void count_possible_groups PROTO((int *, enum machine_mode *,
360 static int modes_equiv_for_class_p PROTO((enum machine_mode,
363 static void spill_failure PROTO((rtx));
364 static int new_spill_reg PROTO((int, int, int *, int *, int,
366 static void delete_dead_insn PROTO((rtx));
367 static void alter_reg PROTO((int, int));
368 static void mark_scratch_live PROTO((rtx));
369 static void set_label_offsets PROTO((rtx, rtx, int));
370 static int eliminate_regs_in_insn PROTO((rtx, int));
371 static void mark_not_eliminable PROTO((rtx, rtx));
372 static int spill_hard_reg PROTO((int, int, FILE *, int));
373 static void scan_paradoxical_subregs PROTO((rtx));
374 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
375 static void order_regs_for_reload PROTO((int));
376 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void reload_as_needed PROTO((rtx, int));
378 static void forget_old_reloads_1 PROTO((rtx, rtx));
379 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
380 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
382 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
384 static int reload_reg_free_p PROTO((int, int, enum reload_type));
385 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
386 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
387 static int reloads_conflict PROTO((int, int));
388 static int allocate_reload_reg PROTO((int, rtx, int, int));
389 static void choose_reload_regs PROTO((rtx, rtx));
390 static void merge_assigned_reloads PROTO((rtx));
391 static void emit_reload_insns PROTO((rtx));
392 static void delete_output_reload PROTO((rtx, int, rtx));
393 static void inc_for_reload PROTO((rtx, rtx, int));
394 static int constraint_accepts_reg_p PROTO((char *, rtx));
395 static int count_occurrences PROTO((rtx, rtx));
397 /* Initialize the reload pass once per compilation. */
404 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
405 Set spill_indirect_levels to the number of levels such addressing is
406 permitted, zero if it is not permitted at all. */
409 = gen_rtx (MEM, Pmode,
410 gen_rtx (PLUS, Pmode,
411 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
413 spill_indirect_levels = 0;
415 while (memory_address_p (QImode, tem))
417 spill_indirect_levels++;
418 tem = gen_rtx (MEM, Pmode, tem);
421 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
423 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
424 indirect_symref_ok = memory_address_p (QImode, tem);
426 /* See if reg+reg is a valid (and offsettable) address. */
428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
430 tem = gen_rtx (PLUS, Pmode,
431 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
432 gen_rtx (REG, Pmode, i));
433 /* This way, we make sure that reg+reg is an offsettable address. */
434 tem = plus_constant (tem, 4);
436 if (memory_address_p (QImode, tem))
438 double_reg_address_ok = 1;
443 /* Initialize obstack for our rtl allocation. */
444 gcc_obstack_init (&reload_obstack);
445 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
447 /* Decide which register class should be used when reloading
448 addresses. If we are using SMALL_REGISTER_CLASSES, and any
449 parameters are passed in registers, then we do not want to use
450 those registers when reloading an address. Otherwise, if a
451 function argument needs a reload, we may wind up clobbering
452 another argument to the function which was already computed. If
453 we find a subset class which simply avoids those registers, we
454 use it instead. ??? It would be better to only use the
455 restricted class when we actually are loading function arguments,
456 but that is hard to determine. */
457 reload_address_base_reg_class = BASE_REG_CLASS;
458 reload_address_index_reg_class = INDEX_REG_CLASS;
459 #ifdef SMALL_REGISTER_CLASSES
460 if (SMALL_REGISTER_CLASSES)
463 HARD_REG_SET base, index;
466 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
467 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
468 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
470 if (FUNCTION_ARG_REGNO_P (regno))
472 CLEAR_HARD_REG_BIT (base, regno);
473 CLEAR_HARD_REG_BIT (index, regno);
477 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
479 for (p = reg_class_subclasses[BASE_REG_CLASS];
480 *p != LIM_REG_CLASSES;
483 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
486 reload_address_base_reg_class = *p;
491 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
493 for (p = reg_class_subclasses[INDEX_REG_CLASS];
494 *p != LIM_REG_CLASSES;
497 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
500 reload_address_index_reg_class = *p;
505 #endif /* SMALL_REGISTER_CLASSES */
508 /* Main entry point for the reload pass.
510 FIRST is the first insn of the function being compiled.
512 GLOBAL nonzero means we were called from global_alloc
513 and should attempt to reallocate any pseudoregs that we
514 displace from hard regs we will use for reloads.
515 If GLOBAL is zero, we do not have enough information to do that,
516 so any pseudo reg that is spilled must go to the stack.
518 DUMPFILE is the global-reg debugging dump file stream, or 0.
519 If it is nonzero, messages are written to it to describe
520 which registers are seized as reload regs, which pseudo regs
521 are spilled from them, and where the pseudo regs are reallocated to.
523 Return value is nonzero if reload failed
524 and we must not do any more for this function. */
527 reload (first, global, dumpfile)
533 register int i, j, k;
535 register struct elim_table *ep;
537 int something_changed;
538 int something_needs_reloads;
539 int something_needs_elimination;
540 int new_basic_block_needs;
541 enum reg_class caller_save_spill_class = NO_REGS;
542 int caller_save_group_size = 1;
544 /* Nonzero means we couldn't get enough spill regs. */
547 /* The basic block number currently being processed for INSN. */
550 /* Make sure even insns with volatile mem refs are recognizable. */
553 /* Enable find_equiv_reg to distinguish insns made by reload. */
554 reload_first_uid = get_max_uid ();
556 for (i = 0; i < N_REG_CLASSES; i++)
557 basic_block_needs[i] = 0;
559 #ifdef SECONDARY_MEMORY_NEEDED
560 /* Initialize the secondary memory table. */
561 clear_secondary_mem ();
564 /* Remember which hard regs appear explicitly
565 before we merge into `regs_ever_live' the ones in which
566 pseudo regs have been allocated. */
567 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
569 /* We don't have a stack slot for any spill reg yet. */
570 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
571 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
573 /* Initialize the save area information for caller-save, in case some
577 /* Compute which hard registers are now in use
578 as homes for pseudo registers.
579 This is done here rather than (eg) in global_alloc
580 because this point is reached even if not optimizing. */
582 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
585 for (i = 0; i < scratch_list_length; i++)
587 mark_scratch_live (scratch_list[i]);
589 /* Make sure that the last insn in the chain
590 is not something that needs reloading. */
591 emit_note (NULL_PTR, NOTE_INSN_DELETED);
593 /* Find all the pseudo registers that didn't get hard regs
594 but do have known equivalent constants or memory slots.
595 These include parameters (known equivalent to parameter slots)
596 and cse'd or loop-moved constant memory addresses.
598 Record constant equivalents in reg_equiv_constant
599 so they will be substituted by find_reloads.
600 Record memory equivalents in reg_mem_equiv so they can
601 be substituted eventually by altering the REG-rtx's. */
603 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
604 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
605 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
606 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
607 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
608 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
609 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
610 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
611 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
612 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
613 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
614 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
615 cannot_omit_stores = (char *) alloca (max_regno);
616 bzero (cannot_omit_stores, max_regno);
618 #ifdef SMALL_REGISTER_CLASSES
619 if (SMALL_REGISTER_CLASSES)
620 CLEAR_HARD_REG_SET (forbidden_regs);
623 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
624 Also find all paradoxical subregs and find largest such for each pseudo.
625 On machines with small register classes, record hard registers that
626 are used for user variables. These can never be used for spills.
627 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
628 caller-saved registers must be marked live. */
630 for (insn = first; insn; insn = NEXT_INSN (insn))
632 rtx set = single_set (insn);
634 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
635 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
636 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
637 if (! call_used_regs[i])
638 regs_ever_live[i] = 1;
640 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
642 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
644 #ifdef LEGITIMATE_PIC_OPERAND_P
645 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
646 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
650 rtx x = XEXP (note, 0);
651 i = REGNO (SET_DEST (set));
652 if (i > LAST_VIRTUAL_REGISTER)
654 if (GET_CODE (x) == MEM)
655 reg_equiv_memory_loc[i] = x;
656 else if (CONSTANT_P (x))
658 if (LEGITIMATE_CONSTANT_P (x))
659 reg_equiv_constant[i] = x;
661 reg_equiv_memory_loc[i]
662 = force_const_mem (GET_MODE (SET_DEST (set)), x);
667 /* If this register is being made equivalent to a MEM
668 and the MEM is not SET_SRC, the equivalencing insn
669 is one with the MEM as a SET_DEST and it occurs later.
670 So don't mark this insn now. */
671 if (GET_CODE (x) != MEM
672 || rtx_equal_p (SET_SRC (set), x))
673 reg_equiv_init[i] = insn;
678 /* If this insn is setting a MEM from a register equivalent to it,
679 this is the equivalencing insn. */
680 else if (set && GET_CODE (SET_DEST (set)) == MEM
681 && GET_CODE (SET_SRC (set)) == REG
682 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
683 && rtx_equal_p (SET_DEST (set),
684 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
685 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
687 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
688 scan_paradoxical_subregs (PATTERN (insn));
691 /* Does this function require a frame pointer? */
693 frame_pointer_needed = (! flag_omit_frame_pointer
694 #ifdef EXIT_IGNORE_STACK
695 /* ?? If EXIT_IGNORE_STACK is set, we will not save
696 and restore sp for alloca. So we can't eliminate
697 the frame pointer in that case. At some point,
698 we should improve this by emitting the
699 sp-adjusting insns for this case. */
700 || (current_function_calls_alloca
701 && EXIT_IGNORE_STACK)
703 || FRAME_POINTER_REQUIRED);
707 /* Initialize the table of registers to eliminate. The way we do this
708 depends on how the eliminable registers were defined. */
709 #ifdef ELIMINABLE_REGS
710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
712 ep->can_eliminate = ep->can_eliminate_previous
713 = (CAN_ELIMINATE (ep->from, ep->to)
714 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
717 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
718 = ! frame_pointer_needed;
721 /* Count the number of eliminable registers and build the FROM and TO
722 REG rtx's. Note that code in gen_rtx will cause, e.g.,
723 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
724 We depend on this. */
725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
727 num_eliminable += ep->can_eliminate;
728 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
729 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
732 num_labels = max_label_num () - get_first_label_num ();
734 /* Allocate the tables used to store offset information at labels. */
735 offsets_known_at = (char *) alloca (num_labels);
737 = (int (*)[NUM_ELIMINABLE_REGS])
738 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
740 offsets_known_at -= get_first_label_num ();
741 offsets_at -= get_first_label_num ();
743 /* Alter each pseudo-reg rtx to contain its hard reg number.
744 Assign stack slots to the pseudos that lack hard regs or equivalents.
745 Do not touch virtual registers. */
747 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
750 /* If we have some registers we think can be eliminated, scan all insns to
751 see if there is an insn that sets one of these registers to something
752 other than itself plus a constant. If so, the register cannot be
753 eliminated. Doing this scan here eliminates an extra pass through the
754 main reload loop in the most common case where register elimination
756 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
757 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
758 || GET_CODE (insn) == CALL_INSN)
759 note_stores (PATTERN (insn), mark_not_eliminable);
761 #ifndef REGISTER_CONSTRAINTS
762 /* If all the pseudo regs have hard regs,
763 except for those that are never referenced,
764 we know that no reloads are needed. */
765 /* But that is not true if there are register constraints, since
766 in that case some pseudos might be in the wrong kind of hard reg. */
768 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
769 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
772 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
776 /* Compute the order of preference for hard registers to spill.
777 Store them by decreasing preference in potential_reload_regs. */
779 order_regs_for_reload (global);
781 /* So far, no hard regs have been spilled. */
783 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
784 spill_reg_order[i] = -1;
786 /* Initialize to -1, which means take the first spill register. */
789 /* On most machines, we can't use any register explicitly used in the
790 rtl as a spill register. But on some, we have to. Those will have
791 taken care to keep the life of hard regs as short as possible. */
793 #ifdef SMALL_REGISTER_CLASSES
794 if (! SMALL_REGISTER_CLASSES)
796 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
798 /* Spill any hard regs that we know we can't eliminate. */
799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
800 if (! ep->can_eliminate)
801 spill_hard_reg (ep->from, global, dumpfile, 1);
803 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
804 if (frame_pointer_needed)
805 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
809 for (i = 0; i < N_REG_CLASSES; i++)
811 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
812 bzero (basic_block_needs[i], n_basic_blocks);
815 /* From now on, we need to emit any moves without making new pseudos. */
816 reload_in_progress = 1;
818 /* This loop scans the entire function each go-round
819 and repeats until one repetition spills no additional hard regs. */
821 /* This flag is set when a pseudo reg is spilled,
822 to require another pass. Note that getting an additional reload
823 reg does not necessarily imply any pseudo reg was spilled;
824 sometimes we find a reload reg that no pseudo reg was allocated in. */
825 something_changed = 1;
826 /* This flag is set if there are any insns that require reloading. */
827 something_needs_reloads = 0;
828 /* This flag is set if there are any insns that require register
830 something_needs_elimination = 0;
831 while (something_changed)
835 /* For each class, number of reload regs needed in that class.
836 This is the maximum over all insns of the needs in that class
837 of the individual insn. */
838 int max_needs[N_REG_CLASSES];
839 /* For each class, size of group of consecutive regs
840 that is needed for the reloads of this class. */
841 int group_size[N_REG_CLASSES];
842 /* For each class, max number of consecutive groups needed.
843 (Each group contains group_size[CLASS] consecutive registers.) */
844 int max_groups[N_REG_CLASSES];
845 /* For each class, max number needed of regs that don't belong
846 to any of the groups. */
847 int max_nongroups[N_REG_CLASSES];
848 /* For each class, the machine mode which requires consecutive
849 groups of regs of that class.
850 If two different modes ever require groups of one class,
851 they must be the same size and equally restrictive for that class,
852 otherwise we can't handle the complexity. */
853 enum machine_mode group_mode[N_REG_CLASSES];
854 /* Record the insn where each maximum need is first found. */
855 rtx max_needs_insn[N_REG_CLASSES];
856 rtx max_groups_insn[N_REG_CLASSES];
857 rtx max_nongroups_insn[N_REG_CLASSES];
859 HOST_WIDE_INT starting_frame_size;
860 int previous_frame_pointer_needed = frame_pointer_needed;
861 static char *reg_class_names[] = REG_CLASS_NAMES;
863 something_changed = 0;
864 bzero ((char *) max_needs, sizeof max_needs);
865 bzero ((char *) max_groups, sizeof max_groups);
866 bzero ((char *) max_nongroups, sizeof max_nongroups);
867 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
868 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
869 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
870 bzero ((char *) group_size, sizeof group_size);
871 for (i = 0; i < N_REG_CLASSES; i++)
872 group_mode[i] = VOIDmode;
874 /* Keep track of which basic blocks are needing the reloads. */
877 /* Remember whether any element of basic_block_needs
878 changes from 0 to 1 in this pass. */
879 new_basic_block_needs = 0;
881 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
882 here because the stack size may be a part of the offset computation
883 for register elimination, and there might have been new stack slots
884 created in the last iteration of this loop. */
885 assign_stack_local (BLKmode, 0, 0);
887 starting_frame_size = get_frame_size ();
889 /* Reset all offsets on eliminable registers to their initial values. */
890 #ifdef ELIMINABLE_REGS
891 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
893 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
894 ep->previous_offset = ep->offset
895 = ep->max_offset = ep->initial_offset;
898 #ifdef INITIAL_FRAME_POINTER_OFFSET
899 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
901 if (!FRAME_POINTER_REQUIRED)
903 reg_eliminate[0].initial_offset = 0;
905 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
906 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
909 num_not_at_initial_offset = 0;
911 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
913 /* Set a known offset for each forced label to be at the initial offset
914 of each elimination. We do this because we assume that all
915 computed jumps occur from a location where each elimination is
916 at its initial offset. */
918 for (x = forced_labels; x; x = XEXP (x, 1))
920 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
922 /* For each pseudo register that has an equivalent location defined,
923 try to eliminate any eliminable registers (such as the frame pointer)
924 assuming initial offsets for the replacement register, which
927 If the resulting location is directly addressable, substitute
928 the MEM we just got directly for the old REG.
930 If it is not addressable but is a constant or the sum of a hard reg
931 and constant, it is probably not addressable because the constant is
932 out of range, in that case record the address; we will generate
933 hairy code to compute the address in a register each time it is
934 needed. Similarly if it is a hard register, but one that is not
935 valid as an address register.
937 If the location is not addressable, but does not have one of the
938 above forms, assign a stack slot. We have to do this to avoid the
939 potential of producing lots of reloads if, e.g., a location involves
940 a pseudo that didn't get a hard register and has an equivalent memory
941 location that also involves a pseudo that didn't get a hard register.
943 Perhaps at some point we will improve reload_when_needed handling
944 so this problem goes away. But that's very hairy. */
946 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
947 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
949 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
951 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
953 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
954 else if (CONSTANT_P (XEXP (x, 0))
955 || (GET_CODE (XEXP (x, 0)) == REG
956 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
957 || (GET_CODE (XEXP (x, 0)) == PLUS
958 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
959 && (REGNO (XEXP (XEXP (x, 0), 0))
960 < FIRST_PSEUDO_REGISTER)
961 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
962 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
965 /* Make a new stack slot. Then indicate that something
966 changed so we go back and recompute offsets for
967 eliminable registers because the allocation of memory
968 below might change some offset. reg_equiv_{mem,address}
969 will be set up for this pseudo on the next pass around
971 reg_equiv_memory_loc[i] = 0;
972 reg_equiv_init[i] = 0;
974 something_changed = 1;
978 /* If we allocated another pseudo to the stack, redo elimination
980 if (something_changed)
983 /* If caller-saves needs a group, initialize the group to include
984 the size and mode required for caller-saves. */
986 if (caller_save_group_size > 1)
988 group_mode[(int) caller_save_spill_class] = Pmode;
989 group_size[(int) caller_save_spill_class] = caller_save_group_size;
992 /* Compute the most additional registers needed by any instruction.
993 Collect information separately for each class of regs. */
995 for (insn = first; insn; insn = NEXT_INSN (insn))
997 if (global && this_block + 1 < n_basic_blocks
998 && insn == basic_block_head[this_block+1])
1001 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1002 might include REG_LABEL), we need to see what effects this
1003 has on the known offsets at labels. */
1005 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1006 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1007 && REG_NOTES (insn) != 0))
1008 set_label_offsets (insn, insn, 0);
1010 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1012 /* Nonzero means don't use a reload reg that overlaps
1013 the place where a function value can be returned. */
1014 rtx avoid_return_reg = 0;
1016 rtx old_body = PATTERN (insn);
1017 int old_code = INSN_CODE (insn);
1018 rtx old_notes = REG_NOTES (insn);
1019 int did_elimination = 0;
1021 /* To compute the number of reload registers of each class
1022 needed for an insn, we must simulate what choose_reload_regs
1023 can do. We do this by splitting an insn into an "input" and
1024 an "output" part. RELOAD_OTHER reloads are used in both.
1025 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1026 which must be live over the entire input section of reloads,
1027 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1028 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1031 The registers needed for output are RELOAD_OTHER and
1032 RELOAD_FOR_OUTPUT, which are live for the entire output
1033 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1034 reloads for each operand.
1036 The total number of registers needed is the maximum of the
1037 inputs and outputs. */
1041 /* [0] is normal, [1] is nongroup. */
1042 int regs[2][N_REG_CLASSES];
1043 int groups[N_REG_CLASSES];
1046 /* Each `struct needs' corresponds to one RELOAD_... type. */
1050 struct needs output;
1052 struct needs other_addr;
1053 struct needs op_addr;
1054 struct needs op_addr_reload;
1055 struct needs in_addr[MAX_RECOG_OPERANDS];
1056 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1057 struct needs out_addr[MAX_RECOG_OPERANDS];
1058 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1061 /* If needed, eliminate any eliminable registers. */
1063 did_elimination = eliminate_regs_in_insn (insn, 0);
1065 #ifdef SMALL_REGISTER_CLASSES
1066 /* Set avoid_return_reg if this is an insn
1067 that might use the value of a function call. */
1068 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1070 if (GET_CODE (PATTERN (insn)) == SET)
1071 after_call = SET_DEST (PATTERN (insn));
1072 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1073 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1074 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1078 else if (SMALL_REGISTER_CLASSES
1080 && !(GET_CODE (PATTERN (insn)) == SET
1081 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1083 if (reg_referenced_p (after_call, PATTERN (insn)))
1084 avoid_return_reg = after_call;
1087 #endif /* SMALL_REGISTER_CLASSES */
1089 /* Analyze the instruction. */
1090 find_reloads (insn, 0, spill_indirect_levels, global,
1093 /* Remember for later shortcuts which insns had any reloads or
1094 register eliminations.
1096 One might think that it would be worthwhile to mark insns
1097 that need register replacements but not reloads, but this is
1098 not safe because find_reloads may do some manipulation of
1099 the insn (such as swapping commutative operands), which would
1100 be lost when we restore the old pattern after register
1101 replacement. So the actions of find_reloads must be redone in
1102 subsequent passes or in reload_as_needed.
1104 However, it is safe to mark insns that need reloads
1105 but not register replacement. */
1107 PUT_MODE (insn, (did_elimination ? QImode
1108 : n_reloads ? HImode
1109 : GET_MODE (insn) == DImode ? DImode
1112 /* Discard any register replacements done. */
1113 if (did_elimination)
1115 obstack_free (&reload_obstack, reload_firstobj);
1116 PATTERN (insn) = old_body;
1117 INSN_CODE (insn) = old_code;
1118 REG_NOTES (insn) = old_notes;
1119 something_needs_elimination = 1;
1122 /* If this insn has no reloads, we need not do anything except
1123 in the case of a CALL_INSN when we have caller-saves and
1124 caller-save needs reloads. */
1127 && ! (GET_CODE (insn) == CALL_INSN
1128 && caller_save_spill_class != NO_REGS))
1131 something_needs_reloads = 1;
1132 bzero ((char *) &insn_needs, sizeof insn_needs);
1134 /* Count each reload once in every class
1135 containing the reload's own class. */
1137 for (i = 0; i < n_reloads; i++)
1139 register enum reg_class *p;
1140 enum reg_class class = reload_reg_class[i];
1142 enum machine_mode mode;
1144 struct needs *this_needs;
1146 /* Don't count the dummy reloads, for which one of the
1147 regs mentioned in the insn can be used for reloading.
1148 Don't count optional reloads.
1149 Don't count reloads that got combined with others. */
1150 if (reload_reg_rtx[i] != 0
1151 || reload_optional[i] != 0
1152 || (reload_out[i] == 0 && reload_in[i] == 0
1153 && ! reload_secondary_p[i]))
1156 /* Show that a reload register of this class is needed
1157 in this basic block. We do not use insn_needs and
1158 insn_groups because they are overly conservative for
1160 if (global && ! basic_block_needs[(int) class][this_block])
1162 basic_block_needs[(int) class][this_block] = 1;
1163 new_basic_block_needs = 1;
1167 mode = reload_inmode[i];
1168 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1169 mode = reload_outmode[i];
1170 size = CLASS_MAX_NREGS (class, mode);
1172 /* If this class doesn't want a group, determine if we have
1173 a nongroup need or a regular need. We have a nongroup
1174 need if this reload conflicts with a group reload whose
1175 class intersects with this reload's class. */
1179 for (j = 0; j < n_reloads; j++)
1180 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1181 (GET_MODE_SIZE (reload_outmode[j])
1182 > GET_MODE_SIZE (reload_inmode[j]))
1186 && (!reload_optional[j])
1187 && (reload_in[j] != 0 || reload_out[j] != 0
1188 || reload_secondary_p[j])
1189 && reloads_conflict (i, j)
1190 && reg_classes_intersect_p (class,
1191 reload_reg_class[j]))
1197 /* Decide which time-of-use to count this reload for. */
1198 switch (reload_when_needed[i])
1201 this_needs = &insn_needs.other;
1203 case RELOAD_FOR_INPUT:
1204 this_needs = &insn_needs.input;
1206 case RELOAD_FOR_OUTPUT:
1207 this_needs = &insn_needs.output;
1209 case RELOAD_FOR_INSN:
1210 this_needs = &insn_needs.insn;
1212 case RELOAD_FOR_OTHER_ADDRESS:
1213 this_needs = &insn_needs.other_addr;
1215 case RELOAD_FOR_INPUT_ADDRESS:
1216 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1218 case RELOAD_FOR_INPADDR_ADDRESS:
1219 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1221 case RELOAD_FOR_OUTPUT_ADDRESS:
1222 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1224 case RELOAD_FOR_OUTADDR_ADDRESS:
1225 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1227 case RELOAD_FOR_OPERAND_ADDRESS:
1228 this_needs = &insn_needs.op_addr;
1230 case RELOAD_FOR_OPADDR_ADDR:
1231 this_needs = &insn_needs.op_addr_reload;
1237 enum machine_mode other_mode, allocate_mode;
1239 /* Count number of groups needed separately from
1240 number of individual regs needed. */
1241 this_needs->groups[(int) class]++;
1242 p = reg_class_superclasses[(int) class];
1243 while (*p != LIM_REG_CLASSES)
1244 this_needs->groups[(int) *p++]++;
1246 /* Record size and mode of a group of this class. */
1247 /* If more than one size group is needed,
1248 make all groups the largest needed size. */
1249 if (group_size[(int) class] < size)
1251 other_mode = group_mode[(int) class];
1252 allocate_mode = mode;
1254 group_size[(int) class] = size;
1255 group_mode[(int) class] = mode;
1260 allocate_mode = group_mode[(int) class];
1263 /* Crash if two dissimilar machine modes both need
1264 groups of consecutive regs of the same class. */
1266 if (other_mode != VOIDmode && other_mode != allocate_mode
1267 && ! modes_equiv_for_class_p (allocate_mode,
1269 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1274 this_needs->regs[nongroup_need][(int) class] += 1;
1275 p = reg_class_superclasses[(int) class];
1276 while (*p != LIM_REG_CLASSES)
1277 this_needs->regs[nongroup_need][(int) *p++] += 1;
1283 /* All reloads have been counted for this insn;
1284 now merge the various times of use.
1285 This sets insn_needs, etc., to the maximum total number
1286 of registers needed at any point in this insn. */
1288 for (i = 0; i < N_REG_CLASSES; i++)
1290 int in_max, out_max;
1292 /* Compute normal and nongroup needs. */
1293 for (j = 0; j <= 1; j++)
1295 for (in_max = 0, out_max = 0, k = 0;
1296 k < reload_n_operands; k++)
1299 = MAX (in_max, insn_needs.in_addr[k].regs[j][i]);
1302 insn_needs.in_addr_addr[k].regs[j][i]);
1304 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1307 insn_needs.out_addr_addr[k].regs[j][i]);
1310 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1311 and operand addresses but not things used to reload
1312 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1313 don't conflict with things needed to reload inputs or
1316 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1317 insn_needs.op_addr_reload.regs[j][i]),
1320 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1322 insn_needs.input.regs[j][i]
1323 = MAX (insn_needs.input.regs[j][i]
1324 + insn_needs.op_addr.regs[j][i]
1325 + insn_needs.insn.regs[j][i],
1326 in_max + insn_needs.input.regs[j][i]);
1328 insn_needs.output.regs[j][i] += out_max;
1329 insn_needs.other.regs[j][i]
1330 += MAX (MAX (insn_needs.input.regs[j][i],
1331 insn_needs.output.regs[j][i]),
1332 insn_needs.other_addr.regs[j][i]);
1336 /* Now compute group needs. */
1337 for (in_max = 0, out_max = 0, j = 0;
1338 j < reload_n_operands; j++)
1340 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1341 in_max = MAX (in_max,
1342 insn_needs.in_addr_addr[j].groups[i]);
1344 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1346 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1349 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1350 insn_needs.op_addr_reload.groups[i]),
1352 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1354 insn_needs.input.groups[i]
1355 = MAX (insn_needs.input.groups[i]
1356 + insn_needs.op_addr.groups[i]
1357 + insn_needs.insn.groups[i],
1358 in_max + insn_needs.input.groups[i]);
1360 insn_needs.output.groups[i] += out_max;
1361 insn_needs.other.groups[i]
1362 += MAX (MAX (insn_needs.input.groups[i],
1363 insn_needs.output.groups[i]),
1364 insn_needs.other_addr.groups[i]);
1367 /* If this is a CALL_INSN and caller-saves will need
1368 a spill register, act as if the spill register is
1369 needed for this insn. However, the spill register
1370 can be used by any reload of this insn, so we only
1371 need do something if no need for that class has
1374 The assumption that every CALL_INSN will trigger a
1375 caller-save is highly conservative, however, the number
1376 of cases where caller-saves will need a spill register but
1377 a block containing a CALL_INSN won't need a spill register
1378 of that class should be quite rare.
1380 If a group is needed, the size and mode of the group will
1381 have been set up at the beginning of this loop. */
1383 if (GET_CODE (insn) == CALL_INSN
1384 && caller_save_spill_class != NO_REGS)
1386 /* See if this register would conflict with any reload
1387 that needs a group. */
1388 int nongroup_need = 0;
1389 int *caller_save_needs;
1391 for (j = 0; j < n_reloads; j++)
1392 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1393 (GET_MODE_SIZE (reload_outmode[j])
1394 > GET_MODE_SIZE (reload_inmode[j]))
1398 && reg_classes_intersect_p (caller_save_spill_class,
1399 reload_reg_class[j]))
1406 = (caller_save_group_size > 1
1407 ? insn_needs.other.groups
1408 : insn_needs.other.regs[nongroup_need]);
1410 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1412 register enum reg_class *p
1413 = reg_class_superclasses[(int) caller_save_spill_class];
1415 caller_save_needs[(int) caller_save_spill_class]++;
1417 while (*p != LIM_REG_CLASSES)
1418 caller_save_needs[(int) *p++] += 1;
1421 /* Show that this basic block will need a register of
1425 && ! (basic_block_needs[(int) caller_save_spill_class]
1428 basic_block_needs[(int) caller_save_spill_class]
1430 new_basic_block_needs = 1;
1434 #ifdef SMALL_REGISTER_CLASSES
1435 /* If this insn stores the value of a function call,
1436 and that value is in a register that has been spilled,
1437 and if the insn needs a reload in a class
1438 that might use that register as the reload register,
1439 then add add an extra need in that class.
1440 This makes sure we have a register available that does
1441 not overlap the return value. */
1443 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1445 int regno = REGNO (avoid_return_reg);
1447 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1449 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1451 /* First compute the "basic needs", which counts a
1452 need only in the smallest class in which it
1455 bcopy ((char *) insn_needs.other.regs[0],
1456 (char *) basic_needs, sizeof basic_needs);
1457 bcopy ((char *) insn_needs.other.groups,
1458 (char *) basic_groups, sizeof basic_groups);
1460 for (i = 0; i < N_REG_CLASSES; i++)
1464 if (basic_needs[i] >= 0)
1465 for (p = reg_class_superclasses[i];
1466 *p != LIM_REG_CLASSES; p++)
1467 basic_needs[(int) *p] -= basic_needs[i];
1469 if (basic_groups[i] >= 0)
1470 for (p = reg_class_superclasses[i];
1471 *p != LIM_REG_CLASSES; p++)
1472 basic_groups[(int) *p] -= basic_groups[i];
1475 /* Now count extra regs if there might be a conflict with
1476 the return value register. */
1478 for (r = regno; r < regno + nregs; r++)
1479 if (spill_reg_order[r] >= 0)
1480 for (i = 0; i < N_REG_CLASSES; i++)
1481 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1483 if (basic_needs[i] > 0)
1487 insn_needs.other.regs[0][i]++;
1488 p = reg_class_superclasses[i];
1489 while (*p != LIM_REG_CLASSES)
1490 insn_needs.other.regs[0][(int) *p++]++;
1492 if (basic_groups[i] > 0)
1496 insn_needs.other.groups[i]++;
1497 p = reg_class_superclasses[i];
1498 while (*p != LIM_REG_CLASSES)
1499 insn_needs.other.groups[(int) *p++]++;
1503 #endif /* SMALL_REGISTER_CLASSES */
1505 /* For each class, collect maximum need of any insn. */
1507 for (i = 0; i < N_REG_CLASSES; i++)
1509 if (max_needs[i] < insn_needs.other.regs[0][i])
1511 max_needs[i] = insn_needs.other.regs[0][i];
1512 max_needs_insn[i] = insn;
1514 if (max_groups[i] < insn_needs.other.groups[i])
1516 max_groups[i] = insn_needs.other.groups[i];
1517 max_groups_insn[i] = insn;
1519 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1521 max_nongroups[i] = insn_needs.other.regs[1][i];
1522 max_nongroups_insn[i] = insn;
1526 /* Note that there is a continue statement above. */
1529 /* If we allocated any new memory locations, make another pass
1530 since it might have changed elimination offsets. */
1531 if (starting_frame_size != get_frame_size ())
1532 something_changed = 1;
1535 for (i = 0; i < N_REG_CLASSES; i++)
1537 if (max_needs[i] > 0)
1539 ";; Need %d reg%s of class %s (for insn %d).\n",
1540 max_needs[i], max_needs[i] == 1 ? "" : "s",
1541 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1542 if (max_nongroups[i] > 0)
1544 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1545 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1546 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1547 if (max_groups[i] > 0)
1549 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1550 max_groups[i], max_groups[i] == 1 ? "" : "s",
1551 mode_name[(int) group_mode[i]],
1552 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1555 /* If we have caller-saves, set up the save areas and see if caller-save
1556 will need a spill register. */
1558 if (caller_save_needed)
1560 /* Set the offsets for setup_save_areas. */
1561 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1563 ep->previous_offset = ep->max_offset;
1565 if ( ! setup_save_areas (&something_changed)
1566 && caller_save_spill_class == NO_REGS)
1568 /* The class we will need depends on whether the machine
1569 supports the sum of two registers for an address; see
1570 find_address_reloads for details. */
1572 caller_save_spill_class
1573 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1574 caller_save_group_size
1575 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1576 something_changed = 1;
1580 /* See if anything that happened changes which eliminations are valid.
1581 For example, on the Sparc, whether or not the frame pointer can
1582 be eliminated can depend on what registers have been used. We need
1583 not check some conditions again (such as flag_omit_frame_pointer)
1584 since they can't have changed. */
1586 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1587 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1588 #ifdef ELIMINABLE_REGS
1589 || ! CAN_ELIMINATE (ep->from, ep->to)
1592 ep->can_eliminate = 0;
1594 /* Look for the case where we have discovered that we can't replace
1595 register A with register B and that means that we will now be
1596 trying to replace register A with register C. This means we can
1597 no longer replace register C with register B and we need to disable
1598 such an elimination, if it exists. This occurs often with A == ap,
1599 B == sp, and C == fp. */
1601 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1603 struct elim_table *op;
1604 register int new_to = -1;
1606 if (! ep->can_eliminate && ep->can_eliminate_previous)
1608 /* Find the current elimination for ep->from, if there is a
1610 for (op = reg_eliminate;
1611 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1612 if (op->from == ep->from && op->can_eliminate)
1618 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1620 for (op = reg_eliminate;
1621 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1622 if (op->from == new_to && op->to == ep->to)
1623 op->can_eliminate = 0;
1627 /* See if any registers that we thought we could eliminate the previous
1628 time are no longer eliminable. If so, something has changed and we
1629 must spill the register. Also, recompute the number of eliminable
1630 registers and see if the frame pointer is needed; it is if there is
1631 no elimination of the frame pointer that we can perform. */
1633 frame_pointer_needed = 1;
1634 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1636 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1637 && ep->to != HARD_FRAME_POINTER_REGNUM)
1638 frame_pointer_needed = 0;
1640 if (! ep->can_eliminate && ep->can_eliminate_previous)
1642 ep->can_eliminate_previous = 0;
1643 spill_hard_reg (ep->from, global, dumpfile, 1);
1644 something_changed = 1;
1649 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1650 /* If we didn't need a frame pointer last time, but we do now, spill
1651 the hard frame pointer. */
1652 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1654 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1655 something_changed = 1;
1659 /* If all needs are met, we win. */
1661 for (i = 0; i < N_REG_CLASSES; i++)
1662 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1664 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1667 /* Not all needs are met; must spill some hard regs. */
1669 /* Put all registers spilled so far back in potential_reload_regs, but
1670 put them at the front, since we've already spilled most of the
1671 pseudos in them (we might have left some pseudos unspilled if they
1672 were in a block that didn't need any spill registers of a conflicting
1673 class. We used to try to mark off the need for those registers,
1674 but doing so properly is very complex and reallocating them is the
1675 simpler approach. First, "pack" potential_reload_regs by pushing
1676 any nonnegative entries towards the end. That will leave room
1677 for the registers we already spilled.
1679 Also, undo the marking of the spill registers from the last time
1680 around in FORBIDDEN_REGS since we will be probably be allocating
1683 ??? It is theoretically possible that we might end up not using one
1684 of our previously-spilled registers in this allocation, even though
1685 they are at the head of the list. It's not clear what to do about
1686 this, but it was no better before, when we marked off the needs met
1687 by the previously-spilled registers. With the current code, globals
1688 can be allocated into these registers, but locals cannot. */
1692 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1693 if (potential_reload_regs[i] != -1)
1694 potential_reload_regs[j--] = potential_reload_regs[i];
1696 for (i = 0; i < n_spills; i++)
1698 potential_reload_regs[i] = spill_regs[i];
1699 spill_reg_order[spill_regs[i]] = -1;
1700 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1706 /* Now find more reload regs to satisfy the remaining need
1707 Do it by ascending class number, since otherwise a reg
1708 might be spilled for a big class and might fail to count
1709 for a smaller class even though it belongs to that class.
1711 Count spilled regs in `spills', and add entries to
1712 `spill_regs' and `spill_reg_order'.
1714 ??? Note there is a problem here.
1715 When there is a need for a group in a high-numbered class,
1716 and also need for non-group regs that come from a lower class,
1717 the non-group regs are chosen first. If there aren't many regs,
1718 they might leave no room for a group.
1720 This was happening on the 386. To fix it, we added the code
1721 that calls possible_group_p, so that the lower class won't
1722 break up the last possible group.
1724 Really fixing the problem would require changes above
1725 in counting the regs already spilled, and in choose_reload_regs.
1726 It might be hard to avoid introducing bugs there. */
1728 CLEAR_HARD_REG_SET (counted_for_groups);
1729 CLEAR_HARD_REG_SET (counted_for_nongroups);
1731 for (class = 0; class < N_REG_CLASSES; class++)
1733 /* First get the groups of registers.
1734 If we got single registers first, we might fragment
1736 while (max_groups[class] > 0)
1738 /* If any single spilled regs happen to form groups,
1739 count them now. Maybe we don't really need
1740 to spill another group. */
1741 count_possible_groups (group_size, group_mode, max_groups,
1744 if (max_groups[class] <= 0)
1747 /* Groups of size 2 (the only groups used on most machines)
1748 are treated specially. */
1749 if (group_size[class] == 2)
1751 /* First, look for a register that will complete a group. */
1752 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1756 j = potential_reload_regs[i];
1757 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1759 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1760 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1761 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1762 && HARD_REGNO_MODE_OK (other, group_mode[class])
1763 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1765 /* We don't want one part of another group.
1766 We could get "two groups" that overlap! */
1767 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1769 (j < FIRST_PSEUDO_REGISTER - 1
1770 && (other = j + 1, spill_reg_order[other] >= 0)
1771 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1772 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1773 && HARD_REGNO_MODE_OK (j, group_mode[class])
1774 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1776 && ! TEST_HARD_REG_BIT (counted_for_groups,
1779 register enum reg_class *p;
1781 /* We have found one that will complete a group,
1782 so count off one group as provided. */
1783 max_groups[class]--;
1784 p = reg_class_superclasses[class];
1785 while (*p != LIM_REG_CLASSES)
1787 if (group_size [(int) *p] <= group_size [class])
1788 max_groups[(int) *p]--;
1792 /* Indicate both these regs are part of a group. */
1793 SET_HARD_REG_BIT (counted_for_groups, j);
1794 SET_HARD_REG_BIT (counted_for_groups, other);
1798 /* We can't complete a group, so start one. */
1799 #ifdef SMALL_REGISTER_CLASSES
1800 /* Look for a pair neither of which is explicitly used. */
1801 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1802 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1805 j = potential_reload_regs[i];
1806 /* Verify that J+1 is a potential reload reg. */
1807 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1808 if (potential_reload_regs[k] == j + 1)
1810 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1811 && k < FIRST_PSEUDO_REGISTER
1812 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1813 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1814 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1815 && HARD_REGNO_MODE_OK (j, group_mode[class])
1816 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1818 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1819 /* Reject J at this stage
1820 if J+1 was explicitly used. */
1821 && ! regs_explicitly_used[j + 1])
1825 /* Now try any group at all
1826 whose registers are not in bad_spill_regs. */
1827 if (i == FIRST_PSEUDO_REGISTER)
1828 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1831 j = potential_reload_regs[i];
1832 /* Verify that J+1 is a potential reload reg. */
1833 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1834 if (potential_reload_regs[k] == j + 1)
1836 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1837 && k < FIRST_PSEUDO_REGISTER
1838 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1839 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1840 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1841 && HARD_REGNO_MODE_OK (j, group_mode[class])
1842 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1844 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1848 /* I should be the index in potential_reload_regs
1849 of the new reload reg we have found. */
1851 if (i >= FIRST_PSEUDO_REGISTER)
1853 /* There are no groups left to spill. */
1854 spill_failure (max_groups_insn[class]);
1860 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1865 /* For groups of more than 2 registers,
1866 look for a sufficient sequence of unspilled registers,
1867 and spill them all at once. */
1868 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1872 j = potential_reload_regs[i];
1874 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1875 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1877 /* Check each reg in the sequence. */
1878 for (k = 0; k < group_size[class]; k++)
1879 if (! (spill_reg_order[j + k] < 0
1880 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1881 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1883 /* We got a full sequence, so spill them all. */
1884 if (k == group_size[class])
1886 register enum reg_class *p;
1887 for (k = 0; k < group_size[class]; k++)
1890 SET_HARD_REG_BIT (counted_for_groups, j + k);
1891 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1892 if (potential_reload_regs[idx] == j + k)
1895 |= new_spill_reg (idx, class,
1896 max_needs, NULL_PTR,
1900 /* We have found one that will complete a group,
1901 so count off one group as provided. */
1902 max_groups[class]--;
1903 p = reg_class_superclasses[class];
1904 while (*p != LIM_REG_CLASSES)
1906 if (group_size [(int) *p]
1907 <= group_size [class])
1908 max_groups[(int) *p]--;
1915 /* We couldn't find any registers for this reload.
1916 Avoid going into an infinite loop. */
1917 if (i >= FIRST_PSEUDO_REGISTER)
1919 /* There are no groups left. */
1920 spill_failure (max_groups_insn[class]);
1927 /* Now similarly satisfy all need for single registers. */
1929 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1931 /* If we spilled enough regs, but they weren't counted
1932 against the non-group need, see if we can count them now.
1933 If so, we can avoid some actual spilling. */
1934 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1935 for (i = 0; i < n_spills; i++)
1936 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1938 && !TEST_HARD_REG_BIT (counted_for_groups,
1940 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1942 && max_nongroups[class] > 0)
1944 register enum reg_class *p;
1946 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1947 max_nongroups[class]--;
1948 p = reg_class_superclasses[class];
1949 while (*p != LIM_REG_CLASSES)
1950 max_nongroups[(int) *p++]--;
1952 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1955 /* Consider the potential reload regs that aren't
1956 yet in use as reload regs, in order of preference.
1957 Find the most preferred one that's in this class. */
1959 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1960 if (potential_reload_regs[i] >= 0
1961 && TEST_HARD_REG_BIT (reg_class_contents[class],
1962 potential_reload_regs[i])
1963 /* If this reg will not be available for groups,
1964 pick one that does not foreclose possible groups.
1965 This is a kludge, and not very general,
1966 but it should be sufficient to make the 386 work,
1967 and the problem should not occur on machines with
1969 && (max_nongroups[class] == 0
1970 || possible_group_p (potential_reload_regs[i], max_groups)))
1973 /* If we couldn't get a register, try to get one even if we
1974 might foreclose possible groups. This may cause problems
1975 later, but that's better than aborting now, since it is
1976 possible that we will, in fact, be able to form the needed
1977 group even with this allocation. */
1979 if (i >= FIRST_PSEUDO_REGISTER
1980 && (asm_noperands (max_needs[class] > 0
1981 ? max_needs_insn[class]
1982 : max_nongroups_insn[class])
1984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1985 if (potential_reload_regs[i] >= 0
1986 && TEST_HARD_REG_BIT (reg_class_contents[class],
1987 potential_reload_regs[i]))
1990 /* I should be the index in potential_reload_regs
1991 of the new reload reg we have found. */
1993 if (i >= FIRST_PSEUDO_REGISTER)
1995 /* There are no possible registers left to spill. */
1996 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1997 : max_nongroups_insn[class]);
2003 |= new_spill_reg (i, class, max_needs, max_nongroups,
2009 /* If global-alloc was run, notify it of any register eliminations we have
2012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2013 if (ep->can_eliminate)
2014 mark_elimination (ep->from, ep->to);
2016 /* Insert code to save and restore call-clobbered hard regs
2017 around calls. Tell if what mode to use so that we will process
2018 those insns in reload_as_needed if we have to. */
2020 if (caller_save_needed)
2021 save_call_clobbered_regs (num_eliminable ? QImode
2022 : caller_save_spill_class != NO_REGS ? HImode
2025 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2026 If that insn didn't set the register (i.e., it copied the register to
2027 memory), just delete that insn instead of the equivalencing insn plus
2028 anything now dead. If we call delete_dead_insn on that insn, we may
2029 delete the insn that actually sets the register if the register die
2030 there and that is incorrect. */
2032 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2033 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2034 && GET_CODE (reg_equiv_init[i]) != NOTE)
2036 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2037 delete_dead_insn (reg_equiv_init[i]);
2040 PUT_CODE (reg_equiv_init[i], NOTE);
2041 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2042 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2046 /* Use the reload registers where necessary
2047 by generating move instructions to move the must-be-register
2048 values into or out of the reload registers. */
2050 if (something_needs_reloads || something_needs_elimination
2051 || (caller_save_needed && num_eliminable)
2052 || caller_save_spill_class != NO_REGS)
2053 reload_as_needed (first, global);
2055 /* If we were able to eliminate the frame pointer, show that it is no
2056 longer live at the start of any basic block. If it ls live by
2057 virtue of being in a pseudo, that pseudo will be marked live
2058 and hence the frame pointer will be known to be live via that
2061 if (! frame_pointer_needed)
2062 for (i = 0; i < n_basic_blocks; i++)
2063 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
2064 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
2065 % REGSET_ELT_BITS));
2067 /* Come here (with failure set nonzero) if we can't get enough spill regs
2068 and we decide not to abort about it. */
2071 reload_in_progress = 0;
2073 /* Now eliminate all pseudo regs by modifying them into
2074 their equivalent memory references.
2075 The REG-rtx's for the pseudos are modified in place,
2076 so all insns that used to refer to them now refer to memory.
2078 For a reg that has a reg_equiv_address, all those insns
2079 were changed by reloading so that no insns refer to it any longer;
2080 but the DECL_RTL of a variable decl may refer to it,
2081 and if so this causes the debugging info to mention the variable. */
2083 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2087 if (reg_equiv_mem[i])
2089 addr = XEXP (reg_equiv_mem[i], 0);
2090 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2092 if (reg_equiv_address[i])
2093 addr = reg_equiv_address[i];
2096 if (reg_renumber[i] < 0)
2098 rtx reg = regno_reg_rtx[i];
2099 XEXP (reg, 0) = addr;
2100 REG_USERVAR_P (reg) = 0;
2101 MEM_IN_STRUCT_P (reg) = in_struct;
2102 PUT_CODE (reg, MEM);
2104 else if (reg_equiv_mem[i])
2105 XEXP (reg_equiv_mem[i], 0) = addr;
2109 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2110 /* Make a pass over all the insns and remove death notes for things that
2111 are no longer registers or no longer die in the insn (e.g., an input
2112 and output pseudo being tied). */
2114 for (insn = first; insn; insn = NEXT_INSN (insn))
2115 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2119 for (note = REG_NOTES (insn); note; note = next)
2121 next = XEXP (note, 1);
2122 if (REG_NOTE_KIND (note) == REG_DEAD
2123 && (GET_CODE (XEXP (note, 0)) != REG
2124 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2125 remove_note (insn, note);
2130 /* Indicate that we no longer have known memory locations or constants. */
2131 reg_equiv_constant = 0;
2132 reg_equiv_memory_loc = 0;
2135 free (scratch_list);
2138 free (scratch_block);
2141 CLEAR_HARD_REG_SET (used_spill_regs);
2142 for (i = 0; i < n_spills; i++)
2143 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2148 /* Nonzero if, after spilling reg REGNO for non-groups,
2149 it will still be possible to find a group if we still need one. */
2152 possible_group_p (regno, max_groups)
2157 int class = (int) NO_REGS;
2159 for (i = 0; i < (int) N_REG_CLASSES; i++)
2160 if (max_groups[i] > 0)
2166 if (class == (int) NO_REGS)
2169 /* Consider each pair of consecutive registers. */
2170 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2172 /* Ignore pairs that include reg REGNO. */
2173 if (i == regno || i + 1 == regno)
2176 /* Ignore pairs that are outside the class that needs the group.
2177 ??? Here we fail to handle the case where two different classes
2178 independently need groups. But this never happens with our
2179 current machine descriptions. */
2180 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2181 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2184 /* A pair of consecutive regs we can still spill does the trick. */
2185 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2186 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2187 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2190 /* A pair of one already spilled and one we can spill does it
2191 provided the one already spilled is not otherwise reserved. */
2192 if (spill_reg_order[i] < 0
2193 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2194 && spill_reg_order[i + 1] >= 0
2195 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2196 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2198 if (spill_reg_order[i + 1] < 0
2199 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2200 && spill_reg_order[i] >= 0
2201 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2202 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2209 /* Count any groups of CLASS that can be formed from the registers recently
2213 count_possible_groups (group_size, group_mode, max_groups, class)
2215 enum machine_mode *group_mode;
2222 /* Now find all consecutive groups of spilled registers
2223 and mark each group off against the need for such groups.
2224 But don't count them against ordinary need, yet. */
2226 if (group_size[class] == 0)
2229 CLEAR_HARD_REG_SET (new);
2231 /* Make a mask of all the regs that are spill regs in class I. */
2232 for (i = 0; i < n_spills; i++)
2233 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2234 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2235 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2236 SET_HARD_REG_BIT (new, spill_regs[i]);
2238 /* Find each consecutive group of them. */
2239 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2240 if (TEST_HARD_REG_BIT (new, i)
2241 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2242 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2244 for (j = 1; j < group_size[class]; j++)
2245 if (! TEST_HARD_REG_BIT (new, i + j))
2248 if (j == group_size[class])
2250 /* We found a group. Mark it off against this class's need for
2251 groups, and against each superclass too. */
2252 register enum reg_class *p;
2254 max_groups[class]--;
2255 p = reg_class_superclasses[class];
2256 while (*p != LIM_REG_CLASSES)
2258 if (group_size [(int) *p] <= group_size [class])
2259 max_groups[(int) *p]--;
2263 /* Don't count these registers again. */
2264 for (j = 0; j < group_size[class]; j++)
2265 SET_HARD_REG_BIT (counted_for_groups, i + j);
2268 /* Skip to the last reg in this group. When i is incremented above,
2269 it will then point to the first reg of the next possible group. */
2274 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2275 another mode that needs to be reloaded for the same register class CLASS.
2276 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2277 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2279 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2280 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2281 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2282 causes unnecessary failures on machines requiring alignment of register
2283 groups when the two modes are different sizes, because the larger mode has
2284 more strict alignment rules than the smaller mode. */
2287 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2288 enum machine_mode allocate_mode, other_mode;
2289 enum reg_class class;
2292 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2294 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2295 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2296 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2302 /* Handle the failure to find a register to spill.
2303 INSN should be one of the insns which needed this particular spill reg. */
2306 spill_failure (insn)
2309 if (asm_noperands (PATTERN (insn)) >= 0)
2310 error_for_asm (insn, "`asm' needs too many reloads");
2312 fatal_insn ("Unable to find a register to spill.", insn);
2315 /* Add a new register to the tables of available spill-registers
2316 (as well as spilling all pseudos allocated to the register).
2317 I is the index of this register in potential_reload_regs.
2318 CLASS is the regclass whose need is being satisfied.
2319 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2320 so that this register can count off against them.
2321 MAX_NONGROUPS is 0 if this register is part of a group.
2322 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2325 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2333 register enum reg_class *p;
2335 int regno = potential_reload_regs[i];
2337 if (i >= FIRST_PSEUDO_REGISTER)
2338 abort (); /* Caller failed to find any register. */
2340 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2341 fatal ("fixed or forbidden register was spilled.\n\
2342 This may be due to a compiler bug or to impossible asm\n\
2343 statements or clauses.");
2345 /* Make reg REGNO an additional reload reg. */
2347 potential_reload_regs[i] = -1;
2348 spill_regs[n_spills] = regno;
2349 spill_reg_order[regno] = n_spills;
2351 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2353 /* Clear off the needs we just satisfied. */
2356 p = reg_class_superclasses[class];
2357 while (*p != LIM_REG_CLASSES)
2358 max_needs[(int) *p++]--;
2360 if (max_nongroups && max_nongroups[class] > 0)
2362 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2363 max_nongroups[class]--;
2364 p = reg_class_superclasses[class];
2365 while (*p != LIM_REG_CLASSES)
2366 max_nongroups[(int) *p++]--;
2369 /* Spill every pseudo reg that was allocated to this reg
2370 or to something that overlaps this reg. */
2372 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2374 /* If there are some registers still to eliminate and this register
2375 wasn't ever used before, additional stack space may have to be
2376 allocated to store this register. Thus, we may have changed the offset
2377 between the stack and frame pointers, so mark that something has changed.
2378 (If new pseudos were spilled, thus requiring more space, VAL would have
2379 been set non-zero by the call to spill_hard_reg above since additional
2380 reloads may be needed in that case.
2382 One might think that we need only set VAL to 1 if this is a call-used
2383 register. However, the set of registers that must be saved by the
2384 prologue is not identical to the call-used set. For example, the
2385 register used by the call insn for the return PC is a call-used register,
2386 but must be saved by the prologue. */
2387 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2390 regs_ever_live[spill_regs[n_spills]] = 1;
2396 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2397 data that is dead in INSN. */
2400 delete_dead_insn (insn)
2403 rtx prev = prev_real_insn (insn);
2406 /* If the previous insn sets a register that dies in our insn, delete it
2408 if (prev && GET_CODE (PATTERN (prev)) == SET
2409 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2410 && reg_mentioned_p (prev_dest, PATTERN (insn))
2411 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2412 delete_dead_insn (prev);
2414 PUT_CODE (insn, NOTE);
2415 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2416 NOTE_SOURCE_FILE (insn) = 0;
2419 /* Modify the home of pseudo-reg I.
2420 The new home is present in reg_renumber[I].
2422 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2423 or it may be -1, meaning there is none or it is not relevant.
2424 This is used so that all pseudos spilled from a given hard reg
2425 can share one stack slot. */
2428 alter_reg (i, from_reg)
2432 /* When outputting an inline function, this can happen
2433 for a reg that isn't actually used. */
2434 if (regno_reg_rtx[i] == 0)
2437 /* If the reg got changed to a MEM at rtl-generation time,
2439 if (GET_CODE (regno_reg_rtx[i]) != REG)
2442 /* Modify the reg-rtx to contain the new hard reg
2443 number or else to contain its pseudo reg number. */
2444 REGNO (regno_reg_rtx[i])
2445 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2447 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2448 allocate a stack slot for it. */
2450 if (reg_renumber[i] < 0
2451 && reg_n_refs[i] > 0
2452 && reg_equiv_constant[i] == 0
2453 && reg_equiv_memory_loc[i] == 0)
2456 int inherent_size = PSEUDO_REGNO_BYTES (i);
2457 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2460 /* Each pseudo reg has an inherent size which comes from its own mode,
2461 and a total size which provides room for paradoxical subregs
2462 which refer to the pseudo reg in wider modes.
2464 We can use a slot already allocated if it provides both
2465 enough inherent space and enough total space.
2466 Otherwise, we allocate a new slot, making sure that it has no less
2467 inherent space, and no less total space, then the previous slot. */
2470 /* No known place to spill from => no slot to reuse. */
2471 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2472 inherent_size == total_size ? 0 : -1);
2473 if (BYTES_BIG_ENDIAN)
2474 /* Cancel the big-endian correction done in assign_stack_local.
2475 Get the address of the beginning of the slot.
2476 This is so we can do a big-endian correction unconditionally
2478 adjust = inherent_size - total_size;
2480 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2482 /* Reuse a stack slot if possible. */
2483 else if (spill_stack_slot[from_reg] != 0
2484 && spill_stack_slot_width[from_reg] >= total_size
2485 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2487 x = spill_stack_slot[from_reg];
2488 /* Allocate a bigger slot. */
2491 /* Compute maximum size needed, both for inherent size
2492 and for total size. */
2493 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2495 if (spill_stack_slot[from_reg])
2497 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2499 mode = GET_MODE (spill_stack_slot[from_reg]);
2500 if (spill_stack_slot_width[from_reg] > total_size)
2501 total_size = spill_stack_slot_width[from_reg];
2503 /* Make a slot with that size. */
2504 x = assign_stack_local (mode, total_size,
2505 inherent_size == total_size ? 0 : -1);
2507 if (BYTES_BIG_ENDIAN)
2509 /* Cancel the big-endian correction done in assign_stack_local.
2510 Get the address of the beginning of the slot.
2511 This is so we can do a big-endian correction unconditionally
2513 adjust = GET_MODE_SIZE (mode) - total_size;
2515 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2518 plus_constant (XEXP (x, 0), adjust));
2520 spill_stack_slot[from_reg] = stack_slot;
2521 spill_stack_slot_width[from_reg] = total_size;
2524 /* On a big endian machine, the "address" of the slot
2525 is the address of the low part that fits its inherent mode. */
2526 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2527 adjust += (total_size - inherent_size);
2529 /* If we have any adjustment to make, or if the stack slot is the
2530 wrong mode, make a new stack slot. */
2531 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2533 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2534 plus_constant (XEXP (x, 0), adjust));
2535 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2538 /* Save the stack slot for later. */
2539 reg_equiv_memory_loc[i] = x;
2543 /* Mark the slots in regs_ever_live for the hard regs
2544 used by pseudo-reg number REGNO. */
2547 mark_home_live (regno)
2550 register int i, lim;
2551 i = reg_renumber[regno];
2554 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2556 regs_ever_live[i++] = 1;
2559 /* Mark the registers used in SCRATCH as being live. */
2562 mark_scratch_live (scratch)
2566 int regno = REGNO (scratch);
2567 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2569 for (i = regno; i < lim; i++)
2570 regs_ever_live[i] = 1;
2573 /* This function handles the tracking of elimination offsets around branches.
2575 X is a piece of RTL being scanned.
2577 INSN is the insn that it came from, if any.
2579 INITIAL_P is non-zero if we are to set the offset to be the initial
2580 offset and zero if we are setting the offset of the label to be the
2584 set_label_offsets (x, insn, initial_p)
2589 enum rtx_code code = GET_CODE (x);
2592 struct elim_table *p;
2597 if (LABEL_REF_NONLOCAL_P (x))
2602 /* ... fall through ... */
2605 /* If we know nothing about this label, set the desired offsets. Note
2606 that this sets the offset at a label to be the offset before a label
2607 if we don't know anything about the label. This is not correct for
2608 the label after a BARRIER, but is the best guess we can make. If
2609 we guessed wrong, we will suppress an elimination that might have
2610 been possible had we been able to guess correctly. */
2612 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2614 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2615 offsets_at[CODE_LABEL_NUMBER (x)][i]
2616 = (initial_p ? reg_eliminate[i].initial_offset
2617 : reg_eliminate[i].offset);
2618 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2621 /* Otherwise, if this is the definition of a label and it is
2622 preceded by a BARRIER, set our offsets to the known offset of
2626 && (tem = prev_nonnote_insn (insn)) != 0
2627 && GET_CODE (tem) == BARRIER)
2629 num_not_at_initial_offset = 0;
2630 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2632 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2633 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2634 if (reg_eliminate[i].can_eliminate
2635 && (reg_eliminate[i].offset
2636 != reg_eliminate[i].initial_offset))
2637 num_not_at_initial_offset++;
2642 /* If neither of the above cases is true, compare each offset
2643 with those previously recorded and suppress any eliminations
2644 where the offsets disagree. */
2646 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2647 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2648 != (initial_p ? reg_eliminate[i].initial_offset
2649 : reg_eliminate[i].offset))
2650 reg_eliminate[i].can_eliminate = 0;
2655 set_label_offsets (PATTERN (insn), insn, initial_p);
2657 /* ... fall through ... */
2661 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2662 and hence must have all eliminations at their initial offsets. */
2663 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2664 if (REG_NOTE_KIND (tem) == REG_LABEL)
2665 set_label_offsets (XEXP (tem, 0), insn, 1);
2670 /* Each of the labels in the address vector must be at their initial
2671 offsets. We want the first first for ADDR_VEC and the second
2672 field for ADDR_DIFF_VEC. */
2674 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2675 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2680 /* We only care about setting PC. If the source is not RETURN,
2681 IF_THEN_ELSE, or a label, disable any eliminations not at
2682 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2683 isn't one of those possibilities. For branches to a label,
2684 call ourselves recursively.
2686 Note that this can disable elimination unnecessarily when we have
2687 a non-local goto since it will look like a non-constant jump to
2688 someplace in the current function. This isn't a significant
2689 problem since such jumps will normally be when all elimination
2690 pairs are back to their initial offsets. */
2692 if (SET_DEST (x) != pc_rtx)
2695 switch (GET_CODE (SET_SRC (x)))
2702 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2706 tem = XEXP (SET_SRC (x), 1);
2707 if (GET_CODE (tem) == LABEL_REF)
2708 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2709 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2712 tem = XEXP (SET_SRC (x), 2);
2713 if (GET_CODE (tem) == LABEL_REF)
2714 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2715 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2720 /* If we reach here, all eliminations must be at their initial
2721 offset because we are doing a jump to a variable address. */
2722 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2723 if (p->offset != p->initial_offset)
2724 p->can_eliminate = 0;
2728 /* Used for communication between the next two function to properly share
2729 the vector for an ASM_OPERANDS. */
2731 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2733 /* Scan X and replace any eliminable registers (such as fp) with a
2734 replacement (such as sp), plus an offset.
2736 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2737 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2738 MEM, we are allowed to replace a sum of a register and the constant zero
2739 with the register, which we cannot do outside a MEM. In addition, we need
2740 to record the fact that a register is referenced outside a MEM.
2742 If INSN is an insn, it is the insn containing X. If we replace a REG
2743 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2744 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2745 that the REG is being modified.
2747 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2748 That's used when we eliminate in expressions stored in notes.
2749 This means, do not set ref_outside_mem even if the reference
2752 If we see a modification to a register we know about, take the
2753 appropriate action (see case SET, below).
2755 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2756 replacements done assuming all offsets are at their initial values. If
2757 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2758 encounter, return the actual location so that find_reloads will do
2759 the proper thing. */
2762 eliminate_regs (x, mem_mode, insn)
2764 enum machine_mode mem_mode;
2767 enum rtx_code code = GET_CODE (x);
2768 struct elim_table *ep;
2793 /* First handle the case where we encounter a bare register that
2794 is eliminable. Replace it with a PLUS. */
2795 if (regno < FIRST_PSEUDO_REGISTER)
2797 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2799 if (ep->from_rtx == x && ep->can_eliminate)
2802 /* Refs inside notes don't count for this purpose. */
2803 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2804 || GET_CODE (insn) == INSN_LIST)))
2805 ep->ref_outside_mem = 1;
2806 return plus_constant (ep->to_rtx, ep->previous_offset);
2810 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2811 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2813 /* In this case, find_reloads would attempt to either use an
2814 incorrect address (if something is not at its initial offset)
2815 or substitute an replaced address into an insn (which loses
2816 if the offset is changed by some later action). So we simply
2817 return the replaced stack slot (assuming it is changed by
2818 elimination) and ignore the fact that this is actually a
2819 reference to the pseudo. Ensure we make a copy of the
2820 address in case it is shared. */
2821 new = eliminate_regs (reg_equiv_memory_loc[regno],
2823 if (new != reg_equiv_memory_loc[regno])
2825 cannot_omit_stores[regno] = 1;
2826 return copy_rtx (new);
2832 /* If this is the sum of an eliminable register and a constant, rework
2834 if (GET_CODE (XEXP (x, 0)) == REG
2835 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2836 && CONSTANT_P (XEXP (x, 1)))
2838 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2840 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2843 /* Refs inside notes don't count for this purpose. */
2844 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2845 || GET_CODE (insn) == INSN_LIST)))
2846 ep->ref_outside_mem = 1;
2848 /* The only time we want to replace a PLUS with a REG (this
2849 occurs when the constant operand of the PLUS is the negative
2850 of the offset) is when we are inside a MEM. We won't want
2851 to do so at other times because that would change the
2852 structure of the insn in a way that reload can't handle.
2853 We special-case the commonest situation in
2854 eliminate_regs_in_insn, so just replace a PLUS with a
2855 PLUS here, unless inside a MEM. */
2856 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2857 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2860 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2861 plus_constant (XEXP (x, 1),
2862 ep->previous_offset));
2865 /* If the register is not eliminable, we are done since the other
2866 operand is a constant. */
2870 /* If this is part of an address, we want to bring any constant to the
2871 outermost PLUS. We will do this by doing register replacement in
2872 our operands and seeing if a constant shows up in one of them.
2874 We assume here this is part of an address (or a "load address" insn)
2875 since an eliminable register is not likely to appear in any other
2878 If we have (plus (eliminable) (reg)), we want to produce
2879 (plus (plus (replacement) (reg) (const))). If this was part of a
2880 normal add insn, (plus (replacement) (reg)) will be pushed as a
2881 reload. This is the desired action. */
2884 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2885 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2887 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2889 /* If one side is a PLUS and the other side is a pseudo that
2890 didn't get a hard register but has a reg_equiv_constant,
2891 we must replace the constant here since it may no longer
2892 be in the position of any operand. */
2893 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2894 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2895 && reg_renumber[REGNO (new1)] < 0
2896 && reg_equiv_constant != 0
2897 && reg_equiv_constant[REGNO (new1)] != 0)
2898 new1 = reg_equiv_constant[REGNO (new1)];
2899 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2900 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2901 && reg_renumber[REGNO (new0)] < 0
2902 && reg_equiv_constant[REGNO (new0)] != 0)
2903 new0 = reg_equiv_constant[REGNO (new0)];
2905 new = form_sum (new0, new1);
2907 /* As above, if we are not inside a MEM we do not want to
2908 turn a PLUS into something else. We might try to do so here
2909 for an addition of 0 if we aren't optimizing. */
2910 if (! mem_mode && GET_CODE (new) != PLUS)
2911 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2919 /* If this is the product of an eliminable register and a
2920 constant, apply the distribute law and move the constant out
2921 so that we have (plus (mult ..) ..). This is needed in order
2922 to keep load-address insns valid. This case is pathological.
2923 We ignore the possibility of overflow here. */
2924 if (GET_CODE (XEXP (x, 0)) == REG
2925 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2926 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2927 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2929 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2932 /* Refs inside notes don't count for this purpose. */
2933 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2934 || GET_CODE (insn) == INSN_LIST)))
2935 ep->ref_outside_mem = 1;
2938 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2939 ep->previous_offset * INTVAL (XEXP (x, 1)));
2942 /* ... fall through ... */
2947 case DIV: case UDIV:
2948 case MOD: case UMOD:
2949 case AND: case IOR: case XOR:
2950 case ROTATERT: case ROTATE:
2951 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2953 case GE: case GT: case GEU: case GTU:
2954 case LE: case LT: case LEU: case LTU:
2956 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2958 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2960 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2961 return gen_rtx (code, GET_MODE (x), new0, new1);
2966 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2969 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2970 if (new != XEXP (x, 0))
2971 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2974 /* ... fall through ... */
2977 /* Now do eliminations in the rest of the chain. If this was
2978 an EXPR_LIST, this might result in allocating more memory than is
2979 strictly needed, but it simplifies the code. */
2982 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2983 if (new != XEXP (x, 1))
2984 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2992 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2993 if (ep->to_rtx == XEXP (x, 0))
2995 int size = GET_MODE_SIZE (mem_mode);
2997 /* If more bytes than MEM_MODE are pushed, account for them. */
2998 #ifdef PUSH_ROUNDING
2999 if (ep->to_rtx == stack_pointer_rtx)
3000 size = PUSH_ROUNDING (size);
3002 if (code == PRE_DEC || code == POST_DEC)
3008 /* Fall through to generic unary operation case. */
3009 case STRICT_LOW_PART:
3011 case SIGN_EXTEND: case ZERO_EXTEND:
3012 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3013 case FLOAT: case FIX:
3014 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3018 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3019 if (new != XEXP (x, 0))
3020 return gen_rtx (code, GET_MODE (x), new);
3024 /* Similar to above processing, but preserve SUBREG_WORD.
3025 Convert (subreg (mem)) to (mem) if not paradoxical.
3026 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3027 pseudo didn't get a hard reg, we must replace this with the
3028 eliminated version of the memory location because push_reloads
3029 may do the replacement in certain circumstances. */
3030 if (GET_CODE (SUBREG_REG (x)) == REG
3031 && (GET_MODE_SIZE (GET_MODE (x))
3032 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3033 && reg_equiv_memory_loc != 0
3034 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3036 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3039 /* If we didn't change anything, we must retain the pseudo. */
3040 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3041 new = SUBREG_REG (x);
3044 /* Otherwise, ensure NEW isn't shared in case we have to reload
3046 new = copy_rtx (new);
3048 /* In this case, we must show that the pseudo is used in this
3049 insn so that delete_output_reload will do the right thing. */
3050 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3051 && GET_CODE (insn) != INSN_LIST)
3052 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
3057 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3059 if (new != XEXP (x, 0))
3061 if (GET_CODE (new) == MEM
3062 && (GET_MODE_SIZE (GET_MODE (x))
3063 <= GET_MODE_SIZE (GET_MODE (new)))
3064 #ifdef LOAD_EXTEND_OP
3065 /* On these machines we will be reloading what is
3066 inside the SUBREG if it originally was a pseudo and
3067 the inner and outer modes are both a word or
3068 smaller. So leave the SUBREG then. */
3069 && ! (GET_CODE (SUBREG_REG (x)) == REG
3070 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
3071 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD
3072 && (GET_MODE_SIZE (GET_MODE (x))
3073 > GET_MODE_SIZE (GET_MODE (new)))
3074 && INTEGRAL_MODE_P (GET_MODE (new))
3075 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
3079 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3080 enum machine_mode mode = GET_MODE (x);
3082 if (BYTES_BIG_ENDIAN)
3083 offset += (MIN (UNITS_PER_WORD,
3084 GET_MODE_SIZE (GET_MODE (new)))
3085 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3087 PUT_MODE (new, mode);
3088 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3092 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3098 /* If using a register that is the source of an eliminate we still
3099 think can be performed, note it cannot be performed since we don't
3100 know how this register is used. */
3101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3102 if (ep->from_rtx == XEXP (x, 0))
3103 ep->can_eliminate = 0;
3105 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3106 if (new != XEXP (x, 0))
3107 return gen_rtx (code, GET_MODE (x), new);
3111 /* If clobbering a register that is the replacement register for an
3112 elimination we still think can be performed, note that it cannot
3113 be performed. Otherwise, we need not be concerned about it. */
3114 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3115 if (ep->to_rtx == XEXP (x, 0))
3116 ep->can_eliminate = 0;
3118 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3119 if (new != XEXP (x, 0))
3120 return gen_rtx (code, GET_MODE (x), new);
3126 /* Properly handle sharing input and constraint vectors. */
3127 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3129 /* When we come to a new vector not seen before,
3130 scan all its elements; keep the old vector if none
3131 of them changes; otherwise, make a copy. */
3132 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3133 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3134 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3135 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3138 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3139 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3142 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3143 new_asm_operands_vec = old_asm_operands_vec;
3145 new_asm_operands_vec
3146 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3149 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3150 if (new_asm_operands_vec == old_asm_operands_vec)
3153 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3154 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3155 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3156 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3157 ASM_OPERANDS_SOURCE_FILE (x),
3158 ASM_OPERANDS_SOURCE_LINE (x));
3159 new->volatil = x->volatil;
3164 /* Check for setting a register that we know about. */
3165 if (GET_CODE (SET_DEST (x)) == REG)
3167 /* See if this is setting the replacement register for an
3170 If DEST is the hard frame pointer, we do nothing because we
3171 assume that all assignments to the frame pointer are for
3172 non-local gotos and are being done at a time when they are valid
3173 and do not disturb anything else. Some machines want to
3174 eliminate a fake argument pointer (or even a fake frame pointer)
3175 with either the real frame or the stack pointer. Assignments to
3176 the hard frame pointer must not prevent this elimination. */
3178 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3180 if (ep->to_rtx == SET_DEST (x)
3181 && SET_DEST (x) != hard_frame_pointer_rtx)
3183 /* If it is being incremented, adjust the offset. Otherwise,
3184 this elimination can't be done. */
3185 rtx src = SET_SRC (x);
3187 if (GET_CODE (src) == PLUS
3188 && XEXP (src, 0) == SET_DEST (x)
3189 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3190 ep->offset -= INTVAL (XEXP (src, 1));
3192 ep->can_eliminate = 0;
3195 /* Now check to see we are assigning to a register that can be
3196 eliminated. If so, it must be as part of a PARALLEL, since we
3197 will not have been called if this is a single SET. So indicate
3198 that we can no longer eliminate this reg. */
3199 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3201 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3202 ep->can_eliminate = 0;
3205 /* Now avoid the loop below in this common case. */
3207 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3208 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3210 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3211 write a CLOBBER insn. */
3212 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3213 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3214 && GET_CODE (insn) != INSN_LIST)
3215 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3217 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3218 return gen_rtx (SET, VOIDmode, new0, new1);
3224 /* Our only special processing is to pass the mode of the MEM to our
3225 recursive call and copy the flags. While we are here, handle this
3226 case more efficiently. */
3227 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3228 if (new != XEXP (x, 0))
3230 new = gen_rtx (MEM, GET_MODE (x), new);
3231 new->volatil = x->volatil;
3232 new->unchanging = x->unchanging;
3233 new->in_struct = x->in_struct;
3240 /* Process each of our operands recursively. If any have changed, make a
3242 fmt = GET_RTX_FORMAT (code);
3243 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3247 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3248 if (new != XEXP (x, i) && ! copied)
3250 rtx new_x = rtx_alloc (code);
3251 bcopy ((char *) x, (char *) new_x,
3252 (sizeof (*new_x) - sizeof (new_x->fld)
3253 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3259 else if (*fmt == 'E')
3262 for (j = 0; j < XVECLEN (x, i); j++)
3264 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3265 if (new != XVECEXP (x, i, j) && ! copied_vec)
3267 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3271 rtx new_x = rtx_alloc (code);
3272 bcopy ((char *) x, (char *) new_x,
3273 (sizeof (*new_x) - sizeof (new_x->fld)
3274 + (sizeof (new_x->fld[0])
3275 * GET_RTX_LENGTH (code))));
3279 XVEC (x, i) = new_v;
3282 XVECEXP (x, i, j) = new;
3290 /* Scan INSN and eliminate all eliminable registers in it.
3292 If REPLACE is nonzero, do the replacement destructively. Also
3293 delete the insn as dead it if it is setting an eliminable register.
3295 If REPLACE is zero, do all our allocations in reload_obstack.
3297 If no eliminations were done and this insn doesn't require any elimination
3298 processing (these are not identical conditions: it might be updating sp,
3299 but not referencing fp; this needs to be seen during reload_as_needed so
3300 that the offset between fp and sp can be taken into consideration), zero
3301 is returned. Otherwise, 1 is returned. */
3304 eliminate_regs_in_insn (insn, replace)
3308 rtx old_body = PATTERN (insn);
3309 rtx old_set = single_set (insn);
3312 struct elim_table *ep;
3315 push_obstacks (&reload_obstack, &reload_obstack);
3317 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3318 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3320 /* Check for setting an eliminable register. */
3321 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3322 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3324 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3325 /* If this is setting the frame pointer register to the
3326 hardware frame pointer register and this is an elimination
3327 that will be done (tested above), this insn is really
3328 adjusting the frame pointer downward to compensate for
3329 the adjustment done before a nonlocal goto. */
3330 if (ep->from == FRAME_POINTER_REGNUM
3331 && ep->to == HARD_FRAME_POINTER_REGNUM)
3333 rtx src = SET_SRC (old_set);
3335 rtx prev_insn, prev_set;
3337 if (src == ep->to_rtx)
3339 else if (GET_CODE (src) == PLUS
3340 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3341 offset = INTVAL (XEXP (src, 0)), ok = 1;
3342 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3343 && (prev_set = single_set (prev_insn)) != 0
3344 && rtx_equal_p (SET_DEST (prev_set), src))
3346 src = SET_SRC (prev_set);
3347 if (src == ep->to_rtx)
3349 else if (GET_CODE (src) == PLUS
3350 && GET_CODE (XEXP (src, 0)) == CONST_INT
3351 && XEXP (src, 1) == ep->to_rtx)
3352 offset = INTVAL (XEXP (src, 0)), ok = 1;
3353 else if (GET_CODE (src) == PLUS
3354 && GET_CODE (XEXP (src, 1)) == CONST_INT
3355 && XEXP (src, 0) == ep->to_rtx)
3356 offset = INTVAL (XEXP (src, 1)), ok = 1;
3364 = plus_constant (ep->to_rtx, offset - ep->offset);
3366 /* First see if this insn remains valid when we
3367 make the change. If not, keep the INSN_CODE
3368 the same and let reload fit it up. */
3369 validate_change (insn, &SET_SRC (old_set), src, 1);
3370 validate_change (insn, &SET_DEST (old_set),
3372 if (! apply_change_group ())
3374 SET_SRC (old_set) = src;
3375 SET_DEST (old_set) = ep->to_rtx;
3385 /* In this case this insn isn't serving a useful purpose. We
3386 will delete it in reload_as_needed once we know that this
3387 elimination is, in fact, being done.
3389 If REPLACE isn't set, we can't delete this insn, but needn't
3390 process it since it won't be used unless something changes. */
3392 delete_dead_insn (insn);
3397 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3398 in the insn is the negative of the offset in FROM. Substitute
3399 (set (reg) (reg to)) for the insn and change its code.
3401 We have to do this here, rather than in eliminate_regs, do that we can
3402 change the insn code. */
3404 if (GET_CODE (SET_SRC (old_set)) == PLUS
3405 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3406 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3407 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3409 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3410 && ep->can_eliminate)
3412 /* We must stop at the first elimination that will be used.
3413 If this one would replace the PLUS with a REG, do it
3414 now. Otherwise, quit the loop and let eliminate_regs
3415 do its normal replacement. */
3416 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3418 /* We assume here that we don't need a PARALLEL of
3419 any CLOBBERs for this assignment. There's not
3420 much we can do if we do need it. */
3421 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3422 SET_DEST (old_set), ep->to_rtx);
3423 INSN_CODE (insn) = -1;
3432 old_asm_operands_vec = 0;
3434 /* Replace the body of this insn with a substituted form. If we changed
3435 something, return non-zero.
3437 If we are replacing a body that was a (set X (plus Y Z)), try to
3438 re-recognize the insn. We do this in case we had a simple addition
3439 but now can do this as a load-address. This saves an insn in this
3442 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3443 if (new_body != old_body)
3445 /* If we aren't replacing things permanently and we changed something,
3446 make another copy to ensure that all the RTL is new. Otherwise
3447 things can go wrong if find_reload swaps commutative operands
3448 and one is inside RTL that has been copied while the other is not. */
3450 /* Don't copy an asm_operands because (1) there's no need and (2)
3451 copy_rtx can't do it properly when there are multiple outputs. */
3452 if (! replace && asm_noperands (old_body) < 0)
3453 new_body = copy_rtx (new_body);
3455 /* If we had a move insn but now we don't, rerecognize it. This will
3456 cause spurious re-recognition if the old move had a PARALLEL since
3457 the new one still will, but we can't call single_set without
3458 having put NEW_BODY into the insn and the re-recognition won't
3459 hurt in this rare case. */
3461 && ((GET_CODE (SET_SRC (old_set)) == REG
3462 && (GET_CODE (new_body) != SET
3463 || GET_CODE (SET_SRC (new_body)) != REG))
3464 /* If this was a load from or store to memory, compare
3465 the MEM in recog_operand to the one in the insn. If they
3466 are not equal, then rerecognize the insn. */
3468 && ((GET_CODE (SET_SRC (old_set)) == MEM
3469 && SET_SRC (old_set) != recog_operand[1])
3470 || (GET_CODE (SET_DEST (old_set)) == MEM
3471 && SET_DEST (old_set) != recog_operand[0])))
3472 /* If this was an add insn before, rerecognize. */
3473 || GET_CODE (SET_SRC (old_set)) == PLUS))
3475 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3476 /* If recognition fails, store the new body anyway.
3477 It's normal to have recognition failures here
3478 due to bizarre memory addresses; reloading will fix them. */
3479 PATTERN (insn) = new_body;
3482 PATTERN (insn) = new_body;
3487 /* Loop through all elimination pairs. See if any have changed and
3488 recalculate the number not at initial offset.
3490 Compute the maximum offset (minimum offset if the stack does not
3491 grow downward) for each elimination pair.
3493 We also detect a cases where register elimination cannot be done,
3494 namely, if a register would be both changed and referenced outside a MEM
3495 in the resulting insn since such an insn is often undefined and, even if
3496 not, we cannot know what meaning will be given to it. Note that it is
3497 valid to have a register used in an address in an insn that changes it
3498 (presumably with a pre- or post-increment or decrement).
3500 If anything changes, return nonzero. */
3502 num_not_at_initial_offset = 0;
3503 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3505 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3506 ep->can_eliminate = 0;
3508 ep->ref_outside_mem = 0;
3510 if (ep->previous_offset != ep->offset)
3513 ep->previous_offset = ep->offset;
3514 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3515 num_not_at_initial_offset++;
3517 #ifdef STACK_GROWS_DOWNWARD
3518 ep->max_offset = MAX (ep->max_offset, ep->offset);
3520 ep->max_offset = MIN (ep->max_offset, ep->offset);
3525 /* If we changed something, perform elimination in REG_NOTES. This is
3526 needed even when REPLACE is zero because a REG_DEAD note might refer
3527 to a register that we eliminate and could cause a different number
3528 of spill registers to be needed in the final reload pass than in
3530 if (val && REG_NOTES (insn) != 0)
3531 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3539 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3540 replacement we currently believe is valid, mark it as not eliminable if X
3541 modifies DEST in any way other than by adding a constant integer to it.
3543 If DEST is the frame pointer, we do nothing because we assume that
3544 all assignments to the hard frame pointer are nonlocal gotos and are being
3545 done at a time when they are valid and do not disturb anything else.
3546 Some machines want to eliminate a fake argument pointer with either the
3547 frame or stack pointer. Assignments to the hard frame pointer must not
3548 prevent this elimination.
3550 Called via note_stores from reload before starting its passes to scan
3551 the insns of the function. */
3554 mark_not_eliminable (dest, x)
3560 /* A SUBREG of a hard register here is just changing its mode. We should
3561 not see a SUBREG of an eliminable hard register, but check just in
3563 if (GET_CODE (dest) == SUBREG)
3564 dest = SUBREG_REG (dest);
3566 if (dest == hard_frame_pointer_rtx)
3569 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3570 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3571 && (GET_CODE (x) != SET
3572 || GET_CODE (SET_SRC (x)) != PLUS
3573 || XEXP (SET_SRC (x), 0) != dest
3574 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3576 reg_eliminate[i].can_eliminate_previous
3577 = reg_eliminate[i].can_eliminate = 0;
3582 /* Kick all pseudos out of hard register REGNO.
3583 If GLOBAL is nonzero, try to find someplace else to put them.
3584 If DUMPFILE is nonzero, log actions taken on that file.
3586 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3587 because we found we can't eliminate some register. In the case, no pseudos
3588 are allowed to be in the register, even if they are only in a block that
3589 doesn't require spill registers, unlike the case when we are spilling this
3590 hard reg to produce another spill register.
3592 Return nonzero if any pseudos needed to be kicked out. */
3595 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3601 enum reg_class class = REGNO_REG_CLASS (regno);
3602 int something_changed = 0;
3605 SET_HARD_REG_BIT (forbidden_regs, regno);
3608 regs_ever_live[regno] = 1;
3610 /* Spill every pseudo reg that was allocated to this reg
3611 or to something that overlaps this reg. */
3613 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3614 if (reg_renumber[i] >= 0
3615 && reg_renumber[i] <= regno
3617 + HARD_REGNO_NREGS (reg_renumber[i],
3618 PSEUDO_REGNO_MODE (i))
3621 /* If this register belongs solely to a basic block which needed no
3622 spilling of any class that this register is contained in,
3623 leave it be, unless we are spilling this register because
3624 it was a hard register that can't be eliminated. */
3626 if (! cant_eliminate
3627 && basic_block_needs[0]
3628 && reg_basic_block[i] >= 0
3629 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3633 for (p = reg_class_superclasses[(int) class];
3634 *p != LIM_REG_CLASSES; p++)
3635 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3638 if (*p == LIM_REG_CLASSES)
3642 /* Mark it as no longer having a hard register home. */
3643 reg_renumber[i] = -1;
3644 /* We will need to scan everything again. */
3645 something_changed = 1;
3647 retry_global_alloc (i, forbidden_regs);
3649 alter_reg (i, regno);
3652 if (reg_renumber[i] == -1)
3653 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3655 fprintf (dumpfile, " Register %d now in %d.\n\n",
3656 i, reg_renumber[i]);
3659 for (i = 0; i < scratch_list_length; i++)
3661 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3663 if (! cant_eliminate && basic_block_needs[0]
3664 && ! basic_block_needs[(int) class][scratch_block[i]])
3668 for (p = reg_class_superclasses[(int) class];
3669 *p != LIM_REG_CLASSES; p++)
3670 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3673 if (*p == LIM_REG_CLASSES)
3676 PUT_CODE (scratch_list[i], SCRATCH);
3677 scratch_list[i] = 0;
3678 something_changed = 1;
3683 return something_changed;
3686 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3687 Also mark any hard registers used to store user variables as
3688 forbidden from being used for spill registers. */
3691 scan_paradoxical_subregs (x)
3696 register enum rtx_code code = GET_CODE (x);
3701 #ifdef SMALL_REGISTER_CLASSES
3702 if (SMALL_REGISTER_CLASSES
3703 && REGNO (x) < FIRST_PSEUDO_REGISTER
3704 && REG_USERVAR_P (x))
3705 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3721 if (GET_CODE (SUBREG_REG (x)) == REG
3722 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3723 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3724 = GET_MODE_SIZE (GET_MODE (x));
3728 fmt = GET_RTX_FORMAT (code);
3729 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3732 scan_paradoxical_subregs (XEXP (x, i));
3733 else if (fmt[i] == 'E')
3736 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3737 scan_paradoxical_subregs (XVECEXP (x, i, j));
3743 hard_reg_use_compare (p1p, p2p)
3744 const GENERIC_PTR p1p;
3745 const GENERIC_PTR p2p;
3747 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3748 *p2 = (struct hard_reg_n_uses *)p2p;
3749 int tem = p1->uses - p2->uses;
3750 if (tem != 0) return tem;
3751 /* If regs are equally good, sort by regno,
3752 so that the results of qsort leave nothing to chance. */
3753 return p1->regno - p2->regno;
3756 /* Choose the order to consider regs for use as reload registers
3757 based on how much trouble would be caused by spilling one.
3758 Store them in order of decreasing preference in potential_reload_regs. */
3761 order_regs_for_reload (global)
3768 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3770 CLEAR_HARD_REG_SET (bad_spill_regs);
3772 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3773 potential_reload_regs[i] = -1;
3775 /* Count number of uses of each hard reg by pseudo regs allocated to it
3776 and then order them by decreasing use. */
3778 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3780 hard_reg_n_uses[i].uses = 0;
3781 hard_reg_n_uses[i].regno = i;
3784 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3786 int regno = reg_renumber[i];
3789 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3792 /* If allocated by local-alloc, show more uses since
3793 we're not going to be able to reallocate it, but
3794 we might if allocated by global alloc. */
3795 if (global && reg_allocno[i] < 0)
3796 hard_reg_n_uses[regno].uses += (reg_n_refs[i] + 1) / 2;
3798 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3801 large += reg_n_refs[i];
3804 /* Now fixed registers (which cannot safely be used for reloading)
3805 get a very high use count so they will be considered least desirable.
3806 Registers used explicitly in the rtl code are almost as bad. */
3808 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3812 hard_reg_n_uses[i].uses += 2 * large + 2;
3813 SET_HARD_REG_BIT (bad_spill_regs, i);
3815 else if (regs_explicitly_used[i])
3817 hard_reg_n_uses[i].uses += large + 1;
3818 /* ??? We are doing this here because of the potential that
3819 bad code may be generated if a register explicitly used in
3820 an insn was used as a spill register for that insn. But
3821 not using these are spill registers may lose on some machine.
3822 We'll have to see how this works out. */
3823 #ifdef SMALL_REGISTER_CLASSES
3824 if (! SMALL_REGISTER_CLASSES)
3826 SET_HARD_REG_BIT (bad_spill_regs, i);
3829 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3830 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3832 #ifdef ELIMINABLE_REGS
3833 /* If registers other than the frame pointer are eliminable, mark them as
3835 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3837 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3838 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3842 /* Prefer registers not so far used, for use in temporary loading.
3843 Among them, if REG_ALLOC_ORDER is defined, use that order.
3844 Otherwise, prefer registers not preserved by calls. */
3846 #ifdef REG_ALLOC_ORDER
3847 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3849 int regno = reg_alloc_order[i];
3851 if (hard_reg_n_uses[regno].uses == 0)
3852 potential_reload_regs[o++] = regno;
3855 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3857 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3858 potential_reload_regs[o++] = i;
3860 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3862 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3863 potential_reload_regs[o++] = i;
3867 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3868 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3870 /* Now add the regs that are already used,
3871 preferring those used less often. The fixed and otherwise forbidden
3872 registers will be at the end of this list. */
3874 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3875 if (hard_reg_n_uses[i].uses != 0)
3876 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3879 /* Used in reload_as_needed to sort the spilled regs. */
3882 compare_spill_regs (r1p, r2p)
3883 const GENERIC_PTR r1p;
3884 const GENERIC_PTR r2p;
3886 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3890 /* Reload pseudo-registers into hard regs around each insn as needed.
3891 Additional register load insns are output before the insn that needs it
3892 and perhaps store insns after insns that modify the reloaded pseudo reg.
3894 reg_last_reload_reg and reg_reloaded_contents keep track of
3895 which registers are already available in reload registers.
3896 We update these for the reloads that we perform,
3897 as the insns are scanned. */
3900 reload_as_needed (first, live_known)
3910 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3911 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3912 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3913 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3914 reg_has_output_reload = (char *) alloca (max_regno);
3915 for (i = 0; i < n_spills; i++)
3917 reg_reloaded_contents[i] = -1;
3918 reg_reloaded_insn[i] = 0;
3921 /* Reset all offsets on eliminable registers to their initial values. */
3922 #ifdef ELIMINABLE_REGS
3923 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3925 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3926 reg_eliminate[i].initial_offset);
3927 reg_eliminate[i].previous_offset
3928 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3931 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3932 reg_eliminate[0].previous_offset
3933 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3936 num_not_at_initial_offset = 0;
3938 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
3939 pack registers with group needs. */
3942 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
3943 for (i = 0; i < n_spills; i++)
3944 spill_reg_order[spill_regs[i]] = i;
3947 for (insn = first; insn;)
3949 register rtx next = NEXT_INSN (insn);
3951 /* Notice when we move to a new basic block. */
3952 if (live_known && this_block + 1 < n_basic_blocks
3953 && insn == basic_block_head[this_block+1])
3956 /* If we pass a label, copy the offsets from the label information
3957 into the current offsets of each elimination. */
3958 if (GET_CODE (insn) == CODE_LABEL)
3960 num_not_at_initial_offset = 0;
3961 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3963 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3964 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3965 if (reg_eliminate[i].can_eliminate
3966 && (reg_eliminate[i].offset
3967 != reg_eliminate[i].initial_offset))
3968 num_not_at_initial_offset++;
3972 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3974 rtx avoid_return_reg = 0;
3975 rtx oldpat = PATTERN (insn);
3977 #ifdef SMALL_REGISTER_CLASSES
3978 /* Set avoid_return_reg if this is an insn
3979 that might use the value of a function call. */
3980 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
3982 if (GET_CODE (PATTERN (insn)) == SET)
3983 after_call = SET_DEST (PATTERN (insn));
3984 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3985 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3986 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3990 else if (SMALL_REGISTER_CLASSES
3992 && !(GET_CODE (PATTERN (insn)) == SET
3993 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3995 if (reg_referenced_p (after_call, PATTERN (insn)))
3996 avoid_return_reg = after_call;
3999 #endif /* SMALL_REGISTER_CLASSES */
4001 /* If this is a USE and CLOBBER of a MEM, ensure that any
4002 references to eliminable registers have been removed. */
4004 if ((GET_CODE (PATTERN (insn)) == USE
4005 || GET_CODE (PATTERN (insn)) == CLOBBER)
4006 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4007 XEXP (XEXP (PATTERN (insn), 0), 0)
4008 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4009 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
4011 /* If we need to do register elimination processing, do so.
4012 This might delete the insn, in which case we are done. */
4013 if (num_eliminable && GET_MODE (insn) == QImode)
4015 eliminate_regs_in_insn (insn, 1);
4016 if (GET_CODE (insn) == NOTE)
4023 if (GET_MODE (insn) == VOIDmode)
4025 /* First find the pseudo regs that must be reloaded for this insn.
4026 This info is returned in the tables reload_... (see reload.h).
4027 Also modify the body of INSN by substituting RELOAD
4028 rtx's for those pseudo regs. */
4031 bzero (reg_has_output_reload, max_regno);
4032 CLEAR_HARD_REG_SET (reg_is_output_reload);
4034 find_reloads (insn, 1, spill_indirect_levels, live_known,
4040 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4044 /* If this block has not had spilling done for a
4045 particular clas and we have any non-optionals that need a
4046 spill reg in that class, abort. */
4048 for (class = 0; class < N_REG_CLASSES; class++)
4049 if (basic_block_needs[class] != 0
4050 && basic_block_needs[class][this_block] == 0)
4051 for (i = 0; i < n_reloads; i++)
4052 if (class == (int) reload_reg_class[i]
4053 && reload_reg_rtx[i] == 0
4054 && ! reload_optional[i]
4055 && (reload_in[i] != 0 || reload_out[i] != 0
4056 || reload_secondary_p[i] != 0))
4057 fatal_insn ("Non-optional registers need a spill register", insn);
4059 /* Now compute which reload regs to reload them into. Perhaps
4060 reusing reload regs from previous insns, or else output
4061 load insns to reload them. Maybe output store insns too.
4062 Record the choices of reload reg in reload_reg_rtx. */
4063 choose_reload_regs (insn, avoid_return_reg);
4065 #ifdef SMALL_REGISTER_CLASSES
4066 /* Merge any reloads that we didn't combine for fear of
4067 increasing the number of spill registers needed but now
4068 discover can be safely merged. */
4069 if (SMALL_REGISTER_CLASSES)
4070 merge_assigned_reloads (insn);
4073 /* Generate the insns to reload operands into or out of
4074 their reload regs. */
4075 emit_reload_insns (insn);
4077 /* Substitute the chosen reload regs from reload_reg_rtx
4078 into the insn's body (or perhaps into the bodies of other
4079 load and store insn that we just made for reloading
4080 and that we moved the structure into). */
4083 /* If this was an ASM, make sure that all the reload insns
4084 we have generated are valid. If not, give an error
4087 if (asm_noperands (PATTERN (insn)) >= 0)
4088 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4089 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4090 && (recog_memoized (p) < 0
4091 || (insn_extract (p),
4092 ! constrain_operands (INSN_CODE (p), 1))))
4094 error_for_asm (insn,
4095 "`asm' operand requires impossible reload");
4097 NOTE_SOURCE_FILE (p) = 0;
4098 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4101 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4102 is no longer validly lying around to save a future reload.
4103 Note that this does not detect pseudos that were reloaded
4104 for this insn in order to be stored in
4105 (obeying register constraints). That is correct; such reload
4106 registers ARE still valid. */
4107 note_stores (oldpat, forget_old_reloads_1);
4109 /* There may have been CLOBBER insns placed after INSN. So scan
4110 between INSN and NEXT and use them to forget old reloads. */
4111 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4112 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4113 note_stores (PATTERN (x), forget_old_reloads_1);
4116 /* Likewise for regs altered by auto-increment in this insn.
4117 But note that the reg-notes are not changed by reloading:
4118 they still contain the pseudo-regs, not the spill regs. */
4119 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4120 if (REG_NOTE_KIND (x) == REG_INC)
4122 /* See if this pseudo reg was reloaded in this insn.
4123 If so, its last-reload info is still valid
4124 because it is based on this insn's reload. */
4125 for (i = 0; i < n_reloads; i++)
4126 if (reload_out[i] == XEXP (x, 0))
4130 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4134 /* A reload reg's contents are unknown after a label. */
4135 if (GET_CODE (insn) == CODE_LABEL)
4136 for (i = 0; i < n_spills; i++)
4138 reg_reloaded_contents[i] = -1;
4139 reg_reloaded_insn[i] = 0;
4142 /* Don't assume a reload reg is still good after a call insn
4143 if it is a call-used reg. */
4144 else if (GET_CODE (insn) == CALL_INSN)
4145 for (i = 0; i < n_spills; i++)
4146 if (call_used_regs[spill_regs[i]])
4148 reg_reloaded_contents[i] = -1;
4149 reg_reloaded_insn[i] = 0;
4152 /* In case registers overlap, allow certain insns to invalidate
4153 particular hard registers. */
4155 #ifdef INSN_CLOBBERS_REGNO_P
4156 for (i = 0 ; i < n_spills ; i++)
4157 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
4159 reg_reloaded_contents[i] = -1;
4160 reg_reloaded_insn[i] = 0;
4172 /* Discard all record of any value reloaded from X,
4173 or reloaded in X from someplace else;
4174 unless X is an output reload reg of the current insn.
4176 X may be a hard reg (the reload reg)
4177 or it may be a pseudo reg that was reloaded from. */
4180 forget_old_reloads_1 (x, ignored)
4188 /* note_stores does give us subregs of hard regs. */
4189 while (GET_CODE (x) == SUBREG)
4191 offset += SUBREG_WORD (x);
4195 if (GET_CODE (x) != REG)
4198 regno = REGNO (x) + offset;
4200 if (regno >= FIRST_PSEUDO_REGISTER)
4205 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4206 /* Storing into a spilled-reg invalidates its contents.
4207 This can happen if a block-local pseudo is allocated to that reg
4208 and it wasn't spilled because this block's total need is 0.
4209 Then some insn might have an optional reload and use this reg. */
4210 for (i = 0; i < nr; i++)
4211 if (spill_reg_order[regno + i] >= 0
4212 /* But don't do this if the reg actually serves as an output
4213 reload reg in the current instruction. */
4215 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4217 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4218 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4222 /* Since value of X has changed,
4223 forget any value previously copied from it. */
4226 /* But don't forget a copy if this is the output reload
4227 that establishes the copy's validity. */
4228 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4229 reg_last_reload_reg[regno + nr] = 0;
4232 /* For each reload, the mode of the reload register. */
4233 static enum machine_mode reload_mode[MAX_RELOADS];
4235 /* For each reload, the largest number of registers it will require. */
4236 static int reload_nregs[MAX_RELOADS];
4238 /* Comparison function for qsort to decide which of two reloads
4239 should be handled first. *P1 and *P2 are the reload numbers. */
4242 reload_reg_class_lower (r1p, r2p)
4243 const GENERIC_PTR r1p;
4244 const GENERIC_PTR r2p;
4246 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4249 /* Consider required reloads before optional ones. */
4250 t = reload_optional[r1] - reload_optional[r2];
4254 /* Count all solitary classes before non-solitary ones. */
4255 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4256 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4260 /* Aside from solitaires, consider all multi-reg groups first. */
4261 t = reload_nregs[r2] - reload_nregs[r1];
4265 /* Consider reloads in order of increasing reg-class number. */
4266 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4270 /* If reloads are equally urgent, sort by reload number,
4271 so that the results of qsort leave nothing to chance. */
4275 /* The following HARD_REG_SETs indicate when each hard register is
4276 used for a reload of various parts of the current insn. */
4278 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4279 static HARD_REG_SET reload_reg_used;
4280 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4281 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4282 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4283 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4284 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4285 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4286 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4287 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4288 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4289 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4290 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4291 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4292 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4293 static HARD_REG_SET reload_reg_used_in_op_addr;
4294 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4295 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4296 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4297 static HARD_REG_SET reload_reg_used_in_insn;
4298 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4299 static HARD_REG_SET reload_reg_used_in_other_addr;
4301 /* If reg is in use as a reload reg for any sort of reload. */
4302 static HARD_REG_SET reload_reg_used_at_all;
4304 /* If reg is use as an inherited reload. We just mark the first register
4306 static HARD_REG_SET reload_reg_used_for_inherit;
4308 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4309 TYPE. MODE is used to indicate how many consecutive regs are
4313 mark_reload_reg_in_use (regno, opnum, type, mode)
4316 enum reload_type type;
4317 enum machine_mode mode;
4319 int nregs = HARD_REGNO_NREGS (regno, mode);
4322 for (i = regno; i < nregs + regno; i++)
4327 SET_HARD_REG_BIT (reload_reg_used, i);
4330 case RELOAD_FOR_INPUT_ADDRESS:
4331 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4334 case RELOAD_FOR_INPADDR_ADDRESS:
4335 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4338 case RELOAD_FOR_OUTPUT_ADDRESS:
4339 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4342 case RELOAD_FOR_OUTADDR_ADDRESS:
4343 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4346 case RELOAD_FOR_OPERAND_ADDRESS:
4347 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4350 case RELOAD_FOR_OPADDR_ADDR:
4351 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4354 case RELOAD_FOR_OTHER_ADDRESS:
4355 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4358 case RELOAD_FOR_INPUT:
4359 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4362 case RELOAD_FOR_OUTPUT:
4363 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4366 case RELOAD_FOR_INSN:
4367 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4371 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4375 /* Similarly, but show REGNO is no longer in use for a reload. */
4378 clear_reload_reg_in_use (regno, opnum, type, mode)
4381 enum reload_type type;
4382 enum machine_mode mode;
4384 int nregs = HARD_REGNO_NREGS (regno, mode);
4387 for (i = regno; i < nregs + regno; i++)
4392 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4395 case RELOAD_FOR_INPUT_ADDRESS:
4396 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4399 case RELOAD_FOR_INPADDR_ADDRESS:
4400 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4403 case RELOAD_FOR_OUTPUT_ADDRESS:
4404 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4407 case RELOAD_FOR_OUTADDR_ADDRESS:
4408 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4411 case RELOAD_FOR_OPERAND_ADDRESS:
4412 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4415 case RELOAD_FOR_OPADDR_ADDR:
4416 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4419 case RELOAD_FOR_OTHER_ADDRESS:
4420 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4423 case RELOAD_FOR_INPUT:
4424 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4427 case RELOAD_FOR_OUTPUT:
4428 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4431 case RELOAD_FOR_INSN:
4432 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4438 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4439 specified by OPNUM and TYPE. */
4442 reload_reg_free_p (regno, opnum, type)
4445 enum reload_type type;
4449 /* In use for a RELOAD_OTHER means it's not available for anything. */
4450 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4456 /* In use for anything means we can't use it for RELOAD_OTHER. */
4457 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4458 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4462 for (i = 0; i < reload_n_operands; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4468 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4473 case RELOAD_FOR_INPUT:
4474 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4475 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4481 /* If it is used for some other input, can't use it. */
4482 for (i = 0; i < reload_n_operands; i++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4486 /* If it is used in a later operand's address, can't use it. */
4487 for (i = opnum + 1; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4494 case RELOAD_FOR_INPUT_ADDRESS:
4495 /* Can't use a register if it is used for an input address for this
4496 operand or used as an input in an earlier one. */
4497 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4498 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4501 for (i = 0; i < opnum; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4507 case RELOAD_FOR_INPADDR_ADDRESS:
4508 /* Can't use a register if it is used for an input address
4509 address for this operand or used as an input in an earlier
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4514 for (i = 0; i < opnum; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4520 case RELOAD_FOR_OUTPUT_ADDRESS:
4521 /* Can't use a register if it is used for an output address for this
4522 operand or used as an output in this or a later operand. */
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4526 for (i = opnum; i < reload_n_operands; i++)
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4532 case RELOAD_FOR_OUTADDR_ADDRESS:
4533 /* Can't use a register if it is used for an output address
4534 address for this operand or used as an output in this or a
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4539 for (i = opnum; i < reload_n_operands; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4545 case RELOAD_FOR_OPERAND_ADDRESS:
4546 for (i = 0; i < reload_n_operands; i++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4550 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4551 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4553 case RELOAD_FOR_OPADDR_ADDR:
4554 for (i = 0; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4558 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4560 case RELOAD_FOR_OUTPUT:
4561 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4562 outputs, or an operand address for this or an earlier output. */
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4566 for (i = 0; i < reload_n_operands; i++)
4567 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4570 for (i = 0; i <= opnum; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4577 case RELOAD_FOR_INSN:
4578 for (i = 0; i < reload_n_operands; i++)
4579 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4583 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4584 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4586 case RELOAD_FOR_OTHER_ADDRESS:
4587 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4592 /* Return 1 if the value in reload reg REGNO, as used by a reload
4593 needed for the part of the insn specified by OPNUM and TYPE,
4594 is not in use for a reload in any prior part of the insn.
4596 We can assume that the reload reg was already tested for availability
4597 at the time it is needed, and we should not check this again,
4598 in case the reg has already been marked in use. */
4601 reload_reg_free_before_p (regno, opnum, type)
4604 enum reload_type type;
4610 case RELOAD_FOR_OTHER_ADDRESS:
4611 /* These always come first. */
4615 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4617 /* If this use is for part of the insn,
4618 check the reg is not in use for any prior part. It is tempting
4619 to try to do this by falling through from objecs that occur
4620 later in the insn to ones that occur earlier, but that will not
4621 correctly take into account the fact that here we MUST ignore
4622 things that would prevent the register from being allocated in
4623 the first place, since we know that it was allocated. */
4625 case RELOAD_FOR_OUTPUT_ADDRESS:
4626 case RELOAD_FOR_OUTADDR_ADDRESS:
4627 /* Earlier reloads are for earlier outputs or their addresses,
4628 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4629 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4631 for (i = 0; i < opnum; i++)
4632 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4633 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4634 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4640 for (i = 0; i < reload_n_operands; i++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4646 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4647 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4648 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4650 case RELOAD_FOR_OUTPUT:
4651 /* This can't be used in the output address for this operand and
4652 anything that can't be used for it, except that we've already
4653 tested for RELOAD_FOR_INSN objects. */
4655 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4659 for (i = 0; i < opnum; i++)
4660 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4661 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4665 for (i = 0; i < reload_n_operands; i++)
4666 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4667 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4668 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4672 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4674 case RELOAD_FOR_OPERAND_ADDRESS:
4675 case RELOAD_FOR_OPADDR_ADDR:
4676 case RELOAD_FOR_INSN:
4677 /* These can't conflict with inputs, or each other, so all we have to
4678 test is input addresses and the addresses of OTHER items. */
4680 for (i = 0; i < reload_n_operands; i++)
4681 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4682 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4685 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4687 case RELOAD_FOR_INPUT:
4688 /* The only things earlier are the address for this and
4689 earlier inputs, other inputs (which we know we don't conflict
4690 with), and addresses of RELOAD_OTHER objects. */
4692 for (i = 0; i <= opnum; i++)
4693 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4694 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4697 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4699 case RELOAD_FOR_INPUT_ADDRESS:
4700 case RELOAD_FOR_INPADDR_ADDRESS:
4701 /* Similarly, all we have to check is for use in earlier inputs'
4703 for (i = 0; i < opnum; i++)
4704 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4705 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4708 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4713 /* Return 1 if the value in reload reg REGNO, as used by a reload
4714 needed for the part of the insn specified by OPNUM and TYPE,
4715 is still available in REGNO at the end of the insn.
4717 We can assume that the reload reg was already tested for availability
4718 at the time it is needed, and we should not check this again,
4719 in case the reg has already been marked in use. */
4722 reload_reg_reaches_end_p (regno, opnum, type)
4725 enum reload_type type;
4732 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4733 its value must reach the end. */
4736 /* If this use is for part of the insn,
4737 its value reaches if no subsequent part uses the same register.
4738 Just like the above function, don't try to do this with lots
4741 case RELOAD_FOR_OTHER_ADDRESS:
4742 /* Here we check for everything else, since these don't conflict
4743 with anything else and everything comes later. */
4745 for (i = 0; i < reload_n_operands; i++)
4746 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4747 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4748 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4749 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4750 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4751 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4754 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4755 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4756 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4758 case RELOAD_FOR_INPUT_ADDRESS:
4759 case RELOAD_FOR_INPADDR_ADDRESS:
4760 /* Similar, except that we check only for this and subsequent inputs
4761 and the address of only subsequent inputs and we do not need
4762 to check for RELOAD_OTHER objects since they are known not to
4765 for (i = opnum; i < reload_n_operands; i++)
4766 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4769 for (i = opnum + 1; i < reload_n_operands; i++)
4770 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4774 for (i = 0; i < reload_n_operands; i++)
4775 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4776 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4777 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4780 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4783 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4784 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4786 case RELOAD_FOR_INPUT:
4787 /* Similar to input address, except we start at the next operand for
4788 both input and input address and we do not check for
4789 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4792 for (i = opnum + 1; i < reload_n_operands; i++)
4793 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4795 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4798 /* ... fall through ... */
4800 case RELOAD_FOR_OPERAND_ADDRESS:
4801 /* Check outputs and their addresses. */
4803 for (i = 0; i < reload_n_operands; i++)
4804 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4806 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4811 case RELOAD_FOR_OPADDR_ADDR:
4812 for (i = 0; i < reload_n_operands; i++)
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4815 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4818 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4819 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4821 case RELOAD_FOR_INSN:
4822 /* These conflict with other outputs with RELOAD_OTHER. So
4823 we need only check for output addresses. */
4827 /* ... fall through ... */
4829 case RELOAD_FOR_OUTPUT:
4830 case RELOAD_FOR_OUTPUT_ADDRESS:
4831 case RELOAD_FOR_OUTADDR_ADDRESS:
4832 /* We already know these can't conflict with a later output. So the
4833 only thing to check are later output addresses. */
4834 for (i = opnum + 1; i < reload_n_operands; i++)
4835 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4836 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4845 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4848 This function uses the same algorithm as reload_reg_free_p above. */
4851 reloads_conflict (r1, r2)
4854 enum reload_type r1_type = reload_when_needed[r1];
4855 enum reload_type r2_type = reload_when_needed[r2];
4856 int r1_opnum = reload_opnum[r1];
4857 int r2_opnum = reload_opnum[r2];
4859 /* RELOAD_OTHER conflicts with everything. */
4860 if (r2_type == RELOAD_OTHER)
4863 /* Otherwise, check conflicts differently for each type. */
4867 case RELOAD_FOR_INPUT:
4868 return (r2_type == RELOAD_FOR_INSN
4869 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4870 || r2_type == RELOAD_FOR_OPADDR_ADDR
4871 || r2_type == RELOAD_FOR_INPUT
4872 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4873 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4874 && r2_opnum > r1_opnum));
4876 case RELOAD_FOR_INPUT_ADDRESS:
4877 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4878 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4880 case RELOAD_FOR_INPADDR_ADDRESS:
4881 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4882 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4884 case RELOAD_FOR_OUTPUT_ADDRESS:
4885 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4886 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4888 case RELOAD_FOR_OUTADDR_ADDRESS:
4889 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4890 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4892 case RELOAD_FOR_OPERAND_ADDRESS:
4893 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4894 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4896 case RELOAD_FOR_OPADDR_ADDR:
4897 return (r2_type == RELOAD_FOR_INPUT
4898 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4900 case RELOAD_FOR_OUTPUT:
4901 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4902 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4903 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4904 && r2_opnum >= r1_opnum));
4906 case RELOAD_FOR_INSN:
4907 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4908 || r2_type == RELOAD_FOR_INSN
4909 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4911 case RELOAD_FOR_OTHER_ADDRESS:
4912 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4922 /* Vector of reload-numbers showing the order in which the reloads should
4924 short reload_order[MAX_RELOADS];
4926 /* Indexed by reload number, 1 if incoming value
4927 inherited from previous insns. */
4928 char reload_inherited[MAX_RELOADS];
4930 /* For an inherited reload, this is the insn the reload was inherited from,
4931 if we know it. Otherwise, this is 0. */
4932 rtx reload_inheritance_insn[MAX_RELOADS];
4934 /* If non-zero, this is a place to get the value of the reload,
4935 rather than using reload_in. */
4936 rtx reload_override_in[MAX_RELOADS];
4938 /* For each reload, the index in spill_regs of the spill register used,
4939 or -1 if we did not need one of the spill registers for this reload. */
4940 int reload_spill_index[MAX_RELOADS];
4942 /* Find a spill register to use as a reload register for reload R.
4943 LAST_RELOAD is non-zero if this is the last reload for the insn being
4946 Set reload_reg_rtx[R] to the register allocated.
4948 If NOERROR is nonzero, we return 1 if successful,
4949 or 0 if we couldn't find a spill reg and we didn't change anything. */
4952 allocate_reload_reg (r, insn, last_reload, noerror)
4964 /* If we put this reload ahead, thinking it is a group,
4965 then insist on finding a group. Otherwise we can grab a
4966 reg that some other reload needs.
4967 (That can happen when we have a 68000 DATA_OR_FP_REG
4968 which is a group of data regs or one fp reg.)
4969 We need not be so restrictive if there are no more reloads
4972 ??? Really it would be nicer to have smarter handling
4973 for that kind of reg class, where a problem like this is normal.
4974 Perhaps those classes should be avoided for reloading
4975 by use of more alternatives. */
4977 int force_group = reload_nregs[r] > 1 && ! last_reload;
4979 /* If we want a single register and haven't yet found one,
4980 take any reg in the right class and not in use.
4981 If we want a consecutive group, here is where we look for it.
4983 We use two passes so we can first look for reload regs to
4984 reuse, which are already in use for other reloads in this insn,
4985 and only then use additional registers.
4986 I think that maximizing reuse is needed to make sure we don't
4987 run out of reload regs. Suppose we have three reloads, and
4988 reloads A and B can share regs. These need two regs.
4989 Suppose A and B are given different regs.
4990 That leaves none for C. */
4991 for (pass = 0; pass < 2; pass++)
4993 /* I is the index in spill_regs.
4994 We advance it round-robin between insns to use all spill regs
4995 equally, so that inherited reloads have a chance
4996 of leapfrogging each other. Don't do this, however, when we have
4997 group needs and failure would be fatal; if we only have a relatively
4998 small number of spill registers, and more than one of them has
4999 group needs, then by starting in the middle, we may end up
5000 allocating the first one in such a way that we are not left with
5001 sufficient groups to handle the rest. */
5003 if (noerror || ! force_group)
5008 for (count = 0; count < n_spills; count++)
5010 int class = (int) reload_reg_class[r];
5012 i = (i + 1) % n_spills;
5014 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
5015 reload_when_needed[r])
5016 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5017 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5018 /* Look first for regs to share, then for unshared. But
5019 don't share regs used for inherited reloads; they are
5020 the ones we want to preserve. */
5022 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5024 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5027 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5028 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5029 (on 68000) got us two FP regs. If NR is 1,
5030 we would reject both of them. */
5032 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5033 /* If we need only one reg, we have already won. */
5036 /* But reject a single reg if we demand a group. */
5041 /* Otherwise check that as many consecutive regs as we need
5043 Also, don't use for a group registers that are
5044 needed for nongroups. */
5045 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5048 regno = spill_regs[i] + nr - 1;
5049 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5050 && spill_reg_order[regno] >= 0
5051 && reload_reg_free_p (regno, reload_opnum[r],
5052 reload_when_needed[r])
5053 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5063 /* If we found something on pass 1, omit pass 2. */
5064 if (count < n_spills)
5068 /* We should have found a spill register by now. */
5069 if (count == n_spills)
5076 /* I is the index in SPILL_REG_RTX of the reload register we are to
5077 allocate. Get an rtx for it and find its register number. */
5079 new = spill_reg_rtx[i];
5081 if (new == 0 || GET_MODE (new) != reload_mode[r])
5082 spill_reg_rtx[i] = new
5083 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
5085 regno = true_regnum (new);
5087 /* Detect when the reload reg can't hold the reload mode.
5088 This used to be one `if', but Sequent compiler can't handle that. */
5089 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5091 enum machine_mode test_mode = VOIDmode;
5093 test_mode = GET_MODE (reload_in[r]);
5094 /* If reload_in[r] has VOIDmode, it means we will load it
5095 in whatever mode the reload reg has: to wit, reload_mode[r].
5096 We have already tested that for validity. */
5097 /* Aside from that, we need to test that the expressions
5098 to reload from or into have modes which are valid for this
5099 reload register. Otherwise the reload insns would be invalid. */
5100 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5101 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5102 if (! (reload_out[r] != 0
5103 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5105 /* The reg is OK. */
5108 /* Mark as in use for this insn the reload regs we use
5110 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5111 reload_when_needed[r], reload_mode[r]);
5113 reload_reg_rtx[r] = new;
5114 reload_spill_index[r] = i;
5119 /* The reg is not OK. */
5124 if (asm_noperands (PATTERN (insn)) < 0)
5125 /* It's the compiler's fault. */
5126 fatal_insn ("Could not find a spill register", insn);
5128 /* It's the user's fault; the operand's mode and constraint
5129 don't match. Disable this reload so we don't crash in final. */
5130 error_for_asm (insn,
5131 "`asm' operand constraint incompatible with operand size");
5134 reload_reg_rtx[r] = 0;
5135 reload_optional[r] = 1;
5136 reload_secondary_p[r] = 1;
5141 /* Assign hard reg targets for the pseudo-registers we must reload
5142 into hard regs for this insn.
5143 Also output the instructions to copy them in and out of the hard regs.
5145 For machines with register classes, we are responsible for
5146 finding a reload reg in the proper class. */
5149 choose_reload_regs (insn, avoid_return_reg)
5151 rtx avoid_return_reg;
5154 int max_group_size = 1;
5155 enum reg_class group_class = NO_REGS;
5158 rtx save_reload_reg_rtx[MAX_RELOADS];
5159 char save_reload_inherited[MAX_RELOADS];
5160 rtx save_reload_inheritance_insn[MAX_RELOADS];
5161 rtx save_reload_override_in[MAX_RELOADS];
5162 int save_reload_spill_index[MAX_RELOADS];
5163 HARD_REG_SET save_reload_reg_used;
5164 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5165 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5166 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5167 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5168 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5169 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5170 HARD_REG_SET save_reload_reg_used_in_op_addr;
5171 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5172 HARD_REG_SET save_reload_reg_used_in_insn;
5173 HARD_REG_SET save_reload_reg_used_in_other_addr;
5174 HARD_REG_SET save_reload_reg_used_at_all;
5176 bzero (reload_inherited, MAX_RELOADS);
5177 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5178 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5180 CLEAR_HARD_REG_SET (reload_reg_used);
5181 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5183 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5184 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5185 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5187 for (i = 0; i < reload_n_operands; i++)
5189 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5190 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5191 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5192 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5193 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5194 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5197 #ifdef SMALL_REGISTER_CLASSES
5198 /* Don't bother with avoiding the return reg
5199 if we have no mandatory reload that could use it. */
5200 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5203 int regno = REGNO (avoid_return_reg);
5205 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5208 for (r = regno; r < regno + nregs; r++)
5209 if (spill_reg_order[r] >= 0)
5210 for (j = 0; j < n_reloads; j++)
5211 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5212 && (reload_in[j] != 0 || reload_out[j] != 0
5213 || reload_secondary_p[j])
5215 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5218 avoid_return_reg = 0;
5220 #endif /* SMALL_REGISTER_CLASSES */
5222 #if 0 /* Not needed, now that we can always retry without inheritance. */
5223 /* See if we have more mandatory reloads than spill regs.
5224 If so, then we cannot risk optimizations that could prevent
5225 reloads from sharing one spill register.
5227 Since we will try finding a better register than reload_reg_rtx
5228 unless it is equal to reload_in or reload_out, count such reloads. */
5232 #ifdef SMALL_REGISTER_CLASSES
5233 if (SMALL_REGISTER_CLASSES)
5234 tem = (avoid_return_reg != 0);
5236 for (j = 0; j < n_reloads; j++)
5237 if (! reload_optional[j]
5238 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5239 && (reload_reg_rtx[j] == 0
5240 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5241 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5248 #ifdef SMALL_REGISTER_CLASSES
5249 /* Don't use the subroutine call return reg for a reload
5250 if we are supposed to avoid it. */
5251 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5253 int regno = REGNO (avoid_return_reg);
5255 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5258 for (r = regno; r < regno + nregs; r++)
5259 if (spill_reg_order[r] >= 0)
5260 SET_HARD_REG_BIT (reload_reg_used, r);
5262 #endif /* SMALL_REGISTER_CLASSES */
5264 /* In order to be certain of getting the registers we need,
5265 we must sort the reloads into order of increasing register class.
5266 Then our grabbing of reload registers will parallel the process
5267 that provided the reload registers.
5269 Also note whether any of the reloads wants a consecutive group of regs.
5270 If so, record the maximum size of the group desired and what
5271 register class contains all the groups needed by this insn. */
5273 for (j = 0; j < n_reloads; j++)
5275 reload_order[j] = j;
5276 reload_spill_index[j] = -1;
5279 = (reload_inmode[j] == VOIDmode
5280 || (GET_MODE_SIZE (reload_outmode[j])
5281 > GET_MODE_SIZE (reload_inmode[j])))
5282 ? reload_outmode[j] : reload_inmode[j];
5284 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5286 if (reload_nregs[j] > 1)
5288 max_group_size = MAX (reload_nregs[j], max_group_size);
5289 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5292 /* If we have already decided to use a certain register,
5293 don't use it in another way. */
5294 if (reload_reg_rtx[j])
5295 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5296 reload_when_needed[j], reload_mode[j]);
5300 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5302 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5303 sizeof reload_reg_rtx);
5304 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5305 bcopy ((char *) reload_inheritance_insn,
5306 (char *) save_reload_inheritance_insn,
5307 sizeof reload_inheritance_insn);
5308 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5309 sizeof reload_override_in);
5310 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5311 sizeof reload_spill_index);
5312 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5313 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5314 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5315 reload_reg_used_in_op_addr);
5317 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5318 reload_reg_used_in_op_addr_reload);
5320 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5321 reload_reg_used_in_insn);
5322 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5323 reload_reg_used_in_other_addr);
5325 for (i = 0; i < reload_n_operands; i++)
5327 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5328 reload_reg_used_in_output[i]);
5329 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5330 reload_reg_used_in_input[i]);
5331 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5332 reload_reg_used_in_input_addr[i]);
5333 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5334 reload_reg_used_in_inpaddr_addr[i]);
5335 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5336 reload_reg_used_in_output_addr[i]);
5337 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5338 reload_reg_used_in_outaddr_addr[i]);
5341 /* If -O, try first with inheritance, then turning it off.
5342 If not -O, don't do inheritance.
5343 Using inheritance when not optimizing leads to paradoxes
5344 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5345 because one side of the comparison might be inherited. */
5347 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5349 /* Process the reloads in order of preference just found.
5350 Beyond this point, subregs can be found in reload_reg_rtx.
5352 This used to look for an existing reloaded home for all
5353 of the reloads, and only then perform any new reloads.
5354 But that could lose if the reloads were done out of reg-class order
5355 because a later reload with a looser constraint might have an old
5356 home in a register needed by an earlier reload with a tighter constraint.
5358 To solve this, we make two passes over the reloads, in the order
5359 described above. In the first pass we try to inherit a reload
5360 from a previous insn. If there is a later reload that needs a
5361 class that is a proper subset of the class being processed, we must
5362 also allocate a spill register during the first pass.
5364 Then make a second pass over the reloads to allocate any reloads
5365 that haven't been given registers yet. */
5367 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5369 for (j = 0; j < n_reloads; j++)
5371 register int r = reload_order[j];
5373 /* Ignore reloads that got marked inoperative. */
5374 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5377 /* If find_reloads chose a to use reload_in or reload_out as a reload
5378 register, we don't need to chose one. Otherwise, try even if it found
5379 one since we might save an insn if we find the value lying around. */
5380 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5381 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5382 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5385 #if 0 /* No longer needed for correct operation.
5386 It might give better code, or might not; worth an experiment? */
5387 /* If this is an optional reload, we can't inherit from earlier insns
5388 until we are sure that any non-optional reloads have been allocated.
5389 The following code takes advantage of the fact that optional reloads
5390 are at the end of reload_order. */
5391 if (reload_optional[r] != 0)
5392 for (i = 0; i < j; i++)
5393 if ((reload_out[reload_order[i]] != 0
5394 || reload_in[reload_order[i]] != 0
5395 || reload_secondary_p[reload_order[i]])
5396 && ! reload_optional[reload_order[i]]
5397 && reload_reg_rtx[reload_order[i]] == 0)
5398 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5401 /* First see if this pseudo is already available as reloaded
5402 for a previous insn. We cannot try to inherit for reloads
5403 that are smaller than the maximum number of registers needed
5404 for groups unless the register we would allocate cannot be used
5407 We could check here to see if this is a secondary reload for
5408 an object that is already in a register of the desired class.
5409 This would avoid the need for the secondary reload register.
5410 But this is complex because we can't easily determine what
5411 objects might want to be loaded via this reload. So let a register
5412 be allocated here. In `emit_reload_insns' we suppress one of the
5413 loads in the case described above. */
5417 register int regno = -1;
5418 enum machine_mode mode;
5420 if (reload_in[r] == 0)
5422 else if (GET_CODE (reload_in[r]) == REG)
5424 regno = REGNO (reload_in[r]);
5425 mode = GET_MODE (reload_in[r]);
5427 else if (GET_CODE (reload_in_reg[r]) == REG)
5429 regno = REGNO (reload_in_reg[r]);
5430 mode = GET_MODE (reload_in_reg[r]);
5433 /* This won't work, since REGNO can be a pseudo reg number.
5434 Also, it takes much more hair to keep track of all the things
5435 that can invalidate an inherited reload of part of a pseudoreg. */
5436 else if (GET_CODE (reload_in[r]) == SUBREG
5437 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5438 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5441 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5443 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5445 if (reg_reloaded_contents[i] == regno
5446 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5447 >= GET_MODE_SIZE (mode))
5448 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5449 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5451 && (reload_nregs[r] == max_group_size
5452 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5454 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5455 reload_when_needed[r])
5456 && reload_reg_free_before_p (spill_regs[i],
5458 reload_when_needed[r]))
5460 /* If a group is needed, verify that all the subsequent
5461 registers still have their values intact. */
5463 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5466 for (k = 1; k < nr; k++)
5467 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5475 /* We found a register that contains the
5476 value we need. If this register is the
5477 same as an `earlyclobber' operand of the
5478 current insn, just mark it as a place to
5479 reload from since we can't use it as the
5480 reload register itself. */
5482 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5483 if (reg_overlap_mentioned_for_reload_p
5484 (reg_last_reload_reg[regno],
5485 reload_earlyclobbers[i1]))
5488 if (i1 != n_earlyclobbers
5489 /* Don't really use the inherited spill reg
5490 if we need it wider than we've got it. */
5491 || (GET_MODE_SIZE (reload_mode[r])
5492 > GET_MODE_SIZE (mode)))
5493 reload_override_in[r] = reg_last_reload_reg[regno];
5497 /* We can use this as a reload reg. */
5498 /* Mark the register as in use for this part of
5500 mark_reload_reg_in_use (spill_regs[i],
5502 reload_when_needed[r],
5504 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5505 reload_inherited[r] = 1;
5506 reload_inheritance_insn[r]
5507 = reg_reloaded_insn[i];
5508 reload_spill_index[r] = i;
5509 for (k = 0; k < nr; k++)
5510 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5518 /* Here's another way to see if the value is already lying around. */
5520 && reload_in[r] != 0
5521 && ! reload_inherited[r]
5522 && reload_out[r] == 0
5523 && (CONSTANT_P (reload_in[r])
5524 || GET_CODE (reload_in[r]) == PLUS
5525 || GET_CODE (reload_in[r]) == REG
5526 || GET_CODE (reload_in[r]) == MEM)
5527 && (reload_nregs[r] == max_group_size
5528 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5531 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5532 -1, NULL_PTR, 0, reload_mode[r]);
5537 if (GET_CODE (equiv) == REG)
5538 regno = REGNO (equiv);
5539 else if (GET_CODE (equiv) == SUBREG)
5541 /* This must be a SUBREG of a hard register.
5542 Make a new REG since this might be used in an
5543 address and not all machines support SUBREGs
5545 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5546 equiv = gen_rtx (REG, reload_mode[r], regno);
5552 /* If we found a spill reg, reject it unless it is free
5553 and of the desired class. */
5555 && ((spill_reg_order[regno] >= 0
5556 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5557 reload_when_needed[r]))
5558 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5562 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5565 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5568 /* We found a register that contains the value we need.
5569 If this register is the same as an `earlyclobber' operand
5570 of the current insn, just mark it as a place to reload from
5571 since we can't use it as the reload register itself. */
5574 for (i = 0; i < n_earlyclobbers; i++)
5575 if (reg_overlap_mentioned_for_reload_p (equiv,
5576 reload_earlyclobbers[i]))
5578 reload_override_in[r] = equiv;
5583 /* JRV: If the equiv register we have found is
5584 explicitly clobbered in the current insn, mark but
5585 don't use, as above. */
5587 if (equiv != 0 && regno_clobbered_p (regno, insn))
5589 reload_override_in[r] = equiv;
5593 /* If we found an equivalent reg, say no code need be generated
5594 to load it, and use it as our reload reg. */
5595 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5597 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5599 reload_reg_rtx[r] = equiv;
5600 reload_inherited[r] = 1;
5602 /* If any of the hard registers in EQUIV are spill
5603 registers, mark them as in use for this insn. */
5604 for (k = 0; k < nr; k++)
5606 i = spill_reg_order[regno + k];
5609 mark_reload_reg_in_use (regno, reload_opnum[r],
5610 reload_when_needed[r],
5612 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5619 /* If we found a register to use already, or if this is an optional
5620 reload, we are done. */
5621 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5624 #if 0 /* No longer needed for correct operation. Might or might not
5625 give better code on the average. Want to experiment? */
5627 /* See if there is a later reload that has a class different from our
5628 class that intersects our class or that requires less register
5629 than our reload. If so, we must allocate a register to this
5630 reload now, since that reload might inherit a previous reload
5631 and take the only available register in our class. Don't do this
5632 for optional reloads since they will force all previous reloads
5633 to be allocated. Also don't do this for reloads that have been
5636 for (i = j + 1; i < n_reloads; i++)
5638 int s = reload_order[i];
5640 if ((reload_in[s] == 0 && reload_out[s] == 0
5641 && ! reload_secondary_p[s])
5642 || reload_optional[s])
5645 if ((reload_reg_class[s] != reload_reg_class[r]
5646 && reg_classes_intersect_p (reload_reg_class[r],
5647 reload_reg_class[s]))
5648 || reload_nregs[s] < reload_nregs[r])
5655 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5659 /* Now allocate reload registers for anything non-optional that
5660 didn't get one yet. */
5661 for (j = 0; j < n_reloads; j++)
5663 register int r = reload_order[j];
5665 /* Ignore reloads that got marked inoperative. */
5666 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5669 /* Skip reloads that already have a register allocated or are
5671 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5674 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5678 /* If that loop got all the way, we have won. */
5683 /* Loop around and try without any inheritance. */
5684 /* First undo everything done by the failed attempt
5685 to allocate with inheritance. */
5686 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5687 sizeof reload_reg_rtx);
5688 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5689 sizeof reload_inherited);
5690 bcopy ((char *) save_reload_inheritance_insn,
5691 (char *) reload_inheritance_insn,
5692 sizeof reload_inheritance_insn);
5693 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5694 sizeof reload_override_in);
5695 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5696 sizeof reload_spill_index);
5697 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5698 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5699 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5700 save_reload_reg_used_in_op_addr);
5701 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5702 save_reload_reg_used_in_op_addr_reload);
5703 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5704 save_reload_reg_used_in_insn);
5705 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5706 save_reload_reg_used_in_other_addr);
5708 for (i = 0; i < reload_n_operands; i++)
5710 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5711 save_reload_reg_used_in_input[i]);
5712 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5713 save_reload_reg_used_in_output[i]);
5714 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5715 save_reload_reg_used_in_input_addr[i]);
5716 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5717 save_reload_reg_used_in_inpaddr_addr[i]);
5718 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5719 save_reload_reg_used_in_output_addr[i]);
5720 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5721 save_reload_reg_used_in_outaddr_addr[i]);
5725 /* If we thought we could inherit a reload, because it seemed that
5726 nothing else wanted the same reload register earlier in the insn,
5727 verify that assumption, now that all reloads have been assigned. */
5729 for (j = 0; j < n_reloads; j++)
5731 register int r = reload_order[j];
5733 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5734 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5736 reload_when_needed[r]))
5737 reload_inherited[r] = 0;
5739 /* If we found a better place to reload from,
5740 validate it in the same fashion, if it is a reload reg. */
5741 if (reload_override_in[r]
5742 && (GET_CODE (reload_override_in[r]) == REG
5743 || GET_CODE (reload_override_in[r]) == SUBREG))
5745 int regno = true_regnum (reload_override_in[r]);
5746 if (spill_reg_order[regno] >= 0
5747 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5748 reload_when_needed[r]))
5749 reload_override_in[r] = 0;
5753 /* Now that reload_override_in is known valid,
5754 actually override reload_in. */
5755 for (j = 0; j < n_reloads; j++)
5756 if (reload_override_in[j])
5757 reload_in[j] = reload_override_in[j];
5759 /* If this reload won't be done because it has been cancelled or is
5760 optional and not inherited, clear reload_reg_rtx so other
5761 routines (such as subst_reloads) don't get confused. */
5762 for (j = 0; j < n_reloads; j++)
5763 if (reload_reg_rtx[j] != 0
5764 && ((reload_optional[j] && ! reload_inherited[j])
5765 || (reload_in[j] == 0 && reload_out[j] == 0
5766 && ! reload_secondary_p[j])))
5768 int regno = true_regnum (reload_reg_rtx[j]);
5770 if (spill_reg_order[regno] >= 0)
5771 clear_reload_reg_in_use (regno, reload_opnum[j],
5772 reload_when_needed[j], reload_mode[j]);
5773 reload_reg_rtx[j] = 0;
5776 /* Record which pseudos and which spill regs have output reloads. */
5777 for (j = 0; j < n_reloads; j++)
5779 register int r = reload_order[j];
5781 i = reload_spill_index[r];
5783 /* I is nonneg if this reload used one of the spill regs.
5784 If reload_reg_rtx[r] is 0, this is an optional reload
5785 that we opted to ignore. */
5786 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5787 && reload_reg_rtx[r] != 0)
5789 register int nregno = REGNO (reload_out[r]);
5792 if (nregno < FIRST_PSEUDO_REGISTER)
5793 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5796 reg_has_output_reload[nregno + nr] = 1;
5800 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5802 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5805 if (reload_when_needed[r] != RELOAD_OTHER
5806 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5807 && reload_when_needed[r] != RELOAD_FOR_INSN)
5813 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5814 reloads of the same item for fear that we might not have enough reload
5815 registers. However, normally they will get the same reload register
5816 and hence actually need not be loaded twice.
5818 Here we check for the most common case of this phenomenon: when we have
5819 a number of reloads for the same object, each of which were allocated
5820 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5821 reload, and is not modified in the insn itself. If we find such,
5822 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5823 This will not increase the number of spill registers needed and will
5824 prevent redundant code. */
5826 #ifdef SMALL_REGISTER_CLASSES
5829 merge_assigned_reloads (insn)
5834 /* Scan all the reloads looking for ones that only load values and
5835 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5836 assigned and not modified by INSN. */
5838 for (i = 0; i < n_reloads; i++)
5840 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5841 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5842 || reg_set_p (reload_reg_rtx[i], insn))
5845 /* Look at all other reloads. Ensure that the only use of this
5846 reload_reg_rtx is in a reload that just loads the same value
5847 as we do. Note that any secondary reloads must be of the identical
5848 class since the values, modes, and result registers are the
5849 same, so we need not do anything with any secondary reloads. */
5851 for (j = 0; j < n_reloads; j++)
5853 if (i == j || reload_reg_rtx[j] == 0
5854 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5858 /* If the reload regs aren't exactly the same (e.g, different modes)
5859 or if the values are different, we can't merge anything with this
5862 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5863 || reload_out[j] != 0 || reload_in[j] == 0
5864 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5868 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5869 we, in fact, found any matching reloads. */
5873 for (j = 0; j < n_reloads; j++)
5874 if (i != j && reload_reg_rtx[j] != 0
5875 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5877 reload_when_needed[i] = RELOAD_OTHER;
5879 transfer_replacements (i, j);
5882 /* If this is now RELOAD_OTHER, look for any reloads that load
5883 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5884 if they were for inputs, RELOAD_OTHER for outputs. Note that
5885 this test is equivalent to looking for reloads for this operand
5888 if (reload_when_needed[i] == RELOAD_OTHER)
5889 for (j = 0; j < n_reloads; j++)
5890 if (reload_in[j] != 0
5891 && reload_when_needed[i] != RELOAD_OTHER
5892 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5894 reload_when_needed[j]
5895 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5896 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
5897 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5901 #endif /* SMALL_RELOAD_CLASSES */
5903 /* Output insns to reload values in and out of the chosen reload regs. */
5906 emit_reload_insns (insn)
5910 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5911 rtx other_input_address_reload_insns = 0;
5912 rtx other_input_reload_insns = 0;
5913 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5914 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5915 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5916 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5917 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5918 rtx operand_reload_insns = 0;
5919 rtx other_operand_reload_insns = 0;
5920 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5921 rtx following_insn = NEXT_INSN (insn);
5922 rtx before_insn = insn;
5924 /* Values to be put in spill_reg_store are put here first. */
5925 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5927 for (j = 0; j < reload_n_operands; j++)
5928 input_reload_insns[j] = input_address_reload_insns[j]
5929 = inpaddr_address_reload_insns[j]
5930 = output_reload_insns[j] = output_address_reload_insns[j]
5931 = outaddr_address_reload_insns[j]
5932 = other_output_reload_insns[j] = 0;
5934 /* Now output the instructions to copy the data into and out of the
5935 reload registers. Do these in the order that the reloads were reported,
5936 since reloads of base and index registers precede reloads of operands
5937 and the operands may need the base and index registers reloaded. */
5939 for (j = 0; j < n_reloads; j++)
5942 rtx oldequiv_reg = 0;
5943 rtx this_reload_insn = 0;
5945 if (reload_spill_index[j] >= 0)
5946 new_spill_reg_store[reload_spill_index[j]] = 0;
5949 if (old != 0 && ! reload_inherited[j]
5950 && ! rtx_equal_p (reload_reg_rtx[j], old)
5951 && reload_reg_rtx[j] != 0)
5953 register rtx reloadreg = reload_reg_rtx[j];
5955 enum machine_mode mode;
5958 /* Determine the mode to reload in.
5959 This is very tricky because we have three to choose from.
5960 There is the mode the insn operand wants (reload_inmode[J]).
5961 There is the mode of the reload register RELOADREG.
5962 There is the intrinsic mode of the operand, which we could find
5963 by stripping some SUBREGs.
5964 It turns out that RELOADREG's mode is irrelevant:
5965 we can change that arbitrarily.
5967 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5968 then the reload reg may not support QImode moves, so use SImode.
5969 If foo is in memory due to spilling a pseudo reg, this is safe,
5970 because the QImode value is in the least significant part of a
5971 slot big enough for a SImode. If foo is some other sort of
5972 memory reference, then it is impossible to reload this case,
5973 so previous passes had better make sure this never happens.
5975 Then consider a one-word union which has SImode and one of its
5976 members is a float, being fetched as (SUBREG:SF union:SI).
5977 We must fetch that as SFmode because we could be loading into
5978 a float-only register. In this case OLD's mode is correct.
5980 Consider an immediate integer: it has VOIDmode. Here we need
5981 to get a mode from something else.
5983 In some cases, there is a fourth mode, the operand's
5984 containing mode. If the insn specifies a containing mode for
5985 this operand, it overrides all others.
5987 I am not sure whether the algorithm here is always right,
5988 but it does the right things in those cases. */
5990 mode = GET_MODE (old);
5991 if (mode == VOIDmode)
5992 mode = reload_inmode[j];
5994 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5995 /* If we need a secondary register for this operation, see if
5996 the value is already in a register in that class. Don't
5997 do this if the secondary register will be used as a scratch
6000 if (reload_secondary_in_reload[j] >= 0
6001 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6004 = find_equiv_reg (old, insn,
6005 reload_reg_class[reload_secondary_in_reload[j]],
6006 -1, NULL_PTR, 0, mode);
6009 /* If reloading from memory, see if there is a register
6010 that already holds the same value. If so, reload from there.
6011 We can pass 0 as the reload_reg_p argument because
6012 any other reload has either already been emitted,
6013 in which case find_equiv_reg will see the reload-insn,
6014 or has yet to be emitted, in which case it doesn't matter
6015 because we will use this equiv reg right away. */
6017 if (oldequiv == 0 && optimize
6018 && (GET_CODE (old) == MEM
6019 || (GET_CODE (old) == REG
6020 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6021 && reg_renumber[REGNO (old)] < 0)))
6022 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6023 -1, NULL_PTR, 0, mode);
6027 int regno = true_regnum (oldequiv);
6029 /* If OLDEQUIV is a spill register, don't use it for this
6030 if any other reload needs it at an earlier stage of this insn
6031 or at this stage. */
6032 if (spill_reg_order[regno] >= 0
6033 && (! reload_reg_free_p (regno, reload_opnum[j],
6034 reload_when_needed[j])
6035 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6036 reload_when_needed[j])))
6039 /* If OLDEQUIV is not a spill register,
6040 don't use it if any other reload wants it. */
6041 if (spill_reg_order[regno] < 0)
6044 for (k = 0; k < n_reloads; k++)
6045 if (reload_reg_rtx[k] != 0 && k != j
6046 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6054 /* If it is no cheaper to copy from OLDEQUIV into the
6055 reload register than it would be to move from memory,
6056 don't use it. Likewise, if we need a secondary register
6060 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6061 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6062 reload_reg_class[j])
6063 >= MEMORY_MOVE_COST (mode)))
6064 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6065 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6069 #ifdef SECONDARY_MEMORY_NEEDED
6070 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
6071 REGNO_REG_CLASS (regno),
6080 else if (GET_CODE (oldequiv) == REG)
6081 oldequiv_reg = oldequiv;
6082 else if (GET_CODE (oldequiv) == SUBREG)
6083 oldequiv_reg = SUBREG_REG (oldequiv);
6085 /* If we are reloading from a register that was recently stored in
6086 with an output-reload, see if we can prove there was
6087 actually no need to store the old value in it. */
6089 if (optimize && GET_CODE (oldequiv) == REG
6090 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6091 && spill_reg_order[REGNO (oldequiv)] >= 0
6092 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
6093 && find_reg_note (insn, REG_DEAD, reload_in[j])
6094 /* This is unsafe if operand occurs more than once in current
6095 insn. Perhaps some occurrences weren't reloaded. */
6096 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6097 delete_output_reload
6098 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
6100 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6101 then load RELOADREG from OLDEQUIV. Note that we cannot use
6102 gen_lowpart_common since it can do the wrong thing when
6103 RELOADREG has a multi-word mode. Note that RELOADREG
6104 must always be a REG here. */
6106 if (GET_MODE (reloadreg) != mode)
6107 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6108 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6109 oldequiv = SUBREG_REG (oldequiv);
6110 if (GET_MODE (oldequiv) != VOIDmode
6111 && mode != GET_MODE (oldequiv))
6112 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
6114 /* Switch to the right place to emit the reload insns. */
6115 switch (reload_when_needed[j])
6118 where = &other_input_reload_insns;
6120 case RELOAD_FOR_INPUT:
6121 where = &input_reload_insns[reload_opnum[j]];
6123 case RELOAD_FOR_INPUT_ADDRESS:
6124 where = &input_address_reload_insns[reload_opnum[j]];
6126 case RELOAD_FOR_INPADDR_ADDRESS:
6127 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6129 case RELOAD_FOR_OUTPUT_ADDRESS:
6130 where = &output_address_reload_insns[reload_opnum[j]];
6132 case RELOAD_FOR_OUTADDR_ADDRESS:
6133 where = &outaddr_address_reload_insns[reload_opnum[j]];
6135 case RELOAD_FOR_OPERAND_ADDRESS:
6136 where = &operand_reload_insns;
6138 case RELOAD_FOR_OPADDR_ADDR:
6139 where = &other_operand_reload_insns;
6141 case RELOAD_FOR_OTHER_ADDRESS:
6142 where = &other_input_address_reload_insns;
6148 push_to_sequence (*where);
6151 /* Auto-increment addresses must be reloaded in a special way. */
6152 if (GET_CODE (oldequiv) == POST_INC
6153 || GET_CODE (oldequiv) == POST_DEC
6154 || GET_CODE (oldequiv) == PRE_INC
6155 || GET_CODE (oldequiv) == PRE_DEC)
6157 /* We are not going to bother supporting the case where a
6158 incremented register can't be copied directly from
6159 OLDEQUIV since this seems highly unlikely. */
6160 if (reload_secondary_in_reload[j] >= 0)
6162 /* Prevent normal processing of this reload. */
6164 /* Output a special code sequence for this case. */
6165 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6168 /* If we are reloading a pseudo-register that was set by the previous
6169 insn, see if we can get rid of that pseudo-register entirely
6170 by redirecting the previous insn into our reload register. */
6172 else if (optimize && GET_CODE (old) == REG
6173 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6174 && dead_or_set_p (insn, old)
6175 /* This is unsafe if some other reload
6176 uses the same reg first. */
6177 && reload_reg_free_before_p (REGNO (reloadreg),
6179 reload_when_needed[j]))
6181 rtx temp = PREV_INSN (insn);
6182 while (temp && GET_CODE (temp) == NOTE)
6183 temp = PREV_INSN (temp);
6185 && GET_CODE (temp) == INSN
6186 && GET_CODE (PATTERN (temp)) == SET
6187 && SET_DEST (PATTERN (temp)) == old
6188 /* Make sure we can access insn_operand_constraint. */
6189 && asm_noperands (PATTERN (temp)) < 0
6190 /* This is unsafe if prev insn rejects our reload reg. */
6191 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6193 /* This is unsafe if operand occurs more than once in current
6194 insn. Perhaps some occurrences aren't reloaded. */
6195 && count_occurrences (PATTERN (insn), old) == 1
6196 /* Don't risk splitting a matching pair of operands. */
6197 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6199 /* Store into the reload register instead of the pseudo. */
6200 SET_DEST (PATTERN (temp)) = reloadreg;
6201 /* If these are the only uses of the pseudo reg,
6202 pretend for GDB it lives in the reload reg we used. */
6203 if (reg_n_deaths[REGNO (old)] == 1
6204 && reg_n_sets[REGNO (old)] == 1)
6206 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6207 alter_reg (REGNO (old), -1);
6213 /* We can't do that, so output an insn to load RELOADREG. */
6217 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6218 rtx second_reload_reg = 0;
6219 enum insn_code icode;
6221 /* If we have a secondary reload, pick up the secondary register
6222 and icode, if any. If OLDEQUIV and OLD are different or
6223 if this is an in-out reload, recompute whether or not we
6224 still need a secondary register and what the icode should
6225 be. If we still need a secondary register and the class or
6226 icode is different, go back to reloading from OLD if using
6227 OLDEQUIV means that we got the wrong type of register. We
6228 cannot have different class or icode due to an in-out reload
6229 because we don't make such reloads when both the input and
6230 output need secondary reload registers. */
6232 if (reload_secondary_in_reload[j] >= 0)
6234 int secondary_reload = reload_secondary_in_reload[j];
6235 rtx real_oldequiv = oldequiv;
6238 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6239 and similarly for OLD.
6240 See comments in get_secondary_reload in reload.c. */
6241 if (GET_CODE (oldequiv) == REG
6242 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6243 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6244 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6246 if (GET_CODE (old) == REG
6247 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6248 && reg_equiv_mem[REGNO (old)] != 0)
6249 real_old = reg_equiv_mem[REGNO (old)];
6251 second_reload_reg = reload_reg_rtx[secondary_reload];
6252 icode = reload_secondary_in_icode[j];
6254 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6255 || (reload_in[j] != 0 && reload_out[j] != 0))
6257 enum reg_class new_class
6258 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6259 mode, real_oldequiv);
6261 if (new_class == NO_REGS)
6262 second_reload_reg = 0;
6265 enum insn_code new_icode;
6266 enum machine_mode new_mode;
6268 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6269 REGNO (second_reload_reg)))
6270 oldequiv = old, real_oldequiv = real_old;
6273 new_icode = reload_in_optab[(int) mode];
6274 if (new_icode != CODE_FOR_nothing
6275 && ((insn_operand_predicate[(int) new_icode][0]
6276 && ! ((*insn_operand_predicate[(int) new_icode][0])
6278 || (insn_operand_predicate[(int) new_icode][1]
6279 && ! ((*insn_operand_predicate[(int) new_icode][1])
6280 (real_oldequiv, mode)))))
6281 new_icode = CODE_FOR_nothing;
6283 if (new_icode == CODE_FOR_nothing)
6286 new_mode = insn_operand_mode[(int) new_icode][2];
6288 if (GET_MODE (second_reload_reg) != new_mode)
6290 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6292 oldequiv = old, real_oldequiv = real_old;
6295 = gen_rtx (REG, new_mode,
6296 REGNO (second_reload_reg));
6302 /* If we still need a secondary reload register, check
6303 to see if it is being used as a scratch or intermediate
6304 register and generate code appropriately. If we need
6305 a scratch register, use REAL_OLDEQUIV since the form of
6306 the insn may depend on the actual address if it is
6309 if (second_reload_reg)
6311 if (icode != CODE_FOR_nothing)
6313 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6314 second_reload_reg));
6319 /* See if we need a scratch register to load the
6320 intermediate register (a tertiary reload). */
6321 enum insn_code tertiary_icode
6322 = reload_secondary_in_icode[secondary_reload];
6324 if (tertiary_icode != CODE_FOR_nothing)
6326 rtx third_reload_reg
6327 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6329 emit_insn ((GEN_FCN (tertiary_icode)
6330 (second_reload_reg, real_oldequiv,
6331 third_reload_reg)));
6334 gen_reload (second_reload_reg, oldequiv,
6336 reload_when_needed[j]);
6338 oldequiv = second_reload_reg;
6344 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6345 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6346 reload_when_needed[j]);
6348 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6349 /* We may have to make a REG_DEAD note for the secondary reload
6350 register in the insns we just made. Find the last insn that
6351 mentioned the register. */
6352 if (! special && second_reload_reg
6353 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6357 for (prev = get_last_insn (); prev;
6358 prev = PREV_INSN (prev))
6359 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6360 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6363 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6372 this_reload_insn = get_last_insn ();
6373 /* End this sequence. */
6374 *where = get_insns ();
6378 /* Add a note saying the input reload reg
6379 dies in this insn, if anyone cares. */
6380 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6382 && reload_reg_rtx[j] != old
6383 && reload_reg_rtx[j] != 0
6384 && reload_out[j] == 0
6385 && ! reload_inherited[j]
6386 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6388 register rtx reloadreg = reload_reg_rtx[j];
6391 /* We can't abort here because we need to support this for sched.c.
6392 It's not terrible to miss a REG_DEAD note, but we should try
6393 to figure out how to do this correctly. */
6394 /* The code below is incorrect for address-only reloads. */
6395 if (reload_when_needed[j] != RELOAD_OTHER
6396 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6400 /* Add a death note to this insn, for an input reload. */
6402 if ((reload_when_needed[j] == RELOAD_OTHER
6403 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6404 && ! dead_or_set_p (insn, reloadreg))
6406 = gen_rtx (EXPR_LIST, REG_DEAD,
6407 reloadreg, REG_NOTES (insn));
6410 /* When we inherit a reload, the last marked death of the reload reg
6411 may no longer really be a death. */
6412 if (reload_reg_rtx[j] != 0
6413 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6414 && reload_inherited[j])
6416 /* Handle inheriting an output reload.
6417 Remove the death note from the output reload insn. */
6418 if (reload_spill_index[j] >= 0
6419 && GET_CODE (reload_in[j]) == REG
6420 && spill_reg_store[reload_spill_index[j]] != 0
6421 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6422 REG_DEAD, REGNO (reload_reg_rtx[j])))
6423 remove_death (REGNO (reload_reg_rtx[j]),
6424 spill_reg_store[reload_spill_index[j]]);
6425 /* Likewise for input reloads that were inherited. */
6426 else if (reload_spill_index[j] >= 0
6427 && GET_CODE (reload_in[j]) == REG
6428 && spill_reg_store[reload_spill_index[j]] == 0
6429 && reload_inheritance_insn[j] != 0
6430 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6431 REGNO (reload_reg_rtx[j])))
6432 remove_death (REGNO (reload_reg_rtx[j]),
6433 reload_inheritance_insn[j]);
6438 /* We got this register from find_equiv_reg.
6439 Search back for its last death note and get rid of it.
6440 But don't search back too far.
6441 Don't go past a place where this reg is set,
6442 since a death note before that remains valid. */
6443 for (prev = PREV_INSN (insn);
6444 prev && GET_CODE (prev) != CODE_LABEL;
6445 prev = PREV_INSN (prev))
6446 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6447 && dead_or_set_p (prev, reload_reg_rtx[j]))
6449 if (find_regno_note (prev, REG_DEAD,
6450 REGNO (reload_reg_rtx[j])))
6451 remove_death (REGNO (reload_reg_rtx[j]), prev);
6457 /* We might have used find_equiv_reg above to choose an alternate
6458 place from which to reload. If so, and it died, we need to remove
6459 that death and move it to one of the insns we just made. */
6461 if (oldequiv_reg != 0
6462 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6466 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6467 prev = PREV_INSN (prev))
6468 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6469 && dead_or_set_p (prev, oldequiv_reg))
6471 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6473 for (prev1 = this_reload_insn;
6474 prev1; prev1 = PREV_INSN (prev1))
6475 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6476 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6479 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6484 remove_death (REGNO (oldequiv_reg), prev);
6491 /* If we are reloading a register that was recently stored in with an
6492 output-reload, see if we can prove there was
6493 actually no need to store the old value in it. */
6495 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6496 && reload_in[j] != 0
6497 && GET_CODE (reload_in[j]) == REG
6499 /* There doesn't seem to be any reason to restrict this to pseudos
6500 and doing so loses in the case where we are copying from a
6501 register of the wrong class. */
6502 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6504 && spill_reg_store[reload_spill_index[j]] != 0
6505 /* This is unsafe if some other reload uses the same reg first. */
6506 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6507 reload_opnum[j], reload_when_needed[j])
6508 && dead_or_set_p (insn, reload_in[j])
6509 /* This is unsafe if operand occurs more than once in current
6510 insn. Perhaps some occurrences weren't reloaded. */
6511 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6512 delete_output_reload (insn, j,
6513 spill_reg_store[reload_spill_index[j]]);
6515 /* Input-reloading is done. Now do output-reloading,
6516 storing the value from the reload-register after the main insn
6517 if reload_out[j] is nonzero.
6519 ??? At some point we need to support handling output reloads of
6520 JUMP_INSNs or insns that set cc0. */
6521 old = reload_out[j];
6523 && reload_reg_rtx[j] != old
6524 && reload_reg_rtx[j] != 0)
6526 register rtx reloadreg = reload_reg_rtx[j];
6527 register rtx second_reloadreg = 0;
6529 enum machine_mode mode;
6532 /* An output operand that dies right away does need a reload,
6533 but need not be copied from it. Show the new location in the
6535 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6536 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6538 XEXP (note, 0) = reload_reg_rtx[j];
6541 /* Likewise for a SUBREG of an operand that dies. */
6542 else if (GET_CODE (old) == SUBREG
6543 && GET_CODE (SUBREG_REG (old)) == REG
6544 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6547 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6551 else if (GET_CODE (old) == SCRATCH)
6552 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6553 but we don't want to make an output reload. */
6557 /* Strip off of OLD any size-increasing SUBREGs such as
6558 (SUBREG:SI foo:QI 0). */
6560 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6561 && (GET_MODE_SIZE (GET_MODE (old))
6562 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6563 old = SUBREG_REG (old);
6566 /* If is a JUMP_INSN, we can't support output reloads yet. */
6567 if (GET_CODE (insn) == JUMP_INSN)
6570 if (reload_when_needed[j] == RELOAD_OTHER)
6573 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6575 /* Determine the mode to reload in.
6576 See comments above (for input reloading). */
6578 mode = GET_MODE (old);
6579 if (mode == VOIDmode)
6581 /* VOIDmode should never happen for an output. */
6582 if (asm_noperands (PATTERN (insn)) < 0)
6583 /* It's the compiler's fault. */
6584 fatal_insn ("VOIDmode on an output", insn);
6585 error_for_asm (insn, "output operand is constant in `asm'");
6586 /* Prevent crash--use something we know is valid. */
6588 old = gen_rtx (REG, mode, REGNO (reloadreg));
6591 if (GET_MODE (reloadreg) != mode)
6592 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6594 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6596 /* If we need two reload regs, set RELOADREG to the intermediate
6597 one, since it will be stored into OLD. We might need a secondary
6598 register only for an input reload, so check again here. */
6600 if (reload_secondary_out_reload[j] >= 0)
6604 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6605 && reg_equiv_mem[REGNO (old)] != 0)
6606 real_old = reg_equiv_mem[REGNO (old)];
6608 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6612 second_reloadreg = reloadreg;
6613 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6615 /* See if RELOADREG is to be used as a scratch register
6616 or as an intermediate register. */
6617 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6619 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6620 (real_old, second_reloadreg, reloadreg)));
6625 /* See if we need both a scratch and intermediate reload
6628 int secondary_reload = reload_secondary_out_reload[j];
6629 enum insn_code tertiary_icode
6630 = reload_secondary_out_icode[secondary_reload];
6632 if (GET_MODE (reloadreg) != mode)
6633 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6635 if (tertiary_icode != CODE_FOR_nothing)
6638 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6641 /* Copy primary reload reg to secondary reload reg.
6642 (Note that these have been swapped above, then
6643 secondary reload reg to OLD using our insn. */
6645 /* If REAL_OLD is a paradoxical SUBREG, remove it
6646 and try to put the opposite SUBREG on
6648 if (GET_CODE (real_old) == SUBREG
6649 && (GET_MODE_SIZE (GET_MODE (real_old))
6650 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6651 && 0 != (tem = gen_lowpart_common
6652 (GET_MODE (SUBREG_REG (real_old)),
6654 real_old = SUBREG_REG (real_old), reloadreg = tem;
6656 gen_reload (reloadreg, second_reloadreg,
6657 reload_opnum[j], reload_when_needed[j]);
6658 emit_insn ((GEN_FCN (tertiary_icode)
6659 (real_old, reloadreg, third_reloadreg)));
6664 /* Copy between the reload regs here and then to
6667 gen_reload (reloadreg, second_reloadreg,
6668 reload_opnum[j], reload_when_needed[j]);
6674 /* Output the last reload insn. */
6676 gen_reload (old, reloadreg, reload_opnum[j],
6677 reload_when_needed[j]);
6679 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6680 /* If final will look at death notes for this reg,
6681 put one on the last output-reload insn to use it. Similarly
6682 for any secondary register. */
6683 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6684 for (p = get_last_insn (); p; p = PREV_INSN (p))
6685 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6686 && reg_overlap_mentioned_for_reload_p (reloadreg,
6688 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6689 reloadreg, REG_NOTES (p));
6691 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6692 if (! special && second_reloadreg
6693 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6694 for (p = get_last_insn (); p; p = PREV_INSN (p))
6695 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6696 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6698 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6699 second_reloadreg, REG_NOTES (p));
6702 /* Look at all insns we emitted, just to be safe. */
6703 for (p = get_insns (); p; p = NEXT_INSN (p))
6704 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6706 /* If this output reload doesn't come from a spill reg,
6707 clear any memory of reloaded copies of the pseudo reg.
6708 If this output reload comes from a spill reg,
6709 reg_has_output_reload will make this do nothing. */
6710 note_stores (PATTERN (p), forget_old_reloads_1);
6712 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6713 && reload_spill_index[j] >= 0)
6714 new_spill_reg_store[reload_spill_index[j]] = p;
6717 if (reload_when_needed[j] == RELOAD_OTHER)
6719 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6720 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6723 output_reload_insns[reload_opnum[j]] = get_insns ();
6729 /* Now write all the insns we made for reloads in the order expected by
6730 the allocation functions. Prior to the insn being reloaded, we write
6731 the following reloads:
6733 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6735 RELOAD_OTHER reloads.
6737 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6738 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6739 RELOAD_FOR_INPUT reload for the operand.
6741 RELOAD_FOR_OPADDR_ADDRS reloads.
6743 RELOAD_FOR_OPERAND_ADDRESS reloads.
6745 After the insn being reloaded, we write the following:
6747 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6748 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6749 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6750 reloads for the operand. The RELOAD_OTHER output reloads are
6751 output in descending order by reload number. */
6753 emit_insns_before (other_input_address_reload_insns, before_insn);
6754 emit_insns_before (other_input_reload_insns, before_insn);
6756 for (j = 0; j < reload_n_operands; j++)
6758 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
6759 emit_insns_before (input_address_reload_insns[j], before_insn);
6760 emit_insns_before (input_reload_insns[j], before_insn);
6763 emit_insns_before (other_operand_reload_insns, before_insn);
6764 emit_insns_before (operand_reload_insns, before_insn);
6766 for (j = 0; j < reload_n_operands; j++)
6768 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6769 emit_insns_before (output_address_reload_insns[j], following_insn);
6770 emit_insns_before (output_reload_insns[j], following_insn);
6771 emit_insns_before (other_output_reload_insns[j], following_insn);
6774 /* Move death notes from INSN
6775 to output-operand-address and output reload insns. */
6776 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6779 /* Loop over those insns, last ones first. */
6780 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6781 insn1 = PREV_INSN (insn1))
6782 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6784 rtx source = SET_SRC (PATTERN (insn1));
6785 rtx dest = SET_DEST (PATTERN (insn1));
6787 /* The note we will examine next. */
6788 rtx reg_notes = REG_NOTES (insn);
6789 /* The place that pointed to this note. */
6790 rtx *prev_reg_note = ®_NOTES (insn);
6792 /* If the note is for something used in the source of this
6793 reload insn, or in the output address, move the note. */
6796 rtx next_reg_notes = XEXP (reg_notes, 1);
6797 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6798 && GET_CODE (XEXP (reg_notes, 0)) == REG
6799 && ((GET_CODE (dest) != REG
6800 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6802 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6805 *prev_reg_note = next_reg_notes;
6806 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6807 REG_NOTES (insn1) = reg_notes;
6810 prev_reg_note = &XEXP (reg_notes, 1);
6812 reg_notes = next_reg_notes;
6818 /* For all the spill regs newly reloaded in this instruction,
6819 record what they were reloaded from, so subsequent instructions
6820 can inherit the reloads.
6822 Update spill_reg_store for the reloads of this insn.
6823 Copy the elements that were updated in the loop above. */
6825 for (j = 0; j < n_reloads; j++)
6827 register int r = reload_order[j];
6828 register int i = reload_spill_index[r];
6830 /* I is nonneg if this reload used one of the spill regs.
6831 If reload_reg_rtx[r] is 0, this is an optional reload
6832 that we opted to ignore. */
6834 if (i >= 0 && reload_reg_rtx[r] != 0)
6837 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6839 int part_reaches_end = 0;
6840 int all_reaches_end = 1;
6842 /* For a multi register reload, we need to check if all or part
6843 of the value lives to the end. */
6844 for (k = 0; k < nr; k++)
6846 if (reload_reg_reaches_end_p (spill_regs[i] + k, reload_opnum[r],
6847 reload_when_needed[r]))
6848 part_reaches_end = 1;
6850 all_reaches_end = 0;
6853 /* Ignore reloads that don't reach the end of the insn in
6855 if (all_reaches_end)
6857 /* First, clear out memory of what used to be in this spill reg.
6858 If consecutive registers are used, clear them all. */
6860 for (k = 0; k < nr; k++)
6862 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6863 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6866 /* Maybe the spill reg contains a copy of reload_out. */
6867 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6869 register int nregno = REGNO (reload_out[r]);
6870 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6871 : HARD_REGNO_NREGS (nregno,
6872 GET_MODE (reload_reg_rtx[r])));
6874 spill_reg_store[i] = new_spill_reg_store[i];
6875 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6877 /* If NREGNO is a hard register, it may occupy more than
6878 one register. If it does, say what is in the
6879 rest of the registers assuming that both registers
6880 agree on how many words the object takes. If not,
6881 invalidate the subsequent registers. */
6883 if (nregno < FIRST_PSEUDO_REGISTER)
6884 for (k = 1; k < nnr; k++)
6885 reg_last_reload_reg[nregno + k]
6888 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6889 REGNO (reload_reg_rtx[r]) + k)
6892 /* Now do the inverse operation. */
6893 for (k = 0; k < nr; k++)
6895 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6896 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6899 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6903 /* Maybe the spill reg contains a copy of reload_in. Only do
6904 something if there will not be an output reload for
6905 the register being reloaded. */
6906 else if (reload_out[r] == 0
6907 && reload_in[r] != 0
6908 && ((GET_CODE (reload_in[r]) == REG
6909 && ! reg_has_output_reload[REGNO (reload_in[r])])
6910 || (GET_CODE (reload_in_reg[r]) == REG
6911 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
6913 register int nregno;
6916 if (GET_CODE (reload_in[r]) == REG)
6917 nregno = REGNO (reload_in[r]);
6919 nregno = REGNO (reload_in_reg[r]);
6921 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6922 : HARD_REGNO_NREGS (nregno,
6923 GET_MODE (reload_reg_rtx[r])));
6925 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6927 if (nregno < FIRST_PSEUDO_REGISTER)
6928 for (k = 1; k < nnr; k++)
6929 reg_last_reload_reg[nregno + k]
6932 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6933 REGNO (reload_reg_rtx[r]) + k)
6936 /* Unless we inherited this reload, show we haven't
6937 recently done a store. */
6938 if (! reload_inherited[r])
6939 spill_reg_store[i] = 0;
6941 for (k = 0; k < nr; k++)
6943 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6944 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6947 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6953 /* However, if part of the reload reaches the end, then we must
6954 invalidate the old info for the part that survives to the end. */
6955 else if (part_reaches_end)
6957 for (k = 0; k < nr; k++)
6958 if (reload_reg_reaches_end_p (spill_regs[i] + k,
6960 reload_when_needed[r]))
6962 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6963 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6968 /* The following if-statement was #if 0'd in 1.34 (or before...).
6969 It's reenabled in 1.35 because supposedly nothing else
6970 deals with this problem. */
6972 /* If a register gets output-reloaded from a non-spill register,
6973 that invalidates any previous reloaded copy of it.
6974 But forget_old_reloads_1 won't get to see it, because
6975 it thinks only about the original insn. So invalidate it here. */
6976 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6978 register int nregno = REGNO (reload_out[r]);
6979 if (nregno >= FIRST_PSEUDO_REGISTER)
6980 reg_last_reload_reg[nregno] = 0;
6983 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
6985 while (num_regs-- > 0)
6986 reg_last_reload_reg[nregno + num_regs] = 0;
6992 /* Emit code to perform a reload from IN (which may be a reload register) to
6993 OUT (which may also be a reload register). IN or OUT is from operand
6994 OPNUM with reload type TYPE.
6996 Returns first insn emitted. */
6999 gen_reload (out, in, opnum, type)
7003 enum reload_type type;
7005 rtx last = get_last_insn ();
7008 /* If IN is a paradoxical SUBREG, remove it and try to put the
7009 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7010 if (GET_CODE (in) == SUBREG
7011 && (GET_MODE_SIZE (GET_MODE (in))
7012 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7013 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7014 in = SUBREG_REG (in), out = tem;
7015 else if (GET_CODE (out) == SUBREG
7016 && (GET_MODE_SIZE (GET_MODE (out))
7017 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7018 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7019 out = SUBREG_REG (out), in = tem;
7021 /* How to do this reload can get quite tricky. Normally, we are being
7022 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7023 register that didn't get a hard register. In that case we can just
7024 call emit_move_insn.
7026 We can also be asked to reload a PLUS that adds a register or a MEM to
7027 another register, constant or MEM. This can occur during frame pointer
7028 elimination and while reloading addresses. This case is handled by
7029 trying to emit a single insn to perform the add. If it is not valid,
7030 we use a two insn sequence.
7032 Finally, we could be called to handle an 'o' constraint by putting
7033 an address into a register. In that case, we first try to do this
7034 with a named pattern of "reload_load_address". If no such pattern
7035 exists, we just emit a SET insn and hope for the best (it will normally
7036 be valid on machines that use 'o').
7038 This entire process is made complex because reload will never
7039 process the insns we generate here and so we must ensure that
7040 they will fit their constraints and also by the fact that parts of
7041 IN might be being reloaded separately and replaced with spill registers.
7042 Because of this, we are, in some sense, just guessing the right approach
7043 here. The one listed above seems to work.
7045 ??? At some point, this whole thing needs to be rethought. */
7047 if (GET_CODE (in) == PLUS
7048 && (GET_CODE (XEXP (in, 0)) == REG
7049 || GET_CODE (XEXP (in, 0)) == SUBREG
7050 || GET_CODE (XEXP (in, 0)) == MEM)
7051 && (GET_CODE (XEXP (in, 1)) == REG
7052 || GET_CODE (XEXP (in, 1)) == SUBREG
7053 || CONSTANT_P (XEXP (in, 1))
7054 || GET_CODE (XEXP (in, 1)) == MEM))
7056 /* We need to compute the sum of a register or a MEM and another
7057 register, constant, or MEM, and put it into the reload
7058 register. The best possible way of doing this is if the machine
7059 has a three-operand ADD insn that accepts the required operands.
7061 The simplest approach is to try to generate such an insn and see if it
7062 is recognized and matches its constraints. If so, it can be used.
7064 It might be better not to actually emit the insn unless it is valid,
7065 but we need to pass the insn as an operand to `recog' and
7066 `insn_extract' and it is simpler to emit and then delete the insn if
7067 not valid than to dummy things up. */
7069 rtx op0, op1, tem, insn;
7072 op0 = find_replacement (&XEXP (in, 0));
7073 op1 = find_replacement (&XEXP (in, 1));
7075 /* Since constraint checking is strict, commutativity won't be
7076 checked, so we need to do that here to avoid spurious failure
7077 if the add instruction is two-address and the second operand
7078 of the add is the same as the reload reg, which is frequently
7079 the case. If the insn would be A = B + A, rearrange it so
7080 it will be A = A + B as constrain_operands expects. */
7082 if (GET_CODE (XEXP (in, 1)) == REG
7083 && REGNO (out) == REGNO (XEXP (in, 1)))
7084 tem = op0, op0 = op1, op1 = tem;
7086 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7087 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
7089 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
7090 code = recog_memoized (insn);
7094 insn_extract (insn);
7095 /* We want constrain operands to treat this insn strictly in
7096 its validity determination, i.e., the way it would after reload
7098 if (constrain_operands (code, 1))
7102 delete_insns_since (last);
7104 /* If that failed, we must use a conservative two-insn sequence.
7105 use move to copy constant, MEM, or pseudo register to the reload
7106 register since "move" will be able to handle an arbitrary operand,
7107 unlike add which can't, in general. Then add the registers.
7109 If there is another way to do this for a specific machine, a
7110 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7113 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7114 || (GET_CODE (op1) == REG
7115 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7116 tem = op0, op0 = op1, op1 = tem;
7118 gen_reload (out, op0, opnum, type);
7120 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7121 This fixes a problem on the 32K where the stack pointer cannot
7122 be used as an operand of an add insn. */
7124 if (rtx_equal_p (op0, op1))
7127 insn = emit_insn (gen_add2_insn (out, op1));
7129 /* If that failed, copy the address register to the reload register.
7130 Then add the constant to the reload register. */
7132 code = recog_memoized (insn);
7136 insn_extract (insn);
7137 /* We want constrain operands to treat this insn strictly in
7138 its validity determination, i.e., the way it would after reload
7140 if (constrain_operands (code, 1))
7144 delete_insns_since (last);
7146 gen_reload (out, op1, opnum, type);
7147 emit_insn (gen_add2_insn (out, op0));
7150 #ifdef SECONDARY_MEMORY_NEEDED
7151 /* If we need a memory location to do the move, do it that way. */
7152 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7153 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7154 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7155 REGNO_REG_CLASS (REGNO (out)),
7158 /* Get the memory to use and rewrite both registers to its mode. */
7159 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7161 if (GET_MODE (loc) != GET_MODE (out))
7162 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
7164 if (GET_MODE (loc) != GET_MODE (in))
7165 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
7167 gen_reload (loc, in, opnum, type);
7168 gen_reload (out, loc, opnum, type);
7172 /* If IN is a simple operand, use gen_move_insn. */
7173 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7174 emit_insn (gen_move_insn (out, in));
7176 #ifdef HAVE_reload_load_address
7177 else if (HAVE_reload_load_address)
7178 emit_insn (gen_reload_load_address (out, in));
7181 /* Otherwise, just write (set OUT IN) and hope for the best. */
7183 emit_insn (gen_rtx (SET, VOIDmode, out, in));
7185 /* Return the first insn emitted.
7186 We can not just return get_last_insn, because there may have
7187 been multiple instructions emitted. Also note that gen_move_insn may
7188 emit more than one insn itself, so we can not assume that there is one
7189 insn emitted per emit_insn_before call. */
7191 return last ? NEXT_INSN (last) : get_insns ();
7194 /* Delete a previously made output-reload
7195 whose result we now believe is not needed.
7196 First we double-check.
7198 INSN is the insn now being processed.
7199 OUTPUT_RELOAD_INSN is the insn of the output reload.
7200 J is the reload-number for this insn. */
7203 delete_output_reload (insn, j, output_reload_insn)
7206 rtx output_reload_insn;
7210 /* Get the raw pseudo-register referred to. */
7212 rtx reg = reload_in[j];
7213 while (GET_CODE (reg) == SUBREG)
7214 reg = SUBREG_REG (reg);
7216 /* If the pseudo-reg we are reloading is no longer referenced
7217 anywhere between the store into it and here,
7218 and no jumps or labels intervene, then the value can get
7219 here through the reload reg alone.
7220 Otherwise, give up--return. */
7221 for (i1 = NEXT_INSN (output_reload_insn);
7222 i1 != insn; i1 = NEXT_INSN (i1))
7224 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7226 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7227 && reg_mentioned_p (reg, PATTERN (i1)))
7231 if (cannot_omit_stores[REGNO (reg)])
7234 /* If this insn will store in the pseudo again,
7235 the previous store can be removed. */
7236 if (reload_out[j] == reload_in[j])
7237 delete_insn (output_reload_insn);
7239 /* See if the pseudo reg has been completely replaced
7240 with reload regs. If so, delete the store insn
7241 and forget we had a stack slot for the pseudo. */
7242 else if (reg_n_deaths[REGNO (reg)] == 1
7243 && reg_basic_block[REGNO (reg)] >= 0
7244 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7248 /* We know that it was used only between here
7249 and the beginning of the current basic block.
7250 (We also know that the last use before INSN was
7251 the output reload we are thinking of deleting, but never mind that.)
7252 Search that range; see if any ref remains. */
7253 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7255 rtx set = single_set (i2);
7257 /* Uses which just store in the pseudo don't count,
7258 since if they are the only uses, they are dead. */
7259 if (set != 0 && SET_DEST (set) == reg)
7261 if (GET_CODE (i2) == CODE_LABEL
7262 || GET_CODE (i2) == JUMP_INSN)
7264 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7265 && reg_mentioned_p (reg, PATTERN (i2)))
7266 /* Some other ref remains;
7267 we can't do anything. */
7271 /* Delete the now-dead stores into this pseudo. */
7272 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7274 rtx set = single_set (i2);
7276 if (set != 0 && SET_DEST (set) == reg)
7278 /* This might be a basic block head,
7279 thus don't use delete_insn. */
7280 PUT_CODE (i2, NOTE);
7281 NOTE_SOURCE_FILE (i2) = 0;
7282 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7284 if (GET_CODE (i2) == CODE_LABEL
7285 || GET_CODE (i2) == JUMP_INSN)
7289 /* For the debugging info,
7290 say the pseudo lives in this reload reg. */
7291 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7292 alter_reg (REGNO (reg), -1);
7296 /* Output reload-insns to reload VALUE into RELOADREG.
7297 VALUE is an autoincrement or autodecrement RTX whose operand
7298 is a register or memory location;
7299 so reloading involves incrementing that location.
7301 INC_AMOUNT is the number to increment or decrement by (always positive).
7302 This cannot be deduced from VALUE. */
7305 inc_for_reload (reloadreg, value, inc_amount)
7310 /* REG or MEM to be copied and incremented. */
7311 rtx incloc = XEXP (value, 0);
7312 /* Nonzero if increment after copying. */
7313 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7319 /* No hard register is equivalent to this register after
7320 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7321 we could inc/dec that register as well (maybe even using it for
7322 the source), but I'm not sure it's worth worrying about. */
7323 if (GET_CODE (incloc) == REG)
7324 reg_last_reload_reg[REGNO (incloc)] = 0;
7326 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7327 inc_amount = - inc_amount;
7329 inc = GEN_INT (inc_amount);
7331 /* If this is post-increment, first copy the location to the reload reg. */
7333 emit_insn (gen_move_insn (reloadreg, incloc));
7335 /* See if we can directly increment INCLOC. Use a method similar to that
7338 last = get_last_insn ();
7339 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7340 gen_rtx (PLUS, GET_MODE (incloc),
7343 code = recog_memoized (add_insn);
7346 insn_extract (add_insn);
7347 if (constrain_operands (code, 1))
7349 /* If this is a pre-increment and we have incremented the value
7350 where it lives, copy the incremented value to RELOADREG to
7351 be used as an address. */
7354 emit_insn (gen_move_insn (reloadreg, incloc));
7360 delete_insns_since (last);
7362 /* If couldn't do the increment directly, must increment in RELOADREG.
7363 The way we do this depends on whether this is pre- or post-increment.
7364 For pre-increment, copy INCLOC to the reload register, increment it
7365 there, then save back. */
7369 emit_insn (gen_move_insn (reloadreg, incloc));
7370 emit_insn (gen_add2_insn (reloadreg, inc));
7371 emit_insn (gen_move_insn (incloc, reloadreg));
7376 Because this might be a jump insn or a compare, and because RELOADREG
7377 may not be available after the insn in an input reload, we must do
7378 the incrementation before the insn being reloaded for.
7380 We have already copied INCLOC to RELOADREG. Increment the copy in
7381 RELOADREG, save that back, then decrement RELOADREG so it has
7382 the original value. */
7384 emit_insn (gen_add2_insn (reloadreg, inc));
7385 emit_insn (gen_move_insn (incloc, reloadreg));
7386 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7392 /* Return 1 if we are certain that the constraint-string STRING allows
7393 the hard register REG. Return 0 if we can't be sure of this. */
7396 constraint_accepts_reg_p (string, reg)
7401 int regno = true_regnum (reg);
7404 /* Initialize for first alternative. */
7406 /* Check that each alternative contains `g' or `r'. */
7408 switch (c = *string++)
7411 /* If an alternative lacks `g' or `r', we lose. */
7414 /* If an alternative lacks `g' or `r', we lose. */
7417 /* Initialize for next alternative. */
7422 /* Any general reg wins for this alternative. */
7423 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7427 /* Any reg in specified class wins for this alternative. */
7429 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7431 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7437 /* Return the number of places FIND appears within X, but don't count
7438 an occurrence if some SET_DEST is FIND. */
7441 count_occurrences (x, find)
7442 register rtx x, find;
7445 register enum rtx_code code;
7446 register char *format_ptr;
7454 code = GET_CODE (x);
7469 if (SET_DEST (x) == find)
7470 return count_occurrences (SET_SRC (x), find);
7474 format_ptr = GET_RTX_FORMAT (code);
7477 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7479 switch (*format_ptr++)
7482 count += count_occurrences (XEXP (x, i), find);
7486 if (XVEC (x, i) != NULL)
7488 for (j = 0; j < XVECLEN (x, i); j++)
7489 count += count_occurrences (XVECEXP (x, i, j), find);
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