1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Describes order of preference for putting regs into spill_regs.
219 Contains the numbers of all the hard regs, in order most preferred first.
220 This order is different for each function.
221 It is set up by order_regs_for_reload.
222 Empty elements at the end contain -1. */
223 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
225 /* Nonzero if indirect addressing is supported on the machine; this means
226 that spilling (REG n) does not require reloading it into a register in
227 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
228 value indicates the level of indirect addressing supported, e.g., two
229 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
231 static char spill_indirect_levels;
233 /* Nonzero if indirect addressing is supported when the innermost MEM is
234 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
235 which these are valid is the same as spill_indirect_levels, above. */
236 char indirect_symref_ok;
238 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
239 char double_reg_address_ok;
241 /* Record the stack slot for each spilled hard register. */
242 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
244 /* Width allocated so far for that stack slot. */
245 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
247 /* Record which pseudos needed to be spilled. */
248 static regset spilled_pseudos;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory used while processing one insn. */
279 char *reload_firstobj;
281 #define obstack_chunk_alloc xmalloc
282 #define obstack_chunk_free free
284 /* List of insn_chain instructions, one for every insn that reload needs to
286 struct insn_chain *reload_insn_chain;
289 extern tree current_function_decl;
291 extern union tree_node *current_function_decl;
294 /* List of all insns needing reloads. */
295 static struct insn_chain *insns_need_reload;
297 /* This structure is used to record information about register eliminations.
298 Each array entry describes one possible way of eliminating a register
299 in favor of another. If there is more than one way of eliminating a
300 particular register, the most preferred should be specified first. */
304 int from; /* Register number to be eliminated. */
305 int to; /* Register number used as replacement. */
306 int initial_offset; /* Initial difference between values. */
307 int can_eliminate; /* Non-zero if this elimination can be done. */
308 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
309 insns made by reload. */
310 int offset; /* Current offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 static struct elim_table * reg_eliminate = 0;
323 /* This is an intermediate structure to initialize the table. It has
324 exactly the members provided by ELIMINABLE_REGS. */
325 static struct elim_table_1
329 } reg_eliminate_1[] =
331 /* If a set of eliminable registers was specified, define the table from it.
332 Otherwise, default to the normal case of the frame pointer being
333 replaced by the stack pointer. */
335 #ifdef ELIMINABLE_REGS
338 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
341 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
343 /* Record the number of pending eliminations that have an offset not equal
344 to their initial offset. If non-zero, we use a new copy of each
345 replacement result in any insns encountered. */
346 int num_not_at_initial_offset;
348 /* Count the number of registers that we may be able to eliminate. */
349 static int num_eliminable;
350 /* And the number of registers that are equivalent to a constant that
351 can be eliminated to frame_pointer / arg_pointer + constant. */
352 static int num_eliminable_invariants;
354 /* For each label, we record the offset of each elimination. If we reach
355 a label by more than one path and an offset differs, we cannot do the
356 elimination. This information is indexed by the number of the label.
357 The first table is an array of flags that records whether we have yet
358 encountered a label and the second table is an array of arrays, one
359 entry in the latter array for each elimination. */
361 static char *offsets_known_at;
362 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
364 /* Number of labels in the current function. */
366 static int num_labels;
368 struct hard_reg_n_uses
374 static void maybe_fix_stack_asms PROTO((void));
375 static void calculate_needs_all_insns PROTO((int));
376 static void calculate_needs PROTO((struct insn_chain *));
377 static void find_reload_regs PROTO((struct insn_chain *chain,
379 static void find_tworeg_group PROTO((struct insn_chain *, int,
381 static void find_group PROTO((struct insn_chain *, int,
383 static int possible_group_p PROTO((struct insn_chain *, int));
384 static void count_possible_groups PROTO((struct insn_chain *, int));
385 static int modes_equiv_for_class_p PROTO((enum machine_mode,
388 static void delete_caller_save_insns PROTO((void));
390 static void spill_failure PROTO((rtx));
391 static void new_spill_reg PROTO((struct insn_chain *, int, int,
393 static void maybe_mark_pseudo_spilled PROTO((int));
394 static void delete_dead_insn PROTO((rtx));
395 static void alter_reg PROTO((int, int));
396 static void set_label_offsets PROTO((rtx, rtx, int));
397 static void check_eliminable_occurrences PROTO((rtx));
398 static void elimination_effects PROTO((rtx, enum machine_mode));
399 static int eliminate_regs_in_insn PROTO((rtx, int));
400 static void update_eliminable_offsets PROTO((void));
401 static void mark_not_eliminable PROTO((rtx, rtx, void *));
402 static void set_initial_elim_offsets PROTO((void));
403 static void verify_initial_elim_offsets PROTO((void));
404 static void set_initial_label_offsets PROTO((void));
405 static void set_offsets_for_label PROTO((rtx));
406 static void init_elim_table PROTO((void));
407 static void update_eliminables PROTO((HARD_REG_SET *));
408 static void spill_hard_reg PROTO((int, FILE *, int));
409 static int finish_spills PROTO((int, FILE *));
410 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
411 static void scan_paradoxical_subregs PROTO((rtx));
412 static int hard_reg_use_compare PROTO((const PTR, const PTR));
413 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
414 static void order_regs_for_reload PROTO((struct insn_chain *));
415 static void reload_as_needed PROTO((int));
416 static void forget_old_reloads_1 PROTO((rtx, rtx, void *));
417 static int reload_reg_class_lower PROTO((const PTR, const PTR));
418 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
420 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
422 static int reload_reg_free_p PROTO((int, int, enum reload_type));
423 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
424 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
425 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
427 static void choose_reload_regs_init PROTO((struct insn_chain *, rtx *));
428 static void choose_reload_regs PROTO((struct insn_chain *));
429 static void merge_assigned_reloads PROTO((rtx));
430 static void emit_reload_insns PROTO((struct insn_chain *));
431 static void delete_output_reload PROTO((rtx, int, int));
432 static void delete_address_reloads PROTO((rtx, rtx));
433 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
434 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
435 static int constraint_accepts_reg_p PROTO((const char *, rtx));
436 static void reload_cse_regs_1 PROTO((rtx));
437 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
438 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
439 static void reload_cse_invalidate_mem PROTO((rtx));
440 static void reload_cse_invalidate_rtx PROTO((rtx, rtx, void *));
441 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
442 static int reload_cse_noop_set_p PROTO((rtx, rtx));
443 static int reload_cse_simplify_set PROTO((rtx, rtx));
444 static int reload_cse_simplify_operands PROTO((rtx));
445 static void reload_cse_check_clobber PROTO((rtx, rtx, void *));
446 static void reload_cse_record_set PROTO((rtx, rtx));
447 static void reload_combine PROTO((void));
448 static void reload_combine_note_use PROTO((rtx *, rtx));
449 static void reload_combine_note_store PROTO((rtx, rtx, void *));
450 static void reload_cse_move2add PROTO((rtx));
451 static void move2add_note_store PROTO((rtx, rtx, void *));
453 static void add_auto_inc_notes PROTO((rtx, rtx));
455 static rtx gen_mode_int PROTO((enum machine_mode,
457 extern void dump_needs PROTO((struct insn_chain *, FILE *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
512 /* List of insn chains that are currently unused. */
513 static struct insn_chain *unused_insn_chains = 0;
515 /* Allocate an empty insn_chain structure. */
519 struct insn_chain *c;
521 if (unused_insn_chains == 0)
523 c = (struct insn_chain *)
524 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
525 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
526 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
530 c = unused_insn_chains;
531 unused_insn_chains = c->next;
533 c->is_caller_save_insn = 0;
534 c->need_operand_change = 0;
540 /* Small utility function to set all regs in hard reg set TO which are
541 allocated to pseudos in regset FROM. */
543 compute_use_by_pseudos (to, from)
548 EXECUTE_IF_SET_IN_REG_SET
549 (from, FIRST_PSEUDO_REGISTER, regno,
551 int r = reg_renumber[regno];
555 /* reload_combine uses the information from
556 BASIC_BLOCK->global_live_at_start, which might still
557 contain registers that have not actually been allocated
558 since they have an equivalence. */
559 if (! reload_completed)
564 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
566 SET_HARD_REG_BIT (*to, r + nregs);
571 /* Global variables used by reload and its subroutines. */
573 /* Set during calculate_needs if an insn needs register elimination. */
574 static int something_needs_elimination;
575 /* Set during calculate_needs if an insn needs an operand changed. */
576 int something_needs_operands_changed;
578 /* Nonzero means we couldn't get enough spill regs. */
581 /* Main entry point for the reload pass.
583 FIRST is the first insn of the function being compiled.
585 GLOBAL nonzero means we were called from global_alloc
586 and should attempt to reallocate any pseudoregs that we
587 displace from hard regs we will use for reloads.
588 If GLOBAL is zero, we do not have enough information to do that,
589 so any pseudo reg that is spilled must go to the stack.
591 DUMPFILE is the global-reg debugging dump file stream, or 0.
592 If it is nonzero, messages are written to it to describe
593 which registers are seized as reload regs, which pseudo regs
594 are spilled from them, and where the pseudo regs are reallocated to.
596 Return value is nonzero if reload failed
597 and we must not do any more for this function. */
600 reload (first, global, dumpfile)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
653 if (! call_used_regs[i] && ! fixed_regs[i])
654 regs_ever_live[i] = 1;
657 /* Find all the pseudo registers that didn't get hard regs
658 but do have known equivalent constants or memory slots.
659 These include parameters (known equivalent to parameter slots)
660 and cse'd or loop-moved constant memory addresses.
662 Record constant equivalents in reg_equiv_constant
663 so they will be substituted by find_reloads.
664 Record memory equivalents in reg_mem_equiv so they can
665 be substituted eventually by altering the REG-rtx's. */
667 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
673 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
674 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
675 pseudo_forbidden_regs
676 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
678 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
680 CLEAR_HARD_REG_SET (bad_spill_regs_global);
682 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
683 Also find all paradoxical subregs and find largest such for each pseudo.
684 On machines with small register classes, record hard registers that
685 are used for user variables. These can never be used for spills.
686 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
687 caller-saved registers must be marked live. */
689 num_eliminable_invariants = 0;
690 for (insn = first; insn; insn = NEXT_INSN (insn))
692 rtx set = single_set (insn);
694 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
697 if (! call_used_regs[i])
698 regs_ever_live[i] = 1;
700 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
702 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
704 #ifdef LEGITIMATE_PIC_OPERAND_P
705 && (! function_invariant_p (XEXP (note, 0))
707 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
711 rtx x = XEXP (note, 0);
712 i = REGNO (SET_DEST (set));
713 if (i > LAST_VIRTUAL_REGISTER)
715 if (GET_CODE (x) == MEM)
717 /* If the operand is a PLUS, the MEM may be shared,
718 so make sure we have an unshared copy here. */
719 if (GET_CODE (XEXP (x, 0)) == PLUS)
722 reg_equiv_memory_loc[i] = x;
724 else if (function_invariant_p (x))
726 if (GET_CODE (x) == PLUS)
728 /* This is PLUS of frame pointer and a constant,
729 and might be shared. Unshare it. */
730 reg_equiv_constant[i] = copy_rtx (x);
731 num_eliminable_invariants++;
733 else if (x == frame_pointer_rtx
734 || x == arg_pointer_rtx)
736 reg_equiv_constant[i] = x;
737 num_eliminable_invariants++;
739 else if (LEGITIMATE_CONSTANT_P (x))
740 reg_equiv_constant[i] = x;
742 reg_equiv_memory_loc[i]
743 = force_const_mem (GET_MODE (SET_DEST (set)), x);
748 /* If this register is being made equivalent to a MEM
749 and the MEM is not SET_SRC, the equivalencing insn
750 is one with the MEM as a SET_DEST and it occurs later.
751 So don't mark this insn now. */
752 if (GET_CODE (x) != MEM
753 || rtx_equal_p (SET_SRC (set), x))
755 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
760 /* If this insn is setting a MEM from a register equivalent to it,
761 this is the equivalencing insn. */
762 else if (set && GET_CODE (SET_DEST (set)) == MEM
763 && GET_CODE (SET_SRC (set)) == REG
764 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
765 && rtx_equal_p (SET_DEST (set),
766 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
767 reg_equiv_init[REGNO (SET_SRC (set))]
768 = gen_rtx_INSN_LIST (VOIDmode, insn,
769 reg_equiv_init[REGNO (SET_SRC (set))]);
771 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
772 scan_paradoxical_subregs (PATTERN (insn));
777 num_labels = max_label_num () - get_first_label_num ();
779 /* Allocate the tables used to store offset information at labels. */
780 /* We used to use alloca here, but the size of what it would try to
781 allocate would occasionally cause it to exceed the stack limit and
782 cause a core dump. */
783 real_known_ptr = xmalloc (num_labels);
785 = (int (*)[NUM_ELIMINABLE_REGS])
786 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
788 offsets_known_at = real_known_ptr - get_first_label_num ();
790 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
792 /* Alter each pseudo-reg rtx to contain its hard reg number.
793 Assign stack slots to the pseudos that lack hard regs or equivalents.
794 Do not touch virtual registers. */
796 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
807 || GET_CODE (insn) == CALL_INSN)
808 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
810 maybe_fix_stack_asms ();
812 insns_need_reload = 0;
813 something_needs_elimination = 0;
815 /* Initialize to -1, which means take the first spill register. */
818 spilled_pseudos = ALLOCA_REG_SET ();
820 /* Spill any hard regs that we know we can't eliminate. */
821 CLEAR_HARD_REG_SET (used_spill_regs);
822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
823 if (! ep->can_eliminate)
824 spill_hard_reg (ep->from, dumpfile, 1);
826 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
827 if (frame_pointer_needed)
828 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
830 finish_spills (global, dumpfile);
832 /* From now on, we may need to generate moves differently. We may also
833 allow modifications of insns which cause them to not be recognized.
834 Any such modifications will be cleaned up during reload itself. */
835 reload_in_progress = 1;
837 /* This loop scans the entire function each go-round
838 and repeats until one repetition spills no additional hard regs. */
841 int something_changed;
843 struct insn_chain *chain;
845 HOST_WIDE_INT starting_frame_size;
847 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
848 here because the stack size may be a part of the offset computation
849 for register elimination, and there might have been new stack slots
850 created in the last iteration of this loop. */
851 assign_stack_local (BLKmode, 0, 0);
853 starting_frame_size = get_frame_size ();
855 set_initial_elim_offsets ();
856 set_initial_label_offsets ();
858 /* For each pseudo register that has an equivalent location defined,
859 try to eliminate any eliminable registers (such as the frame pointer)
860 assuming initial offsets for the replacement register, which
863 If the resulting location is directly addressable, substitute
864 the MEM we just got directly for the old REG.
866 If it is not addressable but is a constant or the sum of a hard reg
867 and constant, it is probably not addressable because the constant is
868 out of range, in that case record the address; we will generate
869 hairy code to compute the address in a register each time it is
870 needed. Similarly if it is a hard register, but one that is not
871 valid as an address register.
873 If the location is not addressable, but does not have one of the
874 above forms, assign a stack slot. We have to do this to avoid the
875 potential of producing lots of reloads if, e.g., a location involves
876 a pseudo that didn't get a hard register and has an equivalent memory
877 location that also involves a pseudo that didn't get a hard register.
879 Perhaps at some point we will improve reload_when_needed handling
880 so this problem goes away. But that's very hairy. */
882 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
883 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
885 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
887 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
889 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
890 else if (CONSTANT_P (XEXP (x, 0))
891 || (GET_CODE (XEXP (x, 0)) == REG
892 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
893 || (GET_CODE (XEXP (x, 0)) == PLUS
894 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
895 && (REGNO (XEXP (XEXP (x, 0), 0))
896 < FIRST_PSEUDO_REGISTER)
897 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
898 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc[i] = 0;
908 reg_equiv_init[i] = 0;
913 if (caller_save_needed)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (starting_frame_size != get_frame_size ())
920 if (caller_save_needed)
922 save_call_clobbered_regs ();
923 /* That might have allocated new insn_chain structures. */
924 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
927 calculate_needs_all_insns (global);
929 CLEAR_REG_SET (spilled_pseudos);
932 something_changed = 0;
934 /* If we allocated any new memory locations, make another pass
935 since it might have changed elimination offsets. */
936 if (starting_frame_size != get_frame_size ())
937 something_changed = 1;
940 HARD_REG_SET to_spill;
941 CLEAR_HARD_REG_SET (to_spill);
942 update_eliminables (&to_spill);
943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
944 if (TEST_HARD_REG_BIT (to_spill, i))
946 spill_hard_reg (i, dumpfile, 1);
949 /* Regardless of the state of spills, if we previously had
950 a register that we thought we could eliminate, but no can
951 not eliminate, we must run another pass.
953 Consider pseudos which have an entry in reg_equiv_* which
954 reference an eliminable register. We must make another pass
955 to update reg_equiv_* so that we do not substitute in the
956 old value from when we thought the elimination could be
958 something_changed = 1;
962 CLEAR_HARD_REG_SET (used_spill_regs);
963 /* Try to satisfy the needs for each insn. */
964 for (chain = insns_need_reload; chain != 0;
965 chain = chain->next_need_reload)
966 find_reload_regs (chain, dumpfile);
971 if (insns_need_reload != 0 || did_spill)
972 something_changed |= finish_spills (global, dumpfile);
974 if (! something_changed)
977 if (caller_save_needed)
978 delete_caller_save_insns ();
981 /* If global-alloc was run, notify it of any register eliminations we have
984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
985 if (ep->can_eliminate)
986 mark_elimination (ep->from, ep->to);
988 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
989 If that insn didn't set the register (i.e., it copied the register to
990 memory), just delete that insn instead of the equivalencing insn plus
991 anything now dead. If we call delete_dead_insn on that insn, we may
992 delete the insn that actually sets the register if the register dies
993 there and that is incorrect. */
995 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
997 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1000 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1002 rtx equiv_insn = XEXP (list, 0);
1003 if (GET_CODE (equiv_insn) == NOTE)
1005 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1006 delete_dead_insn (equiv_insn);
1009 PUT_CODE (equiv_insn, NOTE);
1010 NOTE_SOURCE_FILE (equiv_insn) = 0;
1011 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1017 /* Use the reload registers where necessary
1018 by generating move instructions to move the must-be-register
1019 values into or out of the reload registers. */
1021 if (insns_need_reload != 0 || something_needs_elimination
1022 || something_needs_operands_changed)
1024 int old_frame_size = get_frame_size ();
1026 reload_as_needed (global);
1028 if (old_frame_size != get_frame_size ())
1032 verify_initial_elim_offsets ();
1035 /* If we were able to eliminate the frame pointer, show that it is no
1036 longer live at the start of any basic block. If it ls live by
1037 virtue of being in a pseudo, that pseudo will be marked live
1038 and hence the frame pointer will be known to be live via that
1041 if (! frame_pointer_needed)
1042 for (i = 0; i < n_basic_blocks; i++)
1043 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1044 HARD_FRAME_POINTER_REGNUM);
1046 /* Come here (with failure set nonzero) if we can't get enough spill regs
1047 and we decide not to abort about it. */
1050 reload_in_progress = 0;
1052 /* Now eliminate all pseudo regs by modifying them into
1053 their equivalent memory references.
1054 The REG-rtx's for the pseudos are modified in place,
1055 so all insns that used to refer to them now refer to memory.
1057 For a reg that has a reg_equiv_address, all those insns
1058 were changed by reloading so that no insns refer to it any longer;
1059 but the DECL_RTL of a variable decl may refer to it,
1060 and if so this causes the debugging info to mention the variable. */
1062 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1067 int is_readonly = 0;
1069 if (reg_equiv_memory_loc[i])
1071 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1072 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1073 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1076 if (reg_equiv_mem[i])
1077 addr = XEXP (reg_equiv_mem[i], 0);
1079 if (reg_equiv_address[i])
1080 addr = reg_equiv_address[i];
1084 if (reg_renumber[i] < 0)
1086 rtx reg = regno_reg_rtx[i];
1087 PUT_CODE (reg, MEM);
1088 XEXP (reg, 0) = addr;
1089 REG_USERVAR_P (reg) = 0;
1090 RTX_UNCHANGING_P (reg) = is_readonly;
1091 MEM_IN_STRUCT_P (reg) = in_struct;
1092 MEM_SCALAR_P (reg) = is_scalar;
1093 /* We have no alias information about this newly created
1095 MEM_ALIAS_SET (reg) = 0;
1097 else if (reg_equiv_mem[i])
1098 XEXP (reg_equiv_mem[i], 0) = addr;
1102 /* We must set reload_completed now since the cleanup_subreg_operands call
1103 below will re-recognize each insn and reload may have generated insns
1104 which are only valid during and after reload. */
1105 reload_completed = 1;
1107 /* Make a pass over all the insns and delete all USEs which we
1108 inserted only to tag a REG_EQUAL note on them. Remove all
1109 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1110 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1111 REG_LIBCALL notes since they are no longer useful or accurate.
1112 Strip and regenerate REG_INC notes that may have been moved
1115 for (insn = first; insn; insn = NEXT_INSN (insn))
1116 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1120 if ((GET_CODE (PATTERN (insn)) == USE
1121 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1122 || GET_CODE (PATTERN (insn)) == CLOBBER)
1124 PUT_CODE (insn, NOTE);
1125 NOTE_SOURCE_FILE (insn) = 0;
1126 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1130 pnote = ®_NOTES (insn);
1133 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1134 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1135 || REG_NOTE_KIND (*pnote) == REG_INC
1136 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1137 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1138 *pnote = XEXP (*pnote, 1);
1140 pnote = &XEXP (*pnote, 1);
1144 add_auto_inc_notes (insn, PATTERN (insn));
1147 /* And simplify (subreg (reg)) if it appears as an operand. */
1148 cleanup_subreg_operands (insn);
1151 /* If we are doing stack checking, give a warning if this function's
1152 frame size is larger than we expect. */
1153 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1155 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1156 static int verbose_warned = 0;
1158 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1159 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1160 size += UNITS_PER_WORD;
1162 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1164 warning ("frame size too large for reliable stack checking");
1165 if (! verbose_warned)
1167 warning ("try reducing the number of local variables");
1173 /* Indicate that we no longer have known memory locations or constants. */
1174 if (reg_equiv_constant)
1175 free (reg_equiv_constant);
1176 reg_equiv_constant = 0;
1177 if (reg_equiv_memory_loc)
1178 free (reg_equiv_memory_loc);
1179 reg_equiv_memory_loc = 0;
1182 free (real_known_ptr);
1186 free (reg_equiv_mem);
1187 free (reg_equiv_init);
1188 free (reg_equiv_address);
1189 free (reg_max_ref_width);
1190 free (reg_old_renumber);
1191 free (pseudo_previous_regs);
1192 free (pseudo_forbidden_regs);
1194 FREE_REG_SET (spilled_pseudos);
1196 CLEAR_HARD_REG_SET (used_spill_regs);
1197 for (i = 0; i < n_spills; i++)
1198 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1200 /* Free all the insn_chain structures at once. */
1201 obstack_free (&reload_obstack, reload_startobj);
1202 unused_insn_chains = 0;
1207 /* Yet another special case. Unfortunately, reg-stack forces people to
1208 write incorrect clobbers in asm statements. These clobbers must not
1209 cause the register to appear in bad_spill_regs, otherwise we'll call
1210 fatal_insn later. We clear the corresponding regnos in the live
1211 register sets to avoid this.
1212 The whole thing is rather sick, I'm afraid. */
1214 maybe_fix_stack_asms ()
1217 const char *constraints[MAX_RECOG_OPERANDS];
1218 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1219 struct insn_chain *chain;
1221 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1224 HARD_REG_SET clobbered, allowed;
1227 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1228 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1230 pat = PATTERN (chain->insn);
1231 if (GET_CODE (pat) != PARALLEL)
1234 CLEAR_HARD_REG_SET (clobbered);
1235 CLEAR_HARD_REG_SET (allowed);
1237 /* First, make a mask of all stack regs that are clobbered. */
1238 for (i = 0; i < XVECLEN (pat, 0); i++)
1240 rtx t = XVECEXP (pat, 0, i);
1241 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1242 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1245 /* Get the operand values and constraints out of the insn. */
1246 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1247 constraints, operand_mode);
1249 /* For every operand, see what registers are allowed. */
1250 for (i = 0; i < noperands; i++)
1252 const char *p = constraints[i];
1253 /* For every alternative, we compute the class of registers allowed
1254 for reloading in CLS, and merge its contents into the reg set
1256 int cls = (int) NO_REGS;
1262 if (c == '\0' || c == ',' || c == '#')
1264 /* End of one alternative - mark the regs in the current
1265 class, and reset the class. */
1266 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1271 } while (c != '\0' && c != ',');
1279 case '=': case '+': case '*': case '%': case '?': case '!':
1280 case '0': case '1': case '2': case '3': case '4': case 'm':
1281 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1282 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1283 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1285 #ifdef EXTRA_CONSTRAINT
1286 case 'Q': case 'R': case 'S': case 'T': case 'U':
1291 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1296 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1300 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1305 /* Those of the registers which are clobbered, but allowed by the
1306 constraints, must be usable as reload registers. So clear them
1307 out of the life information. */
1308 AND_HARD_REG_SET (allowed, clobbered);
1309 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1310 if (TEST_HARD_REG_BIT (allowed, i))
1312 CLEAR_REGNO_REG_SET (chain->live_before, i);
1313 CLEAR_REGNO_REG_SET (chain->live_after, i);
1321 /* Walk the chain of insns, and determine for each whether it needs reloads
1322 and/or eliminations. Build the corresponding insns_need_reload list, and
1323 set something_needs_elimination as appropriate. */
1325 calculate_needs_all_insns (global)
1328 struct insn_chain **pprev_reload = &insns_need_reload;
1329 struct insn_chain *chain;
1331 something_needs_elimination = 0;
1333 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1335 rtx insn = chain->insn;
1337 /* Clear out the shortcuts, in case they were set last time through. */
1338 chain->need_elim = 0;
1339 chain->need_reload = 0;
1340 chain->need_operand_change = 0;
1342 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1343 include REG_LABEL), we need to see what effects this has on the
1344 known offsets at labels. */
1346 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1347 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1348 && REG_NOTES (insn) != 0))
1349 set_label_offsets (insn, insn, 0);
1351 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1353 rtx old_body = PATTERN (insn);
1354 int old_code = INSN_CODE (insn);
1355 rtx old_notes = REG_NOTES (insn);
1356 int did_elimination = 0;
1357 int operands_changed = 0;
1358 rtx set = single_set (insn);
1360 /* Skip insns that only set an equivalence. */
1361 if (set && GET_CODE (SET_DEST (set)) == REG
1362 && reg_renumber[REGNO (SET_DEST (set))] < 0
1363 && reg_equiv_constant[REGNO (SET_DEST (set))])
1366 /* If needed, eliminate any eliminable registers. */
1367 if (num_eliminable || num_eliminable_invariants)
1368 did_elimination = eliminate_regs_in_insn (insn, 0);
1370 /* Analyze the instruction. */
1371 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1372 global, spill_reg_order);
1374 /* If a no-op set needs more than one reload, this is likely
1375 to be something that needs input address reloads. We
1376 can't get rid of this cleanly later, and it is of no use
1377 anyway, so discard it now.
1378 We only do this when expensive_optimizations is enabled,
1379 since this complements reload inheritance / output
1380 reload deletion, and it can make debugging harder. */
1381 if (flag_expensive_optimizations && n_reloads > 1)
1383 rtx set = single_set (insn);
1385 && SET_SRC (set) == SET_DEST (set)
1386 && GET_CODE (SET_SRC (set)) == REG
1387 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1389 PUT_CODE (insn, NOTE);
1390 NOTE_SOURCE_FILE (insn) = 0;
1391 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1396 update_eliminable_offsets ();
1398 /* Remember for later shortcuts which insns had any reloads or
1399 register eliminations. */
1400 chain->need_elim = did_elimination;
1401 chain->need_reload = n_reloads > 0;
1402 chain->need_operand_change = operands_changed;
1404 /* Discard any register replacements done. */
1405 if (did_elimination)
1407 obstack_free (&reload_obstack, reload_firstobj);
1408 PATTERN (insn) = old_body;
1409 INSN_CODE (insn) = old_code;
1410 REG_NOTES (insn) = old_notes;
1411 something_needs_elimination = 1;
1414 something_needs_operands_changed |= operands_changed;
1418 *pprev_reload = chain;
1419 pprev_reload = &chain->next_need_reload;
1421 calculate_needs (chain);
1428 /* Compute the most additional registers needed by one instruction,
1429 given by CHAIN. Collect information separately for each class of regs.
1431 To compute the number of reload registers of each class needed for an
1432 insn, we must simulate what choose_reload_regs can do. We do this by
1433 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1434 reloads are used in both. The input part uses those reloads,
1435 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1436 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1437 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1439 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1440 which are live for the entire output portion, and the maximum of all the
1441 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1443 The total number of registers needed is the maximum of the
1444 inputs and outputs. */
1447 calculate_needs (chain)
1448 struct insn_chain *chain;
1452 /* Each `struct needs' corresponds to one RELOAD_... type. */
1456 struct needs output;
1458 struct needs other_addr;
1459 struct needs op_addr;
1460 struct needs op_addr_reload;
1461 struct needs in_addr[MAX_RECOG_OPERANDS];
1462 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1463 struct needs out_addr[MAX_RECOG_OPERANDS];
1464 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1467 bzero ((char *) chain->group_size, sizeof chain->group_size);
1468 for (i = 0; i < N_REG_CLASSES; i++)
1469 chain->group_mode[i] = VOIDmode;
1470 bzero ((char *) &insn_needs, sizeof insn_needs);
1472 /* Count each reload once in every class
1473 containing the reload's own class. */
1475 for (i = 0; i < n_reloads; i++)
1477 register enum reg_class *p;
1478 enum reg_class class = rld[i].class;
1480 enum machine_mode mode;
1481 struct needs *this_needs;
1483 /* Don't count the dummy reloads, for which one of the
1484 regs mentioned in the insn can be used for reloading.
1485 Don't count optional reloads.
1486 Don't count reloads that got combined with others. */
1487 if (rld[i].reg_rtx != 0
1488 || rld[i].optional != 0
1489 || (rld[i].out == 0 && rld[i].in == 0
1490 && ! rld[i].secondary_p))
1494 size = rld[i].nregs;
1496 /* Decide which time-of-use to count this reload for. */
1497 switch (rld[i].when_needed)
1500 this_needs = &insn_needs.other;
1502 case RELOAD_FOR_INPUT:
1503 this_needs = &insn_needs.input;
1505 case RELOAD_FOR_OUTPUT:
1506 this_needs = &insn_needs.output;
1508 case RELOAD_FOR_INSN:
1509 this_needs = &insn_needs.insn;
1511 case RELOAD_FOR_OTHER_ADDRESS:
1512 this_needs = &insn_needs.other_addr;
1514 case RELOAD_FOR_INPUT_ADDRESS:
1515 this_needs = &insn_needs.in_addr[rld[i].opnum];
1517 case RELOAD_FOR_INPADDR_ADDRESS:
1518 this_needs = &insn_needs.in_addr_addr[rld[i].opnum];
1520 case RELOAD_FOR_OUTPUT_ADDRESS:
1521 this_needs = &insn_needs.out_addr[rld[i].opnum];
1523 case RELOAD_FOR_OUTADDR_ADDRESS:
1524 this_needs = &insn_needs.out_addr_addr[rld[i].opnum];
1526 case RELOAD_FOR_OPERAND_ADDRESS:
1527 this_needs = &insn_needs.op_addr;
1529 case RELOAD_FOR_OPADDR_ADDR:
1530 this_needs = &insn_needs.op_addr_reload;
1538 enum machine_mode other_mode, allocate_mode;
1540 /* Count number of groups needed separately from
1541 number of individual regs needed. */
1542 this_needs->groups[(int) class]++;
1543 p = reg_class_superclasses[(int) class];
1544 while (*p != LIM_REG_CLASSES)
1545 this_needs->groups[(int) *p++]++;
1547 /* Record size and mode of a group of this class. */
1548 /* If more than one size group is needed,
1549 make all groups the largest needed size. */
1550 if (chain->group_size[(int) class] < size)
1552 other_mode = chain->group_mode[(int) class];
1553 allocate_mode = mode;
1555 chain->group_size[(int) class] = size;
1556 chain->group_mode[(int) class] = mode;
1561 allocate_mode = chain->group_mode[(int) class];
1564 /* Crash if two dissimilar machine modes both need
1565 groups of consecutive regs of the same class. */
1567 if (other_mode != VOIDmode && other_mode != allocate_mode
1568 && ! modes_equiv_for_class_p (allocate_mode,
1570 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1575 this_needs->regs[(unsigned char)rld[i].nongroup][(int) class] += 1;
1576 p = reg_class_superclasses[(int) class];
1577 while (*p != LIM_REG_CLASSES)
1578 this_needs->regs[(unsigned char)rld[i].nongroup][(int) *p++] += 1;
1584 /* All reloads have been counted for this insn;
1585 now merge the various times of use.
1586 This sets insn_needs, etc., to the maximum total number
1587 of registers needed at any point in this insn. */
1589 for (i = 0; i < N_REG_CLASSES; i++)
1591 int j, in_max, out_max;
1593 /* Compute normal and nongroup needs. */
1594 for (j = 0; j <= 1; j++)
1597 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1599 in_max = MAX (in_max,
1600 (insn_needs.in_addr[k].regs[j][i]
1601 + insn_needs.in_addr_addr[k].regs[j][i]));
1602 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1603 out_max = MAX (out_max,
1604 insn_needs.out_addr_addr[k].regs[j][i]);
1607 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1608 and operand addresses but not things used to reload
1609 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1610 don't conflict with things needed to reload inputs or
1613 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1614 insn_needs.op_addr_reload.regs[j][i]),
1617 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1619 insn_needs.input.regs[j][i]
1620 = MAX (insn_needs.input.regs[j][i]
1621 + insn_needs.op_addr.regs[j][i]
1622 + insn_needs.insn.regs[j][i],
1623 in_max + insn_needs.input.regs[j][i]);
1625 insn_needs.output.regs[j][i] += out_max;
1626 insn_needs.other.regs[j][i]
1627 += MAX (MAX (insn_needs.input.regs[j][i],
1628 insn_needs.output.regs[j][i]),
1629 insn_needs.other_addr.regs[j][i]);
1633 /* Now compute group needs. */
1634 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1636 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1637 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1638 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1639 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1642 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1643 insn_needs.op_addr_reload.groups[i]),
1645 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1647 insn_needs.input.groups[i]
1648 = MAX (insn_needs.input.groups[i]
1649 + insn_needs.op_addr.groups[i]
1650 + insn_needs.insn.groups[i],
1651 in_max + insn_needs.input.groups[i]);
1653 insn_needs.output.groups[i] += out_max;
1654 insn_needs.other.groups[i]
1655 += MAX (MAX (insn_needs.input.groups[i],
1656 insn_needs.output.groups[i]),
1657 insn_needs.other_addr.groups[i]);
1660 /* Record the needs for later. */
1661 chain->need = insn_needs.other;
1664 /* Find a group of exactly 2 registers.
1666 First try to fill out the group by spilling a single register which
1667 would allow completion of the group.
1669 Then try to create a new group from a pair of registers, neither of
1670 which are explicitly used.
1672 Then try to create a group from any pair of registers. */
1675 find_tworeg_group (chain, class, dumpfile)
1676 struct insn_chain *chain;
1681 /* First, look for a register that will complete a group. */
1682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1686 j = potential_reload_regs[i];
1687 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1688 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1689 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1690 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1691 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1692 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1693 /* We don't want one part of another group.
1694 We could get "two groups" that overlap! */
1695 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1696 || (j < FIRST_PSEUDO_REGISTER - 1
1697 && (other = j + 1, spill_reg_order[other] >= 0)
1698 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1699 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1700 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1701 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1702 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1704 register enum reg_class *p;
1706 /* We have found one that will complete a group,
1707 so count off one group as provided. */
1708 chain->need.groups[class]--;
1709 p = reg_class_superclasses[class];
1710 while (*p != LIM_REG_CLASSES)
1712 if (chain->group_size [(int) *p] <= chain->group_size [class])
1713 chain->need.groups[(int) *p]--;
1717 /* Indicate both these regs are part of a group. */
1718 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1719 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1723 /* We can't complete a group, so start one. */
1724 if (i == FIRST_PSEUDO_REGISTER)
1725 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1728 j = potential_reload_regs[i];
1729 /* Verify that J+1 is a potential reload reg. */
1730 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1731 if (potential_reload_regs[k] == j + 1)
1733 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1734 && k < FIRST_PSEUDO_REGISTER
1735 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1736 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1737 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1738 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1739 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1740 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1744 /* I should be the index in potential_reload_regs
1745 of the new reload reg we have found. */
1747 new_spill_reg (chain, i, class, 0, dumpfile);
1750 /* Find a group of more than 2 registers.
1751 Look for a sufficient sequence of unspilled registers, and spill them all
1755 find_group (chain, class, dumpfile)
1756 struct insn_chain *chain;
1762 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1764 int j = potential_reload_regs[i];
1767 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1768 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1771 /* Check each reg in the sequence. */
1772 for (k = 0; k < chain->group_size[class]; k++)
1773 if (! (spill_reg_order[j + k] < 0
1774 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1775 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1777 /* We got a full sequence, so spill them all. */
1778 if (k == chain->group_size[class])
1780 register enum reg_class *p;
1781 for (k = 0; k < chain->group_size[class]; k++)
1784 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1785 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1786 if (potential_reload_regs[idx] == j + k)
1788 new_spill_reg (chain, idx, class, 0, dumpfile);
1791 /* We have found one that will complete a group,
1792 so count off one group as provided. */
1793 chain->need.groups[class]--;
1794 p = reg_class_superclasses[class];
1795 while (*p != LIM_REG_CLASSES)
1797 if (chain->group_size [(int) *p]
1798 <= chain->group_size [class])
1799 chain->need.groups[(int) *p]--;
1806 /* There are no groups left. */
1807 spill_failure (chain->insn);
1811 /* If pseudo REG conflicts with one of our reload registers, mark it as
1814 maybe_mark_pseudo_spilled (reg)
1818 int r = reg_renumber[reg];
1823 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1824 for (i = 0; i < n_spills; i++)
1825 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1827 SET_REGNO_REG_SET (spilled_pseudos, reg);
1832 /* Find more reload regs to satisfy the remaining need of an insn, which
1834 Do it by ascending class number, since otherwise a reg
1835 might be spilled for a big class and might fail to count
1836 for a smaller class even though it belongs to that class.
1838 Count spilled regs in `spills', and add entries to
1839 `spill_regs' and `spill_reg_order'.
1841 ??? Note there is a problem here.
1842 When there is a need for a group in a high-numbered class,
1843 and also need for non-group regs that come from a lower class,
1844 the non-group regs are chosen first. If there aren't many regs,
1845 they might leave no room for a group.
1847 This was happening on the 386. To fix it, we added the code
1848 that calls possible_group_p, so that the lower class won't
1849 break up the last possible group.
1851 Really fixing the problem would require changes above
1852 in counting the regs already spilled, and in choose_reload_regs.
1853 It might be hard to avoid introducing bugs there. */
1856 find_reload_regs (chain, dumpfile)
1857 struct insn_chain *chain;
1861 short *group_needs = chain->need.groups;
1862 short *simple_needs = chain->need.regs[0];
1863 short *nongroup_needs = chain->need.regs[1];
1866 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1868 /* Compute the order of preference for hard registers to spill.
1869 Store them by decreasing preference in potential_reload_regs. */
1871 order_regs_for_reload (chain);
1873 /* So far, no hard regs have been spilled. */
1875 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1876 spill_reg_order[i] = -1;
1878 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1879 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1880 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1882 for (class = 0; class < N_REG_CLASSES; class++)
1884 /* First get the groups of registers.
1885 If we got single registers first, we might fragment
1887 while (group_needs[class] > 0)
1889 /* If any single spilled regs happen to form groups,
1890 count them now. Maybe we don't really need
1891 to spill another group. */
1892 count_possible_groups (chain, class);
1894 if (group_needs[class] <= 0)
1897 /* Groups of size 2, the only groups used on most machines,
1898 are treated specially. */
1899 if (chain->group_size[class] == 2)
1900 find_tworeg_group (chain, class, dumpfile);
1902 find_group (chain, class, dumpfile);
1907 /* Now similarly satisfy all need for single registers. */
1909 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1911 /* If we spilled enough regs, but they weren't counted
1912 against the non-group need, see if we can count them now.
1913 If so, we can avoid some actual spilling. */
1914 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1915 for (i = 0; i < n_spills; i++)
1917 int regno = spill_regs[i];
1918 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1919 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1920 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1921 && nongroup_needs[class] > 0)
1923 register enum reg_class *p;
1925 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1926 nongroup_needs[class]--;
1927 p = reg_class_superclasses[class];
1928 while (*p != LIM_REG_CLASSES)
1929 nongroup_needs[(int) *p++]--;
1933 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1936 /* Consider the potential reload regs that aren't
1937 yet in use as reload regs, in order of preference.
1938 Find the most preferred one that's in this class. */
1940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1942 int regno = potential_reload_regs[i];
1944 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1945 /* If this reg will not be available for groups,
1946 pick one that does not foreclose possible groups.
1947 This is a kludge, and not very general,
1948 but it should be sufficient to make the 386 work,
1949 and the problem should not occur on machines with
1951 && (nongroup_needs[class] == 0
1952 || possible_group_p (chain, regno)))
1956 /* If we couldn't get a register, try to get one even if we
1957 might foreclose possible groups. This may cause problems
1958 later, but that's better than aborting now, since it is
1959 possible that we will, in fact, be able to form the needed
1960 group even with this allocation. */
1962 if (i >= FIRST_PSEUDO_REGISTER
1963 && asm_noperands (chain->insn) < 0)
1964 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1965 if (potential_reload_regs[i] >= 0
1966 && TEST_HARD_REG_BIT (reg_class_contents[class],
1967 potential_reload_regs[i]))
1970 /* I should be the index in potential_reload_regs
1971 of the new reload reg we have found. */
1973 new_spill_reg (chain, i, class, 1, dumpfile);
1979 /* We know which hard regs to use, now mark the pseudos that live in them
1980 as needing to be kicked out. */
1981 EXECUTE_IF_SET_IN_REG_SET
1982 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1984 maybe_mark_pseudo_spilled (i);
1986 EXECUTE_IF_SET_IN_REG_SET
1987 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1989 maybe_mark_pseudo_spilled (i);
1992 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1996 dump_needs (chain, dumpfile)
1997 struct insn_chain *chain;
2000 static const char * const reg_class_names[] = REG_CLASS_NAMES;
2002 struct needs *n = &chain->need;
2004 for (i = 0; i < N_REG_CLASSES; i++)
2006 if (n->regs[i][0] > 0)
2008 ";; Need %d reg%s of class %s.\n",
2009 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2010 reg_class_names[i]);
2011 if (n->regs[i][1] > 0)
2013 ";; Need %d nongroup reg%s of class %s.\n",
2014 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2015 reg_class_names[i]);
2016 if (n->groups[i] > 0)
2018 ";; Need %d group%s (%smode) of class %s.\n",
2019 n->groups[i], n->groups[i] == 1 ? "" : "s",
2020 GET_MODE_NAME(chain->group_mode[i]),
2021 reg_class_names[i]);
2025 /* Delete all insns that were inserted by emit_caller_save_insns during
2028 delete_caller_save_insns ()
2030 struct insn_chain *c = reload_insn_chain;
2034 while (c != 0 && c->is_caller_save_insn)
2036 struct insn_chain *next = c->next;
2039 if (insn == BLOCK_HEAD (c->block))
2040 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2041 if (insn == BLOCK_END (c->block))
2042 BLOCK_END (c->block) = PREV_INSN (insn);
2043 if (c == reload_insn_chain)
2044 reload_insn_chain = next;
2046 if (NEXT_INSN (insn) != 0)
2047 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2048 if (PREV_INSN (insn) != 0)
2049 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2052 next->prev = c->prev;
2054 c->prev->next = next;
2055 c->next = unused_insn_chains;
2056 unused_insn_chains = c;
2064 /* Nonzero if, after spilling reg REGNO for non-groups,
2065 it will still be possible to find a group if we still need one. */
2068 possible_group_p (chain, regno)
2069 struct insn_chain *chain;
2073 int class = (int) NO_REGS;
2075 for (i = 0; i < (int) N_REG_CLASSES; i++)
2076 if (chain->need.groups[i] > 0)
2082 if (class == (int) NO_REGS)
2085 /* Consider each pair of consecutive registers. */
2086 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2088 /* Ignore pairs that include reg REGNO. */
2089 if (i == regno || i + 1 == regno)
2092 /* Ignore pairs that are outside the class that needs the group.
2093 ??? Here we fail to handle the case where two different classes
2094 independently need groups. But this never happens with our
2095 current machine descriptions. */
2096 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2097 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2100 /* A pair of consecutive regs we can still spill does the trick. */
2101 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2102 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2103 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2106 /* A pair of one already spilled and one we can spill does it
2107 provided the one already spilled is not otherwise reserved. */
2108 if (spill_reg_order[i] < 0
2109 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2110 && spill_reg_order[i + 1] >= 0
2111 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2112 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2114 if (spill_reg_order[i + 1] < 0
2115 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2116 && spill_reg_order[i] >= 0
2117 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2118 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2125 /* Count any groups of CLASS that can be formed from the registers recently
2129 count_possible_groups (chain, class)
2130 struct insn_chain *chain;
2136 /* Now find all consecutive groups of spilled registers
2137 and mark each group off against the need for such groups.
2138 But don't count them against ordinary need, yet. */
2140 if (chain->group_size[class] == 0)
2143 CLEAR_HARD_REG_SET (new);
2145 /* Make a mask of all the regs that are spill regs in class I. */
2146 for (i = 0; i < n_spills; i++)
2148 int regno = spill_regs[i];
2150 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2151 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2152 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2153 SET_HARD_REG_BIT (new, regno);
2156 /* Find each consecutive group of them. */
2157 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2158 if (TEST_HARD_REG_BIT (new, i)
2159 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2160 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2162 for (j = 1; j < chain->group_size[class]; j++)
2163 if (! TEST_HARD_REG_BIT (new, i + j))
2166 if (j == chain->group_size[class])
2168 /* We found a group. Mark it off against this class's need for
2169 groups, and against each superclass too. */
2170 register enum reg_class *p;
2172 chain->need.groups[class]--;
2173 p = reg_class_superclasses[class];
2174 while (*p != LIM_REG_CLASSES)
2176 if (chain->group_size [(int) *p] <= chain->group_size [class])
2177 chain->need.groups[(int) *p]--;
2181 /* Don't count these registers again. */
2182 for (j = 0; j < chain->group_size[class]; j++)
2183 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2186 /* Skip to the last reg in this group. When i is incremented above,
2187 it will then point to the first reg of the next possible group. */
2192 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2193 another mode that needs to be reloaded for the same register class CLASS.
2194 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2195 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2197 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2198 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2199 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2200 causes unnecessary failures on machines requiring alignment of register
2201 groups when the two modes are different sizes, because the larger mode has
2202 more strict alignment rules than the smaller mode. */
2205 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2206 enum machine_mode allocate_mode, other_mode;
2207 enum reg_class class;
2210 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2212 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2213 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2214 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2220 /* Handle the failure to find a register to spill.
2221 INSN should be one of the insns which needed this particular spill reg. */
2224 spill_failure (insn)
2227 if (asm_noperands (PATTERN (insn)) >= 0)
2228 error_for_asm (insn, "`asm' needs too many reloads");
2230 fatal_insn ("Unable to find a register to spill.", insn);
2233 /* Add a new register to the tables of available spill-registers.
2234 CHAIN is the insn for which the register will be used; we decrease the
2236 I is the index of this register in potential_reload_regs.
2237 CLASS is the regclass whose need is being satisfied.
2238 NONGROUP is 0 if this register is part of a group.
2239 DUMPFILE is the same as the one that `reload' got. */
2242 new_spill_reg (chain, i, class, nongroup, dumpfile)
2243 struct insn_chain *chain;
2249 register enum reg_class *p;
2250 int regno = potential_reload_regs[i];
2252 if (i >= FIRST_PSEUDO_REGISTER)
2254 spill_failure (chain->insn);
2259 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2261 static const char * const reg_class_names[] = REG_CLASS_NAMES;
2263 if (asm_noperands (PATTERN (chain->insn)) < 0)
2265 /* The error message is still correct - we know only that it wasn't
2266 an asm statement that caused the problem, but one of the global
2267 registers declared by the users might have screwed us. */
2268 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2269 regno, reg_names[regno], reg_class_names[class]);
2270 error ("This may be due to a compiler bug or to impossible asm");
2271 error ("statements or clauses.");
2272 fatal_insn ("This is the instruction:", chain->insn);
2274 error_for_asm (chain->insn, "Invalid `asm' statement:");
2275 error_for_asm (chain->insn,
2276 "fixed or forbidden register %d (%s) was spilled for class %s.",
2277 regno, reg_names[regno], reg_class_names[class]);
2282 /* Make reg REGNO an additional reload reg. */
2284 potential_reload_regs[i] = -1;
2285 spill_regs[n_spills] = regno;
2286 spill_reg_order[regno] = n_spills;
2288 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2289 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2291 /* Clear off the needs we just satisfied. */
2293 chain->need.regs[0][class]--;
2294 p = reg_class_superclasses[class];
2295 while (*p != LIM_REG_CLASSES)
2296 chain->need.regs[0][(int) *p++]--;
2298 if (nongroup && chain->need.regs[1][class] > 0)
2300 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2301 chain->need.regs[1][class]--;
2302 p = reg_class_superclasses[class];
2303 while (*p != LIM_REG_CLASSES)
2304 chain->need.regs[1][(int) *p++]--;
2310 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2311 data that is dead in INSN. */
2314 delete_dead_insn (insn)
2317 rtx prev = prev_real_insn (insn);
2320 /* If the previous insn sets a register that dies in our insn, delete it
2322 if (prev && GET_CODE (PATTERN (prev)) == SET
2323 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2324 && reg_mentioned_p (prev_dest, PATTERN (insn))
2325 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2326 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2327 delete_dead_insn (prev);
2329 PUT_CODE (insn, NOTE);
2330 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2331 NOTE_SOURCE_FILE (insn) = 0;
2334 /* Modify the home of pseudo-reg I.
2335 The new home is present in reg_renumber[I].
2337 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2338 or it may be -1, meaning there is none or it is not relevant.
2339 This is used so that all pseudos spilled from a given hard reg
2340 can share one stack slot. */
2343 alter_reg (i, from_reg)
2347 /* When outputting an inline function, this can happen
2348 for a reg that isn't actually used. */
2349 if (regno_reg_rtx[i] == 0)
2352 /* If the reg got changed to a MEM at rtl-generation time,
2354 if (GET_CODE (regno_reg_rtx[i]) != REG)
2357 /* Modify the reg-rtx to contain the new hard reg
2358 number or else to contain its pseudo reg number. */
2359 REGNO (regno_reg_rtx[i])
2360 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2362 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2363 allocate a stack slot for it. */
2365 if (reg_renumber[i] < 0
2366 && REG_N_REFS (i) > 0
2367 && reg_equiv_constant[i] == 0
2368 && reg_equiv_memory_loc[i] == 0)
2371 int inherent_size = PSEUDO_REGNO_BYTES (i);
2372 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2375 /* Each pseudo reg has an inherent size which comes from its own mode,
2376 and a total size which provides room for paradoxical subregs
2377 which refer to the pseudo reg in wider modes.
2379 We can use a slot already allocated if it provides both
2380 enough inherent space and enough total space.
2381 Otherwise, we allocate a new slot, making sure that it has no less
2382 inherent space, and no less total space, then the previous slot. */
2385 /* No known place to spill from => no slot to reuse. */
2386 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2387 inherent_size == total_size ? 0 : -1);
2388 if (BYTES_BIG_ENDIAN)
2389 /* Cancel the big-endian correction done in assign_stack_local.
2390 Get the address of the beginning of the slot.
2391 This is so we can do a big-endian correction unconditionally
2393 adjust = inherent_size - total_size;
2395 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2397 /* Reuse a stack slot if possible. */
2398 else if (spill_stack_slot[from_reg] != 0
2399 && spill_stack_slot_width[from_reg] >= total_size
2400 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2402 x = spill_stack_slot[from_reg];
2403 /* Allocate a bigger slot. */
2406 /* Compute maximum size needed, both for inherent size
2407 and for total size. */
2408 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2410 if (spill_stack_slot[from_reg])
2412 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2414 mode = GET_MODE (spill_stack_slot[from_reg]);
2415 if (spill_stack_slot_width[from_reg] > total_size)
2416 total_size = spill_stack_slot_width[from_reg];
2418 /* Make a slot with that size. */
2419 x = assign_stack_local (mode, total_size,
2420 inherent_size == total_size ? 0 : -1);
2422 if (BYTES_BIG_ENDIAN)
2424 /* Cancel the big-endian correction done in assign_stack_local.
2425 Get the address of the beginning of the slot.
2426 This is so we can do a big-endian correction unconditionally
2428 adjust = GET_MODE_SIZE (mode) - total_size;
2430 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2433 plus_constant (XEXP (x, 0), adjust));
2435 spill_stack_slot[from_reg] = stack_slot;
2436 spill_stack_slot_width[from_reg] = total_size;
2439 /* On a big endian machine, the "address" of the slot
2440 is the address of the low part that fits its inherent mode. */
2441 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2442 adjust += (total_size - inherent_size);
2444 /* If we have any adjustment to make, or if the stack slot is the
2445 wrong mode, make a new stack slot. */
2446 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2448 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2449 plus_constant (XEXP (x, 0), adjust));
2451 /* If this was shared among registers, must ensure we never
2452 set it readonly since that can cause scheduling
2453 problems. Note we would only have in this adjustment
2454 case in any event, since the code above doesn't set it. */
2457 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2460 /* Save the stack slot for later. */
2461 reg_equiv_memory_loc[i] = x;
2465 /* Mark the slots in regs_ever_live for the hard regs
2466 used by pseudo-reg number REGNO. */
2469 mark_home_live (regno)
2472 register int i, lim;
2473 i = reg_renumber[regno];
2476 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2478 regs_ever_live[i++] = 1;
2481 /* This function handles the tracking of elimination offsets around branches.
2483 X is a piece of RTL being scanned.
2485 INSN is the insn that it came from, if any.
2487 INITIAL_P is non-zero if we are to set the offset to be the initial
2488 offset and zero if we are setting the offset of the label to be the
2492 set_label_offsets (x, insn, initial_p)
2497 enum rtx_code code = GET_CODE (x);
2500 struct elim_table *p;
2505 if (LABEL_REF_NONLOCAL_P (x))
2510 /* ... fall through ... */
2513 /* If we know nothing about this label, set the desired offsets. Note
2514 that this sets the offset at a label to be the offset before a label
2515 if we don't know anything about the label. This is not correct for
2516 the label after a BARRIER, but is the best guess we can make. If
2517 we guessed wrong, we will suppress an elimination that might have
2518 been possible had we been able to guess correctly. */
2520 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2522 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2523 offsets_at[CODE_LABEL_NUMBER (x)][i]
2524 = (initial_p ? reg_eliminate[i].initial_offset
2525 : reg_eliminate[i].offset);
2526 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2529 /* Otherwise, if this is the definition of a label and it is
2530 preceded by a BARRIER, set our offsets to the known offset of
2534 && (tem = prev_nonnote_insn (insn)) != 0
2535 && GET_CODE (tem) == BARRIER)
2536 set_offsets_for_label (insn);
2538 /* If neither of the above cases is true, compare each offset
2539 with those previously recorded and suppress any eliminations
2540 where the offsets disagree. */
2542 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2543 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2544 != (initial_p ? reg_eliminate[i].initial_offset
2545 : reg_eliminate[i].offset))
2546 reg_eliminate[i].can_eliminate = 0;
2551 set_label_offsets (PATTERN (insn), insn, initial_p);
2553 /* ... fall through ... */
2557 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2558 and hence must have all eliminations at their initial offsets. */
2559 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2560 if (REG_NOTE_KIND (tem) == REG_LABEL)
2561 set_label_offsets (XEXP (tem, 0), insn, 1);
2566 /* Each of the labels in the address vector must be at their initial
2567 offsets. We want the first field for ADDR_VEC and the second
2568 field for ADDR_DIFF_VEC. */
2570 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2571 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2576 /* We only care about setting PC. If the source is not RETURN,
2577 IF_THEN_ELSE, or a label, disable any eliminations not at
2578 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2579 isn't one of those possibilities. For branches to a label,
2580 call ourselves recursively.
2582 Note that this can disable elimination unnecessarily when we have
2583 a non-local goto since it will look like a non-constant jump to
2584 someplace in the current function. This isn't a significant
2585 problem since such jumps will normally be when all elimination
2586 pairs are back to their initial offsets. */
2588 if (SET_DEST (x) != pc_rtx)
2591 switch (GET_CODE (SET_SRC (x)))
2598 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2602 tem = XEXP (SET_SRC (x), 1);
2603 if (GET_CODE (tem) == LABEL_REF)
2604 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2605 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2608 tem = XEXP (SET_SRC (x), 2);
2609 if (GET_CODE (tem) == LABEL_REF)
2610 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2611 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2619 /* If we reach here, all eliminations must be at their initial
2620 offset because we are doing a jump to a variable address. */
2621 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2622 if (p->offset != p->initial_offset)
2623 p->can_eliminate = 0;
2631 /* Scan X and replace any eliminable registers (such as fp) with a
2632 replacement (such as sp), plus an offset.
2634 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2635 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2636 MEM, we are allowed to replace a sum of a register and the constant zero
2637 with the register, which we cannot do outside a MEM. In addition, we need
2638 to record the fact that a register is referenced outside a MEM.
2640 If INSN is an insn, it is the insn containing X. If we replace a REG
2641 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2642 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2643 the REG is being modified.
2645 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2646 That's used when we eliminate in expressions stored in notes.
2647 This means, do not set ref_outside_mem even if the reference
2650 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2651 replacements done assuming all offsets are at their initial values. If
2652 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2653 encounter, return the actual location so that find_reloads will do
2654 the proper thing. */
2657 eliminate_regs (x, mem_mode, insn)
2659 enum machine_mode mem_mode;
2662 enum rtx_code code = GET_CODE (x);
2663 struct elim_table *ep;
2670 if (! current_function_decl)
2689 /* This is only for the benefit of the debugging backends, which call
2690 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2691 removed after CSE. */
2692 new = eliminate_regs (XEXP (x, 0), 0, insn);
2693 if (GET_CODE (new) == MEM)
2694 return XEXP (new, 0);
2700 /* First handle the case where we encounter a bare register that
2701 is eliminable. Replace it with a PLUS. */
2702 if (regno < FIRST_PSEUDO_REGISTER)
2704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2706 if (ep->from_rtx == x && ep->can_eliminate)
2707 return plus_constant (ep->to_rtx, ep->previous_offset);
2710 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2711 && reg_equiv_constant[regno]
2712 && ! CONSTANT_P (reg_equiv_constant[regno]))
2713 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2717 /* You might think handling MINUS in a manner similar to PLUS is a
2718 good idea. It is not. It has been tried multiple times and every
2719 time the change has had to have been reverted.
2721 Other parts of reload know a PLUS is special (gen_reload for example)
2722 and require special code to handle code a reloaded PLUS operand.
2724 Also consider backends where the flags register is clobbered by a
2725 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2726 lea instruction comes to mind). If we try to reload a MINUS, we
2727 may kill the flags register that was holding a useful value.
2729 So, please before trying to handle MINUS, consider reload as a
2730 whole instead of this little section as well as the backend issues. */
2732 /* If this is the sum of an eliminable register and a constant, rework
2734 if (GET_CODE (XEXP (x, 0)) == REG
2735 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2736 && CONSTANT_P (XEXP (x, 1)))
2738 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2740 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2742 /* The only time we want to replace a PLUS with a REG (this
2743 occurs when the constant operand of the PLUS is the negative
2744 of the offset) is when we are inside a MEM. We won't want
2745 to do so at other times because that would change the
2746 structure of the insn in a way that reload can't handle.
2747 We special-case the commonest situation in
2748 eliminate_regs_in_insn, so just replace a PLUS with a
2749 PLUS here, unless inside a MEM. */
2750 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2751 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2754 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2755 plus_constant (XEXP (x, 1),
2756 ep->previous_offset));
2759 /* If the register is not eliminable, we are done since the other
2760 operand is a constant. */
2764 /* If this is part of an address, we want to bring any constant to the
2765 outermost PLUS. We will do this by doing register replacement in
2766 our operands and seeing if a constant shows up in one of them.
2768 Note that there is no risk of modifying the structure of the insn,
2769 since we only get called for its operands, thus we are either
2770 modifying the address inside a MEM, or something like an address
2771 operand of a load-address insn. */
2774 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2775 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2777 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2779 /* If one side is a PLUS and the other side is a pseudo that
2780 didn't get a hard register but has a reg_equiv_constant,
2781 we must replace the constant here since it may no longer
2782 be in the position of any operand. */
2783 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2784 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2785 && reg_renumber[REGNO (new1)] < 0
2786 && reg_equiv_constant != 0
2787 && reg_equiv_constant[REGNO (new1)] != 0)
2788 new1 = reg_equiv_constant[REGNO (new1)];
2789 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2790 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2791 && reg_renumber[REGNO (new0)] < 0
2792 && reg_equiv_constant[REGNO (new0)] != 0)
2793 new0 = reg_equiv_constant[REGNO (new0)];
2795 new = form_sum (new0, new1);
2797 /* As above, if we are not inside a MEM we do not want to
2798 turn a PLUS into something else. We might try to do so here
2799 for an addition of 0 if we aren't optimizing. */
2800 if (! mem_mode && GET_CODE (new) != PLUS)
2801 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2809 /* If this is the product of an eliminable register and a
2810 constant, apply the distribute law and move the constant out
2811 so that we have (plus (mult ..) ..). This is needed in order
2812 to keep load-address insns valid. This case is pathological.
2813 We ignore the possibility of overflow here. */
2814 if (GET_CODE (XEXP (x, 0)) == REG
2815 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2816 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2817 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2819 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2822 /* Refs inside notes don't count for this purpose. */
2823 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2824 || GET_CODE (insn) == INSN_LIST)))
2825 ep->ref_outside_mem = 1;
2828 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2829 ep->previous_offset * INTVAL (XEXP (x, 1)));
2832 /* ... fall through ... */
2836 /* See comments before PLUS about handling MINUS. */
2838 case DIV: case UDIV:
2839 case MOD: case UMOD:
2840 case AND: case IOR: case XOR:
2841 case ROTATERT: case ROTATE:
2842 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2844 case GE: case GT: case GEU: case GTU:
2845 case LE: case LT: case LEU: case LTU:
2847 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2849 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2851 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2852 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2857 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2860 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2861 if (new != XEXP (x, 0))
2863 /* If this is a REG_DEAD note, it is not valid anymore.
2864 Using the eliminated version could result in creating a
2865 REG_DEAD note for the stack or frame pointer. */
2866 if (GET_MODE (x) == REG_DEAD)
2868 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2871 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2875 /* ... fall through ... */
2878 /* Now do eliminations in the rest of the chain. If this was
2879 an EXPR_LIST, this might result in allocating more memory than is
2880 strictly needed, but it simplifies the code. */
2883 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2884 if (new != XEXP (x, 1))
2885 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2893 case STRICT_LOW_PART:
2895 case SIGN_EXTEND: case ZERO_EXTEND:
2896 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2897 case FLOAT: case FIX:
2898 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2902 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2903 if (new != XEXP (x, 0))
2904 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2908 /* Similar to above processing, but preserve SUBREG_WORD.
2909 Convert (subreg (mem)) to (mem) if not paradoxical.
2910 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2911 pseudo didn't get a hard reg, we must replace this with the
2912 eliminated version of the memory location because push_reloads
2913 may do the replacement in certain circumstances. */
2914 if (GET_CODE (SUBREG_REG (x)) == REG
2915 && (GET_MODE_SIZE (GET_MODE (x))
2916 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2917 && reg_equiv_memory_loc != 0
2918 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2920 new = SUBREG_REG (x);
2923 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2925 if (new != XEXP (x, 0))
2927 int x_size = GET_MODE_SIZE (GET_MODE (x));
2928 int new_size = GET_MODE_SIZE (GET_MODE (new));
2930 if (GET_CODE (new) == MEM
2931 && ((x_size < new_size
2932 #ifdef WORD_REGISTER_OPERATIONS
2933 /* On these machines, combine can create rtl of the form
2934 (set (subreg:m1 (reg:m2 R) 0) ...)
2935 where m1 < m2, and expects something interesting to
2936 happen to the entire word. Moreover, it will use the
2937 (reg:m2 R) later, expecting all bits to be preserved.
2938 So if the number of words is the same, preserve the
2939 subreg so that push_reloads can see it. */
2940 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2943 || (x_size == new_size))
2946 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2947 enum machine_mode mode = GET_MODE (x);
2949 if (BYTES_BIG_ENDIAN)
2950 offset += (MIN (UNITS_PER_WORD,
2951 GET_MODE_SIZE (GET_MODE (new)))
2952 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2954 PUT_MODE (new, mode);
2955 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2959 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2965 /* This is only for the benefit of the debugging backends, which call
2966 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2967 removed after CSE. */
2968 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2969 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2971 /* Our only special processing is to pass the mode of the MEM to our
2972 recursive call and copy the flags. While we are here, handle this
2973 case more efficiently. */
2974 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2975 if (new != XEXP (x, 0))
2977 new = gen_rtx_MEM (GET_MODE (x), new);
2978 new->volatil = x->volatil;
2979 new->unchanging = x->unchanging;
2980 new->in_struct = x->in_struct;
2996 /* Process each of our operands recursively. If any have changed, make a
2998 fmt = GET_RTX_FORMAT (code);
2999 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3003 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3004 if (new != XEXP (x, i) && ! copied)
3006 rtx new_x = rtx_alloc (code);
3007 bcopy ((char *) x, (char *) new_x,
3008 (sizeof (*new_x) - sizeof (new_x->fld)
3009 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3015 else if (*fmt == 'E')
3018 for (j = 0; j < XVECLEN (x, i); j++)
3020 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3021 if (new != XVECEXP (x, i, j) && ! copied_vec)
3023 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3027 rtx new_x = rtx_alloc (code);
3028 bcopy ((char *) x, (char *) new_x,
3029 (sizeof (*new_x) - sizeof (new_x->fld)
3030 + (sizeof (new_x->fld[0])
3031 * GET_RTX_LENGTH (code))));
3035 XVEC (x, i) = new_v;
3038 XVECEXP (x, i, j) = new;
3046 /* Scan rtx X for modifications of elimination target registers. Update
3047 the table of eliminables to reflect the changed state. MEM_MODE is
3048 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
3051 elimination_effects (x, mem_mode)
3053 enum machine_mode mem_mode;
3056 enum rtx_code code = GET_CODE (x);
3057 struct elim_table *ep;
3083 /* First handle the case where we encounter a bare register that
3084 is eliminable. Replace it with a PLUS. */
3085 if (regno < FIRST_PSEUDO_REGISTER)
3087 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3089 if (ep->from_rtx == x && ep->can_eliminate)
3092 ep->ref_outside_mem = 1;
3097 else if (reg_renumber[regno] < 0 && reg_equiv_constant
3098 && reg_equiv_constant[regno]
3099 && ! CONSTANT_P (reg_equiv_constant[regno]))
3100 elimination_effects (reg_equiv_constant[regno], mem_mode);
3107 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3108 if (ep->to_rtx == XEXP (x, 0))
3110 int size = GET_MODE_SIZE (mem_mode);
3112 /* If more bytes than MEM_MODE are pushed, account for them. */
3113 #ifdef PUSH_ROUNDING
3114 if (ep->to_rtx == stack_pointer_rtx)
3115 size = PUSH_ROUNDING (size);
3117 if (code == PRE_DEC || code == POST_DEC)
3123 /* Fall through to generic unary operation case. */
3124 case STRICT_LOW_PART:
3126 case SIGN_EXTEND: case ZERO_EXTEND:
3127 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3128 case FLOAT: case FIX:
3129 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3133 elimination_effects (XEXP (x, 0), mem_mode);
3137 if (GET_CODE (SUBREG_REG (x)) == REG
3138 && (GET_MODE_SIZE (GET_MODE (x))
3139 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3140 && reg_equiv_memory_loc != 0
3141 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3144 elimination_effects (SUBREG_REG (x), mem_mode);
3148 /* If using a register that is the source of an eliminate we still
3149 think can be performed, note it cannot be performed since we don't
3150 know how this register is used. */
3151 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3152 if (ep->from_rtx == XEXP (x, 0))
3153 ep->can_eliminate = 0;
3155 elimination_effects (XEXP (x, 0), mem_mode);
3159 /* If clobbering a register that is the replacement register for an
3160 elimination we still think can be performed, note that it cannot
3161 be performed. Otherwise, we need not be concerned about it. */
3162 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3163 if (ep->to_rtx == XEXP (x, 0))
3164 ep->can_eliminate = 0;
3166 elimination_effects (XEXP (x, 0), mem_mode);
3170 /* Check for setting a register that we know about. */
3171 if (GET_CODE (SET_DEST (x)) == REG)
3173 /* See if this is setting the replacement register for an
3176 If DEST is the hard frame pointer, we do nothing because we
3177 assume that all assignments to the frame pointer are for
3178 non-local gotos and are being done at a time when they are valid
3179 and do not disturb anything else. Some machines want to
3180 eliminate a fake argument pointer (or even a fake frame pointer)
3181 with either the real frame or the stack pointer. Assignments to
3182 the hard frame pointer must not prevent this elimination. */
3184 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3186 if (ep->to_rtx == SET_DEST (x)
3187 && SET_DEST (x) != hard_frame_pointer_rtx)
3189 /* If it is being incremented, adjust the offset. Otherwise,
3190 this elimination can't be done. */
3191 rtx src = SET_SRC (x);
3193 if (GET_CODE (src) == PLUS
3194 && XEXP (src, 0) == SET_DEST (x)
3195 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3196 ep->offset -= INTVAL (XEXP (src, 1));
3198 ep->can_eliminate = 0;
3202 elimination_effects (SET_DEST (x), 0);
3203 elimination_effects (SET_SRC (x), 0);
3207 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3210 /* Our only special processing is to pass the mode of the MEM to our
3212 elimination_effects (XEXP (x, 0), GET_MODE (x));
3219 fmt = GET_RTX_FORMAT (code);
3220 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3223 elimination_effects (XEXP (x, i), mem_mode);
3224 else if (*fmt == 'E')
3225 for (j = 0; j < XVECLEN (x, i); j++)
3226 elimination_effects (XVECEXP (x, i, j), mem_mode);
3230 /* Descend through rtx X and verify that no references to eliminable registers
3231 remain. If any do remain, mark the involved register as not
3234 check_eliminable_occurrences (x)
3244 code = GET_CODE (x);
3246 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3248 struct elim_table *ep;
3250 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3251 if (ep->from_rtx == x && ep->can_eliminate)
3252 ep->can_eliminate = 0;
3256 fmt = GET_RTX_FORMAT (code);
3257 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3260 check_eliminable_occurrences (XEXP (x, i));
3261 else if (*fmt == 'E')
3264 for (j = 0; j < XVECLEN (x, i); j++)
3265 check_eliminable_occurrences (XVECEXP (x, i, j));
3270 /* Scan INSN and eliminate all eliminable registers in it.
3272 If REPLACE is nonzero, do the replacement destructively. Also
3273 delete the insn as dead it if it is setting an eliminable register.
3275 If REPLACE is zero, do all our allocations in reload_obstack.
3277 If no eliminations were done and this insn doesn't require any elimination
3278 processing (these are not identical conditions: it might be updating sp,
3279 but not referencing fp; this needs to be seen during reload_as_needed so
3280 that the offset between fp and sp can be taken into consideration), zero
3281 is returned. Otherwise, 1 is returned. */
3284 eliminate_regs_in_insn (insn, replace)
3288 int icode = recog_memoized (insn);
3289 rtx old_body = PATTERN (insn);
3290 int insn_is_asm = asm_noperands (old_body) >= 0;
3291 rtx old_set = single_set (insn);
3295 rtx substed_operand[MAX_RECOG_OPERANDS];
3296 rtx orig_operand[MAX_RECOG_OPERANDS];
3297 struct elim_table *ep;
3299 if (! insn_is_asm && icode < 0)
3301 if (GET_CODE (PATTERN (insn)) == USE
3302 || GET_CODE (PATTERN (insn)) == CLOBBER
3303 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3304 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3305 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
3311 push_obstacks (&reload_obstack, &reload_obstack);
3313 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3314 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3316 /* Check for setting an eliminable register. */
3317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3318 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3320 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3321 /* If this is setting the frame pointer register to the
3322 hardware frame pointer register and this is an elimination
3323 that will be done (tested above), this insn is really
3324 adjusting the frame pointer downward to compensate for
3325 the adjustment done before a nonlocal goto. */
3326 if (ep->from == FRAME_POINTER_REGNUM
3327 && ep->to == HARD_FRAME_POINTER_REGNUM)
3329 rtx src = SET_SRC (old_set);
3330 int offset = 0, ok = 0;
3331 rtx prev_insn, prev_set;
3333 if (src == ep->to_rtx)
3335 else if (GET_CODE (src) == PLUS
3336 && GET_CODE (XEXP (src, 0)) == CONST_INT
3337 && XEXP (src, 1) == ep->to_rtx)
3338 offset = INTVAL (XEXP (src, 0)), ok = 1;
3339 else if (GET_CODE (src) == PLUS
3340 && GET_CODE (XEXP (src, 1)) == CONST_INT
3341 && XEXP (src, 0) == ep->to_rtx)
3342 offset = INTVAL (XEXP (src, 1)), ok = 1;
3343 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3344 && (prev_set = single_set (prev_insn)) != 0
3345 && rtx_equal_p (SET_DEST (prev_set), src))
3347 src = SET_SRC (prev_set);
3348 if (src == ep->to_rtx)
3350 else if (GET_CODE (src) == PLUS
3351 && GET_CODE (XEXP (src, 0)) == CONST_INT
3352 && XEXP (src, 1) == ep->to_rtx)
3353 offset = INTVAL (XEXP (src, 0)), ok = 1;
3354 else if (GET_CODE (src) == PLUS
3355 && GET_CODE (XEXP (src, 1)) == CONST_INT
3356 && XEXP (src, 0) == ep->to_rtx)
3357 offset = INTVAL (XEXP (src, 1)), ok = 1;
3365 = plus_constant (ep->to_rtx, offset - ep->offset);
3367 /* First see if this insn remains valid when we
3368 make the change. If not, keep the INSN_CODE
3369 the same and let reload fit it up. */
3370 validate_change (insn, &SET_SRC (old_set), src, 1);
3371 validate_change (insn, &SET_DEST (old_set),
3373 if (! apply_change_group ())
3375 SET_SRC (old_set) = src;
3376 SET_DEST (old_set) = ep->to_rtx;
3386 /* In this case this insn isn't serving a useful purpose. We
3387 will delete it in reload_as_needed once we know that this
3388 elimination is, in fact, being done.
3390 If REPLACE isn't set, we can't delete this insn, but needn't
3391 process it since it won't be used unless something changes. */
3394 delete_dead_insn (insn);
3401 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3402 in the insn is the negative of the offset in FROM. Substitute
3403 (set (reg) (reg to)) for the insn and change its code.
3405 We have to do this here, rather than in eliminate_regs, so that we can
3406 change the insn code. */
3408 if (GET_CODE (SET_SRC (old_set)) == PLUS
3409 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3410 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3411 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3413 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3414 && ep->can_eliminate)
3416 /* We must stop at the first elimination that will be used.
3417 If this one would replace the PLUS with a REG, do it
3418 now. Otherwise, quit the loop and let eliminate_regs
3419 do its normal replacement. */
3420 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3422 /* We assume here that we don't need a PARALLEL of
3423 any CLOBBERs for this assignment. There's not
3424 much we can do if we do need it. */
3425 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3428 INSN_CODE (insn) = -1;
3437 /* Determine the effects of this insn on elimination offsets. */
3438 elimination_effects (old_body, 0);
3440 /* Eliminate all eliminable registers occurring in operands that
3441 can be handled by reload. */
3442 extract_insn (insn);
3444 for (i = 0; i < recog_data.n_operands; i++)
3446 orig_operand[i] = recog_data.operand[i];
3447 substed_operand[i] = recog_data.operand[i];
3449 /* For an asm statement, every operand is eliminable. */
3450 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3452 /* Check for setting a register that we know about. */
3453 if (recog_data.operand_type[i] != OP_IN
3454 && GET_CODE (orig_operand[i]) == REG)
3456 /* If we are assigning to a register that can be eliminated, it
3457 must be as part of a PARALLEL, since the code above handles
3458 single SETs. We must indicate that we can no longer
3459 eliminate this reg. */
3460 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3462 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3463 ep->can_eliminate = 0;
3466 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3467 replace ? insn : NULL_RTX);
3468 if (substed_operand[i] != orig_operand[i])
3469 val = any_changes = 1;
3470 /* Terminate the search in check_eliminable_occurrences at
3472 *recog_data.operand_loc[i] = 0;
3474 /* If an output operand changed from a REG to a MEM and INSN is an
3475 insn, write a CLOBBER insn. */
3476 if (recog_data.operand_type[i] != OP_IN
3477 && GET_CODE (orig_operand[i]) == REG
3478 && GET_CODE (substed_operand[i]) == MEM
3480 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3485 for (i = 0; i < recog_data.n_dups; i++)
3486 *recog_data.dup_loc[i]
3487 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3489 /* If any eliminable remain, they aren't eliminable anymore. */
3490 check_eliminable_occurrences (old_body);
3492 /* Substitute the operands; the new values are in the substed_operand
3494 for (i = 0; i < recog_data.n_operands; i++)
3495 *recog_data.operand_loc[i] = substed_operand[i];
3496 for (i = 0; i < recog_data.n_dups; i++)
3497 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3499 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3500 re-recognize the insn. We do this in case we had a simple addition
3501 but now can do this as a load-address. This saves an insn in this
3503 If re-recognition fails, the old insn code number will still be used,
3504 and some register operands may have changed into PLUS expressions.
3505 These will be handled by find_reloads by loading them into a register
3510 /* If we aren't replacing things permanently and we changed something,
3511 make another copy to ensure that all the RTL is new. Otherwise
3512 things can go wrong if find_reload swaps commutative operands
3513 and one is inside RTL that has been copied while the other is not. */
3514 new_body = old_body;
3516 new_body = copy_insn (old_body);
3517 PATTERN (insn) = new_body;
3519 /* If we had a move insn but now we don't, rerecognize it. This will
3520 cause spurious re-recognition if the old move had a PARALLEL since
3521 the new one still will, but we can't call single_set without
3522 having put NEW_BODY into the insn and the re-recognition won't
3523 hurt in this rare case. */
3524 /* ??? Why this huge if statement - why don't we just rerecognize the
3528 && ((GET_CODE (SET_SRC (old_set)) == REG
3529 && (GET_CODE (new_body) != SET
3530 || GET_CODE (SET_SRC (new_body)) != REG))
3531 /* If this was a load from or store to memory, compare
3532 the MEM in recog_data.operand to the one in the insn.
3533 If they are not equal, then rerecognize the insn. */
3535 && ((GET_CODE (SET_SRC (old_set)) == MEM
3536 && SET_SRC (old_set) != recog_data.operand[1])
3537 || (GET_CODE (SET_DEST (old_set)) == MEM
3538 && SET_DEST (old_set) != recog_data.operand[0])))
3539 /* If this was an add insn before, rerecognize. */
3540 || GET_CODE (SET_SRC (old_set)) == PLUS))
3542 int new_icode = recog (PATTERN (insn), insn, 0);
3544 INSN_CODE (insn) = icode;
3548 /* Restore the old body. If there were any changes to it, we made a copy
3549 of it while the changes were still in place, so we'll correctly return
3550 a modified insn below. */
3553 /* Restore the old body. */
3554 for (i = 0; i < recog_data.n_operands; i++)
3555 *recog_data.operand_loc[i] = orig_operand[i];
3556 for (i = 0; i < recog_data.n_dups; i++)
3557 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3560 /* Update all elimination pairs to reflect the status after the current
3561 insn. The changes we make were determined by the earlier call to
3562 elimination_effects.
3564 We also detect a cases where register elimination cannot be done,
3565 namely, if a register would be both changed and referenced outside a MEM
3566 in the resulting insn since such an insn is often undefined and, even if
3567 not, we cannot know what meaning will be given to it. Note that it is
3568 valid to have a register used in an address in an insn that changes it
3569 (presumably with a pre- or post-increment or decrement).
3571 If anything changes, return nonzero. */
3573 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3575 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3576 ep->can_eliminate = 0;
3578 ep->ref_outside_mem = 0;
3580 if (ep->previous_offset != ep->offset)
3585 /* If we changed something, perform elimination in REG_NOTES. This is
3586 needed even when REPLACE is zero because a REG_DEAD note might refer
3587 to a register that we eliminate and could cause a different number
3588 of spill registers to be needed in the final reload pass than in
3590 if (val && REG_NOTES (insn) != 0)
3591 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3599 /* Loop through all elimination pairs.
3600 Recalculate the number not at initial offset.
3602 Compute the maximum offset (minimum offset if the stack does not
3603 grow downward) for each elimination pair. */
3606 update_eliminable_offsets ()
3608 struct elim_table *ep;
3610 num_not_at_initial_offset = 0;
3611 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3613 ep->previous_offset = ep->offset;
3614 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3615 num_not_at_initial_offset++;
3619 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3620 replacement we currently believe is valid, mark it as not eliminable if X
3621 modifies DEST in any way other than by adding a constant integer to it.
3623 If DEST is the frame pointer, we do nothing because we assume that
3624 all assignments to the hard frame pointer are nonlocal gotos and are being
3625 done at a time when they are valid and do not disturb anything else.
3626 Some machines want to eliminate a fake argument pointer with either the
3627 frame or stack pointer. Assignments to the hard frame pointer must not
3628 prevent this elimination.
3630 Called via note_stores from reload before starting its passes to scan
3631 the insns of the function. */
3634 mark_not_eliminable (dest, x, data)
3637 void *data ATTRIBUTE_UNUSED;
3639 register unsigned int i;
3641 /* A SUBREG of a hard register here is just changing its mode. We should
3642 not see a SUBREG of an eliminable hard register, but check just in
3644 if (GET_CODE (dest) == SUBREG)
3645 dest = SUBREG_REG (dest);
3647 if (dest == hard_frame_pointer_rtx)
3650 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3651 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3652 && (GET_CODE (x) != SET
3653 || GET_CODE (SET_SRC (x)) != PLUS
3654 || XEXP (SET_SRC (x), 0) != dest
3655 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3657 reg_eliminate[i].can_eliminate_previous
3658 = reg_eliminate[i].can_eliminate = 0;
3663 /* Verify that the initial elimination offsets did not change since the
3664 last call to set_initial_elim_offsets. This is used to catch cases
3665 where something illegal happened during reload_as_needed that could
3666 cause incorrect code to be generated if we did not check for it. */
3668 verify_initial_elim_offsets ()
3672 #ifdef ELIMINABLE_REGS
3673 struct elim_table *ep;
3675 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3677 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3678 if (t != ep->initial_offset)
3682 INITIAL_FRAME_POINTER_OFFSET (t);
3683 if (t != reg_eliminate[0].initial_offset)
3688 /* Reset all offsets on eliminable registers to their initial values. */
3690 set_initial_elim_offsets ()
3692 struct elim_table *ep = reg_eliminate;
3694 #ifdef ELIMINABLE_REGS
3695 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3697 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3698 ep->previous_offset = ep->offset = ep->initial_offset;
3701 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3702 ep->previous_offset = ep->offset = ep->initial_offset;
3705 num_not_at_initial_offset = 0;
3708 /* Initialize the known label offsets.
3709 Set a known offset for each forced label to be at the initial offset
3710 of each elimination. We do this because we assume that all
3711 computed jumps occur from a location where each elimination is
3712 at its initial offset.
3713 For all other labels, show that we don't know the offsets. */
3716 set_initial_label_offsets ()
3719 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3721 for (x = forced_labels; x; x = XEXP (x, 1))
3723 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3726 /* Set all elimination offsets to the known values for the code label given
3729 set_offsets_for_label (insn)
3733 int label_nr = CODE_LABEL_NUMBER (insn);
3734 struct elim_table *ep;
3736 num_not_at_initial_offset = 0;
3737 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3739 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3740 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3741 num_not_at_initial_offset++;
3745 /* See if anything that happened changes which eliminations are valid.
3746 For example, on the Sparc, whether or not the frame pointer can
3747 be eliminated can depend on what registers have been used. We need
3748 not check some conditions again (such as flag_omit_frame_pointer)
3749 since they can't have changed. */
3752 update_eliminables (pset)
3755 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3756 int previous_frame_pointer_needed = frame_pointer_needed;
3758 struct elim_table *ep;
3760 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3761 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3762 #ifdef ELIMINABLE_REGS
3763 || ! CAN_ELIMINATE (ep->from, ep->to)
3766 ep->can_eliminate = 0;
3768 /* Look for the case where we have discovered that we can't replace
3769 register A with register B and that means that we will now be
3770 trying to replace register A with register C. This means we can
3771 no longer replace register C with register B and we need to disable
3772 such an elimination, if it exists. This occurs often with A == ap,
3773 B == sp, and C == fp. */
3775 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3777 struct elim_table *op;
3778 register int new_to = -1;
3780 if (! ep->can_eliminate && ep->can_eliminate_previous)
3782 /* Find the current elimination for ep->from, if there is a
3784 for (op = reg_eliminate;
3785 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3786 if (op->from == ep->from && op->can_eliminate)
3792 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3794 for (op = reg_eliminate;
3795 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3796 if (op->from == new_to && op->to == ep->to)
3797 op->can_eliminate = 0;
3801 /* See if any registers that we thought we could eliminate the previous
3802 time are no longer eliminable. If so, something has changed and we
3803 must spill the register. Also, recompute the number of eliminable
3804 registers and see if the frame pointer is needed; it is if there is
3805 no elimination of the frame pointer that we can perform. */
3807 frame_pointer_needed = 1;
3808 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3810 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3811 && ep->to != HARD_FRAME_POINTER_REGNUM)
3812 frame_pointer_needed = 0;
3814 if (! ep->can_eliminate && ep->can_eliminate_previous)
3816 ep->can_eliminate_previous = 0;
3817 SET_HARD_REG_BIT (*pset, ep->from);
3822 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3823 /* If we didn't need a frame pointer last time, but we do now, spill
3824 the hard frame pointer. */
3825 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3826 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3830 /* Initialize the table of registers to eliminate. */
3834 struct elim_table *ep;
3835 #ifdef ELIMINABLE_REGS
3836 struct elim_table_1 *ep1;
3840 reg_eliminate = (struct elim_table *)
3841 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3843 /* Does this function require a frame pointer? */
3845 frame_pointer_needed = (! flag_omit_frame_pointer
3846 #ifdef EXIT_IGNORE_STACK
3847 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3848 and restore sp for alloca. So we can't eliminate
3849 the frame pointer in that case. At some point,
3850 we should improve this by emitting the
3851 sp-adjusting insns for this case. */
3852 || (current_function_calls_alloca
3853 && EXIT_IGNORE_STACK)
3855 || FRAME_POINTER_REQUIRED);
3859 #ifdef ELIMINABLE_REGS
3860 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3861 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3863 ep->from = ep1->from;
3865 ep->can_eliminate = ep->can_eliminate_previous
3866 = (CAN_ELIMINATE (ep->from, ep->to)
3867 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3870 reg_eliminate[0].from = reg_eliminate_1[0].from;
3871 reg_eliminate[0].to = reg_eliminate_1[0].to;
3872 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3873 = ! frame_pointer_needed;
3876 /* Count the number of eliminable registers and build the FROM and TO
3877 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3878 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3879 We depend on this. */
3880 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3882 num_eliminable += ep->can_eliminate;
3883 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3884 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3888 /* Kick all pseudos out of hard register REGNO.
3889 If DUMPFILE is nonzero, log actions taken on that file.
3891 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3892 because we found we can't eliminate some register. In the case, no pseudos
3893 are allowed to be in the register, even if they are only in a block that
3894 doesn't require spill registers, unlike the case when we are spilling this
3895 hard reg to produce another spill register.
3897 Return nonzero if any pseudos needed to be kicked out. */
3900 spill_hard_reg (regno, dumpfile, cant_eliminate)
3902 FILE *dumpfile ATTRIBUTE_UNUSED;
3909 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3910 regs_ever_live[regno] = 1;
3913 /* Spill every pseudo reg that was allocated to this reg
3914 or to something that overlaps this reg. */
3916 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3917 if (reg_renumber[i] >= 0
3918 && reg_renumber[i] <= regno
3920 + HARD_REGNO_NREGS (reg_renumber[i],
3921 PSEUDO_REGNO_MODE (i))
3923 SET_REGNO_REG_SET (spilled_pseudos, i);
3926 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3927 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3929 ior_hard_reg_set (set1, set2)
3930 HARD_REG_SET *set1, *set2;
3932 IOR_HARD_REG_SET (*set1, *set2);
3935 /* After find_reload_regs has been run for all insn that need reloads,
3936 and/or spill_hard_regs was called, this function is used to actually
3937 spill pseudo registers and try to reallocate them. It also sets up the
3938 spill_regs array for use by choose_reload_regs. */
3941 finish_spills (global, dumpfile)
3945 struct insn_chain *chain;
3946 int something_changed = 0;
3949 /* Build the spill_regs array for the function. */
3950 /* If there are some registers still to eliminate and one of the spill regs
3951 wasn't ever used before, additional stack space may have to be
3952 allocated to store this register. Thus, we may have changed the offset
3953 between the stack and frame pointers, so mark that something has changed.
3955 One might think that we need only set VAL to 1 if this is a call-used
3956 register. However, the set of registers that must be saved by the
3957 prologue is not identical to the call-used set. For example, the
3958 register used by the call insn for the return PC is a call-used register,
3959 but must be saved by the prologue. */
3962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3963 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3965 spill_reg_order[i] = n_spills;
3966 spill_regs[n_spills++] = i;
3967 if (num_eliminable && ! regs_ever_live[i])
3968 something_changed = 1;
3969 regs_ever_live[i] = 1;
3972 spill_reg_order[i] = -1;
3974 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3975 if (REGNO_REG_SET_P (spilled_pseudos, i))
3977 /* Record the current hard register the pseudo is allocated to in
3978 pseudo_previous_regs so we avoid reallocating it to the same
3979 hard reg in a later pass. */
3980 if (reg_renumber[i] < 0)
3982 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3983 /* Mark it as no longer having a hard register home. */
3984 reg_renumber[i] = -1;
3985 /* We will need to scan everything again. */
3986 something_changed = 1;
3989 /* Retry global register allocation if possible. */
3992 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3993 /* For every insn that needs reloads, set the registers used as spill
3994 regs in pseudo_forbidden_regs for every pseudo live across the
3996 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3998 EXECUTE_IF_SET_IN_REG_SET
3999 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
4001 ior_hard_reg_set (pseudo_forbidden_regs + i,
4002 &chain->used_spill_regs);
4004 EXECUTE_IF_SET_IN_REG_SET
4005 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
4007 ior_hard_reg_set (pseudo_forbidden_regs + i,
4008 &chain->used_spill_regs);
4012 /* Retry allocating the spilled pseudos. For each reg, merge the
4013 various reg sets that indicate which hard regs can't be used,
4014 and call retry_global_alloc.
4015 We change spill_pseudos here to only contain pseudos that did not
4016 get a new hard register. */
4017 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4018 if (reg_old_renumber[i] != reg_renumber[i])
4020 HARD_REG_SET forbidden;
4021 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
4022 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
4023 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
4024 retry_global_alloc (i, forbidden);
4025 if (reg_renumber[i] >= 0)
4026 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
4030 /* Fix up the register information in the insn chain.
4031 This involves deleting those of the spilled pseudos which did not get
4032 a new hard register home from the live_{before,after} sets. */
4033 for (chain = reload_insn_chain; chain; chain = chain->next)
4035 HARD_REG_SET used_by_pseudos;
4036 HARD_REG_SET used_by_pseudos2;
4038 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
4039 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
4041 /* Mark any unallocated hard regs as available for spills. That
4042 makes inheritance work somewhat better. */
4043 if (chain->need_reload)
4045 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
4046 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
4047 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4049 /* Save the old value for the sanity test below. */
4050 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
4052 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
4053 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
4054 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4055 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4057 /* Make sure we only enlarge the set. */
4058 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
4064 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4065 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4067 int regno = reg_renumber[i];
4068 if (reg_old_renumber[i] == regno)
4071 alter_reg (i, reg_old_renumber[i]);
4072 reg_old_renumber[i] = regno;
4076 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
4078 fprintf (dumpfile, " Register %d now in %d.\n\n",
4079 i, reg_renumber[i]);
4083 return something_changed;
4086 /* Find all paradoxical subregs within X and update reg_max_ref_width.
4087 Also mark any hard registers used to store user variables as
4088 forbidden from being used for spill registers. */
4091 scan_paradoxical_subregs (x)
4095 register const char *fmt;
4096 register enum rtx_code code = GET_CODE (x);
4102 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4103 && REG_USERVAR_P (x))
4104 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4120 if (GET_CODE (SUBREG_REG (x)) == REG
4121 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4122 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4123 = GET_MODE_SIZE (GET_MODE (x));
4130 fmt = GET_RTX_FORMAT (code);
4131 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4134 scan_paradoxical_subregs (XEXP (x, i));
4135 else if (fmt[i] == 'E')
4138 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4139 scan_paradoxical_subregs (XVECEXP (x, i, j));
4145 hard_reg_use_compare (p1p, p2p)
4149 const struct hard_reg_n_uses *p1 = (const struct hard_reg_n_uses *)p1p;
4150 const struct hard_reg_n_uses *p2 = (const struct hard_reg_n_uses *)p2p;
4151 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4152 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4154 return p1->regno - p2->regno;
4159 if (p1->uses > p2->uses)
4161 if (p1->uses < p2->uses)
4163 /* If regs are equally good, sort by regno,
4164 so that the results of qsort leave nothing to chance. */
4165 return p1->regno - p2->regno;
4168 /* Used for communication between order_regs_for_reload and count_pseudo.
4169 Used to avoid counting one pseudo twice. */
4170 static regset pseudos_counted;
4172 /* Update the costs in N_USES, considering that pseudo REG is live. */
4174 count_pseudo (n_uses, reg)
4175 struct hard_reg_n_uses *n_uses;
4178 int r = reg_renumber[reg];
4181 if (REGNO_REG_SET_P (pseudos_counted, reg))
4183 SET_REGNO_REG_SET (pseudos_counted, reg);
4188 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4190 n_uses[r++].uses += REG_N_REFS (reg);
4192 /* Choose the order to consider regs for use as reload registers
4193 based on how much trouble would be caused by spilling one.
4194 Store them in order of decreasing preference in potential_reload_regs. */
4197 order_regs_for_reload (chain)
4198 struct insn_chain *chain;
4202 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4204 pseudos_counted = ALLOCA_REG_SET ();
4206 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4208 /* Count number of uses of each hard reg by pseudo regs allocated to it
4209 and then order them by decreasing use. */
4211 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4213 hard_reg_n_uses[i].regno = i;
4214 hard_reg_n_uses[i].uses = 0;
4216 /* Test the various reasons why we can't use a register for
4217 spilling in this insn. */
4219 || REGNO_REG_SET_P (chain->live_before, i)
4220 || REGNO_REG_SET_P (chain->live_after, i))
4221 SET_HARD_REG_BIT (bad_spill_regs, i);
4224 /* Now compute hard_reg_n_uses. */
4225 CLEAR_REG_SET (pseudos_counted);
4227 EXECUTE_IF_SET_IN_REG_SET
4228 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
4230 count_pseudo (hard_reg_n_uses, i);
4232 EXECUTE_IF_SET_IN_REG_SET
4233 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
4235 count_pseudo (hard_reg_n_uses, i);
4238 FREE_REG_SET (pseudos_counted);
4240 /* Prefer registers not so far used, for use in temporary loading.
4241 Among them, if REG_ALLOC_ORDER is defined, use that order.
4242 Otherwise, prefer registers not preserved by calls. */
4244 #ifdef REG_ALLOC_ORDER
4245 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4247 int regno = reg_alloc_order[i];
4249 if (hard_reg_n_uses[regno].uses == 0
4250 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4251 potential_reload_regs[o++] = regno;
4254 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4256 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4257 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4258 potential_reload_regs[o++] = i;
4260 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4262 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4263 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4264 potential_reload_regs[o++] = i;
4268 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4269 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4271 /* Now add the regs that are already used,
4272 preferring those used less often. The fixed and otherwise forbidden
4273 registers will be at the end of this list. */
4275 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4276 if (hard_reg_n_uses[i].uses != 0
4277 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4278 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4279 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4280 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4281 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4284 /* Reload pseudo-registers into hard regs around each insn as needed.
4285 Additional register load insns are output before the insn that needs it
4286 and perhaps store insns after insns that modify the reloaded pseudo reg.
4288 reg_last_reload_reg and reg_reloaded_contents keep track of
4289 which registers are already available in reload registers.
4290 We update these for the reloads that we perform,
4291 as the insns are scanned. */
4294 reload_as_needed (live_known)
4297 struct insn_chain *chain;
4298 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4303 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4304 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4305 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4306 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4307 reg_has_output_reload = (char *) alloca (max_regno);
4308 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4310 set_initial_elim_offsets ();
4312 for (chain = reload_insn_chain; chain; chain = chain->next)
4315 rtx insn = chain->insn;
4316 rtx old_next = NEXT_INSN (insn);
4318 /* If we pass a label, copy the offsets from the label information
4319 into the current offsets of each elimination. */
4320 if (GET_CODE (insn) == CODE_LABEL)
4321 set_offsets_for_label (insn);
4323 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4325 rtx oldpat = PATTERN (insn);
4327 /* If this is a USE and CLOBBER of a MEM, ensure that any
4328 references to eliminable registers have been removed. */
4330 if ((GET_CODE (PATTERN (insn)) == USE
4331 || GET_CODE (PATTERN (insn)) == CLOBBER)
4332 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4333 XEXP (XEXP (PATTERN (insn), 0), 0)
4334 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4335 GET_MODE (XEXP (PATTERN (insn), 0)),
4338 /* If we need to do register elimination processing, do so.
4339 This might delete the insn, in which case we are done. */
4340 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4342 eliminate_regs_in_insn (insn, 1);
4343 if (GET_CODE (insn) == NOTE)
4345 update_eliminable_offsets ();
4350 /* If need_elim is nonzero but need_reload is zero, one might think
4351 that we could simply set n_reloads to 0. However, find_reloads
4352 could have done some manipulation of the insn (such as swapping
4353 commutative operands), and these manipulations are lost during
4354 the first pass for every insn that needs register elimination.
4355 So the actions of find_reloads must be redone here. */
4357 if (! chain->need_elim && ! chain->need_reload
4358 && ! chain->need_operand_change)
4360 /* First find the pseudo regs that must be reloaded for this insn.
4361 This info is returned in the tables reload_... (see reload.h).
4362 Also modify the body of INSN by substituting RELOAD
4363 rtx's for those pseudo regs. */
4366 bzero (reg_has_output_reload, max_regno);
4367 CLEAR_HARD_REG_SET (reg_is_output_reload);
4369 find_reloads (insn, 1, spill_indirect_levels, live_known,
4373 if (num_eliminable && chain->need_elim)
4374 update_eliminable_offsets ();
4378 rtx next = NEXT_INSN (insn);
4381 prev = PREV_INSN (insn);
4383 /* Now compute which reload regs to reload them into. Perhaps
4384 reusing reload regs from previous insns, or else output
4385 load insns to reload them. Maybe output store insns too.
4386 Record the choices of reload reg in reload_reg_rtx. */
4387 choose_reload_regs (chain);
4389 /* Merge any reloads that we didn't combine for fear of
4390 increasing the number of spill registers needed but now
4391 discover can be safely merged. */
4392 if (SMALL_REGISTER_CLASSES)
4393 merge_assigned_reloads (insn);
4395 /* Generate the insns to reload operands into or out of
4396 their reload regs. */
4397 emit_reload_insns (chain);
4399 /* Substitute the chosen reload regs from reload_reg_rtx
4400 into the insn's body (or perhaps into the bodies of other
4401 load and store insn that we just made for reloading
4402 and that we moved the structure into). */
4405 /* If this was an ASM, make sure that all the reload insns
4406 we have generated are valid. If not, give an error
4409 if (asm_noperands (PATTERN (insn)) >= 0)
4410 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4411 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4412 && (recog_memoized (p) < 0
4413 || (extract_insn (p), ! constrain_operands (1))))
4415 error_for_asm (insn,
4416 "`asm' operand requires impossible reload");
4418 NOTE_SOURCE_FILE (p) = 0;
4419 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4422 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4423 is no longer validly lying around to save a future reload.
4424 Note that this does not detect pseudos that were reloaded
4425 for this insn in order to be stored in
4426 (obeying register constraints). That is correct; such reload
4427 registers ARE still valid. */
4428 note_stores (oldpat, forget_old_reloads_1, NULL);
4430 /* There may have been CLOBBER insns placed after INSN. So scan
4431 between INSN and NEXT and use them to forget old reloads. */
4432 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4433 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4434 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4437 /* Likewise for regs altered by auto-increment in this insn.
4438 REG_INC notes have been changed by reloading:
4439 find_reloads_address_1 records substitutions for them,
4440 which have been performed by subst_reloads above. */
4441 for (i = n_reloads - 1; i >= 0; i--)
4443 rtx in_reg = rld[i].in_reg;
4446 enum rtx_code code = GET_CODE (in_reg);
4447 /* PRE_INC / PRE_DEC will have the reload register ending up
4448 with the same value as the stack slot, but that doesn't
4449 hold true for POST_INC / POST_DEC. Either we have to
4450 convert the memory access to a true POST_INC / POST_DEC,
4451 or we can't use the reload register for inheritance. */
4452 if ((code == POST_INC || code == POST_DEC)
4453 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4454 REGNO (rld[i].reg_rtx))
4455 /* Make sure it is the inc/dec pseudo, and not
4456 some other (e.g. output operand) pseudo. */
4457 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4458 == REGNO (XEXP (in_reg, 0))))
4461 rtx reload_reg = rld[i].reg_rtx;
4462 enum machine_mode mode = GET_MODE (reload_reg);
4466 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4468 /* We really want to ignore REG_INC notes here, so
4469 use PATTERN (p) as argument to reg_set_p . */
4470 if (reg_set_p (reload_reg, PATTERN (p)))
4472 n = count_occurrences (PATTERN (p), reload_reg);
4477 n = validate_replace_rtx (reload_reg,
4478 gen_rtx (code, mode,
4482 /* We must also verify that the constraints
4483 are met after the replacement. */
4486 n = constrain_operands (1);
4490 /* If the constraints were not met, then
4491 undo the replacement. */
4494 validate_replace_rtx (gen_rtx (code, mode,
4506 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4508 /* Mark this as having an output reload so that the
4509 REG_INC processing code below won't invalidate
4510 the reload for inheritance. */
4511 SET_HARD_REG_BIT (reg_is_output_reload,
4512 REGNO (reload_reg));
4513 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4516 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4519 else if ((code == PRE_INC || code == PRE_DEC)
4520 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4521 REGNO (rld[i].reg_rtx))
4522 /* Make sure it is the inc/dec pseudo, and not
4523 some other (e.g. output operand) pseudo. */
4524 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4525 == REGNO (XEXP (in_reg, 0))))
4527 SET_HARD_REG_BIT (reg_is_output_reload,
4528 REGNO (rld[i].reg_rtx));
4529 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4533 /* If a pseudo that got a hard register is auto-incremented,
4534 we must purge records of copying it into pseudos without
4536 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4537 if (REG_NOTE_KIND (x) == REG_INC)
4539 /* See if this pseudo reg was reloaded in this insn.
4540 If so, its last-reload info is still valid
4541 because it is based on this insn's reload. */
4542 for (i = 0; i < n_reloads; i++)
4543 if (rld[i].out == XEXP (x, 0))
4547 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4551 /* A reload reg's contents are unknown after a label. */
4552 if (GET_CODE (insn) == CODE_LABEL)
4553 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4555 /* Don't assume a reload reg is still good after a call insn
4556 if it is a call-used reg. */
4557 else if (GET_CODE (insn) == CALL_INSN)
4558 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4560 /* In case registers overlap, allow certain insns to invalidate
4561 particular hard registers. */
4563 #ifdef INSN_CLOBBERS_REGNO_P
4564 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4565 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4566 && INSN_CLOBBERS_REGNO_P (insn, i))
4567 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4576 /* Discard all record of any value reloaded from X,
4577 or reloaded in X from someplace else;
4578 unless X is an output reload reg of the current insn.
4580 X may be a hard reg (the reload reg)
4581 or it may be a pseudo reg that was reloaded from. */
4584 forget_old_reloads_1 (x, ignored, data)
4586 rtx ignored ATTRIBUTE_UNUSED;
4587 void *data ATTRIBUTE_UNUSED;
4593 /* note_stores does give us subregs of hard regs. */
4594 while (GET_CODE (x) == SUBREG)
4596 offset += SUBREG_WORD (x);
4600 if (GET_CODE (x) != REG)
4603 regno = REGNO (x) + offset;
4605 if (regno >= FIRST_PSEUDO_REGISTER)
4610 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4611 /* Storing into a spilled-reg invalidates its contents.
4612 This can happen if a block-local pseudo is allocated to that reg
4613 and it wasn't spilled because this block's total need is 0.
4614 Then some insn might have an optional reload and use this reg. */
4615 for (i = 0; i < nr; i++)
4616 /* But don't do this if the reg actually serves as an output
4617 reload reg in the current instruction. */
4619 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4620 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4623 /* Since value of X has changed,
4624 forget any value previously copied from it. */
4627 /* But don't forget a copy if this is the output reload
4628 that establishes the copy's validity. */
4629 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4630 reg_last_reload_reg[regno + nr] = 0;
4633 /* Comparison function for qsort to decide which of two reloads
4634 should be handled first. *P1 and *P2 are the reload numbers. */
4637 reload_reg_class_lower (r1p, r2p)
4641 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
4644 /* Consider required reloads before optional ones. */
4645 t = rld[r1].optional - rld[r2].optional;
4649 /* Count all solitary classes before non-solitary ones. */
4650 t = ((reg_class_size[(int) rld[r2].class] == 1)
4651 - (reg_class_size[(int) rld[r1].class] == 1));
4655 /* Aside from solitaires, consider all multi-reg groups first. */
4656 t = rld[r2].nregs - rld[r1].nregs;
4660 /* Consider reloads in order of increasing reg-class number. */
4661 t = (int) rld[r1].class - (int) rld[r2].class;
4665 /* If reloads are equally urgent, sort by reload number,
4666 so that the results of qsort leave nothing to chance. */
4670 /* The following HARD_REG_SETs indicate when each hard register is
4671 used for a reload of various parts of the current insn. */
4673 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4674 static HARD_REG_SET reload_reg_used;
4675 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4676 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4677 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4678 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4679 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4680 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4681 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4682 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4683 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4684 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4685 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4686 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4687 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4688 static HARD_REG_SET reload_reg_used_in_op_addr;
4689 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4690 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4691 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4692 static HARD_REG_SET reload_reg_used_in_insn;
4693 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4694 static HARD_REG_SET reload_reg_used_in_other_addr;
4696 /* If reg is in use as a reload reg for any sort of reload. */
4697 static HARD_REG_SET reload_reg_used_at_all;
4699 /* If reg is use as an inherited reload. We just mark the first register
4701 static HARD_REG_SET reload_reg_used_for_inherit;
4703 /* Records which hard regs are used in any way, either as explicit use or
4704 by being allocated to a pseudo during any point of the current insn. */
4705 static HARD_REG_SET reg_used_in_insn;
4707 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4708 TYPE. MODE is used to indicate how many consecutive regs are
4712 mark_reload_reg_in_use (regno, opnum, type, mode)
4715 enum reload_type type;
4716 enum machine_mode mode;
4718 int nregs = HARD_REGNO_NREGS (regno, mode);
4721 for (i = regno; i < nregs + regno; i++)
4726 SET_HARD_REG_BIT (reload_reg_used, i);
4729 case RELOAD_FOR_INPUT_ADDRESS:
4730 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4733 case RELOAD_FOR_INPADDR_ADDRESS:
4734 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4737 case RELOAD_FOR_OUTPUT_ADDRESS:
4738 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4741 case RELOAD_FOR_OUTADDR_ADDRESS:
4742 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4745 case RELOAD_FOR_OPERAND_ADDRESS:
4746 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4749 case RELOAD_FOR_OPADDR_ADDR:
4750 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4753 case RELOAD_FOR_OTHER_ADDRESS:
4754 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4757 case RELOAD_FOR_INPUT:
4758 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4761 case RELOAD_FOR_OUTPUT:
4762 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4765 case RELOAD_FOR_INSN:
4766 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4770 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4774 /* Similarly, but show REGNO is no longer in use for a reload. */
4777 clear_reload_reg_in_use (regno, opnum, type, mode)
4780 enum reload_type type;
4781 enum machine_mode mode;
4783 int nregs = HARD_REGNO_NREGS (regno, mode);
4784 int start_regno, end_regno;
4786 /* A complication is that for some reload types, inheritance might
4787 allow multiple reloads of the same types to share a reload register.
4788 We set check_opnum if we have to check only reloads with the same
4789 operand number, and check_any if we have to check all reloads. */
4790 int check_opnum = 0;
4792 HARD_REG_SET *used_in_set;
4797 used_in_set = &reload_reg_used;
4800 case RELOAD_FOR_INPUT_ADDRESS:
4801 used_in_set = &reload_reg_used_in_input_addr[opnum];
4804 case RELOAD_FOR_INPADDR_ADDRESS:
4806 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4809 case RELOAD_FOR_OUTPUT_ADDRESS:
4810 used_in_set = &reload_reg_used_in_output_addr[opnum];
4813 case RELOAD_FOR_OUTADDR_ADDRESS:
4815 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4818 case RELOAD_FOR_OPERAND_ADDRESS:
4819 used_in_set = &reload_reg_used_in_op_addr;
4822 case RELOAD_FOR_OPADDR_ADDR:
4824 used_in_set = &reload_reg_used_in_op_addr_reload;
4827 case RELOAD_FOR_OTHER_ADDRESS:
4828 used_in_set = &reload_reg_used_in_other_addr;
4832 case RELOAD_FOR_INPUT:
4833 used_in_set = &reload_reg_used_in_input[opnum];
4836 case RELOAD_FOR_OUTPUT:
4837 used_in_set = &reload_reg_used_in_output[opnum];
4840 case RELOAD_FOR_INSN:
4841 used_in_set = &reload_reg_used_in_insn;
4846 /* We resolve conflicts with remaining reloads of the same type by
4847 excluding the intervals of of reload registers by them from the
4848 interval of freed reload registers. Since we only keep track of
4849 one set of interval bounds, we might have to exclude somewhat
4850 more then what would be necessary if we used a HARD_REG_SET here.
4851 But this should only happen very infrequently, so there should
4852 be no reason to worry about it. */
4854 start_regno = regno;
4855 end_regno = regno + nregs;
4856 if (check_opnum || check_any)
4858 for (i = n_reloads - 1; i >= 0; i--)
4860 if (rld[i].when_needed == type
4861 && (check_any || rld[i].opnum == opnum)
4864 int conflict_start = true_regnum (rld[i].reg_rtx);
4867 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4869 /* If there is an overlap with the first to-be-freed register,
4870 adjust the interval start. */
4871 if (conflict_start <= start_regno && conflict_end > start_regno)
4872 start_regno = conflict_end;
4873 /* Otherwise, if there is a conflict with one of the other
4874 to-be-freed registers, adjust the interval end. */
4875 if (conflict_start > start_regno && conflict_start < end_regno)
4876 end_regno = conflict_start;
4880 for (i = start_regno; i < end_regno; i++)
4881 CLEAR_HARD_REG_BIT (*used_in_set, i);
4884 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4885 specified by OPNUM and TYPE. */
4888 reload_reg_free_p (regno, opnum, type)
4891 enum reload_type type;
4895 /* In use for a RELOAD_OTHER means it's not available for anything. */
4896 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4902 /* In use for anything means we can't use it for RELOAD_OTHER. */
4903 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4904 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4905 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4908 for (i = 0; i < reload_n_operands; i++)
4909 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4910 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4911 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4912 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4913 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4914 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4919 case RELOAD_FOR_INPUT:
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4921 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4924 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4927 /* If it is used for some other input, can't use it. */
4928 for (i = 0; i < reload_n_operands; i++)
4929 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4932 /* If it is used in a later operand's address, can't use it. */
4933 for (i = opnum + 1; i < reload_n_operands; i++)
4934 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4935 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4940 case RELOAD_FOR_INPUT_ADDRESS:
4941 /* Can't use a register if it is used for an input address for this
4942 operand or used as an input in an earlier one. */
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4947 for (i = 0; i < opnum; i++)
4948 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4953 case RELOAD_FOR_INPADDR_ADDRESS:
4954 /* Can't use a register if it is used for an input address
4955 for this operand or used as an input in an earlier
4957 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4960 for (i = 0; i < opnum; i++)
4961 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4966 case RELOAD_FOR_OUTPUT_ADDRESS:
4967 /* Can't use a register if it is used for an output address for this
4968 operand or used as an output in this or a later operand. */
4969 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4972 for (i = opnum; i < reload_n_operands; i++)
4973 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4978 case RELOAD_FOR_OUTADDR_ADDRESS:
4979 /* Can't use a register if it is used for an output address
4980 for this operand or used as an output in this or a
4982 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4985 for (i = opnum; i < reload_n_operands; i++)
4986 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4991 case RELOAD_FOR_OPERAND_ADDRESS:
4992 for (i = 0; i < reload_n_operands; i++)
4993 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4996 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4997 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4999 case RELOAD_FOR_OPADDR_ADDR:
5000 for (i = 0; i < reload_n_operands; i++)
5001 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5004 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5006 case RELOAD_FOR_OUTPUT:
5007 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5008 outputs, or an operand address for this or an earlier output. */
5009 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5012 for (i = 0; i < reload_n_operands; i++)
5013 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5016 for (i = 0; i <= opnum; i++)
5017 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5018 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5023 case RELOAD_FOR_INSN:
5024 for (i = 0; i < reload_n_operands; i++)
5025 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5026 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5029 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5030 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5032 case RELOAD_FOR_OTHER_ADDRESS:
5033 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5038 /* Return 1 if the value in reload reg REGNO, as used by a reload
5039 needed for the part of the insn specified by OPNUM and TYPE,
5040 is still available in REGNO at the end of the insn.
5042 We can assume that the reload reg was already tested for availability
5043 at the time it is needed, and we should not check this again,
5044 in case the reg has already been marked in use. */
5047 reload_reg_reaches_end_p (regno, opnum, type)
5050 enum reload_type type;
5057 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5058 its value must reach the end. */
5061 /* If this use is for part of the insn,
5062 its value reaches if no subsequent part uses the same register.
5063 Just like the above function, don't try to do this with lots
5066 case RELOAD_FOR_OTHER_ADDRESS:
5067 /* Here we check for everything else, since these don't conflict
5068 with anything else and everything comes later. */
5070 for (i = 0; i < reload_n_operands; i++)
5071 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5072 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5073 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5074 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5075 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5076 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5079 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5080 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5081 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5083 case RELOAD_FOR_INPUT_ADDRESS:
5084 case RELOAD_FOR_INPADDR_ADDRESS:
5085 /* Similar, except that we check only for this and subsequent inputs
5086 and the address of only subsequent inputs and we do not need
5087 to check for RELOAD_OTHER objects since they are known not to
5090 for (i = opnum; i < reload_n_operands; i++)
5091 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5094 for (i = opnum + 1; i < reload_n_operands; i++)
5095 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5096 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5099 for (i = 0; i < reload_n_operands; i++)
5100 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5101 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5102 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5105 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5108 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5109 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5111 case RELOAD_FOR_INPUT:
5112 /* Similar to input address, except we start at the next operand for
5113 both input and input address and we do not check for
5114 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5117 for (i = opnum + 1; i < reload_n_operands; i++)
5118 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5119 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5120 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5123 /* ... fall through ... */
5125 case RELOAD_FOR_OPERAND_ADDRESS:
5126 /* Check outputs and their addresses. */
5128 for (i = 0; i < reload_n_operands; i++)
5129 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5130 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5131 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5136 case RELOAD_FOR_OPADDR_ADDR:
5137 for (i = 0; i < reload_n_operands; i++)
5138 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5139 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5140 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5143 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5144 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5146 case RELOAD_FOR_INSN:
5147 /* These conflict with other outputs with RELOAD_OTHER. So
5148 we need only check for output addresses. */
5152 /* ... fall through ... */
5154 case RELOAD_FOR_OUTPUT:
5155 case RELOAD_FOR_OUTPUT_ADDRESS:
5156 case RELOAD_FOR_OUTADDR_ADDRESS:
5157 /* We already know these can't conflict with a later output. So the
5158 only thing to check are later output addresses. */
5159 for (i = opnum + 1; i < reload_n_operands; i++)
5160 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5161 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5170 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5173 This function uses the same algorithm as reload_reg_free_p above. */
5176 reloads_conflict (r1, r2)
5179 enum reload_type r1_type = rld[r1].when_needed;
5180 enum reload_type r2_type = rld[r2].when_needed;
5181 int r1_opnum = rld[r1].opnum;
5182 int r2_opnum = rld[r2].opnum;
5184 /* RELOAD_OTHER conflicts with everything. */
5185 if (r2_type == RELOAD_OTHER)
5188 /* Otherwise, check conflicts differently for each type. */
5192 case RELOAD_FOR_INPUT:
5193 return (r2_type == RELOAD_FOR_INSN
5194 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5195 || r2_type == RELOAD_FOR_OPADDR_ADDR
5196 || r2_type == RELOAD_FOR_INPUT
5197 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5198 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5199 && r2_opnum > r1_opnum));
5201 case RELOAD_FOR_INPUT_ADDRESS:
5202 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5203 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5205 case RELOAD_FOR_INPADDR_ADDRESS:
5206 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5207 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5209 case RELOAD_FOR_OUTPUT_ADDRESS:
5210 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5211 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5213 case RELOAD_FOR_OUTADDR_ADDRESS:
5214 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5215 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5217 case RELOAD_FOR_OPERAND_ADDRESS:
5218 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5219 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5221 case RELOAD_FOR_OPADDR_ADDR:
5222 return (r2_type == RELOAD_FOR_INPUT
5223 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5225 case RELOAD_FOR_OUTPUT:
5226 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5227 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5228 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5229 && r2_opnum >= r1_opnum));
5231 case RELOAD_FOR_INSN:
5232 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5233 || r2_type == RELOAD_FOR_INSN
5234 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5236 case RELOAD_FOR_OTHER_ADDRESS:
5237 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5247 /* Vector of reload-numbers showing the order in which the reloads should
5249 short reload_order[MAX_RELOADS];
5251 /* Indexed by reload number, 1 if incoming value
5252 inherited from previous insns. */
5253 char reload_inherited[MAX_RELOADS];
5255 /* For an inherited reload, this is the insn the reload was inherited from,
5256 if we know it. Otherwise, this is 0. */
5257 rtx reload_inheritance_insn[MAX_RELOADS];
5259 /* If non-zero, this is a place to get the value of the reload,
5260 rather than using reload_in. */
5261 rtx reload_override_in[MAX_RELOADS];
5263 /* For each reload, the hard register number of the register used,
5264 or -1 if we did not need a register for this reload. */
5265 int reload_spill_index[MAX_RELOADS];
5267 /* Return 1 if the value in reload reg REGNO, as used by a reload
5268 needed for the part of the insn specified by OPNUM and TYPE,
5269 may be used to load VALUE into it.
5271 Other read-only reloads with the same value do not conflict
5272 unless OUT is non-zero and these other reloads have to live while
5273 output reloads live.
5274 If OUT is CONST0_RTX, this is a special case: it means that the
5275 test should not be for using register REGNO as reload register, but
5276 for copying from register REGNO into the reload register.
5278 RELOADNUM is the number of the reload we want to load this value for;
5279 a reload does not conflict with itself.
5281 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5282 reloads that load an address for the very reload we are considering.
5284 The caller has to make sure that there is no conflict with the return
5287 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5288 ignore_address_reloads)
5291 enum reload_type type;
5294 int ignore_address_reloads;
5297 /* Set if we see an input reload that must not share its reload register
5298 with any new earlyclobber, but might otherwise share the reload
5299 register with an output or input-output reload. */
5300 int check_earlyclobber = 0;
5304 if (out == const0_rtx)
5310 /* We use some pseudo 'time' value to check if the lifetimes of the
5311 new register use would overlap with the one of a previous reload
5312 that is not read-only or uses a different value.
5313 The 'time' used doesn't have to be linear in any shape or form, just
5315 Some reload types use different 'buckets' for each operand.
5316 So there are MAX_RECOG_OPERANDS different time values for each
5318 We compute TIME1 as the time when the register for the prospective
5319 new reload ceases to be live, and TIME2 for each existing
5320 reload as the time when that the reload register of that reload
5322 Where there is little to be gained by exact lifetime calculations,
5323 we just make conservative assumptions, i.e. a longer lifetime;
5324 this is done in the 'default:' cases. */
5327 case RELOAD_FOR_OTHER_ADDRESS:
5328 /* RELOAD_FOR_OTHER_ADDRESS conflits with RELOAD_OTHER reloads. */
5329 time1 = copy ? 0 : 1;
5332 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5334 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5335 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5336 respectively, to the time values for these, we get distinct time
5337 values. To get distinct time values for each operand, we have to
5338 multiply opnum by at least three. We round that up to four because
5339 multiply by four is often cheaper. */
5340 case RELOAD_FOR_INPADDR_ADDRESS:
5341 time1 = opnum * 4 + 2;
5343 case RELOAD_FOR_INPUT_ADDRESS:
5344 time1 = opnum * 4 + 3;
5346 case RELOAD_FOR_INPUT:
5347 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5348 executes (inclusive). */
5349 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5351 case RELOAD_FOR_OPADDR_ADDR:
5353 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5354 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5356 case RELOAD_FOR_OPERAND_ADDRESS:
5357 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5359 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5361 case RELOAD_FOR_OUTADDR_ADDRESS:
5362 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5364 case RELOAD_FOR_OUTPUT_ADDRESS:
5365 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5368 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5371 for (i = 0; i < n_reloads; i++)
5373 rtx reg = rld[i].reg_rtx;
5374 if (reg && GET_CODE (reg) == REG
5375 && ((unsigned) regno - true_regnum (reg)
5376 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5379 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
5380 || rld[i].out || out)
5383 switch (rld[i].when_needed)
5385 case RELOAD_FOR_OTHER_ADDRESS:
5388 case RELOAD_FOR_INPADDR_ADDRESS:
5389 /* find_reloads makes sure that a
5390 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5391 by at most one - the first -
5392 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5393 address reload is inherited, the address address reload
5394 goes away, so we can ignore this conflict. */
5395 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5396 && ignore_address_reloads
5397 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5398 Then the address address is still needed to store
5399 back the new address. */
5400 && ! rld[reloadnum].out)
5402 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5403 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5405 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5406 && ignore_address_reloads
5407 /* Unless we are reloading an auto_inc expression. */
5408 && ! rld[reloadnum].out)
5410 time2 = rld[i].opnum * 4 + 2;
5412 case RELOAD_FOR_INPUT_ADDRESS:
5413 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5414 && ignore_address_reloads
5415 && ! rld[reloadnum].out)
5417 time2 = rld[i].opnum * 4 + 3;
5419 case RELOAD_FOR_INPUT:
5420 time2 = rld[i].opnum * 4 + 4;
5421 check_earlyclobber = 1;
5423 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5424 == MAX_RECOG_OPERAND * 4 */
5425 case RELOAD_FOR_OPADDR_ADDR:
5426 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5427 && ignore_address_reloads
5428 && ! rld[reloadnum].out)
5430 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5432 case RELOAD_FOR_OPERAND_ADDRESS:
5433 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5434 check_earlyclobber = 1;
5436 case RELOAD_FOR_INSN:
5437 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5439 case RELOAD_FOR_OUTPUT:
5440 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5441 instruction is executed. */
5442 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5444 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5445 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5447 case RELOAD_FOR_OUTADDR_ADDRESS:
5448 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5449 && ignore_address_reloads
5450 && ! rld[reloadnum].out)
5452 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5454 case RELOAD_FOR_OUTPUT_ADDRESS:
5455 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5458 /* If there is no conflict in the input part, handle this
5459 like an output reload. */
5460 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
5462 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5463 /* Earlyclobbered outputs must conflict with inputs. */
5464 if (earlyclobber_operand_p (rld[i].out))
5465 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5470 /* RELOAD_OTHER might be live beyond instruction execution,
5471 but this is not obvious when we set time2 = 1. So check
5472 here if there might be a problem with the new reload
5473 clobbering the register used by the RELOAD_OTHER. */
5481 && (! rld[i].in || rld[i].out
5482 || ! rtx_equal_p (rld[i].in, value)))
5483 || (out && rld[reloadnum].out_reg
5484 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5490 /* Earlyclobbered outputs must conflict with inputs. */
5491 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5497 /* Give an error message saying we failed to find a reload for INSN,
5498 and clear out reload R. */
5500 failed_reload (insn, r)
5504 if (asm_noperands (PATTERN (insn)) < 0)
5505 /* It's the compiler's fault. */
5506 fatal_insn ("Could not find a spill register", insn);
5508 /* It's the user's fault; the operand's mode and constraint
5509 don't match. Disable this reload so we don't crash in final. */
5510 error_for_asm (insn,
5511 "`asm' operand constraint incompatible with operand size");
5515 rld[r].optional = 1;
5516 rld[r].secondary_p = 1;
5519 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5520 for reload R. If it's valid, get an rtx for it. Return nonzero if
5523 set_reload_reg (i, r)
5527 rtx reg = spill_reg_rtx[i];
5529 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5530 spill_reg_rtx[i] = reg
5531 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5533 regno = true_regnum (reg);
5535 /* Detect when the reload reg can't hold the reload mode.
5536 This used to be one `if', but Sequent compiler can't handle that. */
5537 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5539 enum machine_mode test_mode = VOIDmode;
5541 test_mode = GET_MODE (rld[r].in);
5542 /* If rld[r].in has VOIDmode, it means we will load it
5543 in whatever mode the reload reg has: to wit, rld[r].mode.
5544 We have already tested that for validity. */
5545 /* Aside from that, we need to test that the expressions
5546 to reload from or into have modes which are valid for this
5547 reload register. Otherwise the reload insns would be invalid. */
5548 if (! (rld[r].in != 0 && test_mode != VOIDmode
5549 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5550 if (! (rld[r].out != 0
5551 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5553 /* The reg is OK. */
5556 /* Mark as in use for this insn the reload regs we use
5558 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5559 rld[r].when_needed, rld[r].mode);
5561 rld[r].reg_rtx = reg;
5562 reload_spill_index[r] = spill_regs[i];
5569 /* Find a spill register to use as a reload register for reload R.
5570 LAST_RELOAD is non-zero if this is the last reload for the insn being
5573 Set rld[R].reg_rtx to the register allocated.
5575 If NOERROR is nonzero, we return 1 if successful,
5576 or 0 if we couldn't find a spill reg and we didn't change anything. */
5579 allocate_reload_reg (chain, r, last_reload, noerror)
5580 struct insn_chain *chain;
5585 rtx insn = chain->insn;
5588 /* If we put this reload ahead, thinking it is a group,
5589 then insist on finding a group. Otherwise we can grab a
5590 reg that some other reload needs.
5591 (That can happen when we have a 68000 DATA_OR_FP_REG
5592 which is a group of data regs or one fp reg.)
5593 We need not be so restrictive if there are no more reloads
5596 ??? Really it would be nicer to have smarter handling
5597 for that kind of reg class, where a problem like this is normal.
5598 Perhaps those classes should be avoided for reloading
5599 by use of more alternatives. */
5601 int force_group = rld[r].nregs > 1 && ! last_reload;
5603 /* If we want a single register and haven't yet found one,
5604 take any reg in the right class and not in use.
5605 If we want a consecutive group, here is where we look for it.
5607 We use two passes so we can first look for reload regs to
5608 reuse, which are already in use for other reloads in this insn,
5609 and only then use additional registers.
5610 I think that maximizing reuse is needed to make sure we don't
5611 run out of reload regs. Suppose we have three reloads, and
5612 reloads A and B can share regs. These need two regs.
5613 Suppose A and B are given different regs.
5614 That leaves none for C. */
5615 for (pass = 0; pass < 2; pass++)
5617 /* I is the index in spill_regs.
5618 We advance it round-robin between insns to use all spill regs
5619 equally, so that inherited reloads have a chance
5620 of leapfrogging each other. Don't do this, however, when we have
5621 group needs and failure would be fatal; if we only have a relatively
5622 small number of spill registers, and more than one of them has
5623 group needs, then by starting in the middle, we may end up
5624 allocating the first one in such a way that we are not left with
5625 sufficient groups to handle the rest. */
5627 if (noerror || ! force_group)
5632 for (count = 0; count < n_spills; count++)
5634 int class = (int) rld[r].class;
5640 regnum = spill_regs[i];
5642 if ((reload_reg_free_p (regnum, rld[r].opnum,
5645 /* We check reload_reg_used to make sure we
5646 don't clobber the return register. */
5647 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5648 && reload_reg_free_for_value_p (regnum,
5653 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5654 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5655 /* Look first for regs to share, then for unshared. But
5656 don't share regs used for inherited reloads; they are
5657 the ones we want to preserve. */
5659 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5661 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5664 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5665 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5666 (on 68000) got us two FP regs. If NR is 1,
5667 we would reject both of them. */
5670 /* If we need only one reg, we have already won. */
5673 /* But reject a single reg if we demand a group. */
5678 /* Otherwise check that as many consecutive regs as we need
5680 Also, don't use for a group registers that are
5681 needed for nongroups. */
5682 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5685 int regno = regnum + nr - 1;
5686 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5687 && spill_reg_order[regno] >= 0
5688 && reload_reg_free_p (regno, rld[r].opnum,
5690 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5700 /* If we found something on pass 1, omit pass 2. */
5701 if (count < n_spills)
5705 /* We should have found a spill register by now. */
5706 if (count == n_spills)
5713 if (set_reload_reg (i, r))
5716 /* The reg is not OK. */
5721 failed_reload (insn, r);
5726 /* Initialize all the tables needed to allocate reload registers.
5727 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5728 is the array we use to restore the reg_rtx field for every reload. */
5730 choose_reload_regs_init (chain, save_reload_reg_rtx)
5731 struct insn_chain *chain;
5732 rtx *save_reload_reg_rtx;
5736 for (i = 0; i < n_reloads; i++)
5737 rld[i].reg_rtx = save_reload_reg_rtx[i];
5739 bzero (reload_inherited, MAX_RELOADS);
5740 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5741 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5743 CLEAR_HARD_REG_SET (reload_reg_used);
5744 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5745 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5746 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5747 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5748 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5750 CLEAR_HARD_REG_SET (reg_used_in_insn);
5753 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5754 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5755 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5756 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5757 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5758 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5760 for (i = 0; i < reload_n_operands; i++)
5762 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5763 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5764 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5765 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5766 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5767 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5770 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5772 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5774 for (i = 0; i < n_reloads; i++)
5775 /* If we have already decided to use a certain register,
5776 don't use it in another way. */
5778 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5779 rld[i].when_needed, rld[i].mode);
5782 /* Assign hard reg targets for the pseudo-registers we must reload
5783 into hard regs for this insn.
5784 Also output the instructions to copy them in and out of the hard regs.
5786 For machines with register classes, we are responsible for
5787 finding a reload reg in the proper class. */
5790 choose_reload_regs (chain)
5791 struct insn_chain *chain;
5793 rtx insn = chain->insn;
5795 int max_group_size = 1;
5796 enum reg_class group_class = NO_REGS;
5800 rtx save_reload_reg_rtx[MAX_RELOADS];
5802 /* In order to be certain of getting the registers we need,
5803 we must sort the reloads into order of increasing register class.
5804 Then our grabbing of reload registers will parallel the process
5805 that provided the reload registers.
5807 Also note whether any of the reloads wants a consecutive group of regs.
5808 If so, record the maximum size of the group desired and what
5809 register class contains all the groups needed by this insn. */
5811 for (j = 0; j < n_reloads; j++)
5813 reload_order[j] = j;
5814 reload_spill_index[j] = -1;
5816 if (rld[j].nregs > 1)
5818 max_group_size = MAX (rld[j].nregs, max_group_size);
5819 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5822 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5826 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5828 /* If -O, try first with inheritance, then turning it off.
5829 If not -O, don't do inheritance.
5830 Using inheritance when not optimizing leads to paradoxes
5831 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5832 because one side of the comparison might be inherited. */
5834 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5836 choose_reload_regs_init (chain, save_reload_reg_rtx);
5838 /* Process the reloads in order of preference just found.
5839 Beyond this point, subregs can be found in reload_reg_rtx.
5841 This used to look for an existing reloaded home for all
5842 of the reloads, and only then perform any new reloads.
5843 But that could lose if the reloads were done out of reg-class order
5844 because a later reload with a looser constraint might have an old
5845 home in a register needed by an earlier reload with a tighter constraint.
5847 To solve this, we make two passes over the reloads, in the order
5848 described above. In the first pass we try to inherit a reload
5849 from a previous insn. If there is a later reload that needs a
5850 class that is a proper subset of the class being processed, we must
5851 also allocate a spill register during the first pass.
5853 Then make a second pass over the reloads to allocate any reloads
5854 that haven't been given registers yet. */
5856 for (j = 0; j < n_reloads; j++)
5858 register int r = reload_order[j];
5859 rtx search_equiv = NULL_RTX;
5861 /* Ignore reloads that got marked inoperative. */
5862 if (rld[r].out == 0 && rld[r].in == 0
5863 && ! rld[r].secondary_p)
5866 /* If find_reloads chose to use reload_in or reload_out as a reload
5867 register, we don't need to chose one. Otherwise, try even if it
5868 found one since we might save an insn if we find the value lying
5870 Try also when reload_in is a pseudo without a hard reg. */
5871 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5872 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5873 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5874 && GET_CODE (rld[r].in) != MEM
5875 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5878 #if 0 /* No longer needed for correct operation.
5879 It might give better code, or might not; worth an experiment? */
5880 /* If this is an optional reload, we can't inherit from earlier insns
5881 until we are sure that any non-optional reloads have been allocated.
5882 The following code takes advantage of the fact that optional reloads
5883 are at the end of reload_order. */
5884 if (rld[r].optional != 0)
5885 for (i = 0; i < j; i++)
5886 if ((rld[reload_order[i]].out != 0
5887 || rld[reload_order[i]].in != 0
5888 || rld[reload_order[i]].secondary_p)
5889 && ! rld[reload_order[i]].optional
5890 && rld[reload_order[i]].reg_rtx == 0)
5891 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5894 /* First see if this pseudo is already available as reloaded
5895 for a previous insn. We cannot try to inherit for reloads
5896 that are smaller than the maximum number of registers needed
5897 for groups unless the register we would allocate cannot be used
5900 We could check here to see if this is a secondary reload for
5901 an object that is already in a register of the desired class.
5902 This would avoid the need for the secondary reload register.
5903 But this is complex because we can't easily determine what
5904 objects might want to be loaded via this reload. So let a
5905 register be allocated here. In `emit_reload_insns' we suppress
5906 one of the loads in the case described above. */
5911 register int regno = -1;
5912 enum machine_mode mode = VOIDmode;
5916 else if (GET_CODE (rld[r].in) == REG)
5918 regno = REGNO (rld[r].in);
5919 mode = GET_MODE (rld[r].in);
5921 else if (GET_CODE (rld[r].in_reg) == REG)
5923 regno = REGNO (rld[r].in_reg);
5924 mode = GET_MODE (rld[r].in_reg);
5926 else if (GET_CODE (rld[r].in_reg) == SUBREG
5927 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5929 word = SUBREG_WORD (rld[r].in_reg);
5930 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5931 if (regno < FIRST_PSEUDO_REGISTER)
5933 mode = GET_MODE (rld[r].in_reg);
5936 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5937 || GET_CODE (rld[r].in_reg) == PRE_DEC
5938 || GET_CODE (rld[r].in_reg) == POST_INC
5939 || GET_CODE (rld[r].in_reg) == POST_DEC)
5940 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5942 regno = REGNO (XEXP (rld[r].in_reg, 0));
5943 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5944 rld[r].out = rld[r].in;
5948 /* This won't work, since REGNO can be a pseudo reg number.
5949 Also, it takes much more hair to keep track of all the things
5950 that can invalidate an inherited reload of part of a pseudoreg. */
5951 else if (GET_CODE (rld[r].in) == SUBREG
5952 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5953 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5956 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5958 enum reg_class class = rld[r].class, last_class;
5959 rtx last_reg = reg_last_reload_reg[regno];
5961 i = REGNO (last_reg) + word;
5962 last_class = REGNO_REG_CLASS (i);
5963 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5964 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5965 && reg_reloaded_contents[i] == regno
5966 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5967 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5968 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5969 /* Even if we can't use this register as a reload
5970 register, we might use it for reload_override_in,
5971 if copying it to the desired class is cheap
5973 || ((REGISTER_MOVE_COST (last_class, class)
5974 < MEMORY_MOVE_COST (mode, class, 1))
5975 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5976 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5980 #ifdef SECONDARY_MEMORY_NEEDED
5981 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5986 && (rld[r].nregs == max_group_size
5987 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5989 && reload_reg_free_for_value_p (i, rld[r].opnum,
5994 /* If a group is needed, verify that all the subsequent
5995 registers still have their values intact. */
5997 = HARD_REGNO_NREGS (i, rld[r].mode);
6000 for (k = 1; k < nr; k++)
6001 if (reg_reloaded_contents[i + k] != regno
6002 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6009 last_reg = (GET_MODE (last_reg) == mode
6010 ? last_reg : gen_rtx_REG (mode, i));
6012 /* We found a register that contains the
6013 value we need. If this register is the
6014 same as an `earlyclobber' operand of the
6015 current insn, just mark it as a place to
6016 reload from since we can't use it as the
6017 reload register itself. */
6019 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6020 if (reg_overlap_mentioned_for_reload_p
6021 (reg_last_reload_reg[regno],
6022 reload_earlyclobbers[i1]))
6025 if (i1 != n_earlyclobbers
6026 || ! (reload_reg_free_for_value_p
6027 (i, rld[r].opnum, rld[r].when_needed,
6028 rld[r].in, rld[r].out, r, 1))
6029 /* Don't use it if we'd clobber a pseudo reg. */
6030 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6032 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6033 /* Don't clobber the frame pointer. */
6034 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
6035 /* Don't really use the inherited spill reg
6036 if we need it wider than we've got it. */
6037 || (GET_MODE_SIZE (rld[r].mode)
6038 > GET_MODE_SIZE (mode))
6039 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6042 /* If find_reloads chose reload_out as reload
6043 register, stay with it - that leaves the
6044 inherited register for subsequent reloads. */
6045 || (rld[r].out && rld[r].reg_rtx
6046 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6048 reload_override_in[r] = last_reg;
6049 reload_inheritance_insn[r]
6050 = reg_reloaded_insn[i];
6055 /* We can use this as a reload reg. */
6056 /* Mark the register as in use for this part of
6058 mark_reload_reg_in_use (i,
6062 rld[r].reg_rtx = last_reg;
6063 reload_inherited[r] = 1;
6064 reload_inheritance_insn[r]
6065 = reg_reloaded_insn[i];
6066 reload_spill_index[r] = i;
6067 for (k = 0; k < nr; k++)
6068 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6076 /* Here's another way to see if the value is already lying around. */
6079 && ! reload_inherited[r]
6081 && (CONSTANT_P (rld[r].in)
6082 || GET_CODE (rld[r].in) == PLUS
6083 || GET_CODE (rld[r].in) == REG
6084 || GET_CODE (rld[r].in) == MEM)
6085 && (rld[r].nregs == max_group_size
6086 || ! reg_classes_intersect_p (rld[r].class, group_class)))
6087 search_equiv = rld[r].in;
6088 /* If this is an output reload from a simple move insn, look
6089 if an equivalence for the input is available. */
6090 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6092 rtx set = single_set (insn);
6095 && rtx_equal_p (rld[r].out, SET_DEST (set))
6096 && CONSTANT_P (SET_SRC (set)))
6097 search_equiv = SET_SRC (set);
6103 = find_equiv_reg (search_equiv, insn, rld[r].class,
6104 -1, NULL_PTR, 0, rld[r].mode);
6109 if (GET_CODE (equiv) == REG)
6110 regno = REGNO (equiv);
6111 else if (GET_CODE (equiv) == SUBREG)
6113 /* This must be a SUBREG of a hard register.
6114 Make a new REG since this might be used in an
6115 address and not all machines support SUBREGs
6117 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6118 equiv = gen_rtx_REG (rld[r].mode, regno);
6124 /* If we found a spill reg, reject it unless it is free
6125 and of the desired class. */
6127 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6128 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
6132 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6136 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6139 /* We found a register that contains the value we need.
6140 If this register is the same as an `earlyclobber' operand
6141 of the current insn, just mark it as a place to reload from
6142 since we can't use it as the reload register itself. */
6145 for (i = 0; i < n_earlyclobbers; i++)
6146 if (reg_overlap_mentioned_for_reload_p (equiv,
6147 reload_earlyclobbers[i]))
6149 reload_override_in[r] = equiv;
6154 /* If the equiv register we have found is explicitly clobbered
6155 in the current insn, it depends on the reload type if we
6156 can use it, use it for reload_override_in, or not at all.
6157 In particular, we then can't use EQUIV for a
6158 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6160 if (equiv != 0 && regno_clobbered_p (regno, insn))
6162 switch (rld[r].when_needed)
6164 case RELOAD_FOR_OTHER_ADDRESS:
6165 case RELOAD_FOR_INPADDR_ADDRESS:
6166 case RELOAD_FOR_INPUT_ADDRESS:
6167 case RELOAD_FOR_OPADDR_ADDR:
6170 case RELOAD_FOR_INPUT:
6171 case RELOAD_FOR_OPERAND_ADDRESS:
6172 reload_override_in[r] = equiv;
6180 /* If we found an equivalent reg, say no code need be generated
6181 to load it, and use it as our reload reg. */
6182 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6184 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
6186 rld[r].reg_rtx = equiv;
6187 reload_inherited[r] = 1;
6189 /* If reg_reloaded_valid is not set for this register,
6190 there might be a stale spill_reg_store lying around.
6191 We must clear it, since otherwise emit_reload_insns
6192 might delete the store. */
6193 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6194 spill_reg_store[regno] = NULL_RTX;
6195 /* If any of the hard registers in EQUIV are spill
6196 registers, mark them as in use for this insn. */
6197 for (k = 0; k < nr; k++)
6199 i = spill_reg_order[regno + k];
6202 mark_reload_reg_in_use (regno, rld[r].opnum,
6205 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6212 /* If we found a register to use already, or if this is an optional
6213 reload, we are done. */
6214 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6217 #if 0 /* No longer needed for correct operation. Might or might not
6218 give better code on the average. Want to experiment? */
6220 /* See if there is a later reload that has a class different from our
6221 class that intersects our class or that requires less register
6222 than our reload. If so, we must allocate a register to this
6223 reload now, since that reload might inherit a previous reload
6224 and take the only available register in our class. Don't do this
6225 for optional reloads since they will force all previous reloads
6226 to be allocated. Also don't do this for reloads that have been
6229 for (i = j + 1; i < n_reloads; i++)
6231 int s = reload_order[i];
6233 if ((rld[s].in == 0 && rld[s].out == 0
6234 && ! rld[s].secondary_p)
6238 if ((rld[s].class != rld[r].class
6239 && reg_classes_intersect_p (rld[r].class,
6241 || rld[s].nregs < rld[r].nregs)
6248 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6252 /* Now allocate reload registers for anything non-optional that
6253 didn't get one yet. */
6254 for (j = 0; j < n_reloads; j++)
6256 register int r = reload_order[j];
6258 /* Ignore reloads that got marked inoperative. */
6259 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6262 /* Skip reloads that already have a register allocated or are
6264 if (rld[r].reg_rtx != 0 || rld[r].optional)
6267 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6271 /* If that loop got all the way, we have won. */
6275 /* Loop around and try without any inheritance. */
6278 /* If we thought we could inherit a reload, because it seemed that
6279 nothing else wanted the same reload register earlier in the insn,
6280 verify that assumption, now that all reloads have been assigned.
6281 Likewise for reloads where reload_override_in has been set. */
6283 /* If doing expensive optimizations, do one preliminary pass that doesn't
6284 cancel any inheritance, but removes reloads that have been needed only
6285 for reloads that we know can be inherited. */
6286 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6288 for (j = 0; j < n_reloads; j++)
6290 register int r = reload_order[j];
6292 if (reload_inherited[r] && rld[r].reg_rtx)
6293 check_reg = rld[r].reg_rtx;
6294 else if (reload_override_in[r]
6295 && (GET_CODE (reload_override_in[r]) == REG
6296 || GET_CODE (reload_override_in[r]) == SUBREG))
6297 check_reg = reload_override_in[r];
6300 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6304 (reload_inherited[r]
6305 ? rld[r].out : const0_rtx),
6310 reload_inherited[r] = 0;
6311 reload_override_in[r] = 0;
6313 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6314 reload_override_in, then we do not need its related
6315 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6316 likewise for other reload types.
6317 We handle this by removing a reload when its only replacement
6318 is mentioned in reload_in of the reload we are going to inherit.
6319 A special case are auto_inc expressions; even if the input is
6320 inherited, we still need the address for the output. We can
6321 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6322 If we suceeded removing some reload and we are doing a preliminary
6323 pass just to remove such reloads, make another pass, since the
6324 removal of one reload might allow us to inherit another one. */
6326 && rld[r].out != rld[r].in
6327 && remove_address_replacements (rld[r].in) && pass)
6332 /* Now that reload_override_in is known valid,
6333 actually override reload_in. */
6334 for (j = 0; j < n_reloads; j++)
6335 if (reload_override_in[j])
6336 rld[j].in = reload_override_in[j];
6338 /* If this reload won't be done because it has been cancelled or is
6339 optional and not inherited, clear reload_reg_rtx so other
6340 routines (such as subst_reloads) don't get confused. */
6341 for (j = 0; j < n_reloads; j++)
6342 if (rld[j].reg_rtx != 0
6343 && ((rld[j].optional && ! reload_inherited[j])
6344 || (rld[j].in == 0 && rld[j].out == 0
6345 && ! rld[j].secondary_p)))
6347 int regno = true_regnum (rld[j].reg_rtx);
6349 if (spill_reg_order[regno] >= 0)
6350 clear_reload_reg_in_use (regno, rld[j].opnum,
6351 rld[j].when_needed, rld[j].mode);
6355 /* Record which pseudos and which spill regs have output reloads. */
6356 for (j = 0; j < n_reloads; j++)
6358 register int r = reload_order[j];
6360 i = reload_spill_index[r];
6362 /* I is nonneg if this reload uses a register.
6363 If rld[r].reg_rtx is 0, this is an optional reload
6364 that we opted to ignore. */
6365 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
6366 && rld[r].reg_rtx != 0)
6368 register int nregno = REGNO (rld[r].out_reg);
6371 if (nregno < FIRST_PSEUDO_REGISTER)
6372 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
6375 reg_has_output_reload[nregno + nr] = 1;
6379 nr = HARD_REGNO_NREGS (i, rld[r].mode);
6381 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6384 if (rld[r].when_needed != RELOAD_OTHER
6385 && rld[r].when_needed != RELOAD_FOR_OUTPUT
6386 && rld[r].when_needed != RELOAD_FOR_INSN)
6392 /* Deallocate the reload register for reload R. This is called from
6393 remove_address_replacements. */
6395 deallocate_reload_reg (r)
6400 if (! rld[r].reg_rtx)
6402 regno = true_regnum (rld[r].reg_rtx);
6404 if (spill_reg_order[regno] >= 0)
6405 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6407 reload_spill_index[r] = -1;
6410 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6411 reloads of the same item for fear that we might not have enough reload
6412 registers. However, normally they will get the same reload register
6413 and hence actually need not be loaded twice.
6415 Here we check for the most common case of this phenomenon: when we have
6416 a number of reloads for the same object, each of which were allocated
6417 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6418 reload, and is not modified in the insn itself. If we find such,
6419 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6420 This will not increase the number of spill registers needed and will
6421 prevent redundant code. */
6424 merge_assigned_reloads (insn)
6429 /* Scan all the reloads looking for ones that only load values and
6430 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6431 assigned and not modified by INSN. */
6433 for (i = 0; i < n_reloads; i++)
6435 int conflicting_input = 0;
6436 int max_input_address_opnum = -1;
6437 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6439 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6440 || rld[i].out != 0 || rld[i].reg_rtx == 0
6441 || reg_set_p (rld[i].reg_rtx, insn))
6444 /* Look at all other reloads. Ensure that the only use of this
6445 reload_reg_rtx is in a reload that just loads the same value
6446 as we do. Note that any secondary reloads must be of the identical
6447 class since the values, modes, and result registers are the
6448 same, so we need not do anything with any secondary reloads. */
6450 for (j = 0; j < n_reloads; j++)
6452 if (i == j || rld[j].reg_rtx == 0
6453 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6457 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6458 && rld[j].opnum > max_input_address_opnum)
6459 max_input_address_opnum = rld[j].opnum;
6461 /* If the reload regs aren't exactly the same (e.g, different modes)
6462 or if the values are different, we can't merge this reload.
6463 But if it is an input reload, we might still merge
6464 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6466 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6467 || rld[j].out != 0 || rld[j].in == 0
6468 || ! rtx_equal_p (rld[i].in, rld[j].in))
6470 if (rld[j].when_needed != RELOAD_FOR_INPUT
6471 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6472 || rld[i].opnum > rld[j].opnum)
6473 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6475 conflicting_input = 1;
6476 if (min_conflicting_input_opnum > rld[j].opnum)
6477 min_conflicting_input_opnum = rld[j].opnum;
6481 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6482 we, in fact, found any matching reloads. */
6485 && max_input_address_opnum <= min_conflicting_input_opnum)
6487 for (j = 0; j < n_reloads; j++)
6488 if (i != j && rld[j].reg_rtx != 0
6489 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6490 && (! conflicting_input
6491 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6492 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6494 rld[i].when_needed = RELOAD_OTHER;
6496 reload_spill_index[j] = -1;
6497 transfer_replacements (i, j);
6500 /* If this is now RELOAD_OTHER, look for any reloads that load
6501 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6502 if they were for inputs, RELOAD_OTHER for outputs. Note that
6503 this test is equivalent to looking for reloads for this operand
6506 if (rld[i].when_needed == RELOAD_OTHER)
6507 for (j = 0; j < n_reloads; j++)
6509 && rld[i].when_needed != RELOAD_OTHER
6510 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6513 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6514 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6515 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6521 /* Output insns to reload values in and out of the chosen reload regs. */
6524 emit_reload_insns (chain)
6525 struct insn_chain *chain;
6527 rtx insn = chain->insn;
6530 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6531 rtx other_input_address_reload_insns = 0;
6532 rtx other_input_reload_insns = 0;
6533 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6534 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6535 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6536 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6537 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6538 rtx operand_reload_insns = 0;
6539 rtx other_operand_reload_insns = 0;
6540 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6541 rtx following_insn = NEXT_INSN (insn);
6542 rtx before_insn = PREV_INSN (insn);
6544 /* Values to be put in spill_reg_store are put here first. */
6545 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6546 HARD_REG_SET reg_reloaded_died;
6548 CLEAR_HARD_REG_SET (reg_reloaded_died);
6550 for (j = 0; j < reload_n_operands; j++)
6551 input_reload_insns[j] = input_address_reload_insns[j]
6552 = inpaddr_address_reload_insns[j]
6553 = output_reload_insns[j] = output_address_reload_insns[j]
6554 = outaddr_address_reload_insns[j]
6555 = other_output_reload_insns[j] = 0;
6557 /* Now output the instructions to copy the data into and out of the
6558 reload registers. Do these in the order that the reloads were reported,
6559 since reloads of base and index registers precede reloads of operands
6560 and the operands may need the base and index registers reloaded. */
6562 for (j = 0; j < n_reloads; j++)
6565 rtx oldequiv_reg = 0;
6566 rtx this_reload_insn = 0;
6567 int expect_occurrences = 1;
6570 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6571 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6573 old = (rld[j].in && GET_CODE (rld[j].in) == MEM
6574 ? rld[j].in_reg : rld[j].in);
6577 /* AUTO_INC reloads need to be handled even if inherited. We got an
6578 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6579 && (! reload_inherited[j] || (rld[j].out && ! rld[j].out_reg))
6580 && ! rtx_equal_p (rld[j].reg_rtx, old)
6581 && rld[j].reg_rtx != 0)
6583 register rtx reloadreg = rld[j].reg_rtx;
6585 enum machine_mode mode;
6588 /* Determine the mode to reload in.
6589 This is very tricky because we have three to choose from.
6590 There is the mode the insn operand wants (rld[J].inmode).
6591 There is the mode of the reload register RELOADREG.
6592 There is the intrinsic mode of the operand, which we could find
6593 by stripping some SUBREGs.
6594 It turns out that RELOADREG's mode is irrelevant:
6595 we can change that arbitrarily.
6597 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6598 then the reload reg may not support QImode moves, so use SImode.
6599 If foo is in memory due to spilling a pseudo reg, this is safe,
6600 because the QImode value is in the least significant part of a
6601 slot big enough for a SImode. If foo is some other sort of
6602 memory reference, then it is impossible to reload this case,
6603 so previous passes had better make sure this never happens.
6605 Then consider a one-word union which has SImode and one of its
6606 members is a float, being fetched as (SUBREG:SF union:SI).
6607 We must fetch that as SFmode because we could be loading into
6608 a float-only register. In this case OLD's mode is correct.
6610 Consider an immediate integer: it has VOIDmode. Here we need
6611 to get a mode from something else.
6613 In some cases, there is a fourth mode, the operand's
6614 containing mode. If the insn specifies a containing mode for
6615 this operand, it overrides all others.
6617 I am not sure whether the algorithm here is always right,
6618 but it does the right things in those cases. */
6620 mode = GET_MODE (old);
6621 if (mode == VOIDmode)
6622 mode = rld[j].inmode;
6624 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6625 /* If we need a secondary register for this operation, see if
6626 the value is already in a register in that class. Don't
6627 do this if the secondary register will be used as a scratch
6630 if (rld[j].secondary_in_reload >= 0
6631 && rld[j].secondary_in_icode == CODE_FOR_nothing
6634 = find_equiv_reg (old, insn,
6635 rld[rld[j].secondary_in_reload].class,
6636 -1, NULL_PTR, 0, mode);
6639 /* If reloading from memory, see if there is a register
6640 that already holds the same value. If so, reload from there.
6641 We can pass 0 as the reload_reg_p argument because
6642 any other reload has either already been emitted,
6643 in which case find_equiv_reg will see the reload-insn,
6644 or has yet to be emitted, in which case it doesn't matter
6645 because we will use this equiv reg right away. */
6647 if (oldequiv == 0 && optimize
6648 && (GET_CODE (old) == MEM
6649 || (GET_CODE (old) == REG
6650 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6651 && reg_renumber[REGNO (old)] < 0)))
6652 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6653 -1, NULL_PTR, 0, mode);
6657 int regno = true_regnum (oldequiv);
6659 /* Don't use OLDEQUIV if any other reload changes it at an
6660 earlier stage of this insn or at this stage. */
6661 if (! reload_reg_free_for_value_p (regno, rld[j].opnum,
6663 rld[j].in, const0_rtx, j,
6667 /* If it is no cheaper to copy from OLDEQUIV into the
6668 reload register than it would be to move from memory,
6669 don't use it. Likewise, if we need a secondary register
6673 && ((REGNO_REG_CLASS (regno) != rld[j].class
6674 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6676 >= MEMORY_MOVE_COST (mode, rld[j].class, 1)))
6677 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6678 || (SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6682 #ifdef SECONDARY_MEMORY_NEEDED
6683 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6691 /* delete_output_reload is only invoked properly if old contains
6692 the original pseudo register. Since this is replaced with a
6693 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6694 find the pseudo in RELOAD_IN_REG. */
6696 && reload_override_in[j]
6697 && GET_CODE (rld[j].in_reg) == REG)
6700 old = rld[j].in_reg;
6704 else if (GET_CODE (oldequiv) == REG)
6705 oldequiv_reg = oldequiv;
6706 else if (GET_CODE (oldequiv) == SUBREG)
6707 oldequiv_reg = SUBREG_REG (oldequiv);
6709 /* If we are reloading from a register that was recently stored in
6710 with an output-reload, see if we can prove there was
6711 actually no need to store the old value in it. */
6713 if (optimize && GET_CODE (oldequiv) == REG
6714 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6715 && spill_reg_store[REGNO (oldequiv)]
6716 && GET_CODE (old) == REG
6717 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6718 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6720 delete_output_reload (insn, j, REGNO (oldequiv));
6722 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6723 then load RELOADREG from OLDEQUIV. Note that we cannot use
6724 gen_lowpart_common since it can do the wrong thing when
6725 RELOADREG has a multi-word mode. Note that RELOADREG
6726 must always be a REG here. */
6728 if (GET_MODE (reloadreg) != mode)
6729 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6730 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6731 oldequiv = SUBREG_REG (oldequiv);
6732 if (GET_MODE (oldequiv) != VOIDmode
6733 && mode != GET_MODE (oldequiv))
6734 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6736 /* Switch to the right place to emit the reload insns. */
6737 switch (rld[j].when_needed)
6740 where = &other_input_reload_insns;
6742 case RELOAD_FOR_INPUT:
6743 where = &input_reload_insns[rld[j].opnum];
6745 case RELOAD_FOR_INPUT_ADDRESS:
6746 where = &input_address_reload_insns[rld[j].opnum];
6748 case RELOAD_FOR_INPADDR_ADDRESS:
6749 where = &inpaddr_address_reload_insns[rld[j].opnum];
6751 case RELOAD_FOR_OUTPUT_ADDRESS:
6752 where = &output_address_reload_insns[rld[j].opnum];
6754 case RELOAD_FOR_OUTADDR_ADDRESS:
6755 where = &outaddr_address_reload_insns[rld[j].opnum];
6757 case RELOAD_FOR_OPERAND_ADDRESS:
6758 where = &operand_reload_insns;
6760 case RELOAD_FOR_OPADDR_ADDR:
6761 where = &other_operand_reload_insns;
6763 case RELOAD_FOR_OTHER_ADDRESS:
6764 where = &other_input_address_reload_insns;
6770 push_to_sequence (*where);
6773 /* Auto-increment addresses must be reloaded in a special way. */
6774 if (rld[j].out && ! rld[j].out_reg)
6776 /* We are not going to bother supporting the case where a
6777 incremented register can't be copied directly from
6778 OLDEQUIV since this seems highly unlikely. */
6779 if (rld[j].secondary_in_reload >= 0)
6782 if (reload_inherited[j])
6783 oldequiv = reloadreg;
6785 old = XEXP (rld[j].in_reg, 0);
6787 if (optimize && GET_CODE (oldequiv) == REG
6788 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6789 && spill_reg_store[REGNO (oldequiv)]
6790 && GET_CODE (old) == REG
6791 && (dead_or_set_p (insn,
6792 spill_reg_stored_to[REGNO (oldequiv)])
6793 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6795 delete_output_reload (insn, j, REGNO (oldequiv));
6797 /* Prevent normal processing of this reload. */
6799 /* Output a special code sequence for this case. */
6800 new_spill_reg_store[REGNO (reloadreg)]
6801 = inc_for_reload (reloadreg, oldequiv, rld[j].out,
6805 /* If we are reloading a pseudo-register that was set by the previous
6806 insn, see if we can get rid of that pseudo-register entirely
6807 by redirecting the previous insn into our reload register. */
6809 else if (optimize && GET_CODE (old) == REG
6810 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6811 && dead_or_set_p (insn, old)
6812 /* This is unsafe if some other reload
6813 uses the same reg first. */
6814 && reload_reg_free_for_value_p (REGNO (reloadreg),
6820 rtx temp = PREV_INSN (insn);
6821 while (temp && GET_CODE (temp) == NOTE)
6822 temp = PREV_INSN (temp);
6824 && GET_CODE (temp) == INSN
6825 && GET_CODE (PATTERN (temp)) == SET
6826 && SET_DEST (PATTERN (temp)) == old
6827 /* Make sure we can access insn_operand_constraint. */
6828 && asm_noperands (PATTERN (temp)) < 0
6829 /* This is unsafe if prev insn rejects our reload reg. */
6830 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6832 /* This is unsafe if operand occurs more than once in current
6833 insn. Perhaps some occurrences aren't reloaded. */
6834 && count_occurrences (PATTERN (insn), old) == 1
6835 /* Don't risk splitting a matching pair of operands. */
6836 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6838 /* Store into the reload register instead of the pseudo. */
6839 SET_DEST (PATTERN (temp)) = reloadreg;
6841 /* If the previous insn is an output reload, the source is
6842 a reload register, and its spill_reg_store entry will
6843 contain the previous destination. This is now
6845 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6846 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6848 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6849 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6852 /* If these are the only uses of the pseudo reg,
6853 pretend for GDB it lives in the reload reg we used. */
6854 if (REG_N_DEATHS (REGNO (old)) == 1
6855 && REG_N_SETS (REGNO (old)) == 1)
6857 reg_renumber[REGNO (old)] = REGNO (rld[j].reg_rtx);
6858 alter_reg (REGNO (old), -1);
6864 /* We can't do that, so output an insn to load RELOADREG. */
6868 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6869 rtx second_reload_reg = 0;
6870 enum insn_code icode;
6872 /* If we have a secondary reload, pick up the secondary register
6873 and icode, if any. If OLDEQUIV and OLD are different or
6874 if this is an in-out reload, recompute whether or not we
6875 still need a secondary register and what the icode should
6876 be. If we still need a secondary register and the class or
6877 icode is different, go back to reloading from OLD if using
6878 OLDEQUIV means that we got the wrong type of register. We
6879 cannot have different class or icode due to an in-out reload
6880 because we don't make such reloads when both the input and
6881 output need secondary reload registers. */
6883 if (rld[j].secondary_in_reload >= 0)
6885 int secondary_reload = rld[j].secondary_in_reload;
6886 rtx real_oldequiv = oldequiv;
6890 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6891 and similarly for OLD.
6892 See comments in get_secondary_reload in reload.c. */
6893 /* If it is a pseudo that cannot be replaced with its
6894 equivalent MEM, we must fall back to reload_in, which
6895 will have all the necessary substitutions registered.
6896 Likewise for a pseudo that can't be replaced with its
6897 equivalent constant.
6899 Take extra care for subregs of such pseudos. Note that
6900 we cannot use reg_equiv_mem in this case because it is
6901 not in the right mode. */
6904 if (GET_CODE (tmp) == SUBREG)
6905 tmp = SUBREG_REG (tmp);
6906 if (GET_CODE (tmp) == REG
6907 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6908 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6909 || reg_equiv_constant[REGNO (tmp)] != 0))
6911 if (! reg_equiv_mem[REGNO (tmp)]
6912 || num_not_at_initial_offset
6913 || GET_CODE (oldequiv) == SUBREG)
6914 real_oldequiv = rld[j].in;
6916 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6920 if (GET_CODE (tmp) == SUBREG)
6921 tmp = SUBREG_REG (tmp);
6922 if (GET_CODE (tmp) == REG
6923 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6924 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6925 || reg_equiv_constant[REGNO (tmp)] != 0))
6927 if (! reg_equiv_mem[REGNO (tmp)]
6928 || num_not_at_initial_offset
6929 || GET_CODE (old) == SUBREG)
6930 real_old = rld[j].in;
6932 real_old = reg_equiv_mem[REGNO (tmp)];
6935 second_reload_reg = rld[secondary_reload].reg_rtx;
6936 icode = rld[j].secondary_in_icode;
6938 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6939 || (rld[j].in != 0 && rld[j].out != 0))
6941 enum reg_class new_class
6942 = SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6943 mode, real_oldequiv);
6945 if (new_class == NO_REGS)
6946 second_reload_reg = 0;
6949 enum insn_code new_icode;
6950 enum machine_mode new_mode;
6952 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6953 REGNO (second_reload_reg)))
6954 oldequiv = old, real_oldequiv = real_old;
6957 new_icode = reload_in_optab[(int) mode];
6958 if (new_icode != CODE_FOR_nothing
6959 && ((insn_data[(int) new_icode].operand[0].predicate
6960 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6962 || (insn_data[(int) new_icode].operand[1].predicate
6963 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6964 (real_oldequiv, mode)))))
6965 new_icode = CODE_FOR_nothing;
6967 if (new_icode == CODE_FOR_nothing)
6970 new_mode = insn_data[(int) new_icode].operand[2].mode;
6972 if (GET_MODE (second_reload_reg) != new_mode)
6974 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6976 oldequiv = old, real_oldequiv = real_old;
6979 = gen_rtx_REG (new_mode,
6980 REGNO (second_reload_reg));
6986 /* If we still need a secondary reload register, check
6987 to see if it is being used as a scratch or intermediate
6988 register and generate code appropriately. If we need
6989 a scratch register, use REAL_OLDEQUIV since the form of
6990 the insn may depend on the actual address if it is
6993 if (second_reload_reg)
6995 if (icode != CODE_FOR_nothing)
6997 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6998 second_reload_reg));
7003 /* See if we need a scratch register to load the
7004 intermediate register (a tertiary reload). */
7005 enum insn_code tertiary_icode
7006 = rld[secondary_reload].secondary_in_icode;
7008 if (tertiary_icode != CODE_FOR_nothing)
7010 rtx third_reload_reg
7011 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
7013 emit_insn ((GEN_FCN (tertiary_icode)
7014 (second_reload_reg, real_oldequiv,
7015 third_reload_reg)));
7018 gen_reload (second_reload_reg, real_oldequiv,
7020 rld[j].when_needed);
7022 oldequiv = second_reload_reg;
7028 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7030 rtx real_oldequiv = oldequiv;
7032 if ((GET_CODE (oldequiv) == REG
7033 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7034 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7035 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7036 || (GET_CODE (oldequiv) == SUBREG
7037 && GET_CODE (SUBREG_REG (oldequiv)) == REG
7038 && (REGNO (SUBREG_REG (oldequiv))
7039 >= FIRST_PSEUDO_REGISTER)
7040 && ((reg_equiv_memory_loc
7041 [REGNO (SUBREG_REG (oldequiv))] != 0)
7042 || (reg_equiv_constant
7043 [REGNO (SUBREG_REG (oldequiv))] != 0))))
7044 real_oldequiv = rld[j].in;
7045 gen_reload (reloadreg, real_oldequiv, rld[j].opnum,
7046 rld[j].when_needed);
7051 this_reload_insn = get_last_insn ();
7052 /* End this sequence. */
7053 *where = get_insns ();
7056 /* Update reload_override_in so that delete_address_reloads_1
7057 can see the actual register usage. */
7059 reload_override_in[j] = oldequiv;
7062 /* When inheriting a wider reload, we have a MEM in rld[j].in,
7063 e.g. inheriting a SImode output reload for
7064 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7065 if (optimize && reload_inherited[j] && rld[j].in
7066 && GET_CODE (rld[j].in) == MEM
7067 && GET_CODE (rld[j].in_reg) == MEM
7068 && reload_spill_index[j] >= 0
7069 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7072 = count_occurrences (PATTERN (insn), rld[j].in) == 1 ? 0 : -1;
7074 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7077 /* If we are reloading a register that was recently stored in with an
7078 output-reload, see if we can prove there was
7079 actually no need to store the old value in it. */
7082 && (reload_inherited[j] || reload_override_in[j])
7084 && GET_CODE (rld[j].reg_rtx) == REG
7085 && spill_reg_store[REGNO (rld[j].reg_rtx)] != 0
7087 /* There doesn't seem to be any reason to restrict this to pseudos
7088 and doing so loses in the case where we are copying from a
7089 register of the wrong class. */
7090 && (REGNO (spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
7091 >= FIRST_PSEUDO_REGISTER)
7093 /* The insn might have already some references to stackslots
7094 replaced by MEMs, while reload_out_reg still names the
7096 && (dead_or_set_p (insn,
7097 spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
7098 || rtx_equal_p (spill_reg_stored_to[REGNO (rld[j].reg_rtx)],
7100 delete_output_reload (insn, j, REGNO (rld[j].reg_rtx));
7102 /* Input-reloading is done. Now do output-reloading,
7103 storing the value from the reload-register after the main insn
7104 if rld[j].out is nonzero.
7106 ??? At some point we need to support handling output reloads of
7107 JUMP_INSNs or insns that set cc0. */
7109 /* If this is an output reload that stores something that is
7110 not loaded in this same reload, see if we can eliminate a previous
7113 rtx pseudo = rld[j].out_reg;
7116 && GET_CODE (pseudo) == REG
7117 && ! rtx_equal_p (rld[j].in_reg, pseudo)
7118 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7119 && reg_last_reload_reg[REGNO (pseudo)])
7121 int pseudo_no = REGNO (pseudo);
7122 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7124 /* We don't need to test full validity of last_regno for
7125 inherit here; we only want to know if the store actually
7126 matches the pseudo. */
7127 if (reg_reloaded_contents[last_regno] == pseudo_no
7128 && spill_reg_store[last_regno]
7129 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7130 delete_output_reload (insn, j, last_regno);
7134 old = rld[j].out_reg;
7136 && rld[j].reg_rtx != old
7137 && rld[j].reg_rtx != 0)
7139 register rtx reloadreg = rld[j].reg_rtx;
7140 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7141 register rtx second_reloadreg = 0;
7144 enum machine_mode mode;
7147 /* An output operand that dies right away does need a reload,
7148 but need not be copied from it. Show the new location in the
7150 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7151 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7153 XEXP (note, 0) = rld[j].reg_rtx;
7156 /* Likewise for a SUBREG of an operand that dies. */
7157 else if (GET_CODE (old) == SUBREG
7158 && GET_CODE (SUBREG_REG (old)) == REG
7159 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7162 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7166 else if (GET_CODE (old) == SCRATCH)
7167 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7168 but we don't want to make an output reload. */
7172 /* Strip off of OLD any size-increasing SUBREGs such as
7173 (SUBREG:SI foo:QI 0). */
7175 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7176 && (GET_MODE_SIZE (GET_MODE (old))
7177 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7178 old = SUBREG_REG (old);
7181 /* If is a JUMP_INSN, we can't support output reloads yet. */
7182 if (GET_CODE (insn) == JUMP_INSN)
7185 if (rld[j].when_needed == RELOAD_OTHER)
7188 push_to_sequence (output_reload_insns[rld[j].opnum]);
7192 /* Determine the mode to reload in.
7193 See comments above (for input reloading). */
7195 mode = GET_MODE (old);
7196 if (mode == VOIDmode)
7198 /* VOIDmode should never happen for an output. */
7199 if (asm_noperands (PATTERN (insn)) < 0)
7200 /* It's the compiler's fault. */
7201 fatal_insn ("VOIDmode on an output", insn);
7202 error_for_asm (insn, "output operand is constant in `asm'");
7203 /* Prevent crash--use something we know is valid. */
7205 old = gen_rtx_REG (mode, REGNO (reloadreg));
7208 if (GET_MODE (reloadreg) != mode)
7209 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7211 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7213 /* If we need two reload regs, set RELOADREG to the intermediate
7214 one, since it will be stored into OLD. We might need a secondary
7215 register only for an input reload, so check again here. */
7217 if (rld[j].secondary_out_reload >= 0)
7221 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7222 && reg_equiv_mem[REGNO (old)] != 0)
7223 real_old = reg_equiv_mem[REGNO (old)];
7225 if((SECONDARY_OUTPUT_RELOAD_CLASS (rld[j].class,
7229 second_reloadreg = reloadreg;
7230 reloadreg = rld[rld[j].secondary_out_reload].reg_rtx;
7232 /* See if RELOADREG is to be used as a scratch register
7233 or as an intermediate register. */
7234 if (rld[j].secondary_out_icode != CODE_FOR_nothing)
7236 emit_insn ((GEN_FCN (rld[j].secondary_out_icode)
7237 (real_old, second_reloadreg, reloadreg)));
7242 /* See if we need both a scratch and intermediate reload
7245 int secondary_reload = rld[j].secondary_out_reload;
7246 enum insn_code tertiary_icode
7247 = rld[secondary_reload].secondary_out_icode;
7249 if (GET_MODE (reloadreg) != mode)
7250 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7252 if (tertiary_icode != CODE_FOR_nothing)
7255 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
7258 /* Copy primary reload reg to secondary reload reg.
7259 (Note that these have been swapped above, then
7260 secondary reload reg to OLD using our insn. */
7262 /* If REAL_OLD is a paradoxical SUBREG, remove it
7263 and try to put the opposite SUBREG on
7265 if (GET_CODE (real_old) == SUBREG
7266 && (GET_MODE_SIZE (GET_MODE (real_old))
7267 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7268 && 0 != (tem = gen_lowpart_common
7269 (GET_MODE (SUBREG_REG (real_old)),
7271 real_old = SUBREG_REG (real_old), reloadreg = tem;
7273 gen_reload (reloadreg, second_reloadreg,
7274 rld[j].opnum, rld[j].when_needed);
7275 emit_insn ((GEN_FCN (tertiary_icode)
7276 (real_old, reloadreg, third_reloadreg)));
7281 /* Copy between the reload regs here and then to
7284 gen_reload (reloadreg, second_reloadreg,
7285 rld[j].opnum, rld[j].when_needed);
7291 /* Output the last reload insn. */
7296 /* Don't output the last reload if OLD is not the dest of
7297 INSN and is in the src and is clobbered by INSN. */
7298 if (! flag_expensive_optimizations
7299 || GET_CODE (old) != REG
7300 || !(set = single_set (insn))
7301 || rtx_equal_p (old, SET_DEST (set))
7302 || !reg_mentioned_p (old, SET_SRC (set))
7303 || !regno_clobbered_p (REGNO (old), insn))
7304 gen_reload (old, reloadreg, rld[j].opnum,
7305 rld[j].when_needed);
7308 /* Look at all insns we emitted, just to be safe. */
7309 for (p = get_insns (); p; p = NEXT_INSN (p))
7310 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7312 rtx pat = PATTERN (p);
7314 /* If this output reload doesn't come from a spill reg,
7315 clear any memory of reloaded copies of the pseudo reg.
7316 If this output reload comes from a spill reg,
7317 reg_has_output_reload will make this do nothing. */
7318 note_stores (pat, forget_old_reloads_1, NULL);
7320 if (reg_mentioned_p (rld[j].reg_rtx, pat))
7322 rtx set = single_set (insn);
7323 if (reload_spill_index[j] < 0
7325 && SET_SRC (set) == rld[j].reg_rtx)
7327 int src = REGNO (SET_SRC (set));
7329 reload_spill_index[j] = src;
7330 SET_HARD_REG_BIT (reg_is_output_reload, src);
7331 if (find_regno_note (insn, REG_DEAD, src))
7332 SET_HARD_REG_BIT (reg_reloaded_died, src);
7334 if (REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7336 int s = rld[j].secondary_out_reload;
7337 set = single_set (p);
7338 /* If this reload copies only to the secondary reload
7339 register, the secondary reload does the actual
7341 if (s >= 0 && set == NULL_RTX)
7342 ; /* We can't tell what function the secondary reload
7343 has and where the actual store to the pseudo is
7344 made; leave new_spill_reg_store alone. */
7346 && SET_SRC (set) == rld[j].reg_rtx
7347 && SET_DEST (set) == rld[s].reg_rtx)
7349 /* Usually the next instruction will be the
7350 secondary reload insn; if we can confirm
7351 that it is, setting new_spill_reg_store to
7352 that insn will allow an extra optimization. */
7353 rtx s_reg = rld[s].reg_rtx;
7354 rtx next = NEXT_INSN (p);
7355 rld[s].out = rld[j].out;
7356 rld[s].out_reg = rld[j].out_reg;
7357 set = single_set (next);
7358 if (set && SET_SRC (set) == s_reg
7359 && ! new_spill_reg_store[REGNO (s_reg)])
7361 SET_HARD_REG_BIT (reg_is_output_reload,
7363 new_spill_reg_store[REGNO (s_reg)] = next;
7367 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = p;
7372 if (rld[j].when_needed == RELOAD_OTHER)
7374 emit_insns (other_output_reload_insns[rld[j].opnum]);
7375 other_output_reload_insns[rld[j].opnum] = get_insns ();
7378 output_reload_insns[rld[j].opnum] = get_insns ();
7384 /* Now write all the insns we made for reloads in the order expected by
7385 the allocation functions. Prior to the insn being reloaded, we write
7386 the following reloads:
7388 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7390 RELOAD_OTHER reloads.
7392 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7393 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7394 RELOAD_FOR_INPUT reload for the operand.
7396 RELOAD_FOR_OPADDR_ADDRS reloads.
7398 RELOAD_FOR_OPERAND_ADDRESS reloads.
7400 After the insn being reloaded, we write the following:
7402 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7403 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7404 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7405 reloads for the operand. The RELOAD_OTHER output reloads are
7406 output in descending order by reload number. */
7408 emit_insns_before (other_input_address_reload_insns, insn);
7409 emit_insns_before (other_input_reload_insns, insn);
7411 for (j = 0; j < reload_n_operands; j++)
7413 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7414 emit_insns_before (input_address_reload_insns[j], insn);
7415 emit_insns_before (input_reload_insns[j], insn);
7418 emit_insns_before (other_operand_reload_insns, insn);
7419 emit_insns_before (operand_reload_insns, insn);
7421 for (j = 0; j < reload_n_operands; j++)
7423 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7424 emit_insns_before (output_address_reload_insns[j], following_insn);
7425 emit_insns_before (output_reload_insns[j], following_insn);
7426 emit_insns_before (other_output_reload_insns[j], following_insn);
7429 /* Keep basic block info up to date. */
7432 if (BLOCK_HEAD (chain->block) == insn)
7433 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7434 if (BLOCK_END (chain->block) == insn)
7435 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7438 /* For all the spill regs newly reloaded in this instruction,
7439 record what they were reloaded from, so subsequent instructions
7440 can inherit the reloads.
7442 Update spill_reg_store for the reloads of this insn.
7443 Copy the elements that were updated in the loop above. */
7445 for (j = 0; j < n_reloads; j++)
7447 register int r = reload_order[j];
7448 register int i = reload_spill_index[r];
7450 /* If this is a non-inherited input reload from a pseudo, we must
7451 clear any memory of a previous store to the same pseudo. Only do
7452 something if there will not be an output reload for the pseudo
7454 if (rld[r].in_reg != 0
7455 && ! (reload_inherited[r] || reload_override_in[r]))
7457 rtx reg = rld[r].in_reg;
7459 if (GET_CODE (reg) == SUBREG)
7460 reg = SUBREG_REG (reg);
7462 if (GET_CODE (reg) == REG
7463 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7464 && ! reg_has_output_reload[REGNO (reg)])
7466 int nregno = REGNO (reg);
7468 if (reg_last_reload_reg[nregno])
7470 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7472 if (reg_reloaded_contents[last_regno] == nregno)
7473 spill_reg_store[last_regno] = 0;
7478 /* I is nonneg if this reload used a register.
7479 If rld[r].reg_rtx is 0, this is an optional reload
7480 that we opted to ignore. */
7482 if (i >= 0 && rld[r].reg_rtx != 0)
7485 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7487 int part_reaches_end = 0;
7488 int all_reaches_end = 1;
7490 /* For a multi register reload, we need to check if all or part
7491 of the value lives to the end. */
7492 for (k = 0; k < nr; k++)
7494 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7495 rld[r].when_needed))
7496 part_reaches_end = 1;
7498 all_reaches_end = 0;
7501 /* Ignore reloads that don't reach the end of the insn in
7503 if (all_reaches_end)
7505 /* First, clear out memory of what used to be in this spill reg.
7506 If consecutive registers are used, clear them all. */
7508 for (k = 0; k < nr; k++)
7509 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7511 /* Maybe the spill reg contains a copy of reload_out. */
7513 && (GET_CODE (rld[r].out) == REG
7517 || GET_CODE (rld[r].out_reg) == REG))
7519 rtx out = (GET_CODE (rld[r].out) == REG
7523 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7524 register int nregno = REGNO (out);
7525 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7526 : HARD_REGNO_NREGS (nregno,
7527 GET_MODE (rld[r].reg_rtx)));
7529 spill_reg_store[i] = new_spill_reg_store[i];
7530 spill_reg_stored_to[i] = out;
7531 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7533 /* If NREGNO is a hard register, it may occupy more than
7534 one register. If it does, say what is in the
7535 rest of the registers assuming that both registers
7536 agree on how many words the object takes. If not,
7537 invalidate the subsequent registers. */
7539 if (nregno < FIRST_PSEUDO_REGISTER)
7540 for (k = 1; k < nnr; k++)
7541 reg_last_reload_reg[nregno + k]
7543 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7544 REGNO (rld[r].reg_rtx) + k)
7547 /* Now do the inverse operation. */
7548 for (k = 0; k < nr; k++)
7550 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7551 reg_reloaded_contents[i + k]
7552 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7555 reg_reloaded_insn[i + k] = insn;
7556 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7560 /* Maybe the spill reg contains a copy of reload_in. Only do
7561 something if there will not be an output reload for
7562 the register being reloaded. */
7563 else if (rld[r].out_reg == 0
7565 && ((GET_CODE (rld[r].in) == REG
7566 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7567 && ! reg_has_output_reload[REGNO (rld[r].in)])
7568 || (GET_CODE (rld[r].in_reg) == REG
7569 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7570 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7572 register int nregno;
7575 if (GET_CODE (rld[r].in) == REG
7576 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7577 nregno = REGNO (rld[r].in);
7578 else if (GET_CODE (rld[r].in_reg) == REG)
7579 nregno = REGNO (rld[r].in_reg);
7581 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7583 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7584 : HARD_REGNO_NREGS (nregno,
7585 GET_MODE (rld[r].reg_rtx)));
7587 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7589 if (nregno < FIRST_PSEUDO_REGISTER)
7590 for (k = 1; k < nnr; k++)
7591 reg_last_reload_reg[nregno + k]
7593 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7594 REGNO (rld[r].reg_rtx) + k)
7597 /* Unless we inherited this reload, show we haven't
7598 recently done a store.
7599 Previous stores of inherited auto_inc expressions
7600 also have to be discarded. */
7601 if (! reload_inherited[r]
7602 || (rld[r].out && ! rld[r].out_reg))
7603 spill_reg_store[i] = 0;
7605 for (k = 0; k < nr; k++)
7607 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7608 reg_reloaded_contents[i + k]
7609 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7612 reg_reloaded_insn[i + k] = insn;
7613 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7618 /* However, if part of the reload reaches the end, then we must
7619 invalidate the old info for the part that survives to the end. */
7620 else if (part_reaches_end)
7622 for (k = 0; k < nr; k++)
7623 if (reload_reg_reaches_end_p (i + k,
7625 rld[r].when_needed))
7626 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7630 /* The following if-statement was #if 0'd in 1.34 (or before...).
7631 It's reenabled in 1.35 because supposedly nothing else
7632 deals with this problem. */
7634 /* If a register gets output-reloaded from a non-spill register,
7635 that invalidates any previous reloaded copy of it.
7636 But forget_old_reloads_1 won't get to see it, because
7637 it thinks only about the original insn. So invalidate it here. */
7638 if (i < 0 && rld[r].out != 0
7639 && (GET_CODE (rld[r].out) == REG
7640 || (GET_CODE (rld[r].out) == MEM
7641 && GET_CODE (rld[r].out_reg) == REG)))
7643 rtx out = (GET_CODE (rld[r].out) == REG
7644 ? rld[r].out : rld[r].out_reg);
7645 register int nregno = REGNO (out);
7646 if (nregno >= FIRST_PSEUDO_REGISTER)
7648 rtx src_reg, store_insn = NULL_RTX;
7650 reg_last_reload_reg[nregno] = 0;
7652 /* If we can find a hard register that is stored, record
7653 the storing insn so that we may delete this insn with
7654 delete_output_reload. */
7655 src_reg = rld[r].reg_rtx;
7657 /* If this is an optional reload, try to find the source reg
7658 from an input reload. */
7661 rtx set = single_set (insn);
7662 if (set && SET_DEST (set) == rld[r].out)
7666 src_reg = SET_SRC (set);
7668 for (k = 0; k < n_reloads; k++)
7670 if (rld[k].in == src_reg)
7672 src_reg = rld[k].reg_rtx;
7679 store_insn = new_spill_reg_store[REGNO (src_reg)];
7680 if (src_reg && GET_CODE (src_reg) == REG
7681 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7683 int src_regno = REGNO (src_reg);
7684 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7685 /* The place where to find a death note varies with
7686 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7687 necessarily checked exactly in the code that moves
7688 notes, so just check both locations. */
7689 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7691 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7694 spill_reg_store[src_regno + nr] = store_insn;
7695 spill_reg_stored_to[src_regno + nr] = out;
7696 reg_reloaded_contents[src_regno + nr] = nregno;
7697 reg_reloaded_insn[src_regno + nr] = store_insn;
7698 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7699 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7700 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7702 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7704 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7706 reg_last_reload_reg[nregno] = src_reg;
7711 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7713 while (num_regs-- > 0)
7714 reg_last_reload_reg[nregno + num_regs] = 0;
7718 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7721 /* Emit code to perform a reload from IN (which may be a reload register) to
7722 OUT (which may also be a reload register). IN or OUT is from operand
7723 OPNUM with reload type TYPE.
7725 Returns first insn emitted. */
7728 gen_reload (out, in, opnum, type)
7732 enum reload_type type;
7734 rtx last = get_last_insn ();
7737 /* If IN is a paradoxical SUBREG, remove it and try to put the
7738 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7739 if (GET_CODE (in) == SUBREG
7740 && (GET_MODE_SIZE (GET_MODE (in))
7741 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7742 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7743 in = SUBREG_REG (in), out = tem;
7744 else if (GET_CODE (out) == SUBREG
7745 && (GET_MODE_SIZE (GET_MODE (out))
7746 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7747 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7748 out = SUBREG_REG (out), in = tem;
7750 /* How to do this reload can get quite tricky. Normally, we are being
7751 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7752 register that didn't get a hard register. In that case we can just
7753 call emit_move_insn.
7755 We can also be asked to reload a PLUS that adds a register or a MEM to
7756 another register, constant or MEM. This can occur during frame pointer
7757 elimination and while reloading addresses. This case is handled by
7758 trying to emit a single insn to perform the add. If it is not valid,
7759 we use a two insn sequence.
7761 Finally, we could be called to handle an 'o' constraint by putting
7762 an address into a register. In that case, we first try to do this
7763 with a named pattern of "reload_load_address". If no such pattern
7764 exists, we just emit a SET insn and hope for the best (it will normally
7765 be valid on machines that use 'o').
7767 This entire process is made complex because reload will never
7768 process the insns we generate here and so we must ensure that
7769 they will fit their constraints and also by the fact that parts of
7770 IN might be being reloaded separately and replaced with spill registers.
7771 Because of this, we are, in some sense, just guessing the right approach
7772 here. The one listed above seems to work.
7774 ??? At some point, this whole thing needs to be rethought. */
7776 if (GET_CODE (in) == PLUS
7777 && (GET_CODE (XEXP (in, 0)) == REG
7778 || GET_CODE (XEXP (in, 0)) == SUBREG
7779 || GET_CODE (XEXP (in, 0)) == MEM)
7780 && (GET_CODE (XEXP (in, 1)) == REG
7781 || GET_CODE (XEXP (in, 1)) == SUBREG
7782 || CONSTANT_P (XEXP (in, 1))
7783 || GET_CODE (XEXP (in, 1)) == MEM))
7785 /* We need to compute the sum of a register or a MEM and another
7786 register, constant, or MEM, and put it into the reload
7787 register. The best possible way of doing this is if the machine
7788 has a three-operand ADD insn that accepts the required operands.
7790 The simplest approach is to try to generate such an insn and see if it
7791 is recognized and matches its constraints. If so, it can be used.
7793 It might be better not to actually emit the insn unless it is valid,
7794 but we need to pass the insn as an operand to `recog' and
7795 `extract_insn' and it is simpler to emit and then delete the insn if
7796 not valid than to dummy things up. */
7798 rtx op0, op1, tem, insn;
7801 op0 = find_replacement (&XEXP (in, 0));
7802 op1 = find_replacement (&XEXP (in, 1));
7804 /* Since constraint checking is strict, commutativity won't be
7805 checked, so we need to do that here to avoid spurious failure
7806 if the add instruction is two-address and the second operand
7807 of the add is the same as the reload reg, which is frequently
7808 the case. If the insn would be A = B + A, rearrange it so
7809 it will be A = A + B as constrain_operands expects. */
7811 if (GET_CODE (XEXP (in, 1)) == REG
7812 && REGNO (out) == REGNO (XEXP (in, 1)))
7813 tem = op0, op0 = op1, op1 = tem;
7815 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7816 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7818 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7819 code = recog_memoized (insn);
7823 extract_insn (insn);
7824 /* We want constrain operands to treat this insn strictly in
7825 its validity determination, i.e., the way it would after reload
7827 if (constrain_operands (1))
7831 delete_insns_since (last);
7833 /* If that failed, we must use a conservative two-insn sequence.
7835 Use a move to copy one operand into the reload register. Prefer
7836 to reload a constant, MEM or pseudo since the move patterns can
7837 handle an arbitrary operand. If OP1 is not a constant, MEM or
7838 pseudo and OP1 is not a valid operand for an add instruction, then
7841 After reloading one of the operands into the reload register, add
7842 the reload register to the output register.
7844 If there is another way to do this for a specific machine, a
7845 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7848 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7850 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7851 || (GET_CODE (op1) == REG
7852 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7853 || (code != CODE_FOR_nothing
7854 && ! ((*insn_data[code].operand[2].predicate)
7855 (op1, insn_data[code].operand[2].mode))))
7856 tem = op0, op0 = op1, op1 = tem;
7858 gen_reload (out, op0, opnum, type);
7860 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7861 This fixes a problem on the 32K where the stack pointer cannot
7862 be used as an operand of an add insn. */
7864 if (rtx_equal_p (op0, op1))
7867 insn = emit_insn (gen_add2_insn (out, op1));
7869 /* If that failed, copy the address register to the reload register.
7870 Then add the constant to the reload register. */
7872 code = recog_memoized (insn);
7876 extract_insn (insn);
7877 /* We want constrain operands to treat this insn strictly in
7878 its validity determination, i.e., the way it would after reload
7880 if (constrain_operands (1))
7882 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7884 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7889 delete_insns_since (last);
7891 gen_reload (out, op1, opnum, type);
7892 insn = emit_insn (gen_add2_insn (out, op0));
7893 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7896 #ifdef SECONDARY_MEMORY_NEEDED
7897 /* If we need a memory location to do the move, do it that way. */
7898 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7899 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7900 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7901 REGNO_REG_CLASS (REGNO (out)),
7904 /* Get the memory to use and rewrite both registers to its mode. */
7905 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7907 if (GET_MODE (loc) != GET_MODE (out))
7908 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7910 if (GET_MODE (loc) != GET_MODE (in))
7911 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7913 gen_reload (loc, in, opnum, type);
7914 gen_reload (out, loc, opnum, type);
7918 /* If IN is a simple operand, use gen_move_insn. */
7919 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7920 emit_insn (gen_move_insn (out, in));
7922 #ifdef HAVE_reload_load_address
7923 else if (HAVE_reload_load_address)
7924 emit_insn (gen_reload_load_address (out, in));
7927 /* Otherwise, just write (set OUT IN) and hope for the best. */
7929 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7931 /* Return the first insn emitted.
7932 We can not just return get_last_insn, because there may have
7933 been multiple instructions emitted. Also note that gen_move_insn may
7934 emit more than one insn itself, so we can not assume that there is one
7935 insn emitted per emit_insn_before call. */
7937 return last ? NEXT_INSN (last) : get_insns ();
7940 /* Delete a previously made output-reload
7941 whose result we now believe is not needed.
7942 First we double-check.
7944 INSN is the insn now being processed.
7945 LAST_RELOAD_REG is the hard register number for which we want to delete
7946 the last output reload.
7947 J is the reload-number that originally used REG. The caller has made
7948 certain that reload J doesn't use REG any longer for input. */
7951 delete_output_reload (insn, j, last_reload_reg)
7954 int last_reload_reg;
7956 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7957 rtx reg = spill_reg_stored_to[last_reload_reg];
7960 int n_inherited = 0;
7964 /* Get the raw pseudo-register referred to. */
7966 while (GET_CODE (reg) == SUBREG)
7967 reg = SUBREG_REG (reg);
7968 substed = reg_equiv_memory_loc[REGNO (reg)];
7970 /* This is unsafe if the operand occurs more often in the current
7971 insn than it is inherited. */
7972 for (k = n_reloads - 1; k >= 0; k--)
7974 rtx reg2 = rld[k].in;
7977 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7978 reg2 = rld[k].in_reg;
7980 if (rld[k].out && ! rld[k].out_reg)
7981 reg2 = XEXP (rld[k].in_reg, 0);
7983 while (GET_CODE (reg2) == SUBREG)
7984 reg2 = SUBREG_REG (reg2);
7985 if (rtx_equal_p (reg2, reg))
7987 if (reload_inherited[k] || reload_override_in[k] || k == j)
7990 reg2 = rld[k].out_reg;
7993 while (GET_CODE (reg2) == SUBREG)
7994 reg2 = XEXP (reg2, 0);
7995 if (rtx_equal_p (reg2, reg))
8002 n_occurrences = count_occurrences (PATTERN (insn), reg);
8004 n_occurrences += count_occurrences (PATTERN (insn), substed);
8005 if (n_occurrences > n_inherited)
8008 /* If the pseudo-reg we are reloading is no longer referenced
8009 anywhere between the store into it and here,
8010 and no jumps or labels intervene, then the value can get
8011 here through the reload reg alone.
8012 Otherwise, give up--return. */
8013 for (i1 = NEXT_INSN (output_reload_insn);
8014 i1 != insn; i1 = NEXT_INSN (i1))
8016 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
8018 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
8019 && reg_mentioned_p (reg, PATTERN (i1)))
8021 /* If this is USE in front of INSN, we only have to check that
8022 there are no more references than accounted for by inheritance. */
8023 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
8025 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8026 i1 = NEXT_INSN (i1);
8028 if (n_occurrences <= n_inherited && i1 == insn)
8034 /* The caller has already checked that REG dies or is set in INSN.
8035 It has also checked that we are optimizing, and thus some inaccurancies
8036 in the debugging information are acceptable.
8037 So we could just delete output_reload_insn.
8038 But in some cases we can improve the debugging information without
8039 sacrificing optimization - maybe even improving the code:
8040 See if the pseudo reg has been completely replaced
8041 with reload regs. If so, delete the store insn
8042 and forget we had a stack slot for the pseudo. */
8043 if (rld[j].out != rld[j].in
8044 && REG_N_DEATHS (REGNO (reg)) == 1
8045 && REG_N_SETS (REGNO (reg)) == 1
8046 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8047 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8051 /* We know that it was used only between here
8052 and the beginning of the current basic block.
8053 (We also know that the last use before INSN was
8054 the output reload we are thinking of deleting, but never mind that.)
8055 Search that range; see if any ref remains. */
8056 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8058 rtx set = single_set (i2);
8060 /* Uses which just store in the pseudo don't count,
8061 since if they are the only uses, they are dead. */
8062 if (set != 0 && SET_DEST (set) == reg)
8064 if (GET_CODE (i2) == CODE_LABEL
8065 || GET_CODE (i2) == JUMP_INSN)
8067 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
8068 && reg_mentioned_p (reg, PATTERN (i2)))
8070 /* Some other ref remains; just delete the output reload we
8072 delete_address_reloads (output_reload_insn, insn);
8073 PUT_CODE (output_reload_insn, NOTE);
8074 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8075 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8080 /* Delete the now-dead stores into this pseudo. */
8081 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8083 rtx set = single_set (i2);
8085 if (set != 0 && SET_DEST (set) == reg)
8087 delete_address_reloads (i2, insn);
8088 /* This might be a basic block head,
8089 thus don't use delete_insn. */
8090 PUT_CODE (i2, NOTE);
8091 NOTE_SOURCE_FILE (i2) = 0;
8092 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8094 if (GET_CODE (i2) == CODE_LABEL
8095 || GET_CODE (i2) == JUMP_INSN)
8099 /* For the debugging info,
8100 say the pseudo lives in this reload reg. */
8101 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8102 alter_reg (REGNO (reg), -1);
8104 delete_address_reloads (output_reload_insn, insn);
8105 PUT_CODE (output_reload_insn, NOTE);
8106 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8107 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8111 /* We are going to delete DEAD_INSN. Recursively delete loads of
8112 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8113 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8115 delete_address_reloads (dead_insn, current_insn)
8116 rtx dead_insn, current_insn;
8118 rtx set = single_set (dead_insn);
8119 rtx set2, dst, prev, next;
8122 rtx dst = SET_DEST (set);
8123 if (GET_CODE (dst) == MEM)
8124 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8126 /* If we deleted the store from a reloaded post_{in,de}c expression,
8127 we can delete the matching adds. */
8128 prev = PREV_INSN (dead_insn);
8129 next = NEXT_INSN (dead_insn);
8130 if (! prev || ! next)
8132 set = single_set (next);
8133 set2 = single_set (prev);
8135 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8136 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8137 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8139 dst = SET_DEST (set);
8140 if (! rtx_equal_p (dst, SET_DEST (set2))
8141 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8142 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8143 || (INTVAL (XEXP (SET_SRC (set), 1))
8144 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8150 /* Subfunction of delete_address_reloads: process registers found in X. */
8152 delete_address_reloads_1 (dead_insn, x, current_insn)
8153 rtx dead_insn, x, current_insn;
8155 rtx prev, set, dst, i2;
8157 enum rtx_code code = GET_CODE (x);
8161 const char *fmt= GET_RTX_FORMAT (code);
8162 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8165 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8166 else if (fmt[i] == 'E')
8168 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8169 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8176 if (spill_reg_order[REGNO (x)] < 0)
8179 /* Scan backwards for the insn that sets x. This might be a way back due
8181 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8183 code = GET_CODE (prev);
8184 if (code == CODE_LABEL || code == JUMP_INSN)
8186 if (GET_RTX_CLASS (code) != 'i')
8188 if (reg_set_p (x, PATTERN (prev)))
8190 if (reg_referenced_p (x, PATTERN (prev)))
8193 if (! prev || INSN_UID (prev) < reload_first_uid)
8195 /* Check that PREV only sets the reload register. */
8196 set = single_set (prev);
8199 dst = SET_DEST (set);
8200 if (GET_CODE (dst) != REG
8201 || ! rtx_equal_p (dst, x))
8203 if (! reg_set_p (dst, PATTERN (dead_insn)))
8205 /* Check if DST was used in a later insn -
8206 it might have been inherited. */
8207 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8209 if (GET_CODE (i2) == CODE_LABEL)
8211 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8213 if (reg_referenced_p (dst, PATTERN (i2)))
8215 /* If there is a reference to the register in the current insn,
8216 it might be loaded in a non-inherited reload. If no other
8217 reload uses it, that means the register is set before
8219 if (i2 == current_insn)
8221 for (j = n_reloads - 1; j >= 0; j--)
8222 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8223 || reload_override_in[j] == dst)
8225 for (j = n_reloads - 1; j >= 0; j--)
8226 if (rld[j].in && rld[j].reg_rtx == dst)
8233 if (GET_CODE (i2) == JUMP_INSN)
8235 /* If DST is still live at CURRENT_INSN, check if it is used for
8236 any reload. Note that even if CURRENT_INSN sets DST, we still
8237 have to check the reloads. */
8238 if (i2 == current_insn)
8240 for (j = n_reloads - 1; j >= 0; j--)
8241 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8242 || reload_override_in[j] == dst)
8244 /* ??? We can't finish the loop here, because dst might be
8245 allocated to a pseudo in this block if no reload in this
8246 block needs any of the clsses containing DST - see
8247 spill_hard_reg. There is no easy way to tell this, so we
8248 have to scan till the end of the basic block. */
8250 if (reg_set_p (dst, PATTERN (i2)))
8254 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8255 reg_reloaded_contents[REGNO (dst)] = -1;
8256 /* Can't use delete_insn here because PREV might be a basic block head. */
8257 PUT_CODE (prev, NOTE);
8258 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8259 NOTE_SOURCE_FILE (prev) = 0;
8262 /* Output reload-insns to reload VALUE into RELOADREG.
8263 VALUE is an autoincrement or autodecrement RTX whose operand
8264 is a register or memory location;
8265 so reloading involves incrementing that location.
8266 IN is either identical to VALUE, or some cheaper place to reload from.
8268 INC_AMOUNT is the number to increment or decrement by (always positive).
8269 This cannot be deduced from VALUE.
8271 Return the instruction that stores into RELOADREG. */
8274 inc_for_reload (reloadreg, in, value, inc_amount)
8279 /* REG or MEM to be copied and incremented. */
8280 rtx incloc = XEXP (value, 0);
8281 /* Nonzero if increment after copying. */
8282 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8288 rtx real_in = in == value ? XEXP (in, 0) : in;
8290 /* No hard register is equivalent to this register after
8291 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8292 we could inc/dec that register as well (maybe even using it for
8293 the source), but I'm not sure it's worth worrying about. */
8294 if (GET_CODE (incloc) == REG)
8295 reg_last_reload_reg[REGNO (incloc)] = 0;
8297 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8298 inc_amount = - inc_amount;
8300 inc = GEN_INT (inc_amount);
8302 /* If this is post-increment, first copy the location to the reload reg. */
8303 if (post && real_in != reloadreg)
8304 emit_insn (gen_move_insn (reloadreg, real_in));
8308 /* See if we can directly increment INCLOC. Use a method similar to
8309 that in gen_reload. */
8311 last = get_last_insn ();
8312 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8313 gen_rtx_PLUS (GET_MODE (incloc),
8316 code = recog_memoized (add_insn);
8319 extract_insn (add_insn);
8320 if (constrain_operands (1))
8322 /* If this is a pre-increment and we have incremented the value
8323 where it lives, copy the incremented value to RELOADREG to
8324 be used as an address. */
8327 emit_insn (gen_move_insn (reloadreg, incloc));
8332 delete_insns_since (last);
8335 /* If couldn't do the increment directly, must increment in RELOADREG.
8336 The way we do this depends on whether this is pre- or post-increment.
8337 For pre-increment, copy INCLOC to the reload register, increment it
8338 there, then save back. */
8342 if (in != reloadreg)
8343 emit_insn (gen_move_insn (reloadreg, real_in));
8344 emit_insn (gen_add2_insn (reloadreg, inc));
8345 store = emit_insn (gen_move_insn (incloc, reloadreg));
8350 Because this might be a jump insn or a compare, and because RELOADREG
8351 may not be available after the insn in an input reload, we must do
8352 the incrementation before the insn being reloaded for.
8354 We have already copied IN to RELOADREG. Increment the copy in
8355 RELOADREG, save that back, then decrement RELOADREG so it has
8356 the original value. */
8358 emit_insn (gen_add2_insn (reloadreg, inc));
8359 store = emit_insn (gen_move_insn (incloc, reloadreg));
8360 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8366 /* Return 1 if we are certain that the constraint-string STRING allows
8367 the hard register REG. Return 0 if we can't be sure of this. */
8370 constraint_accepts_reg_p (string, reg)
8375 int regno = true_regnum (reg);
8378 /* Initialize for first alternative. */
8380 /* Check that each alternative contains `g' or `r'. */
8382 switch (c = *string++)
8385 /* If an alternative lacks `g' or `r', we lose. */
8388 /* If an alternative lacks `g' or `r', we lose. */
8391 /* Initialize for next alternative. */
8396 /* Any general reg wins for this alternative. */
8397 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8401 /* Any reg in specified class wins for this alternative. */
8403 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8405 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8411 /* Return the number of places FIND appears within X, but don't count
8412 an occurrence if some SET_DEST is FIND. */
8415 count_occurrences (x, find)
8416 register rtx x, find;
8419 register enum rtx_code code;
8420 register const char *format_ptr;
8428 code = GET_CODE (x);
8443 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8447 if (SET_DEST (x) == find)
8448 return count_occurrences (SET_SRC (x), find);
8455 format_ptr = GET_RTX_FORMAT (code);
8458 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8460 switch (*format_ptr++)
8463 count += count_occurrences (XEXP (x, i), find);
8467 if (XVEC (x, i) != NULL)
8469 for (j = 0; j < XVECLEN (x, i); j++)
8470 count += count_occurrences (XVECEXP (x, i, j), find);
8478 /* This array holds values which are equivalent to a hard register
8479 during reload_cse_regs. Each array element is an EXPR_LIST of
8480 values. Each time a hard register is set, we set the corresponding
8481 array element to the value. Each time a hard register is copied
8482 into memory, we add the memory location to the corresponding array
8483 element. We don't store values or memory addresses with side
8484 effects in this array.
8486 If the value is a CONST_INT, then the mode of the containing
8487 EXPR_LIST is the mode in which that CONST_INT was referenced.
8489 We sometimes clobber a specific entry in a list. In that case, we
8490 just set XEXP (list-entry, 0) to 0. */
8492 static rtx *reg_values;
8494 /* This is a preallocated REG rtx which we use as a temporary in
8495 reload_cse_invalidate_regno, so that we don't need to allocate a
8496 new one each time through a loop in that function. */
8498 static rtx invalidate_regno_rtx;
8500 /* Invalidate any entries in reg_values which depend on REGNO,
8501 including those for REGNO itself. This is called if REGNO is
8502 changing. If CLOBBER is true, then always forget anything we
8503 currently know about REGNO. MODE is the mode of the assignment to
8504 REGNO, which is used to determine how many hard registers are being
8505 changed. If MODE is VOIDmode, then only REGNO is being changed;
8506 this is used when invalidating call clobbered registers across a
8510 reload_cse_invalidate_regno (regno, mode, clobber)
8512 enum machine_mode mode;
8518 /* Our callers don't always go through true_regnum; we may see a
8519 pseudo-register here from a CLOBBER or the like. We probably
8520 won't ever see a pseudo-register that has a real register number,
8521 for we check anyhow for safety. */
8522 if (regno >= FIRST_PSEUDO_REGISTER)
8523 regno = reg_renumber[regno];
8527 if (mode == VOIDmode)
8528 endregno = regno + 1;
8530 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8533 for (i = regno; i < endregno; i++)
8536 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8540 for (x = reg_values[i]; x; x = XEXP (x, 1))
8542 if (XEXP (x, 0) != 0
8543 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8545 /* If this is the only entry on the list, clear
8546 reg_values[i]. Otherwise, just clear this entry on
8548 if (XEXP (x, 1) == 0 && x == reg_values[i])
8558 /* We must look at earlier registers, in case REGNO is part of a
8559 multi word value but is not the first register. If an earlier
8560 register has a value in a mode which overlaps REGNO, then we must
8561 invalidate that earlier register. Note that we do not need to
8562 check REGNO or later registers (we must not check REGNO itself,
8563 because we would incorrectly conclude that there was a conflict). */
8565 for (i = 0; i < regno; i++)
8569 for (x = reg_values[i]; x; x = XEXP (x, 1))
8571 if (XEXP (x, 0) != 0)
8573 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8574 REGNO (invalidate_regno_rtx) = i;
8575 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8578 reload_cse_invalidate_regno (i, VOIDmode, 1);
8586 /* The memory at address MEM_BASE is being changed.
8587 Return whether this change will invalidate VAL. */
8590 reload_cse_mem_conflict_p (mem_base, val)
8598 code = GET_CODE (val);
8601 /* Get rid of a few simple cases quickly. */
8614 if (GET_MODE (mem_base) == BLKmode
8615 || GET_MODE (val) == BLKmode)
8617 if (anti_dependence (val, mem_base))
8619 /* The address may contain nested MEMs. */
8626 fmt = GET_RTX_FORMAT (code);
8628 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8632 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8635 else if (fmt[i] == 'E')
8639 for (j = 0; j < XVECLEN (val, i); j++)
8640 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8648 /* Invalidate any entries in reg_values which are changed because of a
8649 store to MEM_RTX. If this is called because of a non-const call
8650 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8653 reload_cse_invalidate_mem (mem_rtx)
8658 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8662 for (x = reg_values[i]; x; x = XEXP (x, 1))
8664 if (XEXP (x, 0) != 0
8665 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8667 /* If this is the only entry on the list, clear
8668 reg_values[i]. Otherwise, just clear this entry on
8670 if (XEXP (x, 1) == 0 && x == reg_values[i])
8681 /* Invalidate DEST, which is being assigned to or clobbered. The
8682 second parameter exists so that this function can be passed to
8683 note_stores; it is ignored. */
8686 reload_cse_invalidate_rtx (dest, ignore, data)
8688 rtx ignore ATTRIBUTE_UNUSED;
8689 void *data ATTRIBUTE_UNUSED;
8691 while (GET_CODE (dest) == STRICT_LOW_PART
8692 || GET_CODE (dest) == SIGN_EXTRACT
8693 || GET_CODE (dest) == ZERO_EXTRACT
8694 || GET_CODE (dest) == SUBREG)
8695 dest = XEXP (dest, 0);
8697 if (GET_CODE (dest) == REG)
8698 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8699 else if (GET_CODE (dest) == MEM)
8700 reload_cse_invalidate_mem (dest);
8703 /* Do a very simple CSE pass over the hard registers.
8705 This function detects no-op moves where we happened to assign two
8706 different pseudo-registers to the same hard register, and then
8707 copied one to the other. Reload will generate a useless
8708 instruction copying a register to itself.
8710 This function also detects cases where we load a value from memory
8711 into two different registers, and (if memory is more expensive than
8712 registers) changes it to simply copy the first register into the
8715 Another optimization is performed that scans the operands of each
8716 instruction to see whether the value is already available in a
8717 hard register. It then replaces the operand with the hard register
8718 if possible, much like an optional reload would. */
8721 reload_cse_regs_1 (first)
8729 init_alias_analysis ();
8731 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8732 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8734 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8735 free them when we are done. */
8736 push_obstacks (&reload_obstack, &reload_obstack);
8737 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8739 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8740 memory for a non-const call instruction. */
8741 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8743 /* This is used in reload_cse_invalidate_regno to avoid consing a
8744 new REG in a loop in that function. */
8745 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8747 for (insn = first; insn; insn = NEXT_INSN (insn))
8751 if (GET_CODE (insn) == CODE_LABEL)
8753 /* Forget all the register values at a code label. We don't
8754 try to do anything clever around jumps. */
8755 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8761 #ifdef NON_SAVING_SETJMP
8762 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8763 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8772 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8775 /* If this is a call instruction, forget anything stored in a
8776 call clobbered register, or, if this is not a const call, in
8778 if (GET_CODE (insn) == CALL_INSN)
8780 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8781 if (call_used_regs[i])
8782 reload_cse_invalidate_regno (i, VOIDmode, 1);
8784 if (! CONST_CALL_P (insn))
8785 reload_cse_invalidate_mem (callmem);
8789 /* Forget all the register values at a volatile asm. */
8790 if (GET_CODE (insn) == INSN
8791 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8792 && MEM_VOLATILE_P (PATTERN (insn)))
8793 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8796 body = PATTERN (insn);
8797 if (GET_CODE (body) == SET)
8800 if (reload_cse_noop_set_p (body, insn))
8802 /* If this sets the return value of the function, we must keep
8803 a USE around, in case this is in a different basic block
8804 than the final USE. Otherwise, we could loose important
8805 register lifeness information on SMALL_REGISTER_CLASSES
8806 machines, where return registers might be used as spills:
8807 subsequent passes assume that spill registers are dead at
8808 the end of a basic block. */
8809 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8812 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8813 INSN_CODE (insn) = -1;
8814 REG_NOTES (insn) = NULL_RTX;
8815 push_obstacks (&reload_obstack, &reload_obstack);
8819 PUT_CODE (insn, NOTE);
8820 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8821 NOTE_SOURCE_FILE (insn) = 0;
8824 /* We're done with this insn. */
8828 /* It's not a no-op, but we can try to simplify it. */
8829 count += reload_cse_simplify_set (body, insn);
8832 apply_change_group ();
8834 reload_cse_simplify_operands (insn);
8836 reload_cse_record_set (body, body);
8838 else if (GET_CODE (body) == PARALLEL)
8841 rtx value = NULL_RTX;
8843 /* If every action in a PARALLEL is a noop, we can delete
8844 the entire PARALLEL. */
8845 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8847 rtx part = XVECEXP (body, 0, i);
8848 if (GET_CODE (part) == SET)
8850 if (! reload_cse_noop_set_p (part, insn))
8852 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8856 value = SET_DEST (part);
8859 else if (GET_CODE (part) != CLOBBER)
8867 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8868 INSN_CODE (insn) = -1;
8869 REG_NOTES (insn) = NULL_RTX;
8870 push_obstacks (&reload_obstack, &reload_obstack);
8874 PUT_CODE (insn, NOTE);
8875 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8876 NOTE_SOURCE_FILE (insn) = 0;
8879 /* We're done with this insn. */
8883 /* It's not a no-op, but we can try to simplify it. */
8884 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8885 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8886 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8889 apply_change_group ();
8891 reload_cse_simplify_operands (insn);
8893 /* Look through the PARALLEL and record the values being
8894 set, if possible. Also handle any CLOBBERs. */
8895 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8897 rtx x = XVECEXP (body, 0, i);
8899 if (GET_CODE (x) == SET)
8900 reload_cse_record_set (x, body);
8902 note_stores (x, reload_cse_invalidate_rtx, NULL);
8906 note_stores (body, reload_cse_invalidate_rtx, NULL);
8909 /* Clobber any registers which appear in REG_INC notes. We
8910 could keep track of the changes to their values, but it is
8911 unlikely to help. */
8915 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8916 if (REG_NOTE_KIND (x) == REG_INC)
8917 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
8921 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8922 after we have processed the insn. */
8923 if (GET_CODE (insn) == CALL_INSN)
8927 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8928 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8929 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
8935 end_alias_analysis ();
8937 /* Free all the temporary structures we created, and go back to the
8938 regular obstacks. */
8939 obstack_free (&reload_obstack, firstobj);
8943 /* Call cse / combine like post-reload optimization phases.
8944 FIRST is the first instruction. */
8946 reload_cse_regs (first)
8949 reload_cse_regs_1 (first);
8951 reload_cse_move2add (first);
8952 if (flag_expensive_optimizations)
8953 reload_cse_regs_1 (first);
8956 /* Return whether the values known for REGNO are equal to VAL. MODE
8957 is the mode of the object that VAL is being copied to; this matters
8958 if VAL is a CONST_INT. */
8961 reload_cse_regno_equal_p (regno, val, mode)
8964 enum machine_mode mode;
8971 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8972 if (XEXP (x, 0) != 0
8973 && rtx_equal_p (XEXP (x, 0), val)
8974 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8975 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8976 && (GET_CODE (val) != CONST_INT
8977 || mode == GET_MODE (x)
8978 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8979 /* On a big endian machine if the value spans more than
8980 one register then this register holds the high part of
8981 it and we can't use it.
8983 ??? We should also compare with the high part of the
8985 && !(WORDS_BIG_ENDIAN
8986 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8987 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8988 GET_MODE_BITSIZE (GET_MODE (x))))))
8994 /* See whether a single set is a noop. SET is the set instruction we
8995 are should check, and INSN is the instruction from which it came. */
8998 reload_cse_noop_set_p (set, insn)
9000 rtx insn ATTRIBUTE_UNUSED;
9003 enum machine_mode dest_mode;
9007 src = SET_SRC (set);
9008 dest = SET_DEST (set);
9009 dest_mode = GET_MODE (dest);
9011 if (side_effects_p (src))
9014 dreg = true_regnum (dest);
9015 sreg = true_regnum (src);
9017 /* Check for setting a register to itself. In this case, we don't
9018 have to worry about REG_DEAD notes. */
9019 if (dreg >= 0 && dreg == sreg)
9025 /* Check for setting a register to itself. */
9029 /* Check for setting a register to a value which we already know
9030 is in the register. */
9031 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
9034 /* Check for setting a register DREG to another register SREG
9035 where SREG is equal to a value which is already in DREG. */
9040 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9044 if (XEXP (x, 0) == 0)
9047 if (dest_mode == GET_MODE (x))
9049 else if (GET_MODE_BITSIZE (dest_mode)
9050 < GET_MODE_BITSIZE (GET_MODE (x)))
9051 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9056 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
9064 else if (GET_CODE (dest) == MEM)
9066 /* Check for storing a register to memory when we know that the
9067 register is equivalent to the memory location. */
9069 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
9070 && ! side_effects_p (dest))
9077 /* Try to simplify a single SET instruction. SET is the set pattern.
9078 INSN is the instruction it came from.
9079 This function only handles one case: if we set a register to a value
9080 which is not a register, we try to find that value in some other register
9081 and change the set into a register copy. */
9084 reload_cse_simplify_set (set, insn)
9090 enum machine_mode dest_mode;
9091 enum reg_class dclass;
9094 dreg = true_regnum (SET_DEST (set));
9098 src = SET_SRC (set);
9099 if (side_effects_p (src) || true_regnum (src) >= 0)
9102 dclass = REGNO_REG_CLASS (dreg);
9104 /* If memory loads are cheaper than register copies, don't change them. */
9105 if (GET_CODE (src) == MEM
9106 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9109 /* If the constant is cheaper than a register, don't change it. */
9110 if (CONSTANT_P (src)
9111 && rtx_cost (src, SET) < 2)
9114 dest_mode = GET_MODE (SET_DEST (set));
9115 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9118 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9119 && reload_cse_regno_equal_p (i, src, dest_mode))
9123 /* Pop back to the real obstacks while changing the insn. */
9126 validated = validate_change (insn, &SET_SRC (set),
9127 gen_rtx_REG (dest_mode, i), 1);
9129 /* Go back to the obstack we are using for temporary
9131 push_obstacks (&reload_obstack, &reload_obstack);
9140 /* Try to replace operands in INSN with equivalent values that are already
9141 in registers. This can be viewed as optional reloading.
9143 For each non-register operand in the insn, see if any hard regs are
9144 known to be equivalent to that operand. Record the alternatives which
9145 can accept these hard registers. Among all alternatives, select the
9146 ones which are better or equal to the one currently matching, where
9147 "better" is in terms of '?' and '!' constraints. Among the remaining
9148 alternatives, select the one which replaces most operands with
9152 reload_cse_simplify_operands (insn)
9157 const char *constraints[MAX_RECOG_OPERANDS];
9159 /* Vector recording how bad an alternative is. */
9160 int *alternative_reject;
9161 /* Vector recording how many registers can be introduced by choosing
9162 this alternative. */
9163 int *alternative_nregs;
9164 /* Array of vectors recording, for each operand and each alternative,
9165 which hard register to substitute, or -1 if the operand should be
9167 int *op_alt_regno[MAX_RECOG_OPERANDS];
9168 /* Array of alternatives, sorted in order of decreasing desirability. */
9169 int *alternative_order;
9170 rtx reg = gen_rtx_REG (VOIDmode, -1);
9172 extract_insn (insn);
9174 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
9177 /* Figure out which alternative currently matches. */
9178 if (! constrain_operands (1))
9179 fatal_insn_not_found (insn);
9181 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9182 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9183 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9184 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
9185 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
9187 for (i = 0; i < recog_data.n_operands; i++)
9189 enum machine_mode mode;
9193 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9194 for (j = 0; j < recog_data.n_alternatives; j++)
9195 op_alt_regno[i][j] = -1;
9197 p = constraints[i] = recog_data.constraints[i];
9198 mode = recog_data.operand_mode[i];
9200 /* Add the reject values for each alternative given by the constraints
9201 for this operand. */
9209 alternative_reject[j] += 3;
9211 alternative_reject[j] += 300;
9214 /* We won't change operands which are already registers. We
9215 also don't want to modify output operands. */
9216 regno = true_regnum (recog_data.operand[i]);
9218 || constraints[i][0] == '='
9219 || constraints[i][0] == '+')
9222 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9224 int class = (int) NO_REGS;
9226 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
9229 REGNO (reg) = regno;
9230 PUT_MODE (reg, mode);
9232 /* We found a register equal to this operand. Now look for all
9233 alternatives that can accept this register and have not been
9234 assigned a register they can use yet. */
9243 case '=': case '+': case '?':
9244 case '#': case '&': case '!':
9246 case '0': case '1': case '2': case '3': case '4':
9247 case '5': case '6': case '7': case '8': case '9':
9248 case 'm': case '<': case '>': case 'V': case 'o':
9249 case 'E': case 'F': case 'G': case 'H':
9250 case 's': case 'i': case 'n':
9251 case 'I': case 'J': case 'K': case 'L':
9252 case 'M': case 'N': case 'O': case 'P':
9253 #ifdef EXTRA_CONSTRAINT
9254 case 'Q': case 'R': case 'S': case 'T': case 'U':
9257 /* These don't say anything we care about. */
9261 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9266 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9269 case ',': case '\0':
9270 /* See if REGNO fits this alternative, and set it up as the
9271 replacement register if we don't have one for this
9272 alternative yet and the operand being replaced is not
9273 a cheap CONST_INT. */
9274 if (op_alt_regno[i][j] == -1
9275 && reg_fits_class_p (reg, class, 0, mode)
9276 && (GET_CODE (recog_data.operand[i]) != CONST_INT
9277 || (rtx_cost (recog_data.operand[i], SET)
9278 > rtx_cost (reg, SET))))
9280 alternative_nregs[j]++;
9281 op_alt_regno[i][j] = regno;
9293 /* Record all alternatives which are better or equal to the currently
9294 matching one in the alternative_order array. */
9295 for (i = j = 0; i < recog_data.n_alternatives; i++)
9296 if (alternative_reject[i] <= alternative_reject[which_alternative])
9297 alternative_order[j++] = i;
9298 recog_data.n_alternatives = j;
9300 /* Sort it. Given a small number of alternatives, a dumb algorithm
9301 won't hurt too much. */
9302 for (i = 0; i < recog_data.n_alternatives - 1; i++)
9305 int best_reject = alternative_reject[alternative_order[i]];
9306 int best_nregs = alternative_nregs[alternative_order[i]];
9309 for (j = i + 1; j < recog_data.n_alternatives; j++)
9311 int this_reject = alternative_reject[alternative_order[j]];
9312 int this_nregs = alternative_nregs[alternative_order[j]];
9314 if (this_reject < best_reject
9315 || (this_reject == best_reject && this_nregs < best_nregs))
9318 best_reject = this_reject;
9319 best_nregs = this_nregs;
9323 tmp = alternative_order[best];
9324 alternative_order[best] = alternative_order[i];
9325 alternative_order[i] = tmp;
9328 /* Substitute the operands as determined by op_alt_regno for the best
9330 j = alternative_order[0];
9332 /* Pop back to the real obstacks while changing the insn. */
9335 for (i = 0; i < recog_data.n_operands; i++)
9337 enum machine_mode mode = recog_data.operand_mode[i];
9338 if (op_alt_regno[i][j] == -1)
9341 validate_change (insn, recog_data.operand_loc[i],
9342 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9345 for (i = recog_data.n_dups - 1; i >= 0; i--)
9347 int op = recog_data.dup_num[i];
9348 enum machine_mode mode = recog_data.operand_mode[op];
9350 if (op_alt_regno[op][j] == -1)
9353 validate_change (insn, recog_data.dup_loc[i],
9354 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9357 /* Go back to the obstack we are using for temporary
9359 push_obstacks (&reload_obstack, &reload_obstack);
9361 return apply_change_group ();
9364 /* These two variables are used to pass information from
9365 reload_cse_record_set to reload_cse_check_clobber. */
9367 static int reload_cse_check_clobbered;
9368 static rtx reload_cse_check_src;
9370 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9371 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9372 second argument, which is passed by note_stores, is ignored. */
9375 reload_cse_check_clobber (dest, ignore, data)
9377 rtx ignore ATTRIBUTE_UNUSED;
9378 void *data ATTRIBUTE_UNUSED;
9380 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9381 reload_cse_check_clobbered = 1;
9384 /* Record the result of a SET instruction. SET is the set pattern.
9385 BODY is the pattern of the insn that it came from. */
9388 reload_cse_record_set (set, body)
9394 enum machine_mode dest_mode;
9396 dest = SET_DEST (set);
9397 src = SET_SRC (set);
9398 dreg = true_regnum (dest);
9399 sreg = true_regnum (src);
9400 dest_mode = GET_MODE (dest);
9402 /* Some machines don't define AUTO_INC_DEC, but they still use push
9403 instructions. We need to catch that case here in order to
9404 invalidate the stack pointer correctly. Note that invalidating
9405 the stack pointer is different from invalidating DEST. */
9407 while (GET_CODE (x) == SUBREG
9408 || GET_CODE (x) == ZERO_EXTRACT
9409 || GET_CODE (x) == SIGN_EXTRACT
9410 || GET_CODE (x) == STRICT_LOW_PART)
9412 if (push_operand (x, GET_MODE (x)))
9414 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
9415 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9419 /* We can only handle an assignment to a register, or a store of a
9420 register to a memory location. For other cases, we just clobber
9421 the destination. We also have to just clobber if there are side
9422 effects in SRC or DEST. */
9423 if ((dreg < 0 && GET_CODE (dest) != MEM)
9424 || side_effects_p (src)
9425 || side_effects_p (dest))
9427 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9432 /* We don't try to handle values involving CC, because it's a pain
9433 to keep track of when they have to be invalidated. */
9434 if (reg_mentioned_p (cc0_rtx, src)
9435 || reg_mentioned_p (cc0_rtx, dest))
9437 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9442 /* If BODY is a PARALLEL, then we need to see whether the source of
9443 SET is clobbered by some other instruction in the PARALLEL. */
9444 if (GET_CODE (body) == PARALLEL)
9448 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9452 x = XVECEXP (body, 0, i);
9456 reload_cse_check_clobbered = 0;
9457 reload_cse_check_src = src;
9458 note_stores (x, reload_cse_check_clobber, NULL);
9459 if (reload_cse_check_clobbered)
9461 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9471 /* This is an assignment to a register. Update the value we
9472 have stored for the register. */
9477 /* This is a copy from one register to another. Any values
9478 which were valid for SREG are now valid for DREG. If the
9479 mode changes, we use gen_lowpart_common to extract only
9480 the part of the value that is copied. */
9481 reg_values[dreg] = 0;
9482 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9486 if (XEXP (x, 0) == 0)
9488 if (dest_mode == GET_MODE (XEXP (x, 0)))
9490 else if (GET_MODE_BITSIZE (dest_mode)
9491 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9494 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9496 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9501 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9503 /* We've changed DREG, so invalidate any values held by other
9504 registers that depend upon it. */
9505 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9507 /* If this assignment changes more than one hard register,
9508 forget anything we know about the others. */
9509 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9510 reg_values[dreg + i] = 0;
9512 else if (GET_CODE (dest) == MEM)
9514 /* Invalidate conflicting memory locations. */
9515 reload_cse_invalidate_mem (dest);
9517 /* If we're storing a register to memory, add DEST to the list
9519 if (sreg >= 0 && ! side_effects_p (dest))
9520 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9525 /* We should have bailed out earlier. */
9530 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9532 This code might also be useful when reload gave up on reg+reg addresssing
9533 because of clashes between the return register and INDEX_REG_CLASS. */
9535 /* The maximum number of uses of a register we can keep track of to
9536 replace them with reg+reg addressing. */
9537 #define RELOAD_COMBINE_MAX_USES 6
9539 /* INSN is the insn where a register has ben used, and USEP points to the
9540 location of the register within the rtl. */
9541 struct reg_use { rtx insn, *usep; };
9543 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9544 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9545 indicates where it becomes live again.
9546 Otherwise, USE_INDEX is the index of the last encountered use of the
9547 register (which is first among these we have seen since we scan backwards),
9548 OFFSET contains the constant offset that is added to the register in
9549 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9550 last, of these uses.
9551 STORE_RUID is always meaningful if we only want to use a value in a
9552 register in a different place: it denotes the next insn in the insn
9553 stream (i.e. the last ecountered) that sets or clobbers the register. */
9556 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9561 } reg_state[FIRST_PSEUDO_REGISTER];
9563 /* Reverse linear uid. This is increased in reload_combine while scanning
9564 the instructions from last to first. It is used to set last_label_ruid
9565 and the store_ruid / use_ruid fields in reg_state. */
9566 static int reload_combine_ruid;
9568 #define LABEL_LIVE(LABEL) \
9569 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9575 int first_index_reg = 1, last_index_reg = 0;
9577 int last_label_ruid;
9578 int min_labelno, n_labels;
9579 HARD_REG_SET ever_live_at_start, *label_live;
9581 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9582 reload has already used it where appropriate, so there is no use in
9583 trying to generate it now. */
9584 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9587 /* To avoid wasting too much time later searching for an index register,
9588 determine the minimum and maximum index register numbers. */
9589 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9591 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9593 if (! last_index_reg)
9595 first_index_reg = i;
9598 /* If no index register is available, we can quit now. */
9599 if (first_index_reg > last_index_reg)
9602 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9603 information is a bit fuzzy immediately after reload, but it's
9604 still good enough to determine which registers are live at a jump
9606 min_labelno = get_first_label_num ();
9607 n_labels = max_label_num () - min_labelno;
9608 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9609 CLEAR_HARD_REG_SET (ever_live_at_start);
9610 for (i = n_basic_blocks - 1; i >= 0; i--)
9612 insn = BLOCK_HEAD (i);
9613 if (GET_CODE (insn) == CODE_LABEL)
9617 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9618 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9619 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9620 IOR_HARD_REG_SET (ever_live_at_start, live);
9624 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9625 last_label_ruid = reload_combine_ruid = 0;
9626 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9628 reg_state[i].store_ruid = reload_combine_ruid;
9630 reg_state[i].use_index = -1;
9632 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9635 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9639 /* We cannot do our optimization across labels. Invalidating all the use
9640 information we have would be costly, so we just note where the label
9641 is and then later disable any optimization that would cross it. */
9642 if (GET_CODE (insn) == CODE_LABEL)
9643 last_label_ruid = reload_combine_ruid;
9644 if (GET_CODE (insn) == BARRIER)
9646 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9647 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9649 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9651 reload_combine_ruid++;
9653 /* Look for (set (REGX) (CONST_INT))
9654 (set (REGX) (PLUS (REGX) (REGY)))
9656 ... (MEM (REGX)) ...
9658 (set (REGZ) (CONST_INT))
9660 ... (MEM (PLUS (REGZ) (REGY)))... .
9662 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9663 and that we know all uses of REGX before it dies. */
9664 set = single_set (insn);
9666 && GET_CODE (SET_DEST (set)) == REG
9667 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9668 GET_MODE (SET_DEST (set)))
9670 && GET_CODE (SET_SRC (set)) == PLUS
9671 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9672 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9673 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9675 rtx reg = SET_DEST (set);
9676 rtx plus = SET_SRC (set);
9677 rtx base = XEXP (plus, 1);
9678 rtx prev = prev_nonnote_insn (insn);
9679 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9680 int regno = REGNO (reg);
9681 rtx const_reg = NULL_RTX;
9682 rtx reg_sum = NULL_RTX;
9684 /* Now, we need an index register.
9685 We'll set index_reg to this index register, const_reg to the
9686 register that is to be loaded with the constant
9687 (denoted as REGZ in the substitution illustration above),
9688 and reg_sum to the register-register that we want to use to
9689 substitute uses of REG (typically in MEMs) with.
9690 First check REG and BASE for being index registers;
9691 we can use them even if they are not dead. */
9692 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9693 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9701 /* Otherwise, look for a free index register. Since we have
9702 checked above that neiter REG nor BASE are index registers,
9703 if we find anything at all, it will be different from these
9705 for (i = first_index_reg; i <= last_index_reg; i++)
9707 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9708 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9709 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9710 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9712 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9713 const_reg = index_reg;
9714 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9719 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9720 (REGY), i.e. BASE, is not clobbered before the last use we'll
9723 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9724 && rtx_equal_p (SET_DEST (prev_set), reg)
9725 && reg_state[regno].use_index >= 0
9726 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9731 /* Change destination register and - if necessary - the
9732 constant value in PREV, the constant loading instruction. */
9733 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9734 if (reg_state[regno].offset != const0_rtx)
9735 validate_change (prev,
9736 &SET_SRC (prev_set),
9737 GEN_INT (INTVAL (SET_SRC (prev_set))
9738 + INTVAL (reg_state[regno].offset)),
9740 /* Now for every use of REG that we have recorded, replace REG
9742 for (i = reg_state[regno].use_index;
9743 i < RELOAD_COMBINE_MAX_USES; i++)
9744 validate_change (reg_state[regno].reg_use[i].insn,
9745 reg_state[regno].reg_use[i].usep,
9748 if (apply_change_group ())
9752 /* Delete the reg-reg addition. */
9753 PUT_CODE (insn, NOTE);
9754 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9755 NOTE_SOURCE_FILE (insn) = 0;
9757 if (reg_state[regno].offset != const0_rtx)
9759 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9761 for (np = ®_NOTES (prev); *np; )
9763 if (REG_NOTE_KIND (*np) == REG_EQUAL
9764 || REG_NOTE_KIND (*np) == REG_EQUIV)
9765 *np = XEXP (*np, 1);
9767 np = &XEXP (*np, 1);
9770 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9771 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9776 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
9777 if (GET_CODE (insn) == CALL_INSN)
9781 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9783 if (call_used_regs[i])
9785 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9786 reg_state[i].store_ruid = reload_combine_ruid;
9789 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9790 link = XEXP (link, 1))
9792 rtx use = XEXP (link, 0);
9793 int regno = REGNO (XEXP (use, 0));
9794 if (GET_CODE (use) == CLOBBER)
9796 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9797 reg_state[regno].store_ruid = reload_combine_ruid;
9800 reg_state[regno].use_index = -1;
9803 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9805 /* Non-spill registers might be used at the call destination in
9806 some unknown fashion, so we have to mark the unknown use. */
9808 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9809 && JUMP_LABEL (insn))
9810 live = &LABEL_LIVE (JUMP_LABEL (insn));
9812 live = &ever_live_at_start;
9813 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9815 if (TEST_HARD_REG_BIT (*live, i))
9816 reg_state[i].use_index = -1;
9819 reload_combine_note_use (&PATTERN (insn), insn);
9820 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9822 if (REG_NOTE_KIND (note) == REG_INC
9823 && GET_CODE (XEXP (note, 0)) == REG)
9825 int regno = REGNO (XEXP (note, 0));
9827 reg_state[regno].store_ruid = reload_combine_ruid;
9828 reg_state[regno].use_index = -1;
9835 /* Check if DST is a register or a subreg of a register; if it is,
9836 update reg_state[regno].store_ruid and reg_state[regno].use_index
9837 accordingly. Called via note_stores from reload_combine. */
9839 reload_combine_note_store (dst, set, data)
9841 void *data ATTRIBUTE_UNUSED;
9845 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9847 if (GET_CODE (dst) == SUBREG)
9849 regno = SUBREG_WORD (dst);
9850 dst = SUBREG_REG (dst);
9852 if (GET_CODE (dst) != REG)
9854 regno += REGNO (dst);
9856 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9857 careful with registers / register parts that are not full words.
9859 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9860 if (GET_CODE (set) != SET
9861 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9862 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9863 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9865 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9867 reg_state[i].use_index = -1;
9868 reg_state[i].store_ruid = reload_combine_ruid;
9873 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9875 reg_state[i].store_ruid = reload_combine_ruid;
9876 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9881 /* XP points to a piece of rtl that has to be checked for any uses of
9883 *XP is the pattern of INSN, or a part of it.
9884 Called from reload_combine, and recursively by itself. */
9886 reload_combine_note_use (xp, insn)
9890 enum rtx_code code = x->code;
9893 rtx offset = const0_rtx; /* For the REG case below. */
9898 if (GET_CODE (SET_DEST (x)) == REG)
9900 reload_combine_note_use (&SET_SRC (x), insn);
9906 if (GET_CODE (SET_DEST (x)) == REG)
9911 /* We are interested in (plus (reg) (const_int)) . */
9912 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9914 offset = XEXP (x, 1);
9919 int regno = REGNO (x);
9922 /* Some spurious USEs of pseudo registers might remain.
9923 Just ignore them. */
9924 if (regno >= FIRST_PSEUDO_REGISTER)
9927 /* If this register is already used in some unknown fashion, we
9929 If we decrement the index from zero to -1, we can't store more
9930 uses, so this register becomes used in an unknown fashion. */
9931 use_index = --reg_state[regno].use_index;
9935 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9937 /* We have found another use for a register that is already
9938 used later. Check if the offsets match; if not, mark the
9939 register as used in an unknown fashion. */
9940 if (! rtx_equal_p (offset, reg_state[regno].offset))
9942 reg_state[regno].use_index = -1;
9948 /* This is the first use of this register we have seen since we
9949 marked it as dead. */
9950 reg_state[regno].offset = offset;
9951 reg_state[regno].use_ruid = reload_combine_ruid;
9953 reg_state[regno].reg_use[use_index].insn = insn;
9954 reg_state[regno].reg_use[use_index].usep = xp;
9962 /* Recursively process the components of X. */
9963 fmt = GET_RTX_FORMAT (code);
9964 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9967 reload_combine_note_use (&XEXP (x, i), insn);
9968 else if (fmt[i] == 'E')
9970 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9971 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9976 /* See if we can reduce the cost of a constant by replacing a move with
9978 /* We cannot do our optimization across labels. Invalidating all the
9979 information about register contents we have would be costly, so we
9980 use last_label_luid (local variable of reload_cse_move2add) to note
9981 where the label is and then later disable any optimization that would
9983 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9984 reg_set_luid[n] is larger than last_label_luid[n] . */
9985 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9986 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9987 reg_mode[n] to be valid.
9988 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9989 has been set to reg_offset[n] in mode reg_mode[n] .
9990 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9991 register n has been set to the sum of reg_offset[n] and register
9992 reg_base_reg[n], calculated in mode reg_mode[n] . */
9993 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9994 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9995 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9996 /* move2add_luid is linearily increased while scanning the instructions
9997 from first to last. It is used to set reg_set_luid in
9998 reload_cse_move2add and move2add_note_store. */
9999 static int move2add_luid;
10001 /* Generate a CONST_INT and force it in the range of MODE. */
10003 gen_mode_int (mode, value)
10004 enum machine_mode mode;
10005 HOST_WIDE_INT value;
10007 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
10008 int width = GET_MODE_BITSIZE (mode);
10010 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
10012 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
10013 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
10014 cval |= (HOST_WIDE_INT) -1 << width;
10016 return GEN_INT (cval);
10020 reload_cse_move2add (first)
10025 int last_label_luid;
10027 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10028 reg_set_luid[i] = 0;
10030 last_label_luid = 0;
10032 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
10036 if (GET_CODE (insn) == CODE_LABEL)
10037 last_label_luid = move2add_luid;
10038 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
10040 pat = PATTERN (insn);
10041 /* For simplicity, we only perform this optimization on
10042 straightforward SETs. */
10043 if (GET_CODE (pat) == SET
10044 && GET_CODE (SET_DEST (pat)) == REG)
10046 rtx reg = SET_DEST (pat);
10047 int regno = REGNO (reg);
10048 rtx src = SET_SRC (pat);
10050 /* Check if we have valid information on the contents of this
10051 register in the mode of REG. */
10052 /* ??? We don't know how zero / sign extension is handled, hence
10053 we can't go from a narrower to a wider mode. */
10054 if (reg_set_luid[regno] > last_label_luid
10055 && (GET_MODE_SIZE (GET_MODE (reg))
10056 <= GET_MODE_SIZE (reg_mode[regno]))
10057 && GET_CODE (reg_offset[regno]) == CONST_INT)
10059 /* Try to transform (set (REGX) (CONST_INT A))
10061 (set (REGX) (CONST_INT B))
10063 (set (REGX) (CONST_INT A))
10065 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10067 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
10071 = gen_mode_int (GET_MODE (reg),
10072 INTVAL (src) - INTVAL (reg_offset[regno]));
10073 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10074 use (set (reg) (reg)) instead.
10075 We don't delete this insn, nor do we convert it into a
10076 note, to avoid losing register notes or the return
10077 value flag. jump2 already knowns how to get rid of
10079 if (new_src == const0_rtx)
10080 success = validate_change (insn, &SET_SRC (pat), reg, 0);
10081 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
10082 && have_add2_insn (GET_MODE (reg)))
10083 success = validate_change (insn, &PATTERN (insn),
10084 gen_add2_insn (reg, new_src), 0);
10085 reg_set_luid[regno] = move2add_luid;
10086 reg_mode[regno] = GET_MODE (reg);
10087 reg_offset[regno] = src;
10091 /* Try to transform (set (REGX) (REGY))
10092 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10094 (set (REGX) (REGY))
10095 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10098 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10100 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10101 else if (GET_CODE (src) == REG
10102 && reg_base_reg[regno] == REGNO (src)
10103 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10105 rtx next = next_nonnote_insn (insn);
10106 rtx set = NULL_RTX;
10108 set = single_set (next);
10111 && SET_DEST (set) == reg
10112 && GET_CODE (SET_SRC (set)) == PLUS
10113 && XEXP (SET_SRC (set), 0) == reg
10114 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10116 rtx src3 = XEXP (SET_SRC (set), 1);
10118 = gen_mode_int (GET_MODE (reg),
10120 - INTVAL (reg_offset[regno]));
10123 if (new_src == const0_rtx)
10124 /* See above why we create (set (reg) (reg)) here. */
10126 = validate_change (next, &SET_SRC (set), reg, 0);
10127 else if ((rtx_cost (new_src, PLUS)
10128 < 2 + rtx_cost (src3, SET))
10129 && have_add2_insn (GET_MODE (reg)))
10131 = validate_change (next, &PATTERN (next),
10132 gen_add2_insn (reg, new_src), 0);
10135 /* INSN might be the first insn in a basic block
10136 if the preceding insn is a conditional jump
10137 or a possible-throwing call. */
10138 PUT_CODE (insn, NOTE);
10139 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10140 NOTE_SOURCE_FILE (insn) = 0;
10143 reg_set_luid[regno] = move2add_luid;
10144 reg_mode[regno] = GET_MODE (reg);
10145 reg_offset[regno] = src3;
10152 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10154 if (REG_NOTE_KIND (note) == REG_INC
10155 && GET_CODE (XEXP (note, 0)) == REG)
10157 /* Indicate that this register has been recently written to,
10158 but the exact contents are not available. */
10159 int regno = REGNO (XEXP (note, 0));
10160 if (regno < FIRST_PSEUDO_REGISTER)
10162 reg_set_luid[regno] = move2add_luid;
10163 reg_offset[regno] = note;
10167 note_stores (PATTERN (insn), move2add_note_store, NULL);
10168 /* If this is a CALL_INSN, all call used registers are stored with
10170 if (GET_CODE (insn) == CALL_INSN)
10172 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10174 if (call_used_regs[i])
10176 reg_set_luid[i] = move2add_luid;
10177 reg_offset[i] = insn; /* Invalidate contents. */
10184 /* SET is a SET or CLOBBER that sets DST.
10185 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10186 Called from reload_cse_move2add via note_stores. */
10188 move2add_note_store (dst, set, data)
10190 void *data ATTRIBUTE_UNUSED;
10195 enum machine_mode mode = GET_MODE (dst);
10196 if (GET_CODE (dst) == SUBREG)
10198 regno = SUBREG_WORD (dst);
10199 dst = SUBREG_REG (dst);
10201 if (GET_CODE (dst) != REG)
10204 regno += REGNO (dst);
10206 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10207 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10208 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10209 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10211 rtx src = SET_SRC (set);
10213 reg_mode[regno] = mode;
10214 switch (GET_CODE (src))
10218 rtx src0 = XEXP (src, 0);
10219 if (GET_CODE (src0) == REG)
10221 if (REGNO (src0) != regno
10222 || reg_offset[regno] != const0_rtx)
10224 reg_base_reg[regno] = REGNO (src0);
10225 reg_set_luid[regno] = move2add_luid;
10227 reg_offset[regno] = XEXP (src, 1);
10230 reg_set_luid[regno] = move2add_luid;
10231 reg_offset[regno] = set; /* Invalidate contents. */
10236 reg_base_reg[regno] = REGNO (SET_SRC (set));
10237 reg_offset[regno] = const0_rtx;
10238 reg_set_luid[regno] = move2add_luid;
10242 reg_base_reg[regno] = -1;
10243 reg_offset[regno] = SET_SRC (set);
10244 reg_set_luid[regno] = move2add_luid;
10250 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10252 /* Indicate that this register has been recently written to,
10253 but the exact contents are not available. */
10254 reg_set_luid[i] = move2add_luid;
10255 reg_offset[i] = dst;
10260 #ifdef AUTO_INC_DEC
10262 add_auto_inc_notes (insn, x)
10266 enum rtx_code code = GET_CODE (x);
10270 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10273 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10277 /* Scan all the operand sub-expressions. */
10278 fmt = GET_RTX_FORMAT (code);
10279 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10282 add_auto_inc_notes (insn, XEXP (x, i));
10283 else if (fmt[i] == 'E')
10284 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10285 add_auto_inc_notes (insn, XVECEXP (x, i, j));
OSDN Git Service
