1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void merge_assigned_reloads (rtx);
435 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
437 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
439 static void do_input_reload (struct insn_chain *, struct reload *, int);
440 static void do_output_reload (struct insn_chain *, struct reload *, int);
441 static void emit_reload_insns (struct insn_chain *);
442 static void delete_output_reload (rtx, int, int, rtx);
443 static void delete_address_reloads (rtx, rtx);
444 static void delete_address_reloads_1 (rtx, rtx, rtx);
445 static rtx inc_for_reload (rtx, rtx, rtx, int);
447 static void add_auto_inc_notes (rtx, rtx);
449 static void copy_eh_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert ((flag_ira && optimize) || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
904 if (flag_ira && optimize)
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
1002 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1004 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1005 else if (CONSTANT_P (XEXP (x, 0))
1006 || (REG_P (XEXP (x, 0))
1007 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1008 || (GET_CODE (XEXP (x, 0)) == PLUS
1009 && REG_P (XEXP (XEXP (x, 0), 0))
1010 && (REGNO (XEXP (XEXP (x, 0), 0))
1011 < FIRST_PSEUDO_REGISTER)
1012 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1013 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1016 /* Make a new stack slot. Then indicate that something
1017 changed so we go back and recompute offsets for
1018 eliminable registers because the allocation of memory
1019 below might change some offset. reg_equiv_{mem,address}
1020 will be set up for this pseudo on the next pass around
1022 reg_equiv_memory_loc[i] = 0;
1023 reg_equiv_init[i] = 0;
1024 alter_reg (i, -1, true);
1028 if (caller_save_needed)
1029 setup_save_areas ();
1031 /* If we allocated another stack slot, redo elimination bookkeeping. */
1032 if (starting_frame_size != get_frame_size ())
1034 if (starting_frame_size && crtl->stack_alignment_needed)
1036 /* If we have a stack frame, we must align it now. The
1037 stack size may be a part of the offset computation for
1038 register elimination. So if this changes the stack size,
1039 then repeat the elimination bookkeeping. We don't
1040 realign when there is no stack, as that will cause a
1041 stack frame when none is needed should
1042 STARTING_FRAME_OFFSET not be already aligned to
1044 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1045 if (starting_frame_size != get_frame_size ())
1049 if (caller_save_needed)
1051 save_call_clobbered_regs ();
1052 /* That might have allocated new insn_chain structures. */
1053 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1056 calculate_needs_all_insns (global);
1058 if (! flag_ira || ! optimize)
1059 /* Don't do it for IRA. We need this info because we don't
1060 change live_throughout and dead_or_set for chains when IRA
1062 CLEAR_REG_SET (&spilled_pseudos);
1066 something_changed = 0;
1068 /* If we allocated any new memory locations, make another pass
1069 since it might have changed elimination offsets. */
1070 if (starting_frame_size != get_frame_size ())
1071 something_changed = 1;
1073 /* Even if the frame size remained the same, we might still have
1074 changed elimination offsets, e.g. if find_reloads called
1075 force_const_mem requiring the back end to allocate a constant
1076 pool base register that needs to be saved on the stack. */
1077 else if (!verify_initial_elim_offsets ())
1078 something_changed = 1;
1081 HARD_REG_SET to_spill;
1082 CLEAR_HARD_REG_SET (to_spill);
1083 update_eliminables (&to_spill);
1084 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1086 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1087 if (TEST_HARD_REG_BIT (to_spill, i))
1089 spill_hard_reg (i, 1);
1092 /* Regardless of the state of spills, if we previously had
1093 a register that we thought we could eliminate, but now can
1094 not eliminate, we must run another pass.
1096 Consider pseudos which have an entry in reg_equiv_* which
1097 reference an eliminable register. We must make another pass
1098 to update reg_equiv_* so that we do not substitute in the
1099 old value from when we thought the elimination could be
1101 something_changed = 1;
1105 select_reload_regs ();
1109 if (insns_need_reload != 0 || did_spill)
1110 something_changed |= finish_spills (global);
1112 if (! something_changed)
1115 if (caller_save_needed)
1116 delete_caller_save_insns ();
1118 obstack_free (&reload_obstack, reload_firstobj);
1121 /* If global-alloc was run, notify it of any register eliminations we have
1124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1125 if (ep->can_eliminate)
1126 mark_elimination (ep->from, ep->to);
1128 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1129 If that insn didn't set the register (i.e., it copied the register to
1130 memory), just delete that insn instead of the equivalencing insn plus
1131 anything now dead. If we call delete_dead_insn on that insn, we may
1132 delete the insn that actually sets the register if the register dies
1133 there and that is incorrect. */
1135 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1137 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1140 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1142 rtx equiv_insn = XEXP (list, 0);
1144 /* If we already deleted the insn or if it may trap, we can't
1145 delete it. The latter case shouldn't happen, but can
1146 if an insn has a variable address, gets a REG_EH_REGION
1147 note added to it, and then gets converted into a load
1148 from a constant address. */
1149 if (NOTE_P (equiv_insn)
1150 || can_throw_internal (equiv_insn))
1152 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1153 delete_dead_insn (equiv_insn);
1155 SET_INSN_DELETED (equiv_insn);
1160 /* Use the reload registers where necessary
1161 by generating move instructions to move the must-be-register
1162 values into or out of the reload registers. */
1164 if (insns_need_reload != 0 || something_needs_elimination
1165 || something_needs_operands_changed)
1167 HOST_WIDE_INT old_frame_size = get_frame_size ();
1169 reload_as_needed (global);
1171 gcc_assert (old_frame_size == get_frame_size ());
1173 gcc_assert (verify_initial_elim_offsets ());
1176 /* If we were able to eliminate the frame pointer, show that it is no
1177 longer live at the start of any basic block. If it ls live by
1178 virtue of being in a pseudo, that pseudo will be marked live
1179 and hence the frame pointer will be known to be live via that
1182 if (! frame_pointer_needed)
1184 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1186 /* Come here (with failure set nonzero) if we can't get enough spill
1190 CLEAR_REG_SET (&changed_allocation_pseudos);
1191 CLEAR_REG_SET (&spilled_pseudos);
1192 reload_in_progress = 0;
1194 /* Now eliminate all pseudo regs by modifying them into
1195 their equivalent memory references.
1196 The REG-rtx's for the pseudos are modified in place,
1197 so all insns that used to refer to them now refer to memory.
1199 For a reg that has a reg_equiv_address, all those insns
1200 were changed by reloading so that no insns refer to it any longer;
1201 but the DECL_RTL of a variable decl may refer to it,
1202 and if so this causes the debugging info to mention the variable. */
1204 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1208 if (reg_equiv_mem[i])
1209 addr = XEXP (reg_equiv_mem[i], 0);
1211 if (reg_equiv_address[i])
1212 addr = reg_equiv_address[i];
1216 if (reg_renumber[i] < 0)
1218 rtx reg = regno_reg_rtx[i];
1220 REG_USERVAR_P (reg) = 0;
1221 PUT_CODE (reg, MEM);
1222 XEXP (reg, 0) = addr;
1223 if (reg_equiv_memory_loc[i])
1224 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1227 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1228 MEM_ATTRS (reg) = 0;
1230 MEM_NOTRAP_P (reg) = 1;
1232 else if (reg_equiv_mem[i])
1233 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We must set reload_completed now since the cleanup_subreg_operands call
1238 below will re-recognize each insn and reload may have generated insns
1239 which are only valid during and after reload. */
1240 reload_completed = 1;
1242 /* Make a pass over all the insns and delete all USEs which we inserted
1243 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1244 notes. Delete all CLOBBER insns, except those that refer to the return
1245 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1246 from misarranging variable-array code, and simplify (subreg (reg))
1247 operands. Strip and regenerate REG_INC notes that may have been moved
1250 for (insn = first; insn; insn = NEXT_INSN (insn))
1256 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1257 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1259 if ((GET_CODE (PATTERN (insn)) == USE
1260 /* We mark with QImode USEs introduced by reload itself. */
1261 && (GET_MODE (insn) == QImode
1262 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1263 || (GET_CODE (PATTERN (insn)) == CLOBBER
1264 && (!MEM_P (XEXP (PATTERN (insn), 0))
1265 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1266 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1267 && XEXP (XEXP (PATTERN (insn), 0), 0)
1268 != stack_pointer_rtx))
1269 && (!REG_P (XEXP (PATTERN (insn), 0))
1270 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1276 /* Some CLOBBERs may survive until here and still reference unassigned
1277 pseudos with const equivalent, which may in turn cause ICE in later
1278 passes if the reference remains in place. */
1279 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1280 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1281 VOIDmode, PATTERN (insn));
1283 /* Discard obvious no-ops, even without -O. This optimization
1284 is fast and doesn't interfere with debugging. */
1285 if (NONJUMP_INSN_P (insn)
1286 && GET_CODE (PATTERN (insn)) == SET
1287 && REG_P (SET_SRC (PATTERN (insn)))
1288 && REG_P (SET_DEST (PATTERN (insn)))
1289 && (REGNO (SET_SRC (PATTERN (insn)))
1290 == REGNO (SET_DEST (PATTERN (insn)))))
1296 pnote = ®_NOTES (insn);
1299 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1300 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1301 || REG_NOTE_KIND (*pnote) == REG_INC)
1302 *pnote = XEXP (*pnote, 1);
1304 pnote = &XEXP (*pnote, 1);
1308 add_auto_inc_notes (insn, PATTERN (insn));
1311 /* Simplify (subreg (reg)) if it appears as an operand. */
1312 cleanup_subreg_operands (insn);
1314 /* Clean up invalid ASMs so that they don't confuse later passes.
1316 if (asm_noperands (PATTERN (insn)) >= 0)
1318 extract_insn (insn);
1319 if (!constrain_operands (1))
1321 error_for_asm (insn,
1322 "%<asm%> operand has impossible constraints");
1329 /* If we are doing generic stack checking, give a warning if this
1330 function's frame size is larger than we expect. */
1331 if (flag_stack_check == GENERIC_STACK_CHECK)
1333 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1334 static int verbose_warned = 0;
1336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1337 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1338 size += UNITS_PER_WORD;
1340 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1342 warning (0, "frame size too large for reliable stack checking");
1343 if (! verbose_warned)
1345 warning (0, "try reducing the number of local variables");
1351 /* Indicate that we no longer have known memory locations or constants. */
1352 if (reg_equiv_constant)
1353 free (reg_equiv_constant);
1354 if (reg_equiv_invariant)
1355 free (reg_equiv_invariant);
1356 reg_equiv_constant = 0;
1357 reg_equiv_invariant = 0;
1358 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1359 reg_equiv_memory_loc = 0;
1361 free (temp_pseudo_reg_arr);
1363 if (offsets_known_at)
1364 free (offsets_known_at);
1368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1369 if (reg_equiv_alt_mem_list[i])
1370 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1371 free (reg_equiv_alt_mem_list);
1373 free (reg_equiv_mem);
1375 free (reg_equiv_address);
1376 free (reg_max_ref_width);
1377 free (reg_old_renumber);
1378 free (pseudo_previous_regs);
1379 free (pseudo_forbidden_regs);
1381 CLEAR_HARD_REG_SET (used_spill_regs);
1382 for (i = 0; i < n_spills; i++)
1383 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1385 /* Free all the insn_chain structures at once. */
1386 obstack_free (&reload_obstack, reload_startobj);
1387 unused_insn_chains = 0;
1388 fixup_abnormal_edges ();
1390 /* Replacing pseudos with their memory equivalents might have
1391 created shared rtx. Subsequent passes would get confused
1392 by this, so unshare everything here. */
1393 unshare_all_rtl_again (first);
1395 #ifdef STACK_BOUNDARY
1396 /* init_emit has set the alignment of the hard frame pointer
1397 to STACK_BOUNDARY. It is very likely no longer valid if
1398 the hard frame pointer was used for register allocation. */
1399 if (!frame_pointer_needed)
1400 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1406 /* Yet another special case. Unfortunately, reg-stack forces people to
1407 write incorrect clobbers in asm statements. These clobbers must not
1408 cause the register to appear in bad_spill_regs, otherwise we'll call
1409 fatal_insn later. We clear the corresponding regnos in the live
1410 register sets to avoid this.
1411 The whole thing is rather sick, I'm afraid. */
1414 maybe_fix_stack_asms (void)
1417 const char *constraints[MAX_RECOG_OPERANDS];
1418 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1419 struct insn_chain *chain;
1421 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1424 HARD_REG_SET clobbered, allowed;
1427 if (! INSN_P (chain->insn)
1428 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1430 pat = PATTERN (chain->insn);
1431 if (GET_CODE (pat) != PARALLEL)
1434 CLEAR_HARD_REG_SET (clobbered);
1435 CLEAR_HARD_REG_SET (allowed);
1437 /* First, make a mask of all stack regs that are clobbered. */
1438 for (i = 0; i < XVECLEN (pat, 0); i++)
1440 rtx t = XVECEXP (pat, 0, i);
1441 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1442 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1445 /* Get the operand values and constraints out of the insn. */
1446 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1447 constraints, operand_mode, NULL);
1449 /* For every operand, see what registers are allowed. */
1450 for (i = 0; i < noperands; i++)
1452 const char *p = constraints[i];
1453 /* For every alternative, we compute the class of registers allowed
1454 for reloading in CLS, and merge its contents into the reg set
1456 int cls = (int) NO_REGS;
1462 if (c == '\0' || c == ',' || c == '#')
1464 /* End of one alternative - mark the regs in the current
1465 class, and reset the class. */
1466 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1472 } while (c != '\0' && c != ',');
1480 case '=': case '+': case '*': case '%': case '?': case '!':
1481 case '0': case '1': case '2': case '3': case '4': case '<':
1482 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1483 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1484 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1485 case TARGET_MEM_CONSTRAINT:
1489 cls = (int) reg_class_subunion[cls]
1490 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1495 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1499 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1500 cls = (int) reg_class_subunion[cls]
1501 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1503 cls = (int) reg_class_subunion[cls]
1504 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1506 p += CONSTRAINT_LEN (c, p);
1509 /* Those of the registers which are clobbered, but allowed by the
1510 constraints, must be usable as reload registers. So clear them
1511 out of the life information. */
1512 AND_HARD_REG_SET (allowed, clobbered);
1513 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1514 if (TEST_HARD_REG_BIT (allowed, i))
1516 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1517 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1524 /* Copy the global variables n_reloads and rld into the corresponding elts
1527 copy_reloads (struct insn_chain *chain)
1529 chain->n_reloads = n_reloads;
1530 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1531 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1532 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1535 /* Walk the chain of insns, and determine for each whether it needs reloads
1536 and/or eliminations. Build the corresponding insns_need_reload list, and
1537 set something_needs_elimination as appropriate. */
1539 calculate_needs_all_insns (int global)
1541 struct insn_chain **pprev_reload = &insns_need_reload;
1542 struct insn_chain *chain, *next = 0;
1544 something_needs_elimination = 0;
1546 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1547 for (chain = reload_insn_chain; chain != 0; chain = next)
1549 rtx insn = chain->insn;
1553 /* Clear out the shortcuts. */
1554 chain->n_reloads = 0;
1555 chain->need_elim = 0;
1556 chain->need_reload = 0;
1557 chain->need_operand_change = 0;
1559 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1560 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1561 what effects this has on the known offsets at labels. */
1563 if (LABEL_P (insn) || JUMP_P (insn)
1564 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1565 set_label_offsets (insn, insn, 0);
1569 rtx old_body = PATTERN (insn);
1570 int old_code = INSN_CODE (insn);
1571 rtx old_notes = REG_NOTES (insn);
1572 int did_elimination = 0;
1573 int operands_changed = 0;
1574 rtx set = single_set (insn);
1576 /* Skip insns that only set an equivalence. */
1577 if (set && REG_P (SET_DEST (set))
1578 && reg_renumber[REGNO (SET_DEST (set))] < 0
1579 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1580 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1581 && reg_equiv_init[REGNO (SET_DEST (set))])
1584 /* If needed, eliminate any eliminable registers. */
1585 if (num_eliminable || num_eliminable_invariants)
1586 did_elimination = eliminate_regs_in_insn (insn, 0);
1588 /* Analyze the instruction. */
1589 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1590 global, spill_reg_order);
1592 /* If a no-op set needs more than one reload, this is likely
1593 to be something that needs input address reloads. We
1594 can't get rid of this cleanly later, and it is of no use
1595 anyway, so discard it now.
1596 We only do this when expensive_optimizations is enabled,
1597 since this complements reload inheritance / output
1598 reload deletion, and it can make debugging harder. */
1599 if (flag_expensive_optimizations && n_reloads > 1)
1601 rtx set = single_set (insn);
1604 ((SET_SRC (set) == SET_DEST (set)
1605 && REG_P (SET_SRC (set))
1606 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1607 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1608 && reg_renumber[REGNO (SET_SRC (set))] < 0
1609 && reg_renumber[REGNO (SET_DEST (set))] < 0
1610 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1611 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1612 && rtx_equal_p (reg_equiv_memory_loc
1613 [REGNO (SET_SRC (set))],
1614 reg_equiv_memory_loc
1615 [REGNO (SET_DEST (set))]))))
1617 if (flag_ira && optimize)
1618 /* Inform IRA about the insn deletion. */
1619 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1620 REGNO (SET_SRC (set)));
1622 /* Delete it from the reload chain. */
1624 chain->prev->next = next;
1626 reload_insn_chain = next;
1628 next->prev = chain->prev;
1629 chain->next = unused_insn_chains;
1630 unused_insn_chains = chain;
1635 update_eliminable_offsets ();
1637 /* Remember for later shortcuts which insns had any reloads or
1638 register eliminations. */
1639 chain->need_elim = did_elimination;
1640 chain->need_reload = n_reloads > 0;
1641 chain->need_operand_change = operands_changed;
1643 /* Discard any register replacements done. */
1644 if (did_elimination)
1646 obstack_free (&reload_obstack, reload_insn_firstobj);
1647 PATTERN (insn) = old_body;
1648 INSN_CODE (insn) = old_code;
1649 REG_NOTES (insn) = old_notes;
1650 something_needs_elimination = 1;
1653 something_needs_operands_changed |= operands_changed;
1657 copy_reloads (chain);
1658 *pprev_reload = chain;
1659 pprev_reload = &chain->next_need_reload;
1666 /* Comparison function for qsort to decide which of two reloads
1667 should be handled first. *P1 and *P2 are the reload numbers. */
1670 reload_reg_class_lower (const void *r1p, const void *r2p)
1672 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1675 /* Consider required reloads before optional ones. */
1676 t = rld[r1].optional - rld[r2].optional;
1680 /* Count all solitary classes before non-solitary ones. */
1681 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1682 - (reg_class_size[(int) rld[r1].rclass] == 1));
1686 /* Aside from solitaires, consider all multi-reg groups first. */
1687 t = rld[r2].nregs - rld[r1].nregs;
1691 /* Consider reloads in order of increasing reg-class number. */
1692 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1696 /* If reloads are equally urgent, sort by reload number,
1697 so that the results of qsort leave nothing to chance. */
1701 /* The cost of spilling each hard reg. */
1702 static int spill_cost[FIRST_PSEUDO_REGISTER];
1704 /* When spilling multiple hard registers, we use SPILL_COST for the first
1705 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1706 only the first hard reg for a multi-reg pseudo. */
1707 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1709 /* Map of hard regno to pseudo regno currently occupying the hard
1711 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1713 /* Update the spill cost arrays, considering that pseudo REG is live. */
1716 count_pseudo (int reg)
1718 int freq = REG_FREQ (reg);
1719 int r = reg_renumber[reg];
1722 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1723 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1724 /* Ignore spilled pseudo-registers which can be here only if IRA
1726 || (flag_ira && optimize && r < 0))
1729 SET_REGNO_REG_SET (&pseudos_counted, reg);
1731 gcc_assert (r >= 0);
1733 spill_add_cost[r] += freq;
1734 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1737 hard_regno_to_pseudo_regno[r + nregs] = reg;
1738 spill_cost[r + nregs] += freq;
1742 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1743 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1746 order_regs_for_reload (struct insn_chain *chain)
1749 HARD_REG_SET used_by_pseudos;
1750 HARD_REG_SET used_by_pseudos2;
1751 reg_set_iterator rsi;
1753 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1755 memset (spill_cost, 0, sizeof spill_cost);
1756 memset (spill_add_cost, 0, sizeof spill_add_cost);
1757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1758 hard_regno_to_pseudo_regno[i] = -1;
1760 /* Count number of uses of each hard reg by pseudo regs allocated to it
1761 and then order them by decreasing use. First exclude hard registers
1762 that are live in or across this insn. */
1764 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1765 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1766 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1767 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1769 /* Now find out which pseudos are allocated to it, and update
1771 CLEAR_REG_SET (&pseudos_counted);
1773 EXECUTE_IF_SET_IN_REG_SET
1774 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1778 EXECUTE_IF_SET_IN_REG_SET
1779 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1783 CLEAR_REG_SET (&pseudos_counted);
1786 /* Vector of reload-numbers showing the order in which the reloads should
1788 static short reload_order[MAX_RELOADS];
1790 /* This is used to keep track of the spill regs used in one insn. */
1791 static HARD_REG_SET used_spill_regs_local;
1793 /* We decided to spill hard register SPILLED, which has a size of
1794 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1795 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1796 update SPILL_COST/SPILL_ADD_COST. */
1799 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1801 int freq = REG_FREQ (reg);
1802 int r = reg_renumber[reg];
1803 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1805 /* Ignore spilled pseudo-registers which can be here only if IRA is
1807 if ((flag_ira && optimize && r < 0)
1808 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1809 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1812 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1814 spill_add_cost[r] -= freq;
1817 hard_regno_to_pseudo_regno[r + nregs] = -1;
1818 spill_cost[r + nregs] -= freq;
1822 /* Find reload register to use for reload number ORDER. */
1825 find_reg (struct insn_chain *chain, int order)
1827 int rnum = reload_order[order];
1828 struct reload *rl = rld + rnum;
1829 int best_cost = INT_MAX;
1831 unsigned int i, j, n;
1833 HARD_REG_SET not_usable;
1834 HARD_REG_SET used_by_other_reload;
1835 reg_set_iterator rsi;
1836 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1837 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1839 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1840 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1841 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1843 CLEAR_HARD_REG_SET (used_by_other_reload);
1844 for (k = 0; k < order; k++)
1846 int other = reload_order[k];
1848 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1849 for (j = 0; j < rld[other].nregs; j++)
1850 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 #ifdef REG_ALLOC_ORDER
1856 unsigned int regno = reg_alloc_order[i];
1858 unsigned int regno = i;
1861 if (! TEST_HARD_REG_BIT (not_usable, regno)
1862 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1863 && HARD_REGNO_MODE_OK (regno, rl->mode))
1865 int this_cost = spill_cost[regno];
1867 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1869 for (j = 1; j < this_nregs; j++)
1871 this_cost += spill_add_cost[regno + j];
1872 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1873 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1879 if (flag_ira && optimize)
1881 /* Ask IRA to find a better pseudo-register for
1883 for (n = j = 0; j < this_nregs; j++)
1885 int r = hard_regno_to_pseudo_regno[regno + j];
1889 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1890 regno_pseudo_regs[n++] = r;
1892 regno_pseudo_regs[n++] = -1;
1894 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1895 best_regno_pseudo_regs,
1902 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1903 if (regno_pseudo_regs[j] < 0)
1910 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1912 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1914 if (this_cost < best_cost
1915 /* Among registers with equal cost, prefer caller-saved ones, or
1916 use REG_ALLOC_ORDER if it is defined. */
1917 || (this_cost == best_cost
1918 #ifdef REG_ALLOC_ORDER
1919 && (inv_reg_alloc_order[regno]
1920 < inv_reg_alloc_order[best_reg])
1922 && call_used_regs[regno]
1923 && ! call_used_regs[best_reg]
1928 best_cost = this_cost;
1936 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1938 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1939 rl->regno = best_reg;
1941 EXECUTE_IF_SET_IN_REG_SET
1942 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1944 count_spilled_pseudo (best_reg, rl->nregs, j);
1947 EXECUTE_IF_SET_IN_REG_SET
1948 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1950 count_spilled_pseudo (best_reg, rl->nregs, j);
1953 for (i = 0; i < rl->nregs; i++)
1955 gcc_assert (spill_cost[best_reg + i] == 0);
1956 gcc_assert (spill_add_cost[best_reg + i] == 0);
1957 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1958 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1963 /* Find more reload regs to satisfy the remaining need of an insn, which
1965 Do it by ascending class number, since otherwise a reg
1966 might be spilled for a big class and might fail to count
1967 for a smaller class even though it belongs to that class. */
1970 find_reload_regs (struct insn_chain *chain)
1974 /* In order to be certain of getting the registers we need,
1975 we must sort the reloads into order of increasing register class.
1976 Then our grabbing of reload registers will parallel the process
1977 that provided the reload registers. */
1978 for (i = 0; i < chain->n_reloads; i++)
1980 /* Show whether this reload already has a hard reg. */
1981 if (chain->rld[i].reg_rtx)
1983 int regno = REGNO (chain->rld[i].reg_rtx);
1984 chain->rld[i].regno = regno;
1986 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1989 chain->rld[i].regno = -1;
1990 reload_order[i] = i;
1993 n_reloads = chain->n_reloads;
1994 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1996 CLEAR_HARD_REG_SET (used_spill_regs_local);
1999 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2001 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2003 /* Compute the order of preference for hard registers to spill. */
2005 order_regs_for_reload (chain);
2007 for (i = 0; i < n_reloads; i++)
2009 int r = reload_order[i];
2011 /* Ignore reloads that got marked inoperative. */
2012 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2013 && ! rld[r].optional
2014 && rld[r].regno == -1)
2015 if (! find_reg (chain, i))
2018 fprintf (dump_file, "reload failure for reload %d\n", r);
2019 spill_failure (chain->insn, rld[r].rclass);
2025 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2026 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2028 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2032 select_reload_regs (void)
2034 struct insn_chain *chain;
2036 /* Try to satisfy the needs for each insn. */
2037 for (chain = insns_need_reload; chain != 0;
2038 chain = chain->next_need_reload)
2039 find_reload_regs (chain);
2042 /* Delete all insns that were inserted by emit_caller_save_insns during
2045 delete_caller_save_insns (void)
2047 struct insn_chain *c = reload_insn_chain;
2051 while (c != 0 && c->is_caller_save_insn)
2053 struct insn_chain *next = c->next;
2056 if (c == reload_insn_chain)
2057 reload_insn_chain = next;
2061 next->prev = c->prev;
2063 c->prev->next = next;
2064 c->next = unused_insn_chains;
2065 unused_insn_chains = c;
2073 /* Handle the failure to find a register to spill.
2074 INSN should be one of the insns which needed this particular spill reg. */
2077 spill_failure (rtx insn, enum reg_class rclass)
2079 if (asm_noperands (PATTERN (insn)) >= 0)
2080 error_for_asm (insn, "can't find a register in class %qs while "
2081 "reloading %<asm%>",
2082 reg_class_names[rclass]);
2085 error ("unable to find a register to spill in class %qs",
2086 reg_class_names[rclass]);
2090 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2091 debug_reload_to_stream (dump_file);
2093 fatal_insn ("this is the insn:", insn);
2097 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2098 data that is dead in INSN. */
2101 delete_dead_insn (rtx insn)
2103 rtx prev = prev_real_insn (insn);
2106 /* If the previous insn sets a register that dies in our insn, delete it
2108 if (prev && GET_CODE (PATTERN (prev)) == SET
2109 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2110 && reg_mentioned_p (prev_dest, PATTERN (insn))
2111 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2112 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2113 delete_dead_insn (prev);
2115 SET_INSN_DELETED (insn);
2118 /* Modify the home of pseudo-reg I.
2119 The new home is present in reg_renumber[I].
2121 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2122 or it may be -1, meaning there is none or it is not relevant.
2123 This is used so that all pseudos spilled from a given hard reg
2124 can share one stack slot. */
2127 alter_reg (int i, int from_reg, bool dont_share_p)
2129 /* When outputting an inline function, this can happen
2130 for a reg that isn't actually used. */
2131 if (regno_reg_rtx[i] == 0)
2134 /* If the reg got changed to a MEM at rtl-generation time,
2136 if (!REG_P (regno_reg_rtx[i]))
2139 /* Modify the reg-rtx to contain the new hard reg
2140 number or else to contain its pseudo reg number. */
2141 SET_REGNO (regno_reg_rtx[i],
2142 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2144 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2145 allocate a stack slot for it. */
2147 if (reg_renumber[i] < 0
2148 && REG_N_REFS (i) > 0
2149 && reg_equiv_constant[i] == 0
2150 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2151 && reg_equiv_memory_loc[i] == 0)
2154 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2155 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2156 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2157 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2158 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2160 bool shared_p = false;
2162 if (flag_ira && optimize)
2163 /* Mark the spill for IRA. */
2164 SET_REGNO_REG_SET (&spilled_pseudos, i);
2165 x = (dont_share_p || ! flag_ira || ! optimize
2166 ? NULL_RTX : ira_reuse_stack_slot (i, inherent_size, total_size));
2169 /* Each pseudo reg has an inherent size which comes from its own mode,
2170 and a total size which provides room for paradoxical subregs
2171 which refer to the pseudo reg in wider modes.
2173 We can use a slot already allocated if it provides both
2174 enough inherent space and enough total space.
2175 Otherwise, we allocate a new slot, making sure that it has no less
2176 inherent space, and no less total space, then the previous slot. */
2177 else if (from_reg == -1 || (! dont_share_p && flag_ira && optimize))
2179 alias_set_type alias_set = new_alias_set ();
2181 /* No known place to spill from => no slot to reuse. */
2182 x = assign_stack_local (mode, total_size,
2183 min_align > inherent_align
2184 || total_size > inherent_size ? -1 : 0);
2185 if (BYTES_BIG_ENDIAN)
2186 /* Cancel the big-endian correction done in assign_stack_local.
2187 Get the address of the beginning of the slot.
2188 This is so we can do a big-endian correction unconditionally
2190 adjust = inherent_size - total_size;
2192 /* Nothing can alias this slot except this pseudo. */
2193 set_mem_alias_set (x, alias_set);
2194 dse_record_singleton_alias_set (alias_set, mode);
2196 if (! dont_share_p && flag_ira && optimize)
2197 /* Inform IRA about allocation a new stack slot. */
2198 ira_mark_new_stack_slot (x, i, total_size);
2201 /* Reuse a stack slot if possible. */
2202 else if (spill_stack_slot[from_reg] != 0
2203 && spill_stack_slot_width[from_reg] >= total_size
2204 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2206 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2207 x = spill_stack_slot[from_reg];
2208 /* Allocate a bigger slot. */
2211 /* Compute maximum size needed, both for inherent size
2212 and for total size. */
2215 if (spill_stack_slot[from_reg])
2217 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2219 mode = GET_MODE (spill_stack_slot[from_reg]);
2220 if (spill_stack_slot_width[from_reg] > total_size)
2221 total_size = spill_stack_slot_width[from_reg];
2222 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2223 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2226 /* Make a slot with that size. */
2227 x = assign_stack_local (mode, total_size,
2228 min_align > inherent_align
2229 || total_size > inherent_size ? -1 : 0);
2232 /* All pseudos mapped to this slot can alias each other. */
2233 if (spill_stack_slot[from_reg])
2235 alias_set_type alias_set
2236 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2237 set_mem_alias_set (x, alias_set);
2238 dse_invalidate_singleton_alias_set (alias_set);
2242 alias_set_type alias_set = new_alias_set ();
2243 set_mem_alias_set (x, alias_set);
2244 dse_record_singleton_alias_set (alias_set, mode);
2247 if (BYTES_BIG_ENDIAN)
2249 /* Cancel the big-endian correction done in assign_stack_local.
2250 Get the address of the beginning of the slot.
2251 This is so we can do a big-endian correction unconditionally
2253 adjust = GET_MODE_SIZE (mode) - total_size;
2256 = adjust_address_nv (x, mode_for_size (total_size
2262 spill_stack_slot[from_reg] = stack_slot;
2263 spill_stack_slot_width[from_reg] = total_size;
2266 /* On a big endian machine, the "address" of the slot
2267 is the address of the low part that fits its inherent mode. */
2268 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2269 adjust += (total_size - inherent_size);
2271 /* If we have any adjustment to make, or if the stack slot is the
2272 wrong mode, make a new stack slot. */
2273 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2275 /* If we have a decl for the original register, set it for the
2276 memory. If this is a shared MEM, make a copy. */
2280 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2282 else if (REG_EXPR (regno_reg_rtx[i])
2283 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2285 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2287 /* We can do this only for the DECLs home pseudo, not for
2288 any copies of it, since otherwise when the stack slot
2289 is reused, nonoverlapping_memrefs_p might think they
2291 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2293 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2296 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2300 /* Save the stack slot for later. */
2301 reg_equiv_memory_loc[i] = x;
2305 /* Mark the slots in regs_ever_live for the hard regs used by
2306 pseudo-reg number REGNO, accessed in MODE. */
2309 mark_home_live_1 (int regno, enum machine_mode mode)
2313 i = reg_renumber[regno];
2316 lim = end_hard_regno (mode, i);
2318 df_set_regs_ever_live(i++, true);
2321 /* Mark the slots in regs_ever_live for the hard regs
2322 used by pseudo-reg number REGNO. */
2325 mark_home_live (int regno)
2327 if (reg_renumber[regno] >= 0)
2328 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2331 /* This function handles the tracking of elimination offsets around branches.
2333 X is a piece of RTL being scanned.
2335 INSN is the insn that it came from, if any.
2337 INITIAL_P is nonzero if we are to set the offset to be the initial
2338 offset and zero if we are setting the offset of the label to be the
2342 set_label_offsets (rtx x, rtx insn, int initial_p)
2344 enum rtx_code code = GET_CODE (x);
2347 struct elim_table *p;
2352 if (LABEL_REF_NONLOCAL_P (x))
2357 /* ... fall through ... */
2360 /* If we know nothing about this label, set the desired offsets. Note
2361 that this sets the offset at a label to be the offset before a label
2362 if we don't know anything about the label. This is not correct for
2363 the label after a BARRIER, but is the best guess we can make. If
2364 we guessed wrong, we will suppress an elimination that might have
2365 been possible had we been able to guess correctly. */
2367 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2369 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2370 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2371 = (initial_p ? reg_eliminate[i].initial_offset
2372 : reg_eliminate[i].offset);
2373 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2376 /* Otherwise, if this is the definition of a label and it is
2377 preceded by a BARRIER, set our offsets to the known offset of
2381 && (tem = prev_nonnote_insn (insn)) != 0
2383 set_offsets_for_label (insn);
2385 /* If neither of the above cases is true, compare each offset
2386 with those previously recorded and suppress any eliminations
2387 where the offsets disagree. */
2389 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2390 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2391 != (initial_p ? reg_eliminate[i].initial_offset
2392 : reg_eliminate[i].offset))
2393 reg_eliminate[i].can_eliminate = 0;
2398 set_label_offsets (PATTERN (insn), insn, initial_p);
2400 /* ... fall through ... */
2404 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2405 to indirectly and hence must have all eliminations at their
2407 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2408 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2409 set_label_offsets (XEXP (tem, 0), insn, 1);
2415 /* Each of the labels in the parallel or address vector must be
2416 at their initial offsets. We want the first field for PARALLEL
2417 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2419 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2420 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2425 /* We only care about setting PC. If the source is not RETURN,
2426 IF_THEN_ELSE, or a label, disable any eliminations not at
2427 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2428 isn't one of those possibilities. For branches to a label,
2429 call ourselves recursively.
2431 Note that this can disable elimination unnecessarily when we have
2432 a non-local goto since it will look like a non-constant jump to
2433 someplace in the current function. This isn't a significant
2434 problem since such jumps will normally be when all elimination
2435 pairs are back to their initial offsets. */
2437 if (SET_DEST (x) != pc_rtx)
2440 switch (GET_CODE (SET_SRC (x)))
2447 set_label_offsets (SET_SRC (x), insn, initial_p);
2451 tem = XEXP (SET_SRC (x), 1);
2452 if (GET_CODE (tem) == LABEL_REF)
2453 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2454 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2457 tem = XEXP (SET_SRC (x), 2);
2458 if (GET_CODE (tem) == LABEL_REF)
2459 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2460 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2468 /* If we reach here, all eliminations must be at their initial
2469 offset because we are doing a jump to a variable address. */
2470 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2471 if (p->offset != p->initial_offset)
2472 p->can_eliminate = 0;
2480 /* Scan X and replace any eliminable registers (such as fp) with a
2481 replacement (such as sp), plus an offset.
2483 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2484 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2485 MEM, we are allowed to replace a sum of a register and the constant zero
2486 with the register, which we cannot do outside a MEM. In addition, we need
2487 to record the fact that a register is referenced outside a MEM.
2489 If INSN is an insn, it is the insn containing X. If we replace a REG
2490 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2491 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2492 the REG is being modified.
2494 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2495 That's used when we eliminate in expressions stored in notes.
2496 This means, do not set ref_outside_mem even if the reference
2499 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2500 replacements done assuming all offsets are at their initial values. If
2501 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2502 encounter, return the actual location so that find_reloads will do
2503 the proper thing. */
2506 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2507 bool may_use_invariant)
2509 enum rtx_code code = GET_CODE (x);
2510 struct elim_table *ep;
2517 if (! current_function_decl)
2540 /* First handle the case where we encounter a bare register that
2541 is eliminable. Replace it with a PLUS. */
2542 if (regno < FIRST_PSEUDO_REGISTER)
2544 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2546 if (ep->from_rtx == x && ep->can_eliminate)
2547 return plus_constant (ep->to_rtx, ep->previous_offset);
2550 else if (reg_renumber && reg_renumber[regno] < 0
2551 && reg_equiv_invariant && reg_equiv_invariant[regno])
2553 if (may_use_invariant)
2554 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2555 mem_mode, insn, true);
2556 /* There exists at least one use of REGNO that cannot be
2557 eliminated. Prevent the defining insn from being deleted. */
2558 reg_equiv_init[regno] = NULL_RTX;
2559 alter_reg (regno, -1, true);
2563 /* You might think handling MINUS in a manner similar to PLUS is a
2564 good idea. It is not. It has been tried multiple times and every
2565 time the change has had to have been reverted.
2567 Other parts of reload know a PLUS is special (gen_reload for example)
2568 and require special code to handle code a reloaded PLUS operand.
2570 Also consider backends where the flags register is clobbered by a
2571 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2572 lea instruction comes to mind). If we try to reload a MINUS, we
2573 may kill the flags register that was holding a useful value.
2575 So, please before trying to handle MINUS, consider reload as a
2576 whole instead of this little section as well as the backend issues. */
2578 /* If this is the sum of an eliminable register and a constant, rework
2580 if (REG_P (XEXP (x, 0))
2581 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2582 && CONSTANT_P (XEXP (x, 1)))
2584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2586 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2588 /* The only time we want to replace a PLUS with a REG (this
2589 occurs when the constant operand of the PLUS is the negative
2590 of the offset) is when we are inside a MEM. We won't want
2591 to do so at other times because that would change the
2592 structure of the insn in a way that reload can't handle.
2593 We special-case the commonest situation in
2594 eliminate_regs_in_insn, so just replace a PLUS with a
2595 PLUS here, unless inside a MEM. */
2596 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2597 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2600 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2601 plus_constant (XEXP (x, 1),
2602 ep->previous_offset));
2605 /* If the register is not eliminable, we are done since the other
2606 operand is a constant. */
2610 /* If this is part of an address, we want to bring any constant to the
2611 outermost PLUS. We will do this by doing register replacement in
2612 our operands and seeing if a constant shows up in one of them.
2614 Note that there is no risk of modifying the structure of the insn,
2615 since we only get called for its operands, thus we are either
2616 modifying the address inside a MEM, or something like an address
2617 operand of a load-address insn. */
2620 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2621 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2623 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2625 /* If one side is a PLUS and the other side is a pseudo that
2626 didn't get a hard register but has a reg_equiv_constant,
2627 we must replace the constant here since it may no longer
2628 be in the position of any operand. */
2629 if (GET_CODE (new0) == PLUS && REG_P (new1)
2630 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2631 && reg_renumber[REGNO (new1)] < 0
2632 && reg_equiv_constant != 0
2633 && reg_equiv_constant[REGNO (new1)] != 0)
2634 new1 = reg_equiv_constant[REGNO (new1)];
2635 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2636 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2637 && reg_renumber[REGNO (new0)] < 0
2638 && reg_equiv_constant[REGNO (new0)] != 0)
2639 new0 = reg_equiv_constant[REGNO (new0)];
2641 new_rtx = form_sum (new0, new1);
2643 /* As above, if we are not inside a MEM we do not want to
2644 turn a PLUS into something else. We might try to do so here
2645 for an addition of 0 if we aren't optimizing. */
2646 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2647 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2655 /* If this is the product of an eliminable register and a
2656 constant, apply the distribute law and move the constant out
2657 so that we have (plus (mult ..) ..). This is needed in order
2658 to keep load-address insns valid. This case is pathological.
2659 We ignore the possibility of overflow here. */
2660 if (REG_P (XEXP (x, 0))
2661 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2662 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2663 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2665 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2668 /* Refs inside notes don't count for this purpose. */
2669 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2670 || GET_CODE (insn) == INSN_LIST)))
2671 ep->ref_outside_mem = 1;
2674 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2675 ep->previous_offset * INTVAL (XEXP (x, 1)));
2678 /* ... fall through ... */
2682 /* See comments before PLUS about handling MINUS. */
2684 case DIV: case UDIV:
2685 case MOD: case UMOD:
2686 case AND: case IOR: case XOR:
2687 case ROTATERT: case ROTATE:
2688 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2690 case GE: case GT: case GEU: case GTU:
2691 case LE: case LT: case LEU: case LTU:
2693 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2694 rtx new1 = XEXP (x, 1)
2695 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2697 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2698 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2703 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2706 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2707 if (new_rtx != XEXP (x, 0))
2709 /* If this is a REG_DEAD note, it is not valid anymore.
2710 Using the eliminated version could result in creating a
2711 REG_DEAD note for the stack or frame pointer. */
2712 if (REG_NOTE_KIND (x) == REG_DEAD)
2714 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2717 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2721 /* ... fall through ... */
2724 /* Now do eliminations in the rest of the chain. If this was
2725 an EXPR_LIST, this might result in allocating more memory than is
2726 strictly needed, but it simplifies the code. */
2729 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2730 if (new_rtx != XEXP (x, 1))
2732 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2740 /* We do not support elimination of a register that is modified.
2741 elimination_effects has already make sure that this does not
2747 /* We do not support elimination of a register that is modified.
2748 elimination_effects has already make sure that this does not
2749 happen. The only remaining case we need to consider here is
2750 that the increment value may be an eliminable register. */
2751 if (GET_CODE (XEXP (x, 1)) == PLUS
2752 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2754 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2757 if (new_rtx != XEXP (XEXP (x, 1), 1))
2758 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2759 gen_rtx_PLUS (GET_MODE (x),
2760 XEXP (x, 0), new_rtx));
2764 case STRICT_LOW_PART:
2766 case SIGN_EXTEND: case ZERO_EXTEND:
2767 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2768 case FLOAT: case FIX:
2769 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2778 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2779 if (new_rtx != XEXP (x, 0))
2780 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2784 /* Similar to above processing, but preserve SUBREG_BYTE.
2785 Convert (subreg (mem)) to (mem) if not paradoxical.
2786 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2787 pseudo didn't get a hard reg, we must replace this with the
2788 eliminated version of the memory location because push_reload
2789 may do the replacement in certain circumstances. */
2790 if (REG_P (SUBREG_REG (x))
2791 && (GET_MODE_SIZE (GET_MODE (x))
2792 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2793 && reg_equiv_memory_loc != 0
2794 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2796 new_rtx = SUBREG_REG (x);
2799 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2801 if (new_rtx != SUBREG_REG (x))
2803 int x_size = GET_MODE_SIZE (GET_MODE (x));
2804 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2807 && ((x_size < new_size
2808 #ifdef WORD_REGISTER_OPERATIONS
2809 /* On these machines, combine can create rtl of the form
2810 (set (subreg:m1 (reg:m2 R) 0) ...)
2811 where m1 < m2, and expects something interesting to
2812 happen to the entire word. Moreover, it will use the
2813 (reg:m2 R) later, expecting all bits to be preserved.
2814 So if the number of words is the same, preserve the
2815 subreg so that push_reload can see it. */
2816 && ! ((x_size - 1) / UNITS_PER_WORD
2817 == (new_size -1 ) / UNITS_PER_WORD)
2820 || x_size == new_size)
2822 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2824 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2830 /* Our only special processing is to pass the mode of the MEM to our
2831 recursive call and copy the flags. While we are here, handle this
2832 case more efficiently. */
2834 replace_equiv_address_nv (x,
2835 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2839 /* Handle insn_list USE that a call to a pure function may generate. */
2840 new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2841 if (new_rtx != XEXP (x, 0))
2842 return gen_rtx_USE (GET_MODE (x), new_rtx);
2854 /* Process each of our operands recursively. If any have changed, make a
2856 fmt = GET_RTX_FORMAT (code);
2857 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2861 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2862 if (new_rtx != XEXP (x, i) && ! copied)
2864 x = shallow_copy_rtx (x);
2867 XEXP (x, i) = new_rtx;
2869 else if (*fmt == 'E')
2872 for (j = 0; j < XVECLEN (x, i); j++)
2874 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2875 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2877 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2881 x = shallow_copy_rtx (x);
2884 XVEC (x, i) = new_v;
2887 XVECEXP (x, i, j) = new_rtx;
2896 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2898 return eliminate_regs_1 (x, mem_mode, insn, false);
2901 /* Scan rtx X for modifications of elimination target registers. Update
2902 the table of eliminables to reflect the changed state. MEM_MODE is
2903 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2906 elimination_effects (rtx x, enum machine_mode mem_mode)
2908 enum rtx_code code = GET_CODE (x);
2909 struct elim_table *ep;
2934 /* First handle the case where we encounter a bare register that
2935 is eliminable. Replace it with a PLUS. */
2936 if (regno < FIRST_PSEUDO_REGISTER)
2938 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2940 if (ep->from_rtx == x && ep->can_eliminate)
2943 ep->ref_outside_mem = 1;
2948 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2949 && reg_equiv_constant[regno]
2950 && ! function_invariant_p (reg_equiv_constant[regno]))
2951 elimination_effects (reg_equiv_constant[regno], mem_mode);
2960 /* If we modify the source of an elimination rule, disable it. */
2961 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2962 if (ep->from_rtx == XEXP (x, 0))
2963 ep->can_eliminate = 0;
2965 /* If we modify the target of an elimination rule by adding a constant,
2966 update its offset. If we modify the target in any other way, we'll
2967 have to disable the rule as well. */
2968 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2969 if (ep->to_rtx == XEXP (x, 0))
2971 int size = GET_MODE_SIZE (mem_mode);
2973 /* If more bytes than MEM_MODE are pushed, account for them. */
2974 #ifdef PUSH_ROUNDING
2975 if (ep->to_rtx == stack_pointer_rtx)
2976 size = PUSH_ROUNDING (size);
2978 if (code == PRE_DEC || code == POST_DEC)
2980 else if (code == PRE_INC || code == POST_INC)
2982 else if (code == PRE_MODIFY || code == POST_MODIFY)
2984 if (GET_CODE (XEXP (x, 1)) == PLUS
2985 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2986 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2987 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2989 ep->can_eliminate = 0;
2993 /* These two aren't unary operators. */
2994 if (code == POST_MODIFY || code == PRE_MODIFY)
2997 /* Fall through to generic unary operation case. */
2998 case STRICT_LOW_PART:
3000 case SIGN_EXTEND: case ZERO_EXTEND:
3001 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3002 case FLOAT: case FIX:
3003 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3012 elimination_effects (XEXP (x, 0), mem_mode);
3016 if (REG_P (SUBREG_REG (x))
3017 && (GET_MODE_SIZE (GET_MODE (x))
3018 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3019 && reg_equiv_memory_loc != 0
3020 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3023 elimination_effects (SUBREG_REG (x), mem_mode);
3027 /* If using a register that is the source of an eliminate we still
3028 think can be performed, note it cannot be performed since we don't
3029 know how this register is used. */
3030 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3031 if (ep->from_rtx == XEXP (x, 0))
3032 ep->can_eliminate = 0;
3034 elimination_effects (XEXP (x, 0), mem_mode);
3038 /* If clobbering a register that is the replacement register for an
3039 elimination we still think can be performed, note that it cannot
3040 be performed. Otherwise, we need not be concerned about it. */
3041 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3042 if (ep->to_rtx == XEXP (x, 0))
3043 ep->can_eliminate = 0;
3045 elimination_effects (XEXP (x, 0), mem_mode);
3049 /* Check for setting a register that we know about. */
3050 if (REG_P (SET_DEST (x)))
3052 /* See if this is setting the replacement register for an
3055 If DEST is the hard frame pointer, we do nothing because we
3056 assume that all assignments to the frame pointer are for
3057 non-local gotos and are being done at a time when they are valid
3058 and do not disturb anything else. Some machines want to
3059 eliminate a fake argument pointer (or even a fake frame pointer)
3060 with either the real frame or the stack pointer. Assignments to
3061 the hard frame pointer must not prevent this elimination. */
3063 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3065 if (ep->to_rtx == SET_DEST (x)
3066 && SET_DEST (x) != hard_frame_pointer_rtx)
3068 /* If it is being incremented, adjust the offset. Otherwise,
3069 this elimination can't be done. */
3070 rtx src = SET_SRC (x);
3072 if (GET_CODE (src) == PLUS
3073 && XEXP (src, 0) == SET_DEST (x)
3074 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3075 ep->offset -= INTVAL (XEXP (src, 1));
3077 ep->can_eliminate = 0;
3081 elimination_effects (SET_DEST (x), 0);
3082 elimination_effects (SET_SRC (x), 0);
3086 /* Our only special processing is to pass the mode of the MEM to our
3088 elimination_effects (XEXP (x, 0), GET_MODE (x));
3095 fmt = GET_RTX_FORMAT (code);
3096 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3099 elimination_effects (XEXP (x, i), mem_mode);
3100 else if (*fmt == 'E')
3101 for (j = 0; j < XVECLEN (x, i); j++)
3102 elimination_effects (XVECEXP (x, i, j), mem_mode);
3106 /* Descend through rtx X and verify that no references to eliminable registers
3107 remain. If any do remain, mark the involved register as not
3111 check_eliminable_occurrences (rtx x)
3120 code = GET_CODE (x);
3122 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3124 struct elim_table *ep;
3126 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3127 if (ep->from_rtx == x)
3128 ep->can_eliminate = 0;
3132 fmt = GET_RTX_FORMAT (code);
3133 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3136 check_eliminable_occurrences (XEXP (x, i));
3137 else if (*fmt == 'E')
3140 for (j = 0; j < XVECLEN (x, i); j++)
3141 check_eliminable_occurrences (XVECEXP (x, i, j));
3146 /* Scan INSN and eliminate all eliminable registers in it.
3148 If REPLACE is nonzero, do the replacement destructively. Also
3149 delete the insn as dead it if it is setting an eliminable register.
3151 If REPLACE is zero, do all our allocations in reload_obstack.
3153 If no eliminations were done and this insn doesn't require any elimination
3154 processing (these are not identical conditions: it might be updating sp,
3155 but not referencing fp; this needs to be seen during reload_as_needed so
3156 that the offset between fp and sp can be taken into consideration), zero
3157 is returned. Otherwise, 1 is returned. */
3160 eliminate_regs_in_insn (rtx insn, int replace)
3162 int icode = recog_memoized (insn);
3163 rtx old_body = PATTERN (insn);
3164 int insn_is_asm = asm_noperands (old_body) >= 0;
3165 rtx old_set = single_set (insn);
3169 rtx substed_operand[MAX_RECOG_OPERANDS];
3170 rtx orig_operand[MAX_RECOG_OPERANDS];
3171 struct elim_table *ep;
3172 rtx plus_src, plus_cst_src;
3174 if (! insn_is_asm && icode < 0)
3176 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3177 || GET_CODE (PATTERN (insn)) == CLOBBER
3178 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3179 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3180 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3184 if (old_set != 0 && REG_P (SET_DEST (old_set))
3185 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3187 /* Check for setting an eliminable register. */
3188 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3189 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3191 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3192 /* If this is setting the frame pointer register to the
3193 hardware frame pointer register and this is an elimination
3194 that will be done (tested above), this insn is really
3195 adjusting the frame pointer downward to compensate for
3196 the adjustment done before a nonlocal goto. */
3197 if (ep->from == FRAME_POINTER_REGNUM
3198 && ep->to == HARD_FRAME_POINTER_REGNUM)
3200 rtx base = SET_SRC (old_set);
3201 rtx base_insn = insn;
3202 HOST_WIDE_INT offset = 0;
3204 while (base != ep->to_rtx)
3206 rtx prev_insn, prev_set;
3208 if (GET_CODE (base) == PLUS
3209 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3211 offset += INTVAL (XEXP (base, 1));
3212 base = XEXP (base, 0);
3214 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3215 && (prev_set = single_set (prev_insn)) != 0
3216 && rtx_equal_p (SET_DEST (prev_set), base))
3218 base = SET_SRC (prev_set);
3219 base_insn = prev_insn;
3225 if (base == ep->to_rtx)
3228 = plus_constant (ep->to_rtx, offset - ep->offset);
3230 new_body = old_body;
3233 new_body = copy_insn (old_body);
3234 if (REG_NOTES (insn))
3235 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3237 PATTERN (insn) = new_body;
3238 old_set = single_set (insn);
3240 /* First see if this insn remains valid when we
3241 make the change. If not, keep the INSN_CODE
3242 the same and let reload fit it up. */
3243 validate_change (insn, &SET_SRC (old_set), src, 1);
3244 validate_change (insn, &SET_DEST (old_set),
3246 if (! apply_change_group ())
3248 SET_SRC (old_set) = src;
3249 SET_DEST (old_set) = ep->to_rtx;
3258 /* In this case this insn isn't serving a useful purpose. We
3259 will delete it in reload_as_needed once we know that this
3260 elimination is, in fact, being done.
3262 If REPLACE isn't set, we can't delete this insn, but needn't
3263 process it since it won't be used unless something changes. */
3266 delete_dead_insn (insn);
3274 /* We allow one special case which happens to work on all machines we
3275 currently support: a single set with the source or a REG_EQUAL
3276 note being a PLUS of an eliminable register and a constant. */
3277 plus_src = plus_cst_src = 0;
3278 if (old_set && REG_P (SET_DEST (old_set)))
3280 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3281 plus_src = SET_SRC (old_set);
3282 /* First see if the source is of the form (plus (...) CST). */
3284 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3285 plus_cst_src = plus_src;
3286 else if (REG_P (SET_SRC (old_set))
3289 /* Otherwise, see if we have a REG_EQUAL note of the form
3290 (plus (...) CST). */
3292 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3294 if ((REG_NOTE_KIND (links) == REG_EQUAL
3295 || REG_NOTE_KIND (links) == REG_EQUIV)
3296 && GET_CODE (XEXP (links, 0)) == PLUS
3297 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3299 plus_cst_src = XEXP (links, 0);
3305 /* Check that the first operand of the PLUS is a hard reg or
3306 the lowpart subreg of one. */
3309 rtx reg = XEXP (plus_cst_src, 0);
3310 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3311 reg = SUBREG_REG (reg);
3313 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3319 rtx reg = XEXP (plus_cst_src, 0);
3320 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3322 if (GET_CODE (reg) == SUBREG)
3323 reg = SUBREG_REG (reg);
3325 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3326 if (ep->from_rtx == reg && ep->can_eliminate)
3328 rtx to_rtx = ep->to_rtx;
3329 offset += ep->offset;
3330 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3332 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3333 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3335 /* If we have a nonzero offset, and the source is already
3336 a simple REG, the following transformation would
3337 increase the cost of the insn by replacing a simple REG
3338 with (plus (reg sp) CST). So try only when we already
3339 had a PLUS before. */
3340 if (offset == 0 || plus_src)
3342 rtx new_src = plus_constant (to_rtx, offset);
3344 new_body = old_body;
3347 new_body = copy_insn (old_body);
3348 if (REG_NOTES (insn))
3349 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3351 PATTERN (insn) = new_body;
3352 old_set = single_set (insn);
3354 /* First see if this insn remains valid when we make the
3355 change. If not, try to replace the whole pattern with
3356 a simple set (this may help if the original insn was a
3357 PARALLEL that was only recognized as single_set due to
3358 REG_UNUSED notes). If this isn't valid either, keep
3359 the INSN_CODE the same and let reload fix it up. */
3360 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3362 rtx new_pat = gen_rtx_SET (VOIDmode,
3363 SET_DEST (old_set), new_src);
3365 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3366 SET_SRC (old_set) = new_src;
3373 /* This can't have an effect on elimination offsets, so skip right
3379 /* Determine the effects of this insn on elimination offsets. */
3380 elimination_effects (old_body, 0);
3382 /* Eliminate all eliminable registers occurring in operands that
3383 can be handled by reload. */
3384 extract_insn (insn);
3385 for (i = 0; i < recog_data.n_operands; i++)
3387 orig_operand[i] = recog_data.operand[i];
3388 substed_operand[i] = recog_data.operand[i];
3390 /* For an asm statement, every operand is eliminable. */
3391 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3393 bool is_set_src, in_plus;
3395 /* Check for setting a register that we know about. */
3396 if (recog_data.operand_type[i] != OP_IN
3397 && REG_P (orig_operand[i]))
3399 /* If we are assigning to a register that can be eliminated, it
3400 must be as part of a PARALLEL, since the code above handles
3401 single SETs. We must indicate that we can no longer
3402 eliminate this reg. */
3403 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3405 if (ep->from_rtx == orig_operand[i])
3406 ep->can_eliminate = 0;
3409 /* Companion to the above plus substitution, we can allow
3410 invariants as the source of a plain move. */
3412 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3416 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3417 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3421 = eliminate_regs_1 (recog_data.operand[i], 0,
3422 replace ? insn : NULL_RTX,
3423 is_set_src || in_plus);
3424 if (substed_operand[i] != orig_operand[i])
3426 /* Terminate the search in check_eliminable_occurrences at
3428 *recog_data.operand_loc[i] = 0;
3430 /* If an output operand changed from a REG to a MEM and INSN is an
3431 insn, write a CLOBBER insn. */
3432 if (recog_data.operand_type[i] != OP_IN
3433 && REG_P (orig_operand[i])
3434 && MEM_P (substed_operand[i])
3436 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3440 for (i = 0; i < recog_data.n_dups; i++)
3441 *recog_data.dup_loc[i]
3442 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3444 /* If any eliminable remain, they aren't eliminable anymore. */
3445 check_eliminable_occurrences (old_body);
3447 /* Substitute the operands; the new values are in the substed_operand
3449 for (i = 0; i < recog_data.n_operands; i++)
3450 *recog_data.operand_loc[i] = substed_operand[i];
3451 for (i = 0; i < recog_data.n_dups; i++)
3452 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3454 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3455 re-recognize the insn. We do this in case we had a simple addition
3456 but now can do this as a load-address. This saves an insn in this
3458 If re-recognition fails, the old insn code number will still be used,
3459 and some register operands may have changed into PLUS expressions.
3460 These will be handled by find_reloads by loading them into a register
3465 /* If we aren't replacing things permanently and we changed something,
3466 make another copy to ensure that all the RTL is new. Otherwise
3467 things can go wrong if find_reload swaps commutative operands
3468 and one is inside RTL that has been copied while the other is not. */
3469 new_body = old_body;
3472 new_body = copy_insn (old_body);
3473 if (REG_NOTES (insn))
3474 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3476 PATTERN (insn) = new_body;
3478 /* If we had a move insn but now we don't, rerecognize it. This will
3479 cause spurious re-recognition if the old move had a PARALLEL since
3480 the new one still will, but we can't call single_set without
3481 having put NEW_BODY into the insn and the re-recognition won't
3482 hurt in this rare case. */
3483 /* ??? Why this huge if statement - why don't we just rerecognize the
3487 && ((REG_P (SET_SRC (old_set))
3488 && (GET_CODE (new_body) != SET
3489 || !REG_P (SET_SRC (new_body))))
3490 /* If this was a load from or store to memory, compare
3491 the MEM in recog_data.operand to the one in the insn.
3492 If they are not equal, then rerecognize the insn. */
3494 && ((MEM_P (SET_SRC (old_set))
3495 && SET_SRC (old_set) != recog_data.operand[1])
3496 || (MEM_P (SET_DEST (old_set))
3497 && SET_DEST (old_set) != recog_data.operand[0])))
3498 /* If this was an add insn before, rerecognize. */
3499 || GET_CODE (SET_SRC (old_set)) == PLUS))
3501 int new_icode = recog (PATTERN (insn), insn, 0);
3503 INSN_CODE (insn) = new_icode;
3507 /* Restore the old body. If there were any changes to it, we made a copy
3508 of it while the changes were still in place, so we'll correctly return
3509 a modified insn below. */
3512 /* Restore the old body. */
3513 for (i = 0; i < recog_data.n_operands; i++)
3514 *recog_data.operand_loc[i] = orig_operand[i];
3515 for (i = 0; i < recog_data.n_dups; i++)
3516 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3519 /* Update all elimination pairs to reflect the status after the current
3520 insn. The changes we make were determined by the earlier call to
3521 elimination_effects.
3523 We also detect cases where register elimination cannot be done,
3524 namely, if a register would be both changed and referenced outside a MEM
3525 in the resulting insn since such an insn is often undefined and, even if
3526 not, we cannot know what meaning will be given to it. Note that it is
3527 valid to have a register used in an address in an insn that changes it
3528 (presumably with a pre- or post-increment or decrement).
3530 If anything changes, return nonzero. */
3532 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3534 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3535 ep->can_eliminate = 0;
3537 ep->ref_outside_mem = 0;
3539 if (ep->previous_offset != ep->offset)
3544 /* If we changed something, perform elimination in REG_NOTES. This is
3545 needed even when REPLACE is zero because a REG_DEAD note might refer
3546 to a register that we eliminate and could cause a different number
3547 of spill registers to be needed in the final reload pass than in
3549 if (val && REG_NOTES (insn) != 0)
3551 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3556 /* Loop through all elimination pairs.
3557 Recalculate the number not at initial offset.
3559 Compute the maximum offset (minimum offset if the stack does not
3560 grow downward) for each elimination pair. */
3563 update_eliminable_offsets (void)
3565 struct elim_table *ep;
3567 num_not_at_initial_offset = 0;
3568 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3570 ep->previous_offset = ep->offset;
3571 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3572 num_not_at_initial_offset++;
3576 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3577 replacement we currently believe is valid, mark it as not eliminable if X
3578 modifies DEST in any way other than by adding a constant integer to it.
3580 If DEST is the frame pointer, we do nothing because we assume that
3581 all assignments to the hard frame pointer are nonlocal gotos and are being
3582 done at a time when they are valid and do not disturb anything else.
3583 Some machines want to eliminate a fake argument pointer with either the
3584 frame or stack pointer. Assignments to the hard frame pointer must not
3585 prevent this elimination.
3587 Called via note_stores from reload before starting its passes to scan
3588 the insns of the function. */
3591 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3595 /* A SUBREG of a hard register here is just changing its mode. We should
3596 not see a SUBREG of an eliminable hard register, but check just in
3598 if (GET_CODE (dest) == SUBREG)
3599 dest = SUBREG_REG (dest);
3601 if (dest == hard_frame_pointer_rtx)
3604 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3605 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3606 && (GET_CODE (x) != SET
3607 || GET_CODE (SET_SRC (x)) != PLUS
3608 || XEXP (SET_SRC (x), 0) != dest
3609 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3611 reg_eliminate[i].can_eliminate_previous
3612 = reg_eliminate[i].can_eliminate = 0;
3617 /* Verify that the initial elimination offsets did not change since the
3618 last call to set_initial_elim_offsets. This is used to catch cases
3619 where something illegal happened during reload_as_needed that could
3620 cause incorrect code to be generated if we did not check for it. */
3623 verify_initial_elim_offsets (void)
3627 if (!num_eliminable)
3630 #ifdef ELIMINABLE_REGS
3632 struct elim_table *ep;
3634 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3636 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3637 if (t != ep->initial_offset)
3642 INITIAL_FRAME_POINTER_OFFSET (t);
3643 if (t != reg_eliminate[0].initial_offset)
3650 /* Reset all offsets on eliminable registers to their initial values. */
3653 set_initial_elim_offsets (void)
3655 struct elim_table *ep = reg_eliminate;
3657 #ifdef ELIMINABLE_REGS
3658 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3660 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3661 ep->previous_offset = ep->offset = ep->initial_offset;
3664 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3665 ep->previous_offset = ep->offset = ep->initial_offset;
3668 num_not_at_initial_offset = 0;
3671 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3674 set_initial_eh_label_offset (rtx label)
3676 set_label_offsets (label, NULL_RTX, 1);
3679 /* Initialize the known label offsets.
3680 Set a known offset for each forced label to be at the initial offset
3681 of each elimination. We do this because we assume that all
3682 computed jumps occur from a location where each elimination is
3683 at its initial offset.
3684 For all other labels, show that we don't know the offsets. */
3687 set_initial_label_offsets (void)
3690 memset (offsets_known_at, 0, num_labels);
3692 for (x = forced_labels; x; x = XEXP (x, 1))
3694 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3696 for_each_eh_label (set_initial_eh_label_offset);
3699 /* Set all elimination offsets to the known values for the code label given
3703 set_offsets_for_label (rtx insn)
3706 int label_nr = CODE_LABEL_NUMBER (insn);
3707 struct elim_table *ep;
3709 num_not_at_initial_offset = 0;
3710 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3712 ep->offset = ep->previous_offset
3713 = offsets_at[label_nr - first_label_num][i];
3714 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3715 num_not_at_initial_offset++;
3719 /* See if anything that happened changes which eliminations are valid.
3720 For example, on the SPARC, whether or not the frame pointer can
3721 be eliminated can depend on what registers have been used. We need
3722 not check some conditions again (such as flag_omit_frame_pointer)
3723 since they can't have changed. */
3726 update_eliminables (HARD_REG_SET *pset)
3728 int previous_frame_pointer_needed = frame_pointer_needed;
3729 struct elim_table *ep;
3731 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3732 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3733 #ifdef ELIMINABLE_REGS
3734 || ! CAN_ELIMINATE (ep->from, ep->to)
3737 ep->can_eliminate = 0;
3739 /* Look for the case where we have discovered that we can't replace
3740 register A with register B and that means that we will now be
3741 trying to replace register A with register C. This means we can
3742 no longer replace register C with register B and we need to disable
3743 such an elimination, if it exists. This occurs often with A == ap,
3744 B == sp, and C == fp. */
3746 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3748 struct elim_table *op;
3751 if (! ep->can_eliminate && ep->can_eliminate_previous)
3753 /* Find the current elimination for ep->from, if there is a
3755 for (op = reg_eliminate;
3756 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3757 if (op->from == ep->from && op->can_eliminate)
3763 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3765 for (op = reg_eliminate;
3766 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3767 if (op->from == new_to && op->to == ep->to)
3768 op->can_eliminate = 0;
3772 /* See if any registers that we thought we could eliminate the previous
3773 time are no longer eliminable. If so, something has changed and we
3774 must spill the register. Also, recompute the number of eliminable
3775 registers and see if the frame pointer is needed; it is if there is
3776 no elimination of the frame pointer that we can perform. */
3778 frame_pointer_needed = 1;
3779 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3781 if (ep->can_eliminate
3782 && ep->from == FRAME_POINTER_REGNUM
3783 && ep->to != HARD_FRAME_POINTER_REGNUM
3784 && (! SUPPORTS_STACK_ALIGNMENT
3785 || ! crtl->stack_realign_needed))
3786 frame_pointer_needed = 0;
3788 if (! ep->can_eliminate && ep->can_eliminate_previous)
3790 ep->can_eliminate_previous = 0;
3791 SET_HARD_REG_BIT (*pset, ep->from);
3796 /* If we didn't need a frame pointer last time, but we do now, spill
3797 the hard frame pointer. */
3798 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3799 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3802 /* Return true if X is used as the target register of an elimination. */
3805 elimination_target_reg_p (rtx x)
3807 struct elim_table *ep;
3809 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3810 if (ep->to_rtx == x && ep->can_eliminate)
3816 /* Initialize the table of registers to eliminate.
3817 Pre-condition: global flag frame_pointer_needed has been set before
3818 calling this function. */
3821 init_elim_table (void)
3823 struct elim_table *ep;
3824 #ifdef ELIMINABLE_REGS
3825 const struct elim_table_1 *ep1;
3829 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3833 #ifdef ELIMINABLE_REGS
3834 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3835 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3837 ep->from = ep1->from;
3839 ep->can_eliminate = ep->can_eliminate_previous
3840 = (CAN_ELIMINATE (ep->from, ep->to)
3841 && ! (ep->to == STACK_POINTER_REGNUM
3842 && frame_pointer_needed
3843 && (! SUPPORTS_STACK_ALIGNMENT
3844 || ! stack_realign_fp)));
3847 reg_eliminate[0].from = reg_eliminate_1[0].from;
3848 reg_eliminate[0].to = reg_eliminate_1[0].to;
3849 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3850 = ! frame_pointer_needed;
3853 /* Count the number of eliminable registers and build the FROM and TO
3854 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3855 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3856 We depend on this. */
3857 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3859 num_eliminable += ep->can_eliminate;
3860 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3861 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3865 /* Kick all pseudos out of hard register REGNO.
3867 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3868 because we found we can't eliminate some register. In the case, no pseudos
3869 are allowed to be in the register, even if they are only in a block that
3870 doesn't require spill registers, unlike the case when we are spilling this
3871 hard reg to produce another spill register.
3873 Return nonzero if any pseudos needed to be kicked out. */
3876 spill_hard_reg (unsigned int regno, int cant_eliminate)
3882 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3883 df_set_regs_ever_live (regno, true);
3886 /* Spill every pseudo reg that was allocated to this reg
3887 or to something that overlaps this reg. */
3889 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3890 if (reg_renumber[i] >= 0
3891 && (unsigned int) reg_renumber[i] <= regno
3892 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3893 SET_REGNO_REG_SET (&spilled_pseudos, i);
3896 /* After find_reload_regs has been run for all insn that need reloads,
3897 and/or spill_hard_regs was called, this function is used to actually
3898 spill pseudo registers and try to reallocate them. It also sets up the
3899 spill_regs array for use by choose_reload_regs. */
3902 finish_spills (int global)
3904 struct insn_chain *chain;
3905 int something_changed = 0;
3907 reg_set_iterator rsi;
3909 /* Build the spill_regs array for the function. */
3910 /* If there are some registers still to eliminate and one of the spill regs
3911 wasn't ever used before, additional stack space may have to be
3912 allocated to store this register. Thus, we may have changed the offset
3913 between the stack and frame pointers, so mark that something has changed.
3915 One might think that we need only set VAL to 1 if this is a call-used
3916 register. However, the set of registers that must be saved by the
3917 prologue is not identical to the call-used set. For example, the
3918 register used by the call insn for the return PC is a call-used register,
3919 but must be saved by the prologue. */
3922 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3923 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3925 spill_reg_order[i] = n_spills;
3926 spill_regs[n_spills++] = i;
3927 if (num_eliminable && ! df_regs_ever_live_p (i))
3928 something_changed = 1;
3929 df_set_regs_ever_live (i, true);
3932 spill_reg_order[i] = -1;
3934 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3935 if (! flag_ira || ! optimize || reg_renumber[i] >= 0)
3937 /* Record the current hard register the pseudo is allocated to
3938 in pseudo_previous_regs so we avoid reallocating it to the
3939 same hard reg in a later pass. */
3940 gcc_assert (reg_renumber[i] >= 0);
3942 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3943 /* Mark it as no longer having a hard register home. */
3944 reg_renumber[i] = -1;
3945 if (flag_ira && optimize)
3946 /* Inform IRA about the change. */
3947 ira_mark_allocation_change (i);
3948 /* We will need to scan everything again. */
3949 something_changed = 1;
3952 /* Retry global register allocation if possible. */
3955 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3956 /* For every insn that needs reloads, set the registers used as spill
3957 regs in pseudo_forbidden_regs for every pseudo live across the
3959 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3961 EXECUTE_IF_SET_IN_REG_SET
3962 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3964 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3965 chain->used_spill_regs);
3967 EXECUTE_IF_SET_IN_REG_SET
3968 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3970 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3971 chain->used_spill_regs);
3975 if (! flag_ira || ! optimize)
3977 /* Retry allocating the spilled pseudos. For each reg,
3978 merge the various reg sets that indicate which hard regs
3979 can't be used, and call retry_global_alloc. We change
3980 spill_pseudos here to only contain pseudos that did not
3981 get a new hard register. */
3982 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3983 if (reg_old_renumber[i] != reg_renumber[i])
3985 HARD_REG_SET forbidden;
3987 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3988 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3989 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3990 retry_global_alloc (i, forbidden);
3991 if (reg_renumber[i] >= 0)
3992 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3997 /* Retry allocating the pseudos spilled in IRA and the
3998 reload. For each reg, merge the various reg sets that
3999 indicate which hard regs can't be used, and call
4000 ira_reassign_pseudos. */
4003 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4004 if (reg_old_renumber[i] != reg_renumber[i])
4006 if (reg_renumber[i] < 0)
4007 temp_pseudo_reg_arr[n++] = i;
4009 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4011 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4012 bad_spill_regs_global,
4013 pseudo_forbidden_regs, pseudo_previous_regs,
4015 something_changed = 1;
4019 /* Fix up the register information in the insn chain.
4020 This involves deleting those of the spilled pseudos which did not get
4021 a new hard register home from the live_{before,after} sets. */
4022 for (chain = reload_insn_chain; chain; chain = chain->next)
4024 HARD_REG_SET used_by_pseudos;
4025 HARD_REG_SET used_by_pseudos2;
4027 if (! flag_ira || ! optimize)
4029 /* Don't do it for IRA because IRA and the reload still can
4030 assign hard registers to the spilled pseudos on next
4031 reload iterations. */
4032 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4033 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4035 /* Mark any unallocated hard regs as available for spills. That
4036 makes inheritance work somewhat better. */
4037 if (chain->need_reload)
4039 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4040 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4041 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4043 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4044 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4045 /* Value of chain->used_spill_regs from previous iteration
4046 may be not included in the value calculated here because
4047 of possible removing caller-saves insns (see function
4048 delete_caller_save_insns. */
4049 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4050 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4054 CLEAR_REG_SET (&changed_allocation_pseudos);
4055 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4056 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4058 int regno = reg_renumber[i];
4059 if (reg_old_renumber[i] == regno)
4062 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4064 alter_reg (i, reg_old_renumber[i], false);
4065 reg_old_renumber[i] = regno;
4069 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4071 fprintf (dump_file, " Register %d now in %d.\n\n",
4072 i, reg_renumber[i]);
4076 return something_changed;
4079 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4082 scan_paradoxical_subregs (rtx x)
4086 enum rtx_code code = GET_CODE (x);
4097 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4105 if (REG_P (SUBREG_REG (x))
4106 && (GET_MODE_SIZE (GET_MODE (x))
4107 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4109 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4110 = GET_MODE_SIZE (GET_MODE (x));
4111 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4119 fmt = GET_RTX_FORMAT (code);
4120 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4123 scan_paradoxical_subregs (XEXP (x, i));
4124 else if (fmt[i] == 'E')
4127 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4128 scan_paradoxical_subregs (XVECEXP (x, i, j));
4133 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4134 examine all of the reload insns between PREV and NEXT exclusive, and
4135 annotate all that may trap. */
4138 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4140 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4141 unsigned int trap_count;
4147 if (may_trap_p (PATTERN (insn)))
4151 remove_note (insn, note);
4155 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4156 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4159 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4163 /* Reload pseudo-registers into hard regs around each insn as needed.
4164 Additional register load insns are output before the insn that needs it
4165 and perhaps store insns after insns that modify the reloaded pseudo reg.
4167 reg_last_reload_reg and reg_reloaded_contents keep track of
4168 which registers are already available in reload registers.
4169 We update these for the reloads that we perform,
4170 as the insns are scanned. */
4173 reload_as_needed (int live_known)
4175 struct insn_chain *chain;
4176 #if defined (AUTO_INC_DEC)
4181 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4182 memset (spill_reg_store, 0, sizeof spill_reg_store);
4183 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4184 INIT_REG_SET (®_has_output_reload);
4185 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4186 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4188 set_initial_elim_offsets ();
4190 for (chain = reload_insn_chain; chain; chain = chain->next)
4193 rtx insn = chain->insn;
4194 rtx old_next = NEXT_INSN (insn);
4196 /* If we pass a label, copy the offsets from the label information
4197 into the current offsets of each elimination. */
4199 set_offsets_for_label (insn);
4201 else if (INSN_P (insn))
4203 regset_head regs_to_forget;
4204 INIT_REG_SET (®s_to_forget);
4205 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4207 /* If this is a USE and CLOBBER of a MEM, ensure that any
4208 references to eliminable registers have been removed. */
4210 if ((GET_CODE (PATTERN (insn)) == USE
4211 || GET_CODE (PATTERN (insn)) == CLOBBER)
4212 && MEM_P (XEXP (PATTERN (insn), 0)))
4213 XEXP (XEXP (PATTERN (insn), 0), 0)
4214 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4215 GET_MODE (XEXP (PATTERN (insn), 0)),
4218 /* If we need to do register elimination processing, do so.
4219 This might delete the insn, in which case we are done. */
4220 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4222 eliminate_regs_in_insn (insn, 1);
4225 update_eliminable_offsets ();
4226 CLEAR_REG_SET (®s_to_forget);
4231 /* If need_elim is nonzero but need_reload is zero, one might think
4232 that we could simply set n_reloads to 0. However, find_reloads
4233 could have done some manipulation of the insn (such as swapping
4234 commutative operands), and these manipulations are lost during
4235 the first pass for every insn that needs register elimination.
4236 So the actions of find_reloads must be redone here. */
4238 if (! chain->need_elim && ! chain->need_reload
4239 && ! chain->need_operand_change)
4241 /* First find the pseudo regs that must be reloaded for this insn.
4242 This info is returned in the tables reload_... (see reload.h).
4243 Also modify the body of INSN by substituting RELOAD
4244 rtx's for those pseudo regs. */
4247 CLEAR_REG_SET (®_has_output_reload);
4248 CLEAR_HARD_REG_SET (reg_is_output_reload);
4250 find_reloads (insn, 1, spill_indirect_levels, live_known,
4256 rtx next = NEXT_INSN (insn);
4259 prev = PREV_INSN (insn);
4261 /* Now compute which reload regs to reload them into. Perhaps
4262 reusing reload regs from previous insns, or else output
4263 load insns to reload them. Maybe output store insns too.
4264 Record the choices of reload reg in reload_reg_rtx. */
4265 choose_reload_regs (chain);
4267 /* Merge any reloads that we didn't combine for fear of
4268 increasing the number of spill registers needed but now
4269 discover can be safely merged. */
4270 if (SMALL_REGISTER_CLASSES)
4271 merge_assigned_reloads (insn);
4273 /* Generate the insns to reload operands into or out of
4274 their reload regs. */
4275 emit_reload_insns (chain);
4277 /* Substitute the chosen reload regs from reload_reg_rtx
4278 into the insn's body (or perhaps into the bodies of other
4279 load and store insn that we just made for reloading
4280 and that we moved the structure into). */
4281 subst_reloads (insn);
4283 /* Adjust the exception region notes for loads and stores. */
4284 if (flag_non_call_exceptions && !CALL_P (insn))
4285 fixup_eh_region_note (insn, prev, next);
4287 /* If this was an ASM, make sure that all the reload insns
4288 we have generated are valid. If not, give an error
4290 if (asm_noperands (PATTERN (insn)) >= 0)
4291 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4292 if (p != insn && INSN_P (p)
4293 && GET_CODE (PATTERN (p)) != USE
4294 && (recog_memoized (p) < 0
4295 || (extract_insn (p), ! constrain_operands (1))))
4297 error_for_asm (insn,
4298 "%<asm%> operand requires "
4299 "impossible reload");
4304 if (num_eliminable && chain->need_elim)
4305 update_eliminable_offsets ();
4307 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4308 is no longer validly lying around to save a future reload.
4309 Note that this does not detect pseudos that were reloaded
4310 for this insn in order to be stored in
4311 (obeying register constraints). That is correct; such reload
4312 registers ARE still valid. */
4313 forget_marked_reloads (®s_to_forget);
4314 CLEAR_REG_SET (®s_to_forget);
4316 /* There may have been CLOBBER insns placed after INSN. So scan
4317 between INSN and NEXT and use them to forget old reloads. */
4318 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4319 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4320 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4323 /* Likewise for regs altered by auto-increment in this insn.
4324 REG_INC notes have been changed by reloading:
4325 find_reloads_address_1 records substitutions for them,
4326 which have been performed by subst_reloads above. */
4327 for (i = n_reloads - 1; i >= 0; i--)
4329 rtx in_reg = rld[i].in_reg;
4332 enum rtx_code code = GET_CODE (in_reg);
4333 /* PRE_INC / PRE_DEC will have the reload register ending up
4334 with the same value as the stack slot, but that doesn't
4335 hold true for POST_INC / POST_DEC. Either we have to
4336 convert the memory access to a true POST_INC / POST_DEC,
4337 or we can't use the reload register for inheritance. */
4338 if ((code == POST_INC || code == POST_DEC)
4339 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4340 REGNO (rld[i].reg_rtx))
4341 /* Make sure it is the inc/dec pseudo, and not
4342 some other (e.g. output operand) pseudo. */
4343 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4344 == REGNO (XEXP (in_reg, 0))))
4347 rtx reload_reg = rld[i].reg_rtx;
4348 enum machine_mode mode = GET_MODE (reload_reg);
4352 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4354 /* We really want to ignore REG_INC notes here, so
4355 use PATTERN (p) as argument to reg_set_p . */
4356 if (reg_set_p (reload_reg, PATTERN (p)))
4358 n = count_occurrences (PATTERN (p), reload_reg, 0);
4363 n = validate_replace_rtx (reload_reg,
4364 gen_rtx_fmt_e (code,
4369 /* We must also verify that the constraints
4370 are met after the replacement. */
4373 n = constrain_operands (1);
4377 /* If the constraints were not met, then
4378 undo the replacement. */
4381 validate_replace_rtx (gen_rtx_fmt_e (code,
4393 add_reg_note (p, REG_INC, reload_reg);
4394 /* Mark this as having an output reload so that the
4395 REG_INC processing code below won't invalidate
4396 the reload for inheritance. */
4397 SET_HARD_REG_BIT (reg_is_output_reload,
4398 REGNO (reload_reg));
4399 SET_REGNO_REG_SET (®_has_output_reload,
4400 REGNO (XEXP (in_reg, 0)));
4403 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4406 else if ((code == PRE_INC || code == PRE_DEC)
4407 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4408 REGNO (rld[i].reg_rtx))
4409 /* Make sure it is the inc/dec pseudo, and not
4410 some other (e.g. output operand) pseudo. */
4411 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4412 == REGNO (XEXP (in_reg, 0))))
4414 SET_HARD_REG_BIT (reg_is_output_reload,
4415 REGNO (rld[i].reg_rtx));
4416 SET_REGNO_REG_SET (®_has_output_reload,
4417 REGNO (XEXP (in_reg, 0)));
4421 /* If a pseudo that got a hard register is auto-incremented,
4422 we must purge records of copying it into pseudos without
4424 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4425 if (REG_NOTE_KIND (x) == REG_INC)
4427 /* See if this pseudo reg was reloaded in this insn.
4428 If so, its last-reload info is still valid
4429 because it is based on this insn's reload. */
4430 for (i = 0; i < n_reloads; i++)
4431 if (rld[i].out == XEXP (x, 0))
4435 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4439 /* A reload reg's contents are unknown after a label. */
4441 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4443 /* Don't assume a reload reg is still good after a call insn
4444 if it is a call-used reg, or if it contains a value that will
4445 be partially clobbered by the call. */
4446 else if (CALL_P (insn))
4448 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4449 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4454 free (reg_last_reload_reg);
4455 CLEAR_REG_SET (®_has_output_reload);
4458 /* Discard all record of any value reloaded from X,
4459 or reloaded in X from someplace else;
4460 unless X is an output reload reg of the current insn.
4462 X may be a hard reg (the reload reg)
4463 or it may be a pseudo reg that was reloaded from.
4465 When DATA is non-NULL just mark the registers in regset
4466 to be forgotten later. */
4469 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4474 regset regs = (regset) data;
4476 /* note_stores does give us subregs of hard regs,
4477 subreg_regno_offset requires a hard reg. */
4478 while (GET_CODE (x) == SUBREG)
4480 /* We ignore the subreg offset when calculating the regno,
4481 because we are using the entire underlying hard register
4491 if (regno >= FIRST_PSEUDO_REGISTER)
4497 nr = hard_regno_nregs[regno][GET_MODE (x)];
4498 /* Storing into a spilled-reg invalidates its contents.
4499 This can happen if a block-local pseudo is allocated to that reg
4500 and it wasn't spilled because this block's total need is 0.
4501 Then some insn might have an optional reload and use this reg. */
4503 for (i = 0; i < nr; i++)
4504 /* But don't do this if the reg actually serves as an output
4505 reload reg in the current instruction. */
4507 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4509 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4510 spill_reg_store[regno + i] = 0;
4516 SET_REGNO_REG_SET (regs, regno + nr);
4519 /* Since value of X has changed,
4520 forget any value previously copied from it. */
4523 /* But don't forget a copy if this is the output reload
4524 that establishes the copy's validity. */
4526 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4527 reg_last_reload_reg[regno + nr] = 0;
4531 /* Forget the reloads marked in regset by previous function. */
4533 forget_marked_reloads (regset regs)
4536 reg_set_iterator rsi;
4537 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4539 if (reg < FIRST_PSEUDO_REGISTER
4540 /* But don't do this if the reg actually serves as an output
4541 reload reg in the current instruction. */
4543 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4545 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4546 spill_reg_store[reg] = 0;
4549 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4550 reg_last_reload_reg[reg] = 0;
4554 /* The following HARD_REG_SETs indicate when each hard register is
4555 used for a reload of various parts of the current insn. */
4557 /* If reg is unavailable for all reloads. */
4558 static HARD_REG_SET reload_reg_unavailable;
4559 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4560 static HARD_REG_SET reload_reg_used;
4561 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4562 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4563 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4564 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4565 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4566 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4567 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4568 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4569 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4570 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4571 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4572 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4573 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4574 static HARD_REG_SET reload_reg_used_in_op_addr;
4575 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4576 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4577 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4578 static HARD_REG_SET reload_reg_used_in_insn;
4579 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4580 static HARD_REG_SET reload_reg_used_in_other_addr;
4582 /* If reg is in use as a reload reg for any sort of reload. */
4583 static HARD_REG_SET reload_reg_used_at_all;
4585 /* If reg is use as an inherited reload. We just mark the first register
4587 static HARD_REG_SET reload_reg_used_for_inherit;
4589 /* Records which hard regs are used in any way, either as explicit use or
4590 by being allocated to a pseudo during any point of the current insn. */
4591 static HARD_REG_SET reg_used_in_insn;
4593 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4594 TYPE. MODE is used to indicate how many consecutive regs are
4598 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4599 enum machine_mode mode)
4601 unsigned int nregs = hard_regno_nregs[regno][mode];
4604 for (i = regno; i < nregs + regno; i++)
4609 SET_HARD_REG_BIT (reload_reg_used, i);
4612 case RELOAD_FOR_INPUT_ADDRESS:
4613 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4616 case RELOAD_FOR_INPADDR_ADDRESS:
4617 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4620 case RELOAD_FOR_OUTPUT_ADDRESS:
4621 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4624 case RELOAD_FOR_OUTADDR_ADDRESS:
4625 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4628 case RELOAD_FOR_OPERAND_ADDRESS:
4629 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4632 case RELOAD_FOR_OPADDR_ADDR:
4633 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4636 case RELOAD_FOR_OTHER_ADDRESS:
4637 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4640 case RELOAD_FOR_INPUT:
4641 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4644 case RELOAD_FOR_OUTPUT:
4645 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4648 case RELOAD_FOR_INSN:
4649 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4653 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4657 /* Similarly, but show REGNO is no longer in use for a reload. */
4660 clear_reload_reg_in_use (unsigned int regno, int opnum,
4661 enum reload_type type, enum machine_mode mode)
4663 unsigned int nregs = hard_regno_nregs[regno][mode];
4664 unsigned int start_regno, end_regno, r;
4666 /* A complication is that for some reload types, inheritance might
4667 allow multiple reloads of the same types to share a reload register.
4668 We set check_opnum if we have to check only reloads with the same
4669 operand number, and check_any if we have to check all reloads. */
4670 int check_opnum = 0;
4672 HARD_REG_SET *used_in_set;
4677 used_in_set = &reload_reg_used;
4680 case RELOAD_FOR_INPUT_ADDRESS:
4681 used_in_set = &reload_reg_used_in_input_addr[opnum];
4684 case RELOAD_FOR_INPADDR_ADDRESS:
4686 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4689 case RELOAD_FOR_OUTPUT_ADDRESS:
4690 used_in_set = &reload_reg_used_in_output_addr[opnum];
4693 case RELOAD_FOR_OUTADDR_ADDRESS:
4695 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4698 case RELOAD_FOR_OPERAND_ADDRESS:
4699 used_in_set = &reload_reg_used_in_op_addr;
4702 case RELOAD_FOR_OPADDR_ADDR:
4704 used_in_set = &reload_reg_used_in_op_addr_reload;
4707 case RELOAD_FOR_OTHER_ADDRESS:
4708 used_in_set = &reload_reg_used_in_other_addr;
4712 case RELOAD_FOR_INPUT:
4713 used_in_set = &reload_reg_used_in_input[opnum];
4716 case RELOAD_FOR_OUTPUT:
4717 used_in_set = &reload_reg_used_in_output[opnum];
4720 case RELOAD_FOR_INSN:
4721 used_in_set = &reload_reg_used_in_insn;
4726 /* We resolve conflicts with remaining reloads of the same type by
4727 excluding the intervals of reload registers by them from the
4728 interval of freed reload registers. Since we only keep track of
4729 one set of interval bounds, we might have to exclude somewhat
4730 more than what would be necessary if we used a HARD_REG_SET here.
4731 But this should only happen very infrequently, so there should
4732 be no reason to worry about it. */
4734 start_regno = regno;
4735 end_regno = regno + nregs;
4736 if (check_opnum || check_any)
4738 for (i = n_reloads - 1; i >= 0; i--)
4740 if (rld[i].when_needed == type
4741 && (check_any || rld[i].opnum == opnum)
4744 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4745 unsigned int conflict_end
4746 = end_hard_regno (rld[i].mode, conflict_start);
4748 /* If there is an overlap with the first to-be-freed register,
4749 adjust the interval start. */
4750 if (conflict_start <= start_regno && conflict_end > start_regno)
4751 start_regno = conflict_end;
4752 /* Otherwise, if there is a conflict with one of the other
4753 to-be-freed registers, adjust the interval end. */
4754 if (conflict_start > start_regno && conflict_start < end_regno)
4755 end_regno = conflict_start;
4760 for (r = start_regno; r < end_regno; r++)
4761 CLEAR_HARD_REG_BIT (*used_in_set, r);
4764 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4765 specified by OPNUM and TYPE. */
4768 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4772 /* In use for a RELOAD_OTHER means it's not available for anything. */
4773 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4774 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4780 /* In use for anything means we can't use it for RELOAD_OTHER. */
4781 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4782 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4783 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4784 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4787 for (i = 0; i < reload_n_operands; i++)
4788 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4789 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4790 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4791 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4792 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4793 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4798 case RELOAD_FOR_INPUT:
4799 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4803 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4806 /* If it is used for some other input, can't use it. */
4807 for (i = 0; i < reload_n_operands; i++)
4808 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4811 /* If it is used in a later operand's address, can't use it. */
4812 for (i = opnum + 1; i < reload_n_operands; i++)
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4819 case RELOAD_FOR_INPUT_ADDRESS:
4820 /* Can't use a register if it is used for an input address for this
4821 operand or used as an input in an earlier one. */
4822 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4826 for (i = 0; i < opnum; i++)
4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4832 case RELOAD_FOR_INPADDR_ADDRESS:
4833 /* Can't use a register if it is used for an input address
4834 for this operand or used as an input in an earlier
4836 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4839 for (i = 0; i < opnum; i++)
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4845 case RELOAD_FOR_OUTPUT_ADDRESS:
4846 /* Can't use a register if it is used for an output address for this
4847 operand or used as an output in this or a later operand. Note
4848 that multiple output operands are emitted in reverse order, so
4849 the conflicting ones are those with lower indices. */
4850 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4853 for (i = 0; i <= opnum; i++)
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4859 case RELOAD_FOR_OUTADDR_ADDRESS:
4860 /* Can't use a register if it is used for an output address
4861 for this operand or used as an output in this or a
4862 later operand. Note that multiple output operands are
4863 emitted in reverse order, so the conflicting ones are
4864 those with lower indices. */
4865 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4868 for (i = 0; i <= opnum; i++)
4869 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4874 case RELOAD_FOR_OPERAND_ADDRESS:
4875 for (i = 0; i < reload_n_operands; i++)
4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4879 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4880 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4882 case RELOAD_FOR_OPADDR_ADDR:
4883 for (i = 0; i < reload_n_operands; i++)
4884 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4887 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4889 case RELOAD_FOR_OUTPUT:
4890 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4891 outputs, or an operand address for this or an earlier output.
4892 Note that multiple output operands are emitted in reverse order,
4893 so the conflicting ones are those with higher indices. */
4894 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4897 for (i = 0; i < reload_n_operands; i++)
4898 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4901 for (i = opnum; i < reload_n_operands; i++)
4902 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4903 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4908 case RELOAD_FOR_INSN:
4909 for (i = 0; i < reload_n_operands; i++)
4910 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4911 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4914 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4915 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4917 case RELOAD_FOR_OTHER_ADDRESS:
4918 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4925 /* Return 1 if the value in reload reg REGNO, as used by a reload
4926 needed for the part of the insn specified by OPNUM and TYPE,
4927 is still available in REGNO at the end of the insn.
4929 We can assume that the reload reg was already tested for availability
4930 at the time it is needed, and we should not check this again,
4931 in case the reg has already been marked in use. */
4934 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4941 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4942 its value must reach the end. */
4945 /* If this use is for part of the insn,
4946 its value reaches if no subsequent part uses the same register.
4947 Just like the above function, don't try to do this with lots
4950 case RELOAD_FOR_OTHER_ADDRESS:
4951 /* Here we check for everything else, since these don't conflict
4952 with anything else and everything comes later. */
4954 for (i = 0; i < reload_n_operands; i++)
4955 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4956 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4957 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4958 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4959 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4960 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4963 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4964 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4965 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4966 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4968 case RELOAD_FOR_INPUT_ADDRESS:
4969 case RELOAD_FOR_INPADDR_ADDRESS:
4970 /* Similar, except that we check only for this and subsequent inputs
4971 and the address of only subsequent inputs and we do not need
4972 to check for RELOAD_OTHER objects since they are known not to
4975 for (i = opnum; i < reload_n_operands; i++)
4976 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4979 for (i = opnum + 1; i < reload_n_operands; i++)
4980 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4981 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4984 for (i = 0; i < reload_n_operands; i++)
4985 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4986 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4987 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4990 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4993 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4994 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4995 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4997 case RELOAD_FOR_INPUT:
4998 /* Similar to input address, except we start at the next operand for
4999 both input and input address and we do not check for
5000 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5003 for (i = opnum + 1; i < reload_n_operands; i++)
5004 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5005 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5006 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5009 /* ... fall through ... */
5011 case RELOAD_FOR_OPERAND_ADDRESS:
5012 /* Check outputs and their addresses. */
5014 for (i = 0; i < reload_n_operands; i++)
5015 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5016 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5017 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5020 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5022 case RELOAD_FOR_OPADDR_ADDR:
5023 for (i = 0; i < reload_n_operands; i++)
5024 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5025 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5026 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5029 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5030 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5031 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5033 case RELOAD_FOR_INSN:
5034 /* These conflict with other outputs with RELOAD_OTHER. So
5035 we need only check for output addresses. */
5037 opnum = reload_n_operands;
5039 /* ... fall through ... */
5041 case RELOAD_FOR_OUTPUT:
5042 case RELOAD_FOR_OUTPUT_ADDRESS:
5043 case RELOAD_FOR_OUTADDR_ADDRESS:
5044 /* We already know these can't conflict with a later output. So the
5045 only thing to check are later output addresses.
5046 Note that multiple output operands are emitted in reverse order,
5047 so the conflicting ones are those with lower indices. */
5048 for (i = 0; i < opnum; i++)
5049 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5050 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5060 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5061 every register in the range [REGNO, REGNO + NREGS). */
5064 reload_regs_reach_end_p (unsigned int regno, int nregs,
5065 int opnum, enum reload_type type)
5069 for (i = 0; i < nregs; i++)
5070 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5076 /* Returns whether R1 and R2 are uniquely chained: the value of one
5077 is used by the other, and that value is not used by any other
5078 reload for this insn. This is used to partially undo the decision
5079 made in find_reloads when in the case of multiple
5080 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5081 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5082 reloads. This code tries to avoid the conflict created by that
5083 change. It might be cleaner to explicitly keep track of which
5084 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5085 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5086 this after the fact. */
5088 reloads_unique_chain_p (int r1, int r2)
5092 /* We only check input reloads. */
5093 if (! rld[r1].in || ! rld[r2].in)
5096 /* Avoid anything with output reloads. */
5097 if (rld[r1].out || rld[r2].out)
5100 /* "chained" means one reload is a component of the other reload,
5101 not the same as the other reload. */
5102 if (rld[r1].opnum != rld[r2].opnum
5103 || rtx_equal_p (rld[r1].in, rld[r2].in)
5104 || rld[r1].optional || rld[r2].optional
5105 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5106 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5109 for (i = 0; i < n_reloads; i ++)
5110 /* Look for input reloads that aren't our two */
5111 if (i != r1 && i != r2 && rld[i].in)
5113 /* If our reload is mentioned at all, it isn't a simple chain. */
5114 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5121 /* The recursive function change all occurrences of WHAT in *WHERE
5124 substitute (rtx *where, const_rtx what, rtx repl)
5133 if (*where == what || rtx_equal_p (*where, what))
5139 code = GET_CODE (*where);
5140 fmt = GET_RTX_FORMAT (code);
5141 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5147 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5148 substitute (&XVECEXP (*where, i, j), what, repl);
5150 else if (fmt[i] == 'e')
5151 substitute (&XEXP (*where, i), what, repl);
5155 /* The function returns TRUE if chain of reload R1 and R2 (in any
5156 order) can be evaluated without usage of intermediate register for
5157 the reload containing another reload. It is important to see
5158 gen_reload to understand what the function is trying to do. As an
5159 example, let us have reload chain
5162 r1: <something> + const
5164 and reload R2 got reload reg HR. The function returns true if
5165 there is a correct insn HR = HR + <something>. Otherwise,
5166 gen_reload will use intermediate register (and this is the reload
5167 reg for R1) to reload <something>.
5169 We need this function to find a conflict for chain reloads. In our
5170 example, if HR = HR + <something> is incorrect insn, then we cannot
5171 use HR as a reload register for R2. If we do use it then we get a
5180 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5184 rtx out, in, tem, insn;
5185 rtx last = get_last_insn ();
5187 /* Make r2 a component of r1. */
5188 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5194 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5195 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5196 gcc_assert (regno >= 0);
5197 out = gen_rtx_REG (rld[r1].mode, regno);
5198 in = copy_rtx (rld[r1].in);
5199 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5201 /* If IN is a paradoxical SUBREG, remove it and try to put the
5202 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5203 if (GET_CODE (in) == SUBREG
5204 && (GET_MODE_SIZE (GET_MODE (in))
5205 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5206 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5207 in = SUBREG_REG (in), out = tem;
5209 if (GET_CODE (in) == PLUS
5210 && (REG_P (XEXP (in, 0))
5211 || GET_CODE (XEXP (in, 0)) == SUBREG
5212 || MEM_P (XEXP (in, 0)))
5213 && (REG_P (XEXP (in, 1))
5214 || GET_CODE (XEXP (in, 1)) == SUBREG
5215 || CONSTANT_P (XEXP (in, 1))
5216 || MEM_P (XEXP (in, 1))))
5218 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5219 code = recog_memoized (insn);
5224 extract_insn (insn);
5225 /* We want constrain operands to treat this insn strictly in
5226 its validity determination, i.e., the way it would after
5227 reload has completed. */
5228 result = constrain_operands (1);
5231 delete_insns_since (last);
5235 /* It looks like other cases in gen_reload are not possible for
5236 chain reloads or do need an intermediate hard registers. */
5240 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5243 This function uses the same algorithm as reload_reg_free_p above. */
5246 reloads_conflict (int r1, int r2)
5248 enum reload_type r1_type = rld[r1].when_needed;
5249 enum reload_type r2_type = rld[r2].when_needed;
5250 int r1_opnum = rld[r1].opnum;
5251 int r2_opnum = rld[r2].opnum;
5253 /* RELOAD_OTHER conflicts with everything. */
5254 if (r2_type == RELOAD_OTHER)
5257 /* Otherwise, check conflicts differently for each type. */
5261 case RELOAD_FOR_INPUT:
5262 return (r2_type == RELOAD_FOR_INSN
5263 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5264 || r2_type == RELOAD_FOR_OPADDR_ADDR
5265 || r2_type == RELOAD_FOR_INPUT
5266 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5267 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5268 && r2_opnum > r1_opnum));
5270 case RELOAD_FOR_INPUT_ADDRESS:
5271 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5272 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5274 case RELOAD_FOR_INPADDR_ADDRESS:
5275 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5276 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5278 case RELOAD_FOR_OUTPUT_ADDRESS:
5279 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5280 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5282 case RELOAD_FOR_OUTADDR_ADDRESS:
5283 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5284 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5286 case RELOAD_FOR_OPERAND_ADDRESS:
5287 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5288 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5289 && (!reloads_unique_chain_p (r1, r2)
5290 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5292 case RELOAD_FOR_OPADDR_ADDR:
5293 return (r2_type == RELOAD_FOR_INPUT
5294 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5296 case RELOAD_FOR_OUTPUT:
5297 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5298 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5299 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5300 && r2_opnum >= r1_opnum));
5302 case RELOAD_FOR_INSN:
5303 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5304 || r2_type == RELOAD_FOR_INSN
5305 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5307 case RELOAD_FOR_OTHER_ADDRESS:
5308 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5318 /* Indexed by reload number, 1 if incoming value
5319 inherited from previous insns. */
5320 static char reload_inherited[MAX_RELOADS];
5322 /* For an inherited reload, this is the insn the reload was inherited from,
5323 if we know it. Otherwise, this is 0. */
5324 static rtx reload_inheritance_insn[MAX_RELOADS];
5326 /* If nonzero, this is a place to get the value of the reload,
5327 rather than using reload_in. */
5328 static rtx reload_override_in[MAX_RELOADS];
5330 /* For each reload, the hard register number of the register used,
5331 or -1 if we did not need a register for this reload. */
5332 static int reload_spill_index[MAX_RELOADS];
5334 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5335 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5337 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5338 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5340 /* Subroutine of free_for_value_p, used to check a single register.
5341 START_REGNO is the starting regno of the full reload register
5342 (possibly comprising multiple hard registers) that we are considering. */
5345 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5346 enum reload_type type, rtx value, rtx out,
5347 int reloadnum, int ignore_address_reloads)
5350 /* Set if we see an input reload that must not share its reload register
5351 with any new earlyclobber, but might otherwise share the reload
5352 register with an output or input-output reload. */
5353 int check_earlyclobber = 0;
5357 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5360 if (out == const0_rtx)
5366 /* We use some pseudo 'time' value to check if the lifetimes of the
5367 new register use would overlap with the one of a previous reload
5368 that is not read-only or uses a different value.
5369 The 'time' used doesn't have to be linear in any shape or form, just
5371 Some reload types use different 'buckets' for each operand.
5372 So there are MAX_RECOG_OPERANDS different time values for each
5374 We compute TIME1 as the time when the register for the prospective
5375 new reload ceases to be live, and TIME2 for each existing
5376 reload as the time when that the reload register of that reload
5378 Where there is little to be gained by exact lifetime calculations,
5379 we just make conservative assumptions, i.e. a longer lifetime;
5380 this is done in the 'default:' cases. */
5383 case RELOAD_FOR_OTHER_ADDRESS:
5384 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5385 time1 = copy ? 0 : 1;
5388 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5390 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5391 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5392 respectively, to the time values for these, we get distinct time
5393 values. To get distinct time values for each operand, we have to
5394 multiply opnum by at least three. We round that up to four because
5395 multiply by four is often cheaper. */
5396 case RELOAD_FOR_INPADDR_ADDRESS:
5397 time1 = opnum * 4 + 2;
5399 case RELOAD_FOR_INPUT_ADDRESS:
5400 time1 = opnum * 4 + 3;
5402 case RELOAD_FOR_INPUT:
5403 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5404 executes (inclusive). */
5405 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5407 case RELOAD_FOR_OPADDR_ADDR:
5409 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5410 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5412 case RELOAD_FOR_OPERAND_ADDRESS:
5413 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5415 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5417 case RELOAD_FOR_OUTADDR_ADDRESS:
5418 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5420 case RELOAD_FOR_OUTPUT_ADDRESS:
5421 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5424 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5427 for (i = 0; i < n_reloads; i++)
5429 rtx reg = rld[i].reg_rtx;
5430 if (reg && REG_P (reg)
5431 && ((unsigned) regno - true_regnum (reg)
5432 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5435 rtx other_input = rld[i].in;
5437 /* If the other reload loads the same input value, that
5438 will not cause a conflict only if it's loading it into
5439 the same register. */
5440 if (true_regnum (reg) != start_regno)
5441 other_input = NULL_RTX;
5442 if (! other_input || ! rtx_equal_p (other_input, value)
5443 || rld[i].out || out)
5446 switch (rld[i].when_needed)
5448 case RELOAD_FOR_OTHER_ADDRESS:
5451 case RELOAD_FOR_INPADDR_ADDRESS:
5452 /* find_reloads makes sure that a
5453 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5454 by at most one - the first -
5455 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5456 address reload is inherited, the address address reload
5457 goes away, so we can ignore this conflict. */
5458 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5459 && ignore_address_reloads
5460 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5461 Then the address address is still needed to store
5462 back the new address. */
5463 && ! rld[reloadnum].out)
5465 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5466 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5468 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5469 && ignore_address_reloads
5470 /* Unless we are reloading an auto_inc expression. */
5471 && ! rld[reloadnum].out)
5473 time2 = rld[i].opnum * 4 + 2;
5475 case RELOAD_FOR_INPUT_ADDRESS:
5476 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5477 && ignore_address_reloads
5478 && ! rld[reloadnum].out)
5480 time2 = rld[i].opnum * 4 + 3;
5482 case RELOAD_FOR_INPUT:
5483 time2 = rld[i].opnum * 4 + 4;
5484 check_earlyclobber = 1;
5486 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5487 == MAX_RECOG_OPERAND * 4 */
5488 case RELOAD_FOR_OPADDR_ADDR:
5489 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5490 && ignore_address_reloads
5491 && ! rld[reloadnum].out)
5493 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5495 case RELOAD_FOR_OPERAND_ADDRESS:
5496 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5497 check_earlyclobber = 1;
5499 case RELOAD_FOR_INSN:
5500 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5502 case RELOAD_FOR_OUTPUT:
5503 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5504 instruction is executed. */
5505 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5507 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5508 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5510 case RELOAD_FOR_OUTADDR_ADDRESS:
5511 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5512 && ignore_address_reloads
5513 && ! rld[reloadnum].out)
5515 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5517 case RELOAD_FOR_OUTPUT_ADDRESS:
5518 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5521 /* If there is no conflict in the input part, handle this
5522 like an output reload. */
5523 if (! rld[i].in || rtx_equal_p (other_input, value))
5525 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5526 /* Earlyclobbered outputs must conflict with inputs. */
5527 if (earlyclobber_operand_p (rld[i].out))
5528 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5533 /* RELOAD_OTHER might be live beyond instruction execution,
5534 but this is not obvious when we set time2 = 1. So check
5535 here if there might be a problem with the new reload
5536 clobbering the register used by the RELOAD_OTHER. */
5544 && (! rld[i].in || rld[i].out
5545 || ! rtx_equal_p (other_input, value)))
5546 || (out && rld[reloadnum].out_reg
5547 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5553 /* Earlyclobbered outputs must conflict with inputs. */
5554 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5560 /* Return 1 if the value in reload reg REGNO, as used by a reload
5561 needed for the part of the insn specified by OPNUM and TYPE,
5562 may be used to load VALUE into it.
5564 MODE is the mode in which the register is used, this is needed to
5565 determine how many hard regs to test.
5567 Other read-only reloads with the same value do not conflict
5568 unless OUT is nonzero and these other reloads have to live while
5569 output reloads live.
5570 If OUT is CONST0_RTX, this is a special case: it means that the
5571 test should not be for using register REGNO as reload register, but
5572 for copying from register REGNO into the reload register.
5574 RELOADNUM is the number of the reload we want to load this value for;
5575 a reload does not conflict with itself.
5577 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5578 reloads that load an address for the very reload we are considering.
5580 The caller has to make sure that there is no conflict with the return
5584 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5585 enum reload_type type, rtx value, rtx out, int reloadnum,
5586 int ignore_address_reloads)
5588 int nregs = hard_regno_nregs[regno][mode];
5590 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5591 value, out, reloadnum,
5592 ignore_address_reloads))
5597 /* Return nonzero if the rtx X is invariant over the current function. */
5598 /* ??? Actually, the places where we use this expect exactly what is
5599 tested here, and not everything that is function invariant. In
5600 particular, the frame pointer and arg pointer are special cased;
5601 pic_offset_table_rtx is not, and we must not spill these things to
5605 function_invariant_p (const_rtx x)
5609 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5611 if (GET_CODE (x) == PLUS
5612 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5613 && CONSTANT_P (XEXP (x, 1)))
5618 /* Determine whether the reload reg X overlaps any rtx'es used for
5619 overriding inheritance. Return nonzero if so. */
5622 conflicts_with_override (rtx x)
5625 for (i = 0; i < n_reloads; i++)
5626 if (reload_override_in[i]
5627 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5632 /* Give an error message saying we failed to find a reload for INSN,
5633 and clear out reload R. */
5635 failed_reload (rtx insn, int r)
5637 if (asm_noperands (PATTERN (insn)) < 0)
5638 /* It's the compiler's fault. */
5639 fatal_insn ("could not find a spill register", insn);
5641 /* It's the user's fault; the operand's mode and constraint
5642 don't match. Disable this reload so we don't crash in final. */
5643 error_for_asm (insn,
5644 "%<asm%> operand constraint incompatible with operand size");
5648 rld[r].optional = 1;
5649 rld[r].secondary_p = 1;
5652 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5653 for reload R. If it's valid, get an rtx for it. Return nonzero if
5656 set_reload_reg (int i, int r)
5659 rtx reg = spill_reg_rtx[i];
5661 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5662 spill_reg_rtx[i] = reg
5663 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5665 regno = true_regnum (reg);
5667 /* Detect when the reload reg can't hold the reload mode.
5668 This used to be one `if', but Sequent compiler can't handle that. */
5669 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5671 enum machine_mode test_mode = VOIDmode;
5673 test_mode = GET_MODE (rld[r].in);
5674 /* If rld[r].in has VOIDmode, it means we will load it
5675 in whatever mode the reload reg has: to wit, rld[r].mode.
5676 We have already tested that for validity. */
5677 /* Aside from that, we need to test that the expressions
5678 to reload from or into have modes which are valid for this
5679 reload register. Otherwise the reload insns would be invalid. */
5680 if (! (rld[r].in != 0 && test_mode != VOIDmode
5681 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5682 if (! (rld[r].out != 0
5683 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5685 /* The reg is OK. */
5688 /* Mark as in use for this insn the reload regs we use
5690 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5691 rld[r].when_needed, rld[r].mode);
5693 rld[r].reg_rtx = reg;
5694 reload_spill_index[r] = spill_regs[i];
5701 /* Find a spill register to use as a reload register for reload R.
5702 LAST_RELOAD is nonzero if this is the last reload for the insn being
5705 Set rld[R].reg_rtx to the register allocated.
5707 We return 1 if successful, or 0 if we couldn't find a spill reg and
5708 we didn't change anything. */
5711 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5716 /* If we put this reload ahead, thinking it is a group,
5717 then insist on finding a group. Otherwise we can grab a
5718 reg that some other reload needs.
5719 (That can happen when we have a 68000 DATA_OR_FP_REG
5720 which is a group of data regs or one fp reg.)
5721 We need not be so restrictive if there are no more reloads
5724 ??? Really it would be nicer to have smarter handling
5725 for that kind of reg class, where a problem like this is normal.
5726 Perhaps those classes should be avoided for reloading
5727 by use of more alternatives. */
5729 int force_group = rld[r].nregs > 1 && ! last_reload;
5731 /* If we want a single register and haven't yet found one,
5732 take any reg in the right class and not in use.
5733 If we want a consecutive group, here is where we look for it.
5735 We use two passes so we can first look for reload regs to
5736 reuse, which are already in use for other reloads in this insn,
5737 and only then use additional registers.
5738 I think that maximizing reuse is needed to make sure we don't
5739 run out of reload regs. Suppose we have three reloads, and
5740 reloads A and B can share regs. These need two regs.
5741 Suppose A and B are given different regs.
5742 That leaves none for C. */
5743 for (pass = 0; pass < 2; pass++)
5745 /* I is the index in spill_regs.
5746 We advance it round-robin between insns to use all spill regs
5747 equally, so that inherited reloads have a chance
5748 of leapfrogging each other. */
5752 for (count = 0; count < n_spills; count++)
5754 int rclass = (int) rld[r].rclass;
5760 regnum = spill_regs[i];
5762 if ((reload_reg_free_p (regnum, rld[r].opnum,
5765 /* We check reload_reg_used to make sure we
5766 don't clobber the return register. */
5767 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5768 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5769 rld[r].when_needed, rld[r].in,
5771 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5772 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5773 /* Look first for regs to share, then for unshared. But
5774 don't share regs used for inherited reloads; they are
5775 the ones we want to preserve. */
5777 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5779 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5782 int nr = hard_regno_nregs[regnum][rld[r].mode];
5783 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5784 (on 68000) got us two FP regs. If NR is 1,
5785 we would reject both of them. */
5788 /* If we need only one reg, we have already won. */
5791 /* But reject a single reg if we demand a group. */
5796 /* Otherwise check that as many consecutive regs as we need
5797 are available here. */
5800 int regno = regnum + nr - 1;
5801 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5802 && spill_reg_order[regno] >= 0
5803 && reload_reg_free_p (regno, rld[r].opnum,
5804 rld[r].when_needed)))
5813 /* If we found something on pass 1, omit pass 2. */
5814 if (count < n_spills)
5818 /* We should have found a spill register by now. */
5819 if (count >= n_spills)
5822 /* I is the index in SPILL_REG_RTX of the reload register we are to
5823 allocate. Get an rtx for it and find its register number. */
5825 return set_reload_reg (i, r);
5828 /* Initialize all the tables needed to allocate reload registers.
5829 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5830 is the array we use to restore the reg_rtx field for every reload. */
5833 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5837 for (i = 0; i < n_reloads; i++)
5838 rld[i].reg_rtx = save_reload_reg_rtx[i];
5840 memset (reload_inherited, 0, MAX_RELOADS);
5841 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5842 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5844 CLEAR_HARD_REG_SET (reload_reg_used);
5845 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5846 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5847 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5848 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5849 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5851 CLEAR_HARD_REG_SET (reg_used_in_insn);
5854 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5855 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5856 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5857 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5858 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5859 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5862 for (i = 0; i < reload_n_operands; i++)
5864 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5865 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5866 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5867 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5868 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5869 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5872 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5874 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5876 for (i = 0; i < n_reloads; i++)
5877 /* If we have already decided to use a certain register,
5878 don't use it in another way. */
5880 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5881 rld[i].when_needed, rld[i].mode);
5884 /* Assign hard reg targets for the pseudo-registers we must reload
5885 into hard regs for this insn.
5886 Also output the instructions to copy them in and out of the hard regs.
5888 For machines with register classes, we are responsible for
5889 finding a reload reg in the proper class. */
5892 choose_reload_regs (struct insn_chain *chain)
5894 rtx insn = chain->insn;
5896 unsigned int max_group_size = 1;
5897 enum reg_class group_class = NO_REGS;
5898 int pass, win, inheritance;
5900 rtx save_reload_reg_rtx[MAX_RELOADS];
5902 /* In order to be certain of getting the registers we need,
5903 we must sort the reloads into order of increasing register class.
5904 Then our grabbing of reload registers will parallel the process
5905 that provided the reload registers.
5907 Also note whether any of the reloads wants a consecutive group of regs.
5908 If so, record the maximum size of the group desired and what
5909 register class contains all the groups needed by this insn. */
5911 for (j = 0; j < n_reloads; j++)
5913 reload_order[j] = j;
5914 if (rld[j].reg_rtx != NULL_RTX)
5916 gcc_assert (REG_P (rld[j].reg_rtx)
5917 && HARD_REGISTER_P (rld[j].reg_rtx));
5918 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5921 reload_spill_index[j] = -1;
5923 if (rld[j].nregs > 1)
5925 max_group_size = MAX (rld[j].nregs, max_group_size);
5927 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5930 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5934 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5936 /* If -O, try first with inheritance, then turning it off.
5937 If not -O, don't do inheritance.
5938 Using inheritance when not optimizing leads to paradoxes
5939 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5940 because one side of the comparison might be inherited. */
5942 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5944 choose_reload_regs_init (chain, save_reload_reg_rtx);
5946 /* Process the reloads in order of preference just found.
5947 Beyond this point, subregs can be found in reload_reg_rtx.
5949 This used to look for an existing reloaded home for all of the
5950 reloads, and only then perform any new reloads. But that could lose
5951 if the reloads were done out of reg-class order because a later
5952 reload with a looser constraint might have an old home in a register
5953 needed by an earlier reload with a tighter constraint.
5955 To solve this, we make two passes over the reloads, in the order
5956 described above. In the first pass we try to inherit a reload
5957 from a previous insn. If there is a later reload that needs a
5958 class that is a proper subset of the class being processed, we must
5959 also allocate a spill register during the first pass.
5961 Then make a second pass over the reloads to allocate any reloads
5962 that haven't been given registers yet. */
5964 for (j = 0; j < n_reloads; j++)
5966 int r = reload_order[j];
5967 rtx search_equiv = NULL_RTX;
5969 /* Ignore reloads that got marked inoperative. */
5970 if (rld[r].out == 0 && rld[r].in == 0
5971 && ! rld[r].secondary_p)
5974 /* If find_reloads chose to use reload_in or reload_out as a reload
5975 register, we don't need to chose one. Otherwise, try even if it
5976 found one since we might save an insn if we find the value lying
5978 Try also when reload_in is a pseudo without a hard reg. */
5979 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5980 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5981 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5982 && !MEM_P (rld[r].in)
5983 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5986 #if 0 /* No longer needed for correct operation.
5987 It might give better code, or might not; worth an experiment? */
5988 /* If this is an optional reload, we can't inherit from earlier insns
5989 until we are sure that any non-optional reloads have been allocated.
5990 The following code takes advantage of the fact that optional reloads
5991 are at the end of reload_order. */
5992 if (rld[r].optional != 0)
5993 for (i = 0; i < j; i++)
5994 if ((rld[reload_order[i]].out != 0
5995 || rld[reload_order[i]].in != 0
5996 || rld[reload_order[i]].secondary_p)
5997 && ! rld[reload_order[i]].optional
5998 && rld[reload_order[i]].reg_rtx == 0)
5999 allocate_reload_reg (chain, reload_order[i], 0);
6002 /* First see if this pseudo is already available as reloaded
6003 for a previous insn. We cannot try to inherit for reloads
6004 that are smaller than the maximum number of registers needed
6005 for groups unless the register we would allocate cannot be used
6008 We could check here to see if this is a secondary reload for
6009 an object that is already in a register of the desired class.
6010 This would avoid the need for the secondary reload register.
6011 But this is complex because we can't easily determine what
6012 objects might want to be loaded via this reload. So let a
6013 register be allocated here. In `emit_reload_insns' we suppress
6014 one of the loads in the case described above. */
6020 enum machine_mode mode = VOIDmode;
6024 else if (REG_P (rld[r].in))
6026 regno = REGNO (rld[r].in);
6027 mode = GET_MODE (rld[r].in);
6029 else if (REG_P (rld[r].in_reg))
6031 regno = REGNO (rld[r].in_reg);
6032 mode = GET_MODE (rld[r].in_reg);
6034 else if (GET_CODE (rld[r].in_reg) == SUBREG
6035 && REG_P (SUBREG_REG (rld[r].in_reg)))
6037 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6038 if (regno < FIRST_PSEUDO_REGISTER)
6039 regno = subreg_regno (rld[r].in_reg);
6041 byte = SUBREG_BYTE (rld[r].in_reg);
6042 mode = GET_MODE (rld[r].in_reg);
6045 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6046 && REG_P (XEXP (rld[r].in_reg, 0)))
6048 regno = REGNO (XEXP (rld[r].in_reg, 0));
6049 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6050 rld[r].out = rld[r].in;
6054 /* This won't work, since REGNO can be a pseudo reg number.
6055 Also, it takes much more hair to keep track of all the things
6056 that can invalidate an inherited reload of part of a pseudoreg. */
6057 else if (GET_CODE (rld[r].in) == SUBREG
6058 && REG_P (SUBREG_REG (rld[r].in)))
6059 regno = subreg_regno (rld[r].in);
6063 && reg_last_reload_reg[regno] != 0
6064 #ifdef CANNOT_CHANGE_MODE_CLASS
6065 /* Verify that the register it's in can be used in
6067 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6068 GET_MODE (reg_last_reload_reg[regno]),
6073 enum reg_class rclass = rld[r].rclass, last_class;
6074 rtx last_reg = reg_last_reload_reg[regno];
6075 enum machine_mode need_mode;
6077 i = REGNO (last_reg);
6078 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6079 last_class = REGNO_REG_CLASS (i);
6085 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
6086 + byte * BITS_PER_UNIT,
6087 GET_MODE_CLASS (mode));
6089 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6090 >= GET_MODE_SIZE (need_mode))
6091 && reg_reloaded_contents[i] == regno
6092 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6093 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6094 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6095 /* Even if we can't use this register as a reload
6096 register, we might use it for reload_override_in,
6097 if copying it to the desired class is cheap
6099 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6100 < MEMORY_MOVE_COST (mode, rclass, 1))
6101 && (secondary_reload_class (1, rclass, mode,
6104 #ifdef SECONDARY_MEMORY_NEEDED
6105 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6110 && (rld[r].nregs == max_group_size
6111 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6113 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6114 rld[r].when_needed, rld[r].in,
6117 /* If a group is needed, verify that all the subsequent
6118 registers still have their values intact. */
6119 int nr = hard_regno_nregs[i][rld[r].mode];
6122 for (k = 1; k < nr; k++)
6123 if (reg_reloaded_contents[i + k] != regno
6124 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6132 last_reg = (GET_MODE (last_reg) == mode
6133 ? last_reg : gen_rtx_REG (mode, i));
6136 for (k = 0; k < nr; k++)
6137 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6140 /* We found a register that contains the
6141 value we need. If this register is the
6142 same as an `earlyclobber' operand of the
6143 current insn, just mark it as a place to
6144 reload from since we can't use it as the
6145 reload register itself. */
6147 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6148 if (reg_overlap_mentioned_for_reload_p
6149 (reg_last_reload_reg[regno],
6150 reload_earlyclobbers[i1]))
6153 if (i1 != n_earlyclobbers
6154 || ! (free_for_value_p (i, rld[r].mode,
6156 rld[r].when_needed, rld[r].in,
6158 /* Don't use it if we'd clobber a pseudo reg. */
6159 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6161 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6162 /* Don't clobber the frame pointer. */
6163 || (i == HARD_FRAME_POINTER_REGNUM
6164 && frame_pointer_needed
6166 /* Don't really use the inherited spill reg
6167 if we need it wider than we've got it. */
6168 || (GET_MODE_SIZE (rld[r].mode)
6169 > GET_MODE_SIZE (mode))
6172 /* If find_reloads chose reload_out as reload
6173 register, stay with it - that leaves the
6174 inherited register for subsequent reloads. */
6175 || (rld[r].out && rld[r].reg_rtx
6176 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6178 if (! rld[r].optional)
6180 reload_override_in[r] = last_reg;
6181 reload_inheritance_insn[r]
6182 = reg_reloaded_insn[i];
6188 /* We can use this as a reload reg. */
6189 /* Mark the register as in use for this part of
6191 mark_reload_reg_in_use (i,
6195 rld[r].reg_rtx = last_reg;
6196 reload_inherited[r] = 1;
6197 reload_inheritance_insn[r]
6198 = reg_reloaded_insn[i];
6199 reload_spill_index[r] = i;
6200 for (k = 0; k < nr; k++)
6201 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6209 /* Here's another way to see if the value is already lying around. */
6212 && ! reload_inherited[r]
6214 && (CONSTANT_P (rld[r].in)
6215 || GET_CODE (rld[r].in) == PLUS
6216 || REG_P (rld[r].in)
6217 || MEM_P (rld[r].in))
6218 && (rld[r].nregs == max_group_size
6219 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6220 search_equiv = rld[r].in;
6221 /* If this is an output reload from a simple move insn, look
6222 if an equivalence for the input is available. */
6223 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6225 rtx set = single_set (insn);
6228 && rtx_equal_p (rld[r].out, SET_DEST (set))
6229 && CONSTANT_P (SET_SRC (set)))
6230 search_equiv = SET_SRC (set);
6236 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6237 -1, NULL, 0, rld[r].mode);
6243 regno = REGNO (equiv);
6246 /* This must be a SUBREG of a hard register.
6247 Make a new REG since this might be used in an
6248 address and not all machines support SUBREGs
6250 gcc_assert (GET_CODE (equiv) == SUBREG);
6251 regno = subreg_regno (equiv);
6252 equiv = gen_rtx_REG (rld[r].mode, regno);
6253 /* If we choose EQUIV as the reload register, but the
6254 loop below decides to cancel the inheritance, we'll
6255 end up reloading EQUIV in rld[r].mode, not the mode
6256 it had originally. That isn't safe when EQUIV isn't
6257 available as a spill register since its value might
6258 still be live at this point. */
6259 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6260 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6265 /* If we found a spill reg, reject it unless it is free
6266 and of the desired class. */
6270 int bad_for_class = 0;
6271 int max_regno = regno + rld[r].nregs;
6273 for (i = regno; i < max_regno; i++)
6275 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6277 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6282 && ! free_for_value_p (regno, rld[r].mode,
6283 rld[r].opnum, rld[r].when_needed,
6284 rld[r].in, rld[r].out, r, 1))
6289 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6292 /* We found a register that contains the value we need.
6293 If this register is the same as an `earlyclobber' operand
6294 of the current insn, just mark it as a place to reload from
6295 since we can't use it as the reload register itself. */
6298 for (i = 0; i < n_earlyclobbers; i++)
6299 if (reg_overlap_mentioned_for_reload_p (equiv,
6300 reload_earlyclobbers[i]))
6302 if (! rld[r].optional)
6303 reload_override_in[r] = equiv;
6308 /* If the equiv register we have found is explicitly clobbered
6309 in the current insn, it depends on the reload type if we
6310 can use it, use it for reload_override_in, or not at all.
6311 In particular, we then can't use EQUIV for a
6312 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6316 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6317 switch (rld[r].when_needed)
6319 case RELOAD_FOR_OTHER_ADDRESS:
6320 case RELOAD_FOR_INPADDR_ADDRESS:
6321 case RELOAD_FOR_INPUT_ADDRESS:
6322 case RELOAD_FOR_OPADDR_ADDR:
6325 case RELOAD_FOR_INPUT:
6326 case RELOAD_FOR_OPERAND_ADDRESS:
6327 if (! rld[r].optional)
6328 reload_override_in[r] = equiv;
6334 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6335 switch (rld[r].when_needed)
6337 case RELOAD_FOR_OTHER_ADDRESS:
6338 case RELOAD_FOR_INPADDR_ADDRESS:
6339 case RELOAD_FOR_INPUT_ADDRESS:
6340 case RELOAD_FOR_OPADDR_ADDR:
6341 case RELOAD_FOR_OPERAND_ADDRESS:
6342 case RELOAD_FOR_INPUT:
6345 if (! rld[r].optional)
6346 reload_override_in[r] = equiv;
6354 /* If we found an equivalent reg, say no code need be generated
6355 to load it, and use it as our reload reg. */
6357 && (regno != HARD_FRAME_POINTER_REGNUM
6358 || !frame_pointer_needed))
6360 int nr = hard_regno_nregs[regno][rld[r].mode];
6362 rld[r].reg_rtx = equiv;
6363 reload_inherited[r] = 1;
6365 /* If reg_reloaded_valid is not set for this register,
6366 there might be a stale spill_reg_store lying around.
6367 We must clear it, since otherwise emit_reload_insns
6368 might delete the store. */
6369 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6370 spill_reg_store[regno] = NULL_RTX;
6371 /* If any of the hard registers in EQUIV are spill
6372 registers, mark them as in use for this insn. */
6373 for (k = 0; k < nr; k++)
6375 i = spill_reg_order[regno + k];
6378 mark_reload_reg_in_use (regno, rld[r].opnum,
6381 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6388 /* If we found a register to use already, or if this is an optional
6389 reload, we are done. */
6390 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6394 /* No longer needed for correct operation. Might or might
6395 not give better code on the average. Want to experiment? */
6397 /* See if there is a later reload that has a class different from our
6398 class that intersects our class or that requires less register
6399 than our reload. If so, we must allocate a register to this
6400 reload now, since that reload might inherit a previous reload
6401 and take the only available register in our class. Don't do this
6402 for optional reloads since they will force all previous reloads
6403 to be allocated. Also don't do this for reloads that have been
6406 for (i = j + 1; i < n_reloads; i++)
6408 int s = reload_order[i];
6410 if ((rld[s].in == 0 && rld[s].out == 0
6411 && ! rld[s].secondary_p)
6415 if ((rld[s].rclass != rld[r].rclass
6416 && reg_classes_intersect_p (rld[r].rclass,
6418 || rld[s].nregs < rld[r].nregs)
6425 allocate_reload_reg (chain, r, j == n_reloads - 1);
6429 /* Now allocate reload registers for anything non-optional that
6430 didn't get one yet. */
6431 for (j = 0; j < n_reloads; j++)
6433 int r = reload_order[j];
6435 /* Ignore reloads that got marked inoperative. */
6436 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6439 /* Skip reloads that already have a register allocated or are
6441 if (rld[r].reg_rtx != 0 || rld[r].optional)
6444 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6448 /* If that loop got all the way, we have won. */
6455 /* Loop around and try without any inheritance. */
6460 /* First undo everything done by the failed attempt
6461 to allocate with inheritance. */
6462 choose_reload_regs_init (chain, save_reload_reg_rtx);
6464 /* Some sanity tests to verify that the reloads found in the first
6465 pass are identical to the ones we have now. */
6466 gcc_assert (chain->n_reloads == n_reloads);
6468 for (i = 0; i < n_reloads; i++)
6470 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6472 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6473 for (j = 0; j < n_spills; j++)
6474 if (spill_regs[j] == chain->rld[i].regno)
6475 if (! set_reload_reg (j, i))
6476 failed_reload (chain->insn, i);
6480 /* If we thought we could inherit a reload, because it seemed that
6481 nothing else wanted the same reload register earlier in the insn,
6482 verify that assumption, now that all reloads have been assigned.
6483 Likewise for reloads where reload_override_in has been set. */
6485 /* If doing expensive optimizations, do one preliminary pass that doesn't
6486 cancel any inheritance, but removes reloads that have been needed only
6487 for reloads that we know can be inherited. */
6488 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6490 for (j = 0; j < n_reloads; j++)
6492 int r = reload_order[j];
6494 if (reload_inherited[r] && rld[r].reg_rtx)
6495 check_reg = rld[r].reg_rtx;
6496 else if (reload_override_in[r]
6497 && (REG_P (reload_override_in[r])
6498 || GET_CODE (reload_override_in[r]) == SUBREG))
6499 check_reg = reload_override_in[r];
6502 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6503 rld[r].opnum, rld[r].when_needed, rld[r].in,
6504 (reload_inherited[r]
6505 ? rld[r].out : const0_rtx),
6510 reload_inherited[r] = 0;
6511 reload_override_in[r] = 0;
6513 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6514 reload_override_in, then we do not need its related
6515 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6516 likewise for other reload types.
6517 We handle this by removing a reload when its only replacement
6518 is mentioned in reload_in of the reload we are going to inherit.
6519 A special case are auto_inc expressions; even if the input is
6520 inherited, we still need the address for the output. We can
6521 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6522 If we succeeded removing some reload and we are doing a preliminary
6523 pass just to remove such reloads, make another pass, since the
6524 removal of one reload might allow us to inherit another one. */
6526 && rld[r].out != rld[r].in
6527 && remove_address_replacements (rld[r].in) && pass)
6532 /* Now that reload_override_in is known valid,
6533 actually override reload_in. */
6534 for (j = 0; j < n_reloads; j++)
6535 if (reload_override_in[j])
6536 rld[j].in = reload_override_in[j];
6538 /* If this reload won't be done because it has been canceled or is
6539 optional and not inherited, clear reload_reg_rtx so other
6540 routines (such as subst_reloads) don't get confused. */
6541 for (j = 0; j < n_reloads; j++)
6542 if (rld[j].reg_rtx != 0
6543 && ((rld[j].optional && ! reload_inherited[j])
6544 || (rld[j].in == 0 && rld[j].out == 0
6545 && ! rld[j].secondary_p)))
6547 int regno = true_regnum (rld[j].reg_rtx);
6549 if (spill_reg_order[regno] >= 0)
6550 clear_reload_reg_in_use (regno, rld[j].opnum,
6551 rld[j].when_needed, rld[j].mode);
6553 reload_spill_index[j] = -1;
6556 /* Record which pseudos and which spill regs have output reloads. */
6557 for (j = 0; j < n_reloads; j++)
6559 int r = reload_order[j];
6561 i = reload_spill_index[r];
6563 /* I is nonneg if this reload uses a register.
6564 If rld[r].reg_rtx is 0, this is an optional reload
6565 that we opted to ignore. */
6566 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6567 && rld[r].reg_rtx != 0)
6569 int nregno = REGNO (rld[r].out_reg);
6572 if (nregno < FIRST_PSEUDO_REGISTER)
6573 nr = hard_regno_nregs[nregno][rld[r].mode];
6576 SET_REGNO_REG_SET (®_has_output_reload,
6581 nr = hard_regno_nregs[i][rld[r].mode];
6583 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6586 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6587 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6588 || rld[r].when_needed == RELOAD_FOR_INSN);
6593 /* Deallocate the reload register for reload R. This is called from
6594 remove_address_replacements. */
6597 deallocate_reload_reg (int r)
6601 if (! rld[r].reg_rtx)
6603 regno = true_regnum (rld[r].reg_rtx);
6605 if (spill_reg_order[regno] >= 0)
6606 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6608 reload_spill_index[r] = -1;
6611 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6612 reloads of the same item for fear that we might not have enough reload
6613 registers. However, normally they will get the same reload register
6614 and hence actually need not be loaded twice.
6616 Here we check for the most common case of this phenomenon: when we have
6617 a number of reloads for the same object, each of which were allocated
6618 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6619 reload, and is not modified in the insn itself. If we find such,
6620 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6621 This will not increase the number of spill registers needed and will
6622 prevent redundant code. */
6625 merge_assigned_reloads (rtx insn)
6629 /* Scan all the reloads looking for ones that only load values and
6630 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6631 assigned and not modified by INSN. */
6633 for (i = 0; i < n_reloads; i++)
6635 int conflicting_input = 0;
6636 int max_input_address_opnum = -1;
6637 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6639 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6640 || rld[i].out != 0 || rld[i].reg_rtx == 0
6641 || reg_set_p (rld[i].reg_rtx, insn))
6644 /* Look at all other reloads. Ensure that the only use of this
6645 reload_reg_rtx is in a reload that just loads the same value
6646 as we do. Note that any secondary reloads must be of the identical
6647 class since the values, modes, and result registers are the
6648 same, so we need not do anything with any secondary reloads. */
6650 for (j = 0; j < n_reloads; j++)
6652 if (i == j || rld[j].reg_rtx == 0
6653 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6657 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6658 && rld[j].opnum > max_input_address_opnum)
6659 max_input_address_opnum = rld[j].opnum;
6661 /* If the reload regs aren't exactly the same (e.g, different modes)
6662 or if the values are different, we can't merge this reload.
6663 But if it is an input reload, we might still merge
6664 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6666 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6667 || rld[j].out != 0 || rld[j].in == 0
6668 || ! rtx_equal_p (rld[i].in, rld[j].in))
6670 if (rld[j].when_needed != RELOAD_FOR_INPUT
6671 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6672 || rld[i].opnum > rld[j].opnum)
6673 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6675 conflicting_input = 1;
6676 if (min_conflicting_input_opnum > rld[j].opnum)
6677 min_conflicting_input_opnum = rld[j].opnum;
6681 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6682 we, in fact, found any matching reloads. */
6685 && max_input_address_opnum <= min_conflicting_input_opnum)
6687 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6689 for (j = 0; j < n_reloads; j++)
6690 if (i != j && rld[j].reg_rtx != 0
6691 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6692 && (! conflicting_input
6693 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6694 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6696 rld[i].when_needed = RELOAD_OTHER;
6698 reload_spill_index[j] = -1;
6699 transfer_replacements (i, j);
6702 /* If this is now RELOAD_OTHER, look for any reloads that
6703 load parts of this operand and set them to
6704 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6705 RELOAD_OTHER for outputs. Note that this test is
6706 equivalent to looking for reloads for this operand
6709 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6710 it may share registers with a RELOAD_FOR_INPUT, so we can
6711 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6712 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6714 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6715 instruction is assigned the same register as the earlier
6716 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6717 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6718 instruction to be deleted later on. */
6720 if (rld[i].when_needed == RELOAD_OTHER)
6721 for (j = 0; j < n_reloads; j++)
6723 && rld[j].when_needed != RELOAD_OTHER
6724 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6725 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6726 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6727 && (! conflicting_input
6728 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6729 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6730 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6736 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6737 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6738 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6740 /* Check to see if we accidentally converted two
6741 reloads that use the same reload register with
6742 different inputs to the same type. If so, the
6743 resulting code won't work. */
6745 for (k = 0; k < j; k++)
6746 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6747 || rld[k].when_needed != rld[j].when_needed
6748 || !rtx_equal_p (rld[k].reg_rtx,
6750 || rtx_equal_p (rld[k].in,
6757 /* These arrays are filled by emit_reload_insns and its subroutines. */
6758 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6759 static rtx other_input_address_reload_insns = 0;
6760 static rtx other_input_reload_insns = 0;
6761 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6762 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6763 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6764 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6765 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6766 static rtx operand_reload_insns = 0;
6767 static rtx other_operand_reload_insns = 0;
6768 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6770 /* Values to be put in spill_reg_store are put here first. */
6771 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6772 static HARD_REG_SET reg_reloaded_died;
6774 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6775 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6776 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6777 adjusted register, and return true. Otherwise, return false. */
6779 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6780 enum reg_class new_class,
6781 enum machine_mode new_mode)
6786 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6788 unsigned regno = REGNO (reg);
6790 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6792 if (GET_MODE (reg) != new_mode)
6794 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6796 if (hard_regno_nregs[regno][new_mode]
6797 > hard_regno_nregs[regno][GET_MODE (reg)])
6799 reg = reload_adjust_reg_for_mode (reg, new_mode);
6807 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6808 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6809 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6810 adjusted register, and return true. Otherwise, return false. */
6812 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6813 enum insn_code icode)
6816 enum reg_class new_class = scratch_reload_class (icode);
6817 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6819 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6820 new_class, new_mode);
6823 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6824 has the number J. OLD contains the value to be used as input. */
6827 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6830 rtx insn = chain->insn;
6832 rtx oldequiv_reg = 0;
6835 enum machine_mode mode;
6838 /* delete_output_reload is only invoked properly if old contains
6839 the original pseudo register. Since this is replaced with a
6840 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6841 find the pseudo in RELOAD_IN_REG. */
6842 if (reload_override_in[j]
6843 && REG_P (rl->in_reg))
6850 else if (REG_P (oldequiv))
6851 oldequiv_reg = oldequiv;
6852 else if (GET_CODE (oldequiv) == SUBREG)
6853 oldequiv_reg = SUBREG_REG (oldequiv);
6855 reloadreg = reload_reg_rtx_for_input[j];
6856 mode = GET_MODE (reloadreg);
6858 /* If we are reloading from a register that was recently stored in
6859 with an output-reload, see if we can prove there was
6860 actually no need to store the old value in it. */
6862 if (optimize && REG_P (oldequiv)
6863 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6864 && spill_reg_store[REGNO (oldequiv)]
6866 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6867 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6869 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6871 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6874 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6875 oldequiv = SUBREG_REG (oldequiv);
6876 if (GET_MODE (oldequiv) != VOIDmode
6877 && mode != GET_MODE (oldequiv))
6878 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6880 /* Switch to the right place to emit the reload insns. */
6881 switch (rl->when_needed)
6884 where = &other_input_reload_insns;
6886 case RELOAD_FOR_INPUT:
6887 where = &input_reload_insns[rl->opnum];
6889 case RELOAD_FOR_INPUT_ADDRESS:
6890 where = &input_address_reload_insns[rl->opnum];
6892 case RELOAD_FOR_INPADDR_ADDRESS:
6893 where = &inpaddr_address_reload_insns[rl->opnum];
6895 case RELOAD_FOR_OUTPUT_ADDRESS:
6896 where = &output_address_reload_insns[rl->opnum];
6898 case RELOAD_FOR_OUTADDR_ADDRESS:
6899 where = &outaddr_address_reload_insns[rl->opnum];
6901 case RELOAD_FOR_OPERAND_ADDRESS:
6902 where = &operand_reload_insns;
6904 case RELOAD_FOR_OPADDR_ADDR:
6905 where = &other_operand_reload_insns;
6907 case RELOAD_FOR_OTHER_ADDRESS:
6908 where = &other_input_address_reload_insns;
6914 push_to_sequence (*where);
6916 /* Auto-increment addresses must be reloaded in a special way. */
6917 if (rl->out && ! rl->out_reg)
6919 /* We are not going to bother supporting the case where a
6920 incremented register can't be copied directly from
6921 OLDEQUIV since this seems highly unlikely. */
6922 gcc_assert (rl->secondary_in_reload < 0);
6924 if (reload_inherited[j])
6925 oldequiv = reloadreg;
6927 old = XEXP (rl->in_reg, 0);
6929 if (optimize && REG_P (oldequiv)
6930 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6931 && spill_reg_store[REGNO (oldequiv)]
6933 && (dead_or_set_p (insn,
6934 spill_reg_stored_to[REGNO (oldequiv)])
6935 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6937 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6939 /* Prevent normal processing of this reload. */
6941 /* Output a special code sequence for this case. */
6942 new_spill_reg_store[REGNO (reloadreg)]
6943 = inc_for_reload (reloadreg, oldequiv, rl->out,
6947 /* If we are reloading a pseudo-register that was set by the previous
6948 insn, see if we can get rid of that pseudo-register entirely
6949 by redirecting the previous insn into our reload register. */
6951 else if (optimize && REG_P (old)
6952 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6953 && dead_or_set_p (insn, old)
6954 /* This is unsafe if some other reload
6955 uses the same reg first. */
6956 && ! conflicts_with_override (reloadreg)
6957 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6958 rl->when_needed, old, rl->out, j, 0))
6960 rtx temp = PREV_INSN (insn);
6961 while (temp && NOTE_P (temp))
6962 temp = PREV_INSN (temp);
6964 && NONJUMP_INSN_P (temp)
6965 && GET_CODE (PATTERN (temp)) == SET
6966 && SET_DEST (PATTERN (temp)) == old
6967 /* Make sure we can access insn_operand_constraint. */
6968 && asm_noperands (PATTERN (temp)) < 0
6969 /* This is unsafe if operand occurs more than once in current
6970 insn. Perhaps some occurrences aren't reloaded. */
6971 && count_occurrences (PATTERN (insn), old, 0) == 1)
6973 rtx old = SET_DEST (PATTERN (temp));
6974 /* Store into the reload register instead of the pseudo. */
6975 SET_DEST (PATTERN (temp)) = reloadreg;
6977 /* Verify that resulting insn is valid. */
6978 extract_insn (temp);
6979 if (constrain_operands (1))
6981 /* If the previous insn is an output reload, the source is
6982 a reload register, and its spill_reg_store entry will
6983 contain the previous destination. This is now
6985 if (REG_P (SET_SRC (PATTERN (temp)))
6986 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6988 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6989 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6992 /* If these are the only uses of the pseudo reg,
6993 pretend for GDB it lives in the reload reg we used. */
6994 if (REG_N_DEATHS (REGNO (old)) == 1
6995 && REG_N_SETS (REGNO (old)) == 1)
6997 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6998 if (flag_ira && optimize)
6999 /* Inform IRA about the change. */
7000 ira_mark_allocation_change (REGNO (old));
7001 alter_reg (REGNO (old), -1, false);
7007 SET_DEST (PATTERN (temp)) = old;
7012 /* We can't do that, so output an insn to load RELOADREG. */
7014 /* If we have a secondary reload, pick up the secondary register
7015 and icode, if any. If OLDEQUIV and OLD are different or
7016 if this is an in-out reload, recompute whether or not we
7017 still need a secondary register and what the icode should
7018 be. If we still need a secondary register and the class or
7019 icode is different, go back to reloading from OLD if using
7020 OLDEQUIV means that we got the wrong type of register. We
7021 cannot have different class or icode due to an in-out reload
7022 because we don't make such reloads when both the input and
7023 output need secondary reload registers. */
7025 if (! special && rl->secondary_in_reload >= 0)
7027 rtx second_reload_reg = 0;
7028 rtx third_reload_reg = 0;
7029 int secondary_reload = rl->secondary_in_reload;
7030 rtx real_oldequiv = oldequiv;
7033 enum insn_code icode;
7034 enum insn_code tertiary_icode = CODE_FOR_nothing;
7036 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7037 and similarly for OLD.
7038 See comments in get_secondary_reload in reload.c. */
7039 /* If it is a pseudo that cannot be replaced with its
7040 equivalent MEM, we must fall back to reload_in, which
7041 will have all the necessary substitutions registered.
7042 Likewise for a pseudo that can't be replaced with its
7043 equivalent constant.
7045 Take extra care for subregs of such pseudos. Note that
7046 we cannot use reg_equiv_mem in this case because it is
7047 not in the right mode. */
7050 if (GET_CODE (tmp) == SUBREG)
7051 tmp = SUBREG_REG (tmp);
7053 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7054 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7055 || reg_equiv_constant[REGNO (tmp)] != 0))
7057 if (! reg_equiv_mem[REGNO (tmp)]
7058 || num_not_at_initial_offset
7059 || GET_CODE (oldequiv) == SUBREG)
7060 real_oldequiv = rl->in;
7062 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7066 if (GET_CODE (tmp) == SUBREG)
7067 tmp = SUBREG_REG (tmp);
7069 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7070 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7071 || reg_equiv_constant[REGNO (tmp)] != 0))
7073 if (! reg_equiv_mem[REGNO (tmp)]
7074 || num_not_at_initial_offset
7075 || GET_CODE (old) == SUBREG)
7078 real_old = reg_equiv_mem[REGNO (tmp)];
7081 second_reload_reg = rld[secondary_reload].reg_rtx;
7082 if (rld[secondary_reload].secondary_in_reload >= 0)
7084 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7086 third_reload_reg = rld[tertiary_reload].reg_rtx;
7087 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7088 /* We'd have to add more code for quartary reloads. */
7089 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7091 icode = rl->secondary_in_icode;
7093 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7094 || (rl->in != 0 && rl->out != 0))
7096 secondary_reload_info sri, sri2;
7097 enum reg_class new_class, new_t_class;
7099 sri.icode = CODE_FOR_nothing;
7100 sri.prev_sri = NULL;
7101 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7104 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7105 second_reload_reg = 0;
7106 else if (new_class == NO_REGS)
7108 if (reload_adjust_reg_for_icode (&second_reload_reg,
7109 third_reload_reg, sri.icode))
7110 icode = sri.icode, third_reload_reg = 0;
7112 oldequiv = old, real_oldequiv = real_old;
7114 else if (sri.icode != CODE_FOR_nothing)
7115 /* We currently lack a way to express this in reloads. */
7119 sri2.icode = CODE_FOR_nothing;
7120 sri2.prev_sri = &sri;
7121 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7122 new_class, mode, &sri);
7123 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7125 if (reload_adjust_reg_for_temp (&second_reload_reg,
7128 third_reload_reg = 0, tertiary_icode = sri2.icode;
7130 oldequiv = old, real_oldequiv = real_old;
7132 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7134 rtx intermediate = second_reload_reg;
7136 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7138 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7141 second_reload_reg = intermediate;
7142 tertiary_icode = sri2.icode;
7145 oldequiv = old, real_oldequiv = real_old;
7147 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7149 rtx intermediate = second_reload_reg;
7151 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7153 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7156 second_reload_reg = intermediate;
7157 tertiary_icode = sri2.icode;
7160 oldequiv = old, real_oldequiv = real_old;
7163 /* This could be handled more intelligently too. */
7164 oldequiv = old, real_oldequiv = real_old;
7168 /* If we still need a secondary reload register, check
7169 to see if it is being used as a scratch or intermediate
7170 register and generate code appropriately. If we need
7171 a scratch register, use REAL_OLDEQUIV since the form of
7172 the insn may depend on the actual address if it is
7175 if (second_reload_reg)
7177 if (icode != CODE_FOR_nothing)
7179 /* We'd have to add extra code to handle this case. */
7180 gcc_assert (!third_reload_reg);
7182 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7183 second_reload_reg));
7188 /* See if we need a scratch register to load the
7189 intermediate register (a tertiary reload). */
7190 if (tertiary_icode != CODE_FOR_nothing)
7192 emit_insn ((GEN_FCN (tertiary_icode)
7193 (second_reload_reg, real_oldequiv,
7194 third_reload_reg)));
7196 else if (third_reload_reg)
7198 gen_reload (third_reload_reg, real_oldequiv,
7201 gen_reload (second_reload_reg, third_reload_reg,
7206 gen_reload (second_reload_reg, real_oldequiv,
7210 oldequiv = second_reload_reg;
7215 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7217 rtx real_oldequiv = oldequiv;
7219 if ((REG_P (oldequiv)
7220 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7221 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7222 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7223 || (GET_CODE (oldequiv) == SUBREG
7224 && REG_P (SUBREG_REG (oldequiv))
7225 && (REGNO (SUBREG_REG (oldequiv))
7226 >= FIRST_PSEUDO_REGISTER)
7227 && ((reg_equiv_memory_loc
7228 [REGNO (SUBREG_REG (oldequiv))] != 0)
7229 || (reg_equiv_constant
7230 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7231 || (CONSTANT_P (oldequiv)
7232 && (PREFERRED_RELOAD_CLASS (oldequiv,
7233 REGNO_REG_CLASS (REGNO (reloadreg)))
7235 real_oldequiv = rl->in;
7236 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7240 if (flag_non_call_exceptions)
7241 copy_eh_notes (insn, get_insns ());
7243 /* End this sequence. */
7244 *where = get_insns ();
7247 /* Update reload_override_in so that delete_address_reloads_1
7248 can see the actual register usage. */
7250 reload_override_in[j] = oldequiv;
7253 /* Generate insns to for the output reload RL, which is for the insn described
7254 by CHAIN and has the number J. */
7256 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7260 rtx insn = chain->insn;
7263 enum machine_mode mode;
7267 if (rl->when_needed == RELOAD_OTHER)
7270 push_to_sequence (output_reload_insns[rl->opnum]);
7272 rl_reg_rtx = reload_reg_rtx_for_output[j];
7273 mode = GET_MODE (rl_reg_rtx);
7275 reloadreg = rl_reg_rtx;
7277 /* If we need two reload regs, set RELOADREG to the intermediate
7278 one, since it will be stored into OLD. We might need a secondary
7279 register only for an input reload, so check again here. */
7281 if (rl->secondary_out_reload >= 0)
7284 int secondary_reload = rl->secondary_out_reload;
7285 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7287 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7288 && reg_equiv_mem[REGNO (old)] != 0)
7289 real_old = reg_equiv_mem[REGNO (old)];
7291 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7293 rtx second_reloadreg = reloadreg;
7294 reloadreg = rld[secondary_reload].reg_rtx;
7296 /* See if RELOADREG is to be used as a scratch register
7297 or as an intermediate register. */
7298 if (rl->secondary_out_icode != CODE_FOR_nothing)
7300 /* We'd have to add extra code to handle this case. */
7301 gcc_assert (tertiary_reload < 0);
7303 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7304 (real_old, second_reloadreg, reloadreg)));
7309 /* See if we need both a scratch and intermediate reload
7312 enum insn_code tertiary_icode
7313 = rld[secondary_reload].secondary_out_icode;
7315 /* We'd have to add more code for quartary reloads. */
7316 gcc_assert (tertiary_reload < 0
7317 || rld[tertiary_reload].secondary_out_reload < 0);
7319 if (GET_MODE (reloadreg) != mode)
7320 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7322 if (tertiary_icode != CODE_FOR_nothing)
7324 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7327 /* Copy primary reload reg to secondary reload reg.
7328 (Note that these have been swapped above, then
7329 secondary reload reg to OLD using our insn.) */
7331 /* If REAL_OLD is a paradoxical SUBREG, remove it
7332 and try to put the opposite SUBREG on
7334 if (GET_CODE (real_old) == SUBREG
7335 && (GET_MODE_SIZE (GET_MODE (real_old))
7336 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7337 && 0 != (tem = gen_lowpart_common
7338 (GET_MODE (SUBREG_REG (real_old)),
7340 real_old = SUBREG_REG (real_old), reloadreg = tem;
7342 gen_reload (reloadreg, second_reloadreg,
7343 rl->opnum, rl->when_needed);
7344 emit_insn ((GEN_FCN (tertiary_icode)
7345 (real_old, reloadreg, third_reloadreg)));
7351 /* Copy between the reload regs here and then to
7354 gen_reload (reloadreg, second_reloadreg,
7355 rl->opnum, rl->when_needed);
7356 if (tertiary_reload >= 0)
7358 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7360 gen_reload (third_reloadreg, reloadreg,
7361 rl->opnum, rl->when_needed);
7362 reloadreg = third_reloadreg;
7369 /* Output the last reload insn. */
7374 /* Don't output the last reload if OLD is not the dest of
7375 INSN and is in the src and is clobbered by INSN. */
7376 if (! flag_expensive_optimizations
7378 || !(set = single_set (insn))
7379 || rtx_equal_p (old, SET_DEST (set))
7380 || !reg_mentioned_p (old, SET_SRC (set))
7381 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7382 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7383 gen_reload (old, reloadreg, rl->opnum,
7387 /* Look at all insns we emitted, just to be safe. */
7388 for (p = get_insns (); p; p = NEXT_INSN (p))
7391 rtx pat = PATTERN (p);
7393 /* If this output reload doesn't come from a spill reg,
7394 clear any memory of reloaded copies of the pseudo reg.
7395 If this output reload comes from a spill reg,
7396 reg_has_output_reload will make this do nothing. */
7397 note_stores (pat, forget_old_reloads_1, NULL);
7399 if (reg_mentioned_p (rl_reg_rtx, pat))
7401 rtx set = single_set (insn);
7402 if (reload_spill_index[j] < 0
7404 && SET_SRC (set) == rl_reg_rtx)
7406 int src = REGNO (SET_SRC (set));
7408 reload_spill_index[j] = src;
7409 SET_HARD_REG_BIT (reg_is_output_reload, src);
7410 if (find_regno_note (insn, REG_DEAD, src))
7411 SET_HARD_REG_BIT (reg_reloaded_died, src);
7413 if (HARD_REGISTER_P (rl_reg_rtx))
7415 int s = rl->secondary_out_reload;
7416 set = single_set (p);
7417 /* If this reload copies only to the secondary reload
7418 register, the secondary reload does the actual
7420 if (s >= 0 && set == NULL_RTX)
7421 /* We can't tell what function the secondary reload
7422 has and where the actual store to the pseudo is
7423 made; leave new_spill_reg_store alone. */
7426 && SET_SRC (set) == rl_reg_rtx
7427 && SET_DEST (set) == rld[s].reg_rtx)
7429 /* Usually the next instruction will be the
7430 secondary reload insn; if we can confirm
7431 that it is, setting new_spill_reg_store to
7432 that insn will allow an extra optimization. */
7433 rtx s_reg = rld[s].reg_rtx;
7434 rtx next = NEXT_INSN (p);
7435 rld[s].out = rl->out;
7436 rld[s].out_reg = rl->out_reg;
7437 set = single_set (next);
7438 if (set && SET_SRC (set) == s_reg
7439 && ! new_spill_reg_store[REGNO (s_reg)])
7441 SET_HARD_REG_BIT (reg_is_output_reload,
7443 new_spill_reg_store[REGNO (s_reg)] = next;
7447 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7452 if (rl->when_needed == RELOAD_OTHER)
7454 emit_insn (other_output_reload_insns[rl->opnum]);
7455 other_output_reload_insns[rl->opnum] = get_insns ();
7458 output_reload_insns[rl->opnum] = get_insns ();
7460 if (flag_non_call_exceptions)
7461 copy_eh_notes (insn, get_insns ());
7466 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7467 and has the number J. */
7469 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7471 rtx insn = chain->insn;
7472 rtx old = (rl->in && MEM_P (rl->in)
7473 ? rl->in_reg : rl->in);
7474 rtx reg_rtx = rl->reg_rtx;
7478 enum machine_mode mode;
7480 /* Determine the mode to reload in.
7481 This is very tricky because we have three to choose from.
7482 There is the mode the insn operand wants (rl->inmode).
7483 There is the mode of the reload register RELOADREG.
7484 There is the intrinsic mode of the operand, which we could find
7485 by stripping some SUBREGs.
7486 It turns out that RELOADREG's mode is irrelevant:
7487 we can change that arbitrarily.
7489 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7490 then the reload reg may not support QImode moves, so use SImode.
7491 If foo is in memory due to spilling a pseudo reg, this is safe,
7492 because the QImode value is in the least significant part of a
7493 slot big enough for a SImode. If foo is some other sort of
7494 memory reference, then it is impossible to reload this case,
7495 so previous passes had better make sure this never happens.
7497 Then consider a one-word union which has SImode and one of its
7498 members is a float, being fetched as (SUBREG:SF union:SI).
7499 We must fetch that as SFmode because we could be loading into
7500 a float-only register. In this case OLD's mode is correct.
7502 Consider an immediate integer: it has VOIDmode. Here we need
7503 to get a mode from something else.
7505 In some cases, there is a fourth mode, the operand's
7506 containing mode. If the insn specifies a containing mode for
7507 this operand, it overrides all others.
7509 I am not sure whether the algorithm here is always right,
7510 but it does the right things in those cases. */
7512 mode = GET_MODE (old);
7513 if (mode == VOIDmode)
7516 /* We cannot use gen_lowpart_common since it can do the wrong thing
7517 when REG_RTX has a multi-word mode. Note that REG_RTX must
7518 always be a REG here. */
7519 if (GET_MODE (reg_rtx) != mode)
7520 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7522 reload_reg_rtx_for_input[j] = reg_rtx;
7525 /* AUTO_INC reloads need to be handled even if inherited. We got an
7526 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7527 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7528 && ! rtx_equal_p (reg_rtx, old)
7530 emit_input_reload_insns (chain, rld + j, old, j);
7532 /* When inheriting a wider reload, we have a MEM in rl->in,
7533 e.g. inheriting a SImode output reload for
7534 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7535 if (optimize && reload_inherited[j] && rl->in
7537 && MEM_P (rl->in_reg)
7538 && reload_spill_index[j] >= 0
7539 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7540 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7542 /* If we are reloading a register that was recently stored in with an
7543 output-reload, see if we can prove there was
7544 actually no need to store the old value in it. */
7547 && (reload_inherited[j] || reload_override_in[j])
7550 && spill_reg_store[REGNO (reg_rtx)] != 0
7552 /* There doesn't seem to be any reason to restrict this to pseudos
7553 and doing so loses in the case where we are copying from a
7554 register of the wrong class. */
7555 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7557 /* The insn might have already some references to stackslots
7558 replaced by MEMs, while reload_out_reg still names the
7560 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7561 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7562 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7565 /* Do output reloading for reload RL, which is for the insn described by
7566 CHAIN and has the number J.
7567 ??? At some point we need to support handling output reloads of
7568 JUMP_INSNs or insns that set cc0. */
7570 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7573 rtx insn = chain->insn;
7574 /* If this is an output reload that stores something that is
7575 not loaded in this same reload, see if we can eliminate a previous
7577 rtx pseudo = rl->out_reg;
7578 rtx reg_rtx = rl->reg_rtx;
7580 if (rl->out && reg_rtx)
7582 enum machine_mode mode;
7584 /* Determine the mode to reload in.
7585 See comments above (for input reloading). */
7586 mode = GET_MODE (rl->out);
7587 if (mode == VOIDmode)
7589 /* VOIDmode should never happen for an output. */
7590 if (asm_noperands (PATTERN (insn)) < 0)
7591 /* It's the compiler's fault. */
7592 fatal_insn ("VOIDmode on an output", insn);
7593 error_for_asm (insn, "output operand is constant in %<asm%>");
7594 /* Prevent crash--use something we know is valid. */
7596 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7598 if (GET_MODE (reg_rtx) != mode)
7599 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7601 reload_reg_rtx_for_output[j] = reg_rtx;
7606 && ! rtx_equal_p (rl->in_reg, pseudo)
7607 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7608 && reg_last_reload_reg[REGNO (pseudo)])
7610 int pseudo_no = REGNO (pseudo);
7611 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7613 /* We don't need to test full validity of last_regno for
7614 inherit here; we only want to know if the store actually
7615 matches the pseudo. */
7616 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7617 && reg_reloaded_contents[last_regno] == pseudo_no
7618 && spill_reg_store[last_regno]
7619 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7620 delete_output_reload (insn, j, last_regno, reg_rtx);
7626 || rtx_equal_p (old, reg_rtx))
7629 /* An output operand that dies right away does need a reload,
7630 but need not be copied from it. Show the new location in the
7632 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7633 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7635 XEXP (note, 0) = reg_rtx;
7638 /* Likewise for a SUBREG of an operand that dies. */
7639 else if (GET_CODE (old) == SUBREG
7640 && REG_P (SUBREG_REG (old))
7641 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7644 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7647 else if (GET_CODE (old) == SCRATCH)
7648 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7649 but we don't want to make an output reload. */
7652 /* If is a JUMP_INSN, we can't support output reloads yet. */
7653 gcc_assert (NONJUMP_INSN_P (insn));
7655 emit_output_reload_insns (chain, rld + j, j);
7658 /* A reload copies values of MODE from register SRC to register DEST.
7659 Return true if it can be treated for inheritance purposes like a
7660 group of reloads, each one reloading a single hard register. The
7661 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7662 occupy the same number of hard registers. */
7665 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7666 int src ATTRIBUTE_UNUSED,
7667 enum machine_mode mode ATTRIBUTE_UNUSED)
7669 #ifdef CANNOT_CHANGE_MODE_CLASS
7670 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7671 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7677 /* Output insns to reload values in and out of the chosen reload regs. */
7680 emit_reload_insns (struct insn_chain *chain)
7682 rtx insn = chain->insn;
7686 CLEAR_HARD_REG_SET (reg_reloaded_died);
7688 for (j = 0; j < reload_n_operands; j++)
7689 input_reload_insns[j] = input_address_reload_insns[j]
7690 = inpaddr_address_reload_insns[j]
7691 = output_reload_insns[j] = output_address_reload_insns[j]
7692 = outaddr_address_reload_insns[j]
7693 = other_output_reload_insns[j] = 0;
7694 other_input_address_reload_insns = 0;
7695 other_input_reload_insns = 0;
7696 operand_reload_insns = 0;
7697 other_operand_reload_insns = 0;
7699 /* Dump reloads into the dump file. */
7702 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7703 debug_reload_to_stream (dump_file);
7706 /* Now output the instructions to copy the data into and out of the
7707 reload registers. Do these in the order that the reloads were reported,
7708 since reloads of base and index registers precede reloads of operands
7709 and the operands may need the base and index registers reloaded. */
7711 for (j = 0; j < n_reloads; j++)
7713 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7717 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7718 new_spill_reg_store[i] = 0;
7721 do_input_reload (chain, rld + j, j);
7722 do_output_reload (chain, rld + j, j);
7725 /* Now write all the insns we made for reloads in the order expected by
7726 the allocation functions. Prior to the insn being reloaded, we write
7727 the following reloads:
7729 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7731 RELOAD_OTHER reloads.
7733 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7734 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7735 RELOAD_FOR_INPUT reload for the operand.
7737 RELOAD_FOR_OPADDR_ADDRS reloads.
7739 RELOAD_FOR_OPERAND_ADDRESS reloads.
7741 After the insn being reloaded, we write the following:
7743 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7744 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7745 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7746 reloads for the operand. The RELOAD_OTHER output reloads are
7747 output in descending order by reload number. */
7749 emit_insn_before (other_input_address_reload_insns, insn);
7750 emit_insn_before (other_input_reload_insns, insn);
7752 for (j = 0; j < reload_n_operands; j++)
7754 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7755 emit_insn_before (input_address_reload_insns[j], insn);
7756 emit_insn_before (input_reload_insns[j], insn);
7759 emit_insn_before (other_operand_reload_insns, insn);
7760 emit_insn_before (operand_reload_insns, insn);
7762 for (j = 0; j < reload_n_operands; j++)
7764 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7765 x = emit_insn_after (output_address_reload_insns[j], x);
7766 x = emit_insn_after (output_reload_insns[j], x);
7767 emit_insn_after (other_output_reload_insns[j], x);
7770 /* For all the spill regs newly reloaded in this instruction,
7771 record what they were reloaded from, so subsequent instructions
7772 can inherit the reloads.
7774 Update spill_reg_store for the reloads of this insn.
7775 Copy the elements that were updated in the loop above. */
7777 for (j = 0; j < n_reloads; j++)
7779 int r = reload_order[j];
7780 int i = reload_spill_index[r];
7782 /* If this is a non-inherited input reload from a pseudo, we must
7783 clear any memory of a previous store to the same pseudo. Only do
7784 something if there will not be an output reload for the pseudo
7786 if (rld[r].in_reg != 0
7787 && ! (reload_inherited[r] || reload_override_in[r]))
7789 rtx reg = rld[r].in_reg;
7791 if (GET_CODE (reg) == SUBREG)
7792 reg = SUBREG_REG (reg);
7795 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7796 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7798 int nregno = REGNO (reg);
7800 if (reg_last_reload_reg[nregno])
7802 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7804 if (reg_reloaded_contents[last_regno] == nregno)
7805 spill_reg_store[last_regno] = 0;
7810 /* I is nonneg if this reload used a register.
7811 If rld[r].reg_rtx is 0, this is an optional reload
7812 that we opted to ignore. */
7814 if (i >= 0 && rld[r].reg_rtx != 0)
7816 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7819 /* For a multi register reload, we need to check if all or part
7820 of the value lives to the end. */
7821 for (k = 0; k < nr; k++)
7822 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7823 rld[r].when_needed))
7824 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7826 /* Maybe the spill reg contains a copy of reload_out. */
7828 && (REG_P (rld[r].out)
7832 || REG_P (rld[r].out_reg)))
7835 enum machine_mode mode;
7838 reg = reload_reg_rtx_for_output[r];
7839 mode = GET_MODE (reg);
7840 regno = REGNO (reg);
7841 nregs = hard_regno_nregs[regno][mode];
7842 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7843 rld[r].when_needed))
7845 rtx out = (REG_P (rld[r].out)
7849 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7850 int out_regno = REGNO (out);
7851 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7852 : hard_regno_nregs[out_regno][mode]);
7855 spill_reg_store[regno] = new_spill_reg_store[regno];
7856 spill_reg_stored_to[regno] = out;
7857 reg_last_reload_reg[out_regno] = reg;
7859 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7860 && nregs == out_nregs
7861 && inherit_piecemeal_p (out_regno, regno, mode));
7863 /* If OUT_REGNO is a hard register, it may occupy more than
7864 one register. If it does, say what is in the
7865 rest of the registers assuming that both registers
7866 agree on how many words the object takes. If not,
7867 invalidate the subsequent registers. */
7869 if (HARD_REGISTER_NUM_P (out_regno))
7870 for (k = 1; k < out_nregs; k++)
7871 reg_last_reload_reg[out_regno + k]
7872 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7874 /* Now do the inverse operation. */
7875 for (k = 0; k < nregs; k++)
7877 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7878 reg_reloaded_contents[regno + k]
7879 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7882 reg_reloaded_insn[regno + k] = insn;
7883 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7884 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7885 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7888 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7893 /* Maybe the spill reg contains a copy of reload_in. Only do
7894 something if there will not be an output reload for
7895 the register being reloaded. */
7896 else if (rld[r].out_reg == 0
7898 && ((REG_P (rld[r].in)
7899 && !HARD_REGISTER_P (rld[r].in)
7900 && !REGNO_REG_SET_P (®_has_output_reload,
7902 || (REG_P (rld[r].in_reg)
7903 && !REGNO_REG_SET_P (®_has_output_reload,
7904 REGNO (rld[r].in_reg))))
7905 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7908 enum machine_mode mode;
7911 reg = reload_reg_rtx_for_input[r];
7912 mode = GET_MODE (reg);
7913 regno = REGNO (reg);
7914 nregs = hard_regno_nregs[regno][mode];
7915 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7916 rld[r].when_needed))
7923 if (REG_P (rld[r].in)
7924 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7926 else if (REG_P (rld[r].in_reg))
7929 in = XEXP (rld[r].in_reg, 0);
7930 in_regno = REGNO (in);
7932 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7933 : hard_regno_nregs[in_regno][mode]);
7935 reg_last_reload_reg[in_regno] = reg;
7937 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7938 && nregs == in_nregs
7939 && inherit_piecemeal_p (regno, in_regno, mode));
7941 if (HARD_REGISTER_NUM_P (in_regno))
7942 for (k = 1; k < in_nregs; k++)
7943 reg_last_reload_reg[in_regno + k]
7944 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7946 /* Unless we inherited this reload, show we haven't
7947 recently done a store.
7948 Previous stores of inherited auto_inc expressions
7949 also have to be discarded. */
7950 if (! reload_inherited[r]
7951 || (rld[r].out && ! rld[r].out_reg))
7952 spill_reg_store[regno] = 0;
7954 for (k = 0; k < nregs; k++)
7956 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7957 reg_reloaded_contents[regno + k]
7958 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7961 reg_reloaded_insn[regno + k] = insn;
7962 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7963 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7964 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7967 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7974 /* The following if-statement was #if 0'd in 1.34 (or before...).
7975 It's reenabled in 1.35 because supposedly nothing else
7976 deals with this problem. */
7978 /* If a register gets output-reloaded from a non-spill register,
7979 that invalidates any previous reloaded copy of it.
7980 But forget_old_reloads_1 won't get to see it, because
7981 it thinks only about the original insn. So invalidate it here.
7982 Also do the same thing for RELOAD_OTHER constraints where the
7983 output is discarded. */
7985 && ((rld[r].out != 0
7986 && (REG_P (rld[r].out)
7987 || (MEM_P (rld[r].out)
7988 && REG_P (rld[r].out_reg))))
7989 || (rld[r].out == 0 && rld[r].out_reg
7990 && REG_P (rld[r].out_reg))))
7992 rtx out = ((rld[r].out && REG_P (rld[r].out))
7993 ? rld[r].out : rld[r].out_reg);
7994 int out_regno = REGNO (out);
7995 enum machine_mode mode = GET_MODE (out);
7997 /* REG_RTX is now set or clobbered by the main instruction.
7998 As the comment above explains, forget_old_reloads_1 only
7999 sees the original instruction, and there is no guarantee
8000 that the original instruction also clobbered REG_RTX.
8001 For example, if find_reloads sees that the input side of
8002 a matched operand pair dies in this instruction, it may
8003 use the input register as the reload register.
8005 Calling forget_old_reloads_1 is a waste of effort if
8006 REG_RTX is also the output register.
8008 If we know that REG_RTX holds the value of a pseudo
8009 register, the code after the call will record that fact. */
8010 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8011 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8013 if (!HARD_REGISTER_NUM_P (out_regno))
8015 rtx src_reg, store_insn = NULL_RTX;
8017 reg_last_reload_reg[out_regno] = 0;
8019 /* If we can find a hard register that is stored, record
8020 the storing insn so that we may delete this insn with
8021 delete_output_reload. */
8022 src_reg = reload_reg_rtx_for_output[r];
8024 /* If this is an optional reload, try to find the source reg
8025 from an input reload. */
8028 rtx set = single_set (insn);
8029 if (set && SET_DEST (set) == rld[r].out)
8033 src_reg = SET_SRC (set);
8035 for (k = 0; k < n_reloads; k++)
8037 if (rld[k].in == src_reg)
8039 src_reg = reload_reg_rtx_for_input[k];
8046 store_insn = new_spill_reg_store[REGNO (src_reg)];
8047 if (src_reg && REG_P (src_reg)
8048 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8050 int src_regno, src_nregs, k;
8053 gcc_assert (GET_MODE (src_reg) == mode);
8054 src_regno = REGNO (src_reg);
8055 src_nregs = hard_regno_nregs[src_regno][mode];
8056 /* The place where to find a death note varies with
8057 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8058 necessarily checked exactly in the code that moves
8059 notes, so just check both locations. */
8060 note = find_regno_note (insn, REG_DEAD, src_regno);
8061 if (! note && store_insn)
8062 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8063 for (k = 0; k < src_nregs; k++)
8065 spill_reg_store[src_regno + k] = store_insn;
8066 spill_reg_stored_to[src_regno + k] = out;
8067 reg_reloaded_contents[src_regno + k] = out_regno;
8068 reg_reloaded_insn[src_regno + k] = store_insn;
8069 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8070 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8071 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8073 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8076 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8078 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8080 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8082 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8084 reg_last_reload_reg[out_regno] = src_reg;
8085 /* We have to set reg_has_output_reload here, or else
8086 forget_old_reloads_1 will clear reg_last_reload_reg
8088 SET_REGNO_REG_SET (®_has_output_reload,
8094 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8096 for (k = 0; k < out_nregs; k++)
8097 reg_last_reload_reg[out_regno + k] = 0;
8101 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8104 /* Go through the motions to emit INSN and test if it is strictly valid.
8105 Return the emitted insn if valid, else return NULL. */
8108 emit_insn_if_valid_for_reload (rtx insn)
8110 rtx last = get_last_insn ();
8113 insn = emit_insn (insn);
8114 code = recog_memoized (insn);
8118 extract_insn (insn);
8119 /* We want constrain operands to treat this insn strictly in its
8120 validity determination, i.e., the way it would after reload has
8122 if (constrain_operands (1))
8126 delete_insns_since (last);
8130 /* Emit code to perform a reload from IN (which may be a reload register) to
8131 OUT (which may also be a reload register). IN or OUT is from operand
8132 OPNUM with reload type TYPE.
8134 Returns first insn emitted. */
8137 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8139 rtx last = get_last_insn ();
8142 /* If IN is a paradoxical SUBREG, remove it and try to put the
8143 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8144 if (GET_CODE (in) == SUBREG
8145 && (GET_MODE_SIZE (GET_MODE (in))
8146 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8147 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8148 in = SUBREG_REG (in), out = tem;
8149 else if (GET_CODE (out) == SUBREG
8150 && (GET_MODE_SIZE (GET_MODE (out))
8151 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8152 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8153 out = SUBREG_REG (out), in = tem;
8155 /* How to do this reload can get quite tricky. Normally, we are being
8156 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8157 register that didn't get a hard register. In that case we can just
8158 call emit_move_insn.
8160 We can also be asked to reload a PLUS that adds a register or a MEM to
8161 another register, constant or MEM. This can occur during frame pointer
8162 elimination and while reloading addresses. This case is handled by
8163 trying to emit a single insn to perform the add. If it is not valid,
8164 we use a two insn sequence.
8166 Or we can be asked to reload an unary operand that was a fragment of
8167 an addressing mode, into a register. If it isn't recognized as-is,
8168 we try making the unop operand and the reload-register the same:
8169 (set reg:X (unop:X expr:Y))
8170 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8172 Finally, we could be called to handle an 'o' constraint by putting
8173 an address into a register. In that case, we first try to do this
8174 with a named pattern of "reload_load_address". If no such pattern
8175 exists, we just emit a SET insn and hope for the best (it will normally
8176 be valid on machines that use 'o').
8178 This entire process is made complex because reload will never
8179 process the insns we generate here and so we must ensure that
8180 they will fit their constraints and also by the fact that parts of
8181 IN might be being reloaded separately and replaced with spill registers.
8182 Because of this, we are, in some sense, just guessing the right approach
8183 here. The one listed above seems to work.
8185 ??? At some point, this whole thing needs to be rethought. */
8187 if (GET_CODE (in) == PLUS
8188 && (REG_P (XEXP (in, 0))
8189 || GET_CODE (XEXP (in, 0)) == SUBREG
8190 || MEM_P (XEXP (in, 0)))
8191 && (REG_P (XEXP (in, 1))
8192 || GET_CODE (XEXP (in, 1)) == SUBREG
8193 || CONSTANT_P (XEXP (in, 1))
8194 || MEM_P (XEXP (in, 1))))
8196 /* We need to compute the sum of a register or a MEM and another
8197 register, constant, or MEM, and put it into the reload
8198 register. The best possible way of doing this is if the machine
8199 has a three-operand ADD insn that accepts the required operands.
8201 The simplest approach is to try to generate such an insn and see if it
8202 is recognized and matches its constraints. If so, it can be used.
8204 It might be better not to actually emit the insn unless it is valid,
8205 but we need to pass the insn as an operand to `recog' and
8206 `extract_insn' and it is simpler to emit and then delete the insn if
8207 not valid than to dummy things up. */
8209 rtx op0, op1, tem, insn;
8212 op0 = find_replacement (&XEXP (in, 0));
8213 op1 = find_replacement (&XEXP (in, 1));
8215 /* Since constraint checking is strict, commutativity won't be
8216 checked, so we need to do that here to avoid spurious failure
8217 if the add instruction is two-address and the second operand
8218 of the add is the same as the reload reg, which is frequently
8219 the case. If the insn would be A = B + A, rearrange it so
8220 it will be A = A + B as constrain_operands expects. */
8222 if (REG_P (XEXP (in, 1))
8223 && REGNO (out) == REGNO (XEXP (in, 1)))
8224 tem = op0, op0 = op1, op1 = tem;
8226 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8227 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8229 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8233 /* If that failed, we must use a conservative two-insn sequence.
8235 Use a move to copy one operand into the reload register. Prefer
8236 to reload a constant, MEM or pseudo since the move patterns can
8237 handle an arbitrary operand. If OP1 is not a constant, MEM or
8238 pseudo and OP1 is not a valid operand for an add instruction, then
8241 After reloading one of the operands into the reload register, add
8242 the reload register to the output register.
8244 If there is another way to do this for a specific machine, a
8245 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8248 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8250 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8252 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8253 || (code != CODE_FOR_nothing
8254 && ! ((*insn_data[code].operand[2].predicate)
8255 (op1, insn_data[code].operand[2].mode))))
8256 tem = op0, op0 = op1, op1 = tem;
8258 gen_reload (out, op0, opnum, type);
8260 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8261 This fixes a problem on the 32K where the stack pointer cannot
8262 be used as an operand of an add insn. */
8264 if (rtx_equal_p (op0, op1))
8267 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8270 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8271 set_unique_reg_note (insn, REG_EQUIV, in);
8275 /* If that failed, copy the address register to the reload register.
8276 Then add the constant to the reload register. */
8278 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8279 gen_reload (out, op1, opnum, type);
8280 insn = emit_insn (gen_add2_insn (out, op0));
8281 set_unique_reg_note (insn, REG_EQUIV, in);
8284 #ifdef SECONDARY_MEMORY_NEEDED
8285 /* If we need a memory location to do the move, do it that way. */
8286 else if ((REG_P (in)
8287 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8288 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8290 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8291 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8292 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8293 REGNO_REG_CLASS (reg_or_subregno (out)),
8296 /* Get the memory to use and rewrite both registers to its mode. */
8297 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8299 if (GET_MODE (loc) != GET_MODE (out))
8300 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8302 if (GET_MODE (loc) != GET_MODE (in))
8303 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8305 gen_reload (loc, in, opnum, type);
8306 gen_reload (out, loc, opnum, type);
8309 else if (REG_P (out) && UNARY_P (in))
8316 op1 = find_replacement (&XEXP (in, 0));
8317 if (op1 != XEXP (in, 0))
8318 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8320 /* First, try a plain SET. */
8321 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8325 /* If that failed, move the inner operand to the reload
8326 register, and try the same unop with the inner expression
8327 replaced with the reload register. */
8329 if (GET_MODE (op1) != GET_MODE (out))
8330 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8334 gen_reload (out_moded, op1, opnum, type);
8337 = gen_rtx_SET (VOIDmode, out,
8338 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8340 insn = emit_insn_if_valid_for_reload (insn);
8343 set_unique_reg_note (insn, REG_EQUIV, in);
8347 fatal_insn ("Failure trying to reload:", set);
8349 /* If IN is a simple operand, use gen_move_insn. */
8350 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8352 tem = emit_insn (gen_move_insn (out, in));
8353 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8354 mark_jump_label (in, tem, 0);
8357 #ifdef HAVE_reload_load_address
8358 else if (HAVE_reload_load_address)
8359 emit_insn (gen_reload_load_address (out, in));
8362 /* Otherwise, just write (set OUT IN) and hope for the best. */
8364 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8366 /* Return the first insn emitted.
8367 We can not just return get_last_insn, because there may have
8368 been multiple instructions emitted. Also note that gen_move_insn may
8369 emit more than one insn itself, so we can not assume that there is one
8370 insn emitted per emit_insn_before call. */
8372 return last ? NEXT_INSN (last) : get_insns ();
8375 /* Delete a previously made output-reload whose result we now believe
8376 is not needed. First we double-check.
8378 INSN is the insn now being processed.
8379 LAST_RELOAD_REG is the hard register number for which we want to delete
8380 the last output reload.
8381 J is the reload-number that originally used REG. The caller has made
8382 certain that reload J doesn't use REG any longer for input.
8383 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8386 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8388 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8389 rtx reg = spill_reg_stored_to[last_reload_reg];
8392 int n_inherited = 0;
8396 /* It is possible that this reload has been only used to set another reload
8397 we eliminated earlier and thus deleted this instruction too. */
8398 if (INSN_DELETED_P (output_reload_insn))
8401 /* Get the raw pseudo-register referred to. */
8403 while (GET_CODE (reg) == SUBREG)
8404 reg = SUBREG_REG (reg);
8405 substed = reg_equiv_memory_loc[REGNO (reg)];
8407 /* This is unsafe if the operand occurs more often in the current
8408 insn than it is inherited. */
8409 for (k = n_reloads - 1; k >= 0; k--)
8411 rtx reg2 = rld[k].in;
8414 if (MEM_P (reg2) || reload_override_in[k])
8415 reg2 = rld[k].in_reg;
8417 if (rld[k].out && ! rld[k].out_reg)
8418 reg2 = XEXP (rld[k].in_reg, 0);
8420 while (GET_CODE (reg2) == SUBREG)
8421 reg2 = SUBREG_REG (reg2);
8422 if (rtx_equal_p (reg2, reg))
8424 if (reload_inherited[k] || reload_override_in[k] || k == j)
8430 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8431 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8432 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8435 n_occurrences += count_occurrences (PATTERN (insn),
8436 eliminate_regs (substed, 0,
8438 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8440 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8441 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8443 if (n_occurrences > n_inherited)
8446 /* If the pseudo-reg we are reloading is no longer referenced
8447 anywhere between the store into it and here,
8448 and we're within the same basic block, then the value can only
8449 pass through the reload reg and end up here.
8450 Otherwise, give up--return. */
8451 for (i1 = NEXT_INSN (output_reload_insn);
8452 i1 != insn; i1 = NEXT_INSN (i1))
8454 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8456 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8457 && reg_mentioned_p (reg, PATTERN (i1)))
8459 /* If this is USE in front of INSN, we only have to check that
8460 there are no more references than accounted for by inheritance. */
8461 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8463 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8464 i1 = NEXT_INSN (i1);
8466 if (n_occurrences <= n_inherited && i1 == insn)
8472 /* We will be deleting the insn. Remove the spill reg information. */
8473 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8475 spill_reg_store[last_reload_reg + k] = 0;
8476 spill_reg_stored_to[last_reload_reg + k] = 0;
8479 /* The caller has already checked that REG dies or is set in INSN.
8480 It has also checked that we are optimizing, and thus some
8481 inaccuracies in the debugging information are acceptable.
8482 So we could just delete output_reload_insn. But in some cases
8483 we can improve the debugging information without sacrificing
8484 optimization - maybe even improving the code: See if the pseudo
8485 reg has been completely replaced with reload regs. If so, delete
8486 the store insn and forget we had a stack slot for the pseudo. */
8487 if (rld[j].out != rld[j].in
8488 && REG_N_DEATHS (REGNO (reg)) == 1
8489 && REG_N_SETS (REGNO (reg)) == 1
8490 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8491 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8495 /* We know that it was used only between here and the beginning of
8496 the current basic block. (We also know that the last use before
8497 INSN was the output reload we are thinking of deleting, but never
8498 mind that.) Search that range; see if any ref remains. */
8499 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8501 rtx set = single_set (i2);
8503 /* Uses which just store in the pseudo don't count,
8504 since if they are the only uses, they are dead. */
8505 if (set != 0 && SET_DEST (set) == reg)
8510 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8511 && reg_mentioned_p (reg, PATTERN (i2)))
8513 /* Some other ref remains; just delete the output reload we
8515 delete_address_reloads (output_reload_insn, insn);
8516 delete_insn (output_reload_insn);
8521 /* Delete the now-dead stores into this pseudo. Note that this
8522 loop also takes care of deleting output_reload_insn. */
8523 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8525 rtx set = single_set (i2);
8527 if (set != 0 && SET_DEST (set) == reg)
8529 delete_address_reloads (i2, insn);
8537 /* For the debugging info, say the pseudo lives in this reload reg. */
8538 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8539 if (flag_ira && optimize)
8540 /* Inform IRA about the change. */
8541 ira_mark_allocation_change (REGNO (reg));
8542 alter_reg (REGNO (reg), -1, false);
8546 delete_address_reloads (output_reload_insn, insn);
8547 delete_insn (output_reload_insn);
8551 /* We are going to delete DEAD_INSN. Recursively delete loads of
8552 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8553 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8555 delete_address_reloads (rtx dead_insn, rtx current_insn)
8557 rtx set = single_set (dead_insn);
8558 rtx set2, dst, prev, next;
8561 rtx dst = SET_DEST (set);
8563 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8565 /* If we deleted the store from a reloaded post_{in,de}c expression,
8566 we can delete the matching adds. */
8567 prev = PREV_INSN (dead_insn);
8568 next = NEXT_INSN (dead_insn);
8569 if (! prev || ! next)
8571 set = single_set (next);
8572 set2 = single_set (prev);
8574 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8575 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8576 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8578 dst = SET_DEST (set);
8579 if (! rtx_equal_p (dst, SET_DEST (set2))
8580 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8581 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8582 || (INTVAL (XEXP (SET_SRC (set), 1))
8583 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8585 delete_related_insns (prev);
8586 delete_related_insns (next);
8589 /* Subfunction of delete_address_reloads: process registers found in X. */
8591 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8593 rtx prev, set, dst, i2;
8595 enum rtx_code code = GET_CODE (x);
8599 const char *fmt = GET_RTX_FORMAT (code);
8600 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8603 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8604 else if (fmt[i] == 'E')
8606 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8607 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8614 if (spill_reg_order[REGNO (x)] < 0)
8617 /* Scan backwards for the insn that sets x. This might be a way back due
8619 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8621 code = GET_CODE (prev);
8622 if (code == CODE_LABEL || code == JUMP_INSN)
8626 if (reg_set_p (x, PATTERN (prev)))
8628 if (reg_referenced_p (x, PATTERN (prev)))
8631 if (! prev || INSN_UID (prev) < reload_first_uid)
8633 /* Check that PREV only sets the reload register. */
8634 set = single_set (prev);
8637 dst = SET_DEST (set);
8639 || ! rtx_equal_p (dst, x))
8641 if (! reg_set_p (dst, PATTERN (dead_insn)))
8643 /* Check if DST was used in a later insn -
8644 it might have been inherited. */
8645 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8651 if (reg_referenced_p (dst, PATTERN (i2)))
8653 /* If there is a reference to the register in the current insn,
8654 it might be loaded in a non-inherited reload. If no other
8655 reload uses it, that means the register is set before
8657 if (i2 == current_insn)
8659 for (j = n_reloads - 1; j >= 0; j--)
8660 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8661 || reload_override_in[j] == dst)
8663 for (j = n_reloads - 1; j >= 0; j--)
8664 if (rld[j].in && rld[j].reg_rtx == dst)
8673 /* If DST is still live at CURRENT_INSN, check if it is used for
8674 any reload. Note that even if CURRENT_INSN sets DST, we still
8675 have to check the reloads. */
8676 if (i2 == current_insn)
8678 for (j = n_reloads - 1; j >= 0; j--)
8679 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8680 || reload_override_in[j] == dst)
8682 /* ??? We can't finish the loop here, because dst might be
8683 allocated to a pseudo in this block if no reload in this
8684 block needs any of the classes containing DST - see
8685 spill_hard_reg. There is no easy way to tell this, so we
8686 have to scan till the end of the basic block. */
8688 if (reg_set_p (dst, PATTERN (i2)))
8692 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8693 reg_reloaded_contents[REGNO (dst)] = -1;
8697 /* Output reload-insns to reload VALUE into RELOADREG.
8698 VALUE is an autoincrement or autodecrement RTX whose operand
8699 is a register or memory location;
8700 so reloading involves incrementing that location.
8701 IN is either identical to VALUE, or some cheaper place to reload from.
8703 INC_AMOUNT is the number to increment or decrement by (always positive).
8704 This cannot be deduced from VALUE.
8706 Return the instruction that stores into RELOADREG. */
8709 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8711 /* REG or MEM to be copied and incremented. */
8712 rtx incloc = find_replacement (&XEXP (value, 0));
8713 /* Nonzero if increment after copying. */
8714 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8715 || GET_CODE (value) == POST_MODIFY);
8721 rtx real_in = in == value ? incloc : in;
8723 /* No hard register is equivalent to this register after
8724 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8725 we could inc/dec that register as well (maybe even using it for
8726 the source), but I'm not sure it's worth worrying about. */
8728 reg_last_reload_reg[REGNO (incloc)] = 0;
8730 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8732 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8733 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8737 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8738 inc_amount = -inc_amount;
8740 inc = GEN_INT (inc_amount);
8743 /* If this is post-increment, first copy the location to the reload reg. */
8744 if (post && real_in != reloadreg)
8745 emit_insn (gen_move_insn (reloadreg, real_in));
8749 /* See if we can directly increment INCLOC. Use a method similar to
8750 that in gen_reload. */
8752 last = get_last_insn ();
8753 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8754 gen_rtx_PLUS (GET_MODE (incloc),
8757 code = recog_memoized (add_insn);
8760 extract_insn (add_insn);
8761 if (constrain_operands (1))
8763 /* If this is a pre-increment and we have incremented the value
8764 where it lives, copy the incremented value to RELOADREG to
8765 be used as an address. */
8768 emit_insn (gen_move_insn (reloadreg, incloc));
8773 delete_insns_since (last);
8776 /* If couldn't do the increment directly, must increment in RELOADREG.
8777 The way we do this depends on whether this is pre- or post-increment.
8778 For pre-increment, copy INCLOC to the reload register, increment it
8779 there, then save back. */
8783 if (in != reloadreg)
8784 emit_insn (gen_move_insn (reloadreg, real_in));
8785 emit_insn (gen_add2_insn (reloadreg, inc));
8786 store = emit_insn (gen_move_insn (incloc, reloadreg));
8791 Because this might be a jump insn or a compare, and because RELOADREG
8792 may not be available after the insn in an input reload, we must do
8793 the incrementation before the insn being reloaded for.
8795 We have already copied IN to RELOADREG. Increment the copy in
8796 RELOADREG, save that back, then decrement RELOADREG so it has
8797 the original value. */
8799 emit_insn (gen_add2_insn (reloadreg, inc));
8800 store = emit_insn (gen_move_insn (incloc, reloadreg));
8801 if (GET_CODE (inc) == CONST_INT)
8802 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8804 emit_insn (gen_sub2_insn (reloadreg, inc));
8812 add_auto_inc_notes (rtx insn, rtx x)
8814 enum rtx_code code = GET_CODE (x);
8818 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8820 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8824 /* Scan all the operand sub-expressions. */
8825 fmt = GET_RTX_FORMAT (code);
8826 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8829 add_auto_inc_notes (insn, XEXP (x, i));
8830 else if (fmt[i] == 'E')
8831 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8832 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8837 /* Copy EH notes from an insn to its reloads. */
8839 copy_eh_notes (rtx insn, rtx x)
8841 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8844 for (; x != 0; x = NEXT_INSN (x))
8846 if (may_trap_p (PATTERN (x)))
8847 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8852 /* This is used by reload pass, that does emit some instructions after
8853 abnormal calls moving basic block end, but in fact it wants to emit
8854 them on the edge. Looks for abnormal call edges, find backward the
8855 proper call and fix the damage.
8857 Similar handle instructions throwing exceptions internally. */
8859 fixup_abnormal_edges (void)
8861 bool inserted = false;
8869 /* Look for cases we are interested in - calls or instructions causing
8871 FOR_EACH_EDGE (e, ei, bb->succs)
8873 if (e->flags & EDGE_ABNORMAL_CALL)
8875 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8876 == (EDGE_ABNORMAL | EDGE_EH))
8879 if (e && !CALL_P (BB_END (bb))
8880 && !can_throw_internal (BB_END (bb)))
8884 /* Get past the new insns generated. Allow notes, as the insns
8885 may be already deleted. */
8887 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8888 && !can_throw_internal (insn)
8889 && insn != BB_HEAD (bb))
8890 insn = PREV_INSN (insn);
8892 if (CALL_P (insn) || can_throw_internal (insn))
8896 stop = NEXT_INSN (BB_END (bb));
8898 insn = NEXT_INSN (insn);
8900 FOR_EACH_EDGE (e, ei, bb->succs)
8901 if (e->flags & EDGE_FALLTHRU)
8904 while (insn && insn != stop)
8906 next = NEXT_INSN (insn);
8911 /* Sometimes there's still the return value USE.
8912 If it's placed after a trapping call (i.e. that
8913 call is the last insn anyway), we have no fallthru
8914 edge. Simply delete this use and don't try to insert
8915 on the non-existent edge. */
8916 if (GET_CODE (PATTERN (insn)) != USE)
8918 /* We're not deleting it, we're moving it. */
8919 INSN_DELETED_P (insn) = 0;
8920 PREV_INSN (insn) = NULL_RTX;
8921 NEXT_INSN (insn) = NULL_RTX;
8923 insert_insn_on_edge (insn, e);
8927 else if (!BARRIER_P (insn))
8928 set_block_for_insn (insn, NULL);
8933 /* It may be that we don't find any such trapping insn. In this
8934 case we discovered quite late that the insn that had been
8935 marked as can_throw_internal in fact couldn't trap at all.
8936 So we should in fact delete the EH edges out of the block. */
8938 purge_dead_edges (bb);
8942 /* We've possibly turned single trapping insn into multiple ones. */
8943 if (flag_non_call_exceptions)
8946 blocks = sbitmap_alloc (last_basic_block);
8947 sbitmap_ones (blocks);
8948 find_many_sub_basic_blocks (blocks);
8949 sbitmap_free (blocks);
8953 commit_edge_insertions ();
8955 #ifdef ENABLE_CHECKING
8956 /* Verify that we didn't turn one trapping insn into many, and that
8957 we found and corrected all of the problems wrt fixups on the
8959 verify_flow_info ();
OSDN Git Service
