1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static rtx gen_mode_int PARAMS ((enum machine_mode,
457 static void failed_reload PARAMS ((rtx, int));
458 static int set_reload_reg PARAMS ((int, int));
459 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
460 static void reload_cse_simplify PARAMS ((rtx));
461 extern void dump_needs PARAMS ((struct insn_chain *));
463 /* Initialize the reload pass once per compilation. */
470 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
471 Set spill_indirect_levels to the number of levels such addressing is
472 permitted, zero if it is not permitted at all. */
475 = gen_rtx_MEM (Pmode,
478 LAST_VIRTUAL_REGISTER + 1),
480 spill_indirect_levels = 0;
482 while (memory_address_p (QImode, tem))
484 spill_indirect_levels++;
485 tem = gen_rtx_MEM (Pmode, tem);
488 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
490 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
491 indirect_symref_ok = memory_address_p (QImode, tem);
493 /* See if reg+reg is a valid (and offsettable) address. */
495 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
497 tem = gen_rtx_PLUS (Pmode,
498 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
499 gen_rtx_REG (Pmode, i));
501 /* This way, we make sure that reg+reg is an offsettable address. */
502 tem = plus_constant (tem, 4);
504 if (memory_address_p (QImode, tem))
506 double_reg_address_ok = 1;
511 /* Initialize obstack for our rtl allocation. */
512 gcc_obstack_init (&reload_obstack);
513 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
515 INIT_REG_SET (&spilled_pseudos);
516 INIT_REG_SET (&pseudos_counted);
519 /* List of insn chains that are currently unused. */
520 static struct insn_chain *unused_insn_chains = 0;
522 /* Allocate an empty insn_chain structure. */
526 struct insn_chain *c;
528 if (unused_insn_chains == 0)
530 c = (struct insn_chain *)
531 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
532 INIT_REG_SET (&c->live_throughout);
533 INIT_REG_SET (&c->dead_or_set);
537 c = unused_insn_chains;
538 unused_insn_chains = c->next;
540 c->is_caller_save_insn = 0;
541 c->need_operand_change = 0;
547 /* Small utility function to set all regs in hard reg set TO which are
548 allocated to pseudos in regset FROM. */
551 compute_use_by_pseudos (to, from)
557 EXECUTE_IF_SET_IN_REG_SET
558 (from, FIRST_PSEUDO_REGISTER, regno,
560 int r = reg_renumber[regno];
565 /* reload_combine uses the information from
566 BASIC_BLOCK->global_live_at_start, which might still
567 contain registers that have not actually been allocated
568 since they have an equivalence. */
569 if (! reload_completed)
574 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
576 SET_HARD_REG_BIT (*to, r + nregs);
581 /* Global variables used by reload and its subroutines. */
583 /* Set during calculate_needs if an insn needs register elimination. */
584 static int something_needs_elimination;
585 /* Set during calculate_needs if an insn needs an operand changed. */
586 int something_needs_operands_changed;
588 /* Nonzero means we couldn't get enough spill regs. */
591 /* Main entry point for the reload pass.
593 FIRST is the first insn of the function being compiled.
595 GLOBAL nonzero means we were called from global_alloc
596 and should attempt to reallocate any pseudoregs that we
597 displace from hard regs we will use for reloads.
598 If GLOBAL is zero, we do not have enough information to do that,
599 so any pseudo reg that is spilled must go to the stack.
601 Return value is nonzero if reload failed
602 and we must not do any more for this function. */
605 reload (first, global)
611 register struct elim_table *ep;
613 /* The two pointers used to track the true location of the memory used
614 for label offsets. */
615 char *real_known_ptr = NULL_PTR;
616 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
618 /* Make sure even insns with volatile mem refs are recognizable. */
623 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
625 /* Make sure that the last insn in the chain
626 is not something that needs reloading. */
627 emit_note (NULL_PTR, NOTE_INSN_DELETED);
629 /* Enable find_equiv_reg to distinguish insns made by reload. */
630 reload_first_uid = get_max_uid ();
632 #ifdef SECONDARY_MEMORY_NEEDED
633 /* Initialize the secondary memory table. */
634 clear_secondary_mem ();
637 /* We don't have a stack slot for any spill reg yet. */
638 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
639 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
641 /* Initialize the save area information for caller-save, in case some
645 /* Compute which hard registers are now in use
646 as homes for pseudo registers.
647 This is done here rather than (eg) in global_alloc
648 because this point is reached even if not optimizing. */
649 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
652 /* A function that receives a nonlocal goto must save all call-saved
654 if (current_function_has_nonlocal_label)
655 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
656 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
657 regs_ever_live[i] = 1;
659 /* Find all the pseudo registers that didn't get hard regs
660 but do have known equivalent constants or memory slots.
661 These include parameters (known equivalent to parameter slots)
662 and cse'd or loop-moved constant memory addresses.
664 Record constant equivalents in reg_equiv_constant
665 so they will be substituted by find_reloads.
666 Record memory equivalents in reg_mem_equiv so they can
667 be substituted eventually by altering the REG-rtx's. */
669 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
674 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
675 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
676 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
677 pseudo_forbidden_regs
678 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
680 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
682 CLEAR_HARD_REG_SET (bad_spill_regs_global);
684 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
685 Also find all paradoxical subregs and find largest such for each pseudo.
686 On machines with small register classes, record hard registers that
687 are used for user variables. These can never be used for spills.
688 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
689 caller-saved registers must be marked live. */
691 num_eliminable_invariants = 0;
692 for (insn = first; insn; insn = NEXT_INSN (insn))
694 rtx set = single_set (insn);
696 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
697 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
698 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
699 if (! call_used_regs[i])
700 regs_ever_live[i] = 1;
702 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
704 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
706 #ifdef LEGITIMATE_PIC_OPERAND_P
707 && (! function_invariant_p (XEXP (note, 0))
709 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
713 rtx x = XEXP (note, 0);
714 i = REGNO (SET_DEST (set));
715 if (i > LAST_VIRTUAL_REGISTER)
717 if (GET_CODE (x) == MEM)
719 /* If the operand is a PLUS, the MEM may be shared,
720 so make sure we have an unshared copy here. */
721 if (GET_CODE (XEXP (x, 0)) == PLUS)
724 reg_equiv_memory_loc[i] = x;
726 else if (function_invariant_p (x))
728 if (GET_CODE (x) == PLUS)
730 /* This is PLUS of frame pointer and a constant,
731 and might be shared. Unshare it. */
732 reg_equiv_constant[i] = copy_rtx (x);
733 num_eliminable_invariants++;
735 else if (x == frame_pointer_rtx
736 || x == arg_pointer_rtx)
738 reg_equiv_constant[i] = x;
739 num_eliminable_invariants++;
741 else if (LEGITIMATE_CONSTANT_P (x))
742 reg_equiv_constant[i] = x;
744 reg_equiv_memory_loc[i]
745 = force_const_mem (GET_MODE (SET_DEST (set)), x);
750 /* If this register is being made equivalent to a MEM
751 and the MEM is not SET_SRC, the equivalencing insn
752 is one with the MEM as a SET_DEST and it occurs later.
753 So don't mark this insn now. */
754 if (GET_CODE (x) != MEM
755 || rtx_equal_p (SET_SRC (set), x))
757 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
762 /* If this insn is setting a MEM from a register equivalent to it,
763 this is the equivalencing insn. */
764 else if (set && GET_CODE (SET_DEST (set)) == MEM
765 && GET_CODE (SET_SRC (set)) == REG
766 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
767 && rtx_equal_p (SET_DEST (set),
768 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
769 reg_equiv_init[REGNO (SET_SRC (set))]
770 = gen_rtx_INSN_LIST (VOIDmode, insn,
771 reg_equiv_init[REGNO (SET_SRC (set))]);
774 scan_paradoxical_subregs (PATTERN (insn));
779 num_labels = max_label_num () - get_first_label_num ();
781 /* Allocate the tables used to store offset information at labels. */
782 /* We used to use alloca here, but the size of what it would try to
783 allocate would occasionally cause it to exceed the stack limit and
784 cause a core dump. */
785 real_known_ptr = xmalloc (num_labels);
787 = (int (*)[NUM_ELIMINABLE_REGS])
788 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
790 offsets_known_at = real_known_ptr - get_first_label_num ();
792 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
794 /* Alter each pseudo-reg rtx to contain its hard reg number.
795 Assign stack slots to the pseudos that lack hard regs or equivalents.
796 Do not touch virtual registers. */
798 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
801 /* If we have some registers we think can be eliminated, scan all insns to
802 see if there is an insn that sets one of these registers to something
803 other than itself plus a constant. If so, the register cannot be
804 eliminated. Doing this scan here eliminates an extra pass through the
805 main reload loop in the most common case where register elimination
807 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
808 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
809 || GET_CODE (insn) == CALL_INSN)
810 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
812 maybe_fix_stack_asms ();
814 insns_need_reload = 0;
815 something_needs_elimination = 0;
817 /* Initialize to -1, which means take the first spill register. */
820 /* Spill any hard regs that we know we can't eliminate. */
821 CLEAR_HARD_REG_SET (used_spill_regs);
822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
823 if (! ep->can_eliminate)
824 spill_hard_reg (ep->from, 1);
826 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
827 if (frame_pointer_needed)
828 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
830 finish_spills (global);
832 /* From now on, we may need to generate moves differently. We may also
833 allow modifications of insns which cause them to not be recognized.
834 Any such modifications will be cleaned up during reload itself. */
835 reload_in_progress = 1;
837 /* This loop scans the entire function each go-round
838 and repeats until one repetition spills no additional hard regs. */
841 int something_changed;
844 HOST_WIDE_INT starting_frame_size;
846 /* Round size of stack frame to stack_alignment_needed. This must be done
847 here because the stack size may be a part of the offset computation
848 for register elimination, and there might have been new stack slots
849 created in the last iteration of this loop. */
850 if (cfun->stack_alignment_needed)
851 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
853 starting_frame_size = get_frame_size ();
855 set_initial_elim_offsets ();
856 set_initial_label_offsets ();
858 /* For each pseudo register that has an equivalent location defined,
859 try to eliminate any eliminable registers (such as the frame pointer)
860 assuming initial offsets for the replacement register, which
863 If the resulting location is directly addressable, substitute
864 the MEM we just got directly for the old REG.
866 If it is not addressable but is a constant or the sum of a hard reg
867 and constant, it is probably not addressable because the constant is
868 out of range, in that case record the address; we will generate
869 hairy code to compute the address in a register each time it is
870 needed. Similarly if it is a hard register, but one that is not
871 valid as an address register.
873 If the location is not addressable, but does not have one of the
874 above forms, assign a stack slot. We have to do this to avoid the
875 potential of producing lots of reloads if, e.g., a location involves
876 a pseudo that didn't get a hard register and has an equivalent memory
877 location that also involves a pseudo that didn't get a hard register.
879 Perhaps at some point we will improve reload_when_needed handling
880 so this problem goes away. But that's very hairy. */
882 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
883 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
885 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
887 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
889 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
890 else if (CONSTANT_P (XEXP (x, 0))
891 || (GET_CODE (XEXP (x, 0)) == REG
892 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
893 || (GET_CODE (XEXP (x, 0)) == PLUS
894 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
895 && (REGNO (XEXP (XEXP (x, 0), 0))
896 < FIRST_PSEUDO_REGISTER)
897 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
898 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc[i] = 0;
908 reg_equiv_init[i] = 0;
913 if (caller_save_needed)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (starting_frame_size != get_frame_size ())
920 if (caller_save_needed)
922 save_call_clobbered_regs ();
923 /* That might have allocated new insn_chain structures. */
924 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
927 calculate_needs_all_insns (global);
929 CLEAR_REG_SET (&spilled_pseudos);
932 something_changed = 0;
934 /* If we allocated any new memory locations, make another pass
935 since it might have changed elimination offsets. */
936 if (starting_frame_size != get_frame_size ())
937 something_changed = 1;
940 HARD_REG_SET to_spill;
941 CLEAR_HARD_REG_SET (to_spill);
942 update_eliminables (&to_spill);
943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
944 if (TEST_HARD_REG_BIT (to_spill, i))
946 spill_hard_reg (i, 1);
949 /* Regardless of the state of spills, if we previously had
950 a register that we thought we could eliminate, but no can
951 not eliminate, we must run another pass.
953 Consider pseudos which have an entry in reg_equiv_* which
954 reference an eliminable register. We must make another pass
955 to update reg_equiv_* so that we do not substitute in the
956 old value from when we thought the elimination could be
958 something_changed = 1;
962 select_reload_regs ();
966 if (insns_need_reload != 0 || did_spill)
967 something_changed |= finish_spills (global);
969 if (! something_changed)
972 if (caller_save_needed)
973 delete_caller_save_insns ();
975 obstack_free (&reload_obstack, reload_firstobj);
978 /* If global-alloc was run, notify it of any register eliminations we have
981 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
982 if (ep->can_eliminate)
983 mark_elimination (ep->from, ep->to);
985 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
986 If that insn didn't set the register (i.e., it copied the register to
987 memory), just delete that insn instead of the equivalencing insn plus
988 anything now dead. If we call delete_dead_insn on that insn, we may
989 delete the insn that actually sets the register if the register dies
990 there and that is incorrect. */
992 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
994 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
997 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
999 rtx equiv_insn = XEXP (list, 0);
1000 if (GET_CODE (equiv_insn) == NOTE)
1002 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1003 delete_dead_insn (equiv_insn);
1006 PUT_CODE (equiv_insn, NOTE);
1007 NOTE_SOURCE_FILE (equiv_insn) = 0;
1008 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1014 /* Use the reload registers where necessary
1015 by generating move instructions to move the must-be-register
1016 values into or out of the reload registers. */
1018 if (insns_need_reload != 0 || something_needs_elimination
1019 || something_needs_operands_changed)
1021 HOST_WIDE_INT old_frame_size = get_frame_size ();
1023 reload_as_needed (global);
1025 if (old_frame_size != get_frame_size ())
1029 verify_initial_elim_offsets ();
1032 /* If we were able to eliminate the frame pointer, show that it is no
1033 longer live at the start of any basic block. If it ls live by
1034 virtue of being in a pseudo, that pseudo will be marked live
1035 and hence the frame pointer will be known to be live via that
1038 if (! frame_pointer_needed)
1039 for (i = 0; i < n_basic_blocks; i++)
1040 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1041 HARD_FRAME_POINTER_REGNUM);
1043 /* Come here (with failure set nonzero) if we can't get enough spill regs
1044 and we decide not to abort about it. */
1047 CLEAR_REG_SET (&spilled_pseudos);
1048 reload_in_progress = 0;
1050 /* Now eliminate all pseudo regs by modifying them into
1051 their equivalent memory references.
1052 The REG-rtx's for the pseudos are modified in place,
1053 so all insns that used to refer to them now refer to memory.
1055 For a reg that has a reg_equiv_address, all those insns
1056 were changed by reloading so that no insns refer to it any longer;
1057 but the DECL_RTL of a variable decl may refer to it,
1058 and if so this causes the debugging info to mention the variable. */
1060 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1065 int is_readonly = 0;
1067 if (reg_equiv_memory_loc[i])
1069 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1070 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1071 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1074 if (reg_equiv_mem[i])
1075 addr = XEXP (reg_equiv_mem[i], 0);
1077 if (reg_equiv_address[i])
1078 addr = reg_equiv_address[i];
1082 if (reg_renumber[i] < 0)
1084 rtx reg = regno_reg_rtx[i];
1085 PUT_CODE (reg, MEM);
1086 XEXP (reg, 0) = addr;
1087 REG_USERVAR_P (reg) = 0;
1088 RTX_UNCHANGING_P (reg) = is_readonly;
1089 MEM_IN_STRUCT_P (reg) = in_struct;
1090 MEM_SCALAR_P (reg) = is_scalar;
1091 /* We have no alias information about this newly created
1093 MEM_ALIAS_SET (reg) = 0;
1095 else if (reg_equiv_mem[i])
1096 XEXP (reg_equiv_mem[i], 0) = addr;
1100 /* We must set reload_completed now since the cleanup_subreg_operands call
1101 below will re-recognize each insn and reload may have generated insns
1102 which are only valid during and after reload. */
1103 reload_completed = 1;
1105 /* Make a pass over all the insns and delete all USEs which we inserted
1106 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1107 notes. Delete all CLOBBER insns that don't refer to the return value
1108 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1109 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1110 and regenerate REG_INC notes that may have been moved around. */
1112 for (insn = first; insn; insn = NEXT_INSN (insn))
1117 if ((GET_CODE (PATTERN (insn)) == USE
1118 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1119 || (GET_CODE (PATTERN (insn)) == CLOBBER
1120 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1121 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1123 PUT_CODE (insn, NOTE);
1124 NOTE_SOURCE_FILE (insn) = 0;
1125 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1129 pnote = ®_NOTES (insn);
1132 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1133 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1134 || REG_NOTE_KIND (*pnote) == REG_INC
1135 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1136 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1137 *pnote = XEXP (*pnote, 1);
1139 pnote = &XEXP (*pnote, 1);
1143 add_auto_inc_notes (insn, PATTERN (insn));
1146 /* And simplify (subreg (reg)) if it appears as an operand. */
1147 cleanup_subreg_operands (insn);
1150 /* If we are doing stack checking, give a warning if this function's
1151 frame size is larger than we expect. */
1152 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1154 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1155 static int verbose_warned = 0;
1157 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1158 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1159 size += UNITS_PER_WORD;
1161 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1163 warning ("frame size too large for reliable stack checking");
1164 if (! verbose_warned)
1166 warning ("try reducing the number of local variables");
1172 /* Indicate that we no longer have known memory locations or constants. */
1173 if (reg_equiv_constant)
1174 free (reg_equiv_constant);
1175 reg_equiv_constant = 0;
1176 if (reg_equiv_memory_loc)
1177 free (reg_equiv_memory_loc);
1178 reg_equiv_memory_loc = 0;
1181 free (real_known_ptr);
1185 free (reg_equiv_mem);
1186 free (reg_equiv_init);
1187 free (reg_equiv_address);
1188 free (reg_max_ref_width);
1189 free (reg_old_renumber);
1190 free (pseudo_previous_regs);
1191 free (pseudo_forbidden_regs);
1193 CLEAR_HARD_REG_SET (used_spill_regs);
1194 for (i = 0; i < n_spills; i++)
1195 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1197 /* Free all the insn_chain structures at once. */
1198 obstack_free (&reload_obstack, reload_startobj);
1199 unused_insn_chains = 0;
1204 /* Yet another special case. Unfortunately, reg-stack forces people to
1205 write incorrect clobbers in asm statements. These clobbers must not
1206 cause the register to appear in bad_spill_regs, otherwise we'll call
1207 fatal_insn later. We clear the corresponding regnos in the live
1208 register sets to avoid this.
1209 The whole thing is rather sick, I'm afraid. */
1212 maybe_fix_stack_asms ()
1215 const char *constraints[MAX_RECOG_OPERANDS];
1216 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1217 struct insn_chain *chain;
1219 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1222 HARD_REG_SET clobbered, allowed;
1225 if (! INSN_P (chain->insn)
1226 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1228 pat = PATTERN (chain->insn);
1229 if (GET_CODE (pat) != PARALLEL)
1232 CLEAR_HARD_REG_SET (clobbered);
1233 CLEAR_HARD_REG_SET (allowed);
1235 /* First, make a mask of all stack regs that are clobbered. */
1236 for (i = 0; i < XVECLEN (pat, 0); i++)
1238 rtx t = XVECEXP (pat, 0, i);
1239 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1240 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1243 /* Get the operand values and constraints out of the insn. */
1244 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1245 constraints, operand_mode);
1247 /* For every operand, see what registers are allowed. */
1248 for (i = 0; i < noperands; i++)
1250 const char *p = constraints[i];
1251 /* For every alternative, we compute the class of registers allowed
1252 for reloading in CLS, and merge its contents into the reg set
1254 int cls = (int) NO_REGS;
1260 if (c == '\0' || c == ',' || c == '#')
1262 /* End of one alternative - mark the regs in the current
1263 class, and reset the class. */
1264 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1269 } while (c != '\0' && c != ',');
1277 case '=': case '+': case '*': case '%': case '?': case '!':
1278 case '0': case '1': case '2': case '3': case '4': case 'm':
1279 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1280 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1281 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1286 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1291 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1295 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1300 /* Those of the registers which are clobbered, but allowed by the
1301 constraints, must be usable as reload registers. So clear them
1302 out of the life information. */
1303 AND_HARD_REG_SET (allowed, clobbered);
1304 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1305 if (TEST_HARD_REG_BIT (allowed, i))
1307 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1308 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1315 /* Copy the global variables n_reloads and rld into the corresponding elts
1318 copy_reloads (chain)
1319 struct insn_chain *chain;
1321 chain->n_reloads = n_reloads;
1323 = (struct reload *) obstack_alloc (&reload_obstack,
1324 n_reloads * sizeof (struct reload));
1325 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1326 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1329 /* Walk the chain of insns, and determine for each whether it needs reloads
1330 and/or eliminations. Build the corresponding insns_need_reload list, and
1331 set something_needs_elimination as appropriate. */
1333 calculate_needs_all_insns (global)
1336 struct insn_chain **pprev_reload = &insns_need_reload;
1337 struct insn_chain *chain, *next = 0;
1339 something_needs_elimination = 0;
1341 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1342 for (chain = reload_insn_chain; chain != 0; chain = next)
1344 rtx insn = chain->insn;
1348 /* Clear out the shortcuts. */
1349 chain->n_reloads = 0;
1350 chain->need_elim = 0;
1351 chain->need_reload = 0;
1352 chain->need_operand_change = 0;
1354 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1355 include REG_LABEL), we need to see what effects this has on the
1356 known offsets at labels. */
1358 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1359 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1360 set_label_offsets (insn, insn, 0);
1364 rtx old_body = PATTERN (insn);
1365 int old_code = INSN_CODE (insn);
1366 rtx old_notes = REG_NOTES (insn);
1367 int did_elimination = 0;
1368 int operands_changed = 0;
1369 rtx set = single_set (insn);
1371 /* Skip insns that only set an equivalence. */
1372 if (set && GET_CODE (SET_DEST (set)) == REG
1373 && reg_renumber[REGNO (SET_DEST (set))] < 0
1374 && reg_equiv_constant[REGNO (SET_DEST (set))])
1377 /* If needed, eliminate any eliminable registers. */
1378 if (num_eliminable || num_eliminable_invariants)
1379 did_elimination = eliminate_regs_in_insn (insn, 0);
1381 /* Analyze the instruction. */
1382 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1383 global, spill_reg_order);
1385 /* If a no-op set needs more than one reload, this is likely
1386 to be something that needs input address reloads. We
1387 can't get rid of this cleanly later, and it is of no use
1388 anyway, so discard it now.
1389 We only do this when expensive_optimizations is enabled,
1390 since this complements reload inheritance / output
1391 reload deletion, and it can make debugging harder. */
1392 if (flag_expensive_optimizations && n_reloads > 1)
1394 rtx set = single_set (insn);
1396 && SET_SRC (set) == SET_DEST (set)
1397 && GET_CODE (SET_SRC (set)) == REG
1398 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1400 PUT_CODE (insn, NOTE);
1401 NOTE_SOURCE_FILE (insn) = 0;
1402 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1403 /* Delete it from the reload chain */
1405 chain->prev->next = next;
1407 reload_insn_chain = next;
1409 next->prev = chain->prev;
1410 chain->next = unused_insn_chains;
1411 unused_insn_chains = chain;
1416 update_eliminable_offsets ();
1418 /* Remember for later shortcuts which insns had any reloads or
1419 register eliminations. */
1420 chain->need_elim = did_elimination;
1421 chain->need_reload = n_reloads > 0;
1422 chain->need_operand_change = operands_changed;
1424 /* Discard any register replacements done. */
1425 if (did_elimination)
1427 obstack_free (&reload_obstack, reload_insn_firstobj);
1428 PATTERN (insn) = old_body;
1429 INSN_CODE (insn) = old_code;
1430 REG_NOTES (insn) = old_notes;
1431 something_needs_elimination = 1;
1434 something_needs_operands_changed |= operands_changed;
1438 copy_reloads (chain);
1439 *pprev_reload = chain;
1440 pprev_reload = &chain->next_need_reload;
1447 /* Comparison function for qsort to decide which of two reloads
1448 should be handled first. *P1 and *P2 are the reload numbers. */
1451 reload_reg_class_lower (r1p, r2p)
1455 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1458 /* Consider required reloads before optional ones. */
1459 t = rld[r1].optional - rld[r2].optional;
1463 /* Count all solitary classes before non-solitary ones. */
1464 t = ((reg_class_size[(int) rld[r2].class] == 1)
1465 - (reg_class_size[(int) rld[r1].class] == 1));
1469 /* Aside from solitaires, consider all multi-reg groups first. */
1470 t = rld[r2].nregs - rld[r1].nregs;
1474 /* Consider reloads in order of increasing reg-class number. */
1475 t = (int) rld[r1].class - (int) rld[r2].class;
1479 /* If reloads are equally urgent, sort by reload number,
1480 so that the results of qsort leave nothing to chance. */
1484 /* The cost of spilling each hard reg. */
1485 static int spill_cost[FIRST_PSEUDO_REGISTER];
1487 /* When spilling multiple hard registers, we use SPILL_COST for the first
1488 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1489 only the first hard reg for a multi-reg pseudo. */
1490 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1492 /* Update the spill cost arrays, considering that pseudo REG is live. */
1498 int n_refs = REG_N_REFS (reg);
1499 int r = reg_renumber[reg];
1502 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1503 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1506 SET_REGNO_REG_SET (&pseudos_counted, reg);
1511 spill_add_cost[r] += n_refs;
1513 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1515 spill_cost[r + nregs] += n_refs;
1518 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1519 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1522 order_regs_for_reload (chain)
1523 struct insn_chain *chain;
1526 HARD_REG_SET used_by_pseudos;
1527 HARD_REG_SET used_by_pseudos2;
1529 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1531 memset (spill_cost, 0, sizeof spill_cost);
1532 memset (spill_add_cost, 0, sizeof spill_add_cost);
1534 /* Count number of uses of each hard reg by pseudo regs allocated to it
1535 and then order them by decreasing use. First exclude hard registers
1536 that are live in or across this insn. */
1538 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1539 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1540 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1541 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1543 /* Now find out which pseudos are allocated to it, and update
1545 CLEAR_REG_SET (&pseudos_counted);
1547 EXECUTE_IF_SET_IN_REG_SET
1548 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1552 EXECUTE_IF_SET_IN_REG_SET
1553 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1557 CLEAR_REG_SET (&pseudos_counted);
1560 /* Vector of reload-numbers showing the order in which the reloads should
1562 static short reload_order[MAX_RELOADS];
1564 /* This is used to keep track of the spill regs used in one insn. */
1565 static HARD_REG_SET used_spill_regs_local;
1567 /* We decided to spill hard register SPILLED, which has a size of
1568 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1569 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1570 update SPILL_COST/SPILL_ADD_COST. */
1573 count_spilled_pseudo (spilled, spilled_nregs, reg)
1574 int spilled, spilled_nregs, reg;
1576 int r = reg_renumber[reg];
1577 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1579 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1580 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1583 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1585 spill_add_cost[r] -= REG_N_REFS (reg);
1587 spill_cost[r + nregs] -= REG_N_REFS (reg);
1590 /* Find reload register to use for reload number ORDER. */
1593 find_reg (chain, order)
1594 struct insn_chain *chain;
1597 int rnum = reload_order[order];
1598 struct reload *rl = rld + rnum;
1599 int best_cost = INT_MAX;
1603 HARD_REG_SET not_usable;
1604 HARD_REG_SET used_by_other_reload;
1606 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1607 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1608 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1610 CLEAR_HARD_REG_SET (used_by_other_reload);
1611 for (k = 0; k < order; k++)
1613 int other = reload_order[k];
1615 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1616 for (j = 0; j < rld[other].nregs; j++)
1617 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1620 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1622 unsigned int regno = i;
1624 if (! TEST_HARD_REG_BIT (not_usable, regno)
1625 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1626 && HARD_REGNO_MODE_OK (regno, rl->mode))
1628 int this_cost = spill_cost[regno];
1630 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1632 for (j = 1; j < this_nregs; j++)
1634 this_cost += spill_add_cost[regno + j];
1635 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1636 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1641 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1643 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1645 if (this_cost < best_cost
1646 /* Among registers with equal cost, prefer caller-saved ones, or
1647 use REG_ALLOC_ORDER if it is defined. */
1648 || (this_cost == best_cost
1649 #ifdef REG_ALLOC_ORDER
1650 && (inv_reg_alloc_order[regno]
1651 < inv_reg_alloc_order[best_reg])
1653 && call_used_regs[regno]
1654 && ! call_used_regs[best_reg]
1659 best_cost = this_cost;
1667 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1669 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1670 rl->regno = best_reg;
1672 EXECUTE_IF_SET_IN_REG_SET
1673 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1675 count_spilled_pseudo (best_reg, rl->nregs, j);
1678 EXECUTE_IF_SET_IN_REG_SET
1679 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1681 count_spilled_pseudo (best_reg, rl->nregs, j);
1684 for (i = 0; i < rl->nregs; i++)
1686 if (spill_cost[best_reg + i] != 0
1687 || spill_add_cost[best_reg + i] != 0)
1689 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1694 /* Find more reload regs to satisfy the remaining need of an insn, which
1696 Do it by ascending class number, since otherwise a reg
1697 might be spilled for a big class and might fail to count
1698 for a smaller class even though it belongs to that class. */
1701 find_reload_regs (chain)
1702 struct insn_chain *chain;
1706 /* In order to be certain of getting the registers we need,
1707 we must sort the reloads into order of increasing register class.
1708 Then our grabbing of reload registers will parallel the process
1709 that provided the reload registers. */
1710 for (i = 0; i < chain->n_reloads; i++)
1712 /* Show whether this reload already has a hard reg. */
1713 if (chain->rld[i].reg_rtx)
1715 int regno = REGNO (chain->rld[i].reg_rtx);
1716 chain->rld[i].regno = regno;
1718 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1721 chain->rld[i].regno = -1;
1722 reload_order[i] = i;
1725 n_reloads = chain->n_reloads;
1726 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1728 CLEAR_HARD_REG_SET (used_spill_regs_local);
1731 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1733 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1735 /* Compute the order of preference for hard registers to spill. */
1737 order_regs_for_reload (chain);
1739 for (i = 0; i < n_reloads; i++)
1741 int r = reload_order[i];
1743 /* Ignore reloads that got marked inoperative. */
1744 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1745 && ! rld[r].optional
1746 && rld[r].regno == -1)
1747 if (! find_reg (chain, i))
1749 spill_failure (chain->insn, rld[r].class);
1755 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1756 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1758 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1762 select_reload_regs ()
1764 struct insn_chain *chain;
1766 /* Try to satisfy the needs for each insn. */
1767 for (chain = insns_need_reload; chain != 0;
1768 chain = chain->next_need_reload)
1769 find_reload_regs (chain);
1772 /* Delete all insns that were inserted by emit_caller_save_insns during
1775 delete_caller_save_insns ()
1777 struct insn_chain *c = reload_insn_chain;
1781 while (c != 0 && c->is_caller_save_insn)
1783 struct insn_chain *next = c->next;
1786 if (insn == BLOCK_HEAD (c->block))
1787 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1788 if (insn == BLOCK_END (c->block))
1789 BLOCK_END (c->block) = PREV_INSN (insn);
1790 if (c == reload_insn_chain)
1791 reload_insn_chain = next;
1793 if (NEXT_INSN (insn) != 0)
1794 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1795 if (PREV_INSN (insn) != 0)
1796 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1799 next->prev = c->prev;
1801 c->prev->next = next;
1802 c->next = unused_insn_chains;
1803 unused_insn_chains = c;
1811 /* Handle the failure to find a register to spill.
1812 INSN should be one of the insns which needed this particular spill reg. */
1815 spill_failure (insn, class)
1817 enum reg_class class;
1819 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1820 if (asm_noperands (PATTERN (insn)) >= 0)
1821 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1822 reg_class_names[class]);
1825 error ("Unable to find a register to spill in class `%s'.",
1826 reg_class_names[class]);
1827 fatal_insn ("This is the insn:", insn);
1831 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1832 data that is dead in INSN. */
1835 delete_dead_insn (insn)
1838 rtx prev = prev_real_insn (insn);
1841 /* If the previous insn sets a register that dies in our insn, delete it
1843 if (prev && GET_CODE (PATTERN (prev)) == SET
1844 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1845 && reg_mentioned_p (prev_dest, PATTERN (insn))
1846 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1847 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1848 delete_dead_insn (prev);
1850 PUT_CODE (insn, NOTE);
1851 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1852 NOTE_SOURCE_FILE (insn) = 0;
1855 /* Modify the home of pseudo-reg I.
1856 The new home is present in reg_renumber[I].
1858 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1859 or it may be -1, meaning there is none or it is not relevant.
1860 This is used so that all pseudos spilled from a given hard reg
1861 can share one stack slot. */
1864 alter_reg (i, from_reg)
1868 /* When outputting an inline function, this can happen
1869 for a reg that isn't actually used. */
1870 if (regno_reg_rtx[i] == 0)
1873 /* If the reg got changed to a MEM at rtl-generation time,
1875 if (GET_CODE (regno_reg_rtx[i]) != REG)
1878 /* Modify the reg-rtx to contain the new hard reg
1879 number or else to contain its pseudo reg number. */
1880 REGNO (regno_reg_rtx[i])
1881 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1883 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1884 allocate a stack slot for it. */
1886 if (reg_renumber[i] < 0
1887 && REG_N_REFS (i) > 0
1888 && reg_equiv_constant[i] == 0
1889 && reg_equiv_memory_loc[i] == 0)
1892 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1893 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1896 /* Each pseudo reg has an inherent size which comes from its own mode,
1897 and a total size which provides room for paradoxical subregs
1898 which refer to the pseudo reg in wider modes.
1900 We can use a slot already allocated if it provides both
1901 enough inherent space and enough total space.
1902 Otherwise, we allocate a new slot, making sure that it has no less
1903 inherent space, and no less total space, then the previous slot. */
1906 /* No known place to spill from => no slot to reuse. */
1907 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1908 inherent_size == total_size ? 0 : -1);
1909 if (BYTES_BIG_ENDIAN)
1910 /* Cancel the big-endian correction done in assign_stack_local.
1911 Get the address of the beginning of the slot.
1912 This is so we can do a big-endian correction unconditionally
1914 adjust = inherent_size - total_size;
1916 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1918 /* Nothing can alias this slot except this pseudo. */
1919 MEM_ALIAS_SET (x) = new_alias_set ();
1922 /* Reuse a stack slot if possible. */
1923 else if (spill_stack_slot[from_reg] != 0
1924 && spill_stack_slot_width[from_reg] >= total_size
1925 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1927 x = spill_stack_slot[from_reg];
1929 /* Allocate a bigger slot. */
1932 /* Compute maximum size needed, both for inherent size
1933 and for total size. */
1934 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1937 if (spill_stack_slot[from_reg])
1939 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1941 mode = GET_MODE (spill_stack_slot[from_reg]);
1942 if (spill_stack_slot_width[from_reg] > total_size)
1943 total_size = spill_stack_slot_width[from_reg];
1946 /* Make a slot with that size. */
1947 x = assign_stack_local (mode, total_size,
1948 inherent_size == total_size ? 0 : -1);
1951 /* All pseudos mapped to this slot can alias each other. */
1952 if (spill_stack_slot[from_reg])
1953 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1955 MEM_ALIAS_SET (x) = new_alias_set ();
1957 if (BYTES_BIG_ENDIAN)
1959 /* Cancel the big-endian correction done in assign_stack_local.
1960 Get the address of the beginning of the slot.
1961 This is so we can do a big-endian correction unconditionally
1963 adjust = GET_MODE_SIZE (mode) - total_size;
1965 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1968 plus_constant (XEXP (x, 0), adjust));
1971 spill_stack_slot[from_reg] = stack_slot;
1972 spill_stack_slot_width[from_reg] = total_size;
1975 /* On a big endian machine, the "address" of the slot
1976 is the address of the low part that fits its inherent mode. */
1977 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1978 adjust += (total_size - inherent_size);
1980 /* If we have any adjustment to make, or if the stack slot is the
1981 wrong mode, make a new stack slot. */
1982 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1984 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1985 plus_constant (XEXP (x, 0), adjust));
1987 MEM_COPY_ATTRIBUTES (new, x);
1991 /* Save the stack slot for later. */
1992 reg_equiv_memory_loc[i] = x;
1996 /* Mark the slots in regs_ever_live for the hard regs
1997 used by pseudo-reg number REGNO. */
2000 mark_home_live (regno)
2003 register int i, lim;
2005 i = reg_renumber[regno];
2008 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2010 regs_ever_live[i++] = 1;
2013 /* This function handles the tracking of elimination offsets around branches.
2015 X is a piece of RTL being scanned.
2017 INSN is the insn that it came from, if any.
2019 INITIAL_P is non-zero if we are to set the offset to be the initial
2020 offset and zero if we are setting the offset of the label to be the
2024 set_label_offsets (x, insn, initial_p)
2029 enum rtx_code code = GET_CODE (x);
2032 struct elim_table *p;
2037 if (LABEL_REF_NONLOCAL_P (x))
2042 /* ... fall through ... */
2045 /* If we know nothing about this label, set the desired offsets. Note
2046 that this sets the offset at a label to be the offset before a label
2047 if we don't know anything about the label. This is not correct for
2048 the label after a BARRIER, but is the best guess we can make. If
2049 we guessed wrong, we will suppress an elimination that might have
2050 been possible had we been able to guess correctly. */
2052 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2054 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2055 offsets_at[CODE_LABEL_NUMBER (x)][i]
2056 = (initial_p ? reg_eliminate[i].initial_offset
2057 : reg_eliminate[i].offset);
2058 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2061 /* Otherwise, if this is the definition of a label and it is
2062 preceded by a BARRIER, set our offsets to the known offset of
2066 && (tem = prev_nonnote_insn (insn)) != 0
2067 && GET_CODE (tem) == BARRIER)
2068 set_offsets_for_label (insn);
2070 /* If neither of the above cases is true, compare each offset
2071 with those previously recorded and suppress any eliminations
2072 where the offsets disagree. */
2074 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2075 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2076 != (initial_p ? reg_eliminate[i].initial_offset
2077 : reg_eliminate[i].offset))
2078 reg_eliminate[i].can_eliminate = 0;
2083 set_label_offsets (PATTERN (insn), insn, initial_p);
2085 /* ... fall through ... */
2089 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2090 and hence must have all eliminations at their initial offsets. */
2091 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2092 if (REG_NOTE_KIND (tem) == REG_LABEL)
2093 set_label_offsets (XEXP (tem, 0), insn, 1);
2099 /* Each of the labels in the parallel or address vector must be
2100 at their initial offsets. We want the first field for PARALLEL
2101 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2103 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2104 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2109 /* We only care about setting PC. If the source is not RETURN,
2110 IF_THEN_ELSE, or a label, disable any eliminations not at
2111 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2112 isn't one of those possibilities. For branches to a label,
2113 call ourselves recursively.
2115 Note that this can disable elimination unnecessarily when we have
2116 a non-local goto since it will look like a non-constant jump to
2117 someplace in the current function. This isn't a significant
2118 problem since such jumps will normally be when all elimination
2119 pairs are back to their initial offsets. */
2121 if (SET_DEST (x) != pc_rtx)
2124 switch (GET_CODE (SET_SRC (x)))
2131 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2135 tem = XEXP (SET_SRC (x), 1);
2136 if (GET_CODE (tem) == LABEL_REF)
2137 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2138 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2141 tem = XEXP (SET_SRC (x), 2);
2142 if (GET_CODE (tem) == LABEL_REF)
2143 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2144 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2152 /* If we reach here, all eliminations must be at their initial
2153 offset because we are doing a jump to a variable address. */
2154 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2155 if (p->offset != p->initial_offset)
2156 p->can_eliminate = 0;
2164 /* Scan X and replace any eliminable registers (such as fp) with a
2165 replacement (such as sp), plus an offset.
2167 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2168 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2169 MEM, we are allowed to replace a sum of a register and the constant zero
2170 with the register, which we cannot do outside a MEM. In addition, we need
2171 to record the fact that a register is referenced outside a MEM.
2173 If INSN is an insn, it is the insn containing X. If we replace a REG
2174 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2175 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2176 the REG is being modified.
2178 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2179 That's used when we eliminate in expressions stored in notes.
2180 This means, do not set ref_outside_mem even if the reference
2183 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2184 replacements done assuming all offsets are at their initial values. If
2185 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2186 encounter, return the actual location so that find_reloads will do
2187 the proper thing. */
2190 eliminate_regs (x, mem_mode, insn)
2192 enum machine_mode mem_mode;
2195 enum rtx_code code = GET_CODE (x);
2196 struct elim_table *ep;
2203 if (! current_function_decl)
2222 /* This is only for the benefit of the debugging backends, which call
2223 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2224 removed after CSE. */
2225 new = eliminate_regs (XEXP (x, 0), 0, insn);
2226 if (GET_CODE (new) == MEM)
2227 return XEXP (new, 0);
2233 /* First handle the case where we encounter a bare register that
2234 is eliminable. Replace it with a PLUS. */
2235 if (regno < FIRST_PSEUDO_REGISTER)
2237 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2239 if (ep->from_rtx == x && ep->can_eliminate)
2240 return plus_constant (ep->to_rtx, ep->previous_offset);
2243 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2244 && reg_equiv_constant[regno]
2245 && ! CONSTANT_P (reg_equiv_constant[regno]))
2246 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2250 /* You might think handling MINUS in a manner similar to PLUS is a
2251 good idea. It is not. It has been tried multiple times and every
2252 time the change has had to have been reverted.
2254 Other parts of reload know a PLUS is special (gen_reload for example)
2255 and require special code to handle code a reloaded PLUS operand.
2257 Also consider backends where the flags register is clobbered by a
2258 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2259 lea instruction comes to mind). If we try to reload a MINUS, we
2260 may kill the flags register that was holding a useful value.
2262 So, please before trying to handle MINUS, consider reload as a
2263 whole instead of this little section as well as the backend issues. */
2265 /* If this is the sum of an eliminable register and a constant, rework
2267 if (GET_CODE (XEXP (x, 0)) == REG
2268 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2269 && CONSTANT_P (XEXP (x, 1)))
2271 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2273 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2275 /* The only time we want to replace a PLUS with a REG (this
2276 occurs when the constant operand of the PLUS is the negative
2277 of the offset) is when we are inside a MEM. We won't want
2278 to do so at other times because that would change the
2279 structure of the insn in a way that reload can't handle.
2280 We special-case the commonest situation in
2281 eliminate_regs_in_insn, so just replace a PLUS with a
2282 PLUS here, unless inside a MEM. */
2283 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2284 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2287 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2288 plus_constant (XEXP (x, 1),
2289 ep->previous_offset));
2292 /* If the register is not eliminable, we are done since the other
2293 operand is a constant. */
2297 /* If this is part of an address, we want to bring any constant to the
2298 outermost PLUS. We will do this by doing register replacement in
2299 our operands and seeing if a constant shows up in one of them.
2301 Note that there is no risk of modifying the structure of the insn,
2302 since we only get called for its operands, thus we are either
2303 modifying the address inside a MEM, or something like an address
2304 operand of a load-address insn. */
2307 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2308 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2310 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2312 /* If one side is a PLUS and the other side is a pseudo that
2313 didn't get a hard register but has a reg_equiv_constant,
2314 we must replace the constant here since it may no longer
2315 be in the position of any operand. */
2316 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2317 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2318 && reg_renumber[REGNO (new1)] < 0
2319 && reg_equiv_constant != 0
2320 && reg_equiv_constant[REGNO (new1)] != 0)
2321 new1 = reg_equiv_constant[REGNO (new1)];
2322 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2323 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2324 && reg_renumber[REGNO (new0)] < 0
2325 && reg_equiv_constant[REGNO (new0)] != 0)
2326 new0 = reg_equiv_constant[REGNO (new0)];
2328 new = form_sum (new0, new1);
2330 /* As above, if we are not inside a MEM we do not want to
2331 turn a PLUS into something else. We might try to do so here
2332 for an addition of 0 if we aren't optimizing. */
2333 if (! mem_mode && GET_CODE (new) != PLUS)
2334 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2342 /* If this is the product of an eliminable register and a
2343 constant, apply the distribute law and move the constant out
2344 so that we have (plus (mult ..) ..). This is needed in order
2345 to keep load-address insns valid. This case is pathological.
2346 We ignore the possibility of overflow here. */
2347 if (GET_CODE (XEXP (x, 0)) == REG
2348 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2349 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2350 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2352 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2355 /* Refs inside notes don't count for this purpose. */
2356 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2357 || GET_CODE (insn) == INSN_LIST)))
2358 ep->ref_outside_mem = 1;
2361 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2362 ep->previous_offset * INTVAL (XEXP (x, 1)));
2365 /* ... fall through ... */
2369 /* See comments before PLUS about handling MINUS. */
2371 case DIV: case UDIV:
2372 case MOD: case UMOD:
2373 case AND: case IOR: case XOR:
2374 case ROTATERT: case ROTATE:
2375 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2377 case GE: case GT: case GEU: case GTU:
2378 case LE: case LT: case LEU: case LTU:
2380 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2382 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2384 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2385 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2390 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2393 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2394 if (new != XEXP (x, 0))
2396 /* If this is a REG_DEAD note, it is not valid anymore.
2397 Using the eliminated version could result in creating a
2398 REG_DEAD note for the stack or frame pointer. */
2399 if (GET_MODE (x) == REG_DEAD)
2401 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2404 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2408 /* ... fall through ... */
2411 /* Now do eliminations in the rest of the chain. If this was
2412 an EXPR_LIST, this might result in allocating more memory than is
2413 strictly needed, but it simplifies the code. */
2416 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2417 if (new != XEXP (x, 1))
2418 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2426 case STRICT_LOW_PART:
2428 case SIGN_EXTEND: case ZERO_EXTEND:
2429 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2430 case FLOAT: case FIX:
2431 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2435 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2436 if (new != XEXP (x, 0))
2437 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2441 /* Similar to above processing, but preserve SUBREG_WORD.
2442 Convert (subreg (mem)) to (mem) if not paradoxical.
2443 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2444 pseudo didn't get a hard reg, we must replace this with the
2445 eliminated version of the memory location because push_reloads
2446 may do the replacement in certain circumstances. */
2447 if (GET_CODE (SUBREG_REG (x)) == REG
2448 && (GET_MODE_SIZE (GET_MODE (x))
2449 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2450 && reg_equiv_memory_loc != 0
2451 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2453 new = SUBREG_REG (x);
2456 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2458 if (new != XEXP (x, 0))
2460 int x_size = GET_MODE_SIZE (GET_MODE (x));
2461 int new_size = GET_MODE_SIZE (GET_MODE (new));
2463 if (GET_CODE (new) == MEM
2464 && ((x_size < new_size
2465 #ifdef WORD_REGISTER_OPERATIONS
2466 /* On these machines, combine can create rtl of the form
2467 (set (subreg:m1 (reg:m2 R) 0) ...)
2468 where m1 < m2, and expects something interesting to
2469 happen to the entire word. Moreover, it will use the
2470 (reg:m2 R) later, expecting all bits to be preserved.
2471 So if the number of words is the same, preserve the
2472 subreg so that push_reloads can see it. */
2473 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2476 || (x_size == new_size))
2479 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2480 enum machine_mode mode = GET_MODE (x);
2482 if (BYTES_BIG_ENDIAN)
2483 offset += (MIN (UNITS_PER_WORD,
2484 GET_MODE_SIZE (GET_MODE (new)))
2485 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2487 PUT_MODE (new, mode);
2488 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2492 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2498 /* This is only for the benefit of the debugging backends, which call
2499 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2500 removed after CSE. */
2501 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2502 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2504 /* Our only special processing is to pass the mode of the MEM to our
2505 recursive call and copy the flags. While we are here, handle this
2506 case more efficiently. */
2507 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2508 if (new != XEXP (x, 0))
2510 new = gen_rtx_MEM (GET_MODE (x), new);
2511 MEM_COPY_ATTRIBUTES (new, x);
2527 /* Process each of our operands recursively. If any have changed, make a
2529 fmt = GET_RTX_FORMAT (code);
2530 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2534 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2535 if (new != XEXP (x, i) && ! copied)
2537 rtx new_x = rtx_alloc (code);
2539 (sizeof (*new_x) - sizeof (new_x->fld)
2540 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2546 else if (*fmt == 'E')
2549 for (j = 0; j < XVECLEN (x, i); j++)
2551 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2552 if (new != XVECEXP (x, i, j) && ! copied_vec)
2554 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2558 rtx new_x = rtx_alloc (code);
2560 (sizeof (*new_x) - sizeof (new_x->fld)
2561 + (sizeof (new_x->fld[0])
2562 * GET_RTX_LENGTH (code))));
2566 XVEC (x, i) = new_v;
2569 XVECEXP (x, i, j) = new;
2577 /* Scan rtx X for modifications of elimination target registers. Update
2578 the table of eliminables to reflect the changed state. MEM_MODE is
2579 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2582 elimination_effects (x, mem_mode)
2584 enum machine_mode mem_mode;
2587 enum rtx_code code = GET_CODE (x);
2588 struct elim_table *ep;
2614 /* First handle the case where we encounter a bare register that
2615 is eliminable. Replace it with a PLUS. */
2616 if (regno < FIRST_PSEUDO_REGISTER)
2618 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2620 if (ep->from_rtx == x && ep->can_eliminate)
2623 ep->ref_outside_mem = 1;
2628 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2629 && reg_equiv_constant[regno]
2630 && ! CONSTANT_P (reg_equiv_constant[regno]))
2631 elimination_effects (reg_equiv_constant[regno], mem_mode);
2640 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2641 if (ep->to_rtx == XEXP (x, 0))
2643 int size = GET_MODE_SIZE (mem_mode);
2645 /* If more bytes than MEM_MODE are pushed, account for them. */
2646 #ifdef PUSH_ROUNDING
2647 if (ep->to_rtx == stack_pointer_rtx)
2648 size = PUSH_ROUNDING (size);
2650 if (code == PRE_DEC || code == POST_DEC)
2652 else if (code == PRE_INC || code == POST_INC)
2654 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2655 && GET_CODE (XEXP (x, 1)) == PLUS
2656 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2657 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2658 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2661 /* These two aren't unary operators. */
2662 if (code == POST_MODIFY || code == PRE_MODIFY)
2665 /* Fall through to generic unary operation case. */
2666 case STRICT_LOW_PART:
2668 case SIGN_EXTEND: case ZERO_EXTEND:
2669 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2670 case FLOAT: case FIX:
2671 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2675 elimination_effects (XEXP (x, 0), mem_mode);
2679 if (GET_CODE (SUBREG_REG (x)) == REG
2680 && (GET_MODE_SIZE (GET_MODE (x))
2681 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2682 && reg_equiv_memory_loc != 0
2683 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2686 elimination_effects (SUBREG_REG (x), mem_mode);
2690 /* If using a register that is the source of an eliminate we still
2691 think can be performed, note it cannot be performed since we don't
2692 know how this register is used. */
2693 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2694 if (ep->from_rtx == XEXP (x, 0))
2695 ep->can_eliminate = 0;
2697 elimination_effects (XEXP (x, 0), mem_mode);
2701 /* If clobbering a register that is the replacement register for an
2702 elimination we still think can be performed, note that it cannot
2703 be performed. Otherwise, we need not be concerned about it. */
2704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2705 if (ep->to_rtx == XEXP (x, 0))
2706 ep->can_eliminate = 0;
2708 elimination_effects (XEXP (x, 0), mem_mode);
2712 /* Check for setting a register that we know about. */
2713 if (GET_CODE (SET_DEST (x)) == REG)
2715 /* See if this is setting the replacement register for an
2718 If DEST is the hard frame pointer, we do nothing because we
2719 assume that all assignments to the frame pointer are for
2720 non-local gotos and are being done at a time when they are valid
2721 and do not disturb anything else. Some machines want to
2722 eliminate a fake argument pointer (or even a fake frame pointer)
2723 with either the real frame or the stack pointer. Assignments to
2724 the hard frame pointer must not prevent this elimination. */
2726 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2728 if (ep->to_rtx == SET_DEST (x)
2729 && SET_DEST (x) != hard_frame_pointer_rtx)
2731 /* If it is being incremented, adjust the offset. Otherwise,
2732 this elimination can't be done. */
2733 rtx src = SET_SRC (x);
2735 if (GET_CODE (src) == PLUS
2736 && XEXP (src, 0) == SET_DEST (x)
2737 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2738 ep->offset -= INTVAL (XEXP (src, 1));
2740 ep->can_eliminate = 0;
2744 elimination_effects (SET_DEST (x), 0);
2745 elimination_effects (SET_SRC (x), 0);
2749 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2752 /* Our only special processing is to pass the mode of the MEM to our
2754 elimination_effects (XEXP (x, 0), GET_MODE (x));
2761 fmt = GET_RTX_FORMAT (code);
2762 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2765 elimination_effects (XEXP (x, i), mem_mode);
2766 else if (*fmt == 'E')
2767 for (j = 0; j < XVECLEN (x, i); j++)
2768 elimination_effects (XVECEXP (x, i, j), mem_mode);
2772 /* Descend through rtx X and verify that no references to eliminable registers
2773 remain. If any do remain, mark the involved register as not
2777 check_eliminable_occurrences (x)
2787 code = GET_CODE (x);
2789 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2791 struct elim_table *ep;
2793 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2794 if (ep->from_rtx == x && ep->can_eliminate)
2795 ep->can_eliminate = 0;
2799 fmt = GET_RTX_FORMAT (code);
2800 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2803 check_eliminable_occurrences (XEXP (x, i));
2804 else if (*fmt == 'E')
2807 for (j = 0; j < XVECLEN (x, i); j++)
2808 check_eliminable_occurrences (XVECEXP (x, i, j));
2813 /* Scan INSN and eliminate all eliminable registers in it.
2815 If REPLACE is nonzero, do the replacement destructively. Also
2816 delete the insn as dead it if it is setting an eliminable register.
2818 If REPLACE is zero, do all our allocations in reload_obstack.
2820 If no eliminations were done and this insn doesn't require any elimination
2821 processing (these are not identical conditions: it might be updating sp,
2822 but not referencing fp; this needs to be seen during reload_as_needed so
2823 that the offset between fp and sp can be taken into consideration), zero
2824 is returned. Otherwise, 1 is returned. */
2827 eliminate_regs_in_insn (insn, replace)
2831 int icode = recog_memoized (insn);
2832 rtx old_body = PATTERN (insn);
2833 int insn_is_asm = asm_noperands (old_body) >= 0;
2834 rtx old_set = single_set (insn);
2838 rtx substed_operand[MAX_RECOG_OPERANDS];
2839 rtx orig_operand[MAX_RECOG_OPERANDS];
2840 struct elim_table *ep;
2842 if (! insn_is_asm && icode < 0)
2844 if (GET_CODE (PATTERN (insn)) == USE
2845 || GET_CODE (PATTERN (insn)) == CLOBBER
2846 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2847 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2848 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2853 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2854 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2856 /* Check for setting an eliminable register. */
2857 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2858 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2860 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2861 /* If this is setting the frame pointer register to the
2862 hardware frame pointer register and this is an elimination
2863 that will be done (tested above), this insn is really
2864 adjusting the frame pointer downward to compensate for
2865 the adjustment done before a nonlocal goto. */
2866 if (ep->from == FRAME_POINTER_REGNUM
2867 && ep->to == HARD_FRAME_POINTER_REGNUM)
2869 rtx src = SET_SRC (old_set);
2870 int offset = 0, ok = 0;
2871 rtx prev_insn, prev_set;
2873 if (src == ep->to_rtx)
2875 else if (GET_CODE (src) == PLUS
2876 && GET_CODE (XEXP (src, 0)) == CONST_INT
2877 && XEXP (src, 1) == ep->to_rtx)
2878 offset = INTVAL (XEXP (src, 0)), ok = 1;
2879 else if (GET_CODE (src) == PLUS
2880 && GET_CODE (XEXP (src, 1)) == CONST_INT
2881 && XEXP (src, 0) == ep->to_rtx)
2882 offset = INTVAL (XEXP (src, 1)), ok = 1;
2883 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2884 && (prev_set = single_set (prev_insn)) != 0
2885 && rtx_equal_p (SET_DEST (prev_set), src))
2887 src = SET_SRC (prev_set);
2888 if (src == ep->to_rtx)
2890 else if (GET_CODE (src) == PLUS
2891 && GET_CODE (XEXP (src, 0)) == CONST_INT
2892 && XEXP (src, 1) == ep->to_rtx)
2893 offset = INTVAL (XEXP (src, 0)), ok = 1;
2894 else if (GET_CODE (src) == PLUS
2895 && GET_CODE (XEXP (src, 1)) == CONST_INT
2896 && XEXP (src, 0) == ep->to_rtx)
2897 offset = INTVAL (XEXP (src, 1)), ok = 1;
2905 = plus_constant (ep->to_rtx, offset - ep->offset);
2907 /* First see if this insn remains valid when we
2908 make the change. If not, keep the INSN_CODE
2909 the same and let reload fit it up. */
2910 validate_change (insn, &SET_SRC (old_set), src, 1);
2911 validate_change (insn, &SET_DEST (old_set),
2913 if (! apply_change_group ())
2915 SET_SRC (old_set) = src;
2916 SET_DEST (old_set) = ep->to_rtx;
2926 /* In this case this insn isn't serving a useful purpose. We
2927 will delete it in reload_as_needed once we know that this
2928 elimination is, in fact, being done.
2930 If REPLACE isn't set, we can't delete this insn, but needn't
2931 process it since it won't be used unless something changes. */
2934 delete_dead_insn (insn);
2942 /* We allow one special case which happens to work on all machines we
2943 currently support: a single set with the source being a PLUS of an
2944 eliminable register and a constant. */
2946 && GET_CODE (SET_SRC (old_set)) == PLUS
2947 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2948 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2949 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2951 rtx reg = XEXP (SET_SRC (old_set), 0);
2952 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2954 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2955 if (ep->from_rtx == reg && ep->can_eliminate)
2957 offset += ep->offset;
2962 /* We assume here that if we need a PARALLEL with
2963 CLOBBERs for this assignment, we can do with the
2964 MATCH_SCRATCHes that add_clobbers allocates.
2965 There's not much we can do if that doesn't work. */
2966 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2970 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
2973 rtvec vec = rtvec_alloc (num_clobbers + 1);
2975 vec->elem[0] = PATTERN (insn);
2976 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
2977 add_clobbers (PATTERN (insn), INSN_CODE (insn));
2979 if (INSN_CODE (insn) < 0)
2984 new_body = old_body;
2987 new_body = copy_insn (old_body);
2988 if (REG_NOTES (insn))
2989 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2991 PATTERN (insn) = new_body;
2992 old_set = single_set (insn);
2994 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2995 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2998 /* This can't have an effect on elimination offsets, so skip right
3004 /* Determine the effects of this insn on elimination offsets. */
3005 elimination_effects (old_body, 0);
3007 /* Eliminate all eliminable registers occurring in operands that
3008 can be handled by reload. */
3009 extract_insn (insn);
3011 for (i = 0; i < recog_data.n_operands; i++)
3013 orig_operand[i] = recog_data.operand[i];
3014 substed_operand[i] = recog_data.operand[i];
3016 /* For an asm statement, every operand is eliminable. */
3017 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3019 /* Check for setting a register that we know about. */
3020 if (recog_data.operand_type[i] != OP_IN
3021 && GET_CODE (orig_operand[i]) == REG)
3023 /* If we are assigning to a register that can be eliminated, it
3024 must be as part of a PARALLEL, since the code above handles
3025 single SETs. We must indicate that we can no longer
3026 eliminate this reg. */
3027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3029 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3030 ep->can_eliminate = 0;
3033 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3034 replace ? insn : NULL_RTX);
3035 if (substed_operand[i] != orig_operand[i])
3036 val = any_changes = 1;
3037 /* Terminate the search in check_eliminable_occurrences at
3039 *recog_data.operand_loc[i] = 0;
3041 /* If an output operand changed from a REG to a MEM and INSN is an
3042 insn, write a CLOBBER insn. */
3043 if (recog_data.operand_type[i] != OP_IN
3044 && GET_CODE (orig_operand[i]) == REG
3045 && GET_CODE (substed_operand[i]) == MEM
3047 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3052 for (i = 0; i < recog_data.n_dups; i++)
3053 *recog_data.dup_loc[i]
3054 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3056 /* If any eliminable remain, they aren't eliminable anymore. */
3057 check_eliminable_occurrences (old_body);
3059 /* Substitute the operands; the new values are in the substed_operand
3061 for (i = 0; i < recog_data.n_operands; i++)
3062 *recog_data.operand_loc[i] = substed_operand[i];
3063 for (i = 0; i < recog_data.n_dups; i++)
3064 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3066 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3067 re-recognize the insn. We do this in case we had a simple addition
3068 but now can do this as a load-address. This saves an insn in this
3070 If re-recognition fails, the old insn code number will still be used,
3071 and some register operands may have changed into PLUS expressions.
3072 These will be handled by find_reloads by loading them into a register
3077 /* If we aren't replacing things permanently and we changed something,
3078 make another copy to ensure that all the RTL is new. Otherwise
3079 things can go wrong if find_reload swaps commutative operands
3080 and one is inside RTL that has been copied while the other is not. */
3081 new_body = old_body;
3084 new_body = copy_insn (old_body);
3085 if (REG_NOTES (insn))
3086 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3088 PATTERN (insn) = new_body;
3090 /* If we had a move insn but now we don't, rerecognize it. This will
3091 cause spurious re-recognition if the old move had a PARALLEL since
3092 the new one still will, but we can't call single_set without
3093 having put NEW_BODY into the insn and the re-recognition won't
3094 hurt in this rare case. */
3095 /* ??? Why this huge if statement - why don't we just rerecognize the
3099 && ((GET_CODE (SET_SRC (old_set)) == REG
3100 && (GET_CODE (new_body) != SET
3101 || GET_CODE (SET_SRC (new_body)) != REG))
3102 /* If this was a load from or store to memory, compare
3103 the MEM in recog_data.operand to the one in the insn.
3104 If they are not equal, then rerecognize the insn. */
3106 && ((GET_CODE (SET_SRC (old_set)) == MEM
3107 && SET_SRC (old_set) != recog_data.operand[1])
3108 || (GET_CODE (SET_DEST (old_set)) == MEM
3109 && SET_DEST (old_set) != recog_data.operand[0])))
3110 /* If this was an add insn before, rerecognize. */
3111 || GET_CODE (SET_SRC (old_set)) == PLUS))
3113 int new_icode = recog (PATTERN (insn), insn, 0);
3115 INSN_CODE (insn) = icode;
3119 /* Restore the old body. If there were any changes to it, we made a copy
3120 of it while the changes were still in place, so we'll correctly return
3121 a modified insn below. */
3124 /* Restore the old body. */
3125 for (i = 0; i < recog_data.n_operands; i++)
3126 *recog_data.operand_loc[i] = orig_operand[i];
3127 for (i = 0; i < recog_data.n_dups; i++)
3128 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3131 /* Update all elimination pairs to reflect the status after the current
3132 insn. The changes we make were determined by the earlier call to
3133 elimination_effects.
3135 We also detect a cases where register elimination cannot be done,
3136 namely, if a register would be both changed and referenced outside a MEM
3137 in the resulting insn since such an insn is often undefined and, even if
3138 not, we cannot know what meaning will be given to it. Note that it is
3139 valid to have a register used in an address in an insn that changes it
3140 (presumably with a pre- or post-increment or decrement).
3142 If anything changes, return nonzero. */
3144 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3146 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3147 ep->can_eliminate = 0;
3149 ep->ref_outside_mem = 0;
3151 if (ep->previous_offset != ep->offset)
3156 /* If we changed something, perform elimination in REG_NOTES. This is
3157 needed even when REPLACE is zero because a REG_DEAD note might refer
3158 to a register that we eliminate and could cause a different number
3159 of spill registers to be needed in the final reload pass than in
3161 if (val && REG_NOTES (insn) != 0)
3162 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3167 /* Loop through all elimination pairs.
3168 Recalculate the number not at initial offset.
3170 Compute the maximum offset (minimum offset if the stack does not
3171 grow downward) for each elimination pair. */
3174 update_eliminable_offsets ()
3176 struct elim_table *ep;
3178 num_not_at_initial_offset = 0;
3179 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3181 ep->previous_offset = ep->offset;
3182 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3183 num_not_at_initial_offset++;
3187 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3188 replacement we currently believe is valid, mark it as not eliminable if X
3189 modifies DEST in any way other than by adding a constant integer to it.
3191 If DEST is the frame pointer, we do nothing because we assume that
3192 all assignments to the hard frame pointer are nonlocal gotos and are being
3193 done at a time when they are valid and do not disturb anything else.
3194 Some machines want to eliminate a fake argument pointer with either the
3195 frame or stack pointer. Assignments to the hard frame pointer must not
3196 prevent this elimination.
3198 Called via note_stores from reload before starting its passes to scan
3199 the insns of the function. */
3202 mark_not_eliminable (dest, x, data)
3205 void *data ATTRIBUTE_UNUSED;
3207 register unsigned int i;
3209 /* A SUBREG of a hard register here is just changing its mode. We should
3210 not see a SUBREG of an eliminable hard register, but check just in
3212 if (GET_CODE (dest) == SUBREG)
3213 dest = SUBREG_REG (dest);
3215 if (dest == hard_frame_pointer_rtx)
3218 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3219 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3220 && (GET_CODE (x) != SET
3221 || GET_CODE (SET_SRC (x)) != PLUS
3222 || XEXP (SET_SRC (x), 0) != dest
3223 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3225 reg_eliminate[i].can_eliminate_previous
3226 = reg_eliminate[i].can_eliminate = 0;
3231 /* Verify that the initial elimination offsets did not change since the
3232 last call to set_initial_elim_offsets. This is used to catch cases
3233 where something illegal happened during reload_as_needed that could
3234 cause incorrect code to be generated if we did not check for it. */
3237 verify_initial_elim_offsets ()
3241 #ifdef ELIMINABLE_REGS
3242 struct elim_table *ep;
3244 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3246 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3247 if (t != ep->initial_offset)
3251 INITIAL_FRAME_POINTER_OFFSET (t);
3252 if (t != reg_eliminate[0].initial_offset)
3257 /* Reset all offsets on eliminable registers to their initial values. */
3260 set_initial_elim_offsets ()
3262 struct elim_table *ep = reg_eliminate;
3264 #ifdef ELIMINABLE_REGS
3265 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3267 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3268 ep->previous_offset = ep->offset = ep->initial_offset;
3271 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3272 ep->previous_offset = ep->offset = ep->initial_offset;
3275 num_not_at_initial_offset = 0;
3278 /* Initialize the known label offsets.
3279 Set a known offset for each forced label to be at the initial offset
3280 of each elimination. We do this because we assume that all
3281 computed jumps occur from a location where each elimination is
3282 at its initial offset.
3283 For all other labels, show that we don't know the offsets. */
3286 set_initial_label_offsets ()
3289 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3291 for (x = forced_labels; x; x = XEXP (x, 1))
3293 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3296 /* Set all elimination offsets to the known values for the code label given
3300 set_offsets_for_label (insn)
3304 int label_nr = CODE_LABEL_NUMBER (insn);
3305 struct elim_table *ep;
3307 num_not_at_initial_offset = 0;
3308 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3310 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3311 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3312 num_not_at_initial_offset++;
3316 /* See if anything that happened changes which eliminations are valid.
3317 For example, on the Sparc, whether or not the frame pointer can
3318 be eliminated can depend on what registers have been used. We need
3319 not check some conditions again (such as flag_omit_frame_pointer)
3320 since they can't have changed. */
3323 update_eliminables (pset)
3326 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3327 int previous_frame_pointer_needed = frame_pointer_needed;
3329 struct elim_table *ep;
3331 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3332 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3333 #ifdef ELIMINABLE_REGS
3334 || ! CAN_ELIMINATE (ep->from, ep->to)
3337 ep->can_eliminate = 0;
3339 /* Look for the case where we have discovered that we can't replace
3340 register A with register B and that means that we will now be
3341 trying to replace register A with register C. This means we can
3342 no longer replace register C with register B and we need to disable
3343 such an elimination, if it exists. This occurs often with A == ap,
3344 B == sp, and C == fp. */
3346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3348 struct elim_table *op;
3349 register int new_to = -1;
3351 if (! ep->can_eliminate && ep->can_eliminate_previous)
3353 /* Find the current elimination for ep->from, if there is a
3355 for (op = reg_eliminate;
3356 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3357 if (op->from == ep->from && op->can_eliminate)
3363 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3365 for (op = reg_eliminate;
3366 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3367 if (op->from == new_to && op->to == ep->to)
3368 op->can_eliminate = 0;
3372 /* See if any registers that we thought we could eliminate the previous
3373 time are no longer eliminable. If so, something has changed and we
3374 must spill the register. Also, recompute the number of eliminable
3375 registers and see if the frame pointer is needed; it is if there is
3376 no elimination of the frame pointer that we can perform. */
3378 frame_pointer_needed = 1;
3379 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3381 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3382 && ep->to != HARD_FRAME_POINTER_REGNUM)
3383 frame_pointer_needed = 0;
3385 if (! ep->can_eliminate && ep->can_eliminate_previous)
3387 ep->can_eliminate_previous = 0;
3388 SET_HARD_REG_BIT (*pset, ep->from);
3393 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3394 /* If we didn't need a frame pointer last time, but we do now, spill
3395 the hard frame pointer. */
3396 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3397 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3401 /* Initialize the table of registers to eliminate. */
3406 struct elim_table *ep;
3407 #ifdef ELIMINABLE_REGS
3408 struct elim_table_1 *ep1;
3412 reg_eliminate = (struct elim_table *)
3413 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3415 /* Does this function require a frame pointer? */
3417 frame_pointer_needed = (! flag_omit_frame_pointer
3418 #ifdef EXIT_IGNORE_STACK
3419 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3420 and restore sp for alloca. So we can't eliminate
3421 the frame pointer in that case. At some point,
3422 we should improve this by emitting the
3423 sp-adjusting insns for this case. */
3424 || (current_function_calls_alloca
3425 && EXIT_IGNORE_STACK)
3427 || FRAME_POINTER_REQUIRED);
3431 #ifdef ELIMINABLE_REGS
3432 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3433 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3435 ep->from = ep1->from;
3437 ep->can_eliminate = ep->can_eliminate_previous
3438 = (CAN_ELIMINATE (ep->from, ep->to)
3439 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3442 reg_eliminate[0].from = reg_eliminate_1[0].from;
3443 reg_eliminate[0].to = reg_eliminate_1[0].to;
3444 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3445 = ! frame_pointer_needed;
3448 /* Count the number of eliminable registers and build the FROM and TO
3449 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3450 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3451 We depend on this. */
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 num_eliminable += ep->can_eliminate;
3455 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3456 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3460 /* Kick all pseudos out of hard register REGNO.
3462 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3463 because we found we can't eliminate some register. In the case, no pseudos
3464 are allowed to be in the register, even if they are only in a block that
3465 doesn't require spill registers, unlike the case when we are spilling this
3466 hard reg to produce another spill register.
3468 Return nonzero if any pseudos needed to be kicked out. */
3471 spill_hard_reg (regno, cant_eliminate)
3479 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3480 regs_ever_live[regno] = 1;
3483 /* Spill every pseudo reg that was allocated to this reg
3484 or to something that overlaps this reg. */
3486 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3487 if (reg_renumber[i] >= 0
3488 && (unsigned int) reg_renumber[i] <= regno
3489 && ((unsigned int) reg_renumber[i]
3490 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3491 PSEUDO_REGNO_MODE (i))
3493 SET_REGNO_REG_SET (&spilled_pseudos, i);
3496 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3497 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3500 ior_hard_reg_set (set1, set2)
3501 HARD_REG_SET *set1, *set2;
3503 IOR_HARD_REG_SET (*set1, *set2);
3506 /* After find_reload_regs has been run for all insn that need reloads,
3507 and/or spill_hard_regs was called, this function is used to actually
3508 spill pseudo registers and try to reallocate them. It also sets up the
3509 spill_regs array for use by choose_reload_regs. */
3512 finish_spills (global)
3515 struct insn_chain *chain;
3516 int something_changed = 0;
3519 /* Build the spill_regs array for the function. */
3520 /* If there are some registers still to eliminate and one of the spill regs
3521 wasn't ever used before, additional stack space may have to be
3522 allocated to store this register. Thus, we may have changed the offset
3523 between the stack and frame pointers, so mark that something has changed.
3525 One might think that we need only set VAL to 1 if this is a call-used
3526 register. However, the set of registers that must be saved by the
3527 prologue is not identical to the call-used set. For example, the
3528 register used by the call insn for the return PC is a call-used register,
3529 but must be saved by the prologue. */
3532 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3533 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3535 spill_reg_order[i] = n_spills;
3536 spill_regs[n_spills++] = i;
3537 if (num_eliminable && ! regs_ever_live[i])
3538 something_changed = 1;
3539 regs_ever_live[i] = 1;
3542 spill_reg_order[i] = -1;
3544 EXECUTE_IF_SET_IN_REG_SET
3545 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3547 /* Record the current hard register the pseudo is allocated to in
3548 pseudo_previous_regs so we avoid reallocating it to the same
3549 hard reg in a later pass. */
3550 if (reg_renumber[i] < 0)
3553 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3554 /* Mark it as no longer having a hard register home. */
3555 reg_renumber[i] = -1;
3556 /* We will need to scan everything again. */
3557 something_changed = 1;
3560 /* Retry global register allocation if possible. */
3563 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3564 /* For every insn that needs reloads, set the registers used as spill
3565 regs in pseudo_forbidden_regs for every pseudo live across the
3567 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3569 EXECUTE_IF_SET_IN_REG_SET
3570 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3572 ior_hard_reg_set (pseudo_forbidden_regs + i,
3573 &chain->used_spill_regs);
3575 EXECUTE_IF_SET_IN_REG_SET
3576 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3578 ior_hard_reg_set (pseudo_forbidden_regs + i,
3579 &chain->used_spill_regs);
3583 /* Retry allocating the spilled pseudos. For each reg, merge the
3584 various reg sets that indicate which hard regs can't be used,
3585 and call retry_global_alloc.
3586 We change spill_pseudos here to only contain pseudos that did not
3587 get a new hard register. */
3588 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3589 if (reg_old_renumber[i] != reg_renumber[i])
3591 HARD_REG_SET forbidden;
3592 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3593 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3594 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3595 retry_global_alloc (i, forbidden);
3596 if (reg_renumber[i] >= 0)
3597 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3601 /* Fix up the register information in the insn chain.
3602 This involves deleting those of the spilled pseudos which did not get
3603 a new hard register home from the live_{before,after} sets. */
3604 for (chain = reload_insn_chain; chain; chain = chain->next)
3606 HARD_REG_SET used_by_pseudos;
3607 HARD_REG_SET used_by_pseudos2;
3609 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3610 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3612 /* Mark any unallocated hard regs as available for spills. That
3613 makes inheritance work somewhat better. */
3614 if (chain->need_reload)
3616 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3617 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3618 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3620 /* Save the old value for the sanity test below. */
3621 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3623 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3624 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3625 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3626 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3628 /* Make sure we only enlarge the set. */
3629 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3635 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3636 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3638 int regno = reg_renumber[i];
3639 if (reg_old_renumber[i] == regno)
3642 alter_reg (i, reg_old_renumber[i]);
3643 reg_old_renumber[i] = regno;
3647 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3649 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3650 i, reg_renumber[i]);
3654 return something_changed;
3657 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3658 Also mark any hard registers used to store user variables as
3659 forbidden from being used for spill registers. */
3662 scan_paradoxical_subregs (x)
3666 register const char *fmt;
3667 register enum rtx_code code = GET_CODE (x);
3673 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3674 && REG_USERVAR_P (x))
3675 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3691 if (GET_CODE (SUBREG_REG (x)) == REG
3692 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3693 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3694 = GET_MODE_SIZE (GET_MODE (x));
3701 fmt = GET_RTX_FORMAT (code);
3702 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3705 scan_paradoxical_subregs (XEXP (x, i));
3706 else if (fmt[i] == 'E')
3709 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3710 scan_paradoxical_subregs (XVECEXP (x, i, j));
3715 /* Reload pseudo-registers into hard regs around each insn as needed.
3716 Additional register load insns are output before the insn that needs it
3717 and perhaps store insns after insns that modify the reloaded pseudo reg.
3719 reg_last_reload_reg and reg_reloaded_contents keep track of
3720 which registers are already available in reload registers.
3721 We update these for the reloads that we perform,
3722 as the insns are scanned. */
3725 reload_as_needed (live_known)
3728 struct insn_chain *chain;
3729 #if defined (AUTO_INC_DEC)
3734 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3735 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3736 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3737 reg_has_output_reload = (char *) xmalloc (max_regno);
3738 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3740 set_initial_elim_offsets ();
3742 for (chain = reload_insn_chain; chain; chain = chain->next)
3745 rtx insn = chain->insn;
3746 rtx old_next = NEXT_INSN (insn);
3748 /* If we pass a label, copy the offsets from the label information
3749 into the current offsets of each elimination. */
3750 if (GET_CODE (insn) == CODE_LABEL)
3751 set_offsets_for_label (insn);
3753 else if (INSN_P (insn))
3755 rtx oldpat = PATTERN (insn);
3757 /* If this is a USE and CLOBBER of a MEM, ensure that any
3758 references to eliminable registers have been removed. */
3760 if ((GET_CODE (PATTERN (insn)) == USE
3761 || GET_CODE (PATTERN (insn)) == CLOBBER)
3762 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3763 XEXP (XEXP (PATTERN (insn), 0), 0)
3764 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3765 GET_MODE (XEXP (PATTERN (insn), 0)),
3768 /* If we need to do register elimination processing, do so.
3769 This might delete the insn, in which case we are done. */
3770 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3772 eliminate_regs_in_insn (insn, 1);
3773 if (GET_CODE (insn) == NOTE)
3775 update_eliminable_offsets ();
3780 /* If need_elim is nonzero but need_reload is zero, one might think
3781 that we could simply set n_reloads to 0. However, find_reloads
3782 could have done some manipulation of the insn (such as swapping
3783 commutative operands), and these manipulations are lost during
3784 the first pass for every insn that needs register elimination.
3785 So the actions of find_reloads must be redone here. */
3787 if (! chain->need_elim && ! chain->need_reload
3788 && ! chain->need_operand_change)
3790 /* First find the pseudo regs that must be reloaded for this insn.
3791 This info is returned in the tables reload_... (see reload.h).
3792 Also modify the body of INSN by substituting RELOAD
3793 rtx's for those pseudo regs. */
3796 memset (reg_has_output_reload, 0, max_regno);
3797 CLEAR_HARD_REG_SET (reg_is_output_reload);
3799 find_reloads (insn, 1, spill_indirect_levels, live_known,
3803 if (num_eliminable && chain->need_elim)
3804 update_eliminable_offsets ();
3808 rtx next = NEXT_INSN (insn);
3811 prev = PREV_INSN (insn);
3813 /* Now compute which reload regs to reload them into. Perhaps
3814 reusing reload regs from previous insns, or else output
3815 load insns to reload them. Maybe output store insns too.
3816 Record the choices of reload reg in reload_reg_rtx. */
3817 choose_reload_regs (chain);
3819 /* Merge any reloads that we didn't combine for fear of
3820 increasing the number of spill registers needed but now
3821 discover can be safely merged. */
3822 if (SMALL_REGISTER_CLASSES)
3823 merge_assigned_reloads (insn);
3825 /* Generate the insns to reload operands into or out of
3826 their reload regs. */
3827 emit_reload_insns (chain);
3829 /* Substitute the chosen reload regs from reload_reg_rtx
3830 into the insn's body (or perhaps into the bodies of other
3831 load and store insn that we just made for reloading
3832 and that we moved the structure into). */
3835 /* If this was an ASM, make sure that all the reload insns
3836 we have generated are valid. If not, give an error
3839 if (asm_noperands (PATTERN (insn)) >= 0)
3840 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3841 if (p != insn && INSN_P (p)
3842 && (recog_memoized (p) < 0
3843 || (extract_insn (p), ! constrain_operands (1))))
3845 error_for_asm (insn,
3846 "`asm' operand requires impossible reload");
3848 NOTE_SOURCE_FILE (p) = 0;
3849 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3852 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3853 is no longer validly lying around to save a future reload.
3854 Note that this does not detect pseudos that were reloaded
3855 for this insn in order to be stored in
3856 (obeying register constraints). That is correct; such reload
3857 registers ARE still valid. */
3858 note_stores (oldpat, forget_old_reloads_1, NULL);
3860 /* There may have been CLOBBER insns placed after INSN. So scan
3861 between INSN and NEXT and use them to forget old reloads. */
3862 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3863 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3864 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3867 /* Likewise for regs altered by auto-increment in this insn.
3868 REG_INC notes have been changed by reloading:
3869 find_reloads_address_1 records substitutions for them,
3870 which have been performed by subst_reloads above. */
3871 for (i = n_reloads - 1; i >= 0; i--)
3873 rtx in_reg = rld[i].in_reg;
3876 enum rtx_code code = GET_CODE (in_reg);
3877 /* PRE_INC / PRE_DEC will have the reload register ending up
3878 with the same value as the stack slot, but that doesn't
3879 hold true for POST_INC / POST_DEC. Either we have to
3880 convert the memory access to a true POST_INC / POST_DEC,
3881 or we can't use the reload register for inheritance. */
3882 if ((code == POST_INC || code == POST_DEC)
3883 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3884 REGNO (rld[i].reg_rtx))
3885 /* Make sure it is the inc/dec pseudo, and not
3886 some other (e.g. output operand) pseudo. */
3887 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3888 == REGNO (XEXP (in_reg, 0))))
3891 rtx reload_reg = rld[i].reg_rtx;
3892 enum machine_mode mode = GET_MODE (reload_reg);
3896 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3898 /* We really want to ignore REG_INC notes here, so
3899 use PATTERN (p) as argument to reg_set_p . */
3900 if (reg_set_p (reload_reg, PATTERN (p)))
3902 n = count_occurrences (PATTERN (p), reload_reg, 0);
3907 n = validate_replace_rtx (reload_reg,
3908 gen_rtx (code, mode,
3912 /* We must also verify that the constraints
3913 are met after the replacement. */
3916 n = constrain_operands (1);
3920 /* If the constraints were not met, then
3921 undo the replacement. */
3924 validate_replace_rtx (gen_rtx (code, mode,
3936 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3938 /* Mark this as having an output reload so that the
3939 REG_INC processing code below won't invalidate
3940 the reload for inheritance. */
3941 SET_HARD_REG_BIT (reg_is_output_reload,
3942 REGNO (reload_reg));
3943 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3946 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3949 else if ((code == PRE_INC || code == PRE_DEC)
3950 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3951 REGNO (rld[i].reg_rtx))
3952 /* Make sure it is the inc/dec pseudo, and not
3953 some other (e.g. output operand) pseudo. */
3954 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3955 == REGNO (XEXP (in_reg, 0))))
3957 SET_HARD_REG_BIT (reg_is_output_reload,
3958 REGNO (rld[i].reg_rtx));
3959 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3963 /* If a pseudo that got a hard register is auto-incremented,
3964 we must purge records of copying it into pseudos without
3966 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3967 if (REG_NOTE_KIND (x) == REG_INC)
3969 /* See if this pseudo reg was reloaded in this insn.
3970 If so, its last-reload info is still valid
3971 because it is based on this insn's reload. */
3972 for (i = 0; i < n_reloads; i++)
3973 if (rld[i].out == XEXP (x, 0))
3977 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3981 /* A reload reg's contents are unknown after a label. */
3982 if (GET_CODE (insn) == CODE_LABEL)
3983 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3985 /* Don't assume a reload reg is still good after a call insn
3986 if it is a call-used reg. */
3987 else if (GET_CODE (insn) == CALL_INSN)
3988 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3992 free (reg_last_reload_reg);
3993 free (reg_has_output_reload);
3996 /* Discard all record of any value reloaded from X,
3997 or reloaded in X from someplace else;
3998 unless X is an output reload reg of the current insn.
4000 X may be a hard reg (the reload reg)
4001 or it may be a pseudo reg that was reloaded from. */
4004 forget_old_reloads_1 (x, ignored, data)
4006 rtx ignored ATTRIBUTE_UNUSED;
4007 void *data ATTRIBUTE_UNUSED;
4013 /* note_stores does give us subregs of hard regs. */
4014 while (GET_CODE (x) == SUBREG)
4016 offset += SUBREG_WORD (x);
4020 if (GET_CODE (x) != REG)
4023 regno = REGNO (x) + offset;
4025 if (regno >= FIRST_PSEUDO_REGISTER)
4031 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4032 /* Storing into a spilled-reg invalidates its contents.
4033 This can happen if a block-local pseudo is allocated to that reg
4034 and it wasn't spilled because this block's total need is 0.
4035 Then some insn might have an optional reload and use this reg. */
4036 for (i = 0; i < nr; i++)
4037 /* But don't do this if the reg actually serves as an output
4038 reload reg in the current instruction. */
4040 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4042 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4043 spill_reg_store[regno + i] = 0;
4047 /* Since value of X has changed,
4048 forget any value previously copied from it. */
4051 /* But don't forget a copy if this is the output reload
4052 that establishes the copy's validity. */
4053 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4054 reg_last_reload_reg[regno + nr] = 0;
4057 /* The following HARD_REG_SETs indicate when each hard register is
4058 used for a reload of various parts of the current insn. */
4060 /* If reg is unavailable for all reloads. */
4061 static HARD_REG_SET reload_reg_unavailable;
4062 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4063 static HARD_REG_SET reload_reg_used;
4064 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4065 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4066 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4067 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4068 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4069 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4070 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4071 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4072 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4073 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4074 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4075 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4076 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4077 static HARD_REG_SET reload_reg_used_in_op_addr;
4078 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4079 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4080 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4081 static HARD_REG_SET reload_reg_used_in_insn;
4082 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4083 static HARD_REG_SET reload_reg_used_in_other_addr;
4085 /* If reg is in use as a reload reg for any sort of reload. */
4086 static HARD_REG_SET reload_reg_used_at_all;
4088 /* If reg is use as an inherited reload. We just mark the first register
4090 static HARD_REG_SET reload_reg_used_for_inherit;
4092 /* Records which hard regs are used in any way, either as explicit use or
4093 by being allocated to a pseudo during any point of the current insn. */
4094 static HARD_REG_SET reg_used_in_insn;
4096 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4097 TYPE. MODE is used to indicate how many consecutive regs are
4101 mark_reload_reg_in_use (regno, opnum, type, mode)
4104 enum reload_type type;
4105 enum machine_mode mode;
4107 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4110 for (i = regno; i < nregs + regno; i++)
4115 SET_HARD_REG_BIT (reload_reg_used, i);
4118 case RELOAD_FOR_INPUT_ADDRESS:
4119 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4122 case RELOAD_FOR_INPADDR_ADDRESS:
4123 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4126 case RELOAD_FOR_OUTPUT_ADDRESS:
4127 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4130 case RELOAD_FOR_OUTADDR_ADDRESS:
4131 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4134 case RELOAD_FOR_OPERAND_ADDRESS:
4135 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4138 case RELOAD_FOR_OPADDR_ADDR:
4139 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4142 case RELOAD_FOR_OTHER_ADDRESS:
4143 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4146 case RELOAD_FOR_INPUT:
4147 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4150 case RELOAD_FOR_OUTPUT:
4151 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4154 case RELOAD_FOR_INSN:
4155 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4159 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4163 /* Similarly, but show REGNO is no longer in use for a reload. */
4166 clear_reload_reg_in_use (regno, opnum, type, mode)
4169 enum reload_type type;
4170 enum machine_mode mode;
4172 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4173 unsigned int start_regno, end_regno, r;
4175 /* A complication is that for some reload types, inheritance might
4176 allow multiple reloads of the same types to share a reload register.
4177 We set check_opnum if we have to check only reloads with the same
4178 operand number, and check_any if we have to check all reloads. */
4179 int check_opnum = 0;
4181 HARD_REG_SET *used_in_set;
4186 used_in_set = &reload_reg_used;
4189 case RELOAD_FOR_INPUT_ADDRESS:
4190 used_in_set = &reload_reg_used_in_input_addr[opnum];
4193 case RELOAD_FOR_INPADDR_ADDRESS:
4195 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4198 case RELOAD_FOR_OUTPUT_ADDRESS:
4199 used_in_set = &reload_reg_used_in_output_addr[opnum];
4202 case RELOAD_FOR_OUTADDR_ADDRESS:
4204 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4207 case RELOAD_FOR_OPERAND_ADDRESS:
4208 used_in_set = &reload_reg_used_in_op_addr;
4211 case RELOAD_FOR_OPADDR_ADDR:
4213 used_in_set = &reload_reg_used_in_op_addr_reload;
4216 case RELOAD_FOR_OTHER_ADDRESS:
4217 used_in_set = &reload_reg_used_in_other_addr;
4221 case RELOAD_FOR_INPUT:
4222 used_in_set = &reload_reg_used_in_input[opnum];
4225 case RELOAD_FOR_OUTPUT:
4226 used_in_set = &reload_reg_used_in_output[opnum];
4229 case RELOAD_FOR_INSN:
4230 used_in_set = &reload_reg_used_in_insn;
4235 /* We resolve conflicts with remaining reloads of the same type by
4236 excluding the intervals of of reload registers by them from the
4237 interval of freed reload registers. Since we only keep track of
4238 one set of interval bounds, we might have to exclude somewhat
4239 more then what would be necessary if we used a HARD_REG_SET here.
4240 But this should only happen very infrequently, so there should
4241 be no reason to worry about it. */
4243 start_regno = regno;
4244 end_regno = regno + nregs;
4245 if (check_opnum || check_any)
4247 for (i = n_reloads - 1; i >= 0; i--)
4249 if (rld[i].when_needed == type
4250 && (check_any || rld[i].opnum == opnum)
4253 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4254 unsigned int conflict_end
4256 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4258 /* If there is an overlap with the first to-be-freed register,
4259 adjust the interval start. */
4260 if (conflict_start <= start_regno && conflict_end > start_regno)
4261 start_regno = conflict_end;
4262 /* Otherwise, if there is a conflict with one of the other
4263 to-be-freed registers, adjust the interval end. */
4264 if (conflict_start > start_regno && conflict_start < end_regno)
4265 end_regno = conflict_start;
4270 for (r = start_regno; r < end_regno; r++)
4271 CLEAR_HARD_REG_BIT (*used_in_set, r);
4274 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4275 specified by OPNUM and TYPE. */
4278 reload_reg_free_p (regno, opnum, type)
4281 enum reload_type type;
4285 /* In use for a RELOAD_OTHER means it's not available for anything. */
4286 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4287 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4293 /* In use for anything means we can't use it for RELOAD_OTHER. */
4294 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4295 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4296 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4299 for (i = 0; i < reload_n_operands; i++)
4300 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4301 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4302 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4303 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4304 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4305 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4310 case RELOAD_FOR_INPUT:
4311 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4312 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4315 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4318 /* If it is used for some other input, can't use it. */
4319 for (i = 0; i < reload_n_operands; i++)
4320 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4323 /* If it is used in a later operand's address, can't use it. */
4324 for (i = opnum + 1; i < reload_n_operands; i++)
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4326 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4331 case RELOAD_FOR_INPUT_ADDRESS:
4332 /* Can't use a register if it is used for an input address for this
4333 operand or used as an input in an earlier one. */
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4335 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4338 for (i = 0; i < opnum; i++)
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4344 case RELOAD_FOR_INPADDR_ADDRESS:
4345 /* Can't use a register if it is used for an input address
4346 for this operand or used as an input in an earlier
4348 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4351 for (i = 0; i < opnum; i++)
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4357 case RELOAD_FOR_OUTPUT_ADDRESS:
4358 /* Can't use a register if it is used for an output address for this
4359 operand or used as an output in this or a later operand. */
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4363 for (i = opnum; i < reload_n_operands; i++)
4364 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4369 case RELOAD_FOR_OUTADDR_ADDRESS:
4370 /* Can't use a register if it is used for an output address
4371 for this operand or used as an output in this or a
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4376 for (i = opnum; i < reload_n_operands; i++)
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4382 case RELOAD_FOR_OPERAND_ADDRESS:
4383 for (i = 0; i < reload_n_operands; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4387 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4388 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4390 case RELOAD_FOR_OPADDR_ADDR:
4391 for (i = 0; i < reload_n_operands; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4395 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4397 case RELOAD_FOR_OUTPUT:
4398 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4399 outputs, or an operand address for this or an earlier output. */
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4403 for (i = 0; i < reload_n_operands; i++)
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4407 for (i = 0; i <= opnum; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4414 case RELOAD_FOR_INSN:
4415 for (i = 0; i < reload_n_operands; i++)
4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4417 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4420 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4421 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4423 case RELOAD_FOR_OTHER_ADDRESS:
4424 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4429 /* Return 1 if the value in reload reg REGNO, as used by a reload
4430 needed for the part of the insn specified by OPNUM and TYPE,
4431 is still available in REGNO at the end of the insn.
4433 We can assume that the reload reg was already tested for availability
4434 at the time it is needed, and we should not check this again,
4435 in case the reg has already been marked in use. */
4438 reload_reg_reaches_end_p (regno, opnum, type)
4441 enum reload_type type;
4448 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4449 its value must reach the end. */
4452 /* If this use is for part of the insn,
4453 its value reaches if no subsequent part uses the same register.
4454 Just like the above function, don't try to do this with lots
4457 case RELOAD_FOR_OTHER_ADDRESS:
4458 /* Here we check for everything else, since these don't conflict
4459 with anything else and everything comes later. */
4461 for (i = 0; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4470 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4471 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4472 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4474 case RELOAD_FOR_INPUT_ADDRESS:
4475 case RELOAD_FOR_INPADDR_ADDRESS:
4476 /* Similar, except that we check only for this and subsequent inputs
4477 and the address of only subsequent inputs and we do not need
4478 to check for RELOAD_OTHER objects since they are known not to
4481 for (i = opnum; i < reload_n_operands; i++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4485 for (i = opnum + 1; i < reload_n_operands; i++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4490 for (i = 0; i < reload_n_operands; i++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4492 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4499 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4500 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4501 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4503 case RELOAD_FOR_INPUT:
4504 /* Similar to input address, except we start at the next operand for
4505 both input and input address and we do not check for
4506 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4509 for (i = opnum + 1; i < reload_n_operands; i++)
4510 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4511 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4512 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4515 /* ... fall through ... */
4517 case RELOAD_FOR_OPERAND_ADDRESS:
4518 /* Check outputs and their addresses. */
4520 for (i = 0; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4526 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4528 case RELOAD_FOR_OPADDR_ADDR:
4529 for (i = 0; i < reload_n_operands; i++)
4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4535 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4536 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4537 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4539 case RELOAD_FOR_INSN:
4540 /* These conflict with other outputs with RELOAD_OTHER. So
4541 we need only check for output addresses. */
4545 /* ... fall through ... */
4547 case RELOAD_FOR_OUTPUT:
4548 case RELOAD_FOR_OUTPUT_ADDRESS:
4549 case RELOAD_FOR_OUTADDR_ADDRESS:
4550 /* We already know these can't conflict with a later output. So the
4551 only thing to check are later output addresses. */
4552 for (i = opnum + 1; i < reload_n_operands; i++)
4553 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4563 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4566 This function uses the same algorithm as reload_reg_free_p above. */
4569 reloads_conflict (r1, r2)
4572 enum reload_type r1_type = rld[r1].when_needed;
4573 enum reload_type r2_type = rld[r2].when_needed;
4574 int r1_opnum = rld[r1].opnum;
4575 int r2_opnum = rld[r2].opnum;
4577 /* RELOAD_OTHER conflicts with everything. */
4578 if (r2_type == RELOAD_OTHER)
4581 /* Otherwise, check conflicts differently for each type. */
4585 case RELOAD_FOR_INPUT:
4586 return (r2_type == RELOAD_FOR_INSN
4587 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4588 || r2_type == RELOAD_FOR_OPADDR_ADDR
4589 || r2_type == RELOAD_FOR_INPUT
4590 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4591 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4592 && r2_opnum > r1_opnum));
4594 case RELOAD_FOR_INPUT_ADDRESS:
4595 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4596 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4598 case RELOAD_FOR_INPADDR_ADDRESS:
4599 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4600 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4602 case RELOAD_FOR_OUTPUT_ADDRESS:
4603 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4604 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4606 case RELOAD_FOR_OUTADDR_ADDRESS:
4607 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4608 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4610 case RELOAD_FOR_OPERAND_ADDRESS:
4611 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4612 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4614 case RELOAD_FOR_OPADDR_ADDR:
4615 return (r2_type == RELOAD_FOR_INPUT
4616 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4618 case RELOAD_FOR_OUTPUT:
4619 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4620 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4621 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4622 && r2_opnum <= r1_opnum));
4624 case RELOAD_FOR_INSN:
4625 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4626 || r2_type == RELOAD_FOR_INSN
4627 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4629 case RELOAD_FOR_OTHER_ADDRESS:
4630 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4640 /* Indexed by reload number, 1 if incoming value
4641 inherited from previous insns. */
4642 char reload_inherited[MAX_RELOADS];
4644 /* For an inherited reload, this is the insn the reload was inherited from,
4645 if we know it. Otherwise, this is 0. */
4646 rtx reload_inheritance_insn[MAX_RELOADS];
4648 /* If non-zero, this is a place to get the value of the reload,
4649 rather than using reload_in. */
4650 rtx reload_override_in[MAX_RELOADS];
4652 /* For each reload, the hard register number of the register used,
4653 or -1 if we did not need a register for this reload. */
4654 int reload_spill_index[MAX_RELOADS];
4656 /* Subroutine of free_for_value_p, used to check a single register. */
4659 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4660 ignore_address_reloads)
4663 enum reload_type type;
4666 int ignore_address_reloads;
4669 /* Set if we see an input reload that must not share its reload register
4670 with any new earlyclobber, but might otherwise share the reload
4671 register with an output or input-output reload. */
4672 int check_earlyclobber = 0;
4676 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4679 if (out == const0_rtx)
4685 /* We use some pseudo 'time' value to check if the lifetimes of the
4686 new register use would overlap with the one of a previous reload
4687 that is not read-only or uses a different value.
4688 The 'time' used doesn't have to be linear in any shape or form, just
4690 Some reload types use different 'buckets' for each operand.
4691 So there are MAX_RECOG_OPERANDS different time values for each
4693 We compute TIME1 as the time when the register for the prospective
4694 new reload ceases to be live, and TIME2 for each existing
4695 reload as the time when that the reload register of that reload
4697 Where there is little to be gained by exact lifetime calculations,
4698 we just make conservative assumptions, i.e. a longer lifetime;
4699 this is done in the 'default:' cases. */
4702 case RELOAD_FOR_OTHER_ADDRESS:
4703 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4704 time1 = copy ? 0 : 1;
4707 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4709 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4710 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4711 respectively, to the time values for these, we get distinct time
4712 values. To get distinct time values for each operand, we have to
4713 multiply opnum by at least three. We round that up to four because
4714 multiply by four is often cheaper. */
4715 case RELOAD_FOR_INPADDR_ADDRESS:
4716 time1 = opnum * 4 + 2;
4718 case RELOAD_FOR_INPUT_ADDRESS:
4719 time1 = opnum * 4 + 3;
4721 case RELOAD_FOR_INPUT:
4722 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4723 executes (inclusive). */
4724 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4726 case RELOAD_FOR_OPADDR_ADDR:
4728 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4729 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4731 case RELOAD_FOR_OPERAND_ADDRESS:
4732 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4734 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4736 case RELOAD_FOR_OUTADDR_ADDRESS:
4737 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4739 case RELOAD_FOR_OUTPUT_ADDRESS:
4740 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4743 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4746 for (i = 0; i < n_reloads; i++)
4748 rtx reg = rld[i].reg_rtx;
4749 if (reg && GET_CODE (reg) == REG
4750 && ((unsigned) regno - true_regnum (reg)
4751 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4754 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4755 || rld[i].out || out)
4758 switch (rld[i].when_needed)
4760 case RELOAD_FOR_OTHER_ADDRESS:
4763 case RELOAD_FOR_INPADDR_ADDRESS:
4764 /* find_reloads makes sure that a
4765 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4766 by at most one - the first -
4767 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4768 address reload is inherited, the address address reload
4769 goes away, so we can ignore this conflict. */
4770 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4771 && ignore_address_reloads
4772 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4773 Then the address address is still needed to store
4774 back the new address. */
4775 && ! rld[reloadnum].out)
4777 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4778 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4780 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4781 && ignore_address_reloads
4782 /* Unless we are reloading an auto_inc expression. */
4783 && ! rld[reloadnum].out)
4785 time2 = rld[i].opnum * 4 + 2;
4787 case RELOAD_FOR_INPUT_ADDRESS:
4788 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4789 && ignore_address_reloads
4790 && ! rld[reloadnum].out)
4792 time2 = rld[i].opnum * 4 + 3;
4794 case RELOAD_FOR_INPUT:
4795 time2 = rld[i].opnum * 4 + 4;
4796 check_earlyclobber = 1;
4798 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4799 == MAX_RECOG_OPERAND * 4 */
4800 case RELOAD_FOR_OPADDR_ADDR:
4801 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4802 && ignore_address_reloads
4803 && ! rld[reloadnum].out)
4805 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4807 case RELOAD_FOR_OPERAND_ADDRESS:
4808 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4809 check_earlyclobber = 1;
4811 case RELOAD_FOR_INSN:
4812 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4814 case RELOAD_FOR_OUTPUT:
4815 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4816 instruction is executed. */
4817 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4819 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4820 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4822 case RELOAD_FOR_OUTADDR_ADDRESS:
4823 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4824 && ignore_address_reloads
4825 && ! rld[reloadnum].out)
4827 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4829 case RELOAD_FOR_OUTPUT_ADDRESS:
4830 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4833 /* If there is no conflict in the input part, handle this
4834 like an output reload. */
4835 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4837 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4838 /* Earlyclobbered outputs must conflict with inputs. */
4839 if (earlyclobber_operand_p (rld[i].out))
4840 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4845 /* RELOAD_OTHER might be live beyond instruction execution,
4846 but this is not obvious when we set time2 = 1. So check
4847 here if there might be a problem with the new reload
4848 clobbering the register used by the RELOAD_OTHER. */
4856 && (! rld[i].in || rld[i].out
4857 || ! rtx_equal_p (rld[i].in, value)))
4858 || (out && rld[reloadnum].out_reg
4859 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4865 /* Earlyclobbered outputs must conflict with inputs. */
4866 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4872 /* Return 1 if the value in reload reg REGNO, as used by a reload
4873 needed for the part of the insn specified by OPNUM and TYPE,
4874 may be used to load VALUE into it.
4876 MODE is the mode in which the register is used, this is needed to
4877 determine how many hard regs to test.
4879 Other read-only reloads with the same value do not conflict
4880 unless OUT is non-zero and these other reloads have to live while
4881 output reloads live.
4882 If OUT is CONST0_RTX, this is a special case: it means that the
4883 test should not be for using register REGNO as reload register, but
4884 for copying from register REGNO into the reload register.
4886 RELOADNUM is the number of the reload we want to load this value for;
4887 a reload does not conflict with itself.
4889 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4890 reloads that load an address for the very reload we are considering.
4892 The caller has to make sure that there is no conflict with the return
4896 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4897 ignore_address_reloads)
4899 enum machine_mode mode;
4901 enum reload_type type;
4904 int ignore_address_reloads;
4906 int nregs = HARD_REGNO_NREGS (regno, mode);
4908 if (! reload_reg_free_for_value_p (regno + nregs, opnum, type, value, out,
4909 reloadnum, ignore_address_reloads))
4914 /* Determine whether the reload reg X overlaps any rtx'es used for
4915 overriding inheritance. Return nonzero if so. */
4918 conflicts_with_override (x)
4922 for (i = 0; i < n_reloads; i++)
4923 if (reload_override_in[i]
4924 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4929 /* Give an error message saying we failed to find a reload for INSN,
4930 and clear out reload R. */
4932 failed_reload (insn, r)
4936 if (asm_noperands (PATTERN (insn)) < 0)
4937 /* It's the compiler's fault. */
4938 fatal_insn ("Could not find a spill register", insn);
4940 /* It's the user's fault; the operand's mode and constraint
4941 don't match. Disable this reload so we don't crash in final. */
4942 error_for_asm (insn,
4943 "`asm' operand constraint incompatible with operand size");
4947 rld[r].optional = 1;
4948 rld[r].secondary_p = 1;
4951 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4952 for reload R. If it's valid, get an rtx for it. Return nonzero if
4955 set_reload_reg (i, r)
4959 rtx reg = spill_reg_rtx[i];
4961 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4962 spill_reg_rtx[i] = reg
4963 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4965 regno = true_regnum (reg);
4967 /* Detect when the reload reg can't hold the reload mode.
4968 This used to be one `if', but Sequent compiler can't handle that. */
4969 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4971 enum machine_mode test_mode = VOIDmode;
4973 test_mode = GET_MODE (rld[r].in);
4974 /* If rld[r].in has VOIDmode, it means we will load it
4975 in whatever mode the reload reg has: to wit, rld[r].mode.
4976 We have already tested that for validity. */
4977 /* Aside from that, we need to test that the expressions
4978 to reload from or into have modes which are valid for this
4979 reload register. Otherwise the reload insns would be invalid. */
4980 if (! (rld[r].in != 0 && test_mode != VOIDmode
4981 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4982 if (! (rld[r].out != 0
4983 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4985 /* The reg is OK. */
4988 /* Mark as in use for this insn the reload regs we use
4990 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4991 rld[r].when_needed, rld[r].mode);
4993 rld[r].reg_rtx = reg;
4994 reload_spill_index[r] = spill_regs[i];
5001 /* Find a spill register to use as a reload register for reload R.
5002 LAST_RELOAD is non-zero if this is the last reload for the insn being
5005 Set rld[R].reg_rtx to the register allocated.
5007 We return 1 if successful, or 0 if we couldn't find a spill reg and
5008 we didn't change anything. */
5011 allocate_reload_reg (chain, r, last_reload)
5012 struct insn_chain *chain ATTRIBUTE_UNUSED;
5018 /* If we put this reload ahead, thinking it is a group,
5019 then insist on finding a group. Otherwise we can grab a
5020 reg that some other reload needs.
5021 (That can happen when we have a 68000 DATA_OR_FP_REG
5022 which is a group of data regs or one fp reg.)
5023 We need not be so restrictive if there are no more reloads
5026 ??? Really it would be nicer to have smarter handling
5027 for that kind of reg class, where a problem like this is normal.
5028 Perhaps those classes should be avoided for reloading
5029 by use of more alternatives. */
5031 int force_group = rld[r].nregs > 1 && ! last_reload;
5033 /* If we want a single register and haven't yet found one,
5034 take any reg in the right class and not in use.
5035 If we want a consecutive group, here is where we look for it.
5037 We use two passes so we can first look for reload regs to
5038 reuse, which are already in use for other reloads in this insn,
5039 and only then use additional registers.
5040 I think that maximizing reuse is needed to make sure we don't
5041 run out of reload regs. Suppose we have three reloads, and
5042 reloads A and B can share regs. These need two regs.
5043 Suppose A and B are given different regs.
5044 That leaves none for C. */
5045 for (pass = 0; pass < 2; pass++)
5047 /* I is the index in spill_regs.
5048 We advance it round-robin between insns to use all spill regs
5049 equally, so that inherited reloads have a chance
5050 of leapfrogging each other. */
5054 for (count = 0; count < n_spills; count++)
5056 int class = (int) rld[r].class;
5062 regnum = spill_regs[i];
5064 if ((reload_reg_free_p (regnum, rld[r].opnum,
5067 /* We check reload_reg_used to make sure we
5068 don't clobber the return register. */
5069 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5070 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5071 rld[r].when_needed, rld[r].in,
5073 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5074 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5075 /* Look first for regs to share, then for unshared. But
5076 don't share regs used for inherited reloads; they are
5077 the ones we want to preserve. */
5079 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5081 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5084 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5085 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5086 (on 68000) got us two FP regs. If NR is 1,
5087 we would reject both of them. */
5090 /* If we need only one reg, we have already won. */
5093 /* But reject a single reg if we demand a group. */
5098 /* Otherwise check that as many consecutive regs as we need
5099 are available here. */
5102 int regno = regnum + nr - 1;
5103 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5104 && spill_reg_order[regno] >= 0
5105 && reload_reg_free_p (regno, rld[r].opnum,
5106 rld[r].when_needed)))
5115 /* If we found something on pass 1, omit pass 2. */
5116 if (count < n_spills)
5120 /* We should have found a spill register by now. */
5121 if (count >= n_spills)
5124 /* I is the index in SPILL_REG_RTX of the reload register we are to
5125 allocate. Get an rtx for it and find its register number. */
5127 return set_reload_reg (i, r);
5130 /* Initialize all the tables needed to allocate reload registers.
5131 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5132 is the array we use to restore the reg_rtx field for every reload. */
5135 choose_reload_regs_init (chain, save_reload_reg_rtx)
5136 struct insn_chain *chain;
5137 rtx *save_reload_reg_rtx;
5141 for (i = 0; i < n_reloads; i++)
5142 rld[i].reg_rtx = save_reload_reg_rtx[i];
5144 memset (reload_inherited, 0, MAX_RELOADS);
5145 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5146 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5148 CLEAR_HARD_REG_SET (reload_reg_used);
5149 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5150 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5151 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5152 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5153 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5155 CLEAR_HARD_REG_SET (reg_used_in_insn);
5158 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5159 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5160 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5161 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5162 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5163 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5166 for (i = 0; i < reload_n_operands; i++)
5168 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5169 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5170 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5171 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5172 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5173 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5176 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5178 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5180 for (i = 0; i < n_reloads; i++)
5181 /* If we have already decided to use a certain register,
5182 don't use it in another way. */
5184 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5185 rld[i].when_needed, rld[i].mode);
5188 /* Assign hard reg targets for the pseudo-registers we must reload
5189 into hard regs for this insn.
5190 Also output the instructions to copy them in and out of the hard regs.
5192 For machines with register classes, we are responsible for
5193 finding a reload reg in the proper class. */
5196 choose_reload_regs (chain)
5197 struct insn_chain *chain;
5199 rtx insn = chain->insn;
5201 unsigned int max_group_size = 1;
5202 enum reg_class group_class = NO_REGS;
5203 int pass, win, inheritance;
5205 rtx save_reload_reg_rtx[MAX_RELOADS];
5207 /* In order to be certain of getting the registers we need,
5208 we must sort the reloads into order of increasing register class.
5209 Then our grabbing of reload registers will parallel the process
5210 that provided the reload registers.
5212 Also note whether any of the reloads wants a consecutive group of regs.
5213 If so, record the maximum size of the group desired and what
5214 register class contains all the groups needed by this insn. */
5216 for (j = 0; j < n_reloads; j++)
5218 reload_order[j] = j;
5219 reload_spill_index[j] = -1;
5221 if (rld[j].nregs > 1)
5223 max_group_size = MAX (rld[j].nregs, max_group_size);
5225 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5228 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5232 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5234 /* If -O, try first with inheritance, then turning it off.
5235 If not -O, don't do inheritance.
5236 Using inheritance when not optimizing leads to paradoxes
5237 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5238 because one side of the comparison might be inherited. */
5240 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5242 choose_reload_regs_init (chain, save_reload_reg_rtx);
5244 /* Process the reloads in order of preference just found.
5245 Beyond this point, subregs can be found in reload_reg_rtx.
5247 This used to look for an existing reloaded home for all of the
5248 reloads, and only then perform any new reloads. But that could lose
5249 if the reloads were done out of reg-class order because a later
5250 reload with a looser constraint might have an old home in a register
5251 needed by an earlier reload with a tighter constraint.
5253 To solve this, we make two passes over the reloads, in the order
5254 described above. In the first pass we try to inherit a reload
5255 from a previous insn. If there is a later reload that needs a
5256 class that is a proper subset of the class being processed, we must
5257 also allocate a spill register during the first pass.
5259 Then make a second pass over the reloads to allocate any reloads
5260 that haven't been given registers yet. */
5262 for (j = 0; j < n_reloads; j++)
5264 register int r = reload_order[j];
5265 rtx search_equiv = NULL_RTX;
5267 /* Ignore reloads that got marked inoperative. */
5268 if (rld[r].out == 0 && rld[r].in == 0
5269 && ! rld[r].secondary_p)
5272 /* If find_reloads chose to use reload_in or reload_out as a reload
5273 register, we don't need to chose one. Otherwise, try even if it
5274 found one since we might save an insn if we find the value lying
5276 Try also when reload_in is a pseudo without a hard reg. */
5277 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5278 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5279 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5280 && GET_CODE (rld[r].in) != MEM
5281 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5284 #if 0 /* No longer needed for correct operation.
5285 It might give better code, or might not; worth an experiment? */
5286 /* If this is an optional reload, we can't inherit from earlier insns
5287 until we are sure that any non-optional reloads have been allocated.
5288 The following code takes advantage of the fact that optional reloads
5289 are at the end of reload_order. */
5290 if (rld[r].optional != 0)
5291 for (i = 0; i < j; i++)
5292 if ((rld[reload_order[i]].out != 0
5293 || rld[reload_order[i]].in != 0
5294 || rld[reload_order[i]].secondary_p)
5295 && ! rld[reload_order[i]].optional
5296 && rld[reload_order[i]].reg_rtx == 0)
5297 allocate_reload_reg (chain, reload_order[i], 0);
5300 /* First see if this pseudo is already available as reloaded
5301 for a previous insn. We cannot try to inherit for reloads
5302 that are smaller than the maximum number of registers needed
5303 for groups unless the register we would allocate cannot be used
5306 We could check here to see if this is a secondary reload for
5307 an object that is already in a register of the desired class.
5308 This would avoid the need for the secondary reload register.
5309 But this is complex because we can't easily determine what
5310 objects might want to be loaded via this reload. So let a
5311 register be allocated here. In `emit_reload_insns' we suppress
5312 one of the loads in the case described above. */
5317 register int regno = -1;
5318 enum machine_mode mode = VOIDmode;
5322 else if (GET_CODE (rld[r].in) == REG)
5324 regno = REGNO (rld[r].in);
5325 mode = GET_MODE (rld[r].in);
5327 else if (GET_CODE (rld[r].in_reg) == REG)
5329 regno = REGNO (rld[r].in_reg);
5330 mode = GET_MODE (rld[r].in_reg);
5332 else if (GET_CODE (rld[r].in_reg) == SUBREG
5333 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5335 word = SUBREG_WORD (rld[r].in_reg);
5336 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5337 if (regno < FIRST_PSEUDO_REGISTER)
5339 mode = GET_MODE (rld[r].in_reg);
5342 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5343 || GET_CODE (rld[r].in_reg) == PRE_DEC
5344 || GET_CODE (rld[r].in_reg) == POST_INC
5345 || GET_CODE (rld[r].in_reg) == POST_DEC)
5346 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5348 regno = REGNO (XEXP (rld[r].in_reg, 0));
5349 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5350 rld[r].out = rld[r].in;
5354 /* This won't work, since REGNO can be a pseudo reg number.
5355 Also, it takes much more hair to keep track of all the things
5356 that can invalidate an inherited reload of part of a pseudoreg. */
5357 else if (GET_CODE (rld[r].in) == SUBREG
5358 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5359 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5362 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5364 enum reg_class class = rld[r].class, last_class;
5365 rtx last_reg = reg_last_reload_reg[regno];
5366 enum machine_mode need_mode;
5368 i = REGNO (last_reg) + word;
5369 last_class = REGNO_REG_CLASS (i);
5375 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5376 + word * UNITS_PER_WORD,
5377 GET_MODE_CLASS (mode));
5380 #ifdef CLASS_CANNOT_CHANGE_MODE
5382 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5383 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5385 : (GET_MODE_SIZE (GET_MODE (last_reg))
5386 >= GET_MODE_SIZE (need_mode)))
5388 (GET_MODE_SIZE (GET_MODE (last_reg))
5389 >= GET_MODE_SIZE (need_mode))
5391 && reg_reloaded_contents[i] == regno
5392 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5393 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5394 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5395 /* Even if we can't use this register as a reload
5396 register, we might use it for reload_override_in,
5397 if copying it to the desired class is cheap
5399 || ((REGISTER_MOVE_COST (last_class, class)
5400 < MEMORY_MOVE_COST (mode, class, 1))
5401 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5402 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5406 #ifdef SECONDARY_MEMORY_NEEDED
5407 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5412 && (rld[r].nregs == max_group_size
5413 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5415 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5416 rld[r].when_needed, rld[r].in,
5419 /* If a group is needed, verify that all the subsequent
5420 registers still have their values intact. */
5421 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5424 for (k = 1; k < nr; k++)
5425 if (reg_reloaded_contents[i + k] != regno
5426 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5433 last_reg = (GET_MODE (last_reg) == mode
5434 ? last_reg : gen_rtx_REG (mode, i));
5436 /* We found a register that contains the
5437 value we need. If this register is the
5438 same as an `earlyclobber' operand of the
5439 current insn, just mark it as a place to
5440 reload from since we can't use it as the
5441 reload register itself. */
5443 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5444 if (reg_overlap_mentioned_for_reload_p
5445 (reg_last_reload_reg[regno],
5446 reload_earlyclobbers[i1]))
5449 if (i1 != n_earlyclobbers
5450 || ! (free_for_value_p (i, rld[r].mode,
5452 rld[r].when_needed, rld[r].in,
5454 /* Don't use it if we'd clobber a pseudo reg. */
5455 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5457 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5458 /* Don't clobber the frame pointer. */
5459 || (i == HARD_FRAME_POINTER_REGNUM
5461 /* Don't really use the inherited spill reg
5462 if we need it wider than we've got it. */
5463 || (GET_MODE_SIZE (rld[r].mode)
5464 > GET_MODE_SIZE (mode))
5465 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5468 /* If find_reloads chose reload_out as reload
5469 register, stay with it - that leaves the
5470 inherited register for subsequent reloads. */
5471 || (rld[r].out && rld[r].reg_rtx
5472 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5474 if (! rld[r].optional)
5476 reload_override_in[r] = last_reg;
5477 reload_inheritance_insn[r]
5478 = reg_reloaded_insn[i];
5484 /* We can use this as a reload reg. */
5485 /* Mark the register as in use for this part of
5487 mark_reload_reg_in_use (i,
5491 rld[r].reg_rtx = last_reg;
5492 reload_inherited[r] = 1;
5493 reload_inheritance_insn[r]
5494 = reg_reloaded_insn[i];
5495 reload_spill_index[r] = i;
5496 for (k = 0; k < nr; k++)
5497 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5505 /* Here's another way to see if the value is already lying around. */
5508 && ! reload_inherited[r]
5510 && (CONSTANT_P (rld[r].in)
5511 || GET_CODE (rld[r].in) == PLUS
5512 || GET_CODE (rld[r].in) == REG
5513 || GET_CODE (rld[r].in) == MEM)
5514 && (rld[r].nregs == max_group_size
5515 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5516 search_equiv = rld[r].in;
5517 /* If this is an output reload from a simple move insn, look
5518 if an equivalence for the input is available. */
5519 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5521 rtx set = single_set (insn);
5524 && rtx_equal_p (rld[r].out, SET_DEST (set))
5525 && CONSTANT_P (SET_SRC (set)))
5526 search_equiv = SET_SRC (set);
5532 = find_equiv_reg (search_equiv, insn, rld[r].class,
5533 -1, NULL_PTR, 0, rld[r].mode);
5538 if (GET_CODE (equiv) == REG)
5539 regno = REGNO (equiv);
5540 else if (GET_CODE (equiv) == SUBREG)
5542 /* This must be a SUBREG of a hard register.
5543 Make a new REG since this might be used in an
5544 address and not all machines support SUBREGs
5546 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5547 equiv = gen_rtx_REG (rld[r].mode, regno);
5553 /* If we found a spill reg, reject it unless it is free
5554 and of the desired class. */
5556 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5557 && ! free_for_value_p (regno, rld[r].mode,
5558 rld[r].opnum, rld[r].when_needed,
5559 rld[r].in, rld[r].out, r, 1))
5560 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5564 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5567 /* We found a register that contains the value we need.
5568 If this register is the same as an `earlyclobber' operand
5569 of the current insn, just mark it as a place to reload from
5570 since we can't use it as the reload register itself. */
5573 for (i = 0; i < n_earlyclobbers; i++)
5574 if (reg_overlap_mentioned_for_reload_p (equiv,
5575 reload_earlyclobbers[i]))
5577 if (! rld[r].optional)
5578 reload_override_in[r] = equiv;
5583 /* If the equiv register we have found is explicitly clobbered
5584 in the current insn, it depends on the reload type if we
5585 can use it, use it for reload_override_in, or not at all.
5586 In particular, we then can't use EQUIV for a
5587 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5591 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5592 switch (rld[r].when_needed)
5594 case RELOAD_FOR_OTHER_ADDRESS:
5595 case RELOAD_FOR_INPADDR_ADDRESS:
5596 case RELOAD_FOR_INPUT_ADDRESS:
5597 case RELOAD_FOR_OPADDR_ADDR:
5600 case RELOAD_FOR_INPUT:
5601 case RELOAD_FOR_OPERAND_ADDRESS:
5602 if (! rld[r].optional)
5603 reload_override_in[r] = equiv;
5609 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5610 switch (rld[r].when_needed)
5612 case RELOAD_FOR_OTHER_ADDRESS:
5613 case RELOAD_FOR_INPADDR_ADDRESS:
5614 case RELOAD_FOR_INPUT_ADDRESS:
5615 case RELOAD_FOR_OPADDR_ADDR:
5616 case RELOAD_FOR_OPERAND_ADDRESS:
5617 case RELOAD_FOR_INPUT:
5620 if (! rld[r].optional)
5621 reload_override_in[r] = equiv;
5629 /* If we found an equivalent reg, say no code need be generated
5630 to load it, and use it as our reload reg. */
5631 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5633 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5635 rld[r].reg_rtx = equiv;
5636 reload_inherited[r] = 1;
5638 /* If reg_reloaded_valid is not set for this register,
5639 there might be a stale spill_reg_store lying around.
5640 We must clear it, since otherwise emit_reload_insns
5641 might delete the store. */
5642 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5643 spill_reg_store[regno] = NULL_RTX;
5644 /* If any of the hard registers in EQUIV are spill
5645 registers, mark them as in use for this insn. */
5646 for (k = 0; k < nr; k++)
5648 i = spill_reg_order[regno + k];
5651 mark_reload_reg_in_use (regno, rld[r].opnum,
5654 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5661 /* If we found a register to use already, or if this is an optional
5662 reload, we are done. */
5663 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5667 /* No longer needed for correct operation. Might or might
5668 not give better code on the average. Want to experiment? */
5670 /* See if there is a later reload that has a class different from our
5671 class that intersects our class or that requires less register
5672 than our reload. If so, we must allocate a register to this
5673 reload now, since that reload might inherit a previous reload
5674 and take the only available register in our class. Don't do this
5675 for optional reloads since they will force all previous reloads
5676 to be allocated. Also don't do this for reloads that have been
5679 for (i = j + 1; i < n_reloads; i++)
5681 int s = reload_order[i];
5683 if ((rld[s].in == 0 && rld[s].out == 0
5684 && ! rld[s].secondary_p)
5688 if ((rld[s].class != rld[r].class
5689 && reg_classes_intersect_p (rld[r].class,
5691 || rld[s].nregs < rld[r].nregs)
5698 allocate_reload_reg (chain, r, j == n_reloads - 1);
5702 /* Now allocate reload registers for anything non-optional that
5703 didn't get one yet. */
5704 for (j = 0; j < n_reloads; j++)
5706 register int r = reload_order[j];
5708 /* Ignore reloads that got marked inoperative. */
5709 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5712 /* Skip reloads that already have a register allocated or are
5714 if (rld[r].reg_rtx != 0 || rld[r].optional)
5717 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5721 /* If that loop got all the way, we have won. */
5728 /* Loop around and try without any inheritance. */
5733 /* First undo everything done by the failed attempt
5734 to allocate with inheritance. */
5735 choose_reload_regs_init (chain, save_reload_reg_rtx);
5737 /* Some sanity tests to verify that the reloads found in the first
5738 pass are identical to the ones we have now. */
5739 if (chain->n_reloads != n_reloads)
5742 for (i = 0; i < n_reloads; i++)
5744 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5746 if (chain->rld[i].when_needed != rld[i].when_needed)
5748 for (j = 0; j < n_spills; j++)
5749 if (spill_regs[j] == chain->rld[i].regno)
5750 if (! set_reload_reg (j, i))
5751 failed_reload (chain->insn, i);
5755 /* If we thought we could inherit a reload, because it seemed that
5756 nothing else wanted the same reload register earlier in the insn,
5757 verify that assumption, now that all reloads have been assigned.
5758 Likewise for reloads where reload_override_in has been set. */
5760 /* If doing expensive optimizations, do one preliminary pass that doesn't
5761 cancel any inheritance, but removes reloads that have been needed only
5762 for reloads that we know can be inherited. */
5763 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5765 for (j = 0; j < n_reloads; j++)
5767 register int r = reload_order[j];
5769 if (reload_inherited[r] && rld[r].reg_rtx)
5770 check_reg = rld[r].reg_rtx;
5771 else if (reload_override_in[r]
5772 && (GET_CODE (reload_override_in[r]) == REG
5773 || GET_CODE (reload_override_in[r]) == SUBREG))
5774 check_reg = reload_override_in[r];
5777 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5778 rld[r].opnum, rld[r].when_needed, rld[r].in,
5779 (reload_inherited[r]
5780 ? rld[r].out : const0_rtx),
5785 reload_inherited[r] = 0;
5786 reload_override_in[r] = 0;
5788 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5789 reload_override_in, then we do not need its related
5790 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5791 likewise for other reload types.
5792 We handle this by removing a reload when its only replacement
5793 is mentioned in reload_in of the reload we are going to inherit.
5794 A special case are auto_inc expressions; even if the input is
5795 inherited, we still need the address for the output. We can
5796 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5797 If we suceeded removing some reload and we are doing a preliminary
5798 pass just to remove such reloads, make another pass, since the
5799 removal of one reload might allow us to inherit another one. */
5801 && rld[r].out != rld[r].in
5802 && remove_address_replacements (rld[r].in) && pass)
5807 /* Now that reload_override_in is known valid,
5808 actually override reload_in. */
5809 for (j = 0; j < n_reloads; j++)
5810 if (reload_override_in[j])
5811 rld[j].in = reload_override_in[j];
5813 /* If this reload won't be done because it has been cancelled or is
5814 optional and not inherited, clear reload_reg_rtx so other
5815 routines (such as subst_reloads) don't get confused. */
5816 for (j = 0; j < n_reloads; j++)
5817 if (rld[j].reg_rtx != 0
5818 && ((rld[j].optional && ! reload_inherited[j])
5819 || (rld[j].in == 0 && rld[j].out == 0
5820 && ! rld[j].secondary_p)))
5822 int regno = true_regnum (rld[j].reg_rtx);
5824 if (spill_reg_order[regno] >= 0)
5825 clear_reload_reg_in_use (regno, rld[j].opnum,
5826 rld[j].when_needed, rld[j].mode);
5828 reload_spill_index[j] = -1;
5831 /* Record which pseudos and which spill regs have output reloads. */
5832 for (j = 0; j < n_reloads; j++)
5834 register int r = reload_order[j];
5836 i = reload_spill_index[r];
5838 /* I is nonneg if this reload uses a register.
5839 If rld[r].reg_rtx is 0, this is an optional reload
5840 that we opted to ignore. */
5841 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5842 && rld[r].reg_rtx != 0)
5844 register int nregno = REGNO (rld[r].out_reg);
5847 if (nregno < FIRST_PSEUDO_REGISTER)
5848 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5851 reg_has_output_reload[nregno + nr] = 1;
5855 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5857 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5860 if (rld[r].when_needed != RELOAD_OTHER
5861 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5862 && rld[r].when_needed != RELOAD_FOR_INSN)
5868 /* Deallocate the reload register for reload R. This is called from
5869 remove_address_replacements. */
5872 deallocate_reload_reg (r)
5877 if (! rld[r].reg_rtx)
5879 regno = true_regnum (rld[r].reg_rtx);
5881 if (spill_reg_order[regno] >= 0)
5882 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5884 reload_spill_index[r] = -1;
5887 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5888 reloads of the same item for fear that we might not have enough reload
5889 registers. However, normally they will get the same reload register
5890 and hence actually need not be loaded twice.
5892 Here we check for the most common case of this phenomenon: when we have
5893 a number of reloads for the same object, each of which were allocated
5894 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5895 reload, and is not modified in the insn itself. If we find such,
5896 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5897 This will not increase the number of spill registers needed and will
5898 prevent redundant code. */
5901 merge_assigned_reloads (insn)
5906 /* Scan all the reloads looking for ones that only load values and
5907 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5908 assigned and not modified by INSN. */
5910 for (i = 0; i < n_reloads; i++)
5912 int conflicting_input = 0;
5913 int max_input_address_opnum = -1;
5914 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5916 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5917 || rld[i].out != 0 || rld[i].reg_rtx == 0
5918 || reg_set_p (rld[i].reg_rtx, insn))
5921 /* Look at all other reloads. Ensure that the only use of this
5922 reload_reg_rtx is in a reload that just loads the same value
5923 as we do. Note that any secondary reloads must be of the identical
5924 class since the values, modes, and result registers are the
5925 same, so we need not do anything with any secondary reloads. */
5927 for (j = 0; j < n_reloads; j++)
5929 if (i == j || rld[j].reg_rtx == 0
5930 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5934 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5935 && rld[j].opnum > max_input_address_opnum)
5936 max_input_address_opnum = rld[j].opnum;
5938 /* If the reload regs aren't exactly the same (e.g, different modes)
5939 or if the values are different, we can't merge this reload.
5940 But if it is an input reload, we might still merge
5941 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5943 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5944 || rld[j].out != 0 || rld[j].in == 0
5945 || ! rtx_equal_p (rld[i].in, rld[j].in))
5947 if (rld[j].when_needed != RELOAD_FOR_INPUT
5948 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5949 || rld[i].opnum > rld[j].opnum)
5950 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5952 conflicting_input = 1;
5953 if (min_conflicting_input_opnum > rld[j].opnum)
5954 min_conflicting_input_opnum = rld[j].opnum;
5958 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5959 we, in fact, found any matching reloads. */
5962 && max_input_address_opnum <= min_conflicting_input_opnum)
5964 for (j = 0; j < n_reloads; j++)
5965 if (i != j && rld[j].reg_rtx != 0
5966 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5967 && (! conflicting_input
5968 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5969 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5971 rld[i].when_needed = RELOAD_OTHER;
5973 reload_spill_index[j] = -1;
5974 transfer_replacements (i, j);
5977 /* If this is now RELOAD_OTHER, look for any reloads that load
5978 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5979 if they were for inputs, RELOAD_OTHER for outputs. Note that
5980 this test is equivalent to looking for reloads for this operand
5983 if (rld[i].when_needed == RELOAD_OTHER)
5984 for (j = 0; j < n_reloads; j++)
5986 && rld[i].when_needed != RELOAD_OTHER
5987 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5990 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5991 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5992 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5997 /* These arrays are filled by emit_reload_insns and its subroutines. */
5998 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5999 static rtx other_input_address_reload_insns = 0;
6000 static rtx other_input_reload_insns = 0;
6001 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6002 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6003 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6004 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6005 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6006 static rtx operand_reload_insns = 0;
6007 static rtx other_operand_reload_insns = 0;
6008 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6010 /* Values to be put in spill_reg_store are put here first. */
6011 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6012 static HARD_REG_SET reg_reloaded_died;
6014 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6015 has the number J. OLD contains the value to be used as input. */
6018 emit_input_reload_insns (chain, rl, old, j)
6019 struct insn_chain *chain;
6024 rtx insn = chain->insn;
6025 register rtx reloadreg = rl->reg_rtx;
6026 rtx oldequiv_reg = 0;
6029 enum machine_mode mode;
6032 /* Determine the mode to reload in.
6033 This is very tricky because we have three to choose from.
6034 There is the mode the insn operand wants (rl->inmode).
6035 There is the mode of the reload register RELOADREG.
6036 There is the intrinsic mode of the operand, which we could find
6037 by stripping some SUBREGs.
6038 It turns out that RELOADREG's mode is irrelevant:
6039 we can change that arbitrarily.
6041 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6042 then the reload reg may not support QImode moves, so use SImode.
6043 If foo is in memory due to spilling a pseudo reg, this is safe,
6044 because the QImode value is in the least significant part of a
6045 slot big enough for a SImode. If foo is some other sort of
6046 memory reference, then it is impossible to reload this case,
6047 so previous passes had better make sure this never happens.
6049 Then consider a one-word union which has SImode and one of its
6050 members is a float, being fetched as (SUBREG:SF union:SI).
6051 We must fetch that as SFmode because we could be loading into
6052 a float-only register. In this case OLD's mode is correct.
6054 Consider an immediate integer: it has VOIDmode. Here we need
6055 to get a mode from something else.
6057 In some cases, there is a fourth mode, the operand's
6058 containing mode. If the insn specifies a containing mode for
6059 this operand, it overrides all others.
6061 I am not sure whether the algorithm here is always right,
6062 but it does the right things in those cases. */
6064 mode = GET_MODE (old);
6065 if (mode == VOIDmode)
6068 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6069 /* If we need a secondary register for this operation, see if
6070 the value is already in a register in that class. Don't
6071 do this if the secondary register will be used as a scratch
6074 if (rl->secondary_in_reload >= 0
6075 && rl->secondary_in_icode == CODE_FOR_nothing
6078 = find_equiv_reg (old, insn,
6079 rld[rl->secondary_in_reload].class,
6080 -1, NULL_PTR, 0, mode);
6083 /* If reloading from memory, see if there is a register
6084 that already holds the same value. If so, reload from there.
6085 We can pass 0 as the reload_reg_p argument because
6086 any other reload has either already been emitted,
6087 in which case find_equiv_reg will see the reload-insn,
6088 or has yet to be emitted, in which case it doesn't matter
6089 because we will use this equiv reg right away. */
6091 if (oldequiv == 0 && optimize
6092 && (GET_CODE (old) == MEM
6093 || (GET_CODE (old) == REG
6094 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6095 && reg_renumber[REGNO (old)] < 0)))
6096 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6097 -1, NULL_PTR, 0, mode);
6101 unsigned int regno = true_regnum (oldequiv);
6103 /* Don't use OLDEQUIV if any other reload changes it at an
6104 earlier stage of this insn or at this stage. */
6105 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6106 rl->in, const0_rtx, j, 0))
6109 /* If it is no cheaper to copy from OLDEQUIV into the
6110 reload register than it would be to move from memory,
6111 don't use it. Likewise, if we need a secondary register
6115 && ((REGNO_REG_CLASS (regno) != rl->class
6116 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6118 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6119 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6120 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6124 #ifdef SECONDARY_MEMORY_NEEDED
6125 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6133 /* delete_output_reload is only invoked properly if old contains
6134 the original pseudo register. Since this is replaced with a
6135 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6136 find the pseudo in RELOAD_IN_REG. */
6138 && reload_override_in[j]
6139 && GET_CODE (rl->in_reg) == REG)
6146 else if (GET_CODE (oldequiv) == REG)
6147 oldequiv_reg = oldequiv;
6148 else if (GET_CODE (oldequiv) == SUBREG)
6149 oldequiv_reg = SUBREG_REG (oldequiv);
6151 /* If we are reloading from a register that was recently stored in
6152 with an output-reload, see if we can prove there was
6153 actually no need to store the old value in it. */
6155 if (optimize && GET_CODE (oldequiv) == REG
6156 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6157 && spill_reg_store[REGNO (oldequiv)]
6158 && GET_CODE (old) == REG
6159 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6160 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6162 delete_output_reload (insn, j, REGNO (oldequiv));
6164 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6165 then load RELOADREG from OLDEQUIV. Note that we cannot use
6166 gen_lowpart_common since it can do the wrong thing when
6167 RELOADREG has a multi-word mode. Note that RELOADREG
6168 must always be a REG here. */
6170 if (GET_MODE (reloadreg) != mode)
6171 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6172 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6173 oldequiv = SUBREG_REG (oldequiv);
6174 if (GET_MODE (oldequiv) != VOIDmode
6175 && mode != GET_MODE (oldequiv))
6176 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6178 /* Switch to the right place to emit the reload insns. */
6179 switch (rl->when_needed)
6182 where = &other_input_reload_insns;
6184 case RELOAD_FOR_INPUT:
6185 where = &input_reload_insns[rl->opnum];
6187 case RELOAD_FOR_INPUT_ADDRESS:
6188 where = &input_address_reload_insns[rl->opnum];
6190 case RELOAD_FOR_INPADDR_ADDRESS:
6191 where = &inpaddr_address_reload_insns[rl->opnum];
6193 case RELOAD_FOR_OUTPUT_ADDRESS:
6194 where = &output_address_reload_insns[rl->opnum];
6196 case RELOAD_FOR_OUTADDR_ADDRESS:
6197 where = &outaddr_address_reload_insns[rl->opnum];
6199 case RELOAD_FOR_OPERAND_ADDRESS:
6200 where = &operand_reload_insns;
6202 case RELOAD_FOR_OPADDR_ADDR:
6203 where = &other_operand_reload_insns;
6205 case RELOAD_FOR_OTHER_ADDRESS:
6206 where = &other_input_address_reload_insns;
6212 push_to_sequence (*where);
6214 /* Auto-increment addresses must be reloaded in a special way. */
6215 if (rl->out && ! rl->out_reg)
6217 /* We are not going to bother supporting the case where a
6218 incremented register can't be copied directly from
6219 OLDEQUIV since this seems highly unlikely. */
6220 if (rl->secondary_in_reload >= 0)
6223 if (reload_inherited[j])
6224 oldequiv = reloadreg;
6226 old = XEXP (rl->in_reg, 0);
6228 if (optimize && GET_CODE (oldequiv) == REG
6229 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6230 && spill_reg_store[REGNO (oldequiv)]
6231 && GET_CODE (old) == REG
6232 && (dead_or_set_p (insn,
6233 spill_reg_stored_to[REGNO (oldequiv)])
6234 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6236 delete_output_reload (insn, j, REGNO (oldequiv));
6238 /* Prevent normal processing of this reload. */
6240 /* Output a special code sequence for this case. */
6241 new_spill_reg_store[REGNO (reloadreg)]
6242 = inc_for_reload (reloadreg, oldequiv, rl->out,
6246 /* If we are reloading a pseudo-register that was set by the previous
6247 insn, see if we can get rid of that pseudo-register entirely
6248 by redirecting the previous insn into our reload register. */
6250 else if (optimize && GET_CODE (old) == REG
6251 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6252 && dead_or_set_p (insn, old)
6253 /* This is unsafe if some other reload
6254 uses the same reg first. */
6255 && ! conflicts_with_override (reloadreg)
6256 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6257 rl->when_needed, old, rl->out, j, 0))
6259 rtx temp = PREV_INSN (insn);
6260 while (temp && GET_CODE (temp) == NOTE)
6261 temp = PREV_INSN (temp);
6263 && GET_CODE (temp) == INSN
6264 && GET_CODE (PATTERN (temp)) == SET
6265 && SET_DEST (PATTERN (temp)) == old
6266 /* Make sure we can access insn_operand_constraint. */
6267 && asm_noperands (PATTERN (temp)) < 0
6268 /* This is unsafe if prev insn rejects our reload reg. */
6269 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6271 /* This is unsafe if operand occurs more than once in current
6272 insn. Perhaps some occurrences aren't reloaded. */
6273 && count_occurrences (PATTERN (insn), old, 0) == 1
6274 /* Don't risk splitting a matching pair of operands. */
6275 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6277 /* Store into the reload register instead of the pseudo. */
6278 SET_DEST (PATTERN (temp)) = reloadreg;
6280 /* If the previous insn is an output reload, the source is
6281 a reload register, and its spill_reg_store entry will
6282 contain the previous destination. This is now
6284 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6285 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6287 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6288 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6291 /* If these are the only uses of the pseudo reg,
6292 pretend for GDB it lives in the reload reg we used. */
6293 if (REG_N_DEATHS (REGNO (old)) == 1
6294 && REG_N_SETS (REGNO (old)) == 1)
6296 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6297 alter_reg (REGNO (old), -1);
6303 /* We can't do that, so output an insn to load RELOADREG. */
6305 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6306 /* If we have a secondary reload, pick up the secondary register
6307 and icode, if any. If OLDEQUIV and OLD are different or
6308 if this is an in-out reload, recompute whether or not we
6309 still need a secondary register and what the icode should
6310 be. If we still need a secondary register and the class or
6311 icode is different, go back to reloading from OLD if using
6312 OLDEQUIV means that we got the wrong type of register. We
6313 cannot have different class or icode due to an in-out reload
6314 because we don't make such reloads when both the input and
6315 output need secondary reload registers. */
6317 if (! special && rl->secondary_in_reload >= 0)
6319 rtx second_reload_reg = 0;
6320 int secondary_reload = rl->secondary_in_reload;
6321 rtx real_oldequiv = oldequiv;
6324 enum insn_code icode;
6326 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6327 and similarly for OLD.
6328 See comments in get_secondary_reload in reload.c. */
6329 /* If it is a pseudo that cannot be replaced with its
6330 equivalent MEM, we must fall back to reload_in, which
6331 will have all the necessary substitutions registered.
6332 Likewise for a pseudo that can't be replaced with its
6333 equivalent constant.
6335 Take extra care for subregs of such pseudos. Note that
6336 we cannot use reg_equiv_mem in this case because it is
6337 not in the right mode. */
6340 if (GET_CODE (tmp) == SUBREG)
6341 tmp = SUBREG_REG (tmp);
6342 if (GET_CODE (tmp) == REG
6343 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6344 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6345 || reg_equiv_constant[REGNO (tmp)] != 0))
6347 if (! reg_equiv_mem[REGNO (tmp)]
6348 || num_not_at_initial_offset
6349 || GET_CODE (oldequiv) == SUBREG)
6350 real_oldequiv = rl->in;
6352 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6356 if (GET_CODE (tmp) == SUBREG)
6357 tmp = SUBREG_REG (tmp);
6358 if (GET_CODE (tmp) == REG
6359 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6360 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6361 || reg_equiv_constant[REGNO (tmp)] != 0))
6363 if (! reg_equiv_mem[REGNO (tmp)]
6364 || num_not_at_initial_offset
6365 || GET_CODE (old) == SUBREG)
6368 real_old = reg_equiv_mem[REGNO (tmp)];
6371 second_reload_reg = rld[secondary_reload].reg_rtx;
6372 icode = rl->secondary_in_icode;
6374 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6375 || (rl->in != 0 && rl->out != 0))
6377 enum reg_class new_class
6378 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6379 mode, real_oldequiv);
6381 if (new_class == NO_REGS)
6382 second_reload_reg = 0;
6385 enum insn_code new_icode;
6386 enum machine_mode new_mode;
6388 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6389 REGNO (second_reload_reg)))
6390 oldequiv = old, real_oldequiv = real_old;
6393 new_icode = reload_in_optab[(int) mode];
6394 if (new_icode != CODE_FOR_nothing
6395 && ((insn_data[(int) new_icode].operand[0].predicate
6396 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6398 || (insn_data[(int) new_icode].operand[1].predicate
6399 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6400 (real_oldequiv, mode)))))
6401 new_icode = CODE_FOR_nothing;
6403 if (new_icode == CODE_FOR_nothing)
6406 new_mode = insn_data[(int) new_icode].operand[2].mode;
6408 if (GET_MODE (second_reload_reg) != new_mode)
6410 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6412 oldequiv = old, real_oldequiv = real_old;
6415 = gen_rtx_REG (new_mode,
6416 REGNO (second_reload_reg));
6422 /* If we still need a secondary reload register, check
6423 to see if it is being used as a scratch or intermediate
6424 register and generate code appropriately. If we need
6425 a scratch register, use REAL_OLDEQUIV since the form of
6426 the insn may depend on the actual address if it is
6429 if (second_reload_reg)
6431 if (icode != CODE_FOR_nothing)
6433 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6434 second_reload_reg));
6439 /* See if we need a scratch register to load the
6440 intermediate register (a tertiary reload). */
6441 enum insn_code tertiary_icode
6442 = rld[secondary_reload].secondary_in_icode;
6444 if (tertiary_icode != CODE_FOR_nothing)
6446 rtx third_reload_reg
6447 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6449 emit_insn ((GEN_FCN (tertiary_icode)
6450 (second_reload_reg, real_oldequiv,
6451 third_reload_reg)));
6454 gen_reload (second_reload_reg, real_oldequiv,
6458 oldequiv = second_reload_reg;
6464 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6466 rtx real_oldequiv = oldequiv;
6468 if ((GET_CODE (oldequiv) == REG
6469 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6470 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6471 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6472 || (GET_CODE (oldequiv) == SUBREG
6473 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6474 && (REGNO (SUBREG_REG (oldequiv))
6475 >= FIRST_PSEUDO_REGISTER)
6476 && ((reg_equiv_memory_loc
6477 [REGNO (SUBREG_REG (oldequiv))] != 0)
6478 || (reg_equiv_constant
6479 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6480 || (CONSTANT_P (oldequiv)
6481 && PREFERRED_RELOAD_CLASS (oldequiv,
6482 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6483 real_oldequiv = rl->in;
6484 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6488 /* End this sequence. */
6489 *where = get_insns ();
6492 /* Update reload_override_in so that delete_address_reloads_1
6493 can see the actual register usage. */
6495 reload_override_in[j] = oldequiv;
6498 /* Generate insns to for the output reload RL, which is for the insn described
6499 by CHAIN and has the number J. */
6501 emit_output_reload_insns (chain, rl, j)
6502 struct insn_chain *chain;
6506 rtx reloadreg = rl->reg_rtx;
6507 rtx insn = chain->insn;
6510 enum machine_mode mode = GET_MODE (old);
6513 if (rl->when_needed == RELOAD_OTHER)
6516 push_to_sequence (output_reload_insns[rl->opnum]);
6518 /* Determine the mode to reload in.
6519 See comments above (for input reloading). */
6521 if (mode == VOIDmode)
6523 /* VOIDmode should never happen for an output. */
6524 if (asm_noperands (PATTERN (insn)) < 0)
6525 /* It's the compiler's fault. */
6526 fatal_insn ("VOIDmode on an output", insn);
6527 error_for_asm (insn, "output operand is constant in `asm'");
6528 /* Prevent crash--use something we know is valid. */
6530 old = gen_rtx_REG (mode, REGNO (reloadreg));
6533 if (GET_MODE (reloadreg) != mode)
6534 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6536 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6538 /* If we need two reload regs, set RELOADREG to the intermediate
6539 one, since it will be stored into OLD. We might need a secondary
6540 register only for an input reload, so check again here. */
6542 if (rl->secondary_out_reload >= 0)
6546 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6547 && reg_equiv_mem[REGNO (old)] != 0)
6548 real_old = reg_equiv_mem[REGNO (old)];
6550 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6554 rtx second_reloadreg = reloadreg;
6555 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6557 /* See if RELOADREG is to be used as a scratch register
6558 or as an intermediate register. */
6559 if (rl->secondary_out_icode != CODE_FOR_nothing)
6561 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6562 (real_old, second_reloadreg, reloadreg)));
6567 /* See if we need both a scratch and intermediate reload
6570 int secondary_reload = rl->secondary_out_reload;
6571 enum insn_code tertiary_icode
6572 = rld[secondary_reload].secondary_out_icode;
6574 if (GET_MODE (reloadreg) != mode)
6575 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6577 if (tertiary_icode != CODE_FOR_nothing)
6580 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6583 /* Copy primary reload reg to secondary reload reg.
6584 (Note that these have been swapped above, then
6585 secondary reload reg to OLD using our insn. */
6587 /* If REAL_OLD is a paradoxical SUBREG, remove it
6588 and try to put the opposite SUBREG on
6590 if (GET_CODE (real_old) == SUBREG
6591 && (GET_MODE_SIZE (GET_MODE (real_old))
6592 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6593 && 0 != (tem = gen_lowpart_common
6594 (GET_MODE (SUBREG_REG (real_old)),
6596 real_old = SUBREG_REG (real_old), reloadreg = tem;
6598 gen_reload (reloadreg, second_reloadreg,
6599 rl->opnum, rl->when_needed);
6600 emit_insn ((GEN_FCN (tertiary_icode)
6601 (real_old, reloadreg, third_reloadreg)));
6606 /* Copy between the reload regs here and then to
6609 gen_reload (reloadreg, second_reloadreg,
6610 rl->opnum, rl->when_needed);
6616 /* Output the last reload insn. */
6621 /* Don't output the last reload if OLD is not the dest of
6622 INSN and is in the src and is clobbered by INSN. */
6623 if (! flag_expensive_optimizations
6624 || GET_CODE (old) != REG
6625 || !(set = single_set (insn))
6626 || rtx_equal_p (old, SET_DEST (set))
6627 || !reg_mentioned_p (old, SET_SRC (set))
6628 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6629 gen_reload (old, reloadreg, rl->opnum,
6633 /* Look at all insns we emitted, just to be safe. */
6634 for (p = get_insns (); p; p = NEXT_INSN (p))
6637 rtx pat = PATTERN (p);
6639 /* If this output reload doesn't come from a spill reg,
6640 clear any memory of reloaded copies of the pseudo reg.
6641 If this output reload comes from a spill reg,
6642 reg_has_output_reload will make this do nothing. */
6643 note_stores (pat, forget_old_reloads_1, NULL);
6645 if (reg_mentioned_p (rl->reg_rtx, pat))
6647 rtx set = single_set (insn);
6648 if (reload_spill_index[j] < 0
6650 && SET_SRC (set) == rl->reg_rtx)
6652 int src = REGNO (SET_SRC (set));
6654 reload_spill_index[j] = src;
6655 SET_HARD_REG_BIT (reg_is_output_reload, src);
6656 if (find_regno_note (insn, REG_DEAD, src))
6657 SET_HARD_REG_BIT (reg_reloaded_died, src);
6659 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6661 int s = rl->secondary_out_reload;
6662 set = single_set (p);
6663 /* If this reload copies only to the secondary reload
6664 register, the secondary reload does the actual
6666 if (s >= 0 && set == NULL_RTX)
6667 /* We can't tell what function the secondary reload
6668 has and where the actual store to the pseudo is
6669 made; leave new_spill_reg_store alone. */
6672 && SET_SRC (set) == rl->reg_rtx
6673 && SET_DEST (set) == rld[s].reg_rtx)
6675 /* Usually the next instruction will be the
6676 secondary reload insn; if we can confirm
6677 that it is, setting new_spill_reg_store to
6678 that insn will allow an extra optimization. */
6679 rtx s_reg = rld[s].reg_rtx;
6680 rtx next = NEXT_INSN (p);
6681 rld[s].out = rl->out;
6682 rld[s].out_reg = rl->out_reg;
6683 set = single_set (next);
6684 if (set && SET_SRC (set) == s_reg
6685 && ! new_spill_reg_store[REGNO (s_reg)])
6687 SET_HARD_REG_BIT (reg_is_output_reload,
6689 new_spill_reg_store[REGNO (s_reg)] = next;
6693 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6698 if (rl->when_needed == RELOAD_OTHER)
6700 emit_insns (other_output_reload_insns[rl->opnum]);
6701 other_output_reload_insns[rl->opnum] = get_insns ();
6704 output_reload_insns[rl->opnum] = get_insns ();
6709 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6710 and has the number J. */
6712 do_input_reload (chain, rl, j)
6713 struct insn_chain *chain;
6717 int expect_occurrences = 1;
6718 rtx insn = chain->insn;
6719 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6720 ? rl->in_reg : rl->in);
6723 /* AUTO_INC reloads need to be handled even if inherited. We got an
6724 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6725 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6726 && ! rtx_equal_p (rl->reg_rtx, old)
6727 && rl->reg_rtx != 0)
6728 emit_input_reload_insns (chain, rld + j, old, j);
6730 /* When inheriting a wider reload, we have a MEM in rl->in,
6731 e.g. inheriting a SImode output reload for
6732 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6733 if (optimize && reload_inherited[j] && rl->in
6734 && GET_CODE (rl->in) == MEM
6735 && GET_CODE (rl->in_reg) == MEM
6736 && reload_spill_index[j] >= 0
6737 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6740 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6741 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6744 /* If we are reloading a register that was recently stored in with an
6745 output-reload, see if we can prove there was
6746 actually no need to store the old value in it. */
6749 && (reload_inherited[j] || reload_override_in[j])
6751 && GET_CODE (rl->reg_rtx) == REG
6752 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6754 /* There doesn't seem to be any reason to restrict this to pseudos
6755 and doing so loses in the case where we are copying from a
6756 register of the wrong class. */
6757 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6758 >= FIRST_PSEUDO_REGISTER)
6760 /* The insn might have already some references to stackslots
6761 replaced by MEMs, while reload_out_reg still names the
6763 && (dead_or_set_p (insn,
6764 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6765 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6767 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6770 /* Do output reloading for reload RL, which is for the insn described by
6771 CHAIN and has the number J.
6772 ??? At some point we need to support handling output reloads of
6773 JUMP_INSNs or insns that set cc0. */
6775 do_output_reload (chain, rl, j)
6776 struct insn_chain *chain;
6781 rtx insn = chain->insn;
6782 /* If this is an output reload that stores something that is
6783 not loaded in this same reload, see if we can eliminate a previous
6785 rtx pseudo = rl->out_reg;
6788 && GET_CODE (pseudo) == REG
6789 && ! rtx_equal_p (rl->in_reg, pseudo)
6790 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6791 && reg_last_reload_reg[REGNO (pseudo)])
6793 int pseudo_no = REGNO (pseudo);
6794 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6796 /* We don't need to test full validity of last_regno for
6797 inherit here; we only want to know if the store actually
6798 matches the pseudo. */
6799 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6800 && reg_reloaded_contents[last_regno] == pseudo_no
6801 && spill_reg_store[last_regno]
6802 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6803 delete_output_reload (insn, j, last_regno);
6808 || rl->reg_rtx == old
6809 || rl->reg_rtx == 0)
6812 /* An output operand that dies right away does need a reload,
6813 but need not be copied from it. Show the new location in the
6815 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6816 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6818 XEXP (note, 0) = rl->reg_rtx;
6821 /* Likewise for a SUBREG of an operand that dies. */
6822 else if (GET_CODE (old) == SUBREG
6823 && GET_CODE (SUBREG_REG (old)) == REG
6824 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6827 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6831 else if (GET_CODE (old) == SCRATCH)
6832 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6833 but we don't want to make an output reload. */
6836 /* If is a JUMP_INSN, we can't support output reloads yet. */
6837 if (GET_CODE (insn) == JUMP_INSN)
6840 emit_output_reload_insns (chain, rld + j, j);
6843 /* Output insns to reload values in and out of the chosen reload regs. */
6846 emit_reload_insns (chain)
6847 struct insn_chain *chain;
6849 rtx insn = chain->insn;
6852 rtx following_insn = NEXT_INSN (insn);
6853 rtx before_insn = PREV_INSN (insn);
6855 CLEAR_HARD_REG_SET (reg_reloaded_died);
6857 for (j = 0; j < reload_n_operands; j++)
6858 input_reload_insns[j] = input_address_reload_insns[j]
6859 = inpaddr_address_reload_insns[j]
6860 = output_reload_insns[j] = output_address_reload_insns[j]
6861 = outaddr_address_reload_insns[j]
6862 = other_output_reload_insns[j] = 0;
6863 other_input_address_reload_insns = 0;
6864 other_input_reload_insns = 0;
6865 operand_reload_insns = 0;
6866 other_operand_reload_insns = 0;
6868 /* Dump reloads into the dump file. */
6871 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6872 debug_reload_to_stream (rtl_dump_file);
6875 /* Now output the instructions to copy the data into and out of the
6876 reload registers. Do these in the order that the reloads were reported,
6877 since reloads of base and index registers precede reloads of operands
6878 and the operands may need the base and index registers reloaded. */
6880 for (j = 0; j < n_reloads; j++)
6883 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6884 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6886 do_input_reload (chain, rld + j, j);
6887 do_output_reload (chain, rld + j, j);
6890 /* Now write all the insns we made for reloads in the order expected by
6891 the allocation functions. Prior to the insn being reloaded, we write
6892 the following reloads:
6894 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6896 RELOAD_OTHER reloads.
6898 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6899 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6900 RELOAD_FOR_INPUT reload for the operand.
6902 RELOAD_FOR_OPADDR_ADDRS reloads.
6904 RELOAD_FOR_OPERAND_ADDRESS reloads.
6906 After the insn being reloaded, we write the following:
6908 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6909 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6910 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6911 reloads for the operand. The RELOAD_OTHER output reloads are
6912 output in descending order by reload number. */
6914 emit_insns_before (other_input_address_reload_insns, insn);
6915 emit_insns_before (other_input_reload_insns, insn);
6917 for (j = 0; j < reload_n_operands; j++)
6919 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6920 emit_insns_before (input_address_reload_insns[j], insn);
6921 emit_insns_before (input_reload_insns[j], insn);
6924 emit_insns_before (other_operand_reload_insns, insn);
6925 emit_insns_before (operand_reload_insns, insn);
6927 for (j = 0; j < reload_n_operands; j++)
6929 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6930 emit_insns_before (output_address_reload_insns[j], following_insn);
6931 emit_insns_before (output_reload_insns[j], following_insn);
6932 emit_insns_before (other_output_reload_insns[j], following_insn);
6935 /* Keep basic block info up to date. */
6938 if (BLOCK_HEAD (chain->block) == insn)
6939 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6940 if (BLOCK_END (chain->block) == insn)
6941 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6944 /* For all the spill regs newly reloaded in this instruction,
6945 record what they were reloaded from, so subsequent instructions
6946 can inherit the reloads.
6948 Update spill_reg_store for the reloads of this insn.
6949 Copy the elements that were updated in the loop above. */
6951 for (j = 0; j < n_reloads; j++)
6953 register int r = reload_order[j];
6954 register int i = reload_spill_index[r];
6956 /* If this is a non-inherited input reload from a pseudo, we must
6957 clear any memory of a previous store to the same pseudo. Only do
6958 something if there will not be an output reload for the pseudo
6960 if (rld[r].in_reg != 0
6961 && ! (reload_inherited[r] || reload_override_in[r]))
6963 rtx reg = rld[r].in_reg;
6965 if (GET_CODE (reg) == SUBREG)
6966 reg = SUBREG_REG (reg);
6968 if (GET_CODE (reg) == REG
6969 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6970 && ! reg_has_output_reload[REGNO (reg)])
6972 int nregno = REGNO (reg);
6974 if (reg_last_reload_reg[nregno])
6976 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6978 if (reg_reloaded_contents[last_regno] == nregno)
6979 spill_reg_store[last_regno] = 0;
6984 /* I is nonneg if this reload used a register.
6985 If rld[r].reg_rtx is 0, this is an optional reload
6986 that we opted to ignore. */
6988 if (i >= 0 && rld[r].reg_rtx != 0)
6990 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6992 int part_reaches_end = 0;
6993 int all_reaches_end = 1;
6995 /* For a multi register reload, we need to check if all or part
6996 of the value lives to the end. */
6997 for (k = 0; k < nr; k++)
6999 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7000 rld[r].when_needed))
7001 part_reaches_end = 1;
7003 all_reaches_end = 0;
7006 /* Ignore reloads that don't reach the end of the insn in
7008 if (all_reaches_end)
7010 /* First, clear out memory of what used to be in this spill reg.
7011 If consecutive registers are used, clear them all. */
7013 for (k = 0; k < nr; k++)
7014 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7016 /* Maybe the spill reg contains a copy of reload_out. */
7018 && (GET_CODE (rld[r].out) == REG
7022 || GET_CODE (rld[r].out_reg) == REG))
7024 rtx out = (GET_CODE (rld[r].out) == REG
7028 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7029 register int nregno = REGNO (out);
7030 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7031 : HARD_REGNO_NREGS (nregno,
7032 GET_MODE (rld[r].reg_rtx)));
7034 spill_reg_store[i] = new_spill_reg_store[i];
7035 spill_reg_stored_to[i] = out;
7036 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7038 /* If NREGNO is a hard register, it may occupy more than
7039 one register. If it does, say what is in the
7040 rest of the registers assuming that both registers
7041 agree on how many words the object takes. If not,
7042 invalidate the subsequent registers. */
7044 if (nregno < FIRST_PSEUDO_REGISTER)
7045 for (k = 1; k < nnr; k++)
7046 reg_last_reload_reg[nregno + k]
7048 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7049 REGNO (rld[r].reg_rtx) + k)
7052 /* Now do the inverse operation. */
7053 for (k = 0; k < nr; k++)
7055 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7056 reg_reloaded_contents[i + k]
7057 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7060 reg_reloaded_insn[i + k] = insn;
7061 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7065 /* Maybe the spill reg contains a copy of reload_in. Only do
7066 something if there will not be an output reload for
7067 the register being reloaded. */
7068 else if (rld[r].out_reg == 0
7070 && ((GET_CODE (rld[r].in) == REG
7071 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7072 && ! reg_has_output_reload[REGNO (rld[r].in)])
7073 || (GET_CODE (rld[r].in_reg) == REG
7074 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7075 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7077 register int nregno;
7080 if (GET_CODE (rld[r].in) == REG
7081 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7082 nregno = REGNO (rld[r].in);
7083 else if (GET_CODE (rld[r].in_reg) == REG)
7084 nregno = REGNO (rld[r].in_reg);
7086 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7088 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7089 : HARD_REGNO_NREGS (nregno,
7090 GET_MODE (rld[r].reg_rtx)));
7092 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7094 if (nregno < FIRST_PSEUDO_REGISTER)
7095 for (k = 1; k < nnr; k++)
7096 reg_last_reload_reg[nregno + k]
7098 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7099 REGNO (rld[r].reg_rtx) + k)
7102 /* Unless we inherited this reload, show we haven't
7103 recently done a store.
7104 Previous stores of inherited auto_inc expressions
7105 also have to be discarded. */
7106 if (! reload_inherited[r]
7107 || (rld[r].out && ! rld[r].out_reg))
7108 spill_reg_store[i] = 0;
7110 for (k = 0; k < nr; k++)
7112 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7113 reg_reloaded_contents[i + k]
7114 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7117 reg_reloaded_insn[i + k] = insn;
7118 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7123 /* However, if part of the reload reaches the end, then we must
7124 invalidate the old info for the part that survives to the end. */
7125 else if (part_reaches_end)
7127 for (k = 0; k < nr; k++)
7128 if (reload_reg_reaches_end_p (i + k,
7130 rld[r].when_needed))
7131 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7135 /* The following if-statement was #if 0'd in 1.34 (or before...).
7136 It's reenabled in 1.35 because supposedly nothing else
7137 deals with this problem. */
7139 /* If a register gets output-reloaded from a non-spill register,
7140 that invalidates any previous reloaded copy of it.
7141 But forget_old_reloads_1 won't get to see it, because
7142 it thinks only about the original insn. So invalidate it here. */
7143 if (i < 0 && rld[r].out != 0
7144 && (GET_CODE (rld[r].out) == REG
7145 || (GET_CODE (rld[r].out) == MEM
7146 && GET_CODE (rld[r].out_reg) == REG)))
7148 rtx out = (GET_CODE (rld[r].out) == REG
7149 ? rld[r].out : rld[r].out_reg);
7150 register int nregno = REGNO (out);
7151 if (nregno >= FIRST_PSEUDO_REGISTER)
7153 rtx src_reg, store_insn = NULL_RTX;
7155 reg_last_reload_reg[nregno] = 0;
7157 /* If we can find a hard register that is stored, record
7158 the storing insn so that we may delete this insn with
7159 delete_output_reload. */
7160 src_reg = rld[r].reg_rtx;
7162 /* If this is an optional reload, try to find the source reg
7163 from an input reload. */
7166 rtx set = single_set (insn);
7167 if (set && SET_DEST (set) == rld[r].out)
7171 src_reg = SET_SRC (set);
7173 for (k = 0; k < n_reloads; k++)
7175 if (rld[k].in == src_reg)
7177 src_reg = rld[k].reg_rtx;
7184 store_insn = new_spill_reg_store[REGNO (src_reg)];
7185 if (src_reg && GET_CODE (src_reg) == REG
7186 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7188 int src_regno = REGNO (src_reg);
7189 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7190 /* The place where to find a death note varies with
7191 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7192 necessarily checked exactly in the code that moves
7193 notes, so just check both locations. */
7194 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7196 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7199 spill_reg_store[src_regno + nr] = store_insn;
7200 spill_reg_stored_to[src_regno + nr] = out;
7201 reg_reloaded_contents[src_regno + nr] = nregno;
7202 reg_reloaded_insn[src_regno + nr] = store_insn;
7203 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7204 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7205 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7207 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7209 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7211 reg_last_reload_reg[nregno] = src_reg;
7216 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7218 while (num_regs-- > 0)
7219 reg_last_reload_reg[nregno + num_regs] = 0;
7223 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7226 /* Emit code to perform a reload from IN (which may be a reload register) to
7227 OUT (which may also be a reload register). IN or OUT is from operand
7228 OPNUM with reload type TYPE.
7230 Returns first insn emitted. */
7233 gen_reload (out, in, opnum, type)
7237 enum reload_type type;
7239 rtx last = get_last_insn ();
7242 /* If IN is a paradoxical SUBREG, remove it and try to put the
7243 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7244 if (GET_CODE (in) == SUBREG
7245 && (GET_MODE_SIZE (GET_MODE (in))
7246 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7247 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7248 in = SUBREG_REG (in), out = tem;
7249 else if (GET_CODE (out) == SUBREG
7250 && (GET_MODE_SIZE (GET_MODE (out))
7251 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7252 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7253 out = SUBREG_REG (out), in = tem;
7255 /* How to do this reload can get quite tricky. Normally, we are being
7256 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7257 register that didn't get a hard register. In that case we can just
7258 call emit_move_insn.
7260 We can also be asked to reload a PLUS that adds a register or a MEM to
7261 another register, constant or MEM. This can occur during frame pointer
7262 elimination and while reloading addresses. This case is handled by
7263 trying to emit a single insn to perform the add. If it is not valid,
7264 we use a two insn sequence.
7266 Finally, we could be called to handle an 'o' constraint by putting
7267 an address into a register. In that case, we first try to do this
7268 with a named pattern of "reload_load_address". If no such pattern
7269 exists, we just emit a SET insn and hope for the best (it will normally
7270 be valid on machines that use 'o').
7272 This entire process is made complex because reload will never
7273 process the insns we generate here and so we must ensure that
7274 they will fit their constraints and also by the fact that parts of
7275 IN might be being reloaded separately and replaced with spill registers.
7276 Because of this, we are, in some sense, just guessing the right approach
7277 here. The one listed above seems to work.
7279 ??? At some point, this whole thing needs to be rethought. */
7281 if (GET_CODE (in) == PLUS
7282 && (GET_CODE (XEXP (in, 0)) == REG
7283 || GET_CODE (XEXP (in, 0)) == SUBREG
7284 || GET_CODE (XEXP (in, 0)) == MEM)
7285 && (GET_CODE (XEXP (in, 1)) == REG
7286 || GET_CODE (XEXP (in, 1)) == SUBREG
7287 || CONSTANT_P (XEXP (in, 1))
7288 || GET_CODE (XEXP (in, 1)) == MEM))
7290 /* We need to compute the sum of a register or a MEM and another
7291 register, constant, or MEM, and put it into the reload
7292 register. The best possible way of doing this is if the machine
7293 has a three-operand ADD insn that accepts the required operands.
7295 The simplest approach is to try to generate such an insn and see if it
7296 is recognized and matches its constraints. If so, it can be used.
7298 It might be better not to actually emit the insn unless it is valid,
7299 but we need to pass the insn as an operand to `recog' and
7300 `extract_insn' and it is simpler to emit and then delete the insn if
7301 not valid than to dummy things up. */
7303 rtx op0, op1, tem, insn;
7306 op0 = find_replacement (&XEXP (in, 0));
7307 op1 = find_replacement (&XEXP (in, 1));
7309 /* Since constraint checking is strict, commutativity won't be
7310 checked, so we need to do that here to avoid spurious failure
7311 if the add instruction is two-address and the second operand
7312 of the add is the same as the reload reg, which is frequently
7313 the case. If the insn would be A = B + A, rearrange it so
7314 it will be A = A + B as constrain_operands expects. */
7316 if (GET_CODE (XEXP (in, 1)) == REG
7317 && REGNO (out) == REGNO (XEXP (in, 1)))
7318 tem = op0, op0 = op1, op1 = tem;
7320 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7321 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7323 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7324 code = recog_memoized (insn);
7328 extract_insn (insn);
7329 /* We want constrain operands to treat this insn strictly in
7330 its validity determination, i.e., the way it would after reload
7332 if (constrain_operands (1))
7336 delete_insns_since (last);
7338 /* If that failed, we must use a conservative two-insn sequence.
7340 Use a move to copy one operand into the reload register. Prefer
7341 to reload a constant, MEM or pseudo since the move patterns can
7342 handle an arbitrary operand. If OP1 is not a constant, MEM or
7343 pseudo and OP1 is not a valid operand for an add instruction, then
7346 After reloading one of the operands into the reload register, add
7347 the reload register to the output register.
7349 If there is another way to do this for a specific machine, a
7350 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7353 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7355 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7356 || (GET_CODE (op1) == REG
7357 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7358 || (code != CODE_FOR_nothing
7359 && ! ((*insn_data[code].operand[2].predicate)
7360 (op1, insn_data[code].operand[2].mode))))
7361 tem = op0, op0 = op1, op1 = tem;
7363 gen_reload (out, op0, opnum, type);
7365 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7366 This fixes a problem on the 32K where the stack pointer cannot
7367 be used as an operand of an add insn. */
7369 if (rtx_equal_p (op0, op1))
7372 insn = emit_insn (gen_add2_insn (out, op1));
7374 /* If that failed, copy the address register to the reload register.
7375 Then add the constant to the reload register. */
7377 code = recog_memoized (insn);
7381 extract_insn (insn);
7382 /* We want constrain operands to treat this insn strictly in
7383 its validity determination, i.e., the way it would after reload
7385 if (constrain_operands (1))
7387 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7389 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7394 delete_insns_since (last);
7396 gen_reload (out, op1, opnum, type);
7397 insn = emit_insn (gen_add2_insn (out, op0));
7398 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7401 #ifdef SECONDARY_MEMORY_NEEDED
7402 /* If we need a memory location to do the move, do it that way. */
7403 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7404 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7405 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7406 REGNO_REG_CLASS (REGNO (out)),
7409 /* Get the memory to use and rewrite both registers to its mode. */
7410 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7412 if (GET_MODE (loc) != GET_MODE (out))
7413 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7415 if (GET_MODE (loc) != GET_MODE (in))
7416 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7418 gen_reload (loc, in, opnum, type);
7419 gen_reload (out, loc, opnum, type);
7423 /* If IN is a simple operand, use gen_move_insn. */
7424 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7425 emit_insn (gen_move_insn (out, in));
7427 #ifdef HAVE_reload_load_address
7428 else if (HAVE_reload_load_address)
7429 emit_insn (gen_reload_load_address (out, in));
7432 /* Otherwise, just write (set OUT IN) and hope for the best. */
7434 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7436 /* Return the first insn emitted.
7437 We can not just return get_last_insn, because there may have
7438 been multiple instructions emitted. Also note that gen_move_insn may
7439 emit more than one insn itself, so we can not assume that there is one
7440 insn emitted per emit_insn_before call. */
7442 return last ? NEXT_INSN (last) : get_insns ();
7445 /* Delete a previously made output-reload
7446 whose result we now believe is not needed.
7447 First we double-check.
7449 INSN is the insn now being processed.
7450 LAST_RELOAD_REG is the hard register number for which we want to delete
7451 the last output reload.
7452 J is the reload-number that originally used REG. The caller has made
7453 certain that reload J doesn't use REG any longer for input. */
7456 delete_output_reload (insn, j, last_reload_reg)
7459 int last_reload_reg;
7461 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7462 rtx reg = spill_reg_stored_to[last_reload_reg];
7465 int n_inherited = 0;
7469 /* Get the raw pseudo-register referred to. */
7471 while (GET_CODE (reg) == SUBREG)
7472 reg = SUBREG_REG (reg);
7473 substed = reg_equiv_memory_loc[REGNO (reg)];
7475 /* This is unsafe if the operand occurs more often in the current
7476 insn than it is inherited. */
7477 for (k = n_reloads - 1; k >= 0; k--)
7479 rtx reg2 = rld[k].in;
7482 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7483 reg2 = rld[k].in_reg;
7485 if (rld[k].out && ! rld[k].out_reg)
7486 reg2 = XEXP (rld[k].in_reg, 0);
7488 while (GET_CODE (reg2) == SUBREG)
7489 reg2 = SUBREG_REG (reg2);
7490 if (rtx_equal_p (reg2, reg))
7492 if (reload_inherited[k] || reload_override_in[k] || k == j)
7495 reg2 = rld[k].out_reg;
7498 while (GET_CODE (reg2) == SUBREG)
7499 reg2 = XEXP (reg2, 0);
7500 if (rtx_equal_p (reg2, reg))
7507 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7509 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7510 if (n_occurrences > n_inherited)
7513 /* If the pseudo-reg we are reloading is no longer referenced
7514 anywhere between the store into it and here,
7515 and no jumps or labels intervene, then the value can get
7516 here through the reload reg alone.
7517 Otherwise, give up--return. */
7518 for (i1 = NEXT_INSN (output_reload_insn);
7519 i1 != insn; i1 = NEXT_INSN (i1))
7521 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7523 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7524 && reg_mentioned_p (reg, PATTERN (i1)))
7526 /* If this is USE in front of INSN, we only have to check that
7527 there are no more references than accounted for by inheritance. */
7528 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7530 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7531 i1 = NEXT_INSN (i1);
7533 if (n_occurrences <= n_inherited && i1 == insn)
7539 /* The caller has already checked that REG dies or is set in INSN.
7540 It has also checked that we are optimizing, and thus some inaccurancies
7541 in the debugging information are acceptable.
7542 So we could just delete output_reload_insn.
7543 But in some cases we can improve the debugging information without
7544 sacrificing optimization - maybe even improving the code:
7545 See if the pseudo reg has been completely replaced
7546 with reload regs. If so, delete the store insn
7547 and forget we had a stack slot for the pseudo. */
7548 if (rld[j].out != rld[j].in
7549 && REG_N_DEATHS (REGNO (reg)) == 1
7550 && REG_N_SETS (REGNO (reg)) == 1
7551 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7552 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7556 /* We know that it was used only between here
7557 and the beginning of the current basic block.
7558 (We also know that the last use before INSN was
7559 the output reload we are thinking of deleting, but never mind that.)
7560 Search that range; see if any ref remains. */
7561 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7563 rtx set = single_set (i2);
7565 /* Uses which just store in the pseudo don't count,
7566 since if they are the only uses, they are dead. */
7567 if (set != 0 && SET_DEST (set) == reg)
7569 if (GET_CODE (i2) == CODE_LABEL
7570 || GET_CODE (i2) == JUMP_INSN)
7572 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7573 && reg_mentioned_p (reg, PATTERN (i2)))
7575 /* Some other ref remains; just delete the output reload we
7577 delete_address_reloads (output_reload_insn, insn);
7578 PUT_CODE (output_reload_insn, NOTE);
7579 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7580 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7585 /* Delete the now-dead stores into this pseudo. */
7586 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7588 rtx set = single_set (i2);
7590 if (set != 0 && SET_DEST (set) == reg)
7592 delete_address_reloads (i2, insn);
7593 /* This might be a basic block head,
7594 thus don't use delete_insn. */
7595 PUT_CODE (i2, NOTE);
7596 NOTE_SOURCE_FILE (i2) = 0;
7597 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7599 if (GET_CODE (i2) == CODE_LABEL
7600 || GET_CODE (i2) == JUMP_INSN)
7604 /* For the debugging info,
7605 say the pseudo lives in this reload reg. */
7606 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7607 alter_reg (REGNO (reg), -1);
7609 delete_address_reloads (output_reload_insn, insn);
7610 PUT_CODE (output_reload_insn, NOTE);
7611 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7612 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7616 /* We are going to delete DEAD_INSN. Recursively delete loads of
7617 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7618 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7620 delete_address_reloads (dead_insn, current_insn)
7621 rtx dead_insn, current_insn;
7623 rtx set = single_set (dead_insn);
7624 rtx set2, dst, prev, next;
7627 rtx dst = SET_DEST (set);
7628 if (GET_CODE (dst) == MEM)
7629 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7631 /* If we deleted the store from a reloaded post_{in,de}c expression,
7632 we can delete the matching adds. */
7633 prev = PREV_INSN (dead_insn);
7634 next = NEXT_INSN (dead_insn);
7635 if (! prev || ! next)
7637 set = single_set (next);
7638 set2 = single_set (prev);
7640 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7641 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7642 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7644 dst = SET_DEST (set);
7645 if (! rtx_equal_p (dst, SET_DEST (set2))
7646 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7647 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7648 || (INTVAL (XEXP (SET_SRC (set), 1))
7649 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7655 /* Subfunction of delete_address_reloads: process registers found in X. */
7657 delete_address_reloads_1 (dead_insn, x, current_insn)
7658 rtx dead_insn, x, current_insn;
7660 rtx prev, set, dst, i2;
7662 enum rtx_code code = GET_CODE (x);
7666 const char *fmt = GET_RTX_FORMAT (code);
7667 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7670 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7671 else if (fmt[i] == 'E')
7673 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7674 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7681 if (spill_reg_order[REGNO (x)] < 0)
7684 /* Scan backwards for the insn that sets x. This might be a way back due
7686 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7688 code = GET_CODE (prev);
7689 if (code == CODE_LABEL || code == JUMP_INSN)
7691 if (GET_RTX_CLASS (code) != 'i')
7693 if (reg_set_p (x, PATTERN (prev)))
7695 if (reg_referenced_p (x, PATTERN (prev)))
7698 if (! prev || INSN_UID (prev) < reload_first_uid)
7700 /* Check that PREV only sets the reload register. */
7701 set = single_set (prev);
7704 dst = SET_DEST (set);
7705 if (GET_CODE (dst) != REG
7706 || ! rtx_equal_p (dst, x))
7708 if (! reg_set_p (dst, PATTERN (dead_insn)))
7710 /* Check if DST was used in a later insn -
7711 it might have been inherited. */
7712 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7714 if (GET_CODE (i2) == CODE_LABEL)
7718 if (reg_referenced_p (dst, PATTERN (i2)))
7720 /* If there is a reference to the register in the current insn,
7721 it might be loaded in a non-inherited reload. If no other
7722 reload uses it, that means the register is set before
7724 if (i2 == current_insn)
7726 for (j = n_reloads - 1; j >= 0; j--)
7727 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7728 || reload_override_in[j] == dst)
7730 for (j = n_reloads - 1; j >= 0; j--)
7731 if (rld[j].in && rld[j].reg_rtx == dst)
7738 if (GET_CODE (i2) == JUMP_INSN)
7740 /* If DST is still live at CURRENT_INSN, check if it is used for
7741 any reload. Note that even if CURRENT_INSN sets DST, we still
7742 have to check the reloads. */
7743 if (i2 == current_insn)
7745 for (j = n_reloads - 1; j >= 0; j--)
7746 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7747 || reload_override_in[j] == dst)
7749 /* ??? We can't finish the loop here, because dst might be
7750 allocated to a pseudo in this block if no reload in this
7751 block needs any of the clsses containing DST - see
7752 spill_hard_reg. There is no easy way to tell this, so we
7753 have to scan till the end of the basic block. */
7755 if (reg_set_p (dst, PATTERN (i2)))
7759 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7760 reg_reloaded_contents[REGNO (dst)] = -1;
7761 /* Can't use delete_insn here because PREV might be a basic block head. */
7762 PUT_CODE (prev, NOTE);
7763 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7764 NOTE_SOURCE_FILE (prev) = 0;
7767 /* Output reload-insns to reload VALUE into RELOADREG.
7768 VALUE is an autoincrement or autodecrement RTX whose operand
7769 is a register or memory location;
7770 so reloading involves incrementing that location.
7771 IN is either identical to VALUE, or some cheaper place to reload from.
7773 INC_AMOUNT is the number to increment or decrement by (always positive).
7774 This cannot be deduced from VALUE.
7776 Return the instruction that stores into RELOADREG. */
7779 inc_for_reload (reloadreg, in, value, inc_amount)
7784 /* REG or MEM to be copied and incremented. */
7785 rtx incloc = XEXP (value, 0);
7786 /* Nonzero if increment after copying. */
7787 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7793 rtx real_in = in == value ? XEXP (in, 0) : in;
7795 /* No hard register is equivalent to this register after
7796 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7797 we could inc/dec that register as well (maybe even using it for
7798 the source), but I'm not sure it's worth worrying about. */
7799 if (GET_CODE (incloc) == REG)
7800 reg_last_reload_reg[REGNO (incloc)] = 0;
7802 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7803 inc_amount = -inc_amount;
7805 inc = GEN_INT (inc_amount);
7807 /* If this is post-increment, first copy the location to the reload reg. */
7808 if (post && real_in != reloadreg)
7809 emit_insn (gen_move_insn (reloadreg, real_in));
7813 /* See if we can directly increment INCLOC. Use a method similar to
7814 that in gen_reload. */
7816 last = get_last_insn ();
7817 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7818 gen_rtx_PLUS (GET_MODE (incloc),
7821 code = recog_memoized (add_insn);
7824 extract_insn (add_insn);
7825 if (constrain_operands (1))
7827 /* If this is a pre-increment and we have incremented the value
7828 where it lives, copy the incremented value to RELOADREG to
7829 be used as an address. */
7832 emit_insn (gen_move_insn (reloadreg, incloc));
7837 delete_insns_since (last);
7840 /* If couldn't do the increment directly, must increment in RELOADREG.
7841 The way we do this depends on whether this is pre- or post-increment.
7842 For pre-increment, copy INCLOC to the reload register, increment it
7843 there, then save back. */
7847 if (in != reloadreg)
7848 emit_insn (gen_move_insn (reloadreg, real_in));
7849 emit_insn (gen_add2_insn (reloadreg, inc));
7850 store = emit_insn (gen_move_insn (incloc, reloadreg));
7855 Because this might be a jump insn or a compare, and because RELOADREG
7856 may not be available after the insn in an input reload, we must do
7857 the incrementation before the insn being reloaded for.
7859 We have already copied IN to RELOADREG. Increment the copy in
7860 RELOADREG, save that back, then decrement RELOADREG so it has
7861 the original value. */
7863 emit_insn (gen_add2_insn (reloadreg, inc));
7864 store = emit_insn (gen_move_insn (incloc, reloadreg));
7865 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7871 /* Return 1 if we are certain that the constraint-string STRING allows
7872 the hard register REG. Return 0 if we can't be sure of this. */
7875 constraint_accepts_reg_p (string, reg)
7880 int regno = true_regnum (reg);
7883 /* Initialize for first alternative. */
7885 /* Check that each alternative contains `g' or `r'. */
7887 switch (c = *string++)
7890 /* If an alternative lacks `g' or `r', we lose. */
7893 /* If an alternative lacks `g' or `r', we lose. */
7896 /* Initialize for next alternative. */
7901 /* Any general reg wins for this alternative. */
7902 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7906 /* Any reg in specified class wins for this alternative. */
7908 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7910 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7916 /* INSN is a no-op; delete it.
7917 If this sets the return value of the function, we must keep a USE around,
7918 in case this is in a different basic block than the final USE. Otherwise,
7919 we could loose important register lifeness information on
7920 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7921 spills: subsequent passes assume that spill registers are dead at the end
7923 VALUE must be the return value in such a case, NULL otherwise. */
7925 reload_cse_delete_noop_set (insn, value)
7930 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7931 INSN_CODE (insn) = -1;
7932 REG_NOTES (insn) = NULL_RTX;
7936 PUT_CODE (insn, NOTE);
7937 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7938 NOTE_SOURCE_FILE (insn) = 0;
7942 /* See whether a single set SET is a noop. */
7944 reload_cse_noop_set_p (set)
7947 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7950 /* Try to simplify INSN. */
7952 reload_cse_simplify (insn)
7955 rtx body = PATTERN (insn);
7957 if (GET_CODE (body) == SET)
7960 if (reload_cse_noop_set_p (body))
7962 rtx value = SET_DEST (body);
7963 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7965 reload_cse_delete_noop_set (insn, value);
7969 /* It's not a no-op, but we can try to simplify it. */
7970 count += reload_cse_simplify_set (body, insn);
7973 apply_change_group ();
7975 reload_cse_simplify_operands (insn);
7977 else if (GET_CODE (body) == PARALLEL)
7981 rtx value = NULL_RTX;
7983 /* If every action in a PARALLEL is a noop, we can delete
7984 the entire PARALLEL. */
7985 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7987 rtx part = XVECEXP (body, 0, i);
7988 if (GET_CODE (part) == SET)
7990 if (! reload_cse_noop_set_p (part))
7992 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7996 value = SET_DEST (part);
7999 else if (GET_CODE (part) != CLOBBER)
8005 reload_cse_delete_noop_set (insn, value);
8006 /* We're done with this insn. */
8010 /* It's not a no-op, but we can try to simplify it. */
8011 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8012 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8013 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8016 apply_change_group ();
8018 reload_cse_simplify_operands (insn);
8022 /* Do a very simple CSE pass over the hard registers.
8024 This function detects no-op moves where we happened to assign two
8025 different pseudo-registers to the same hard register, and then
8026 copied one to the other. Reload will generate a useless
8027 instruction copying a register to itself.
8029 This function also detects cases where we load a value from memory
8030 into two different registers, and (if memory is more expensive than
8031 registers) changes it to simply copy the first register into the
8034 Another optimization is performed that scans the operands of each
8035 instruction to see whether the value is already available in a
8036 hard register. It then replaces the operand with the hard register
8037 if possible, much like an optional reload would. */
8040 reload_cse_regs_1 (first)
8046 init_alias_analysis ();
8048 for (insn = first; insn; insn = NEXT_INSN (insn))
8051 reload_cse_simplify (insn);
8053 cselib_process_insn (insn);
8057 end_alias_analysis ();
8061 /* Call cse / combine like post-reload optimization phases.
8062 FIRST is the first instruction. */
8064 reload_cse_regs (first)
8067 reload_cse_regs_1 (first);
8069 reload_cse_move2add (first);
8070 if (flag_expensive_optimizations)
8071 reload_cse_regs_1 (first);
8074 /* Try to simplify a single SET instruction. SET is the set pattern.
8075 INSN is the instruction it came from.
8076 This function only handles one case: if we set a register to a value
8077 which is not a register, we try to find that value in some other register
8078 and change the set into a register copy. */
8081 reload_cse_simplify_set (set, insn)
8088 enum reg_class dclass;
8091 struct elt_loc_list *l;
8093 dreg = true_regnum (SET_DEST (set));
8097 src = SET_SRC (set);
8098 if (side_effects_p (src) || true_regnum (src) >= 0)
8101 dclass = REGNO_REG_CLASS (dreg);
8103 /* If memory loads are cheaper than register copies, don't change them. */
8104 if (GET_CODE (src) == MEM)
8105 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8106 else if (CONSTANT_P (src))
8107 old_cost = rtx_cost (src, SET);
8108 else if (GET_CODE (src) == REG)
8109 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8112 old_cost = rtx_cost (src, SET);
8114 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8117 for (l = val->locs; l; l = l->next)
8120 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8121 this_cost = rtx_cost (l->loc, SET);
8122 else if (GET_CODE (l->loc) == REG)
8123 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8127 /* If equal costs, prefer registers over anything else. That tends to
8128 lead to smaller instructions on some machines. */
8129 if ((this_cost < old_cost
8130 || (this_cost == old_cost
8131 && GET_CODE (l->loc) == REG
8132 && GET_CODE (SET_SRC (set)) != REG))
8133 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8134 old_cost = this_cost, did_change = 1;
8140 /* Try to replace operands in INSN with equivalent values that are already
8141 in registers. This can be viewed as optional reloading.
8143 For each non-register operand in the insn, see if any hard regs are
8144 known to be equivalent to that operand. Record the alternatives which
8145 can accept these hard registers. Among all alternatives, select the
8146 ones which are better or equal to the one currently matching, where
8147 "better" is in terms of '?' and '!' constraints. Among the remaining
8148 alternatives, select the one which replaces most operands with
8152 reload_cse_simplify_operands (insn)
8157 /* For each operand, all registers that are equivalent to it. */
8158 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8160 const char *constraints[MAX_RECOG_OPERANDS];
8162 /* Vector recording how bad an alternative is. */
8163 int *alternative_reject;
8164 /* Vector recording how many registers can be introduced by choosing
8165 this alternative. */
8166 int *alternative_nregs;
8167 /* Array of vectors recording, for each operand and each alternative,
8168 which hard register to substitute, or -1 if the operand should be
8170 int *op_alt_regno[MAX_RECOG_OPERANDS];
8171 /* Array of alternatives, sorted in order of decreasing desirability. */
8172 int *alternative_order;
8173 rtx reg = gen_rtx_REG (VOIDmode, -1);
8175 extract_insn (insn);
8177 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8180 /* Figure out which alternative currently matches. */
8181 if (! constrain_operands (1))
8182 fatal_insn_not_found (insn);
8184 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8185 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8186 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8187 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8188 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8190 /* For each operand, find out which regs are equivalent. */
8191 for (i = 0; i < recog_data.n_operands; i++)
8194 struct elt_loc_list *l;
8196 CLEAR_HARD_REG_SET (equiv_regs[i]);
8198 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8199 right, so avoid the problem here. Likewise if we have a constant
8200 and the insn pattern doesn't tell us the mode we need. */
8201 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8202 || (CONSTANT_P (recog_data.operand[i])
8203 && recog_data.operand_mode[i] == VOIDmode))
8206 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8210 for (l = v->locs; l; l = l->next)
8211 if (GET_CODE (l->loc) == REG)
8212 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8215 for (i = 0; i < recog_data.n_operands; i++)
8217 enum machine_mode mode;
8221 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8222 for (j = 0; j < recog_data.n_alternatives; j++)
8223 op_alt_regno[i][j] = -1;
8225 p = constraints[i] = recog_data.constraints[i];
8226 mode = recog_data.operand_mode[i];
8228 /* Add the reject values for each alternative given by the constraints
8229 for this operand. */
8237 alternative_reject[j] += 3;
8239 alternative_reject[j] += 300;
8242 /* We won't change operands which are already registers. We
8243 also don't want to modify output operands. */
8244 regno = true_regnum (recog_data.operand[i]);
8246 || constraints[i][0] == '='
8247 || constraints[i][0] == '+')
8250 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8252 int class = (int) NO_REGS;
8254 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8257 REGNO (reg) = regno;
8258 PUT_MODE (reg, mode);
8260 /* We found a register equal to this operand. Now look for all
8261 alternatives that can accept this register and have not been
8262 assigned a register they can use yet. */
8271 case '=': case '+': case '?':
8272 case '#': case '&': case '!':
8274 case '0': case '1': case '2': case '3': case '4':
8275 case '5': case '6': case '7': case '8': case '9':
8276 case 'm': case '<': case '>': case 'V': case 'o':
8277 case 'E': case 'F': case 'G': case 'H':
8278 case 's': case 'i': case 'n':
8279 case 'I': case 'J': case 'K': case 'L':
8280 case 'M': case 'N': case 'O': case 'P':
8282 /* These don't say anything we care about. */
8286 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8291 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8294 case ',': case '\0':
8295 /* See if REGNO fits this alternative, and set it up as the
8296 replacement register if we don't have one for this
8297 alternative yet and the operand being replaced is not
8298 a cheap CONST_INT. */
8299 if (op_alt_regno[i][j] == -1
8300 && reg_fits_class_p (reg, class, 0, mode)
8301 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8302 || (rtx_cost (recog_data.operand[i], SET)
8303 > rtx_cost (reg, SET))))
8305 alternative_nregs[j]++;
8306 op_alt_regno[i][j] = regno;
8318 /* Record all alternatives which are better or equal to the currently
8319 matching one in the alternative_order array. */
8320 for (i = j = 0; i < recog_data.n_alternatives; i++)
8321 if (alternative_reject[i] <= alternative_reject[which_alternative])
8322 alternative_order[j++] = i;
8323 recog_data.n_alternatives = j;
8325 /* Sort it. Given a small number of alternatives, a dumb algorithm
8326 won't hurt too much. */
8327 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8330 int best_reject = alternative_reject[alternative_order[i]];
8331 int best_nregs = alternative_nregs[alternative_order[i]];
8334 for (j = i + 1; j < recog_data.n_alternatives; j++)
8336 int this_reject = alternative_reject[alternative_order[j]];
8337 int this_nregs = alternative_nregs[alternative_order[j]];
8339 if (this_reject < best_reject
8340 || (this_reject == best_reject && this_nregs < best_nregs))
8343 best_reject = this_reject;
8344 best_nregs = this_nregs;
8348 tmp = alternative_order[best];
8349 alternative_order[best] = alternative_order[i];
8350 alternative_order[i] = tmp;
8353 /* Substitute the operands as determined by op_alt_regno for the best
8355 j = alternative_order[0];
8357 for (i = 0; i < recog_data.n_operands; i++)
8359 enum machine_mode mode = recog_data.operand_mode[i];
8360 if (op_alt_regno[i][j] == -1)
8363 validate_change (insn, recog_data.operand_loc[i],
8364 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8367 for (i = recog_data.n_dups - 1; i >= 0; i--)
8369 int op = recog_data.dup_num[i];
8370 enum machine_mode mode = recog_data.operand_mode[op];
8372 if (op_alt_regno[op][j] == -1)
8375 validate_change (insn, recog_data.dup_loc[i],
8376 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8379 return apply_change_group ();
8382 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8384 This code might also be useful when reload gave up on reg+reg addresssing
8385 because of clashes between the return register and INDEX_REG_CLASS. */
8387 /* The maximum number of uses of a register we can keep track of to
8388 replace them with reg+reg addressing. */
8389 #define RELOAD_COMBINE_MAX_USES 6
8391 /* INSN is the insn where a register has ben used, and USEP points to the
8392 location of the register within the rtl. */
8393 struct reg_use { rtx insn, *usep; };
8395 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8396 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8397 indicates where it becomes live again.
8398 Otherwise, USE_INDEX is the index of the last encountered use of the
8399 register (which is first among these we have seen since we scan backwards),
8400 OFFSET contains the constant offset that is added to the register in
8401 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8402 last, of these uses.
8403 STORE_RUID is always meaningful if we only want to use a value in a
8404 register in a different place: it denotes the next insn in the insn
8405 stream (i.e. the last ecountered) that sets or clobbers the register. */
8408 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8413 } reg_state[FIRST_PSEUDO_REGISTER];
8415 /* Reverse linear uid. This is increased in reload_combine while scanning
8416 the instructions from last to first. It is used to set last_label_ruid
8417 and the store_ruid / use_ruid fields in reg_state. */
8418 static int reload_combine_ruid;
8420 #define LABEL_LIVE(LABEL) \
8421 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8427 int first_index_reg = -1, last_index_reg;
8430 int last_label_ruid;
8431 int min_labelno, n_labels;
8432 HARD_REG_SET ever_live_at_start, *label_live;
8434 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8435 reload has already used it where appropriate, so there is no use in
8436 trying to generate it now. */
8437 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8440 /* To avoid wasting too much time later searching for an index register,
8441 determine the minimum and maximum index register numbers. */
8442 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8443 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8445 if (first_index_reg == -1)
8446 first_index_reg = r;
8451 /* If no index register is available, we can quit now. */
8452 if (first_index_reg == -1)
8455 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8456 information is a bit fuzzy immediately after reload, but it's
8457 still good enough to determine which registers are live at a jump
8459 min_labelno = get_first_label_num ();
8460 n_labels = max_label_num () - min_labelno;
8461 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8462 CLEAR_HARD_REG_SET (ever_live_at_start);
8464 for (i = n_basic_blocks - 1; i >= 0; i--)
8466 insn = BLOCK_HEAD (i);
8467 if (GET_CODE (insn) == CODE_LABEL)
8471 REG_SET_TO_HARD_REG_SET (live,
8472 BASIC_BLOCK (i)->global_live_at_start);
8473 compute_use_by_pseudos (&live,
8474 BASIC_BLOCK (i)->global_live_at_start);
8475 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8476 IOR_HARD_REG_SET (ever_live_at_start, live);
8480 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8481 last_label_ruid = reload_combine_ruid = 0;
8482 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8484 reg_state[r].store_ruid = reload_combine_ruid;
8486 reg_state[r].use_index = -1;
8488 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8491 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8495 /* We cannot do our optimization across labels. Invalidating all the use
8496 information we have would be costly, so we just note where the label
8497 is and then later disable any optimization that would cross it. */
8498 if (GET_CODE (insn) == CODE_LABEL)
8499 last_label_ruid = reload_combine_ruid;
8500 else if (GET_CODE (insn) == BARRIER)
8501 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8502 if (! fixed_regs[r])
8503 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8505 if (! INSN_P (insn))
8508 reload_combine_ruid++;
8510 /* Look for (set (REGX) (CONST_INT))
8511 (set (REGX) (PLUS (REGX) (REGY)))
8513 ... (MEM (REGX)) ...
8515 (set (REGZ) (CONST_INT))
8517 ... (MEM (PLUS (REGZ) (REGY)))... .
8519 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8520 and that we know all uses of REGX before it dies. */
8521 set = single_set (insn);
8523 && GET_CODE (SET_DEST (set)) == REG
8524 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8525 GET_MODE (SET_DEST (set)))
8527 && GET_CODE (SET_SRC (set)) == PLUS
8528 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8529 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8530 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8532 rtx reg = SET_DEST (set);
8533 rtx plus = SET_SRC (set);
8534 rtx base = XEXP (plus, 1);
8535 rtx prev = prev_nonnote_insn (insn);
8536 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8537 unsigned int regno = REGNO (reg);
8538 rtx const_reg = NULL_RTX;
8539 rtx reg_sum = NULL_RTX;
8541 /* Now, we need an index register.
8542 We'll set index_reg to this index register, const_reg to the
8543 register that is to be loaded with the constant
8544 (denoted as REGZ in the substitution illustration above),
8545 and reg_sum to the register-register that we want to use to
8546 substitute uses of REG (typically in MEMs) with.
8547 First check REG and BASE for being index registers;
8548 we can use them even if they are not dead. */
8549 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8550 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8558 /* Otherwise, look for a free index register. Since we have
8559 checked above that neiter REG nor BASE are index registers,
8560 if we find anything at all, it will be different from these
8562 for (i = first_index_reg; i <= last_index_reg; i++)
8564 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8566 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8567 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8568 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8570 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8572 const_reg = index_reg;
8573 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8579 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8580 (REGY), i.e. BASE, is not clobbered before the last use we'll
8583 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8584 && rtx_equal_p (SET_DEST (prev_set), reg)
8585 && reg_state[regno].use_index >= 0
8586 && (reg_state[REGNO (base)].store_ruid
8587 <= reg_state[regno].use_ruid)
8592 /* Change destination register and, if necessary, the
8593 constant value in PREV, the constant loading instruction. */
8594 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8595 if (reg_state[regno].offset != const0_rtx)
8596 validate_change (prev,
8597 &SET_SRC (prev_set),
8598 GEN_INT (INTVAL (SET_SRC (prev_set))
8599 + INTVAL (reg_state[regno].offset)),
8602 /* Now for every use of REG that we have recorded, replace REG
8604 for (i = reg_state[regno].use_index;
8605 i < RELOAD_COMBINE_MAX_USES; i++)
8606 validate_change (reg_state[regno].reg_use[i].insn,
8607 reg_state[regno].reg_use[i].usep,
8610 if (apply_change_group ())
8614 /* Delete the reg-reg addition. */
8615 PUT_CODE (insn, NOTE);
8616 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8617 NOTE_SOURCE_FILE (insn) = 0;
8619 if (reg_state[regno].offset != const0_rtx)
8620 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8622 for (np = ®_NOTES (prev); *np;)
8624 if (REG_NOTE_KIND (*np) == REG_EQUAL
8625 || REG_NOTE_KIND (*np) == REG_EQUIV)
8626 *np = XEXP (*np, 1);
8628 np = &XEXP (*np, 1);
8631 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8632 reg_state[REGNO (const_reg)].store_ruid
8633 = reload_combine_ruid;
8639 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8641 if (GET_CODE (insn) == CALL_INSN)
8645 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8646 if (call_used_regs[r])
8648 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8649 reg_state[r].store_ruid = reload_combine_ruid;
8652 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8653 link = XEXP (link, 1))
8654 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8656 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8658 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8660 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8661 reg_state[regno].store_ruid = reload_combine_ruid;
8664 reg_state[regno].use_index = -1;
8668 else if (GET_CODE (insn) == JUMP_INSN
8669 && GET_CODE (PATTERN (insn)) != RETURN)
8671 /* Non-spill registers might be used at the call destination in
8672 some unknown fashion, so we have to mark the unknown use. */
8675 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8676 && JUMP_LABEL (insn))
8677 live = &LABEL_LIVE (JUMP_LABEL (insn));
8679 live = &ever_live_at_start;
8681 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8682 if (TEST_HARD_REG_BIT (*live, i))
8683 reg_state[i].use_index = -1;
8686 reload_combine_note_use (&PATTERN (insn), insn);
8687 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8689 if (REG_NOTE_KIND (note) == REG_INC
8690 && GET_CODE (XEXP (note, 0)) == REG)
8692 int regno = REGNO (XEXP (note, 0));
8694 reg_state[regno].store_ruid = reload_combine_ruid;
8695 reg_state[regno].use_index = -1;
8703 /* Check if DST is a register or a subreg of a register; if it is,
8704 update reg_state[regno].store_ruid and reg_state[regno].use_index
8705 accordingly. Called via note_stores from reload_combine. */
8708 reload_combine_note_store (dst, set, data)
8710 void *data ATTRIBUTE_UNUSED;
8714 enum machine_mode mode = GET_MODE (dst);
8716 if (GET_CODE (dst) == SUBREG)
8718 regno = SUBREG_WORD (dst);
8719 dst = SUBREG_REG (dst);
8721 if (GET_CODE (dst) != REG)
8723 regno += REGNO (dst);
8725 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8726 careful with registers / register parts that are not full words.
8728 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8729 if (GET_CODE (set) != SET
8730 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8731 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8732 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8734 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8736 reg_state[i].use_index = -1;
8737 reg_state[i].store_ruid = reload_combine_ruid;
8742 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8744 reg_state[i].store_ruid = reload_combine_ruid;
8745 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8750 /* XP points to a piece of rtl that has to be checked for any uses of
8752 *XP is the pattern of INSN, or a part of it.
8753 Called from reload_combine, and recursively by itself. */
8755 reload_combine_note_use (xp, insn)
8759 enum rtx_code code = x->code;
8762 rtx offset = const0_rtx; /* For the REG case below. */
8767 if (GET_CODE (SET_DEST (x)) == REG)
8769 reload_combine_note_use (&SET_SRC (x), insn);
8775 /* If this is the USE of a return value, we can't change it. */
8776 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8778 /* Mark the return register as used in an unknown fashion. */
8779 rtx reg = XEXP (x, 0);
8780 int regno = REGNO (reg);
8781 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8783 while (--nregs >= 0)
8784 reg_state[regno + nregs].use_index = -1;
8790 if (GET_CODE (SET_DEST (x)) == REG)
8795 /* We are interested in (plus (reg) (const_int)) . */
8796 if (GET_CODE (XEXP (x, 0)) != REG
8797 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8799 offset = XEXP (x, 1);
8804 int regno = REGNO (x);
8808 /* Some spurious USEs of pseudo registers might remain.
8809 Just ignore them. */
8810 if (regno >= FIRST_PSEUDO_REGISTER)
8813 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8815 /* We can't substitute into multi-hard-reg uses. */
8818 while (--nregs >= 0)
8819 reg_state[regno + nregs].use_index = -1;
8823 /* If this register is already used in some unknown fashion, we
8825 If we decrement the index from zero to -1, we can't store more
8826 uses, so this register becomes used in an unknown fashion. */
8827 use_index = --reg_state[regno].use_index;
8831 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8833 /* We have found another use for a register that is already
8834 used later. Check if the offsets match; if not, mark the
8835 register as used in an unknown fashion. */
8836 if (! rtx_equal_p (offset, reg_state[regno].offset))
8838 reg_state[regno].use_index = -1;
8844 /* This is the first use of this register we have seen since we
8845 marked it as dead. */
8846 reg_state[regno].offset = offset;
8847 reg_state[regno].use_ruid = reload_combine_ruid;
8849 reg_state[regno].reg_use[use_index].insn = insn;
8850 reg_state[regno].reg_use[use_index].usep = xp;
8858 /* Recursively process the components of X. */
8859 fmt = GET_RTX_FORMAT (code);
8860 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8863 reload_combine_note_use (&XEXP (x, i), insn);
8864 else if (fmt[i] == 'E')
8866 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8867 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8872 /* See if we can reduce the cost of a constant by replacing a move with
8874 /* We cannot do our optimization across labels. Invalidating all the
8875 information about register contents we have would be costly, so we
8876 use last_label_luid (local variable of reload_cse_move2add) to note
8877 where the label is and then later disable any optimization that would
8879 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8880 reg_set_luid[n] is larger than last_label_luid[n] . */
8881 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8883 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8884 reg_mode[n] to be valid.
8885 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8886 has been set to reg_offset[n] in mode reg_mode[n] .
8887 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8888 register n has been set to the sum of reg_offset[n] and register
8889 reg_base_reg[n], calculated in mode reg_mode[n] . */
8890 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8891 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8892 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8894 /* move2add_luid is linearily increased while scanning the instructions
8895 from first to last. It is used to set reg_set_luid in
8896 reload_cse_move2add and move2add_note_store. */
8897 static int move2add_luid;
8899 /* Generate a CONST_INT and force it in the range of MODE. */
8902 gen_mode_int (mode, value)
8903 enum machine_mode mode;
8904 HOST_WIDE_INT value;
8906 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8907 int width = GET_MODE_BITSIZE (mode);
8909 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8911 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8912 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8913 cval |= (HOST_WIDE_INT) -1 << width;
8915 return GEN_INT (cval);
8919 reload_cse_move2add (first)
8924 int last_label_luid;
8926 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8927 reg_set_luid[i] = 0;
8929 last_label_luid = 0;
8931 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8935 if (GET_CODE (insn) == CODE_LABEL)
8936 last_label_luid = move2add_luid;
8937 if (! INSN_P (insn))
8939 pat = PATTERN (insn);
8940 /* For simplicity, we only perform this optimization on
8941 straightforward SETs. */
8942 if (GET_CODE (pat) == SET
8943 && GET_CODE (SET_DEST (pat)) == REG)
8945 rtx reg = SET_DEST (pat);
8946 int regno = REGNO (reg);
8947 rtx src = SET_SRC (pat);
8949 /* Check if we have valid information on the contents of this
8950 register in the mode of REG. */
8951 /* ??? We don't know how zero / sign extension is handled, hence
8952 we can't go from a narrower to a wider mode. */
8953 if (reg_set_luid[regno] > last_label_luid
8954 && ((GET_MODE_SIZE (GET_MODE (reg))
8955 == GET_MODE_SIZE (reg_mode[regno]))
8956 || ((GET_MODE_SIZE (GET_MODE (reg))
8957 <= GET_MODE_SIZE (reg_mode[regno]))
8958 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8959 GET_MODE_BITSIZE (reg_mode[regno]))))
8960 && GET_CODE (reg_offset[regno]) == CONST_INT)
8962 /* Try to transform (set (REGX) (CONST_INT A))
8964 (set (REGX) (CONST_INT B))
8966 (set (REGX) (CONST_INT A))
8968 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8970 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8974 = gen_mode_int (GET_MODE (reg),
8975 INTVAL (src) - INTVAL (reg_offset[regno]));
8976 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8977 use (set (reg) (reg)) instead.
8978 We don't delete this insn, nor do we convert it into a
8979 note, to avoid losing register notes or the return
8980 value flag. jump2 already knowns how to get rid of
8982 if (new_src == const0_rtx)
8983 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8984 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8985 && have_add2_insn (GET_MODE (reg)))
8986 success = validate_change (insn, &PATTERN (insn),
8987 gen_add2_insn (reg, new_src), 0);
8988 reg_set_luid[regno] = move2add_luid;
8989 reg_mode[regno] = GET_MODE (reg);
8990 reg_offset[regno] = src;
8994 /* Try to transform (set (REGX) (REGY))
8995 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8998 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9001 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9003 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9004 else if (GET_CODE (src) == REG
9005 && reg_base_reg[regno] == (int) REGNO (src)
9006 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9008 rtx next = next_nonnote_insn (insn);
9011 set = single_set (next);
9014 && SET_DEST (set) == reg
9015 && GET_CODE (SET_SRC (set)) == PLUS
9016 && XEXP (SET_SRC (set), 0) == reg
9017 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9019 rtx src3 = XEXP (SET_SRC (set), 1);
9021 = gen_mode_int (GET_MODE (reg),
9023 - INTVAL (reg_offset[regno]));
9026 if (new_src == const0_rtx)
9027 /* See above why we create (set (reg) (reg)) here. */
9029 = validate_change (next, &SET_SRC (set), reg, 0);
9030 else if ((rtx_cost (new_src, PLUS)
9031 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9032 && have_add2_insn (GET_MODE (reg)))
9034 = validate_change (next, &PATTERN (next),
9035 gen_add2_insn (reg, new_src), 0);
9038 /* INSN might be the first insn in a basic block
9039 if the preceding insn is a conditional jump
9040 or a possible-throwing call. */
9041 PUT_CODE (insn, NOTE);
9042 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9043 NOTE_SOURCE_FILE (insn) = 0;
9046 reg_set_luid[regno] = move2add_luid;
9047 reg_mode[regno] = GET_MODE (reg);
9048 reg_offset[regno] = src3;
9055 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9057 if (REG_NOTE_KIND (note) == REG_INC
9058 && GET_CODE (XEXP (note, 0)) == REG)
9060 /* Indicate that this register has been recently written to,
9061 but the exact contents are not available. */
9062 int regno = REGNO (XEXP (note, 0));
9063 if (regno < FIRST_PSEUDO_REGISTER)
9065 reg_set_luid[regno] = move2add_luid;
9066 reg_offset[regno] = note;
9070 note_stores (PATTERN (insn), move2add_note_store, NULL);
9071 /* If this is a CALL_INSN, all call used registers are stored with
9073 if (GET_CODE (insn) == CALL_INSN)
9075 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9077 if (call_used_regs[i])
9079 reg_set_luid[i] = move2add_luid;
9080 reg_offset[i] = insn; /* Invalidate contents. */
9087 /* SET is a SET or CLOBBER that sets DST.
9088 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9089 Called from reload_cse_move2add via note_stores. */
9092 move2add_note_store (dst, set, data)
9094 void *data ATTRIBUTE_UNUSED;
9096 unsigned int regno = 0;
9098 enum machine_mode mode = GET_MODE (dst);
9100 if (GET_CODE (dst) == SUBREG)
9102 regno = SUBREG_WORD (dst);
9103 dst = SUBREG_REG (dst);
9106 /* Some targets do argument pushes without adding REG_INC notes. */
9108 if (GET_CODE (dst) == MEM)
9110 dst = XEXP (dst, 0);
9111 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9112 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9114 regno = REGNO (XEXP (dst, 0));
9115 reg_set_luid[regno] = move2add_luid;
9116 reg_offset[regno] = dst;
9120 if (GET_CODE (dst) != REG)
9123 regno += REGNO (dst);
9125 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9126 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9127 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9128 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9130 rtx src = SET_SRC (set);
9132 reg_mode[regno] = mode;
9133 switch (GET_CODE (src))
9137 rtx src0 = XEXP (src, 0);
9139 if (GET_CODE (src0) == REG)
9141 if (REGNO (src0) != regno
9142 || reg_offset[regno] != const0_rtx)
9144 reg_base_reg[regno] = REGNO (src0);
9145 reg_set_luid[regno] = move2add_luid;
9148 reg_offset[regno] = XEXP (src, 1);
9152 reg_set_luid[regno] = move2add_luid;
9153 reg_offset[regno] = set; /* Invalidate contents. */
9158 reg_base_reg[regno] = REGNO (SET_SRC (set));
9159 reg_offset[regno] = const0_rtx;
9160 reg_set_luid[regno] = move2add_luid;
9164 reg_base_reg[regno] = -1;
9165 reg_offset[regno] = SET_SRC (set);
9166 reg_set_luid[regno] = move2add_luid;
9172 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9174 for (i = regno; i < endregno; i++)
9176 /* Indicate that this register has been recently written to,
9177 but the exact contents are not available. */
9178 reg_set_luid[i] = move2add_luid;
9179 reg_offset[i] = dst;
9186 add_auto_inc_notes (insn, x)
9190 enum rtx_code code = GET_CODE (x);
9194 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9197 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9201 /* Scan all the operand sub-expressions. */
9202 fmt = GET_RTX_FORMAT (code);
9203 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9206 add_auto_inc_notes (insn, XEXP (x, i));
9207 else if (fmt[i] == 'E')
9208 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9209 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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