1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
35 #include "basic-block.h"
43 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
44 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 #ifndef REGISTER_MOVE_COST
82 #define REGISTER_MOVE_COST(m, x, y) 2
86 #define LOCAL_REGNO(REGNO) 0
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx *reg_equiv_constant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx *reg_equiv_address;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx *reg_equiv_init;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs[FIRST_PSEUDO_REGISTER];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET *pseudo_previous_regs;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET *pseudo_forbidden_regs;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table *reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 static void replace_pseudos_in_call_usage PARAMS((rtx *,
374 static void maybe_fix_stack_asms PARAMS ((void));
375 static void copy_reloads PARAMS ((struct insn_chain *));
376 static void calculate_needs_all_insns PARAMS ((int));
377 static int find_reg PARAMS ((struct insn_chain *, int));
378 static void find_reload_regs PARAMS ((struct insn_chain *));
379 static void select_reload_regs PARAMS ((void));
380 static void delete_caller_save_insns PARAMS ((void));
382 static void spill_failure PARAMS ((rtx, enum reg_class));
383 static void count_spilled_pseudo PARAMS ((int, int, int));
384 static void delete_dead_insn PARAMS ((rtx));
385 static void alter_reg PARAMS ((int, int));
386 static void set_label_offsets PARAMS ((rtx, rtx, int));
387 static void check_eliminable_occurrences PARAMS ((rtx));
388 static void elimination_effects PARAMS ((rtx, enum machine_mode));
389 static int eliminate_regs_in_insn PARAMS ((rtx, int));
390 static void update_eliminable_offsets PARAMS ((void));
391 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
392 static void set_initial_elim_offsets PARAMS ((void));
393 static void verify_initial_elim_offsets PARAMS ((void));
394 static void set_initial_label_offsets PARAMS ((void));
395 static void set_offsets_for_label PARAMS ((rtx));
396 static void init_elim_table PARAMS ((void));
397 static void update_eliminables PARAMS ((HARD_REG_SET *));
398 static void spill_hard_reg PARAMS ((unsigned int, int));
399 static int finish_spills PARAMS ((int));
400 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
401 static void scan_paradoxical_subregs PARAMS ((rtx));
402 static void count_pseudo PARAMS ((int));
403 static void order_regs_for_reload PARAMS ((struct insn_chain *));
404 static void reload_as_needed PARAMS ((int));
405 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
406 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
407 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
410 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
413 static int reload_reg_free_p PARAMS ((unsigned int, int,
415 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
417 rtx, rtx, int, int));
418 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
419 enum reload_type, rtx, rtx,
421 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
423 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
425 static int conflicts_with_override PARAMS ((rtx));
426 static void failed_reload PARAMS ((rtx, int));
427 static int set_reload_reg PARAMS ((int, int));
428 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
429 static void choose_reload_regs PARAMS ((struct insn_chain *));
430 static void merge_assigned_reloads PARAMS ((rtx));
431 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, rtx, int));
433 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_input_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void do_output_reload PARAMS ((struct insn_chain *,
438 struct reload *, int));
439 static void emit_reload_insns PARAMS ((struct insn_chain *));
440 static void delete_output_reload PARAMS ((rtx, int, int));
441 static void delete_address_reloads PARAMS ((rtx, rtx));
442 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
443 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
444 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
445 static void reload_cse_regs_1 PARAMS ((rtx));
446 static int reload_cse_noop_set_p PARAMS ((rtx));
447 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
448 static int reload_cse_simplify_operands PARAMS ((rtx));
449 static void reload_combine PARAMS ((void));
450 static void reload_combine_note_use PARAMS ((rtx *, rtx));
451 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
452 static void reload_cse_move2add PARAMS ((rtx));
453 static void move2add_note_store PARAMS ((rtx, rtx, void *));
455 static void add_auto_inc_notes PARAMS ((rtx, rtx));
457 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
459 static void failed_reload PARAMS ((rtx, int));
460 static int set_reload_reg PARAMS ((int, int));
461 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
462 static void reload_cse_simplify PARAMS ((rtx));
463 extern void dump_needs PARAMS ((struct insn_chain *));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode,
480 LAST_VIRTUAL_REGISTER + 1),
482 spill_indirect_levels = 0;
484 while (memory_address_p (QImode, tem))
486 spill_indirect_levels++;
487 tem = gen_rtx_MEM (Pmode, tem);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
493 indirect_symref_ok = memory_address_p (QImode, tem);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
499 tem = gen_rtx_PLUS (Pmode,
500 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
501 gen_rtx_REG (Pmode, i));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem = plus_constant (tem, 4);
506 if (memory_address_p (QImode, tem))
508 double_reg_address_ok = 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack);
515 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
517 INIT_REG_SET (&spilled_pseudos);
518 INIT_REG_SET (&pseudos_counted);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain *unused_insn_chains = 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain *c;
530 if (unused_insn_chains == 0)
532 c = (struct insn_chain *)
533 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
534 INIT_REG_SET (&c->live_throughout);
535 INIT_REG_SET (&c->dead_or_set);
539 c = unused_insn_chains;
540 unused_insn_chains = c->next;
542 c->is_caller_save_insn = 0;
543 c->need_operand_change = 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to, from)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from, FIRST_PSEUDO_REGISTER, regno,
562 int r = reg_renumber[regno];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed)
576 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
578 SET_HARD_REG_BIT (*to, r + nregs);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc, mem_mode, usage)
589 enum machine_mode mem_mode;
603 int regno = REGNO (x);
605 if (regno < FIRST_PSEUDO_REGISTER)
608 x = eliminate_regs (x, mem_mode, usage);
612 replace_pseudos_in_call_usage (loc, mem_mode, usage);
616 if (reg_equiv_constant[regno])
617 *loc = reg_equiv_constant[regno];
618 else if (reg_equiv_mem[regno])
619 *loc = reg_equiv_mem[regno];
620 else if (reg_equiv_address[regno])
621 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 else if (GET_CODE (regno_reg_rtx[regno]) != REG
623 || REGNO (regno_reg_rtx[regno]) != regno)
624 *loc = regno_reg_rtx[regno];
630 else if (code == MEM)
632 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
636 /* Process each of our operands recursively. */
637 fmt = GET_RTX_FORMAT (code);
638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
640 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
641 else if (*fmt == 'E')
642 for (j = 0; j < XVECLEN (x, i); j++)
643 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first, global)
677 register struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL_PTR;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL_PTR, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
741 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
742 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
743 pseudo_forbidden_regs
744 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
746 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
748 CLEAR_HARD_REG_SET (bad_spill_regs_global);
750 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
751 Also find all paradoxical subregs and find largest such for each pseudo.
752 On machines with small register classes, record hard registers that
753 are used for user variables. These can never be used for spills.
754 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
755 caller-saved registers must be marked live. */
757 num_eliminable_invariants = 0;
758 for (insn = first; insn; insn = NEXT_INSN (insn))
760 rtx set = single_set (insn);
762 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
763 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
764 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
765 if (! call_used_regs[i])
766 regs_ever_live[i] = 1;
768 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
770 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
772 #ifdef LEGITIMATE_PIC_OPERAND_P
773 && (! function_invariant_p (XEXP (note, 0))
775 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
779 rtx x = XEXP (note, 0);
780 i = REGNO (SET_DEST (set));
781 if (i > LAST_VIRTUAL_REGISTER)
783 if (GET_CODE (x) == MEM)
785 /* If the operand is a PLUS, the MEM may be shared,
786 so make sure we have an unshared copy here. */
787 if (GET_CODE (XEXP (x, 0)) == PLUS)
790 reg_equiv_memory_loc[i] = x;
792 else if (function_invariant_p (x))
794 if (GET_CODE (x) == PLUS)
796 /* This is PLUS of frame pointer and a constant,
797 and might be shared. Unshare it. */
798 reg_equiv_constant[i] = copy_rtx (x);
799 num_eliminable_invariants++;
801 else if (x == frame_pointer_rtx
802 || x == arg_pointer_rtx)
804 reg_equiv_constant[i] = x;
805 num_eliminable_invariants++;
807 else if (LEGITIMATE_CONSTANT_P (x))
808 reg_equiv_constant[i] = x;
810 reg_equiv_memory_loc[i]
811 = force_const_mem (GET_MODE (SET_DEST (set)), x);
816 /* If this register is being made equivalent to a MEM
817 and the MEM is not SET_SRC, the equivalencing insn
818 is one with the MEM as a SET_DEST and it occurs later.
819 So don't mark this insn now. */
820 if (GET_CODE (x) != MEM
821 || rtx_equal_p (SET_SRC (set), x))
823 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
828 /* If this insn is setting a MEM from a register equivalent to it,
829 this is the equivalencing insn. */
830 else if (set && GET_CODE (SET_DEST (set)) == MEM
831 && GET_CODE (SET_SRC (set)) == REG
832 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
833 && rtx_equal_p (SET_DEST (set),
834 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
835 reg_equiv_init[REGNO (SET_SRC (set))]
836 = gen_rtx_INSN_LIST (VOIDmode, insn,
837 reg_equiv_init[REGNO (SET_SRC (set))]);
840 scan_paradoxical_subregs (PATTERN (insn));
845 num_labels = max_label_num () - get_first_label_num ();
847 /* Allocate the tables used to store offset information at labels. */
848 /* We used to use alloca here, but the size of what it would try to
849 allocate would occasionally cause it to exceed the stack limit and
850 cause a core dump. */
851 real_known_ptr = xmalloc (num_labels);
853 = (int (*)[NUM_ELIMINABLE_REGS])
854 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
856 offsets_known_at = real_known_ptr - get_first_label_num ();
858 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
860 /* Alter each pseudo-reg rtx to contain its hard reg number.
861 Assign stack slots to the pseudos that lack hard regs or equivalents.
862 Do not touch virtual registers. */
864 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
867 /* If we have some registers we think can be eliminated, scan all insns to
868 see if there is an insn that sets one of these registers to something
869 other than itself plus a constant. If so, the register cannot be
870 eliminated. Doing this scan here eliminates an extra pass through the
871 main reload loop in the most common case where register elimination
873 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
874 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
875 || GET_CODE (insn) == CALL_INSN)
876 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
878 maybe_fix_stack_asms ();
880 insns_need_reload = 0;
881 something_needs_elimination = 0;
883 /* Initialize to -1, which means take the first spill register. */
886 /* Spill any hard regs that we know we can't eliminate. */
887 CLEAR_HARD_REG_SET (used_spill_regs);
888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
889 if (! ep->can_eliminate)
890 spill_hard_reg (ep->from, 1);
892 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
893 if (frame_pointer_needed)
894 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
896 finish_spills (global);
898 /* From now on, we may need to generate moves differently. We may also
899 allow modifications of insns which cause them to not be recognized.
900 Any such modifications will be cleaned up during reload itself. */
901 reload_in_progress = 1;
903 /* This loop scans the entire function each go-round
904 and repeats until one repetition spills no additional hard regs. */
907 int something_changed;
910 HOST_WIDE_INT starting_frame_size;
912 /* Round size of stack frame to stack_alignment_needed. This must be done
913 here because the stack size may be a part of the offset computation
914 for register elimination, and there might have been new stack slots
915 created in the last iteration of this loop. */
916 if (cfun->stack_alignment_needed)
917 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
919 starting_frame_size = get_frame_size ();
921 set_initial_elim_offsets ();
922 set_initial_label_offsets ();
924 /* For each pseudo register that has an equivalent location defined,
925 try to eliminate any eliminable registers (such as the frame pointer)
926 assuming initial offsets for the replacement register, which
929 If the resulting location is directly addressable, substitute
930 the MEM we just got directly for the old REG.
932 If it is not addressable but is a constant or the sum of a hard reg
933 and constant, it is probably not addressable because the constant is
934 out of range, in that case record the address; we will generate
935 hairy code to compute the address in a register each time it is
936 needed. Similarly if it is a hard register, but one that is not
937 valid as an address register.
939 If the location is not addressable, but does not have one of the
940 above forms, assign a stack slot. We have to do this to avoid the
941 potential of producing lots of reloads if, e.g., a location involves
942 a pseudo that didn't get a hard register and has an equivalent memory
943 location that also involves a pseudo that didn't get a hard register.
945 Perhaps at some point we will improve reload_when_needed handling
946 so this problem goes away. But that's very hairy. */
948 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
949 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
951 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
953 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
955 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
956 else if (CONSTANT_P (XEXP (x, 0))
957 || (GET_CODE (XEXP (x, 0)) == REG
958 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
959 || (GET_CODE (XEXP (x, 0)) == PLUS
960 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
961 && (REGNO (XEXP (XEXP (x, 0), 0))
962 < FIRST_PSEUDO_REGISTER)
963 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
964 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
967 /* Make a new stack slot. Then indicate that something
968 changed so we go back and recompute offsets for
969 eliminable registers because the allocation of memory
970 below might change some offset. reg_equiv_{mem,address}
971 will be set up for this pseudo on the next pass around
973 reg_equiv_memory_loc[i] = 0;
974 reg_equiv_init[i] = 0;
979 if (caller_save_needed)
982 /* If we allocated another stack slot, redo elimination bookkeeping. */
983 if (starting_frame_size != get_frame_size ())
986 if (caller_save_needed)
988 save_call_clobbered_regs ();
989 /* That might have allocated new insn_chain structures. */
990 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
993 calculate_needs_all_insns (global);
995 CLEAR_REG_SET (&spilled_pseudos);
998 something_changed = 0;
1000 /* If we allocated any new memory locations, make another pass
1001 since it might have changed elimination offsets. */
1002 if (starting_frame_size != get_frame_size ())
1003 something_changed = 1;
1006 HARD_REG_SET to_spill;
1007 CLEAR_HARD_REG_SET (to_spill);
1008 update_eliminables (&to_spill);
1009 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1010 if (TEST_HARD_REG_BIT (to_spill, i))
1012 spill_hard_reg (i, 1);
1015 /* Regardless of the state of spills, if we previously had
1016 a register that we thought we could eliminate, but no can
1017 not eliminate, we must run another pass.
1019 Consider pseudos which have an entry in reg_equiv_* which
1020 reference an eliminable register. We must make another pass
1021 to update reg_equiv_* so that we do not substitute in the
1022 old value from when we thought the elimination could be
1024 something_changed = 1;
1028 select_reload_regs ();
1032 if (insns_need_reload != 0 || did_spill)
1033 something_changed |= finish_spills (global);
1035 if (! something_changed)
1038 if (caller_save_needed)
1039 delete_caller_save_insns ();
1041 obstack_free (&reload_obstack, reload_firstobj);
1044 /* If global-alloc was run, notify it of any register eliminations we have
1047 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1048 if (ep->can_eliminate)
1049 mark_elimination (ep->from, ep->to);
1051 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1052 If that insn didn't set the register (i.e., it copied the register to
1053 memory), just delete that insn instead of the equivalencing insn plus
1054 anything now dead. If we call delete_dead_insn on that insn, we may
1055 delete the insn that actually sets the register if the register dies
1056 there and that is incorrect. */
1058 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1060 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1063 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1065 rtx equiv_insn = XEXP (list, 0);
1066 if (GET_CODE (equiv_insn) == NOTE)
1068 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1069 delete_dead_insn (equiv_insn);
1072 PUT_CODE (equiv_insn, NOTE);
1073 NOTE_SOURCE_FILE (equiv_insn) = 0;
1074 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload != 0 || something_needs_elimination
1085 || something_needs_operands_changed)
1087 HOST_WIDE_INT old_frame_size = get_frame_size ();
1089 reload_as_needed (global);
1091 if (old_frame_size != get_frame_size ())
1095 verify_initial_elim_offsets ();
1098 /* If we were able to eliminate the frame pointer, show that it is no
1099 longer live at the start of any basic block. If it ls live by
1100 virtue of being in a pseudo, that pseudo will be marked live
1101 and hence the frame pointer will be known to be live via that
1104 if (! frame_pointer_needed)
1105 for (i = 0; i < n_basic_blocks; i++)
1106 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1107 HARD_FRAME_POINTER_REGNUM);
1109 /* Come here (with failure set nonzero) if we can't get enough spill regs
1110 and we decide not to abort about it. */
1113 CLEAR_REG_SET (&spilled_pseudos);
1114 reload_in_progress = 0;
1116 /* Now eliminate all pseudo regs by modifying them into
1117 their equivalent memory references.
1118 The REG-rtx's for the pseudos are modified in place,
1119 so all insns that used to refer to them now refer to memory.
1121 For a reg that has a reg_equiv_address, all those insns
1122 were changed by reloading so that no insns refer to it any longer;
1123 but the DECL_RTL of a variable decl may refer to it,
1124 and if so this causes the debugging info to mention the variable. */
1126 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1131 int is_readonly = 0;
1133 if (reg_equiv_memory_loc[i])
1135 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1136 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1137 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1140 if (reg_equiv_mem[i])
1141 addr = XEXP (reg_equiv_mem[i], 0);
1143 if (reg_equiv_address[i])
1144 addr = reg_equiv_address[i];
1148 if (reg_renumber[i] < 0)
1150 rtx reg = regno_reg_rtx[i];
1151 PUT_CODE (reg, MEM);
1152 XEXP (reg, 0) = addr;
1153 REG_USERVAR_P (reg) = 0;
1154 RTX_UNCHANGING_P (reg) = is_readonly;
1155 MEM_IN_STRUCT_P (reg) = in_struct;
1156 MEM_SCALAR_P (reg) = is_scalar;
1157 /* We have no alias information about this newly created
1159 MEM_ALIAS_SET (reg) = 0;
1161 else if (reg_equiv_mem[i])
1162 XEXP (reg_equiv_mem[i], 0) = addr;
1166 /* We must set reload_completed now since the cleanup_subreg_operands call
1167 below will re-recognize each insn and reload may have generated insns
1168 which are only valid during and after reload. */
1169 reload_completed = 1;
1171 /* Make a pass over all the insns and delete all USEs which we inserted
1172 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1173 notes. Delete all CLOBBER insns that don't refer to the return value
1174 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1175 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1176 and regenerate REG_INC notes that may have been moved around. */
1178 for (insn = first; insn; insn = NEXT_INSN (insn))
1183 if (GET_CODE (insn) == CALL_INSN)
1184 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1186 CALL_INSN_FUNCTION_USAGE (insn));
1188 if ((GET_CODE (PATTERN (insn)) == USE
1189 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1190 || (GET_CODE (PATTERN (insn)) == CLOBBER
1191 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1192 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1194 PUT_CODE (insn, NOTE);
1195 NOTE_SOURCE_FILE (insn) = 0;
1196 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1200 pnote = ®_NOTES (insn);
1203 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1204 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1205 || REG_NOTE_KIND (*pnote) == REG_INC
1206 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1207 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1208 *pnote = XEXP (*pnote, 1);
1210 pnote = &XEXP (*pnote, 1);
1214 add_auto_inc_notes (insn, PATTERN (insn));
1217 /* And simplify (subreg (reg)) if it appears as an operand. */
1218 cleanup_subreg_operands (insn);
1221 /* If we are doing stack checking, give a warning if this function's
1222 frame size is larger than we expect. */
1223 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1225 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1226 static int verbose_warned = 0;
1228 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1229 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1230 size += UNITS_PER_WORD;
1232 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1234 warning ("frame size too large for reliable stack checking");
1235 if (! verbose_warned)
1237 warning ("try reducing the number of local variables");
1243 /* Indicate that we no longer have known memory locations or constants. */
1244 if (reg_equiv_constant)
1245 free (reg_equiv_constant);
1246 reg_equiv_constant = 0;
1247 if (reg_equiv_memory_loc)
1248 free (reg_equiv_memory_loc);
1249 reg_equiv_memory_loc = 0;
1252 free (real_known_ptr);
1256 free (reg_equiv_mem);
1257 free (reg_equiv_init);
1258 free (reg_equiv_address);
1259 free (reg_max_ref_width);
1260 free (reg_old_renumber);
1261 free (pseudo_previous_regs);
1262 free (pseudo_forbidden_regs);
1264 CLEAR_HARD_REG_SET (used_spill_regs);
1265 for (i = 0; i < n_spills; i++)
1266 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1268 /* Free all the insn_chain structures at once. */
1269 obstack_free (&reload_obstack, reload_startobj);
1270 unused_insn_chains = 0;
1275 /* Yet another special case. Unfortunately, reg-stack forces people to
1276 write incorrect clobbers in asm statements. These clobbers must not
1277 cause the register to appear in bad_spill_regs, otherwise we'll call
1278 fatal_insn later. We clear the corresponding regnos in the live
1279 register sets to avoid this.
1280 The whole thing is rather sick, I'm afraid. */
1283 maybe_fix_stack_asms ()
1286 const char *constraints[MAX_RECOG_OPERANDS];
1287 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1288 struct insn_chain *chain;
1290 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1293 HARD_REG_SET clobbered, allowed;
1296 if (! INSN_P (chain->insn)
1297 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1299 pat = PATTERN (chain->insn);
1300 if (GET_CODE (pat) != PARALLEL)
1303 CLEAR_HARD_REG_SET (clobbered);
1304 CLEAR_HARD_REG_SET (allowed);
1306 /* First, make a mask of all stack regs that are clobbered. */
1307 for (i = 0; i < XVECLEN (pat, 0); i++)
1309 rtx t = XVECEXP (pat, 0, i);
1310 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1311 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1314 /* Get the operand values and constraints out of the insn. */
1315 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1316 constraints, operand_mode);
1318 /* For every operand, see what registers are allowed. */
1319 for (i = 0; i < noperands; i++)
1321 const char *p = constraints[i];
1322 /* For every alternative, we compute the class of registers allowed
1323 for reloading in CLS, and merge its contents into the reg set
1325 int cls = (int) NO_REGS;
1331 if (c == '\0' || c == ',' || c == '#')
1333 /* End of one alternative - mark the regs in the current
1334 class, and reset the class. */
1335 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1340 } while (c != '\0' && c != ',');
1348 case '=': case '+': case '*': case '%': case '?': case '!':
1349 case '0': case '1': case '2': case '3': case '4': case 'm':
1350 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1351 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1352 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1357 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1362 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1366 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1371 /* Those of the registers which are clobbered, but allowed by the
1372 constraints, must be usable as reload registers. So clear them
1373 out of the life information. */
1374 AND_HARD_REG_SET (allowed, clobbered);
1375 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1376 if (TEST_HARD_REG_BIT (allowed, i))
1378 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1379 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1386 /* Copy the global variables n_reloads and rld into the corresponding elts
1389 copy_reloads (chain)
1390 struct insn_chain *chain;
1392 chain->n_reloads = n_reloads;
1394 = (struct reload *) obstack_alloc (&reload_obstack,
1395 n_reloads * sizeof (struct reload));
1396 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1397 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1400 /* Walk the chain of insns, and determine for each whether it needs reloads
1401 and/or eliminations. Build the corresponding insns_need_reload list, and
1402 set something_needs_elimination as appropriate. */
1404 calculate_needs_all_insns (global)
1407 struct insn_chain **pprev_reload = &insns_need_reload;
1408 struct insn_chain *chain, *next = 0;
1410 something_needs_elimination = 0;
1412 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1413 for (chain = reload_insn_chain; chain != 0; chain = next)
1415 rtx insn = chain->insn;
1419 /* Clear out the shortcuts. */
1420 chain->n_reloads = 0;
1421 chain->need_elim = 0;
1422 chain->need_reload = 0;
1423 chain->need_operand_change = 0;
1425 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1426 include REG_LABEL), we need to see what effects this has on the
1427 known offsets at labels. */
1429 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1430 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1431 set_label_offsets (insn, insn, 0);
1435 rtx old_body = PATTERN (insn);
1436 int old_code = INSN_CODE (insn);
1437 rtx old_notes = REG_NOTES (insn);
1438 int did_elimination = 0;
1439 int operands_changed = 0;
1440 rtx set = single_set (insn);
1442 /* Skip insns that only set an equivalence. */
1443 if (set && GET_CODE (SET_DEST (set)) == REG
1444 && reg_renumber[REGNO (SET_DEST (set))] < 0
1445 && reg_equiv_constant[REGNO (SET_DEST (set))])
1448 /* If needed, eliminate any eliminable registers. */
1449 if (num_eliminable || num_eliminable_invariants)
1450 did_elimination = eliminate_regs_in_insn (insn, 0);
1452 /* Analyze the instruction. */
1453 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1454 global, spill_reg_order);
1456 /* If a no-op set needs more than one reload, this is likely
1457 to be something that needs input address reloads. We
1458 can't get rid of this cleanly later, and it is of no use
1459 anyway, so discard it now.
1460 We only do this when expensive_optimizations is enabled,
1461 since this complements reload inheritance / output
1462 reload deletion, and it can make debugging harder. */
1463 if (flag_expensive_optimizations && n_reloads > 1)
1465 rtx set = single_set (insn);
1467 && SET_SRC (set) == SET_DEST (set)
1468 && GET_CODE (SET_SRC (set)) == REG
1469 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1471 PUT_CODE (insn, NOTE);
1472 NOTE_SOURCE_FILE (insn) = 0;
1473 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1474 /* Delete it from the reload chain */
1476 chain->prev->next = next;
1478 reload_insn_chain = next;
1480 next->prev = chain->prev;
1481 chain->next = unused_insn_chains;
1482 unused_insn_chains = chain;
1487 update_eliminable_offsets ();
1489 /* Remember for later shortcuts which insns had any reloads or
1490 register eliminations. */
1491 chain->need_elim = did_elimination;
1492 chain->need_reload = n_reloads > 0;
1493 chain->need_operand_change = operands_changed;
1495 /* Discard any register replacements done. */
1496 if (did_elimination)
1498 obstack_free (&reload_obstack, reload_insn_firstobj);
1499 PATTERN (insn) = old_body;
1500 INSN_CODE (insn) = old_code;
1501 REG_NOTES (insn) = old_notes;
1502 something_needs_elimination = 1;
1505 something_needs_operands_changed |= operands_changed;
1509 copy_reloads (chain);
1510 *pprev_reload = chain;
1511 pprev_reload = &chain->next_need_reload;
1518 /* Comparison function for qsort to decide which of two reloads
1519 should be handled first. *P1 and *P2 are the reload numbers. */
1522 reload_reg_class_lower (r1p, r2p)
1526 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1529 /* Consider required reloads before optional ones. */
1530 t = rld[r1].optional - rld[r2].optional;
1534 /* Count all solitary classes before non-solitary ones. */
1535 t = ((reg_class_size[(int) rld[r2].class] == 1)
1536 - (reg_class_size[(int) rld[r1].class] == 1));
1540 /* Aside from solitaires, consider all multi-reg groups first. */
1541 t = rld[r2].nregs - rld[r1].nregs;
1545 /* Consider reloads in order of increasing reg-class number. */
1546 t = (int) rld[r1].class - (int) rld[r2].class;
1550 /* If reloads are equally urgent, sort by reload number,
1551 so that the results of qsort leave nothing to chance. */
1555 /* The cost of spilling each hard reg. */
1556 static int spill_cost[FIRST_PSEUDO_REGISTER];
1558 /* When spilling multiple hard registers, we use SPILL_COST for the first
1559 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1560 only the first hard reg for a multi-reg pseudo. */
1561 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1563 /* Update the spill cost arrays, considering that pseudo REG is live. */
1569 int n_refs = REG_N_REFS (reg);
1570 int r = reg_renumber[reg];
1573 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1574 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1577 SET_REGNO_REG_SET (&pseudos_counted, reg);
1582 spill_add_cost[r] += n_refs;
1584 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1586 spill_cost[r + nregs] += n_refs;
1589 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1590 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1593 order_regs_for_reload (chain)
1594 struct insn_chain *chain;
1597 HARD_REG_SET used_by_pseudos;
1598 HARD_REG_SET used_by_pseudos2;
1600 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1602 memset (spill_cost, 0, sizeof spill_cost);
1603 memset (spill_add_cost, 0, sizeof spill_add_cost);
1605 /* Count number of uses of each hard reg by pseudo regs allocated to it
1606 and then order them by decreasing use. First exclude hard registers
1607 that are live in or across this insn. */
1609 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1611 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1614 /* Now find out which pseudos are allocated to it, and update
1616 CLEAR_REG_SET (&pseudos_counted);
1618 EXECUTE_IF_SET_IN_REG_SET
1619 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1623 EXECUTE_IF_SET_IN_REG_SET
1624 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1628 CLEAR_REG_SET (&pseudos_counted);
1631 /* Vector of reload-numbers showing the order in which the reloads should
1633 static short reload_order[MAX_RELOADS];
1635 /* This is used to keep track of the spill regs used in one insn. */
1636 static HARD_REG_SET used_spill_regs_local;
1638 /* We decided to spill hard register SPILLED, which has a size of
1639 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1640 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1641 update SPILL_COST/SPILL_ADD_COST. */
1644 count_spilled_pseudo (spilled, spilled_nregs, reg)
1645 int spilled, spilled_nregs, reg;
1647 int r = reg_renumber[reg];
1648 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1650 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1651 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1654 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1656 spill_add_cost[r] -= REG_N_REFS (reg);
1658 spill_cost[r + nregs] -= REG_N_REFS (reg);
1661 /* Find reload register to use for reload number ORDER. */
1664 find_reg (chain, order)
1665 struct insn_chain *chain;
1668 int rnum = reload_order[order];
1669 struct reload *rl = rld + rnum;
1670 int best_cost = INT_MAX;
1674 HARD_REG_SET not_usable;
1675 HARD_REG_SET used_by_other_reload;
1677 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1678 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1679 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1681 CLEAR_HARD_REG_SET (used_by_other_reload);
1682 for (k = 0; k < order; k++)
1684 int other = reload_order[k];
1686 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1687 for (j = 0; j < rld[other].nregs; j++)
1688 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1691 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1693 unsigned int regno = i;
1695 if (! TEST_HARD_REG_BIT (not_usable, regno)
1696 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1697 && HARD_REGNO_MODE_OK (regno, rl->mode))
1699 int this_cost = spill_cost[regno];
1701 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1703 for (j = 1; j < this_nregs; j++)
1705 this_cost += spill_add_cost[regno + j];
1706 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1707 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1712 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1714 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1716 if (this_cost < best_cost
1717 /* Among registers with equal cost, prefer caller-saved ones, or
1718 use REG_ALLOC_ORDER if it is defined. */
1719 || (this_cost == best_cost
1720 #ifdef REG_ALLOC_ORDER
1721 && (inv_reg_alloc_order[regno]
1722 < inv_reg_alloc_order[best_reg])
1724 && call_used_regs[regno]
1725 && ! call_used_regs[best_reg]
1730 best_cost = this_cost;
1738 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1740 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1741 rl->regno = best_reg;
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1746 count_spilled_pseudo (best_reg, rl->nregs, j);
1749 EXECUTE_IF_SET_IN_REG_SET
1750 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1752 count_spilled_pseudo (best_reg, rl->nregs, j);
1755 for (i = 0; i < rl->nregs; i++)
1757 if (spill_cost[best_reg + i] != 0
1758 || spill_add_cost[best_reg + i] != 0)
1760 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1765 /* Find more reload regs to satisfy the remaining need of an insn, which
1767 Do it by ascending class number, since otherwise a reg
1768 might be spilled for a big class and might fail to count
1769 for a smaller class even though it belongs to that class. */
1772 find_reload_regs (chain)
1773 struct insn_chain *chain;
1777 /* In order to be certain of getting the registers we need,
1778 we must sort the reloads into order of increasing register class.
1779 Then our grabbing of reload registers will parallel the process
1780 that provided the reload registers. */
1781 for (i = 0; i < chain->n_reloads; i++)
1783 /* Show whether this reload already has a hard reg. */
1784 if (chain->rld[i].reg_rtx)
1786 int regno = REGNO (chain->rld[i].reg_rtx);
1787 chain->rld[i].regno = regno;
1789 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1792 chain->rld[i].regno = -1;
1793 reload_order[i] = i;
1796 n_reloads = chain->n_reloads;
1797 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1799 CLEAR_HARD_REG_SET (used_spill_regs_local);
1802 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1804 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1806 /* Compute the order of preference for hard registers to spill. */
1808 order_regs_for_reload (chain);
1810 for (i = 0; i < n_reloads; i++)
1812 int r = reload_order[i];
1814 /* Ignore reloads that got marked inoperative. */
1815 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1816 && ! rld[r].optional
1817 && rld[r].regno == -1)
1818 if (! find_reg (chain, i))
1820 spill_failure (chain->insn, rld[r].class);
1826 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1827 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1829 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1833 select_reload_regs ()
1835 struct insn_chain *chain;
1837 /* Try to satisfy the needs for each insn. */
1838 for (chain = insns_need_reload; chain != 0;
1839 chain = chain->next_need_reload)
1840 find_reload_regs (chain);
1843 /* Delete all insns that were inserted by emit_caller_save_insns during
1846 delete_caller_save_insns ()
1848 struct insn_chain *c = reload_insn_chain;
1852 while (c != 0 && c->is_caller_save_insn)
1854 struct insn_chain *next = c->next;
1857 if (insn == BLOCK_HEAD (c->block))
1858 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1859 if (insn == BLOCK_END (c->block))
1860 BLOCK_END (c->block) = PREV_INSN (insn);
1861 if (c == reload_insn_chain)
1862 reload_insn_chain = next;
1864 if (NEXT_INSN (insn) != 0)
1865 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1866 if (PREV_INSN (insn) != 0)
1867 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1870 next->prev = c->prev;
1872 c->prev->next = next;
1873 c->next = unused_insn_chains;
1874 unused_insn_chains = c;
1882 /* Handle the failure to find a register to spill.
1883 INSN should be one of the insns which needed this particular spill reg. */
1886 spill_failure (insn, class)
1888 enum reg_class class;
1890 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1891 if (asm_noperands (PATTERN (insn)) >= 0)
1892 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1893 reg_class_names[class]);
1896 error ("Unable to find a register to spill in class `%s'.",
1897 reg_class_names[class]);
1898 fatal_insn ("This is the insn:", insn);
1902 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1903 data that is dead in INSN. */
1906 delete_dead_insn (insn)
1909 rtx prev = prev_real_insn (insn);
1912 /* If the previous insn sets a register that dies in our insn, delete it
1914 if (prev && GET_CODE (PATTERN (prev)) == SET
1915 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1916 && reg_mentioned_p (prev_dest, PATTERN (insn))
1917 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1918 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1919 delete_dead_insn (prev);
1921 PUT_CODE (insn, NOTE);
1922 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1923 NOTE_SOURCE_FILE (insn) = 0;
1926 /* Modify the home of pseudo-reg I.
1927 The new home is present in reg_renumber[I].
1929 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1930 or it may be -1, meaning there is none or it is not relevant.
1931 This is used so that all pseudos spilled from a given hard reg
1932 can share one stack slot. */
1935 alter_reg (i, from_reg)
1939 /* When outputting an inline function, this can happen
1940 for a reg that isn't actually used. */
1941 if (regno_reg_rtx[i] == 0)
1944 /* If the reg got changed to a MEM at rtl-generation time,
1946 if (GET_CODE (regno_reg_rtx[i]) != REG)
1949 /* Modify the reg-rtx to contain the new hard reg
1950 number or else to contain its pseudo reg number. */
1951 REGNO (regno_reg_rtx[i])
1952 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1954 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1955 allocate a stack slot for it. */
1957 if (reg_renumber[i] < 0
1958 && REG_N_REFS (i) > 0
1959 && reg_equiv_constant[i] == 0
1960 && reg_equiv_memory_loc[i] == 0)
1963 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1964 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1967 /* Each pseudo reg has an inherent size which comes from its own mode,
1968 and a total size which provides room for paradoxical subregs
1969 which refer to the pseudo reg in wider modes.
1971 We can use a slot already allocated if it provides both
1972 enough inherent space and enough total space.
1973 Otherwise, we allocate a new slot, making sure that it has no less
1974 inherent space, and no less total space, then the previous slot. */
1977 /* No known place to spill from => no slot to reuse. */
1978 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1979 inherent_size == total_size ? 0 : -1);
1980 if (BYTES_BIG_ENDIAN)
1981 /* Cancel the big-endian correction done in assign_stack_local.
1982 Get the address of the beginning of the slot.
1983 This is so we can do a big-endian correction unconditionally
1985 adjust = inherent_size - total_size;
1987 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1989 /* Nothing can alias this slot except this pseudo. */
1990 MEM_ALIAS_SET (x) = new_alias_set ();
1993 /* Reuse a stack slot if possible. */
1994 else if (spill_stack_slot[from_reg] != 0
1995 && spill_stack_slot_width[from_reg] >= total_size
1996 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1998 x = spill_stack_slot[from_reg];
2000 /* Allocate a bigger slot. */
2003 /* Compute maximum size needed, both for inherent size
2004 and for total size. */
2005 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2008 if (spill_stack_slot[from_reg])
2010 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2012 mode = GET_MODE (spill_stack_slot[from_reg]);
2013 if (spill_stack_slot_width[from_reg] > total_size)
2014 total_size = spill_stack_slot_width[from_reg];
2017 /* Make a slot with that size. */
2018 x = assign_stack_local (mode, total_size,
2019 inherent_size == total_size ? 0 : -1);
2022 /* All pseudos mapped to this slot can alias each other. */
2023 if (spill_stack_slot[from_reg])
2024 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2026 MEM_ALIAS_SET (x) = new_alias_set ();
2028 if (BYTES_BIG_ENDIAN)
2030 /* Cancel the big-endian correction done in assign_stack_local.
2031 Get the address of the beginning of the slot.
2032 This is so we can do a big-endian correction unconditionally
2034 adjust = GET_MODE_SIZE (mode) - total_size;
2036 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2039 plus_constant (XEXP (x, 0), adjust));
2042 spill_stack_slot[from_reg] = stack_slot;
2043 spill_stack_slot_width[from_reg] = total_size;
2046 /* On a big endian machine, the "address" of the slot
2047 is the address of the low part that fits its inherent mode. */
2048 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2049 adjust += (total_size - inherent_size);
2051 /* If we have any adjustment to make, or if the stack slot is the
2052 wrong mode, make a new stack slot. */
2053 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2055 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2056 plus_constant (XEXP (x, 0), adjust));
2058 MEM_COPY_ATTRIBUTES (new, x);
2062 /* Save the stack slot for later. */
2063 reg_equiv_memory_loc[i] = x;
2067 /* Mark the slots in regs_ever_live for the hard regs
2068 used by pseudo-reg number REGNO. */
2071 mark_home_live (regno)
2074 register int i, lim;
2076 i = reg_renumber[regno];
2079 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2081 regs_ever_live[i++] = 1;
2084 /* This function handles the tracking of elimination offsets around branches.
2086 X is a piece of RTL being scanned.
2088 INSN is the insn that it came from, if any.
2090 INITIAL_P is non-zero if we are to set the offset to be the initial
2091 offset and zero if we are setting the offset of the label to be the
2095 set_label_offsets (x, insn, initial_p)
2100 enum rtx_code code = GET_CODE (x);
2103 struct elim_table *p;
2108 if (LABEL_REF_NONLOCAL_P (x))
2113 /* ... fall through ... */
2116 /* If we know nothing about this label, set the desired offsets. Note
2117 that this sets the offset at a label to be the offset before a label
2118 if we don't know anything about the label. This is not correct for
2119 the label after a BARRIER, but is the best guess we can make. If
2120 we guessed wrong, we will suppress an elimination that might have
2121 been possible had we been able to guess correctly. */
2123 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2125 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2126 offsets_at[CODE_LABEL_NUMBER (x)][i]
2127 = (initial_p ? reg_eliminate[i].initial_offset
2128 : reg_eliminate[i].offset);
2129 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2132 /* Otherwise, if this is the definition of a label and it is
2133 preceded by a BARRIER, set our offsets to the known offset of
2137 && (tem = prev_nonnote_insn (insn)) != 0
2138 && GET_CODE (tem) == BARRIER)
2139 set_offsets_for_label (insn);
2141 /* If neither of the above cases is true, compare each offset
2142 with those previously recorded and suppress any eliminations
2143 where the offsets disagree. */
2145 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2146 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2147 != (initial_p ? reg_eliminate[i].initial_offset
2148 : reg_eliminate[i].offset))
2149 reg_eliminate[i].can_eliminate = 0;
2154 set_label_offsets (PATTERN (insn), insn, initial_p);
2156 /* ... fall through ... */
2160 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2161 and hence must have all eliminations at their initial offsets. */
2162 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2163 if (REG_NOTE_KIND (tem) == REG_LABEL)
2164 set_label_offsets (XEXP (tem, 0), insn, 1);
2170 /* Each of the labels in the parallel or address vector must be
2171 at their initial offsets. We want the first field for PARALLEL
2172 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2174 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2175 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2180 /* We only care about setting PC. If the source is not RETURN,
2181 IF_THEN_ELSE, or a label, disable any eliminations not at
2182 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2183 isn't one of those possibilities. For branches to a label,
2184 call ourselves recursively.
2186 Note that this can disable elimination unnecessarily when we have
2187 a non-local goto since it will look like a non-constant jump to
2188 someplace in the current function. This isn't a significant
2189 problem since such jumps will normally be when all elimination
2190 pairs are back to their initial offsets. */
2192 if (SET_DEST (x) != pc_rtx)
2195 switch (GET_CODE (SET_SRC (x)))
2202 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2206 tem = XEXP (SET_SRC (x), 1);
2207 if (GET_CODE (tem) == LABEL_REF)
2208 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2209 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2212 tem = XEXP (SET_SRC (x), 2);
2213 if (GET_CODE (tem) == LABEL_REF)
2214 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2215 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2223 /* If we reach here, all eliminations must be at their initial
2224 offset because we are doing a jump to a variable address. */
2225 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2226 if (p->offset != p->initial_offset)
2227 p->can_eliminate = 0;
2235 /* Scan X and replace any eliminable registers (such as fp) with a
2236 replacement (such as sp), plus an offset.
2238 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2239 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2240 MEM, we are allowed to replace a sum of a register and the constant zero
2241 with the register, which we cannot do outside a MEM. In addition, we need
2242 to record the fact that a register is referenced outside a MEM.
2244 If INSN is an insn, it is the insn containing X. If we replace a REG
2245 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2246 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2247 the REG is being modified.
2249 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2250 That's used when we eliminate in expressions stored in notes.
2251 This means, do not set ref_outside_mem even if the reference
2254 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2255 replacements done assuming all offsets are at their initial values. If
2256 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2257 encounter, return the actual location so that find_reloads will do
2258 the proper thing. */
2261 eliminate_regs (x, mem_mode, insn)
2263 enum machine_mode mem_mode;
2266 enum rtx_code code = GET_CODE (x);
2267 struct elim_table *ep;
2274 if (! current_function_decl)
2293 /* This is only for the benefit of the debugging backends, which call
2294 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2295 removed after CSE. */
2296 new = eliminate_regs (XEXP (x, 0), 0, insn);
2297 if (GET_CODE (new) == MEM)
2298 return XEXP (new, 0);
2304 /* First handle the case where we encounter a bare register that
2305 is eliminable. Replace it with a PLUS. */
2306 if (regno < FIRST_PSEUDO_REGISTER)
2308 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2310 if (ep->from_rtx == x && ep->can_eliminate)
2311 return plus_constant (ep->to_rtx, ep->previous_offset);
2314 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2315 && reg_equiv_constant[regno]
2316 && ! CONSTANT_P (reg_equiv_constant[regno]))
2317 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2321 /* You might think handling MINUS in a manner similar to PLUS is a
2322 good idea. It is not. It has been tried multiple times and every
2323 time the change has had to have been reverted.
2325 Other parts of reload know a PLUS is special (gen_reload for example)
2326 and require special code to handle code a reloaded PLUS operand.
2328 Also consider backends where the flags register is clobbered by a
2329 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2330 lea instruction comes to mind). If we try to reload a MINUS, we
2331 may kill the flags register that was holding a useful value.
2333 So, please before trying to handle MINUS, consider reload as a
2334 whole instead of this little section as well as the backend issues. */
2336 /* If this is the sum of an eliminable register and a constant, rework
2338 if (GET_CODE (XEXP (x, 0)) == REG
2339 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2340 && CONSTANT_P (XEXP (x, 1)))
2342 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2344 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2346 /* The only time we want to replace a PLUS with a REG (this
2347 occurs when the constant operand of the PLUS is the negative
2348 of the offset) is when we are inside a MEM. We won't want
2349 to do so at other times because that would change the
2350 structure of the insn in a way that reload can't handle.
2351 We special-case the commonest situation in
2352 eliminate_regs_in_insn, so just replace a PLUS with a
2353 PLUS here, unless inside a MEM. */
2354 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2355 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2358 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2359 plus_constant (XEXP (x, 1),
2360 ep->previous_offset));
2363 /* If the register is not eliminable, we are done since the other
2364 operand is a constant. */
2368 /* If this is part of an address, we want to bring any constant to the
2369 outermost PLUS. We will do this by doing register replacement in
2370 our operands and seeing if a constant shows up in one of them.
2372 Note that there is no risk of modifying the structure of the insn,
2373 since we only get called for its operands, thus we are either
2374 modifying the address inside a MEM, or something like an address
2375 operand of a load-address insn. */
2378 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2379 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2381 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2383 /* If one side is a PLUS and the other side is a pseudo that
2384 didn't get a hard register but has a reg_equiv_constant,
2385 we must replace the constant here since it may no longer
2386 be in the position of any operand. */
2387 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2388 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2389 && reg_renumber[REGNO (new1)] < 0
2390 && reg_equiv_constant != 0
2391 && reg_equiv_constant[REGNO (new1)] != 0)
2392 new1 = reg_equiv_constant[REGNO (new1)];
2393 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2394 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2395 && reg_renumber[REGNO (new0)] < 0
2396 && reg_equiv_constant[REGNO (new0)] != 0)
2397 new0 = reg_equiv_constant[REGNO (new0)];
2399 new = form_sum (new0, new1);
2401 /* As above, if we are not inside a MEM we do not want to
2402 turn a PLUS into something else. We might try to do so here
2403 for an addition of 0 if we aren't optimizing. */
2404 if (! mem_mode && GET_CODE (new) != PLUS)
2405 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2413 /* If this is the product of an eliminable register and a
2414 constant, apply the distribute law and move the constant out
2415 so that we have (plus (mult ..) ..). This is needed in order
2416 to keep load-address insns valid. This case is pathological.
2417 We ignore the possibility of overflow here. */
2418 if (GET_CODE (XEXP (x, 0)) == REG
2419 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2420 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2421 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2423 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2426 /* Refs inside notes don't count for this purpose. */
2427 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2428 || GET_CODE (insn) == INSN_LIST)))
2429 ep->ref_outside_mem = 1;
2432 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2433 ep->previous_offset * INTVAL (XEXP (x, 1)));
2436 /* ... fall through ... */
2440 /* See comments before PLUS about handling MINUS. */
2442 case DIV: case UDIV:
2443 case MOD: case UMOD:
2444 case AND: case IOR: case XOR:
2445 case ROTATERT: case ROTATE:
2446 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2448 case GE: case GT: case GEU: case GTU:
2449 case LE: case LT: case LEU: case LTU:
2451 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2453 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2455 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2456 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2461 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2464 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2465 if (new != XEXP (x, 0))
2467 /* If this is a REG_DEAD note, it is not valid anymore.
2468 Using the eliminated version could result in creating a
2469 REG_DEAD note for the stack or frame pointer. */
2470 if (GET_MODE (x) == REG_DEAD)
2472 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2475 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2479 /* ... fall through ... */
2482 /* Now do eliminations in the rest of the chain. If this was
2483 an EXPR_LIST, this might result in allocating more memory than is
2484 strictly needed, but it simplifies the code. */
2487 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2488 if (new != XEXP (x, 1))
2489 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2497 case STRICT_LOW_PART:
2499 case SIGN_EXTEND: case ZERO_EXTEND:
2500 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2501 case FLOAT: case FIX:
2502 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2506 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2507 if (new != XEXP (x, 0))
2508 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2512 /* Similar to above processing, but preserve SUBREG_BYTE.
2513 Convert (subreg (mem)) to (mem) if not paradoxical.
2514 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2515 pseudo didn't get a hard reg, we must replace this with the
2516 eliminated version of the memory location because push_reloads
2517 may do the replacement in certain circumstances. */
2518 if (GET_CODE (SUBREG_REG (x)) == REG
2519 && (GET_MODE_SIZE (GET_MODE (x))
2520 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2521 && reg_equiv_memory_loc != 0
2522 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2524 new = SUBREG_REG (x);
2527 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2529 if (new != SUBREG_REG (x))
2531 int x_size = GET_MODE_SIZE (GET_MODE (x));
2532 int new_size = GET_MODE_SIZE (GET_MODE (new));
2534 if (GET_CODE (new) == MEM
2535 && ((x_size < new_size
2536 #ifdef WORD_REGISTER_OPERATIONS
2537 /* On these machines, combine can create rtl of the form
2538 (set (subreg:m1 (reg:m2 R) 0) ...)
2539 where m1 < m2, and expects something interesting to
2540 happen to the entire word. Moreover, it will use the
2541 (reg:m2 R) later, expecting all bits to be preserved.
2542 So if the number of words is the same, preserve the
2543 subreg so that push_reloads can see it. */
2544 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2547 || (x_size == new_size))
2550 int offset = SUBREG_BYTE (x);
2551 enum machine_mode mode = GET_MODE (x);
2553 PUT_MODE (new, mode);
2554 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2558 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2564 /* This is only for the benefit of the debugging backends, which call
2565 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2566 removed after CSE. */
2567 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2568 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2570 /* Our only special processing is to pass the mode of the MEM to our
2571 recursive call and copy the flags. While we are here, handle this
2572 case more efficiently. */
2573 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2574 if (new != XEXP (x, 0))
2576 new = gen_rtx_MEM (GET_MODE (x), new);
2577 MEM_COPY_ATTRIBUTES (new, x);
2584 /* Handle insn_list USE that a call to a pure function may generate. */
2585 new = eliminate_regs (XEXP (x, 0), 0, insn);
2586 if (new != XEXP (x, 0))
2587 return gen_rtx_USE (GET_MODE (x), new);
2599 /* Process each of our operands recursively. If any have changed, make a
2601 fmt = GET_RTX_FORMAT (code);
2602 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2606 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2607 if (new != XEXP (x, i) && ! copied)
2609 rtx new_x = rtx_alloc (code);
2611 (sizeof (*new_x) - sizeof (new_x->fld)
2612 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2618 else if (*fmt == 'E')
2621 for (j = 0; j < XVECLEN (x, i); j++)
2623 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2624 if (new != XVECEXP (x, i, j) && ! copied_vec)
2626 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2630 rtx new_x = rtx_alloc (code);
2632 (sizeof (*new_x) - sizeof (new_x->fld)
2633 + (sizeof (new_x->fld[0])
2634 * GET_RTX_LENGTH (code))));
2638 XVEC (x, i) = new_v;
2641 XVECEXP (x, i, j) = new;
2649 /* Scan rtx X for modifications of elimination target registers. Update
2650 the table of eliminables to reflect the changed state. MEM_MODE is
2651 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2654 elimination_effects (x, mem_mode)
2656 enum machine_mode mem_mode;
2659 enum rtx_code code = GET_CODE (x);
2660 struct elim_table *ep;
2686 /* First handle the case where we encounter a bare register that
2687 is eliminable. Replace it with a PLUS. */
2688 if (regno < FIRST_PSEUDO_REGISTER)
2690 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2692 if (ep->from_rtx == x && ep->can_eliminate)
2695 ep->ref_outside_mem = 1;
2700 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2701 && reg_equiv_constant[regno]
2702 && ! CONSTANT_P (reg_equiv_constant[regno]))
2703 elimination_effects (reg_equiv_constant[regno], mem_mode);
2712 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2713 if (ep->to_rtx == XEXP (x, 0))
2715 int size = GET_MODE_SIZE (mem_mode);
2717 /* If more bytes than MEM_MODE are pushed, account for them. */
2718 #ifdef PUSH_ROUNDING
2719 if (ep->to_rtx == stack_pointer_rtx)
2720 size = PUSH_ROUNDING (size);
2722 if (code == PRE_DEC || code == POST_DEC)
2724 else if (code == PRE_INC || code == POST_INC)
2726 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2727 && GET_CODE (XEXP (x, 1)) == PLUS
2728 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2729 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2730 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2733 /* These two aren't unary operators. */
2734 if (code == POST_MODIFY || code == PRE_MODIFY)
2737 /* Fall through to generic unary operation case. */
2738 case STRICT_LOW_PART:
2740 case SIGN_EXTEND: case ZERO_EXTEND:
2741 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2742 case FLOAT: case FIX:
2743 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2747 elimination_effects (XEXP (x, 0), mem_mode);
2751 if (GET_CODE (SUBREG_REG (x)) == REG
2752 && (GET_MODE_SIZE (GET_MODE (x))
2753 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2754 && reg_equiv_memory_loc != 0
2755 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2758 elimination_effects (SUBREG_REG (x), mem_mode);
2762 /* If using a register that is the source of an eliminate we still
2763 think can be performed, note it cannot be performed since we don't
2764 know how this register is used. */
2765 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2766 if (ep->from_rtx == XEXP (x, 0))
2767 ep->can_eliminate = 0;
2769 elimination_effects (XEXP (x, 0), mem_mode);
2773 /* If clobbering a register that is the replacement register for an
2774 elimination we still think can be performed, note that it cannot
2775 be performed. Otherwise, we need not be concerned about it. */
2776 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2777 if (ep->to_rtx == XEXP (x, 0))
2778 ep->can_eliminate = 0;
2780 elimination_effects (XEXP (x, 0), mem_mode);
2784 /* Check for setting a register that we know about. */
2785 if (GET_CODE (SET_DEST (x)) == REG)
2787 /* See if this is setting the replacement register for an
2790 If DEST is the hard frame pointer, we do nothing because we
2791 assume that all assignments to the frame pointer are for
2792 non-local gotos and are being done at a time when they are valid
2793 and do not disturb anything else. Some machines want to
2794 eliminate a fake argument pointer (or even a fake frame pointer)
2795 with either the real frame or the stack pointer. Assignments to
2796 the hard frame pointer must not prevent this elimination. */
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2800 if (ep->to_rtx == SET_DEST (x)
2801 && SET_DEST (x) != hard_frame_pointer_rtx)
2803 /* If it is being incremented, adjust the offset. Otherwise,
2804 this elimination can't be done. */
2805 rtx src = SET_SRC (x);
2807 if (GET_CODE (src) == PLUS
2808 && XEXP (src, 0) == SET_DEST (x)
2809 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2810 ep->offset -= INTVAL (XEXP (src, 1));
2812 ep->can_eliminate = 0;
2816 elimination_effects (SET_DEST (x), 0);
2817 elimination_effects (SET_SRC (x), 0);
2821 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2824 /* Our only special processing is to pass the mode of the MEM to our
2826 elimination_effects (XEXP (x, 0), GET_MODE (x));
2833 fmt = GET_RTX_FORMAT (code);
2834 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2837 elimination_effects (XEXP (x, i), mem_mode);
2838 else if (*fmt == 'E')
2839 for (j = 0; j < XVECLEN (x, i); j++)
2840 elimination_effects (XVECEXP (x, i, j), mem_mode);
2844 /* Descend through rtx X and verify that no references to eliminable registers
2845 remain. If any do remain, mark the involved register as not
2849 check_eliminable_occurrences (x)
2859 code = GET_CODE (x);
2861 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2863 struct elim_table *ep;
2865 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2866 if (ep->from_rtx == x && ep->can_eliminate)
2867 ep->can_eliminate = 0;
2871 fmt = GET_RTX_FORMAT (code);
2872 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2875 check_eliminable_occurrences (XEXP (x, i));
2876 else if (*fmt == 'E')
2879 for (j = 0; j < XVECLEN (x, i); j++)
2880 check_eliminable_occurrences (XVECEXP (x, i, j));
2885 /* Scan INSN and eliminate all eliminable registers in it.
2887 If REPLACE is nonzero, do the replacement destructively. Also
2888 delete the insn as dead it if it is setting an eliminable register.
2890 If REPLACE is zero, do all our allocations in reload_obstack.
2892 If no eliminations were done and this insn doesn't require any elimination
2893 processing (these are not identical conditions: it might be updating sp,
2894 but not referencing fp; this needs to be seen during reload_as_needed so
2895 that the offset between fp and sp can be taken into consideration), zero
2896 is returned. Otherwise, 1 is returned. */
2899 eliminate_regs_in_insn (insn, replace)
2903 int icode = recog_memoized (insn);
2904 rtx old_body = PATTERN (insn);
2905 int insn_is_asm = asm_noperands (old_body) >= 0;
2906 rtx old_set = single_set (insn);
2910 rtx substed_operand[MAX_RECOG_OPERANDS];
2911 rtx orig_operand[MAX_RECOG_OPERANDS];
2912 struct elim_table *ep;
2914 if (! insn_is_asm && icode < 0)
2916 if (GET_CODE (PATTERN (insn)) == USE
2917 || GET_CODE (PATTERN (insn)) == CLOBBER
2918 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2919 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2920 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2925 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2926 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2928 /* Check for setting an eliminable register. */
2929 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2930 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2932 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2933 /* If this is setting the frame pointer register to the
2934 hardware frame pointer register and this is an elimination
2935 that will be done (tested above), this insn is really
2936 adjusting the frame pointer downward to compensate for
2937 the adjustment done before a nonlocal goto. */
2938 if (ep->from == FRAME_POINTER_REGNUM
2939 && ep->to == HARD_FRAME_POINTER_REGNUM)
2941 rtx src = SET_SRC (old_set);
2942 int offset = 0, ok = 0;
2943 rtx prev_insn, prev_set;
2945 if (src == ep->to_rtx)
2947 else if (GET_CODE (src) == PLUS
2948 && GET_CODE (XEXP (src, 0)) == CONST_INT
2949 && XEXP (src, 1) == ep->to_rtx)
2950 offset = INTVAL (XEXP (src, 0)), ok = 1;
2951 else if (GET_CODE (src) == PLUS
2952 && GET_CODE (XEXP (src, 1)) == CONST_INT
2953 && XEXP (src, 0) == ep->to_rtx)
2954 offset = INTVAL (XEXP (src, 1)), ok = 1;
2955 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2956 && (prev_set = single_set (prev_insn)) != 0
2957 && rtx_equal_p (SET_DEST (prev_set), src))
2959 src = SET_SRC (prev_set);
2960 if (src == ep->to_rtx)
2962 else if (GET_CODE (src) == PLUS
2963 && GET_CODE (XEXP (src, 0)) == CONST_INT
2964 && XEXP (src, 1) == ep->to_rtx)
2965 offset = INTVAL (XEXP (src, 0)), ok = 1;
2966 else if (GET_CODE (src) == PLUS
2967 && GET_CODE (XEXP (src, 1)) == CONST_INT
2968 && XEXP (src, 0) == ep->to_rtx)
2969 offset = INTVAL (XEXP (src, 1)), ok = 1;
2977 = plus_constant (ep->to_rtx, offset - ep->offset);
2979 /* First see if this insn remains valid when we
2980 make the change. If not, keep the INSN_CODE
2981 the same and let reload fit it up. */
2982 validate_change (insn, &SET_SRC (old_set), src, 1);
2983 validate_change (insn, &SET_DEST (old_set),
2985 if (! apply_change_group ())
2987 SET_SRC (old_set) = src;
2988 SET_DEST (old_set) = ep->to_rtx;
2998 /* In this case this insn isn't serving a useful purpose. We
2999 will delete it in reload_as_needed once we know that this
3000 elimination is, in fact, being done.
3002 If REPLACE isn't set, we can't delete this insn, but needn't
3003 process it since it won't be used unless something changes. */
3006 delete_dead_insn (insn);
3014 /* We allow one special case which happens to work on all machines we
3015 currently support: a single set with the source being a PLUS of an
3016 eliminable register and a constant. */
3018 && GET_CODE (SET_DEST (old_set)) == REG
3019 && GET_CODE (SET_SRC (old_set)) == PLUS
3020 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3021 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3022 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3024 rtx reg = XEXP (SET_SRC (old_set), 0);
3025 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3028 if (ep->from_rtx == reg && ep->can_eliminate)
3030 offset += ep->offset;
3035 /* We assume here that if we need a PARALLEL with
3036 CLOBBERs for this assignment, we can do with the
3037 MATCH_SCRATCHes that add_clobbers allocates.
3038 There's not much we can do if that doesn't work. */
3039 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3043 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3046 rtvec vec = rtvec_alloc (num_clobbers + 1);
3048 vec->elem[0] = PATTERN (insn);
3049 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3050 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3052 if (INSN_CODE (insn) < 0)
3057 new_body = old_body;
3060 new_body = copy_insn (old_body);
3061 if (REG_NOTES (insn))
3062 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3064 PATTERN (insn) = new_body;
3065 old_set = single_set (insn);
3067 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3068 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3071 /* This can't have an effect on elimination offsets, so skip right
3077 /* Determine the effects of this insn on elimination offsets. */
3078 elimination_effects (old_body, 0);
3080 /* Eliminate all eliminable registers occurring in operands that
3081 can be handled by reload. */
3082 extract_insn (insn);
3084 for (i = 0; i < recog_data.n_operands; i++)
3086 orig_operand[i] = recog_data.operand[i];
3087 substed_operand[i] = recog_data.operand[i];
3089 /* For an asm statement, every operand is eliminable. */
3090 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3092 /* Check for setting a register that we know about. */
3093 if (recog_data.operand_type[i] != OP_IN
3094 && GET_CODE (orig_operand[i]) == REG)
3096 /* If we are assigning to a register that can be eliminated, it
3097 must be as part of a PARALLEL, since the code above handles
3098 single SETs. We must indicate that we can no longer
3099 eliminate this reg. */
3100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3102 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3103 ep->can_eliminate = 0;
3106 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3107 replace ? insn : NULL_RTX);
3108 if (substed_operand[i] != orig_operand[i])
3109 val = any_changes = 1;
3110 /* Terminate the search in check_eliminable_occurrences at
3112 *recog_data.operand_loc[i] = 0;
3114 /* If an output operand changed from a REG to a MEM and INSN is an
3115 insn, write a CLOBBER insn. */
3116 if (recog_data.operand_type[i] != OP_IN
3117 && GET_CODE (orig_operand[i]) == REG
3118 && GET_CODE (substed_operand[i]) == MEM
3120 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3125 for (i = 0; i < recog_data.n_dups; i++)
3126 *recog_data.dup_loc[i]
3127 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3129 /* If any eliminable remain, they aren't eliminable anymore. */
3130 check_eliminable_occurrences (old_body);
3132 /* Substitute the operands; the new values are in the substed_operand
3134 for (i = 0; i < recog_data.n_operands; i++)
3135 *recog_data.operand_loc[i] = substed_operand[i];
3136 for (i = 0; i < recog_data.n_dups; i++)
3137 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3139 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3140 re-recognize the insn. We do this in case we had a simple addition
3141 but now can do this as a load-address. This saves an insn in this
3143 If re-recognition fails, the old insn code number will still be used,
3144 and some register operands may have changed into PLUS expressions.
3145 These will be handled by find_reloads by loading them into a register
3150 /* If we aren't replacing things permanently and we changed something,
3151 make another copy to ensure that all the RTL is new. Otherwise
3152 things can go wrong if find_reload swaps commutative operands
3153 and one is inside RTL that has been copied while the other is not. */
3154 new_body = old_body;
3157 new_body = copy_insn (old_body);
3158 if (REG_NOTES (insn))
3159 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3161 PATTERN (insn) = new_body;
3163 /* If we had a move insn but now we don't, rerecognize it. This will
3164 cause spurious re-recognition if the old move had a PARALLEL since
3165 the new one still will, but we can't call single_set without
3166 having put NEW_BODY into the insn and the re-recognition won't
3167 hurt in this rare case. */
3168 /* ??? Why this huge if statement - why don't we just rerecognize the
3172 && ((GET_CODE (SET_SRC (old_set)) == REG
3173 && (GET_CODE (new_body) != SET
3174 || GET_CODE (SET_SRC (new_body)) != REG))
3175 /* If this was a load from or store to memory, compare
3176 the MEM in recog_data.operand to the one in the insn.
3177 If they are not equal, then rerecognize the insn. */
3179 && ((GET_CODE (SET_SRC (old_set)) == MEM
3180 && SET_SRC (old_set) != recog_data.operand[1])
3181 || (GET_CODE (SET_DEST (old_set)) == MEM
3182 && SET_DEST (old_set) != recog_data.operand[0])))
3183 /* If this was an add insn before, rerecognize. */
3184 || GET_CODE (SET_SRC (old_set)) == PLUS))
3186 int new_icode = recog (PATTERN (insn), insn, 0);
3188 INSN_CODE (insn) = icode;
3192 /* Restore the old body. If there were any changes to it, we made a copy
3193 of it while the changes were still in place, so we'll correctly return
3194 a modified insn below. */
3197 /* Restore the old body. */
3198 for (i = 0; i < recog_data.n_operands; i++)
3199 *recog_data.operand_loc[i] = orig_operand[i];
3200 for (i = 0; i < recog_data.n_dups; i++)
3201 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3204 /* Update all elimination pairs to reflect the status after the current
3205 insn. The changes we make were determined by the earlier call to
3206 elimination_effects.
3208 We also detect a cases where register elimination cannot be done,
3209 namely, if a register would be both changed and referenced outside a MEM
3210 in the resulting insn since such an insn is often undefined and, even if
3211 not, we cannot know what meaning will be given to it. Note that it is
3212 valid to have a register used in an address in an insn that changes it
3213 (presumably with a pre- or post-increment or decrement).
3215 If anything changes, return nonzero. */
3217 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3220 ep->can_eliminate = 0;
3222 ep->ref_outside_mem = 0;
3224 if (ep->previous_offset != ep->offset)
3229 /* If we changed something, perform elimination in REG_NOTES. This is
3230 needed even when REPLACE is zero because a REG_DEAD note might refer
3231 to a register that we eliminate and could cause a different number
3232 of spill registers to be needed in the final reload pass than in
3234 if (val && REG_NOTES (insn) != 0)
3235 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3240 /* Loop through all elimination pairs.
3241 Recalculate the number not at initial offset.
3243 Compute the maximum offset (minimum offset if the stack does not
3244 grow downward) for each elimination pair. */
3247 update_eliminable_offsets ()
3249 struct elim_table *ep;
3251 num_not_at_initial_offset = 0;
3252 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 ep->previous_offset = ep->offset;
3255 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3256 num_not_at_initial_offset++;
3260 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3261 replacement we currently believe is valid, mark it as not eliminable if X
3262 modifies DEST in any way other than by adding a constant integer to it.
3264 If DEST is the frame pointer, we do nothing because we assume that
3265 all assignments to the hard frame pointer are nonlocal gotos and are being
3266 done at a time when they are valid and do not disturb anything else.
3267 Some machines want to eliminate a fake argument pointer with either the
3268 frame or stack pointer. Assignments to the hard frame pointer must not
3269 prevent this elimination.
3271 Called via note_stores from reload before starting its passes to scan
3272 the insns of the function. */
3275 mark_not_eliminable (dest, x, data)
3278 void *data ATTRIBUTE_UNUSED;
3280 register unsigned int i;
3282 /* A SUBREG of a hard register here is just changing its mode. We should
3283 not see a SUBREG of an eliminable hard register, but check just in
3285 if (GET_CODE (dest) == SUBREG)
3286 dest = SUBREG_REG (dest);
3288 if (dest == hard_frame_pointer_rtx)
3291 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3292 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3293 && (GET_CODE (x) != SET
3294 || GET_CODE (SET_SRC (x)) != PLUS
3295 || XEXP (SET_SRC (x), 0) != dest
3296 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3298 reg_eliminate[i].can_eliminate_previous
3299 = reg_eliminate[i].can_eliminate = 0;
3304 /* Verify that the initial elimination offsets did not change since the
3305 last call to set_initial_elim_offsets. This is used to catch cases
3306 where something illegal happened during reload_as_needed that could
3307 cause incorrect code to be generated if we did not check for it. */
3310 verify_initial_elim_offsets ()
3314 #ifdef ELIMINABLE_REGS
3315 struct elim_table *ep;
3317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3319 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3320 if (t != ep->initial_offset)
3324 INITIAL_FRAME_POINTER_OFFSET (t);
3325 if (t != reg_eliminate[0].initial_offset)
3330 /* Reset all offsets on eliminable registers to their initial values. */
3333 set_initial_elim_offsets ()
3335 struct elim_table *ep = reg_eliminate;
3337 #ifdef ELIMINABLE_REGS
3338 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3340 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3341 ep->previous_offset = ep->offset = ep->initial_offset;
3344 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3345 ep->previous_offset = ep->offset = ep->initial_offset;
3348 num_not_at_initial_offset = 0;
3351 /* Initialize the known label offsets.
3352 Set a known offset for each forced label to be at the initial offset
3353 of each elimination. We do this because we assume that all
3354 computed jumps occur from a location where each elimination is
3355 at its initial offset.
3356 For all other labels, show that we don't know the offsets. */
3359 set_initial_label_offsets ()
3362 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3364 for (x = forced_labels; x; x = XEXP (x, 1))
3366 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3369 /* Set all elimination offsets to the known values for the code label given
3373 set_offsets_for_label (insn)
3377 int label_nr = CODE_LABEL_NUMBER (insn);
3378 struct elim_table *ep;
3380 num_not_at_initial_offset = 0;
3381 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3383 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3384 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3385 num_not_at_initial_offset++;
3389 /* See if anything that happened changes which eliminations are valid.
3390 For example, on the Sparc, whether or not the frame pointer can
3391 be eliminated can depend on what registers have been used. We need
3392 not check some conditions again (such as flag_omit_frame_pointer)
3393 since they can't have changed. */
3396 update_eliminables (pset)
3399 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3400 int previous_frame_pointer_needed = frame_pointer_needed;
3402 struct elim_table *ep;
3404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3405 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3406 #ifdef ELIMINABLE_REGS
3407 || ! CAN_ELIMINATE (ep->from, ep->to)
3410 ep->can_eliminate = 0;
3412 /* Look for the case where we have discovered that we can't replace
3413 register A with register B and that means that we will now be
3414 trying to replace register A with register C. This means we can
3415 no longer replace register C with register B and we need to disable
3416 such an elimination, if it exists. This occurs often with A == ap,
3417 B == sp, and C == fp. */
3419 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3421 struct elim_table *op;
3422 register int new_to = -1;
3424 if (! ep->can_eliminate && ep->can_eliminate_previous)
3426 /* Find the current elimination for ep->from, if there is a
3428 for (op = reg_eliminate;
3429 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3430 if (op->from == ep->from && op->can_eliminate)
3436 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3438 for (op = reg_eliminate;
3439 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3440 if (op->from == new_to && op->to == ep->to)
3441 op->can_eliminate = 0;
3445 /* See if any registers that we thought we could eliminate the previous
3446 time are no longer eliminable. If so, something has changed and we
3447 must spill the register. Also, recompute the number of eliminable
3448 registers and see if the frame pointer is needed; it is if there is
3449 no elimination of the frame pointer that we can perform. */
3451 frame_pointer_needed = 1;
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3455 && ep->to != HARD_FRAME_POINTER_REGNUM)
3456 frame_pointer_needed = 0;
3458 if (! ep->can_eliminate && ep->can_eliminate_previous)
3460 ep->can_eliminate_previous = 0;
3461 SET_HARD_REG_BIT (*pset, ep->from);
3466 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3467 /* If we didn't need a frame pointer last time, but we do now, spill
3468 the hard frame pointer. */
3469 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3470 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3474 /* Initialize the table of registers to eliminate. */
3479 struct elim_table *ep;
3480 #ifdef ELIMINABLE_REGS
3481 struct elim_table_1 *ep1;
3485 reg_eliminate = (struct elim_table *)
3486 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3488 /* Does this function require a frame pointer? */
3490 frame_pointer_needed = (! flag_omit_frame_pointer
3491 #ifdef EXIT_IGNORE_STACK
3492 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3493 and restore sp for alloca. So we can't eliminate
3494 the frame pointer in that case. At some point,
3495 we should improve this by emitting the
3496 sp-adjusting insns for this case. */
3497 || (current_function_calls_alloca
3498 && EXIT_IGNORE_STACK)
3500 || FRAME_POINTER_REQUIRED);
3504 #ifdef ELIMINABLE_REGS
3505 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3506 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3508 ep->from = ep1->from;
3510 ep->can_eliminate = ep->can_eliminate_previous
3511 = (CAN_ELIMINATE (ep->from, ep->to)
3512 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3515 reg_eliminate[0].from = reg_eliminate_1[0].from;
3516 reg_eliminate[0].to = reg_eliminate_1[0].to;
3517 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3518 = ! frame_pointer_needed;
3521 /* Count the number of eliminable registers and build the FROM and TO
3522 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3523 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3524 We depend on this. */
3525 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3527 num_eliminable += ep->can_eliminate;
3528 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3529 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3533 /* Kick all pseudos out of hard register REGNO.
3535 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3536 because we found we can't eliminate some register. In the case, no pseudos
3537 are allowed to be in the register, even if they are only in a block that
3538 doesn't require spill registers, unlike the case when we are spilling this
3539 hard reg to produce another spill register.
3541 Return nonzero if any pseudos needed to be kicked out. */
3544 spill_hard_reg (regno, cant_eliminate)
3552 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3553 regs_ever_live[regno] = 1;
3556 /* Spill every pseudo reg that was allocated to this reg
3557 or to something that overlaps this reg. */
3559 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3560 if (reg_renumber[i] >= 0
3561 && (unsigned int) reg_renumber[i] <= regno
3562 && ((unsigned int) reg_renumber[i]
3563 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3564 PSEUDO_REGNO_MODE (i))
3566 SET_REGNO_REG_SET (&spilled_pseudos, i);
3569 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3570 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3573 ior_hard_reg_set (set1, set2)
3574 HARD_REG_SET *set1, *set2;
3576 IOR_HARD_REG_SET (*set1, *set2);
3579 /* After find_reload_regs has been run for all insn that need reloads,
3580 and/or spill_hard_regs was called, this function is used to actually
3581 spill pseudo registers and try to reallocate them. It also sets up the
3582 spill_regs array for use by choose_reload_regs. */
3585 finish_spills (global)
3588 struct insn_chain *chain;
3589 int something_changed = 0;
3592 /* Build the spill_regs array for the function. */
3593 /* If there are some registers still to eliminate and one of the spill regs
3594 wasn't ever used before, additional stack space may have to be
3595 allocated to store this register. Thus, we may have changed the offset
3596 between the stack and frame pointers, so mark that something has changed.
3598 One might think that we need only set VAL to 1 if this is a call-used
3599 register. However, the set of registers that must be saved by the
3600 prologue is not identical to the call-used set. For example, the
3601 register used by the call insn for the return PC is a call-used register,
3602 but must be saved by the prologue. */
3605 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3606 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3608 spill_reg_order[i] = n_spills;
3609 spill_regs[n_spills++] = i;
3610 if (num_eliminable && ! regs_ever_live[i])
3611 something_changed = 1;
3612 regs_ever_live[i] = 1;
3615 spill_reg_order[i] = -1;
3617 EXECUTE_IF_SET_IN_REG_SET
3618 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3620 /* Record the current hard register the pseudo is allocated to in
3621 pseudo_previous_regs so we avoid reallocating it to the same
3622 hard reg in a later pass. */
3623 if (reg_renumber[i] < 0)
3626 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3627 /* Mark it as no longer having a hard register home. */
3628 reg_renumber[i] = -1;
3629 /* We will need to scan everything again. */
3630 something_changed = 1;
3633 /* Retry global register allocation if possible. */
3636 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3637 /* For every insn that needs reloads, set the registers used as spill
3638 regs in pseudo_forbidden_regs for every pseudo live across the
3640 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3642 EXECUTE_IF_SET_IN_REG_SET
3643 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3645 ior_hard_reg_set (pseudo_forbidden_regs + i,
3646 &chain->used_spill_regs);
3648 EXECUTE_IF_SET_IN_REG_SET
3649 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3651 ior_hard_reg_set (pseudo_forbidden_regs + i,
3652 &chain->used_spill_regs);
3656 /* Retry allocating the spilled pseudos. For each reg, merge the
3657 various reg sets that indicate which hard regs can't be used,
3658 and call retry_global_alloc.
3659 We change spill_pseudos here to only contain pseudos that did not
3660 get a new hard register. */
3661 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3662 if (reg_old_renumber[i] != reg_renumber[i])
3664 HARD_REG_SET forbidden;
3665 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3666 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3667 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3668 retry_global_alloc (i, forbidden);
3669 if (reg_renumber[i] >= 0)
3670 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3674 /* Fix up the register information in the insn chain.
3675 This involves deleting those of the spilled pseudos which did not get
3676 a new hard register home from the live_{before,after} sets. */
3677 for (chain = reload_insn_chain; chain; chain = chain->next)
3679 HARD_REG_SET used_by_pseudos;
3680 HARD_REG_SET used_by_pseudos2;
3682 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3683 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3685 /* Mark any unallocated hard regs as available for spills. That
3686 makes inheritance work somewhat better. */
3687 if (chain->need_reload)
3689 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3691 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3693 /* Save the old value for the sanity test below. */
3694 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3696 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3698 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3699 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3701 /* Make sure we only enlarge the set. */
3702 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3708 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3709 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3711 int regno = reg_renumber[i];
3712 if (reg_old_renumber[i] == regno)
3715 alter_reg (i, reg_old_renumber[i]);
3716 reg_old_renumber[i] = regno;
3720 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3722 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3723 i, reg_renumber[i]);
3727 return something_changed;
3730 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3731 Also mark any hard registers used to store user variables as
3732 forbidden from being used for spill registers. */
3735 scan_paradoxical_subregs (x)
3739 register const char *fmt;
3740 register enum rtx_code code = GET_CODE (x);
3746 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3747 && REG_USERVAR_P (x))
3748 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3764 if (GET_CODE (SUBREG_REG (x)) == REG
3765 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3766 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3767 = GET_MODE_SIZE (GET_MODE (x));
3774 fmt = GET_RTX_FORMAT (code);
3775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3778 scan_paradoxical_subregs (XEXP (x, i));
3779 else if (fmt[i] == 'E')
3782 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3783 scan_paradoxical_subregs (XVECEXP (x, i, j));
3788 /* Reload pseudo-registers into hard regs around each insn as needed.
3789 Additional register load insns are output before the insn that needs it
3790 and perhaps store insns after insns that modify the reloaded pseudo reg.
3792 reg_last_reload_reg and reg_reloaded_contents keep track of
3793 which registers are already available in reload registers.
3794 We update these for the reloads that we perform,
3795 as the insns are scanned. */
3798 reload_as_needed (live_known)
3801 struct insn_chain *chain;
3802 #if defined (AUTO_INC_DEC)
3807 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3808 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3809 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3810 reg_has_output_reload = (char *) xmalloc (max_regno);
3811 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3813 set_initial_elim_offsets ();
3815 for (chain = reload_insn_chain; chain; chain = chain->next)
3818 rtx insn = chain->insn;
3819 rtx old_next = NEXT_INSN (insn);
3821 /* If we pass a label, copy the offsets from the label information
3822 into the current offsets of each elimination. */
3823 if (GET_CODE (insn) == CODE_LABEL)
3824 set_offsets_for_label (insn);
3826 else if (INSN_P (insn))
3828 rtx oldpat = PATTERN (insn);
3830 /* If this is a USE and CLOBBER of a MEM, ensure that any
3831 references to eliminable registers have been removed. */
3833 if ((GET_CODE (PATTERN (insn)) == USE
3834 || GET_CODE (PATTERN (insn)) == CLOBBER)
3835 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3836 XEXP (XEXP (PATTERN (insn), 0), 0)
3837 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3838 GET_MODE (XEXP (PATTERN (insn), 0)),
3841 /* If we need to do register elimination processing, do so.
3842 This might delete the insn, in which case we are done. */
3843 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3845 eliminate_regs_in_insn (insn, 1);
3846 if (GET_CODE (insn) == NOTE)
3848 update_eliminable_offsets ();
3853 /* If need_elim is nonzero but need_reload is zero, one might think
3854 that we could simply set n_reloads to 0. However, find_reloads
3855 could have done some manipulation of the insn (such as swapping
3856 commutative operands), and these manipulations are lost during
3857 the first pass for every insn that needs register elimination.
3858 So the actions of find_reloads must be redone here. */
3860 if (! chain->need_elim && ! chain->need_reload
3861 && ! chain->need_operand_change)
3863 /* First find the pseudo regs that must be reloaded for this insn.
3864 This info is returned in the tables reload_... (see reload.h).
3865 Also modify the body of INSN by substituting RELOAD
3866 rtx's for those pseudo regs. */
3869 memset (reg_has_output_reload, 0, max_regno);
3870 CLEAR_HARD_REG_SET (reg_is_output_reload);
3872 find_reloads (insn, 1, spill_indirect_levels, live_known,
3876 if (num_eliminable && chain->need_elim)
3877 update_eliminable_offsets ();
3881 rtx next = NEXT_INSN (insn);
3884 prev = PREV_INSN (insn);
3886 /* Now compute which reload regs to reload them into. Perhaps
3887 reusing reload regs from previous insns, or else output
3888 load insns to reload them. Maybe output store insns too.
3889 Record the choices of reload reg in reload_reg_rtx. */
3890 choose_reload_regs (chain);
3892 /* Merge any reloads that we didn't combine for fear of
3893 increasing the number of spill registers needed but now
3894 discover can be safely merged. */
3895 if (SMALL_REGISTER_CLASSES)
3896 merge_assigned_reloads (insn);
3898 /* Generate the insns to reload operands into or out of
3899 their reload regs. */
3900 emit_reload_insns (chain);
3902 /* Substitute the chosen reload regs from reload_reg_rtx
3903 into the insn's body (or perhaps into the bodies of other
3904 load and store insn that we just made for reloading
3905 and that we moved the structure into). */
3906 subst_reloads (insn);
3908 /* If this was an ASM, make sure that all the reload insns
3909 we have generated are valid. If not, give an error
3912 if (asm_noperands (PATTERN (insn)) >= 0)
3913 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3914 if (p != insn && INSN_P (p)
3915 && (recog_memoized (p) < 0
3916 || (extract_insn (p), ! constrain_operands (1))))
3918 error_for_asm (insn,
3919 "`asm' operand requires impossible reload");
3921 NOTE_SOURCE_FILE (p) = 0;
3922 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3925 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3926 is no longer validly lying around to save a future reload.
3927 Note that this does not detect pseudos that were reloaded
3928 for this insn in order to be stored in
3929 (obeying register constraints). That is correct; such reload
3930 registers ARE still valid. */
3931 note_stores (oldpat, forget_old_reloads_1, NULL);
3933 /* There may have been CLOBBER insns placed after INSN. So scan
3934 between INSN and NEXT and use them to forget old reloads. */
3935 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3936 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3937 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3940 /* Likewise for regs altered by auto-increment in this insn.
3941 REG_INC notes have been changed by reloading:
3942 find_reloads_address_1 records substitutions for them,
3943 which have been performed by subst_reloads above. */
3944 for (i = n_reloads - 1; i >= 0; i--)
3946 rtx in_reg = rld[i].in_reg;
3949 enum rtx_code code = GET_CODE (in_reg);
3950 /* PRE_INC / PRE_DEC will have the reload register ending up
3951 with the same value as the stack slot, but that doesn't
3952 hold true for POST_INC / POST_DEC. Either we have to
3953 convert the memory access to a true POST_INC / POST_DEC,
3954 or we can't use the reload register for inheritance. */
3955 if ((code == POST_INC || code == POST_DEC)
3956 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3957 REGNO (rld[i].reg_rtx))
3958 /* Make sure it is the inc/dec pseudo, and not
3959 some other (e.g. output operand) pseudo. */
3960 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3961 == REGNO (XEXP (in_reg, 0))))
3964 rtx reload_reg = rld[i].reg_rtx;
3965 enum machine_mode mode = GET_MODE (reload_reg);
3969 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3971 /* We really want to ignore REG_INC notes here, so
3972 use PATTERN (p) as argument to reg_set_p . */
3973 if (reg_set_p (reload_reg, PATTERN (p)))
3975 n = count_occurrences (PATTERN (p), reload_reg, 0);
3980 n = validate_replace_rtx (reload_reg,
3981 gen_rtx (code, mode,
3985 /* We must also verify that the constraints
3986 are met after the replacement. */
3989 n = constrain_operands (1);
3993 /* If the constraints were not met, then
3994 undo the replacement. */
3997 validate_replace_rtx (gen_rtx (code, mode,
4009 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4011 /* Mark this as having an output reload so that the
4012 REG_INC processing code below won't invalidate
4013 the reload for inheritance. */
4014 SET_HARD_REG_BIT (reg_is_output_reload,
4015 REGNO (reload_reg));
4016 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4019 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4022 else if ((code == PRE_INC || code == PRE_DEC)
4023 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4024 REGNO (rld[i].reg_rtx))
4025 /* Make sure it is the inc/dec pseudo, and not
4026 some other (e.g. output operand) pseudo. */
4027 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4028 == REGNO (XEXP (in_reg, 0))))
4030 SET_HARD_REG_BIT (reg_is_output_reload,
4031 REGNO (rld[i].reg_rtx));
4032 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4036 /* If a pseudo that got a hard register is auto-incremented,
4037 we must purge records of copying it into pseudos without
4039 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4040 if (REG_NOTE_KIND (x) == REG_INC)
4042 /* See if this pseudo reg was reloaded in this insn.
4043 If so, its last-reload info is still valid
4044 because it is based on this insn's reload. */
4045 for (i = 0; i < n_reloads; i++)
4046 if (rld[i].out == XEXP (x, 0))
4050 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4054 /* A reload reg's contents are unknown after a label. */
4055 if (GET_CODE (insn) == CODE_LABEL)
4056 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4058 /* Don't assume a reload reg is still good after a call insn
4059 if it is a call-used reg. */
4060 else if (GET_CODE (insn) == CALL_INSN)
4061 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4065 free (reg_last_reload_reg);
4066 free (reg_has_output_reload);
4069 /* Discard all record of any value reloaded from X,
4070 or reloaded in X from someplace else;
4071 unless X is an output reload reg of the current insn.
4073 X may be a hard reg (the reload reg)
4074 or it may be a pseudo reg that was reloaded from. */
4077 forget_old_reloads_1 (x, ignored, data)
4079 rtx ignored ATTRIBUTE_UNUSED;
4080 void *data ATTRIBUTE_UNUSED;
4086 /* note_stores does give us subregs of hard regs,
4087 subreg_regno_offset will abort if it is not a hard reg. */
4088 while (GET_CODE (x) == SUBREG)
4090 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4091 GET_MODE (SUBREG_REG (x)),
4097 if (GET_CODE (x) != REG)
4100 regno = REGNO (x) + offset;
4102 if (regno >= FIRST_PSEUDO_REGISTER)
4108 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4109 /* Storing into a spilled-reg invalidates its contents.
4110 This can happen if a block-local pseudo is allocated to that reg
4111 and it wasn't spilled because this block's total need is 0.
4112 Then some insn might have an optional reload and use this reg. */
4113 for (i = 0; i < nr; i++)
4114 /* But don't do this if the reg actually serves as an output
4115 reload reg in the current instruction. */
4117 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4119 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4120 spill_reg_store[regno + i] = 0;
4124 /* Since value of X has changed,
4125 forget any value previously copied from it. */
4128 /* But don't forget a copy if this is the output reload
4129 that establishes the copy's validity. */
4130 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4131 reg_last_reload_reg[regno + nr] = 0;
4134 /* The following HARD_REG_SETs indicate when each hard register is
4135 used for a reload of various parts of the current insn. */
4137 /* If reg is unavailable for all reloads. */
4138 static HARD_REG_SET reload_reg_unavailable;
4139 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4140 static HARD_REG_SET reload_reg_used;
4141 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4146 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4147 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4148 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4149 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4150 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4151 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4152 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4153 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4154 static HARD_REG_SET reload_reg_used_in_op_addr;
4155 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4156 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4157 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4158 static HARD_REG_SET reload_reg_used_in_insn;
4159 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4160 static HARD_REG_SET reload_reg_used_in_other_addr;
4162 /* If reg is in use as a reload reg for any sort of reload. */
4163 static HARD_REG_SET reload_reg_used_at_all;
4165 /* If reg is use as an inherited reload. We just mark the first register
4167 static HARD_REG_SET reload_reg_used_for_inherit;
4169 /* Records which hard regs are used in any way, either as explicit use or
4170 by being allocated to a pseudo during any point of the current insn. */
4171 static HARD_REG_SET reg_used_in_insn;
4173 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4174 TYPE. MODE is used to indicate how many consecutive regs are
4178 mark_reload_reg_in_use (regno, opnum, type, mode)
4181 enum reload_type type;
4182 enum machine_mode mode;
4184 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4187 for (i = regno; i < nregs + regno; i++)
4192 SET_HARD_REG_BIT (reload_reg_used, i);
4195 case RELOAD_FOR_INPUT_ADDRESS:
4196 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4199 case RELOAD_FOR_INPADDR_ADDRESS:
4200 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4203 case RELOAD_FOR_OUTPUT_ADDRESS:
4204 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4207 case RELOAD_FOR_OUTADDR_ADDRESS:
4208 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4211 case RELOAD_FOR_OPERAND_ADDRESS:
4212 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4215 case RELOAD_FOR_OPADDR_ADDR:
4216 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4219 case RELOAD_FOR_OTHER_ADDRESS:
4220 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4223 case RELOAD_FOR_INPUT:
4224 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4227 case RELOAD_FOR_OUTPUT:
4228 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4231 case RELOAD_FOR_INSN:
4232 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4236 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4240 /* Similarly, but show REGNO is no longer in use for a reload. */
4243 clear_reload_reg_in_use (regno, opnum, type, mode)
4246 enum reload_type type;
4247 enum machine_mode mode;
4249 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4250 unsigned int start_regno, end_regno, r;
4252 /* A complication is that for some reload types, inheritance might
4253 allow multiple reloads of the same types to share a reload register.
4254 We set check_opnum if we have to check only reloads with the same
4255 operand number, and check_any if we have to check all reloads. */
4256 int check_opnum = 0;
4258 HARD_REG_SET *used_in_set;
4263 used_in_set = &reload_reg_used;
4266 case RELOAD_FOR_INPUT_ADDRESS:
4267 used_in_set = &reload_reg_used_in_input_addr[opnum];
4270 case RELOAD_FOR_INPADDR_ADDRESS:
4272 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4275 case RELOAD_FOR_OUTPUT_ADDRESS:
4276 used_in_set = &reload_reg_used_in_output_addr[opnum];
4279 case RELOAD_FOR_OUTADDR_ADDRESS:
4281 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4284 case RELOAD_FOR_OPERAND_ADDRESS:
4285 used_in_set = &reload_reg_used_in_op_addr;
4288 case RELOAD_FOR_OPADDR_ADDR:
4290 used_in_set = &reload_reg_used_in_op_addr_reload;
4293 case RELOAD_FOR_OTHER_ADDRESS:
4294 used_in_set = &reload_reg_used_in_other_addr;
4298 case RELOAD_FOR_INPUT:
4299 used_in_set = &reload_reg_used_in_input[opnum];
4302 case RELOAD_FOR_OUTPUT:
4303 used_in_set = &reload_reg_used_in_output[opnum];
4306 case RELOAD_FOR_INSN:
4307 used_in_set = &reload_reg_used_in_insn;
4312 /* We resolve conflicts with remaining reloads of the same type by
4313 excluding the intervals of of reload registers by them from the
4314 interval of freed reload registers. Since we only keep track of
4315 one set of interval bounds, we might have to exclude somewhat
4316 more then what would be necessary if we used a HARD_REG_SET here.
4317 But this should only happen very infrequently, so there should
4318 be no reason to worry about it. */
4320 start_regno = regno;
4321 end_regno = regno + nregs;
4322 if (check_opnum || check_any)
4324 for (i = n_reloads - 1; i >= 0; i--)
4326 if (rld[i].when_needed == type
4327 && (check_any || rld[i].opnum == opnum)
4330 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4331 unsigned int conflict_end
4333 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4335 /* If there is an overlap with the first to-be-freed register,
4336 adjust the interval start. */
4337 if (conflict_start <= start_regno && conflict_end > start_regno)
4338 start_regno = conflict_end;
4339 /* Otherwise, if there is a conflict with one of the other
4340 to-be-freed registers, adjust the interval end. */
4341 if (conflict_start > start_regno && conflict_start < end_regno)
4342 end_regno = conflict_start;
4347 for (r = start_regno; r < end_regno; r++)
4348 CLEAR_HARD_REG_BIT (*used_in_set, r);
4351 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4352 specified by OPNUM and TYPE. */
4355 reload_reg_free_p (regno, opnum, type)
4358 enum reload_type type;
4362 /* In use for a RELOAD_OTHER means it's not available for anything. */
4363 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4364 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4370 /* In use for anything means we can't use it for RELOAD_OTHER. */
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4376 for (i = 0; i < reload_n_operands; i++)
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4387 case RELOAD_FOR_INPUT:
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4395 /* If it is used for some other input, can't use it. */
4396 for (i = 0; i < reload_n_operands; i++)
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4400 /* If it is used in a later operand's address, can't use it. */
4401 for (i = opnum + 1; i < reload_n_operands; i++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4408 case RELOAD_FOR_INPUT_ADDRESS:
4409 /* Can't use a register if it is used for an input address for this
4410 operand or used as an input in an earlier one. */
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4415 for (i = 0; i < opnum; i++)
4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4421 case RELOAD_FOR_INPADDR_ADDRESS:
4422 /* Can't use a register if it is used for an input address
4423 for this operand or used as an input in an earlier
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4428 for (i = 0; i < opnum; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4434 case RELOAD_FOR_OUTPUT_ADDRESS:
4435 /* Can't use a register if it is used for an output address for this
4436 operand or used as an output in this or a later operand. */
4437 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4440 for (i = opnum; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4446 case RELOAD_FOR_OUTADDR_ADDRESS:
4447 /* Can't use a register if it is used for an output address
4448 for this operand or used as an output in this or a
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4453 for (i = opnum; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4459 case RELOAD_FOR_OPERAND_ADDRESS:
4460 for (i = 0; i < reload_n_operands; i++)
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4465 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4467 case RELOAD_FOR_OPADDR_ADDR:
4468 for (i = 0; i < reload_n_operands; i++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4472 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4474 case RELOAD_FOR_OUTPUT:
4475 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4476 outputs, or an operand address for this or an earlier output. */
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4480 for (i = 0; i < reload_n_operands; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4484 for (i = 0; i <= opnum; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4491 case RELOAD_FOR_INSN:
4492 for (i = 0; i < reload_n_operands; i++)
4493 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4497 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4498 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4500 case RELOAD_FOR_OTHER_ADDRESS:
4501 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4506 /* Return 1 if the value in reload reg REGNO, as used by a reload
4507 needed for the part of the insn specified by OPNUM and TYPE,
4508 is still available in REGNO at the end of the insn.
4510 We can assume that the reload reg was already tested for availability
4511 at the time it is needed, and we should not check this again,
4512 in case the reg has already been marked in use. */
4515 reload_reg_reaches_end_p (regno, opnum, type)
4518 enum reload_type type;
4525 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4526 its value must reach the end. */
4529 /* If this use is for part of the insn,
4530 its value reaches if no subsequent part uses the same register.
4531 Just like the above function, don't try to do this with lots
4534 case RELOAD_FOR_OTHER_ADDRESS:
4535 /* Here we check for everything else, since these don't conflict
4536 with anything else and everything comes later. */
4538 for (i = 0; i < reload_n_operands; i++)
4539 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4547 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4548 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4549 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4551 case RELOAD_FOR_INPUT_ADDRESS:
4552 case RELOAD_FOR_INPADDR_ADDRESS:
4553 /* Similar, except that we check only for this and subsequent inputs
4554 and the address of only subsequent inputs and we do not need
4555 to check for RELOAD_OTHER objects since they are known not to
4558 for (i = opnum; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4562 for (i = opnum + 1; i < reload_n_operands; i++)
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4567 for (i = 0; i < reload_n_operands; i++)
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4573 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4576 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4577 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4578 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4580 case RELOAD_FOR_INPUT:
4581 /* Similar to input address, except we start at the next operand for
4582 both input and input address and we do not check for
4583 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4586 for (i = opnum + 1; i < reload_n_operands; i++)
4587 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4588 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4592 /* ... fall through ... */
4594 case RELOAD_FOR_OPERAND_ADDRESS:
4595 /* Check outputs and their addresses. */
4597 for (i = 0; i < reload_n_operands; i++)
4598 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4599 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4603 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4605 case RELOAD_FOR_OPADDR_ADDR:
4606 for (i = 0; i < reload_n_operands; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4612 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4613 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4614 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4616 case RELOAD_FOR_INSN:
4617 /* These conflict with other outputs with RELOAD_OTHER. So
4618 we need only check for output addresses. */
4622 /* ... fall through ... */
4624 case RELOAD_FOR_OUTPUT:
4625 case RELOAD_FOR_OUTPUT_ADDRESS:
4626 case RELOAD_FOR_OUTADDR_ADDRESS:
4627 /* We already know these can't conflict with a later output. So the
4628 only thing to check are later output addresses. */
4629 for (i = opnum + 1; i < reload_n_operands; i++)
4630 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4631 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4640 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4643 This function uses the same algorithm as reload_reg_free_p above. */
4646 reloads_conflict (r1, r2)
4649 enum reload_type r1_type = rld[r1].when_needed;
4650 enum reload_type r2_type = rld[r2].when_needed;
4651 int r1_opnum = rld[r1].opnum;
4652 int r2_opnum = rld[r2].opnum;
4654 /* RELOAD_OTHER conflicts with everything. */
4655 if (r2_type == RELOAD_OTHER)
4658 /* Otherwise, check conflicts differently for each type. */
4662 case RELOAD_FOR_INPUT:
4663 return (r2_type == RELOAD_FOR_INSN
4664 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4665 || r2_type == RELOAD_FOR_OPADDR_ADDR
4666 || r2_type == RELOAD_FOR_INPUT
4667 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4668 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4669 && r2_opnum > r1_opnum));
4671 case RELOAD_FOR_INPUT_ADDRESS:
4672 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4673 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4675 case RELOAD_FOR_INPADDR_ADDRESS:
4676 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4677 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4679 case RELOAD_FOR_OUTPUT_ADDRESS:
4680 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4681 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4683 case RELOAD_FOR_OUTADDR_ADDRESS:
4684 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4685 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4687 case RELOAD_FOR_OPERAND_ADDRESS:
4688 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4689 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4691 case RELOAD_FOR_OPADDR_ADDR:
4692 return (r2_type == RELOAD_FOR_INPUT
4693 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4695 case RELOAD_FOR_OUTPUT:
4696 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4697 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4698 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4699 && r2_opnum <= r1_opnum));
4701 case RELOAD_FOR_INSN:
4702 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4703 || r2_type == RELOAD_FOR_INSN
4704 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4706 case RELOAD_FOR_OTHER_ADDRESS:
4707 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4717 /* Indexed by reload number, 1 if incoming value
4718 inherited from previous insns. */
4719 char reload_inherited[MAX_RELOADS];
4721 /* For an inherited reload, this is the insn the reload was inherited from,
4722 if we know it. Otherwise, this is 0. */
4723 rtx reload_inheritance_insn[MAX_RELOADS];
4725 /* If non-zero, this is a place to get the value of the reload,
4726 rather than using reload_in. */
4727 rtx reload_override_in[MAX_RELOADS];
4729 /* For each reload, the hard register number of the register used,
4730 or -1 if we did not need a register for this reload. */
4731 int reload_spill_index[MAX_RELOADS];
4733 /* Subroutine of free_for_value_p, used to check a single register.
4734 START_REGNO is the starting regno of the full reload register
4735 (possibly comprising multiple hard registers) that we are considering. */
4738 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4739 reloadnum, ignore_address_reloads)
4740 int start_regno, regno;
4742 enum reload_type type;
4745 int ignore_address_reloads;
4748 /* Set if we see an input reload that must not share its reload register
4749 with any new earlyclobber, but might otherwise share the reload
4750 register with an output or input-output reload. */
4751 int check_earlyclobber = 0;
4755 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4758 if (out == const0_rtx)
4764 /* We use some pseudo 'time' value to check if the lifetimes of the
4765 new register use would overlap with the one of a previous reload
4766 that is not read-only or uses a different value.
4767 The 'time' used doesn't have to be linear in any shape or form, just
4769 Some reload types use different 'buckets' for each operand.
4770 So there are MAX_RECOG_OPERANDS different time values for each
4772 We compute TIME1 as the time when the register for the prospective
4773 new reload ceases to be live, and TIME2 for each existing
4774 reload as the time when that the reload register of that reload
4776 Where there is little to be gained by exact lifetime calculations,
4777 we just make conservative assumptions, i.e. a longer lifetime;
4778 this is done in the 'default:' cases. */
4781 case RELOAD_FOR_OTHER_ADDRESS:
4782 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4783 time1 = copy ? 0 : 1;
4786 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4788 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4789 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4790 respectively, to the time values for these, we get distinct time
4791 values. To get distinct time values for each operand, we have to
4792 multiply opnum by at least three. We round that up to four because
4793 multiply by four is often cheaper. */
4794 case RELOAD_FOR_INPADDR_ADDRESS:
4795 time1 = opnum * 4 + 2;
4797 case RELOAD_FOR_INPUT_ADDRESS:
4798 time1 = opnum * 4 + 3;
4800 case RELOAD_FOR_INPUT:
4801 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4802 executes (inclusive). */
4803 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4805 case RELOAD_FOR_OPADDR_ADDR:
4807 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4808 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4810 case RELOAD_FOR_OPERAND_ADDRESS:
4811 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4813 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4815 case RELOAD_FOR_OUTADDR_ADDRESS:
4816 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4818 case RELOAD_FOR_OUTPUT_ADDRESS:
4819 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4822 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4825 for (i = 0; i < n_reloads; i++)
4827 rtx reg = rld[i].reg_rtx;
4828 if (reg && GET_CODE (reg) == REG
4829 && ((unsigned) regno - true_regnum (reg)
4830 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4833 rtx other_input = rld[i].in;
4835 /* If the other reload loads the same input value, that
4836 will not cause a conflict only if it's loading it into
4837 the same register. */
4838 if (true_regnum (reg) != start_regno)
4839 other_input = NULL_RTX;
4840 if (! other_input || ! rtx_equal_p (other_input, value)
4841 || rld[i].out || out)
4844 switch (rld[i].when_needed)
4846 case RELOAD_FOR_OTHER_ADDRESS:
4849 case RELOAD_FOR_INPADDR_ADDRESS:
4850 /* find_reloads makes sure that a
4851 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4852 by at most one - the first -
4853 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4854 address reload is inherited, the address address reload
4855 goes away, so we can ignore this conflict. */
4856 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4857 && ignore_address_reloads
4858 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4859 Then the address address is still needed to store
4860 back the new address. */
4861 && ! rld[reloadnum].out)
4863 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4864 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4866 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4867 && ignore_address_reloads
4868 /* Unless we are reloading an auto_inc expression. */
4869 && ! rld[reloadnum].out)
4871 time2 = rld[i].opnum * 4 + 2;
4873 case RELOAD_FOR_INPUT_ADDRESS:
4874 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4875 && ignore_address_reloads
4876 && ! rld[reloadnum].out)
4878 time2 = rld[i].opnum * 4 + 3;
4880 case RELOAD_FOR_INPUT:
4881 time2 = rld[i].opnum * 4 + 4;
4882 check_earlyclobber = 1;
4884 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4885 == MAX_RECOG_OPERAND * 4 */
4886 case RELOAD_FOR_OPADDR_ADDR:
4887 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4888 && ignore_address_reloads
4889 && ! rld[reloadnum].out)
4891 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4893 case RELOAD_FOR_OPERAND_ADDRESS:
4894 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4895 check_earlyclobber = 1;
4897 case RELOAD_FOR_INSN:
4898 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4900 case RELOAD_FOR_OUTPUT:
4901 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4902 instruction is executed. */
4903 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4905 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4906 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4908 case RELOAD_FOR_OUTADDR_ADDRESS:
4909 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4910 && ignore_address_reloads
4911 && ! rld[reloadnum].out)
4913 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4915 case RELOAD_FOR_OUTPUT_ADDRESS:
4916 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4919 /* If there is no conflict in the input part, handle this
4920 like an output reload. */
4921 if (! rld[i].in || rtx_equal_p (other_input, value))
4923 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4924 /* Earlyclobbered outputs must conflict with inputs. */
4925 if (earlyclobber_operand_p (rld[i].out))
4926 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4931 /* RELOAD_OTHER might be live beyond instruction execution,
4932 but this is not obvious when we set time2 = 1. So check
4933 here if there might be a problem with the new reload
4934 clobbering the register used by the RELOAD_OTHER. */
4942 && (! rld[i].in || rld[i].out
4943 || ! rtx_equal_p (other_input, value)))
4944 || (out && rld[reloadnum].out_reg
4945 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4951 /* Earlyclobbered outputs must conflict with inputs. */
4952 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4958 /* Return 1 if the value in reload reg REGNO, as used by a reload
4959 needed for the part of the insn specified by OPNUM and TYPE,
4960 may be used to load VALUE into it.
4962 MODE is the mode in which the register is used, this is needed to
4963 determine how many hard regs to test.
4965 Other read-only reloads with the same value do not conflict
4966 unless OUT is non-zero and these other reloads have to live while
4967 output reloads live.
4968 If OUT is CONST0_RTX, this is a special case: it means that the
4969 test should not be for using register REGNO as reload register, but
4970 for copying from register REGNO into the reload register.
4972 RELOADNUM is the number of the reload we want to load this value for;
4973 a reload does not conflict with itself.
4975 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4976 reloads that load an address for the very reload we are considering.
4978 The caller has to make sure that there is no conflict with the return
4982 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4983 ignore_address_reloads)
4985 enum machine_mode mode;
4987 enum reload_type type;
4990 int ignore_address_reloads;
4992 int nregs = HARD_REGNO_NREGS (regno, mode);
4994 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4995 value, out, reloadnum,
4996 ignore_address_reloads))
5001 /* Determine whether the reload reg X overlaps any rtx'es used for
5002 overriding inheritance. Return nonzero if so. */
5005 conflicts_with_override (x)
5009 for (i = 0; i < n_reloads; i++)
5010 if (reload_override_in[i]
5011 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5016 /* Give an error message saying we failed to find a reload for INSN,
5017 and clear out reload R. */
5019 failed_reload (insn, r)
5023 if (asm_noperands (PATTERN (insn)) < 0)
5024 /* It's the compiler's fault. */
5025 fatal_insn ("Could not find a spill register", insn);
5027 /* It's the user's fault; the operand's mode and constraint
5028 don't match. Disable this reload so we don't crash in final. */
5029 error_for_asm (insn,
5030 "`asm' operand constraint incompatible with operand size");
5034 rld[r].optional = 1;
5035 rld[r].secondary_p = 1;
5038 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5039 for reload R. If it's valid, get an rtx for it. Return nonzero if
5042 set_reload_reg (i, r)
5046 rtx reg = spill_reg_rtx[i];
5048 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5049 spill_reg_rtx[i] = reg
5050 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5052 regno = true_regnum (reg);
5054 /* Detect when the reload reg can't hold the reload mode.
5055 This used to be one `if', but Sequent compiler can't handle that. */
5056 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5058 enum machine_mode test_mode = VOIDmode;
5060 test_mode = GET_MODE (rld[r].in);
5061 /* If rld[r].in has VOIDmode, it means we will load it
5062 in whatever mode the reload reg has: to wit, rld[r].mode.
5063 We have already tested that for validity. */
5064 /* Aside from that, we need to test that the expressions
5065 to reload from or into have modes which are valid for this
5066 reload register. Otherwise the reload insns would be invalid. */
5067 if (! (rld[r].in != 0 && test_mode != VOIDmode
5068 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5069 if (! (rld[r].out != 0
5070 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5072 /* The reg is OK. */
5075 /* Mark as in use for this insn the reload regs we use
5077 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5078 rld[r].when_needed, rld[r].mode);
5080 rld[r].reg_rtx = reg;
5081 reload_spill_index[r] = spill_regs[i];
5088 /* Find a spill register to use as a reload register for reload R.
5089 LAST_RELOAD is non-zero if this is the last reload for the insn being
5092 Set rld[R].reg_rtx to the register allocated.
5094 We return 1 if successful, or 0 if we couldn't find a spill reg and
5095 we didn't change anything. */
5098 allocate_reload_reg (chain, r, last_reload)
5099 struct insn_chain *chain ATTRIBUTE_UNUSED;
5105 /* If we put this reload ahead, thinking it is a group,
5106 then insist on finding a group. Otherwise we can grab a
5107 reg that some other reload needs.
5108 (That can happen when we have a 68000 DATA_OR_FP_REG
5109 which is a group of data regs or one fp reg.)
5110 We need not be so restrictive if there are no more reloads
5113 ??? Really it would be nicer to have smarter handling
5114 for that kind of reg class, where a problem like this is normal.
5115 Perhaps those classes should be avoided for reloading
5116 by use of more alternatives. */
5118 int force_group = rld[r].nregs > 1 && ! last_reload;
5120 /* If we want a single register and haven't yet found one,
5121 take any reg in the right class and not in use.
5122 If we want a consecutive group, here is where we look for it.
5124 We use two passes so we can first look for reload regs to
5125 reuse, which are already in use for other reloads in this insn,
5126 and only then use additional registers.
5127 I think that maximizing reuse is needed to make sure we don't
5128 run out of reload regs. Suppose we have three reloads, and
5129 reloads A and B can share regs. These need two regs.
5130 Suppose A and B are given different regs.
5131 That leaves none for C. */
5132 for (pass = 0; pass < 2; pass++)
5134 /* I is the index in spill_regs.
5135 We advance it round-robin between insns to use all spill regs
5136 equally, so that inherited reloads have a chance
5137 of leapfrogging each other. */
5141 for (count = 0; count < n_spills; count++)
5143 int class = (int) rld[r].class;
5149 regnum = spill_regs[i];
5151 if ((reload_reg_free_p (regnum, rld[r].opnum,
5154 /* We check reload_reg_used to make sure we
5155 don't clobber the return register. */
5156 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5157 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5158 rld[r].when_needed, rld[r].in,
5160 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5161 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5162 /* Look first for regs to share, then for unshared. But
5163 don't share regs used for inherited reloads; they are
5164 the ones we want to preserve. */
5166 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5168 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5171 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5172 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5173 (on 68000) got us two FP regs. If NR is 1,
5174 we would reject both of them. */
5177 /* If we need only one reg, we have already won. */
5180 /* But reject a single reg if we demand a group. */
5185 /* Otherwise check that as many consecutive regs as we need
5186 are available here. */
5189 int regno = regnum + nr - 1;
5190 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5191 && spill_reg_order[regno] >= 0
5192 && reload_reg_free_p (regno, rld[r].opnum,
5193 rld[r].when_needed)))
5202 /* If we found something on pass 1, omit pass 2. */
5203 if (count < n_spills)
5207 /* We should have found a spill register by now. */
5208 if (count >= n_spills)
5211 /* I is the index in SPILL_REG_RTX of the reload register we are to
5212 allocate. Get an rtx for it and find its register number. */
5214 return set_reload_reg (i, r);
5217 /* Initialize all the tables needed to allocate reload registers.
5218 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5219 is the array we use to restore the reg_rtx field for every reload. */
5222 choose_reload_regs_init (chain, save_reload_reg_rtx)
5223 struct insn_chain *chain;
5224 rtx *save_reload_reg_rtx;
5228 for (i = 0; i < n_reloads; i++)
5229 rld[i].reg_rtx = save_reload_reg_rtx[i];
5231 memset (reload_inherited, 0, MAX_RELOADS);
5232 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5233 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5235 CLEAR_HARD_REG_SET (reload_reg_used);
5236 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5240 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5242 CLEAR_HARD_REG_SET (reg_used_in_insn);
5245 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5246 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5247 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5248 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5249 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5250 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5253 for (i = 0; i < reload_n_operands; i++)
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5263 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5265 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5267 for (i = 0; i < n_reloads; i++)
5268 /* If we have already decided to use a certain register,
5269 don't use it in another way. */
5271 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5272 rld[i].when_needed, rld[i].mode);
5275 /* Assign hard reg targets for the pseudo-registers we must reload
5276 into hard regs for this insn.
5277 Also output the instructions to copy them in and out of the hard regs.
5279 For machines with register classes, we are responsible for
5280 finding a reload reg in the proper class. */
5283 choose_reload_regs (chain)
5284 struct insn_chain *chain;
5286 rtx insn = chain->insn;
5288 unsigned int max_group_size = 1;
5289 enum reg_class group_class = NO_REGS;
5290 int pass, win, inheritance;
5292 rtx save_reload_reg_rtx[MAX_RELOADS];
5294 /* In order to be certain of getting the registers we need,
5295 we must sort the reloads into order of increasing register class.
5296 Then our grabbing of reload registers will parallel the process
5297 that provided the reload registers.
5299 Also note whether any of the reloads wants a consecutive group of regs.
5300 If so, record the maximum size of the group desired and what
5301 register class contains all the groups needed by this insn. */
5303 for (j = 0; j < n_reloads; j++)
5305 reload_order[j] = j;
5306 reload_spill_index[j] = -1;
5308 if (rld[j].nregs > 1)
5310 max_group_size = MAX (rld[j].nregs, max_group_size);
5312 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5315 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5319 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5321 /* If -O, try first with inheritance, then turning it off.
5322 If not -O, don't do inheritance.
5323 Using inheritance when not optimizing leads to paradoxes
5324 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5325 because one side of the comparison might be inherited. */
5327 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5329 choose_reload_regs_init (chain, save_reload_reg_rtx);
5331 /* Process the reloads in order of preference just found.
5332 Beyond this point, subregs can be found in reload_reg_rtx.
5334 This used to look for an existing reloaded home for all of the
5335 reloads, and only then perform any new reloads. But that could lose
5336 if the reloads were done out of reg-class order because a later
5337 reload with a looser constraint might have an old home in a register
5338 needed by an earlier reload with a tighter constraint.
5340 To solve this, we make two passes over the reloads, in the order
5341 described above. In the first pass we try to inherit a reload
5342 from a previous insn. If there is a later reload that needs a
5343 class that is a proper subset of the class being processed, we must
5344 also allocate a spill register during the first pass.
5346 Then make a second pass over the reloads to allocate any reloads
5347 that haven't been given registers yet. */
5349 for (j = 0; j < n_reloads; j++)
5351 register int r = reload_order[j];
5352 rtx search_equiv = NULL_RTX;
5354 /* Ignore reloads that got marked inoperative. */
5355 if (rld[r].out == 0 && rld[r].in == 0
5356 && ! rld[r].secondary_p)
5359 /* If find_reloads chose to use reload_in or reload_out as a reload
5360 register, we don't need to chose one. Otherwise, try even if it
5361 found one since we might save an insn if we find the value lying
5363 Try also when reload_in is a pseudo without a hard reg. */
5364 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5365 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5366 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5367 && GET_CODE (rld[r].in) != MEM
5368 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5371 #if 0 /* No longer needed for correct operation.
5372 It might give better code, or might not; worth an experiment? */
5373 /* If this is an optional reload, we can't inherit from earlier insns
5374 until we are sure that any non-optional reloads have been allocated.
5375 The following code takes advantage of the fact that optional reloads
5376 are at the end of reload_order. */
5377 if (rld[r].optional != 0)
5378 for (i = 0; i < j; i++)
5379 if ((rld[reload_order[i]].out != 0
5380 || rld[reload_order[i]].in != 0
5381 || rld[reload_order[i]].secondary_p)
5382 && ! rld[reload_order[i]].optional
5383 && rld[reload_order[i]].reg_rtx == 0)
5384 allocate_reload_reg (chain, reload_order[i], 0);
5387 /* First see if this pseudo is already available as reloaded
5388 for a previous insn. We cannot try to inherit for reloads
5389 that are smaller than the maximum number of registers needed
5390 for groups unless the register we would allocate cannot be used
5393 We could check here to see if this is a secondary reload for
5394 an object that is already in a register of the desired class.
5395 This would avoid the need for the secondary reload register.
5396 But this is complex because we can't easily determine what
5397 objects might want to be loaded via this reload. So let a
5398 register be allocated here. In `emit_reload_insns' we suppress
5399 one of the loads in the case described above. */
5404 register int regno = -1;
5405 enum machine_mode mode = VOIDmode;
5409 else if (GET_CODE (rld[r].in) == REG)
5411 regno = REGNO (rld[r].in);
5412 mode = GET_MODE (rld[r].in);
5414 else if (GET_CODE (rld[r].in_reg) == REG)
5416 regno = REGNO (rld[r].in_reg);
5417 mode = GET_MODE (rld[r].in_reg);
5419 else if (GET_CODE (rld[r].in_reg) == SUBREG
5420 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5422 byte = SUBREG_BYTE (rld[r].in_reg);
5423 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5424 if (regno < FIRST_PSEUDO_REGISTER)
5425 regno = subreg_regno (rld[r].in_reg);
5426 mode = GET_MODE (rld[r].in_reg);
5429 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5430 || GET_CODE (rld[r].in_reg) == PRE_DEC
5431 || GET_CODE (rld[r].in_reg) == POST_INC
5432 || GET_CODE (rld[r].in_reg) == POST_DEC)
5433 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5435 regno = REGNO (XEXP (rld[r].in_reg, 0));
5436 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5437 rld[r].out = rld[r].in;
5441 /* This won't work, since REGNO can be a pseudo reg number.
5442 Also, it takes much more hair to keep track of all the things
5443 that can invalidate an inherited reload of part of a pseudoreg. */
5444 else if (GET_CODE (rld[r].in) == SUBREG
5445 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5446 regno = subreg_regno (rld[r].in);
5449 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5451 enum reg_class class = rld[r].class, last_class;
5452 rtx last_reg = reg_last_reload_reg[regno];
5453 enum machine_mode need_mode;
5455 i = REGNO (last_reg);
5456 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5457 last_class = REGNO_REG_CLASS (i);
5463 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5464 GET_MODE_CLASS (mode));
5467 #ifdef CLASS_CANNOT_CHANGE_MODE
5469 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5470 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5472 : (GET_MODE_SIZE (GET_MODE (last_reg))
5473 >= GET_MODE_SIZE (need_mode)))
5475 (GET_MODE_SIZE (GET_MODE (last_reg))
5476 >= GET_MODE_SIZE (need_mode))
5478 && reg_reloaded_contents[i] == regno
5479 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5480 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5481 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5482 /* Even if we can't use this register as a reload
5483 register, we might use it for reload_override_in,
5484 if copying it to the desired class is cheap
5486 || ((REGISTER_MOVE_COST (mode, last_class, class)
5487 < MEMORY_MOVE_COST (mode, class, 1))
5488 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5489 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5493 #ifdef SECONDARY_MEMORY_NEEDED
5494 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5499 && (rld[r].nregs == max_group_size
5500 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5502 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5503 rld[r].when_needed, rld[r].in,
5506 /* If a group is needed, verify that all the subsequent
5507 registers still have their values intact. */
5508 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5511 for (k = 1; k < nr; k++)
5512 if (reg_reloaded_contents[i + k] != regno
5513 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5520 last_reg = (GET_MODE (last_reg) == mode
5521 ? last_reg : gen_rtx_REG (mode, i));
5523 /* We found a register that contains the
5524 value we need. If this register is the
5525 same as an `earlyclobber' operand of the
5526 current insn, just mark it as a place to
5527 reload from since we can't use it as the
5528 reload register itself. */
5530 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5531 if (reg_overlap_mentioned_for_reload_p
5532 (reg_last_reload_reg[regno],
5533 reload_earlyclobbers[i1]))
5536 if (i1 != n_earlyclobbers
5537 || ! (free_for_value_p (i, rld[r].mode,
5539 rld[r].when_needed, rld[r].in,
5541 /* Don't use it if we'd clobber a pseudo reg. */
5542 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5544 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5545 /* Don't clobber the frame pointer. */
5546 || (i == HARD_FRAME_POINTER_REGNUM
5548 /* Don't really use the inherited spill reg
5549 if we need it wider than we've got it. */
5550 || (GET_MODE_SIZE (rld[r].mode)
5551 > GET_MODE_SIZE (mode))
5552 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5555 /* If find_reloads chose reload_out as reload
5556 register, stay with it - that leaves the
5557 inherited register for subsequent reloads. */
5558 || (rld[r].out && rld[r].reg_rtx
5559 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5561 if (! rld[r].optional)
5563 reload_override_in[r] = last_reg;
5564 reload_inheritance_insn[r]
5565 = reg_reloaded_insn[i];
5571 /* We can use this as a reload reg. */
5572 /* Mark the register as in use for this part of
5574 mark_reload_reg_in_use (i,
5578 rld[r].reg_rtx = last_reg;
5579 reload_inherited[r] = 1;
5580 reload_inheritance_insn[r]
5581 = reg_reloaded_insn[i];
5582 reload_spill_index[r] = i;
5583 for (k = 0; k < nr; k++)
5584 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5592 /* Here's another way to see if the value is already lying around. */
5595 && ! reload_inherited[r]
5597 && (CONSTANT_P (rld[r].in)
5598 || GET_CODE (rld[r].in) == PLUS
5599 || GET_CODE (rld[r].in) == REG
5600 || GET_CODE (rld[r].in) == MEM)
5601 && (rld[r].nregs == max_group_size
5602 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5603 search_equiv = rld[r].in;
5604 /* If this is an output reload from a simple move insn, look
5605 if an equivalence for the input is available. */
5606 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5608 rtx set = single_set (insn);
5611 && rtx_equal_p (rld[r].out, SET_DEST (set))
5612 && CONSTANT_P (SET_SRC (set)))
5613 search_equiv = SET_SRC (set);
5619 = find_equiv_reg (search_equiv, insn, rld[r].class,
5620 -1, NULL_PTR, 0, rld[r].mode);
5625 if (GET_CODE (equiv) == REG)
5626 regno = REGNO (equiv);
5627 else if (GET_CODE (equiv) == SUBREG)
5629 /* This must be a SUBREG of a hard register.
5630 Make a new REG since this might be used in an
5631 address and not all machines support SUBREGs
5633 regno = subreg_regno (equiv);
5634 equiv = gen_rtx_REG (rld[r].mode, regno);
5640 /* If we found a spill reg, reject it unless it is free
5641 and of the desired class. */
5643 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5644 && ! free_for_value_p (regno, rld[r].mode,
5645 rld[r].opnum, rld[r].when_needed,
5646 rld[r].in, rld[r].out, r, 1))
5647 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5651 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5654 /* We found a register that contains the value we need.
5655 If this register is the same as an `earlyclobber' operand
5656 of the current insn, just mark it as a place to reload from
5657 since we can't use it as the reload register itself. */
5660 for (i = 0; i < n_earlyclobbers; i++)
5661 if (reg_overlap_mentioned_for_reload_p (equiv,
5662 reload_earlyclobbers[i]))
5664 if (! rld[r].optional)
5665 reload_override_in[r] = equiv;
5670 /* If the equiv register we have found is explicitly clobbered
5671 in the current insn, it depends on the reload type if we
5672 can use it, use it for reload_override_in, or not at all.
5673 In particular, we then can't use EQUIV for a
5674 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5678 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5679 switch (rld[r].when_needed)
5681 case RELOAD_FOR_OTHER_ADDRESS:
5682 case RELOAD_FOR_INPADDR_ADDRESS:
5683 case RELOAD_FOR_INPUT_ADDRESS:
5684 case RELOAD_FOR_OPADDR_ADDR:
5687 case RELOAD_FOR_INPUT:
5688 case RELOAD_FOR_OPERAND_ADDRESS:
5689 if (! rld[r].optional)
5690 reload_override_in[r] = equiv;
5696 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5697 switch (rld[r].when_needed)
5699 case RELOAD_FOR_OTHER_ADDRESS:
5700 case RELOAD_FOR_INPADDR_ADDRESS:
5701 case RELOAD_FOR_INPUT_ADDRESS:
5702 case RELOAD_FOR_OPADDR_ADDR:
5703 case RELOAD_FOR_OPERAND_ADDRESS:
5704 case RELOAD_FOR_INPUT:
5707 if (! rld[r].optional)
5708 reload_override_in[r] = equiv;
5716 /* If we found an equivalent reg, say no code need be generated
5717 to load it, and use it as our reload reg. */
5718 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5720 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5722 rld[r].reg_rtx = equiv;
5723 reload_inherited[r] = 1;
5725 /* If reg_reloaded_valid is not set for this register,
5726 there might be a stale spill_reg_store lying around.
5727 We must clear it, since otherwise emit_reload_insns
5728 might delete the store. */
5729 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5730 spill_reg_store[regno] = NULL_RTX;
5731 /* If any of the hard registers in EQUIV are spill
5732 registers, mark them as in use for this insn. */
5733 for (k = 0; k < nr; k++)
5735 i = spill_reg_order[regno + k];
5738 mark_reload_reg_in_use (regno, rld[r].opnum,
5741 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5748 /* If we found a register to use already, or if this is an optional
5749 reload, we are done. */
5750 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5754 /* No longer needed for correct operation. Might or might
5755 not give better code on the average. Want to experiment? */
5757 /* See if there is a later reload that has a class different from our
5758 class that intersects our class or that requires less register
5759 than our reload. If so, we must allocate a register to this
5760 reload now, since that reload might inherit a previous reload
5761 and take the only available register in our class. Don't do this
5762 for optional reloads since they will force all previous reloads
5763 to be allocated. Also don't do this for reloads that have been
5766 for (i = j + 1; i < n_reloads; i++)
5768 int s = reload_order[i];
5770 if ((rld[s].in == 0 && rld[s].out == 0
5771 && ! rld[s].secondary_p)
5775 if ((rld[s].class != rld[r].class
5776 && reg_classes_intersect_p (rld[r].class,
5778 || rld[s].nregs < rld[r].nregs)
5785 allocate_reload_reg (chain, r, j == n_reloads - 1);
5789 /* Now allocate reload registers for anything non-optional that
5790 didn't get one yet. */
5791 for (j = 0; j < n_reloads; j++)
5793 register int r = reload_order[j];
5795 /* Ignore reloads that got marked inoperative. */
5796 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5799 /* Skip reloads that already have a register allocated or are
5801 if (rld[r].reg_rtx != 0 || rld[r].optional)
5804 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5808 /* If that loop got all the way, we have won. */
5815 /* Loop around and try without any inheritance. */
5820 /* First undo everything done by the failed attempt
5821 to allocate with inheritance. */
5822 choose_reload_regs_init (chain, save_reload_reg_rtx);
5824 /* Some sanity tests to verify that the reloads found in the first
5825 pass are identical to the ones we have now. */
5826 if (chain->n_reloads != n_reloads)
5829 for (i = 0; i < n_reloads; i++)
5831 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5833 if (chain->rld[i].when_needed != rld[i].when_needed)
5835 for (j = 0; j < n_spills; j++)
5836 if (spill_regs[j] == chain->rld[i].regno)
5837 if (! set_reload_reg (j, i))
5838 failed_reload (chain->insn, i);
5842 /* If we thought we could inherit a reload, because it seemed that
5843 nothing else wanted the same reload register earlier in the insn,
5844 verify that assumption, now that all reloads have been assigned.
5845 Likewise for reloads where reload_override_in has been set. */
5847 /* If doing expensive optimizations, do one preliminary pass that doesn't
5848 cancel any inheritance, but removes reloads that have been needed only
5849 for reloads that we know can be inherited. */
5850 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5852 for (j = 0; j < n_reloads; j++)
5854 register int r = reload_order[j];
5856 if (reload_inherited[r] && rld[r].reg_rtx)
5857 check_reg = rld[r].reg_rtx;
5858 else if (reload_override_in[r]
5859 && (GET_CODE (reload_override_in[r]) == REG
5860 || GET_CODE (reload_override_in[r]) == SUBREG))
5861 check_reg = reload_override_in[r];
5864 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5865 rld[r].opnum, rld[r].when_needed, rld[r].in,
5866 (reload_inherited[r]
5867 ? rld[r].out : const0_rtx),
5872 reload_inherited[r] = 0;
5873 reload_override_in[r] = 0;
5875 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5876 reload_override_in, then we do not need its related
5877 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5878 likewise for other reload types.
5879 We handle this by removing a reload when its only replacement
5880 is mentioned in reload_in of the reload we are going to inherit.
5881 A special case are auto_inc expressions; even if the input is
5882 inherited, we still need the address for the output. We can
5883 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5884 If we suceeded removing some reload and we are doing a preliminary
5885 pass just to remove such reloads, make another pass, since the
5886 removal of one reload might allow us to inherit another one. */
5888 && rld[r].out != rld[r].in
5889 && remove_address_replacements (rld[r].in) && pass)
5894 /* Now that reload_override_in is known valid,
5895 actually override reload_in. */
5896 for (j = 0; j < n_reloads; j++)
5897 if (reload_override_in[j])
5898 rld[j].in = reload_override_in[j];
5900 /* If this reload won't be done because it has been cancelled or is
5901 optional and not inherited, clear reload_reg_rtx so other
5902 routines (such as subst_reloads) don't get confused. */
5903 for (j = 0; j < n_reloads; j++)
5904 if (rld[j].reg_rtx != 0
5905 && ((rld[j].optional && ! reload_inherited[j])
5906 || (rld[j].in == 0 && rld[j].out == 0
5907 && ! rld[j].secondary_p)))
5909 int regno = true_regnum (rld[j].reg_rtx);
5911 if (spill_reg_order[regno] >= 0)
5912 clear_reload_reg_in_use (regno, rld[j].opnum,
5913 rld[j].when_needed, rld[j].mode);
5915 reload_spill_index[j] = -1;
5918 /* Record which pseudos and which spill regs have output reloads. */
5919 for (j = 0; j < n_reloads; j++)
5921 register int r = reload_order[j];
5923 i = reload_spill_index[r];
5925 /* I is nonneg if this reload uses a register.
5926 If rld[r].reg_rtx is 0, this is an optional reload
5927 that we opted to ignore. */
5928 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5929 && rld[r].reg_rtx != 0)
5931 register int nregno = REGNO (rld[r].out_reg);
5934 if (nregno < FIRST_PSEUDO_REGISTER)
5935 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5938 reg_has_output_reload[nregno + nr] = 1;
5942 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5944 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5947 if (rld[r].when_needed != RELOAD_OTHER
5948 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5949 && rld[r].when_needed != RELOAD_FOR_INSN)
5955 /* Deallocate the reload register for reload R. This is called from
5956 remove_address_replacements. */
5959 deallocate_reload_reg (r)
5964 if (! rld[r].reg_rtx)
5966 regno = true_regnum (rld[r].reg_rtx);
5968 if (spill_reg_order[regno] >= 0)
5969 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5971 reload_spill_index[r] = -1;
5974 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5975 reloads of the same item for fear that we might not have enough reload
5976 registers. However, normally they will get the same reload register
5977 and hence actually need not be loaded twice.
5979 Here we check for the most common case of this phenomenon: when we have
5980 a number of reloads for the same object, each of which were allocated
5981 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5982 reload, and is not modified in the insn itself. If we find such,
5983 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5984 This will not increase the number of spill registers needed and will
5985 prevent redundant code. */
5988 merge_assigned_reloads (insn)
5993 /* Scan all the reloads looking for ones that only load values and
5994 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5995 assigned and not modified by INSN. */
5997 for (i = 0; i < n_reloads; i++)
5999 int conflicting_input = 0;
6000 int max_input_address_opnum = -1;
6001 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6003 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6004 || rld[i].out != 0 || rld[i].reg_rtx == 0
6005 || reg_set_p (rld[i].reg_rtx, insn))
6008 /* Look at all other reloads. Ensure that the only use of this
6009 reload_reg_rtx is in a reload that just loads the same value
6010 as we do. Note that any secondary reloads must be of the identical
6011 class since the values, modes, and result registers are the
6012 same, so we need not do anything with any secondary reloads. */
6014 for (j = 0; j < n_reloads; j++)
6016 if (i == j || rld[j].reg_rtx == 0
6017 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6021 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6022 && rld[j].opnum > max_input_address_opnum)
6023 max_input_address_opnum = rld[j].opnum;
6025 /* If the reload regs aren't exactly the same (e.g, different modes)
6026 or if the values are different, we can't merge this reload.
6027 But if it is an input reload, we might still merge
6028 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6030 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6031 || rld[j].out != 0 || rld[j].in == 0
6032 || ! rtx_equal_p (rld[i].in, rld[j].in))
6034 if (rld[j].when_needed != RELOAD_FOR_INPUT
6035 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6036 || rld[i].opnum > rld[j].opnum)
6037 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6039 conflicting_input = 1;
6040 if (min_conflicting_input_opnum > rld[j].opnum)
6041 min_conflicting_input_opnum = rld[j].opnum;
6045 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6046 we, in fact, found any matching reloads. */
6049 && max_input_address_opnum <= min_conflicting_input_opnum)
6051 for (j = 0; j < n_reloads; j++)
6052 if (i != j && rld[j].reg_rtx != 0
6053 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6054 && (! conflicting_input
6055 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6056 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6058 rld[i].when_needed = RELOAD_OTHER;
6060 reload_spill_index[j] = -1;
6061 transfer_replacements (i, j);
6064 /* If this is now RELOAD_OTHER, look for any reloads that load
6065 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6066 if they were for inputs, RELOAD_OTHER for outputs. Note that
6067 this test is equivalent to looking for reloads for this operand
6070 if (rld[i].when_needed == RELOAD_OTHER)
6071 for (j = 0; j < n_reloads; j++)
6073 && rld[i].when_needed != RELOAD_OTHER
6074 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6077 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6078 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6079 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6084 /* These arrays are filled by emit_reload_insns and its subroutines. */
6085 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6086 static rtx other_input_address_reload_insns = 0;
6087 static rtx other_input_reload_insns = 0;
6088 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6091 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6092 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6093 static rtx operand_reload_insns = 0;
6094 static rtx other_operand_reload_insns = 0;
6095 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6097 /* Values to be put in spill_reg_store are put here first. */
6098 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6099 static HARD_REG_SET reg_reloaded_died;
6101 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6102 has the number J. OLD contains the value to be used as input. */
6105 emit_input_reload_insns (chain, rl, old, j)
6106 struct insn_chain *chain;
6111 rtx insn = chain->insn;
6112 register rtx reloadreg = rl->reg_rtx;
6113 rtx oldequiv_reg = 0;
6116 enum machine_mode mode;
6119 /* Determine the mode to reload in.
6120 This is very tricky because we have three to choose from.
6121 There is the mode the insn operand wants (rl->inmode).
6122 There is the mode of the reload register RELOADREG.
6123 There is the intrinsic mode of the operand, which we could find
6124 by stripping some SUBREGs.
6125 It turns out that RELOADREG's mode is irrelevant:
6126 we can change that arbitrarily.
6128 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6129 then the reload reg may not support QImode moves, so use SImode.
6130 If foo is in memory due to spilling a pseudo reg, this is safe,
6131 because the QImode value is in the least significant part of a
6132 slot big enough for a SImode. If foo is some other sort of
6133 memory reference, then it is impossible to reload this case,
6134 so previous passes had better make sure this never happens.
6136 Then consider a one-word union which has SImode and one of its
6137 members is a float, being fetched as (SUBREG:SF union:SI).
6138 We must fetch that as SFmode because we could be loading into
6139 a float-only register. In this case OLD's mode is correct.
6141 Consider an immediate integer: it has VOIDmode. Here we need
6142 to get a mode from something else.
6144 In some cases, there is a fourth mode, the operand's
6145 containing mode. If the insn specifies a containing mode for
6146 this operand, it overrides all others.
6148 I am not sure whether the algorithm here is always right,
6149 but it does the right things in those cases. */
6151 mode = GET_MODE (old);
6152 if (mode == VOIDmode)
6155 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6156 /* If we need a secondary register for this operation, see if
6157 the value is already in a register in that class. Don't
6158 do this if the secondary register will be used as a scratch
6161 if (rl->secondary_in_reload >= 0
6162 && rl->secondary_in_icode == CODE_FOR_nothing
6165 = find_equiv_reg (old, insn,
6166 rld[rl->secondary_in_reload].class,
6167 -1, NULL_PTR, 0, mode);
6170 /* If reloading from memory, see if there is a register
6171 that already holds the same value. If so, reload from there.
6172 We can pass 0 as the reload_reg_p argument because
6173 any other reload has either already been emitted,
6174 in which case find_equiv_reg will see the reload-insn,
6175 or has yet to be emitted, in which case it doesn't matter
6176 because we will use this equiv reg right away. */
6178 if (oldequiv == 0 && optimize
6179 && (GET_CODE (old) == MEM
6180 || (GET_CODE (old) == REG
6181 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6182 && reg_renumber[REGNO (old)] < 0)))
6183 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6184 -1, NULL_PTR, 0, mode);
6188 unsigned int regno = true_regnum (oldequiv);
6190 /* Don't use OLDEQUIV if any other reload changes it at an
6191 earlier stage of this insn or at this stage. */
6192 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6193 rl->in, const0_rtx, j, 0))
6196 /* If it is no cheaper to copy from OLDEQUIV into the
6197 reload register than it would be to move from memory,
6198 don't use it. Likewise, if we need a secondary register
6202 && ((REGNO_REG_CLASS (regno) != rl->class
6203 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6205 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6206 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6207 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6211 #ifdef SECONDARY_MEMORY_NEEDED
6212 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6220 /* delete_output_reload is only invoked properly if old contains
6221 the original pseudo register. Since this is replaced with a
6222 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6223 find the pseudo in RELOAD_IN_REG. */
6225 && reload_override_in[j]
6226 && GET_CODE (rl->in_reg) == REG)
6233 else if (GET_CODE (oldequiv) == REG)
6234 oldequiv_reg = oldequiv;
6235 else if (GET_CODE (oldequiv) == SUBREG)
6236 oldequiv_reg = SUBREG_REG (oldequiv);
6238 /* If we are reloading from a register that was recently stored in
6239 with an output-reload, see if we can prove there was
6240 actually no need to store the old value in it. */
6242 if (optimize && GET_CODE (oldequiv) == REG
6243 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6244 && spill_reg_store[REGNO (oldequiv)]
6245 && GET_CODE (old) == REG
6246 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6247 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6249 delete_output_reload (insn, j, REGNO (oldequiv));
6251 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6252 then load RELOADREG from OLDEQUIV. Note that we cannot use
6253 gen_lowpart_common since it can do the wrong thing when
6254 RELOADREG has a multi-word mode. Note that RELOADREG
6255 must always be a REG here. */
6257 if (GET_MODE (reloadreg) != mode)
6258 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6259 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6260 oldequiv = SUBREG_REG (oldequiv);
6261 if (GET_MODE (oldequiv) != VOIDmode
6262 && mode != GET_MODE (oldequiv))
6263 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6265 /* Switch to the right place to emit the reload insns. */
6266 switch (rl->when_needed)
6269 where = &other_input_reload_insns;
6271 case RELOAD_FOR_INPUT:
6272 where = &input_reload_insns[rl->opnum];
6274 case RELOAD_FOR_INPUT_ADDRESS:
6275 where = &input_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_INPADDR_ADDRESS:
6278 where = &inpaddr_address_reload_insns[rl->opnum];
6280 case RELOAD_FOR_OUTPUT_ADDRESS:
6281 where = &output_address_reload_insns[rl->opnum];
6283 case RELOAD_FOR_OUTADDR_ADDRESS:
6284 where = &outaddr_address_reload_insns[rl->opnum];
6286 case RELOAD_FOR_OPERAND_ADDRESS:
6287 where = &operand_reload_insns;
6289 case RELOAD_FOR_OPADDR_ADDR:
6290 where = &other_operand_reload_insns;
6292 case RELOAD_FOR_OTHER_ADDRESS:
6293 where = &other_input_address_reload_insns;
6299 push_to_sequence (*where);
6301 /* Auto-increment addresses must be reloaded in a special way. */
6302 if (rl->out && ! rl->out_reg)
6304 /* We are not going to bother supporting the case where a
6305 incremented register can't be copied directly from
6306 OLDEQUIV since this seems highly unlikely. */
6307 if (rl->secondary_in_reload >= 0)
6310 if (reload_inherited[j])
6311 oldequiv = reloadreg;
6313 old = XEXP (rl->in_reg, 0);
6315 if (optimize && GET_CODE (oldequiv) == REG
6316 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6317 && spill_reg_store[REGNO (oldequiv)]
6318 && GET_CODE (old) == REG
6319 && (dead_or_set_p (insn,
6320 spill_reg_stored_to[REGNO (oldequiv)])
6321 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6323 delete_output_reload (insn, j, REGNO (oldequiv));
6325 /* Prevent normal processing of this reload. */
6327 /* Output a special code sequence for this case. */
6328 new_spill_reg_store[REGNO (reloadreg)]
6329 = inc_for_reload (reloadreg, oldequiv, rl->out,
6333 /* If we are reloading a pseudo-register that was set by the previous
6334 insn, see if we can get rid of that pseudo-register entirely
6335 by redirecting the previous insn into our reload register. */
6337 else if (optimize && GET_CODE (old) == REG
6338 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6339 && dead_or_set_p (insn, old)
6340 /* This is unsafe if some other reload
6341 uses the same reg first. */
6342 && ! conflicts_with_override (reloadreg)
6343 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6344 rl->when_needed, old, rl->out, j, 0))
6346 rtx temp = PREV_INSN (insn);
6347 while (temp && GET_CODE (temp) == NOTE)
6348 temp = PREV_INSN (temp);
6350 && GET_CODE (temp) == INSN
6351 && GET_CODE (PATTERN (temp)) == SET
6352 && SET_DEST (PATTERN (temp)) == old
6353 /* Make sure we can access insn_operand_constraint. */
6354 && asm_noperands (PATTERN (temp)) < 0
6355 /* This is unsafe if prev insn rejects our reload reg. */
6356 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6358 /* This is unsafe if operand occurs more than once in current
6359 insn. Perhaps some occurrences aren't reloaded. */
6360 && count_occurrences (PATTERN (insn), old, 0) == 1
6361 /* Don't risk splitting a matching pair of operands. */
6362 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6364 /* Store into the reload register instead of the pseudo. */
6365 SET_DEST (PATTERN (temp)) = reloadreg;
6367 /* If the previous insn is an output reload, the source is
6368 a reload register, and its spill_reg_store entry will
6369 contain the previous destination. This is now
6371 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6372 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6374 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6375 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6378 /* If these are the only uses of the pseudo reg,
6379 pretend for GDB it lives in the reload reg we used. */
6380 if (REG_N_DEATHS (REGNO (old)) == 1
6381 && REG_N_SETS (REGNO (old)) == 1)
6383 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6384 alter_reg (REGNO (old), -1);
6390 /* We can't do that, so output an insn to load RELOADREG. */
6392 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6393 /* If we have a secondary reload, pick up the secondary register
6394 and icode, if any. If OLDEQUIV and OLD are different or
6395 if this is an in-out reload, recompute whether or not we
6396 still need a secondary register and what the icode should
6397 be. If we still need a secondary register and the class or
6398 icode is different, go back to reloading from OLD if using
6399 OLDEQUIV means that we got the wrong type of register. We
6400 cannot have different class or icode due to an in-out reload
6401 because we don't make such reloads when both the input and
6402 output need secondary reload registers. */
6404 if (! special && rl->secondary_in_reload >= 0)
6406 rtx second_reload_reg = 0;
6407 int secondary_reload = rl->secondary_in_reload;
6408 rtx real_oldequiv = oldequiv;
6411 enum insn_code icode;
6413 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6414 and similarly for OLD.
6415 See comments in get_secondary_reload in reload.c. */
6416 /* If it is a pseudo that cannot be replaced with its
6417 equivalent MEM, we must fall back to reload_in, which
6418 will have all the necessary substitutions registered.
6419 Likewise for a pseudo that can't be replaced with its
6420 equivalent constant.
6422 Take extra care for subregs of such pseudos. Note that
6423 we cannot use reg_equiv_mem in this case because it is
6424 not in the right mode. */
6427 if (GET_CODE (tmp) == SUBREG)
6428 tmp = SUBREG_REG (tmp);
6429 if (GET_CODE (tmp) == REG
6430 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6431 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6432 || reg_equiv_constant[REGNO (tmp)] != 0))
6434 if (! reg_equiv_mem[REGNO (tmp)]
6435 || num_not_at_initial_offset
6436 || GET_CODE (oldequiv) == SUBREG)
6437 real_oldequiv = rl->in;
6439 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6443 if (GET_CODE (tmp) == SUBREG)
6444 tmp = SUBREG_REG (tmp);
6445 if (GET_CODE (tmp) == REG
6446 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6447 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6448 || reg_equiv_constant[REGNO (tmp)] != 0))
6450 if (! reg_equiv_mem[REGNO (tmp)]
6451 || num_not_at_initial_offset
6452 || GET_CODE (old) == SUBREG)
6455 real_old = reg_equiv_mem[REGNO (tmp)];
6458 second_reload_reg = rld[secondary_reload].reg_rtx;
6459 icode = rl->secondary_in_icode;
6461 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6462 || (rl->in != 0 && rl->out != 0))
6464 enum reg_class new_class
6465 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6466 mode, real_oldequiv);
6468 if (new_class == NO_REGS)
6469 second_reload_reg = 0;
6472 enum insn_code new_icode;
6473 enum machine_mode new_mode;
6475 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6476 REGNO (second_reload_reg)))
6477 oldequiv = old, real_oldequiv = real_old;
6480 new_icode = reload_in_optab[(int) mode];
6481 if (new_icode != CODE_FOR_nothing
6482 && ((insn_data[(int) new_icode].operand[0].predicate
6483 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6485 || (insn_data[(int) new_icode].operand[1].predicate
6486 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6487 (real_oldequiv, mode)))))
6488 new_icode = CODE_FOR_nothing;
6490 if (new_icode == CODE_FOR_nothing)
6493 new_mode = insn_data[(int) new_icode].operand[2].mode;
6495 if (GET_MODE (second_reload_reg) != new_mode)
6497 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6499 oldequiv = old, real_oldequiv = real_old;
6502 = gen_rtx_REG (new_mode,
6503 REGNO (second_reload_reg));
6509 /* If we still need a secondary reload register, check
6510 to see if it is being used as a scratch or intermediate
6511 register and generate code appropriately. If we need
6512 a scratch register, use REAL_OLDEQUIV since the form of
6513 the insn may depend on the actual address if it is
6516 if (second_reload_reg)
6518 if (icode != CODE_FOR_nothing)
6520 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6521 second_reload_reg));
6526 /* See if we need a scratch register to load the
6527 intermediate register (a tertiary reload). */
6528 enum insn_code tertiary_icode
6529 = rld[secondary_reload].secondary_in_icode;
6531 if (tertiary_icode != CODE_FOR_nothing)
6533 rtx third_reload_reg
6534 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6536 emit_insn ((GEN_FCN (tertiary_icode)
6537 (second_reload_reg, real_oldequiv,
6538 third_reload_reg)));
6541 gen_reload (second_reload_reg, real_oldequiv,
6545 oldequiv = second_reload_reg;
6551 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6553 rtx real_oldequiv = oldequiv;
6555 if ((GET_CODE (oldequiv) == REG
6556 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6557 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6558 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6559 || (GET_CODE (oldequiv) == SUBREG
6560 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6561 && (REGNO (SUBREG_REG (oldequiv))
6562 >= FIRST_PSEUDO_REGISTER)
6563 && ((reg_equiv_memory_loc
6564 [REGNO (SUBREG_REG (oldequiv))] != 0)
6565 || (reg_equiv_constant
6566 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6567 || (CONSTANT_P (oldequiv)
6568 && PREFERRED_RELOAD_CLASS (oldequiv,
6569 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6570 real_oldequiv = rl->in;
6571 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6575 /* End this sequence. */
6576 *where = get_insns ();
6579 /* Update reload_override_in so that delete_address_reloads_1
6580 can see the actual register usage. */
6582 reload_override_in[j] = oldequiv;
6585 /* Generate insns to for the output reload RL, which is for the insn described
6586 by CHAIN and has the number J. */
6588 emit_output_reload_insns (chain, rl, j)
6589 struct insn_chain *chain;
6593 rtx reloadreg = rl->reg_rtx;
6594 rtx insn = chain->insn;
6597 enum machine_mode mode = GET_MODE (old);
6600 if (rl->when_needed == RELOAD_OTHER)
6603 push_to_sequence (output_reload_insns[rl->opnum]);
6605 /* Determine the mode to reload in.
6606 See comments above (for input reloading). */
6608 if (mode == VOIDmode)
6610 /* VOIDmode should never happen for an output. */
6611 if (asm_noperands (PATTERN (insn)) < 0)
6612 /* It's the compiler's fault. */
6613 fatal_insn ("VOIDmode on an output", insn);
6614 error_for_asm (insn, "output operand is constant in `asm'");
6615 /* Prevent crash--use something we know is valid. */
6617 old = gen_rtx_REG (mode, REGNO (reloadreg));
6620 if (GET_MODE (reloadreg) != mode)
6621 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6623 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6625 /* If we need two reload regs, set RELOADREG to the intermediate
6626 one, since it will be stored into OLD. We might need a secondary
6627 register only for an input reload, so check again here. */
6629 if (rl->secondary_out_reload >= 0)
6633 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6634 && reg_equiv_mem[REGNO (old)] != 0)
6635 real_old = reg_equiv_mem[REGNO (old)];
6637 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6641 rtx second_reloadreg = reloadreg;
6642 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6644 /* See if RELOADREG is to be used as a scratch register
6645 or as an intermediate register. */
6646 if (rl->secondary_out_icode != CODE_FOR_nothing)
6648 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6649 (real_old, second_reloadreg, reloadreg)));
6654 /* See if we need both a scratch and intermediate reload
6657 int secondary_reload = rl->secondary_out_reload;
6658 enum insn_code tertiary_icode
6659 = rld[secondary_reload].secondary_out_icode;
6661 if (GET_MODE (reloadreg) != mode)
6662 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6664 if (tertiary_icode != CODE_FOR_nothing)
6667 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6670 /* Copy primary reload reg to secondary reload reg.
6671 (Note that these have been swapped above, then
6672 secondary reload reg to OLD using our insn.) */
6674 /* If REAL_OLD is a paradoxical SUBREG, remove it
6675 and try to put the opposite SUBREG on
6677 if (GET_CODE (real_old) == SUBREG
6678 && (GET_MODE_SIZE (GET_MODE (real_old))
6679 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6680 && 0 != (tem = gen_lowpart_common
6681 (GET_MODE (SUBREG_REG (real_old)),
6683 real_old = SUBREG_REG (real_old), reloadreg = tem;
6685 gen_reload (reloadreg, second_reloadreg,
6686 rl->opnum, rl->when_needed);
6687 emit_insn ((GEN_FCN (tertiary_icode)
6688 (real_old, reloadreg, third_reloadreg)));
6693 /* Copy between the reload regs here and then to
6696 gen_reload (reloadreg, second_reloadreg,
6697 rl->opnum, rl->when_needed);
6703 /* Output the last reload insn. */
6708 /* Don't output the last reload if OLD is not the dest of
6709 INSN and is in the src and is clobbered by INSN. */
6710 if (! flag_expensive_optimizations
6711 || GET_CODE (old) != REG
6712 || !(set = single_set (insn))
6713 || rtx_equal_p (old, SET_DEST (set))
6714 || !reg_mentioned_p (old, SET_SRC (set))
6715 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6716 gen_reload (old, reloadreg, rl->opnum,
6720 /* Look at all insns we emitted, just to be safe. */
6721 for (p = get_insns (); p; p = NEXT_INSN (p))
6724 rtx pat = PATTERN (p);
6726 /* If this output reload doesn't come from a spill reg,
6727 clear any memory of reloaded copies of the pseudo reg.
6728 If this output reload comes from a spill reg,
6729 reg_has_output_reload will make this do nothing. */
6730 note_stores (pat, forget_old_reloads_1, NULL);
6732 if (reg_mentioned_p (rl->reg_rtx, pat))
6734 rtx set = single_set (insn);
6735 if (reload_spill_index[j] < 0
6737 && SET_SRC (set) == rl->reg_rtx)
6739 int src = REGNO (SET_SRC (set));
6741 reload_spill_index[j] = src;
6742 SET_HARD_REG_BIT (reg_is_output_reload, src);
6743 if (find_regno_note (insn, REG_DEAD, src))
6744 SET_HARD_REG_BIT (reg_reloaded_died, src);
6746 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6748 int s = rl->secondary_out_reload;
6749 set = single_set (p);
6750 /* If this reload copies only to the secondary reload
6751 register, the secondary reload does the actual
6753 if (s >= 0 && set == NULL_RTX)
6754 /* We can't tell what function the secondary reload
6755 has and where the actual store to the pseudo is
6756 made; leave new_spill_reg_store alone. */
6759 && SET_SRC (set) == rl->reg_rtx
6760 && SET_DEST (set) == rld[s].reg_rtx)
6762 /* Usually the next instruction will be the
6763 secondary reload insn; if we can confirm
6764 that it is, setting new_spill_reg_store to
6765 that insn will allow an extra optimization. */
6766 rtx s_reg = rld[s].reg_rtx;
6767 rtx next = NEXT_INSN (p);
6768 rld[s].out = rl->out;
6769 rld[s].out_reg = rl->out_reg;
6770 set = single_set (next);
6771 if (set && SET_SRC (set) == s_reg
6772 && ! new_spill_reg_store[REGNO (s_reg)])
6774 SET_HARD_REG_BIT (reg_is_output_reload,
6776 new_spill_reg_store[REGNO (s_reg)] = next;
6780 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6785 if (rl->when_needed == RELOAD_OTHER)
6787 emit_insns (other_output_reload_insns[rl->opnum]);
6788 other_output_reload_insns[rl->opnum] = get_insns ();
6791 output_reload_insns[rl->opnum] = get_insns ();
6796 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6797 and has the number J. */
6799 do_input_reload (chain, rl, j)
6800 struct insn_chain *chain;
6804 int expect_occurrences = 1;
6805 rtx insn = chain->insn;
6806 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6807 ? rl->in_reg : rl->in);
6810 /* AUTO_INC reloads need to be handled even if inherited. We got an
6811 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6812 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6813 && ! rtx_equal_p (rl->reg_rtx, old)
6814 && rl->reg_rtx != 0)
6815 emit_input_reload_insns (chain, rld + j, old, j);
6817 /* When inheriting a wider reload, we have a MEM in rl->in,
6818 e.g. inheriting a SImode output reload for
6819 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6820 if (optimize && reload_inherited[j] && rl->in
6821 && GET_CODE (rl->in) == MEM
6822 && GET_CODE (rl->in_reg) == MEM
6823 && reload_spill_index[j] >= 0
6824 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6827 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6828 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6831 /* If we are reloading a register that was recently stored in with an
6832 output-reload, see if we can prove there was
6833 actually no need to store the old value in it. */
6836 && (reload_inherited[j] || reload_override_in[j])
6838 && GET_CODE (rl->reg_rtx) == REG
6839 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6841 /* There doesn't seem to be any reason to restrict this to pseudos
6842 and doing so loses in the case where we are copying from a
6843 register of the wrong class. */
6844 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6845 >= FIRST_PSEUDO_REGISTER)
6847 /* The insn might have already some references to stackslots
6848 replaced by MEMs, while reload_out_reg still names the
6850 && (dead_or_set_p (insn,
6851 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6852 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6854 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6857 /* Do output reloading for reload RL, which is for the insn described by
6858 CHAIN and has the number J.
6859 ??? At some point we need to support handling output reloads of
6860 JUMP_INSNs or insns that set cc0. */
6862 do_output_reload (chain, rl, j)
6863 struct insn_chain *chain;
6868 rtx insn = chain->insn;
6869 /* If this is an output reload that stores something that is
6870 not loaded in this same reload, see if we can eliminate a previous
6872 rtx pseudo = rl->out_reg;
6875 && GET_CODE (pseudo) == REG
6876 && ! rtx_equal_p (rl->in_reg, pseudo)
6877 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6878 && reg_last_reload_reg[REGNO (pseudo)])
6880 int pseudo_no = REGNO (pseudo);
6881 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6883 /* We don't need to test full validity of last_regno for
6884 inherit here; we only want to know if the store actually
6885 matches the pseudo. */
6886 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6887 && reg_reloaded_contents[last_regno] == pseudo_no
6888 && spill_reg_store[last_regno]
6889 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6890 delete_output_reload (insn, j, last_regno);
6895 || rl->reg_rtx == old
6896 || rl->reg_rtx == 0)
6899 /* An output operand that dies right away does need a reload,
6900 but need not be copied from it. Show the new location in the
6902 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6903 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6905 XEXP (note, 0) = rl->reg_rtx;
6908 /* Likewise for a SUBREG of an operand that dies. */
6909 else if (GET_CODE (old) == SUBREG
6910 && GET_CODE (SUBREG_REG (old)) == REG
6911 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6914 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6918 else if (GET_CODE (old) == SCRATCH)
6919 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6920 but we don't want to make an output reload. */
6923 /* If is a JUMP_INSN, we can't support output reloads yet. */
6924 if (GET_CODE (insn) == JUMP_INSN)
6927 emit_output_reload_insns (chain, rld + j, j);
6930 /* Output insns to reload values in and out of the chosen reload regs. */
6933 emit_reload_insns (chain)
6934 struct insn_chain *chain;
6936 rtx insn = chain->insn;
6939 rtx following_insn = NEXT_INSN (insn);
6940 rtx before_insn = PREV_INSN (insn);
6942 CLEAR_HARD_REG_SET (reg_reloaded_died);
6944 for (j = 0; j < reload_n_operands; j++)
6945 input_reload_insns[j] = input_address_reload_insns[j]
6946 = inpaddr_address_reload_insns[j]
6947 = output_reload_insns[j] = output_address_reload_insns[j]
6948 = outaddr_address_reload_insns[j]
6949 = other_output_reload_insns[j] = 0;
6950 other_input_address_reload_insns = 0;
6951 other_input_reload_insns = 0;
6952 operand_reload_insns = 0;
6953 other_operand_reload_insns = 0;
6955 /* Dump reloads into the dump file. */
6958 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6959 debug_reload_to_stream (rtl_dump_file);
6962 /* Now output the instructions to copy the data into and out of the
6963 reload registers. Do these in the order that the reloads were reported,
6964 since reloads of base and index registers precede reloads of operands
6965 and the operands may need the base and index registers reloaded. */
6967 for (j = 0; j < n_reloads; j++)
6970 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6971 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6973 do_input_reload (chain, rld + j, j);
6974 do_output_reload (chain, rld + j, j);
6977 /* Now write all the insns we made for reloads in the order expected by
6978 the allocation functions. Prior to the insn being reloaded, we write
6979 the following reloads:
6981 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6983 RELOAD_OTHER reloads.
6985 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6986 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6987 RELOAD_FOR_INPUT reload for the operand.
6989 RELOAD_FOR_OPADDR_ADDRS reloads.
6991 RELOAD_FOR_OPERAND_ADDRESS reloads.
6993 After the insn being reloaded, we write the following:
6995 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6996 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6997 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6998 reloads for the operand. The RELOAD_OTHER output reloads are
6999 output in descending order by reload number. */
7001 emit_insns_before (other_input_address_reload_insns, insn);
7002 emit_insns_before (other_input_reload_insns, insn);
7004 for (j = 0; j < reload_n_operands; j++)
7006 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7007 emit_insns_before (input_address_reload_insns[j], insn);
7008 emit_insns_before (input_reload_insns[j], insn);
7011 emit_insns_before (other_operand_reload_insns, insn);
7012 emit_insns_before (operand_reload_insns, insn);
7014 for (j = 0; j < reload_n_operands; j++)
7016 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7017 emit_insns_before (output_address_reload_insns[j], following_insn);
7018 emit_insns_before (output_reload_insns[j], following_insn);
7019 emit_insns_before (other_output_reload_insns[j], following_insn);
7022 /* Keep basic block info up to date. */
7025 if (BLOCK_HEAD (chain->block) == insn)
7026 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7027 if (BLOCK_END (chain->block) == insn)
7028 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7031 /* For all the spill regs newly reloaded in this instruction,
7032 record what they were reloaded from, so subsequent instructions
7033 can inherit the reloads.
7035 Update spill_reg_store for the reloads of this insn.
7036 Copy the elements that were updated in the loop above. */
7038 for (j = 0; j < n_reloads; j++)
7040 register int r = reload_order[j];
7041 register int i = reload_spill_index[r];
7043 /* If this is a non-inherited input reload from a pseudo, we must
7044 clear any memory of a previous store to the same pseudo. Only do
7045 something if there will not be an output reload for the pseudo
7047 if (rld[r].in_reg != 0
7048 && ! (reload_inherited[r] || reload_override_in[r]))
7050 rtx reg = rld[r].in_reg;
7052 if (GET_CODE (reg) == SUBREG)
7053 reg = SUBREG_REG (reg);
7055 if (GET_CODE (reg) == REG
7056 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7057 && ! reg_has_output_reload[REGNO (reg)])
7059 int nregno = REGNO (reg);
7061 if (reg_last_reload_reg[nregno])
7063 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7065 if (reg_reloaded_contents[last_regno] == nregno)
7066 spill_reg_store[last_regno] = 0;
7071 /* I is nonneg if this reload used a register.
7072 If rld[r].reg_rtx is 0, this is an optional reload
7073 that we opted to ignore. */
7075 if (i >= 0 && rld[r].reg_rtx != 0)
7077 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7079 int part_reaches_end = 0;
7080 int all_reaches_end = 1;
7082 /* For a multi register reload, we need to check if all or part
7083 of the value lives to the end. */
7084 for (k = 0; k < nr; k++)
7086 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7087 rld[r].when_needed))
7088 part_reaches_end = 1;
7090 all_reaches_end = 0;
7093 /* Ignore reloads that don't reach the end of the insn in
7095 if (all_reaches_end)
7097 /* First, clear out memory of what used to be in this spill reg.
7098 If consecutive registers are used, clear them all. */
7100 for (k = 0; k < nr; k++)
7101 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7103 /* Maybe the spill reg contains a copy of reload_out. */
7105 && (GET_CODE (rld[r].out) == REG
7109 || GET_CODE (rld[r].out_reg) == REG))
7111 rtx out = (GET_CODE (rld[r].out) == REG
7115 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7116 register int nregno = REGNO (out);
7117 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7118 : HARD_REGNO_NREGS (nregno,
7119 GET_MODE (rld[r].reg_rtx)));
7121 spill_reg_store[i] = new_spill_reg_store[i];
7122 spill_reg_stored_to[i] = out;
7123 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7125 /* If NREGNO is a hard register, it may occupy more than
7126 one register. If it does, say what is in the
7127 rest of the registers assuming that both registers
7128 agree on how many words the object takes. If not,
7129 invalidate the subsequent registers. */
7131 if (nregno < FIRST_PSEUDO_REGISTER)
7132 for (k = 1; k < nnr; k++)
7133 reg_last_reload_reg[nregno + k]
7135 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7136 REGNO (rld[r].reg_rtx) + k)
7139 /* Now do the inverse operation. */
7140 for (k = 0; k < nr; k++)
7142 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7143 reg_reloaded_contents[i + k]
7144 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7147 reg_reloaded_insn[i + k] = insn;
7148 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7152 /* Maybe the spill reg contains a copy of reload_in. Only do
7153 something if there will not be an output reload for
7154 the register being reloaded. */
7155 else if (rld[r].out_reg == 0
7157 && ((GET_CODE (rld[r].in) == REG
7158 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7159 && ! reg_has_output_reload[REGNO (rld[r].in)])
7160 || (GET_CODE (rld[r].in_reg) == REG
7161 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7162 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7164 register int nregno;
7167 if (GET_CODE (rld[r].in) == REG
7168 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7169 nregno = REGNO (rld[r].in);
7170 else if (GET_CODE (rld[r].in_reg) == REG)
7171 nregno = REGNO (rld[r].in_reg);
7173 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7175 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7176 : HARD_REGNO_NREGS (nregno,
7177 GET_MODE (rld[r].reg_rtx)));
7179 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7181 if (nregno < FIRST_PSEUDO_REGISTER)
7182 for (k = 1; k < nnr; k++)
7183 reg_last_reload_reg[nregno + k]
7185 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7186 REGNO (rld[r].reg_rtx) + k)
7189 /* Unless we inherited this reload, show we haven't
7190 recently done a store.
7191 Previous stores of inherited auto_inc expressions
7192 also have to be discarded. */
7193 if (! reload_inherited[r]
7194 || (rld[r].out && ! rld[r].out_reg))
7195 spill_reg_store[i] = 0;
7197 for (k = 0; k < nr; k++)
7199 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7200 reg_reloaded_contents[i + k]
7201 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7204 reg_reloaded_insn[i + k] = insn;
7205 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7210 /* However, if part of the reload reaches the end, then we must
7211 invalidate the old info for the part that survives to the end. */
7212 else if (part_reaches_end)
7214 for (k = 0; k < nr; k++)
7215 if (reload_reg_reaches_end_p (i + k,
7217 rld[r].when_needed))
7218 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7222 /* The following if-statement was #if 0'd in 1.34 (or before...).
7223 It's reenabled in 1.35 because supposedly nothing else
7224 deals with this problem. */
7226 /* If a register gets output-reloaded from a non-spill register,
7227 that invalidates any previous reloaded copy of it.
7228 But forget_old_reloads_1 won't get to see it, because
7229 it thinks only about the original insn. So invalidate it here. */
7230 if (i < 0 && rld[r].out != 0
7231 && (GET_CODE (rld[r].out) == REG
7232 || (GET_CODE (rld[r].out) == MEM
7233 && GET_CODE (rld[r].out_reg) == REG)))
7235 rtx out = (GET_CODE (rld[r].out) == REG
7236 ? rld[r].out : rld[r].out_reg);
7237 register int nregno = REGNO (out);
7238 if (nregno >= FIRST_PSEUDO_REGISTER)
7240 rtx src_reg, store_insn = NULL_RTX;
7242 reg_last_reload_reg[nregno] = 0;
7244 /* If we can find a hard register that is stored, record
7245 the storing insn so that we may delete this insn with
7246 delete_output_reload. */
7247 src_reg = rld[r].reg_rtx;
7249 /* If this is an optional reload, try to find the source reg
7250 from an input reload. */
7253 rtx set = single_set (insn);
7254 if (set && SET_DEST (set) == rld[r].out)
7258 src_reg = SET_SRC (set);
7260 for (k = 0; k < n_reloads; k++)
7262 if (rld[k].in == src_reg)
7264 src_reg = rld[k].reg_rtx;
7271 store_insn = new_spill_reg_store[REGNO (src_reg)];
7272 if (src_reg && GET_CODE (src_reg) == REG
7273 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7275 int src_regno = REGNO (src_reg);
7276 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7277 /* The place where to find a death note varies with
7278 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7279 necessarily checked exactly in the code that moves
7280 notes, so just check both locations. */
7281 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7283 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7286 spill_reg_store[src_regno + nr] = store_insn;
7287 spill_reg_stored_to[src_regno + nr] = out;
7288 reg_reloaded_contents[src_regno + nr] = nregno;
7289 reg_reloaded_insn[src_regno + nr] = store_insn;
7290 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7291 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7292 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7294 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7296 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7298 reg_last_reload_reg[nregno] = src_reg;
7303 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7305 while (num_regs-- > 0)
7306 reg_last_reload_reg[nregno + num_regs] = 0;
7310 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7313 /* Emit code to perform a reload from IN (which may be a reload register) to
7314 OUT (which may also be a reload register). IN or OUT is from operand
7315 OPNUM with reload type TYPE.
7317 Returns first insn emitted. */
7320 gen_reload (out, in, opnum, type)
7324 enum reload_type type;
7326 rtx last = get_last_insn ();
7329 /* If IN is a paradoxical SUBREG, remove it and try to put the
7330 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7331 if (GET_CODE (in) == SUBREG
7332 && (GET_MODE_SIZE (GET_MODE (in))
7333 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7334 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7335 in = SUBREG_REG (in), out = tem;
7336 else if (GET_CODE (out) == SUBREG
7337 && (GET_MODE_SIZE (GET_MODE (out))
7338 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7339 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7340 out = SUBREG_REG (out), in = tem;
7342 /* How to do this reload can get quite tricky. Normally, we are being
7343 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7344 register that didn't get a hard register. In that case we can just
7345 call emit_move_insn.
7347 We can also be asked to reload a PLUS that adds a register or a MEM to
7348 another register, constant or MEM. This can occur during frame pointer
7349 elimination and while reloading addresses. This case is handled by
7350 trying to emit a single insn to perform the add. If it is not valid,
7351 we use a two insn sequence.
7353 Finally, we could be called to handle an 'o' constraint by putting
7354 an address into a register. In that case, we first try to do this
7355 with a named pattern of "reload_load_address". If no such pattern
7356 exists, we just emit a SET insn and hope for the best (it will normally
7357 be valid on machines that use 'o').
7359 This entire process is made complex because reload will never
7360 process the insns we generate here and so we must ensure that
7361 they will fit their constraints and also by the fact that parts of
7362 IN might be being reloaded separately and replaced with spill registers.
7363 Because of this, we are, in some sense, just guessing the right approach
7364 here. The one listed above seems to work.
7366 ??? At some point, this whole thing needs to be rethought. */
7368 if (GET_CODE (in) == PLUS
7369 && (GET_CODE (XEXP (in, 0)) == REG
7370 || GET_CODE (XEXP (in, 0)) == SUBREG
7371 || GET_CODE (XEXP (in, 0)) == MEM)
7372 && (GET_CODE (XEXP (in, 1)) == REG
7373 || GET_CODE (XEXP (in, 1)) == SUBREG
7374 || CONSTANT_P (XEXP (in, 1))
7375 || GET_CODE (XEXP (in, 1)) == MEM))
7377 /* We need to compute the sum of a register or a MEM and another
7378 register, constant, or MEM, and put it into the reload
7379 register. The best possible way of doing this is if the machine
7380 has a three-operand ADD insn that accepts the required operands.
7382 The simplest approach is to try to generate such an insn and see if it
7383 is recognized and matches its constraints. If so, it can be used.
7385 It might be better not to actually emit the insn unless it is valid,
7386 but we need to pass the insn as an operand to `recog' and
7387 `extract_insn' and it is simpler to emit and then delete the insn if
7388 not valid than to dummy things up. */
7390 rtx op0, op1, tem, insn;
7393 op0 = find_replacement (&XEXP (in, 0));
7394 op1 = find_replacement (&XEXP (in, 1));
7396 /* Since constraint checking is strict, commutativity won't be
7397 checked, so we need to do that here to avoid spurious failure
7398 if the add instruction is two-address and the second operand
7399 of the add is the same as the reload reg, which is frequently
7400 the case. If the insn would be A = B + A, rearrange it so
7401 it will be A = A + B as constrain_operands expects. */
7403 if (GET_CODE (XEXP (in, 1)) == REG
7404 && REGNO (out) == REGNO (XEXP (in, 1)))
7405 tem = op0, op0 = op1, op1 = tem;
7407 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7408 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7410 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7411 code = recog_memoized (insn);
7415 extract_insn (insn);
7416 /* We want constrain operands to treat this insn strictly in
7417 its validity determination, i.e., the way it would after reload
7419 if (constrain_operands (1))
7423 delete_insns_since (last);
7425 /* If that failed, we must use a conservative two-insn sequence.
7427 Use a move to copy one operand into the reload register. Prefer
7428 to reload a constant, MEM or pseudo since the move patterns can
7429 handle an arbitrary operand. If OP1 is not a constant, MEM or
7430 pseudo and OP1 is not a valid operand for an add instruction, then
7433 After reloading one of the operands into the reload register, add
7434 the reload register to the output register.
7436 If there is another way to do this for a specific machine, a
7437 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7440 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7442 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7443 || (GET_CODE (op1) == REG
7444 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7445 || (code != CODE_FOR_nothing
7446 && ! ((*insn_data[code].operand[2].predicate)
7447 (op1, insn_data[code].operand[2].mode))))
7448 tem = op0, op0 = op1, op1 = tem;
7450 gen_reload (out, op0, opnum, type);
7452 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7453 This fixes a problem on the 32K where the stack pointer cannot
7454 be used as an operand of an add insn. */
7456 if (rtx_equal_p (op0, op1))
7459 insn = emit_insn (gen_add2_insn (out, op1));
7461 /* If that failed, copy the address register to the reload register.
7462 Then add the constant to the reload register. */
7464 code = recog_memoized (insn);
7468 extract_insn (insn);
7469 /* We want constrain operands to treat this insn strictly in
7470 its validity determination, i.e., the way it would after reload
7472 if (constrain_operands (1))
7474 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7476 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7481 delete_insns_since (last);
7483 gen_reload (out, op1, opnum, type);
7484 insn = emit_insn (gen_add2_insn (out, op0));
7485 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7488 #ifdef SECONDARY_MEMORY_NEEDED
7489 /* If we need a memory location to do the move, do it that way. */
7490 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7491 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7492 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7493 REGNO_REG_CLASS (REGNO (out)),
7496 /* Get the memory to use and rewrite both registers to its mode. */
7497 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7499 if (GET_MODE (loc) != GET_MODE (out))
7500 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7502 if (GET_MODE (loc) != GET_MODE (in))
7503 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7505 gen_reload (loc, in, opnum, type);
7506 gen_reload (out, loc, opnum, type);
7510 /* If IN is a simple operand, use gen_move_insn. */
7511 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7512 emit_insn (gen_move_insn (out, in));
7514 #ifdef HAVE_reload_load_address
7515 else if (HAVE_reload_load_address)
7516 emit_insn (gen_reload_load_address (out, in));
7519 /* Otherwise, just write (set OUT IN) and hope for the best. */
7521 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7523 /* Return the first insn emitted.
7524 We can not just return get_last_insn, because there may have
7525 been multiple instructions emitted. Also note that gen_move_insn may
7526 emit more than one insn itself, so we can not assume that there is one
7527 insn emitted per emit_insn_before call. */
7529 return last ? NEXT_INSN (last) : get_insns ();
7532 /* Delete a previously made output-reload
7533 whose result we now believe is not needed.
7534 First we double-check.
7536 INSN is the insn now being processed.
7537 LAST_RELOAD_REG is the hard register number for which we want to delete
7538 the last output reload.
7539 J is the reload-number that originally used REG. The caller has made
7540 certain that reload J doesn't use REG any longer for input. */
7543 delete_output_reload (insn, j, last_reload_reg)
7546 int last_reload_reg;
7548 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7549 rtx reg = spill_reg_stored_to[last_reload_reg];
7552 int n_inherited = 0;
7556 /* Get the raw pseudo-register referred to. */
7558 while (GET_CODE (reg) == SUBREG)
7559 reg = SUBREG_REG (reg);
7560 substed = reg_equiv_memory_loc[REGNO (reg)];
7562 /* This is unsafe if the operand occurs more often in the current
7563 insn than it is inherited. */
7564 for (k = n_reloads - 1; k >= 0; k--)
7566 rtx reg2 = rld[k].in;
7569 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7570 reg2 = rld[k].in_reg;
7572 if (rld[k].out && ! rld[k].out_reg)
7573 reg2 = XEXP (rld[k].in_reg, 0);
7575 while (GET_CODE (reg2) == SUBREG)
7576 reg2 = SUBREG_REG (reg2);
7577 if (rtx_equal_p (reg2, reg))
7579 if (reload_inherited[k] || reload_override_in[k] || k == j)
7582 reg2 = rld[k].out_reg;
7585 while (GET_CODE (reg2) == SUBREG)
7586 reg2 = XEXP (reg2, 0);
7587 if (rtx_equal_p (reg2, reg))
7594 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7596 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7597 if (n_occurrences > n_inherited)
7600 /* If the pseudo-reg we are reloading is no longer referenced
7601 anywhere between the store into it and here,
7602 and no jumps or labels intervene, then the value can get
7603 here through the reload reg alone.
7604 Otherwise, give up--return. */
7605 for (i1 = NEXT_INSN (output_reload_insn);
7606 i1 != insn; i1 = NEXT_INSN (i1))
7608 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7610 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7611 && reg_mentioned_p (reg, PATTERN (i1)))
7613 /* If this is USE in front of INSN, we only have to check that
7614 there are no more references than accounted for by inheritance. */
7615 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7617 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7618 i1 = NEXT_INSN (i1);
7620 if (n_occurrences <= n_inherited && i1 == insn)
7626 /* The caller has already checked that REG dies or is set in INSN.
7627 It has also checked that we are optimizing, and thus some inaccurancies
7628 in the debugging information are acceptable.
7629 So we could just delete output_reload_insn.
7630 But in some cases we can improve the debugging information without
7631 sacrificing optimization - maybe even improving the code:
7632 See if the pseudo reg has been completely replaced
7633 with reload regs. If so, delete the store insn
7634 and forget we had a stack slot for the pseudo. */
7635 if (rld[j].out != rld[j].in
7636 && REG_N_DEATHS (REGNO (reg)) == 1
7637 && REG_N_SETS (REGNO (reg)) == 1
7638 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7639 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7643 /* We know that it was used only between here
7644 and the beginning of the current basic block.
7645 (We also know that the last use before INSN was
7646 the output reload we are thinking of deleting, but never mind that.)
7647 Search that range; see if any ref remains. */
7648 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7650 rtx set = single_set (i2);
7652 /* Uses which just store in the pseudo don't count,
7653 since if they are the only uses, they are dead. */
7654 if (set != 0 && SET_DEST (set) == reg)
7656 if (GET_CODE (i2) == CODE_LABEL
7657 || GET_CODE (i2) == JUMP_INSN)
7659 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7660 && reg_mentioned_p (reg, PATTERN (i2)))
7662 /* Some other ref remains; just delete the output reload we
7664 delete_address_reloads (output_reload_insn, insn);
7665 PUT_CODE (output_reload_insn, NOTE);
7666 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7667 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7672 /* Delete the now-dead stores into this pseudo. */
7673 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7675 rtx set = single_set (i2);
7677 if (set != 0 && SET_DEST (set) == reg)
7679 delete_address_reloads (i2, insn);
7680 /* This might be a basic block head,
7681 thus don't use delete_insn. */
7682 PUT_CODE (i2, NOTE);
7683 NOTE_SOURCE_FILE (i2) = 0;
7684 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7686 if (GET_CODE (i2) == CODE_LABEL
7687 || GET_CODE (i2) == JUMP_INSN)
7691 /* For the debugging info,
7692 say the pseudo lives in this reload reg. */
7693 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7694 alter_reg (REGNO (reg), -1);
7696 delete_address_reloads (output_reload_insn, insn);
7697 PUT_CODE (output_reload_insn, NOTE);
7698 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7699 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7703 /* We are going to delete DEAD_INSN. Recursively delete loads of
7704 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7705 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7707 delete_address_reloads (dead_insn, current_insn)
7708 rtx dead_insn, current_insn;
7710 rtx set = single_set (dead_insn);
7711 rtx set2, dst, prev, next;
7714 rtx dst = SET_DEST (set);
7715 if (GET_CODE (dst) == MEM)
7716 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7718 /* If we deleted the store from a reloaded post_{in,de}c expression,
7719 we can delete the matching adds. */
7720 prev = PREV_INSN (dead_insn);
7721 next = NEXT_INSN (dead_insn);
7722 if (! prev || ! next)
7724 set = single_set (next);
7725 set2 = single_set (prev);
7727 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7728 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7729 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7731 dst = SET_DEST (set);
7732 if (! rtx_equal_p (dst, SET_DEST (set2))
7733 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7734 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7735 || (INTVAL (XEXP (SET_SRC (set), 1))
7736 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7742 /* Subfunction of delete_address_reloads: process registers found in X. */
7744 delete_address_reloads_1 (dead_insn, x, current_insn)
7745 rtx dead_insn, x, current_insn;
7747 rtx prev, set, dst, i2;
7749 enum rtx_code code = GET_CODE (x);
7753 const char *fmt = GET_RTX_FORMAT (code);
7754 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7757 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7758 else if (fmt[i] == 'E')
7760 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7761 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7768 if (spill_reg_order[REGNO (x)] < 0)
7771 /* Scan backwards for the insn that sets x. This might be a way back due
7773 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7775 code = GET_CODE (prev);
7776 if (code == CODE_LABEL || code == JUMP_INSN)
7778 if (GET_RTX_CLASS (code) != 'i')
7780 if (reg_set_p (x, PATTERN (prev)))
7782 if (reg_referenced_p (x, PATTERN (prev)))
7785 if (! prev || INSN_UID (prev) < reload_first_uid)
7787 /* Check that PREV only sets the reload register. */
7788 set = single_set (prev);
7791 dst = SET_DEST (set);
7792 if (GET_CODE (dst) != REG
7793 || ! rtx_equal_p (dst, x))
7795 if (! reg_set_p (dst, PATTERN (dead_insn)))
7797 /* Check if DST was used in a later insn -
7798 it might have been inherited. */
7799 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7801 if (GET_CODE (i2) == CODE_LABEL)
7805 if (reg_referenced_p (dst, PATTERN (i2)))
7807 /* If there is a reference to the register in the current insn,
7808 it might be loaded in a non-inherited reload. If no other
7809 reload uses it, that means the register is set before
7811 if (i2 == current_insn)
7813 for (j = n_reloads - 1; j >= 0; j--)
7814 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7815 || reload_override_in[j] == dst)
7817 for (j = n_reloads - 1; j >= 0; j--)
7818 if (rld[j].in && rld[j].reg_rtx == dst)
7825 if (GET_CODE (i2) == JUMP_INSN)
7827 /* If DST is still live at CURRENT_INSN, check if it is used for
7828 any reload. Note that even if CURRENT_INSN sets DST, we still
7829 have to check the reloads. */
7830 if (i2 == current_insn)
7832 for (j = n_reloads - 1; j >= 0; j--)
7833 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7834 || reload_override_in[j] == dst)
7836 /* ??? We can't finish the loop here, because dst might be
7837 allocated to a pseudo in this block if no reload in this
7838 block needs any of the clsses containing DST - see
7839 spill_hard_reg. There is no easy way to tell this, so we
7840 have to scan till the end of the basic block. */
7842 if (reg_set_p (dst, PATTERN (i2)))
7846 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7847 reg_reloaded_contents[REGNO (dst)] = -1;
7848 /* Can't use delete_insn here because PREV might be a basic block head. */
7849 PUT_CODE (prev, NOTE);
7850 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7851 NOTE_SOURCE_FILE (prev) = 0;
7854 /* Output reload-insns to reload VALUE into RELOADREG.
7855 VALUE is an autoincrement or autodecrement RTX whose operand
7856 is a register or memory location;
7857 so reloading involves incrementing that location.
7858 IN is either identical to VALUE, or some cheaper place to reload from.
7860 INC_AMOUNT is the number to increment or decrement by (always positive).
7861 This cannot be deduced from VALUE.
7863 Return the instruction that stores into RELOADREG. */
7866 inc_for_reload (reloadreg, in, value, inc_amount)
7871 /* REG or MEM to be copied and incremented. */
7872 rtx incloc = XEXP (value, 0);
7873 /* Nonzero if increment after copying. */
7874 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7880 rtx real_in = in == value ? XEXP (in, 0) : in;
7882 /* No hard register is equivalent to this register after
7883 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7884 we could inc/dec that register as well (maybe even using it for
7885 the source), but I'm not sure it's worth worrying about. */
7886 if (GET_CODE (incloc) == REG)
7887 reg_last_reload_reg[REGNO (incloc)] = 0;
7889 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7890 inc_amount = -inc_amount;
7892 inc = GEN_INT (inc_amount);
7894 /* If this is post-increment, first copy the location to the reload reg. */
7895 if (post && real_in != reloadreg)
7896 emit_insn (gen_move_insn (reloadreg, real_in));
7900 /* See if we can directly increment INCLOC. Use a method similar to
7901 that in gen_reload. */
7903 last = get_last_insn ();
7904 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7905 gen_rtx_PLUS (GET_MODE (incloc),
7908 code = recog_memoized (add_insn);
7911 extract_insn (add_insn);
7912 if (constrain_operands (1))
7914 /* If this is a pre-increment and we have incremented the value
7915 where it lives, copy the incremented value to RELOADREG to
7916 be used as an address. */
7919 emit_insn (gen_move_insn (reloadreg, incloc));
7924 delete_insns_since (last);
7927 /* If couldn't do the increment directly, must increment in RELOADREG.
7928 The way we do this depends on whether this is pre- or post-increment.
7929 For pre-increment, copy INCLOC to the reload register, increment it
7930 there, then save back. */
7934 if (in != reloadreg)
7935 emit_insn (gen_move_insn (reloadreg, real_in));
7936 emit_insn (gen_add2_insn (reloadreg, inc));
7937 store = emit_insn (gen_move_insn (incloc, reloadreg));
7942 Because this might be a jump insn or a compare, and because RELOADREG
7943 may not be available after the insn in an input reload, we must do
7944 the incrementation before the insn being reloaded for.
7946 We have already copied IN to RELOADREG. Increment the copy in
7947 RELOADREG, save that back, then decrement RELOADREG so it has
7948 the original value. */
7950 emit_insn (gen_add2_insn (reloadreg, inc));
7951 store = emit_insn (gen_move_insn (incloc, reloadreg));
7952 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7958 /* Return 1 if we are certain that the constraint-string STRING allows
7959 the hard register REG. Return 0 if we can't be sure of this. */
7962 constraint_accepts_reg_p (string, reg)
7967 int regno = true_regnum (reg);
7970 /* Initialize for first alternative. */
7972 /* Check that each alternative contains `g' or `r'. */
7974 switch (c = *string++)
7977 /* If an alternative lacks `g' or `r', we lose. */
7980 /* If an alternative lacks `g' or `r', we lose. */
7983 /* Initialize for next alternative. */
7988 /* Any general reg wins for this alternative. */
7989 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7993 /* Any reg in specified class wins for this alternative. */
7995 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7997 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8003 /* INSN is a no-op; delete it.
8004 If this sets the return value of the function, we must keep a USE around,
8005 in case this is in a different basic block than the final USE. Otherwise,
8006 we could loose important register lifeness information on
8007 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8008 spills: subsequent passes assume that spill registers are dead at the end
8010 VALUE must be the return value in such a case, NULL otherwise. */
8012 reload_cse_delete_noop_set (insn, value)
8017 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8018 INSN_CODE (insn) = -1;
8019 REG_NOTES (insn) = NULL_RTX;
8023 PUT_CODE (insn, NOTE);
8024 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8025 NOTE_SOURCE_FILE (insn) = 0;
8029 /* See whether a single set SET is a noop. */
8031 reload_cse_noop_set_p (set)
8034 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8037 /* Try to simplify INSN. */
8039 reload_cse_simplify (insn)
8042 rtx body = PATTERN (insn);
8044 if (GET_CODE (body) == SET)
8048 /* Simplify even if we may think it is a no-op.
8049 We may think a memory load of a value smaller than WORD_SIZE
8050 is redundant because we haven't taken into account possible
8051 implicit extension. reload_cse_simplify_set() will bring
8052 this out, so it's safer to simplify before we delete. */
8053 count += reload_cse_simplify_set (body, insn);
8055 if (!count && reload_cse_noop_set_p (body))
8057 rtx value = SET_DEST (body);
8058 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8060 reload_cse_delete_noop_set (insn, value);
8065 apply_change_group ();
8067 reload_cse_simplify_operands (insn);
8069 else if (GET_CODE (body) == PARALLEL)
8073 rtx value = NULL_RTX;
8075 /* If every action in a PARALLEL is a noop, we can delete
8076 the entire PARALLEL. */
8077 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8079 rtx part = XVECEXP (body, 0, i);
8080 if (GET_CODE (part) == SET)
8082 if (! reload_cse_noop_set_p (part))
8084 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8088 value = SET_DEST (part);
8091 else if (GET_CODE (part) != CLOBBER)
8097 reload_cse_delete_noop_set (insn, value);
8098 /* We're done with this insn. */
8102 /* It's not a no-op, but we can try to simplify it. */
8103 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8104 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8105 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8108 apply_change_group ();
8110 reload_cse_simplify_operands (insn);
8114 /* Do a very simple CSE pass over the hard registers.
8116 This function detects no-op moves where we happened to assign two
8117 different pseudo-registers to the same hard register, and then
8118 copied one to the other. Reload will generate a useless
8119 instruction copying a register to itself.
8121 This function also detects cases where we load a value from memory
8122 into two different registers, and (if memory is more expensive than
8123 registers) changes it to simply copy the first register into the
8126 Another optimization is performed that scans the operands of each
8127 instruction to see whether the value is already available in a
8128 hard register. It then replaces the operand with the hard register
8129 if possible, much like an optional reload would. */
8132 reload_cse_regs_1 (first)
8138 init_alias_analysis ();
8140 for (insn = first; insn; insn = NEXT_INSN (insn))
8143 reload_cse_simplify (insn);
8145 cselib_process_insn (insn);
8149 end_alias_analysis ();
8153 /* Call cse / combine like post-reload optimization phases.
8154 FIRST is the first instruction. */
8156 reload_cse_regs (first)
8159 reload_cse_regs_1 (first);
8161 reload_cse_move2add (first);
8162 if (flag_expensive_optimizations)
8163 reload_cse_regs_1 (first);
8166 /* Try to simplify a single SET instruction. SET is the set pattern.
8167 INSN is the instruction it came from.
8168 This function only handles one case: if we set a register to a value
8169 which is not a register, we try to find that value in some other register
8170 and change the set into a register copy. */
8173 reload_cse_simplify_set (set, insn)
8180 enum reg_class dclass;
8183 struct elt_loc_list *l;
8184 #ifdef LOAD_EXTEND_OP
8185 enum rtx_code extend_op = NIL;
8188 dreg = true_regnum (SET_DEST (set));
8192 src = SET_SRC (set);
8193 if (side_effects_p (src) || true_regnum (src) >= 0)
8196 dclass = REGNO_REG_CLASS (dreg);
8198 #ifdef LOAD_EXTEND_OP
8199 /* When replacing a memory with a register, we need to honor assumptions
8200 that combine made wrt the contents of sign bits. We'll do this by
8201 generating an extend instruction instead of a reg->reg copy. Thus
8202 the destination must be a register that we can widen. */
8203 if (GET_CODE (src) == MEM
8204 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8205 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8206 && GET_CODE (SET_DEST (set)) != REG)
8210 /* If memory loads are cheaper than register copies, don't change them. */
8211 if (GET_CODE (src) == MEM)
8212 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8213 else if (CONSTANT_P (src))
8214 old_cost = rtx_cost (src, SET);
8215 else if (GET_CODE (src) == REG)
8216 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8217 REGNO_REG_CLASS (REGNO (src)), dclass);
8220 old_cost = rtx_cost (src, SET);
8222 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8225 for (l = val->locs; l; l = l->next)
8227 rtx this_rtx = l->loc;
8230 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8232 #ifdef LOAD_EXTEND_OP
8233 if (extend_op != NIL)
8235 HOST_WIDE_INT this_val;
8237 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8238 constants, such as SYMBOL_REF, cannot be extended. */
8239 if (GET_CODE (this_rtx) != CONST_INT)
8242 this_val = INTVAL (this_rtx);
8246 this_val &= GET_MODE_MASK (GET_MODE (src));
8249 /* ??? In theory we're already extended. */
8250 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8255 this_rtx = GEN_INT (this_val);
8258 this_cost = rtx_cost (this_rtx, SET);
8260 else if (GET_CODE (this_rtx) == REG)
8262 #ifdef LOAD_EXTEND_OP
8263 if (extend_op != NIL)
8265 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8266 this_cost = rtx_cost (this_rtx, SET);
8270 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8271 REGNO_REG_CLASS (REGNO (this_rtx)),
8277 /* If equal costs, prefer registers over anything else. That
8278 tends to lead to smaller instructions on some machines. */
8279 if (this_cost < old_cost
8280 || (this_cost == old_cost
8281 && GET_CODE (this_rtx) == REG
8282 && GET_CODE (SET_SRC (set)) != REG))
8284 #ifdef LOAD_EXTEND_OP
8285 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8286 && extend_op != NIL)
8288 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8289 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8290 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8294 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8295 old_cost = this_cost, did_change = 1;
8302 /* Try to replace operands in INSN with equivalent values that are already
8303 in registers. This can be viewed as optional reloading.
8305 For each non-register operand in the insn, see if any hard regs are
8306 known to be equivalent to that operand. Record the alternatives which
8307 can accept these hard registers. Among all alternatives, select the
8308 ones which are better or equal to the one currently matching, where
8309 "better" is in terms of '?' and '!' constraints. Among the remaining
8310 alternatives, select the one which replaces most operands with
8314 reload_cse_simplify_operands (insn)
8319 /* For each operand, all registers that are equivalent to it. */
8320 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8322 const char *constraints[MAX_RECOG_OPERANDS];
8324 /* Vector recording how bad an alternative is. */
8325 int *alternative_reject;
8326 /* Vector recording how many registers can be introduced by choosing
8327 this alternative. */
8328 int *alternative_nregs;
8329 /* Array of vectors recording, for each operand and each alternative,
8330 which hard register to substitute, or -1 if the operand should be
8332 int *op_alt_regno[MAX_RECOG_OPERANDS];
8333 /* Array of alternatives, sorted in order of decreasing desirability. */
8334 int *alternative_order;
8335 rtx reg = gen_rtx_REG (VOIDmode, -1);
8337 extract_insn (insn);
8339 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8342 /* Figure out which alternative currently matches. */
8343 if (! constrain_operands (1))
8344 fatal_insn_not_found (insn);
8346 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8347 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8348 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8349 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8350 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8352 /* For each operand, find out which regs are equivalent. */
8353 for (i = 0; i < recog_data.n_operands; i++)
8356 struct elt_loc_list *l;
8358 CLEAR_HARD_REG_SET (equiv_regs[i]);
8360 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8361 right, so avoid the problem here. Likewise if we have a constant
8362 and the insn pattern doesn't tell us the mode we need. */
8363 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8364 || (CONSTANT_P (recog_data.operand[i])
8365 && recog_data.operand_mode[i] == VOIDmode))
8368 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8372 for (l = v->locs; l; l = l->next)
8373 if (GET_CODE (l->loc) == REG)
8374 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8377 for (i = 0; i < recog_data.n_operands; i++)
8379 enum machine_mode mode;
8383 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8384 for (j = 0; j < recog_data.n_alternatives; j++)
8385 op_alt_regno[i][j] = -1;
8387 p = constraints[i] = recog_data.constraints[i];
8388 mode = recog_data.operand_mode[i];
8390 /* Add the reject values for each alternative given by the constraints
8391 for this operand. */
8399 alternative_reject[j] += 3;
8401 alternative_reject[j] += 300;
8404 /* We won't change operands which are already registers. We
8405 also don't want to modify output operands. */
8406 regno = true_regnum (recog_data.operand[i]);
8408 || constraints[i][0] == '='
8409 || constraints[i][0] == '+')
8412 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8414 int class = (int) NO_REGS;
8416 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8419 REGNO (reg) = regno;
8420 PUT_MODE (reg, mode);
8422 /* We found a register equal to this operand. Now look for all
8423 alternatives that can accept this register and have not been
8424 assigned a register they can use yet. */
8433 case '=': case '+': case '?':
8434 case '#': case '&': case '!':
8436 case '0': case '1': case '2': case '3': case '4':
8437 case '5': case '6': case '7': case '8': case '9':
8438 case 'm': case '<': case '>': case 'V': case 'o':
8439 case 'E': case 'F': case 'G': case 'H':
8440 case 's': case 'i': case 'n':
8441 case 'I': case 'J': case 'K': case 'L':
8442 case 'M': case 'N': case 'O': case 'P':
8444 /* These don't say anything we care about. */
8448 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8453 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8456 case ',': case '\0':
8457 /* See if REGNO fits this alternative, and set it up as the
8458 replacement register if we don't have one for this
8459 alternative yet and the operand being replaced is not
8460 a cheap CONST_INT. */
8461 if (op_alt_regno[i][j] == -1
8462 && reg_fits_class_p (reg, class, 0, mode)
8463 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8464 || (rtx_cost (recog_data.operand[i], SET)
8465 > rtx_cost (reg, SET))))
8467 alternative_nregs[j]++;
8468 op_alt_regno[i][j] = regno;
8480 /* Record all alternatives which are better or equal to the currently
8481 matching one in the alternative_order array. */
8482 for (i = j = 0; i < recog_data.n_alternatives; i++)
8483 if (alternative_reject[i] <= alternative_reject[which_alternative])
8484 alternative_order[j++] = i;
8485 recog_data.n_alternatives = j;
8487 /* Sort it. Given a small number of alternatives, a dumb algorithm
8488 won't hurt too much. */
8489 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8492 int best_reject = alternative_reject[alternative_order[i]];
8493 int best_nregs = alternative_nregs[alternative_order[i]];
8496 for (j = i + 1; j < recog_data.n_alternatives; j++)
8498 int this_reject = alternative_reject[alternative_order[j]];
8499 int this_nregs = alternative_nregs[alternative_order[j]];
8501 if (this_reject < best_reject
8502 || (this_reject == best_reject && this_nregs < best_nregs))
8505 best_reject = this_reject;
8506 best_nregs = this_nregs;
8510 tmp = alternative_order[best];
8511 alternative_order[best] = alternative_order[i];
8512 alternative_order[i] = tmp;
8515 /* Substitute the operands as determined by op_alt_regno for the best
8517 j = alternative_order[0];
8519 for (i = 0; i < recog_data.n_operands; i++)
8521 enum machine_mode mode = recog_data.operand_mode[i];
8522 if (op_alt_regno[i][j] == -1)
8525 validate_change (insn, recog_data.operand_loc[i],
8526 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8529 for (i = recog_data.n_dups - 1; i >= 0; i--)
8531 int op = recog_data.dup_num[i];
8532 enum machine_mode mode = recog_data.operand_mode[op];
8534 if (op_alt_regno[op][j] == -1)
8537 validate_change (insn, recog_data.dup_loc[i],
8538 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8541 return apply_change_group ();
8544 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8546 This code might also be useful when reload gave up on reg+reg addresssing
8547 because of clashes between the return register and INDEX_REG_CLASS. */
8549 /* The maximum number of uses of a register we can keep track of to
8550 replace them with reg+reg addressing. */
8551 #define RELOAD_COMBINE_MAX_USES 6
8553 /* INSN is the insn where a register has ben used, and USEP points to the
8554 location of the register within the rtl. */
8555 struct reg_use { rtx insn, *usep; };
8557 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8558 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8559 indicates where it becomes live again.
8560 Otherwise, USE_INDEX is the index of the last encountered use of the
8561 register (which is first among these we have seen since we scan backwards),
8562 OFFSET contains the constant offset that is added to the register in
8563 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8564 last, of these uses.
8565 STORE_RUID is always meaningful if we only want to use a value in a
8566 register in a different place: it denotes the next insn in the insn
8567 stream (i.e. the last ecountered) that sets or clobbers the register. */
8570 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8575 } reg_state[FIRST_PSEUDO_REGISTER];
8577 /* Reverse linear uid. This is increased in reload_combine while scanning
8578 the instructions from last to first. It is used to set last_label_ruid
8579 and the store_ruid / use_ruid fields in reg_state. */
8580 static int reload_combine_ruid;
8582 #define LABEL_LIVE(LABEL) \
8583 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8589 int first_index_reg = -1, last_index_reg;
8592 int last_label_ruid;
8593 int min_labelno, n_labels;
8594 HARD_REG_SET ever_live_at_start, *label_live;
8596 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8597 reload has already used it where appropriate, so there is no use in
8598 trying to generate it now. */
8599 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8602 /* To avoid wasting too much time later searching for an index register,
8603 determine the minimum and maximum index register numbers. */
8604 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8605 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8607 if (first_index_reg == -1)
8608 first_index_reg = r;
8613 /* If no index register is available, we can quit now. */
8614 if (first_index_reg == -1)
8617 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8618 information is a bit fuzzy immediately after reload, but it's
8619 still good enough to determine which registers are live at a jump
8621 min_labelno = get_first_label_num ();
8622 n_labels = max_label_num () - min_labelno;
8623 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8624 CLEAR_HARD_REG_SET (ever_live_at_start);
8626 for (i = n_basic_blocks - 1; i >= 0; i--)
8628 insn = BLOCK_HEAD (i);
8629 if (GET_CODE (insn) == CODE_LABEL)
8633 REG_SET_TO_HARD_REG_SET (live,
8634 BASIC_BLOCK (i)->global_live_at_start);
8635 compute_use_by_pseudos (&live,
8636 BASIC_BLOCK (i)->global_live_at_start);
8637 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8638 IOR_HARD_REG_SET (ever_live_at_start, live);
8642 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8643 last_label_ruid = reload_combine_ruid = 0;
8644 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8646 reg_state[r].store_ruid = reload_combine_ruid;
8648 reg_state[r].use_index = -1;
8650 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8653 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8657 /* We cannot do our optimization across labels. Invalidating all the use
8658 information we have would be costly, so we just note where the label
8659 is and then later disable any optimization that would cross it. */
8660 if (GET_CODE (insn) == CODE_LABEL)
8661 last_label_ruid = reload_combine_ruid;
8662 else if (GET_CODE (insn) == BARRIER)
8663 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8664 if (! fixed_regs[r])
8665 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8667 if (! INSN_P (insn))
8670 reload_combine_ruid++;
8672 /* Look for (set (REGX) (CONST_INT))
8673 (set (REGX) (PLUS (REGX) (REGY)))
8675 ... (MEM (REGX)) ...
8677 (set (REGZ) (CONST_INT))
8679 ... (MEM (PLUS (REGZ) (REGY)))... .
8681 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8682 and that we know all uses of REGX before it dies. */
8683 set = single_set (insn);
8685 && GET_CODE (SET_DEST (set)) == REG
8686 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8687 GET_MODE (SET_DEST (set)))
8689 && GET_CODE (SET_SRC (set)) == PLUS
8690 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8691 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8692 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8694 rtx reg = SET_DEST (set);
8695 rtx plus = SET_SRC (set);
8696 rtx base = XEXP (plus, 1);
8697 rtx prev = prev_nonnote_insn (insn);
8698 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8699 unsigned int regno = REGNO (reg);
8700 rtx const_reg = NULL_RTX;
8701 rtx reg_sum = NULL_RTX;
8703 /* Now, we need an index register.
8704 We'll set index_reg to this index register, const_reg to the
8705 register that is to be loaded with the constant
8706 (denoted as REGZ in the substitution illustration above),
8707 and reg_sum to the register-register that we want to use to
8708 substitute uses of REG (typically in MEMs) with.
8709 First check REG and BASE for being index registers;
8710 we can use them even if they are not dead. */
8711 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8712 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8720 /* Otherwise, look for a free index register. Since we have
8721 checked above that neiter REG nor BASE are index registers,
8722 if we find anything at all, it will be different from these
8724 for (i = first_index_reg; i <= last_index_reg; i++)
8726 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8728 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8729 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8730 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8732 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8734 const_reg = index_reg;
8735 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8741 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8742 (REGY), i.e. BASE, is not clobbered before the last use we'll
8745 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8746 && rtx_equal_p (SET_DEST (prev_set), reg)
8747 && reg_state[regno].use_index >= 0
8748 && (reg_state[REGNO (base)].store_ruid
8749 <= reg_state[regno].use_ruid)
8754 /* Change destination register and, if necessary, the
8755 constant value in PREV, the constant loading instruction. */
8756 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8757 if (reg_state[regno].offset != const0_rtx)
8758 validate_change (prev,
8759 &SET_SRC (prev_set),
8760 GEN_INT (INTVAL (SET_SRC (prev_set))
8761 + INTVAL (reg_state[regno].offset)),
8764 /* Now for every use of REG that we have recorded, replace REG
8766 for (i = reg_state[regno].use_index;
8767 i < RELOAD_COMBINE_MAX_USES; i++)
8768 validate_change (reg_state[regno].reg_use[i].insn,
8769 reg_state[regno].reg_use[i].usep,
8772 if (apply_change_group ())
8776 /* Delete the reg-reg addition. */
8777 PUT_CODE (insn, NOTE);
8778 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8779 NOTE_SOURCE_FILE (insn) = 0;
8781 if (reg_state[regno].offset != const0_rtx)
8782 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8784 for (np = ®_NOTES (prev); *np;)
8786 if (REG_NOTE_KIND (*np) == REG_EQUAL
8787 || REG_NOTE_KIND (*np) == REG_EQUIV)
8788 *np = XEXP (*np, 1);
8790 np = &XEXP (*np, 1);
8793 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8794 reg_state[REGNO (const_reg)].store_ruid
8795 = reload_combine_ruid;
8801 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8803 if (GET_CODE (insn) == CALL_INSN)
8807 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8808 if (call_used_regs[r])
8810 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8811 reg_state[r].store_ruid = reload_combine_ruid;
8814 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8815 link = XEXP (link, 1))
8817 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8818 if (GET_CODE (usage_rtx) == REG)
8821 unsigned int start_reg = REGNO (usage_rtx);
8822 unsigned int num_regs =
8823 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8824 unsigned int end_reg = start_reg + num_regs - 1;
8825 for (i = start_reg; i <= end_reg; i++)
8826 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8828 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8829 reg_state[i].store_ruid = reload_combine_ruid;
8832 reg_state[i].use_index = -1;
8837 else if (GET_CODE (insn) == JUMP_INSN
8838 && GET_CODE (PATTERN (insn)) != RETURN)
8840 /* Non-spill registers might be used at the call destination in
8841 some unknown fashion, so we have to mark the unknown use. */
8844 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8845 && JUMP_LABEL (insn))
8846 live = &LABEL_LIVE (JUMP_LABEL (insn));
8848 live = &ever_live_at_start;
8850 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8851 if (TEST_HARD_REG_BIT (*live, i))
8852 reg_state[i].use_index = -1;
8855 reload_combine_note_use (&PATTERN (insn), insn);
8856 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8858 if (REG_NOTE_KIND (note) == REG_INC
8859 && GET_CODE (XEXP (note, 0)) == REG)
8861 int regno = REGNO (XEXP (note, 0));
8863 reg_state[regno].store_ruid = reload_combine_ruid;
8864 reg_state[regno].use_index = -1;
8872 /* Check if DST is a register or a subreg of a register; if it is,
8873 update reg_state[regno].store_ruid and reg_state[regno].use_index
8874 accordingly. Called via note_stores from reload_combine. */
8877 reload_combine_note_store (dst, set, data)
8879 void *data ATTRIBUTE_UNUSED;
8883 enum machine_mode mode = GET_MODE (dst);
8885 if (GET_CODE (dst) == SUBREG)
8887 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8888 GET_MODE (SUBREG_REG (dst)),
8891 dst = SUBREG_REG (dst);
8893 if (GET_CODE (dst) != REG)
8895 regno += REGNO (dst);
8897 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8898 careful with registers / register parts that are not full words.
8900 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8901 if (GET_CODE (set) != SET
8902 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8903 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8904 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8906 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8908 reg_state[i].use_index = -1;
8909 reg_state[i].store_ruid = reload_combine_ruid;
8914 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8916 reg_state[i].store_ruid = reload_combine_ruid;
8917 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8922 /* XP points to a piece of rtl that has to be checked for any uses of
8924 *XP is the pattern of INSN, or a part of it.
8925 Called from reload_combine, and recursively by itself. */
8927 reload_combine_note_use (xp, insn)
8931 enum rtx_code code = x->code;
8934 rtx offset = const0_rtx; /* For the REG case below. */
8939 if (GET_CODE (SET_DEST (x)) == REG)
8941 reload_combine_note_use (&SET_SRC (x), insn);
8947 /* If this is the USE of a return value, we can't change it. */
8948 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8950 /* Mark the return register as used in an unknown fashion. */
8951 rtx reg = XEXP (x, 0);
8952 int regno = REGNO (reg);
8953 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8955 while (--nregs >= 0)
8956 reg_state[regno + nregs].use_index = -1;
8962 if (GET_CODE (SET_DEST (x)) == REG)
8967 /* We are interested in (plus (reg) (const_int)) . */
8968 if (GET_CODE (XEXP (x, 0)) != REG
8969 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8971 offset = XEXP (x, 1);
8976 int regno = REGNO (x);
8980 /* Some spurious USEs of pseudo registers might remain.
8981 Just ignore them. */
8982 if (regno >= FIRST_PSEUDO_REGISTER)
8985 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8987 /* We can't substitute into multi-hard-reg uses. */
8990 while (--nregs >= 0)
8991 reg_state[regno + nregs].use_index = -1;
8995 /* If this register is already used in some unknown fashion, we
8997 If we decrement the index from zero to -1, we can't store more
8998 uses, so this register becomes used in an unknown fashion. */
8999 use_index = --reg_state[regno].use_index;
9003 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9005 /* We have found another use for a register that is already
9006 used later. Check if the offsets match; if not, mark the
9007 register as used in an unknown fashion. */
9008 if (! rtx_equal_p (offset, reg_state[regno].offset))
9010 reg_state[regno].use_index = -1;
9016 /* This is the first use of this register we have seen since we
9017 marked it as dead. */
9018 reg_state[regno].offset = offset;
9019 reg_state[regno].use_ruid = reload_combine_ruid;
9021 reg_state[regno].reg_use[use_index].insn = insn;
9022 reg_state[regno].reg_use[use_index].usep = xp;
9030 /* Recursively process the components of X. */
9031 fmt = GET_RTX_FORMAT (code);
9032 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9035 reload_combine_note_use (&XEXP (x, i), insn);
9036 else if (fmt[i] == 'E')
9038 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9039 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9044 /* See if we can reduce the cost of a constant by replacing a move
9045 with an add. We track situations in which a register is set to a
9046 constant or to a register plus a constant. */
9047 /* We cannot do our optimization across labels. Invalidating all the
9048 information about register contents we have would be costly, so we
9049 use move2add_last_label_luid to note where the label is and then
9050 later disable any optimization that would cross it.
9051 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9052 reg_set_luid[n] is greater than last_label_luid[n] . */
9053 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9055 /* If reg_base_reg[n] is negative, register n has been set to
9056 reg_offset[n] in mode reg_mode[n] .
9057 If reg_base_reg[n] is non-negative, register n has been set to the
9058 sum of reg_offset[n] and the value of register reg_base_reg[n]
9059 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9060 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9061 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9062 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9064 /* move2add_luid is linearily increased while scanning the instructions
9065 from first to last. It is used to set reg_set_luid in
9066 reload_cse_move2add and move2add_note_store. */
9067 static int move2add_luid;
9069 /* move2add_last_label_luid is set whenever a label is found. Labels
9070 invalidate all previously collected reg_offset data. */
9071 static int move2add_last_label_luid;
9073 /* Generate a CONST_INT and force it in the range of MODE. */
9075 static HOST_WIDE_INT
9076 sext_for_mode (mode, value)
9077 enum machine_mode mode;
9078 HOST_WIDE_INT value;
9080 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9081 int width = GET_MODE_BITSIZE (mode);
9083 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9085 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9086 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9087 cval |= (HOST_WIDE_INT) -1 << width;
9092 /* ??? We don't know how zero / sign extension is handled, hence we
9093 can't go from a narrower to a wider mode. */
9094 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9095 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9096 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9097 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9098 GET_MODE_BITSIZE (INMODE))))
9101 reload_cse_move2add (first)
9107 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9108 reg_set_luid[i] = 0;
9110 move2add_last_label_luid = 0;
9112 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9116 if (GET_CODE (insn) == CODE_LABEL)
9118 move2add_last_label_luid = move2add_luid;
9119 /* We're going to increment move2add_luid twice after a
9120 label, so that we can use move2add_last_label_luid + 1 as
9121 the luid for constants. */
9125 if (! INSN_P (insn))
9127 pat = PATTERN (insn);
9128 /* For simplicity, we only perform this optimization on
9129 straightforward SETs. */
9130 if (GET_CODE (pat) == SET
9131 && GET_CODE (SET_DEST (pat)) == REG)
9133 rtx reg = SET_DEST (pat);
9134 int regno = REGNO (reg);
9135 rtx src = SET_SRC (pat);
9137 /* Check if we have valid information on the contents of this
9138 register in the mode of REG. */
9139 if (reg_set_luid[regno] > move2add_last_label_luid
9140 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9142 /* Try to transform (set (REGX) (CONST_INT A))
9144 (set (REGX) (CONST_INT B))
9146 (set (REGX) (CONST_INT A))
9148 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9150 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9153 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9155 - reg_offset[regno]));
9156 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9157 use (set (reg) (reg)) instead.
9158 We don't delete this insn, nor do we convert it into a
9159 note, to avoid losing register notes or the return
9160 value flag. jump2 already knowns how to get rid of
9162 if (new_src == const0_rtx)
9163 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9164 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9165 && have_add2_insn (GET_MODE (reg)))
9166 success = validate_change (insn, &PATTERN (insn),
9167 gen_add2_insn (reg, new_src), 0);
9168 reg_set_luid[regno] = move2add_luid;
9169 reg_mode[regno] = GET_MODE (reg);
9170 reg_offset[regno] = INTVAL (src);
9174 /* Try to transform (set (REGX) (REGY))
9175 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9178 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9181 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9183 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9184 else if (GET_CODE (src) == REG
9185 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9186 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9187 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9188 reg_mode[REGNO (src)]))
9190 rtx next = next_nonnote_insn (insn);
9193 set = single_set (next);
9195 && SET_DEST (set) == reg
9196 && GET_CODE (SET_SRC (set)) == PLUS
9197 && XEXP (SET_SRC (set), 0) == reg
9198 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9200 rtx src3 = XEXP (SET_SRC (set), 1);
9201 HOST_WIDE_INT added_offset = INTVAL (src3);
9202 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9203 HOST_WIDE_INT regno_offset = reg_offset[regno];
9204 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9210 if (new_src == const0_rtx)
9211 /* See above why we create (set (reg) (reg)) here. */
9213 = validate_change (next, &SET_SRC (set), reg, 0);
9214 else if ((rtx_cost (new_src, PLUS)
9215 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9216 && have_add2_insn (GET_MODE (reg)))
9218 = validate_change (next, &PATTERN (next),
9219 gen_add2_insn (reg, new_src), 0);
9222 /* INSN might be the first insn in a basic block
9223 if the preceding insn is a conditional jump
9224 or a possible-throwing call. */
9225 PUT_CODE (insn, NOTE);
9226 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9227 NOTE_SOURCE_FILE (insn) = 0;
9230 reg_mode[regno] = GET_MODE (reg);
9231 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9240 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9242 if (REG_NOTE_KIND (note) == REG_INC
9243 && GET_CODE (XEXP (note, 0)) == REG)
9245 /* Reset the information about this register. */
9246 int regno = REGNO (XEXP (note, 0));
9247 if (regno < FIRST_PSEUDO_REGISTER)
9248 reg_set_luid[regno] = 0;
9251 note_stores (PATTERN (insn), move2add_note_store, NULL);
9252 /* If this is a CALL_INSN, all call used registers are stored with
9254 if (GET_CODE (insn) == CALL_INSN)
9256 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9258 if (call_used_regs[i])
9259 /* Reset the information about this register. */
9260 reg_set_luid[i] = 0;
9266 /* SET is a SET or CLOBBER that sets DST.
9267 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9268 Called from reload_cse_move2add via note_stores. */
9271 move2add_note_store (dst, set, data)
9273 void *data ATTRIBUTE_UNUSED;
9275 unsigned int regno = 0;
9277 enum machine_mode mode = GET_MODE (dst);
9279 if (GET_CODE (dst) == SUBREG)
9281 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9282 GET_MODE (SUBREG_REG (dst)),
9285 dst = SUBREG_REG (dst);
9288 /* Some targets do argument pushes without adding REG_INC notes. */
9290 if (GET_CODE (dst) == MEM)
9292 dst = XEXP (dst, 0);
9293 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9294 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9295 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9298 if (GET_CODE (dst) != REG)
9301 regno += REGNO (dst);
9303 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9304 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9305 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9306 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9308 rtx src = SET_SRC (set);
9310 HOST_WIDE_INT offset;
9312 /* This may be different from mode, if SET_DEST (set) is a
9314 enum machine_mode dst_mode = GET_MODE (dst);
9316 switch (GET_CODE (src))
9319 if (GET_CODE (XEXP (src, 0)) == REG)
9321 base_reg = XEXP (src, 0);
9323 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9324 offset = INTVAL (XEXP (src, 1));
9325 else if (GET_CODE (XEXP (src, 1)) == REG
9326 && (reg_set_luid[REGNO (XEXP (src, 1))]
9327 > move2add_last_label_luid)
9328 && (MODES_OK_FOR_MOVE2ADD
9329 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9331 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9332 offset = reg_offset[REGNO (XEXP (src, 1))];
9333 /* Maybe the first register is known to be a
9335 else if (reg_set_luid[REGNO (base_reg)]
9336 > move2add_last_label_luid
9337 && (MODES_OK_FOR_MOVE2ADD
9338 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9339 && reg_base_reg[REGNO (base_reg)] < 0)
9341 offset = reg_offset[REGNO (base_reg)];
9342 base_reg = XEXP (src, 1);
9361 /* Start tracking the register as a constant. */
9362 reg_base_reg[regno] = -1;
9363 reg_offset[regno] = INTVAL (SET_SRC (set));
9364 /* We assign the same luid to all registers set to constants. */
9365 reg_set_luid[regno] = move2add_last_label_luid + 1;
9366 reg_mode[regno] = mode;
9371 /* Invalidate the contents of the register. */
9372 reg_set_luid[regno] = 0;
9376 base_regno = REGNO (base_reg);
9377 /* If information about the base register is not valid, set it
9378 up as a new base register, pretending its value is known
9379 starting from the current insn. */
9380 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9382 reg_base_reg[base_regno] = base_regno;
9383 reg_offset[base_regno] = 0;
9384 reg_set_luid[base_regno] = move2add_luid;
9385 reg_mode[base_regno] = mode;
9387 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9388 reg_mode[base_regno]))
9391 reg_mode[regno] = mode;
9393 /* Copy base information from our base register. */
9394 reg_set_luid[regno] = reg_set_luid[base_regno];
9395 reg_base_reg[regno] = reg_base_reg[base_regno];
9397 /* Compute the sum of the offsets or constants. */
9398 reg_offset[regno] = sext_for_mode (dst_mode,
9400 + reg_offset[base_regno]);
9404 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9406 for (i = regno; i < endregno; i++)
9407 /* Reset the information about this register. */
9408 reg_set_luid[i] = 0;
9414 add_auto_inc_notes (insn, x)
9418 enum rtx_code code = GET_CODE (x);
9422 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9425 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9429 /* Scan all the operand sub-expressions. */
9430 fmt = GET_RTX_FORMAT (code);
9431 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9434 add_auto_inc_notes (insn, XEXP (x, i));
9435 else if (fmt[i] == 'E')
9436 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9437 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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