1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Describes order of preference for putting regs into spill_regs.
219 Contains the numbers of all the hard regs, in order most preferred first.
220 This order is different for each function.
221 It is set up by order_regs_for_reload.
222 Empty elements at the end contain -1. */
223 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
225 /* Nonzero if indirect addressing is supported on the machine; this means
226 that spilling (REG n) does not require reloading it into a register in
227 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
228 value indicates the level of indirect addressing supported, e.g., two
229 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
231 static char spill_indirect_levels;
233 /* Nonzero if indirect addressing is supported when the innermost MEM is
234 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
235 which these are valid is the same as spill_indirect_levels, above. */
236 char indirect_symref_ok;
238 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
239 char double_reg_address_ok;
241 /* Record the stack slot for each spilled hard register. */
242 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
244 /* Width allocated so far for that stack slot. */
245 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
247 /* Record which pseudos needed to be spilled. */
248 static regset spilled_pseudos;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory used while processing one insn. */
279 char *reload_firstobj;
281 #define obstack_chunk_alloc xmalloc
282 #define obstack_chunk_free free
284 /* List of insn_chain instructions, one for every insn that reload needs to
286 struct insn_chain *reload_insn_chain;
289 extern tree current_function_decl;
291 extern union tree_node *current_function_decl;
294 /* List of all insns needing reloads. */
295 static struct insn_chain *insns_need_reload;
297 /* This structure is used to record information about register eliminations.
298 Each array entry describes one possible way of eliminating a register
299 in favor of another. If there is more than one way of eliminating a
300 particular register, the most preferred should be specified first. */
304 int from; /* Register number to be eliminated. */
305 int to; /* Register number used as replacement. */
306 int initial_offset; /* Initial difference between values. */
307 int can_eliminate; /* Non-zero if this elimination can be done. */
308 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
309 insns made by reload. */
310 int offset; /* Current offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 static struct elim_table * reg_eliminate = 0;
323 /* This is an intermediate structure to initialize the table. It has
324 exactly the members provided by ELIMINABLE_REGS. */
325 static struct elim_table_1
329 } reg_eliminate_1[] =
331 /* If a set of eliminable registers was specified, define the table from it.
332 Otherwise, default to the normal case of the frame pointer being
333 replaced by the stack pointer. */
335 #ifdef ELIMINABLE_REGS
338 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
341 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
343 /* Record the number of pending eliminations that have an offset not equal
344 to their initial offset. If non-zero, we use a new copy of each
345 replacement result in any insns encountered. */
346 int num_not_at_initial_offset;
348 /* Count the number of registers that we may be able to eliminate. */
349 static int num_eliminable;
350 /* And the number of registers that are equivalent to a constant that
351 can be eliminated to frame_pointer / arg_pointer + constant. */
352 static int num_eliminable_invariants;
354 /* For each label, we record the offset of each elimination. If we reach
355 a label by more than one path and an offset differs, we cannot do the
356 elimination. This information is indexed by the number of the label.
357 The first table is an array of flags that records whether we have yet
358 encountered a label and the second table is an array of arrays, one
359 entry in the latter array for each elimination. */
361 static char *offsets_known_at;
362 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
364 /* Number of labels in the current function. */
366 static int num_labels;
368 struct hard_reg_n_uses
374 static void maybe_fix_stack_asms PROTO((void));
375 static void calculate_needs_all_insns PROTO((int));
376 static void calculate_needs PROTO((struct insn_chain *));
377 static void find_reload_regs PROTO((struct insn_chain *chain,
379 static void find_tworeg_group PROTO((struct insn_chain *, int,
381 static void find_group PROTO((struct insn_chain *, int,
383 static int possible_group_p PROTO((struct insn_chain *, int));
384 static void count_possible_groups PROTO((struct insn_chain *, int));
385 static int modes_equiv_for_class_p PROTO((enum machine_mode,
388 static void delete_caller_save_insns PROTO((void));
390 static void spill_failure PROTO((rtx));
391 static void new_spill_reg PROTO((struct insn_chain *, int, int,
393 static void maybe_mark_pseudo_spilled PROTO((int));
394 static void delete_dead_insn PROTO((rtx));
395 static void alter_reg PROTO((int, int));
396 static void set_label_offsets PROTO((rtx, rtx, int));
397 static void check_eliminable_occurrences PROTO((rtx));
398 static void elimination_effects PROTO((rtx, enum machine_mode));
399 static int eliminate_regs_in_insn PROTO((rtx, int));
400 static void update_eliminable_offsets PROTO((void));
401 static void mark_not_eliminable PROTO((rtx, rtx, void *));
402 static void set_initial_elim_offsets PROTO((void));
403 static void verify_initial_elim_offsets PROTO((void));
404 static void set_initial_label_offsets PROTO((void));
405 static void set_offsets_for_label PROTO((rtx));
406 static void init_elim_table PROTO((void));
407 static void update_eliminables PROTO((HARD_REG_SET *));
408 static void spill_hard_reg PROTO((int, FILE *, int));
409 static int finish_spills PROTO((int, FILE *));
410 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
411 static void scan_paradoxical_subregs PROTO((rtx));
412 static int hard_reg_use_compare PROTO((const PTR, const PTR));
413 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
414 static void order_regs_for_reload PROTO((struct insn_chain *));
415 static void reload_as_needed PROTO((int));
416 static void forget_old_reloads_1 PROTO((rtx, rtx, void *));
417 static int reload_reg_class_lower PROTO((const PTR, const PTR));
418 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
420 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
422 static int reload_reg_free_p PROTO((int, int, enum reload_type));
423 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
424 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
425 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
427 static void choose_reload_regs_init PROTO((struct insn_chain *, rtx *));
428 static void choose_reload_regs PROTO((struct insn_chain *));
429 static void merge_assigned_reloads PROTO((rtx));
430 static void emit_reload_insns PROTO((struct insn_chain *));
431 static void delete_output_reload PROTO((rtx, int, int));
432 static void delete_address_reloads PROTO((rtx, rtx));
433 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
434 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
435 static int constraint_accepts_reg_p PROTO((const char *, rtx));
436 static void reload_cse_regs_1 PROTO((rtx));
437 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
438 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
439 static void reload_cse_invalidate_mem PROTO((rtx));
440 static void reload_cse_invalidate_rtx PROTO((rtx, rtx, void *));
441 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
442 static int reload_cse_noop_set_p PROTO((rtx, rtx));
443 static int reload_cse_simplify_set PROTO((rtx, rtx));
444 static int reload_cse_simplify_operands PROTO((rtx));
445 static void reload_cse_check_clobber PROTO((rtx, rtx, void *));
446 static void reload_cse_record_set PROTO((rtx, rtx));
447 static void reload_combine PROTO((void));
448 static void reload_combine_note_use PROTO((rtx *, rtx));
449 static void reload_combine_note_store PROTO((rtx, rtx, void *));
450 static void reload_cse_move2add PROTO((rtx));
451 static void move2add_note_store PROTO((rtx, rtx, void *));
453 static void add_auto_inc_notes PROTO((rtx, rtx));
455 static rtx gen_mode_int PROTO((enum machine_mode,
457 static void failed_reload PROTO((rtx, int));
458 static int set_reload_reg PROTO((int, int));
459 extern void dump_needs PROTO((struct insn_chain *, FILE *));
461 /* Initialize the reload pass once per compilation. */
468 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
469 Set spill_indirect_levels to the number of levels such addressing is
470 permitted, zero if it is not permitted at all. */
473 = gen_rtx_MEM (Pmode,
476 LAST_VIRTUAL_REGISTER + 1),
478 spill_indirect_levels = 0;
480 while (memory_address_p (QImode, tem))
482 spill_indirect_levels++;
483 tem = gen_rtx_MEM (Pmode, tem);
486 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
488 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
489 indirect_symref_ok = memory_address_p (QImode, tem);
491 /* See if reg+reg is a valid (and offsettable) address. */
493 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
495 tem = gen_rtx_PLUS (Pmode,
496 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
497 gen_rtx_REG (Pmode, i));
499 /* This way, we make sure that reg+reg is an offsettable address. */
500 tem = plus_constant (tem, 4);
502 if (memory_address_p (QImode, tem))
504 double_reg_address_ok = 1;
509 /* Initialize obstack for our rtl allocation. */
510 gcc_obstack_init (&reload_obstack);
511 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = (struct insn_chain *)
526 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
527 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
528 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
532 c = unused_insn_chains;
533 unused_insn_chains = c->next;
535 c->is_caller_save_insn = 0;
536 c->need_operand_change = 0;
542 /* Small utility function to set all regs in hard reg set TO which are
543 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (to, from)
550 EXECUTE_IF_SET_IN_REG_SET
551 (from, FIRST_PSEUDO_REGISTER, regno,
553 int r = reg_renumber[regno];
557 /* reload_combine uses the information from
558 BASIC_BLOCK->global_live_at_start, which might still
559 contain registers that have not actually been allocated
560 since they have an equivalence. */
561 if (! reload_completed)
566 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
568 SET_HARD_REG_BIT (*to, r + nregs);
573 /* Global variables used by reload and its subroutines. */
575 /* Set during calculate_needs if an insn needs register elimination. */
576 static int something_needs_elimination;
577 /* Set during calculate_needs if an insn needs an operand changed. */
578 int something_needs_operands_changed;
580 /* Nonzero means we couldn't get enough spill regs. */
583 /* Main entry point for the reload pass.
585 FIRST is the first insn of the function being compiled.
587 GLOBAL nonzero means we were called from global_alloc
588 and should attempt to reallocate any pseudoregs that we
589 displace from hard regs we will use for reloads.
590 If GLOBAL is zero, we do not have enough information to do that,
591 so any pseudo reg that is spilled must go to the stack.
593 DUMPFILE is the global-reg debugging dump file stream, or 0.
594 If it is nonzero, messages are written to it to describe
595 which registers are seized as reload regs, which pseudo regs
596 are spilled from them, and where the pseudo regs are reallocated to.
598 Return value is nonzero if reload failed
599 and we must not do any more for this function. */
602 reload (first, global, dumpfile)
609 register struct elim_table *ep;
611 /* The two pointers used to track the true location of the memory used
612 for label offsets. */
613 char *real_known_ptr = NULL_PTR;
614 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
616 /* Make sure even insns with volatile mem refs are recognizable. */
621 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
623 /* Make sure that the last insn in the chain
624 is not something that needs reloading. */
625 emit_note (NULL_PTR, NOTE_INSN_DELETED);
627 /* Enable find_equiv_reg to distinguish insns made by reload. */
628 reload_first_uid = get_max_uid ();
630 #ifdef SECONDARY_MEMORY_NEEDED
631 /* Initialize the secondary memory table. */
632 clear_secondary_mem ();
635 /* We don't have a stack slot for any spill reg yet. */
636 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
637 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
639 /* Initialize the save area information for caller-save, in case some
643 /* Compute which hard registers are now in use
644 as homes for pseudo registers.
645 This is done here rather than (eg) in global_alloc
646 because this point is reached even if not optimizing. */
647 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
650 /* A function that receives a nonlocal goto must save all call-saved
652 if (current_function_has_nonlocal_label)
653 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
655 if (! call_used_regs[i] && ! fixed_regs[i])
656 regs_ever_live[i] = 1;
659 /* Find all the pseudo registers that didn't get hard regs
660 but do have known equivalent constants or memory slots.
661 These include parameters (known equivalent to parameter slots)
662 and cse'd or loop-moved constant memory addresses.
664 Record constant equivalents in reg_equiv_constant
665 so they will be substituted by find_reloads.
666 Record memory equivalents in reg_mem_equiv so they can
667 be substituted eventually by altering the REG-rtx's. */
669 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
674 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
675 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
676 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
677 pseudo_forbidden_regs
678 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
680 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
682 CLEAR_HARD_REG_SET (bad_spill_regs_global);
684 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
685 Also find all paradoxical subregs and find largest such for each pseudo.
686 On machines with small register classes, record hard registers that
687 are used for user variables. These can never be used for spills.
688 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
689 caller-saved registers must be marked live. */
691 num_eliminable_invariants = 0;
692 for (insn = first; insn; insn = NEXT_INSN (insn))
694 rtx set = single_set (insn);
696 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
697 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
698 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
699 if (! call_used_regs[i])
700 regs_ever_live[i] = 1;
702 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
704 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
706 #ifdef LEGITIMATE_PIC_OPERAND_P
707 && (! function_invariant_p (XEXP (note, 0))
709 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
713 rtx x = XEXP (note, 0);
714 i = REGNO (SET_DEST (set));
715 if (i > LAST_VIRTUAL_REGISTER)
717 if (GET_CODE (x) == MEM)
719 /* If the operand is a PLUS, the MEM may be shared,
720 so make sure we have an unshared copy here. */
721 if (GET_CODE (XEXP (x, 0)) == PLUS)
724 reg_equiv_memory_loc[i] = x;
726 else if (function_invariant_p (x))
728 if (GET_CODE (x) == PLUS)
730 /* This is PLUS of frame pointer and a constant,
731 and might be shared. Unshare it. */
732 reg_equiv_constant[i] = copy_rtx (x);
733 num_eliminable_invariants++;
735 else if (x == frame_pointer_rtx
736 || x == arg_pointer_rtx)
738 reg_equiv_constant[i] = x;
739 num_eliminable_invariants++;
741 else if (LEGITIMATE_CONSTANT_P (x))
742 reg_equiv_constant[i] = x;
744 reg_equiv_memory_loc[i]
745 = force_const_mem (GET_MODE (SET_DEST (set)), x);
750 /* If this register is being made equivalent to a MEM
751 and the MEM is not SET_SRC, the equivalencing insn
752 is one with the MEM as a SET_DEST and it occurs later.
753 So don't mark this insn now. */
754 if (GET_CODE (x) != MEM
755 || rtx_equal_p (SET_SRC (set), x))
757 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
762 /* If this insn is setting a MEM from a register equivalent to it,
763 this is the equivalencing insn. */
764 else if (set && GET_CODE (SET_DEST (set)) == MEM
765 && GET_CODE (SET_SRC (set)) == REG
766 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
767 && rtx_equal_p (SET_DEST (set),
768 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
769 reg_equiv_init[REGNO (SET_SRC (set))]
770 = gen_rtx_INSN_LIST (VOIDmode, insn,
771 reg_equiv_init[REGNO (SET_SRC (set))]);
773 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
774 scan_paradoxical_subregs (PATTERN (insn));
779 num_labels = max_label_num () - get_first_label_num ();
781 /* Allocate the tables used to store offset information at labels. */
782 /* We used to use alloca here, but the size of what it would try to
783 allocate would occasionally cause it to exceed the stack limit and
784 cause a core dump. */
785 real_known_ptr = xmalloc (num_labels);
787 = (int (*)[NUM_ELIMINABLE_REGS])
788 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
790 offsets_known_at = real_known_ptr - get_first_label_num ();
792 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
794 /* Alter each pseudo-reg rtx to contain its hard reg number.
795 Assign stack slots to the pseudos that lack hard regs or equivalents.
796 Do not touch virtual registers. */
798 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
801 /* If we have some registers we think can be eliminated, scan all insns to
802 see if there is an insn that sets one of these registers to something
803 other than itself plus a constant. If so, the register cannot be
804 eliminated. Doing this scan here eliminates an extra pass through the
805 main reload loop in the most common case where register elimination
807 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
808 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
809 || GET_CODE (insn) == CALL_INSN)
810 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
812 maybe_fix_stack_asms ();
814 insns_need_reload = 0;
815 something_needs_elimination = 0;
817 /* Initialize to -1, which means take the first spill register. */
820 spilled_pseudos = ALLOCA_REG_SET ();
822 /* Spill any hard regs that we know we can't eliminate. */
823 CLEAR_HARD_REG_SET (used_spill_regs);
824 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
825 if (! ep->can_eliminate)
826 spill_hard_reg (ep->from, dumpfile, 1);
828 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
829 if (frame_pointer_needed)
830 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
832 finish_spills (global, dumpfile);
834 /* From now on, we may need to generate moves differently. We may also
835 allow modifications of insns which cause them to not be recognized.
836 Any such modifications will be cleaned up during reload itself. */
837 reload_in_progress = 1;
839 /* This loop scans the entire function each go-round
840 and repeats until one repetition spills no additional hard regs. */
843 int something_changed;
845 struct insn_chain *chain;
847 HOST_WIDE_INT starting_frame_size;
849 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
850 here because the stack size may be a part of the offset computation
851 for register elimination, and there might have been new stack slots
852 created in the last iteration of this loop. */
853 assign_stack_local (BLKmode, 0, 0);
855 starting_frame_size = get_frame_size ();
857 set_initial_elim_offsets ();
858 set_initial_label_offsets ();
860 /* For each pseudo register that has an equivalent location defined,
861 try to eliminate any eliminable registers (such as the frame pointer)
862 assuming initial offsets for the replacement register, which
865 If the resulting location is directly addressable, substitute
866 the MEM we just got directly for the old REG.
868 If it is not addressable but is a constant or the sum of a hard reg
869 and constant, it is probably not addressable because the constant is
870 out of range, in that case record the address; we will generate
871 hairy code to compute the address in a register each time it is
872 needed. Similarly if it is a hard register, but one that is not
873 valid as an address register.
875 If the location is not addressable, but does not have one of the
876 above forms, assign a stack slot. We have to do this to avoid the
877 potential of producing lots of reloads if, e.g., a location involves
878 a pseudo that didn't get a hard register and has an equivalent memory
879 location that also involves a pseudo that didn't get a hard register.
881 Perhaps at some point we will improve reload_when_needed handling
882 so this problem goes away. But that's very hairy. */
884 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
885 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
887 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
889 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
891 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
892 else if (CONSTANT_P (XEXP (x, 0))
893 || (GET_CODE (XEXP (x, 0)) == REG
894 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
895 || (GET_CODE (XEXP (x, 0)) == PLUS
896 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
897 && (REGNO (XEXP (XEXP (x, 0), 0))
898 < FIRST_PSEUDO_REGISTER)
899 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
900 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
903 /* Make a new stack slot. Then indicate that something
904 changed so we go back and recompute offsets for
905 eliminable registers because the allocation of memory
906 below might change some offset. reg_equiv_{mem,address}
907 will be set up for this pseudo on the next pass around
909 reg_equiv_memory_loc[i] = 0;
910 reg_equiv_init[i] = 0;
915 if (caller_save_needed)
918 /* If we allocated another stack slot, redo elimination bookkeeping. */
919 if (starting_frame_size != get_frame_size ())
922 if (caller_save_needed)
924 save_call_clobbered_regs ();
925 /* That might have allocated new insn_chain structures. */
926 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
929 calculate_needs_all_insns (global);
931 CLEAR_REG_SET (spilled_pseudos);
934 something_changed = 0;
936 /* If we allocated any new memory locations, make another pass
937 since it might have changed elimination offsets. */
938 if (starting_frame_size != get_frame_size ())
939 something_changed = 1;
942 HARD_REG_SET to_spill;
943 CLEAR_HARD_REG_SET (to_spill);
944 update_eliminables (&to_spill);
945 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
946 if (TEST_HARD_REG_BIT (to_spill, i))
948 spill_hard_reg (i, dumpfile, 1);
951 /* Regardless of the state of spills, if we previously had
952 a register that we thought we could eliminate, but no can
953 not eliminate, we must run another pass.
955 Consider pseudos which have an entry in reg_equiv_* which
956 reference an eliminable register. We must make another pass
957 to update reg_equiv_* so that we do not substitute in the
958 old value from when we thought the elimination could be
960 something_changed = 1;
964 CLEAR_HARD_REG_SET (used_spill_regs);
965 /* Try to satisfy the needs for each insn. */
966 for (chain = insns_need_reload; chain != 0;
967 chain = chain->next_need_reload)
968 find_reload_regs (chain, dumpfile);
973 if (insns_need_reload != 0 || did_spill)
974 something_changed |= finish_spills (global, dumpfile);
976 if (! something_changed)
979 if (caller_save_needed)
980 delete_caller_save_insns ();
983 /* If global-alloc was run, notify it of any register eliminations we have
986 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
987 if (ep->can_eliminate)
988 mark_elimination (ep->from, ep->to);
990 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
991 If that insn didn't set the register (i.e., it copied the register to
992 memory), just delete that insn instead of the equivalencing insn plus
993 anything now dead. If we call delete_dead_insn on that insn, we may
994 delete the insn that actually sets the register if the register dies
995 there and that is incorrect. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
999 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1002 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1004 rtx equiv_insn = XEXP (list, 0);
1005 if (GET_CODE (equiv_insn) == NOTE)
1007 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1008 delete_dead_insn (equiv_insn);
1011 PUT_CODE (equiv_insn, NOTE);
1012 NOTE_SOURCE_FILE (equiv_insn) = 0;
1013 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1019 /* Use the reload registers where necessary
1020 by generating move instructions to move the must-be-register
1021 values into or out of the reload registers. */
1023 if (insns_need_reload != 0 || something_needs_elimination
1024 || something_needs_operands_changed)
1026 int old_frame_size = get_frame_size ();
1028 reload_as_needed (global);
1030 if (old_frame_size != get_frame_size ())
1034 verify_initial_elim_offsets ();
1037 /* If we were able to eliminate the frame pointer, show that it is no
1038 longer live at the start of any basic block. If it ls live by
1039 virtue of being in a pseudo, that pseudo will be marked live
1040 and hence the frame pointer will be known to be live via that
1043 if (! frame_pointer_needed)
1044 for (i = 0; i < n_basic_blocks; i++)
1045 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1046 HARD_FRAME_POINTER_REGNUM);
1048 /* Come here (with failure set nonzero) if we can't get enough spill regs
1049 and we decide not to abort about it. */
1052 reload_in_progress = 0;
1054 /* Now eliminate all pseudo regs by modifying them into
1055 their equivalent memory references.
1056 The REG-rtx's for the pseudos are modified in place,
1057 so all insns that used to refer to them now refer to memory.
1059 For a reg that has a reg_equiv_address, all those insns
1060 were changed by reloading so that no insns refer to it any longer;
1061 but the DECL_RTL of a variable decl may refer to it,
1062 and if so this causes the debugging info to mention the variable. */
1064 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1069 int is_readonly = 0;
1071 if (reg_equiv_memory_loc[i])
1073 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1074 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1075 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1078 if (reg_equiv_mem[i])
1079 addr = XEXP (reg_equiv_mem[i], 0);
1081 if (reg_equiv_address[i])
1082 addr = reg_equiv_address[i];
1086 if (reg_renumber[i] < 0)
1088 rtx reg = regno_reg_rtx[i];
1089 PUT_CODE (reg, MEM);
1090 XEXP (reg, 0) = addr;
1091 REG_USERVAR_P (reg) = 0;
1092 RTX_UNCHANGING_P (reg) = is_readonly;
1093 MEM_IN_STRUCT_P (reg) = in_struct;
1094 MEM_SCALAR_P (reg) = is_scalar;
1095 /* We have no alias information about this newly created
1097 MEM_ALIAS_SET (reg) = 0;
1099 else if (reg_equiv_mem[i])
1100 XEXP (reg_equiv_mem[i], 0) = addr;
1104 /* We must set reload_completed now since the cleanup_subreg_operands call
1105 below will re-recognize each insn and reload may have generated insns
1106 which are only valid during and after reload. */
1107 reload_completed = 1;
1109 /* Make a pass over all the insns and delete all USEs which we inserted
1110 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1111 notes. Delete all CLOBBER insns that don't refer to the return value
1112 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1113 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1114 and regenerate REG_INC notes that may have been moved around. */
1116 for (insn = first; insn; insn = NEXT_INSN (insn))
1117 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1121 if ((GET_CODE (PATTERN (insn)) == USE
1122 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1123 || (GET_CODE (PATTERN (insn)) == CLOBBER
1124 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1125 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1127 PUT_CODE (insn, NOTE);
1128 NOTE_SOURCE_FILE (insn) = 0;
1129 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1133 pnote = ®_NOTES (insn);
1136 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1137 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1138 || REG_NOTE_KIND (*pnote) == REG_INC
1139 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1140 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1141 *pnote = XEXP (*pnote, 1);
1143 pnote = &XEXP (*pnote, 1);
1147 add_auto_inc_notes (insn, PATTERN (insn));
1150 /* And simplify (subreg (reg)) if it appears as an operand. */
1151 cleanup_subreg_operands (insn);
1154 /* If we are doing stack checking, give a warning if this function's
1155 frame size is larger than we expect. */
1156 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1158 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1159 static int verbose_warned = 0;
1161 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1162 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1163 size += UNITS_PER_WORD;
1165 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1167 warning ("frame size too large for reliable stack checking");
1168 if (! verbose_warned)
1170 warning ("try reducing the number of local variables");
1176 /* Indicate that we no longer have known memory locations or constants. */
1177 if (reg_equiv_constant)
1178 free (reg_equiv_constant);
1179 reg_equiv_constant = 0;
1180 if (reg_equiv_memory_loc)
1181 free (reg_equiv_memory_loc);
1182 reg_equiv_memory_loc = 0;
1185 free (real_known_ptr);
1189 free (reg_equiv_mem);
1190 free (reg_equiv_init);
1191 free (reg_equiv_address);
1192 free (reg_max_ref_width);
1193 free (reg_old_renumber);
1194 free (pseudo_previous_regs);
1195 free (pseudo_forbidden_regs);
1197 FREE_REG_SET (spilled_pseudos);
1199 CLEAR_HARD_REG_SET (used_spill_regs);
1200 for (i = 0; i < n_spills; i++)
1201 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1203 /* Free all the insn_chain structures at once. */
1204 obstack_free (&reload_obstack, reload_startobj);
1205 unused_insn_chains = 0;
1210 /* Yet another special case. Unfortunately, reg-stack forces people to
1211 write incorrect clobbers in asm statements. These clobbers must not
1212 cause the register to appear in bad_spill_regs, otherwise we'll call
1213 fatal_insn later. We clear the corresponding regnos in the live
1214 register sets to avoid this.
1215 The whole thing is rather sick, I'm afraid. */
1217 maybe_fix_stack_asms ()
1220 const char *constraints[MAX_RECOG_OPERANDS];
1221 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1222 struct insn_chain *chain;
1224 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1227 HARD_REG_SET clobbered, allowed;
1230 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1231 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1233 pat = PATTERN (chain->insn);
1234 if (GET_CODE (pat) != PARALLEL)
1237 CLEAR_HARD_REG_SET (clobbered);
1238 CLEAR_HARD_REG_SET (allowed);
1240 /* First, make a mask of all stack regs that are clobbered. */
1241 for (i = 0; i < XVECLEN (pat, 0); i++)
1243 rtx t = XVECEXP (pat, 0, i);
1244 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1245 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1248 /* Get the operand values and constraints out of the insn. */
1249 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1250 constraints, operand_mode);
1252 /* For every operand, see what registers are allowed. */
1253 for (i = 0; i < noperands; i++)
1255 const char *p = constraints[i];
1256 /* For every alternative, we compute the class of registers allowed
1257 for reloading in CLS, and merge its contents into the reg set
1259 int cls = (int) NO_REGS;
1265 if (c == '\0' || c == ',' || c == '#')
1267 /* End of one alternative - mark the regs in the current
1268 class, and reset the class. */
1269 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1274 } while (c != '\0' && c != ',');
1282 case '=': case '+': case '*': case '%': case '?': case '!':
1283 case '0': case '1': case '2': case '3': case '4': case 'm':
1284 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1285 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1286 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1288 #ifdef EXTRA_CONSTRAINT
1289 case 'Q': case 'R': case 'S': case 'T': case 'U':
1294 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1299 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1303 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1308 /* Those of the registers which are clobbered, but allowed by the
1309 constraints, must be usable as reload registers. So clear them
1310 out of the life information. */
1311 AND_HARD_REG_SET (allowed, clobbered);
1312 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1313 if (TEST_HARD_REG_BIT (allowed, i))
1315 CLEAR_REGNO_REG_SET (chain->live_before, i);
1316 CLEAR_REGNO_REG_SET (chain->live_after, i);
1324 /* Walk the chain of insns, and determine for each whether it needs reloads
1325 and/or eliminations. Build the corresponding insns_need_reload list, and
1326 set something_needs_elimination as appropriate. */
1328 calculate_needs_all_insns (global)
1331 struct insn_chain **pprev_reload = &insns_need_reload;
1332 struct insn_chain *chain;
1334 something_needs_elimination = 0;
1336 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1338 rtx insn = chain->insn;
1340 /* Clear out the shortcuts, in case they were set last time through. */
1341 chain->need_elim = 0;
1342 chain->need_reload = 0;
1343 chain->need_operand_change = 0;
1345 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1346 include REG_LABEL), we need to see what effects this has on the
1347 known offsets at labels. */
1349 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1350 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1351 && REG_NOTES (insn) != 0))
1352 set_label_offsets (insn, insn, 0);
1354 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1356 rtx old_body = PATTERN (insn);
1357 int old_code = INSN_CODE (insn);
1358 rtx old_notes = REG_NOTES (insn);
1359 int did_elimination = 0;
1360 int operands_changed = 0;
1361 rtx set = single_set (insn);
1363 /* Skip insns that only set an equivalence. */
1364 if (set && GET_CODE (SET_DEST (set)) == REG
1365 && reg_renumber[REGNO (SET_DEST (set))] < 0
1366 && reg_equiv_constant[REGNO (SET_DEST (set))])
1369 /* If needed, eliminate any eliminable registers. */
1370 if (num_eliminable || num_eliminable_invariants)
1371 did_elimination = eliminate_regs_in_insn (insn, 0);
1373 /* Analyze the instruction. */
1374 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1375 global, spill_reg_order);
1377 /* If a no-op set needs more than one reload, this is likely
1378 to be something that needs input address reloads. We
1379 can't get rid of this cleanly later, and it is of no use
1380 anyway, so discard it now.
1381 We only do this when expensive_optimizations is enabled,
1382 since this complements reload inheritance / output
1383 reload deletion, and it can make debugging harder. */
1384 if (flag_expensive_optimizations && n_reloads > 1)
1386 rtx set = single_set (insn);
1388 && SET_SRC (set) == SET_DEST (set)
1389 && GET_CODE (SET_SRC (set)) == REG
1390 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1392 PUT_CODE (insn, NOTE);
1393 NOTE_SOURCE_FILE (insn) = 0;
1394 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1399 update_eliminable_offsets ();
1401 /* Remember for later shortcuts which insns had any reloads or
1402 register eliminations. */
1403 chain->need_elim = did_elimination;
1404 chain->need_reload = n_reloads > 0;
1405 chain->need_operand_change = operands_changed;
1407 /* Discard any register replacements done. */
1408 if (did_elimination)
1410 obstack_free (&reload_obstack, reload_firstobj);
1411 PATTERN (insn) = old_body;
1412 INSN_CODE (insn) = old_code;
1413 REG_NOTES (insn) = old_notes;
1414 something_needs_elimination = 1;
1417 something_needs_operands_changed |= operands_changed;
1421 *pprev_reload = chain;
1422 pprev_reload = &chain->next_need_reload;
1424 calculate_needs (chain);
1431 /* Compute the most additional registers needed by one instruction,
1432 given by CHAIN. Collect information separately for each class of regs.
1434 To compute the number of reload registers of each class needed for an
1435 insn, we must simulate what choose_reload_regs can do. We do this by
1436 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1437 reloads are used in both. The input part uses those reloads,
1438 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1439 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1440 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1442 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1443 which are live for the entire output portion, and the maximum of all the
1444 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1446 The total number of registers needed is the maximum of the
1447 inputs and outputs. */
1450 calculate_needs (chain)
1451 struct insn_chain *chain;
1455 /* Each `struct needs' corresponds to one RELOAD_... type. */
1459 struct needs output;
1461 struct needs other_addr;
1462 struct needs op_addr;
1463 struct needs op_addr_reload;
1464 struct needs in_addr[MAX_RECOG_OPERANDS];
1465 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1466 struct needs out_addr[MAX_RECOG_OPERANDS];
1467 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1470 bzero ((char *) chain->group_size, sizeof chain->group_size);
1471 for (i = 0; i < N_REG_CLASSES; i++)
1472 chain->group_mode[i] = VOIDmode;
1473 bzero ((char *) &insn_needs, sizeof insn_needs);
1475 /* Count each reload once in every class
1476 containing the reload's own class. */
1478 for (i = 0; i < n_reloads; i++)
1480 register enum reg_class *p;
1481 enum reg_class class = rld[i].class;
1483 enum machine_mode mode;
1484 struct needs *this_needs;
1486 /* Don't count the dummy reloads, for which one of the
1487 regs mentioned in the insn can be used for reloading.
1488 Don't count optional reloads.
1489 Don't count reloads that got combined with others. */
1490 if (rld[i].reg_rtx != 0
1491 || rld[i].optional != 0
1492 || (rld[i].out == 0 && rld[i].in == 0
1493 && ! rld[i].secondary_p))
1497 size = rld[i].nregs;
1499 /* Decide which time-of-use to count this reload for. */
1500 switch (rld[i].when_needed)
1503 this_needs = &insn_needs.other;
1505 case RELOAD_FOR_INPUT:
1506 this_needs = &insn_needs.input;
1508 case RELOAD_FOR_OUTPUT:
1509 this_needs = &insn_needs.output;
1511 case RELOAD_FOR_INSN:
1512 this_needs = &insn_needs.insn;
1514 case RELOAD_FOR_OTHER_ADDRESS:
1515 this_needs = &insn_needs.other_addr;
1517 case RELOAD_FOR_INPUT_ADDRESS:
1518 this_needs = &insn_needs.in_addr[rld[i].opnum];
1520 case RELOAD_FOR_INPADDR_ADDRESS:
1521 this_needs = &insn_needs.in_addr_addr[rld[i].opnum];
1523 case RELOAD_FOR_OUTPUT_ADDRESS:
1524 this_needs = &insn_needs.out_addr[rld[i].opnum];
1526 case RELOAD_FOR_OUTADDR_ADDRESS:
1527 this_needs = &insn_needs.out_addr_addr[rld[i].opnum];
1529 case RELOAD_FOR_OPERAND_ADDRESS:
1530 this_needs = &insn_needs.op_addr;
1532 case RELOAD_FOR_OPADDR_ADDR:
1533 this_needs = &insn_needs.op_addr_reload;
1541 enum machine_mode other_mode, allocate_mode;
1543 /* Count number of groups needed separately from
1544 number of individual regs needed. */
1545 this_needs->groups[(int) class]++;
1546 p = reg_class_superclasses[(int) class];
1547 while (*p != LIM_REG_CLASSES)
1548 this_needs->groups[(int) *p++]++;
1550 /* Record size and mode of a group of this class. */
1551 /* If more than one size group is needed,
1552 make all groups the largest needed size. */
1553 if (chain->group_size[(int) class] < size)
1555 other_mode = chain->group_mode[(int) class];
1556 allocate_mode = mode;
1558 chain->group_size[(int) class] = size;
1559 chain->group_mode[(int) class] = mode;
1564 allocate_mode = chain->group_mode[(int) class];
1567 /* Crash if two dissimilar machine modes both need
1568 groups of consecutive regs of the same class. */
1570 if (other_mode != VOIDmode && other_mode != allocate_mode
1571 && ! modes_equiv_for_class_p (allocate_mode,
1573 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1578 this_needs->regs[(unsigned char)rld[i].nongroup][(int) class] += 1;
1579 p = reg_class_superclasses[(int) class];
1580 while (*p != LIM_REG_CLASSES)
1581 this_needs->regs[(unsigned char)rld[i].nongroup][(int) *p++] += 1;
1587 /* All reloads have been counted for this insn;
1588 now merge the various times of use.
1589 This sets insn_needs, etc., to the maximum total number
1590 of registers needed at any point in this insn. */
1592 for (i = 0; i < N_REG_CLASSES; i++)
1594 int j, in_max, out_max;
1596 /* Compute normal and nongroup needs. */
1597 for (j = 0; j <= 1; j++)
1600 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1602 in_max = MAX (in_max,
1603 (insn_needs.in_addr[k].regs[j][i]
1604 + insn_needs.in_addr_addr[k].regs[j][i]));
1605 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1606 out_max = MAX (out_max,
1607 insn_needs.out_addr_addr[k].regs[j][i]);
1610 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1611 and operand addresses but not things used to reload
1612 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1613 don't conflict with things needed to reload inputs or
1616 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1617 insn_needs.op_addr_reload.regs[j][i]),
1620 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1622 insn_needs.input.regs[j][i]
1623 = MAX (insn_needs.input.regs[j][i]
1624 + insn_needs.op_addr.regs[j][i]
1625 + insn_needs.insn.regs[j][i],
1626 in_max + insn_needs.input.regs[j][i]);
1628 insn_needs.output.regs[j][i] += out_max;
1629 insn_needs.other.regs[j][i]
1630 += MAX (MAX (insn_needs.input.regs[j][i],
1631 insn_needs.output.regs[j][i]),
1632 insn_needs.other_addr.regs[j][i]);
1636 /* Now compute group needs. */
1637 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1639 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1640 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1641 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1642 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1645 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1646 insn_needs.op_addr_reload.groups[i]),
1648 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1650 insn_needs.input.groups[i]
1651 = MAX (insn_needs.input.groups[i]
1652 + insn_needs.op_addr.groups[i]
1653 + insn_needs.insn.groups[i],
1654 in_max + insn_needs.input.groups[i]);
1656 insn_needs.output.groups[i] += out_max;
1657 insn_needs.other.groups[i]
1658 += MAX (MAX (insn_needs.input.groups[i],
1659 insn_needs.output.groups[i]),
1660 insn_needs.other_addr.groups[i]);
1663 /* Record the needs for later. */
1664 chain->need = insn_needs.other;
1667 /* Find a group of exactly 2 registers.
1669 First try to fill out the group by spilling a single register which
1670 would allow completion of the group.
1672 Then try to create a new group from a pair of registers, neither of
1673 which are explicitly used.
1675 Then try to create a group from any pair of registers. */
1678 find_tworeg_group (chain, class, dumpfile)
1679 struct insn_chain *chain;
1684 /* First, look for a register that will complete a group. */
1685 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1689 j = potential_reload_regs[i];
1690 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1691 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1692 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1693 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1694 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1695 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1696 /* We don't want one part of another group.
1697 We could get "two groups" that overlap! */
1698 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1699 || (j < FIRST_PSEUDO_REGISTER - 1
1700 && (other = j + 1, spill_reg_order[other] >= 0)
1701 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1702 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1703 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1704 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1705 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1707 register enum reg_class *p;
1709 /* We have found one that will complete a group,
1710 so count off one group as provided. */
1711 chain->need.groups[class]--;
1712 p = reg_class_superclasses[class];
1713 while (*p != LIM_REG_CLASSES)
1715 if (chain->group_size [(int) *p] <= chain->group_size [class])
1716 chain->need.groups[(int) *p]--;
1720 /* Indicate both these regs are part of a group. */
1721 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1722 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1726 /* We can't complete a group, so start one. */
1727 if (i == FIRST_PSEUDO_REGISTER)
1728 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1731 j = potential_reload_regs[i];
1732 /* Verify that J+1 is a potential reload reg. */
1733 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1734 if (potential_reload_regs[k] == j + 1)
1736 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1737 && k < FIRST_PSEUDO_REGISTER
1738 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1739 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1740 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1741 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1742 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1743 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1747 /* I should be the index in potential_reload_regs
1748 of the new reload reg we have found. */
1750 new_spill_reg (chain, i, class, 0, dumpfile);
1753 /* Find a group of more than 2 registers.
1754 Look for a sufficient sequence of unspilled registers, and spill them all
1758 find_group (chain, class, dumpfile)
1759 struct insn_chain *chain;
1765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1767 int j = potential_reload_regs[i];
1770 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1771 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1774 /* Check each reg in the sequence. */
1775 for (k = 0; k < chain->group_size[class]; k++)
1776 if (! (spill_reg_order[j + k] < 0
1777 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1778 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1780 /* We got a full sequence, so spill them all. */
1781 if (k == chain->group_size[class])
1783 register enum reg_class *p;
1784 for (k = 0; k < chain->group_size[class]; k++)
1787 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1788 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1789 if (potential_reload_regs[idx] == j + k)
1791 new_spill_reg (chain, idx, class, 0, dumpfile);
1794 /* We have found one that will complete a group,
1795 so count off one group as provided. */
1796 chain->need.groups[class]--;
1797 p = reg_class_superclasses[class];
1798 while (*p != LIM_REG_CLASSES)
1800 if (chain->group_size [(int) *p]
1801 <= chain->group_size [class])
1802 chain->need.groups[(int) *p]--;
1809 /* There are no groups left. */
1810 spill_failure (chain->insn);
1814 /* If pseudo REG conflicts with one of our reload registers, mark it as
1817 maybe_mark_pseudo_spilled (reg)
1821 int r = reg_renumber[reg];
1826 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1827 for (i = 0; i < n_spills; i++)
1828 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1830 SET_REGNO_REG_SET (spilled_pseudos, reg);
1835 /* Find more reload regs to satisfy the remaining need of an insn, which
1837 Do it by ascending class number, since otherwise a reg
1838 might be spilled for a big class and might fail to count
1839 for a smaller class even though it belongs to that class.
1841 Count spilled regs in `spills', and add entries to
1842 `spill_regs' and `spill_reg_order'.
1844 ??? Note there is a problem here.
1845 When there is a need for a group in a high-numbered class,
1846 and also need for non-group regs that come from a lower class,
1847 the non-group regs are chosen first. If there aren't many regs,
1848 they might leave no room for a group.
1850 This was happening on the 386. To fix it, we added the code
1851 that calls possible_group_p, so that the lower class won't
1852 break up the last possible group.
1854 Really fixing the problem would require changes above
1855 in counting the regs already spilled, and in choose_reload_regs.
1856 It might be hard to avoid introducing bugs there. */
1859 find_reload_regs (chain, dumpfile)
1860 struct insn_chain *chain;
1864 short *group_needs = chain->need.groups;
1865 short *simple_needs = chain->need.regs[0];
1866 short *nongroup_needs = chain->need.regs[1];
1869 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1871 /* Compute the order of preference for hard registers to spill.
1872 Store them by decreasing preference in potential_reload_regs. */
1874 order_regs_for_reload (chain);
1876 /* So far, no hard regs have been spilled. */
1878 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1879 spill_reg_order[i] = -1;
1881 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1882 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1883 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1885 for (class = 0; class < N_REG_CLASSES; class++)
1887 /* First get the groups of registers.
1888 If we got single registers first, we might fragment
1890 while (group_needs[class] > 0)
1892 /* If any single spilled regs happen to form groups,
1893 count them now. Maybe we don't really need
1894 to spill another group. */
1895 count_possible_groups (chain, class);
1897 if (group_needs[class] <= 0)
1900 /* Groups of size 2, the only groups used on most machines,
1901 are treated specially. */
1902 if (chain->group_size[class] == 2)
1903 find_tworeg_group (chain, class, dumpfile);
1905 find_group (chain, class, dumpfile);
1910 /* Now similarly satisfy all need for single registers. */
1912 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1914 /* If we spilled enough regs, but they weren't counted
1915 against the non-group need, see if we can count them now.
1916 If so, we can avoid some actual spilling. */
1917 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1918 for (i = 0; i < n_spills; i++)
1920 int regno = spill_regs[i];
1921 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1922 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1923 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1924 && nongroup_needs[class] > 0)
1926 register enum reg_class *p;
1928 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1929 nongroup_needs[class]--;
1930 p = reg_class_superclasses[class];
1931 while (*p != LIM_REG_CLASSES)
1932 nongroup_needs[(int) *p++]--;
1936 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1939 /* Consider the potential reload regs that aren't
1940 yet in use as reload regs, in order of preference.
1941 Find the most preferred one that's in this class. */
1943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1945 int regno = potential_reload_regs[i];
1947 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1948 /* If this reg will not be available for groups,
1949 pick one that does not foreclose possible groups.
1950 This is a kludge, and not very general,
1951 but it should be sufficient to make the 386 work,
1952 and the problem should not occur on machines with
1954 && (nongroup_needs[class] == 0
1955 || possible_group_p (chain, regno)))
1959 /* If we couldn't get a register, try to get one even if we
1960 might foreclose possible groups. This may cause problems
1961 later, but that's better than aborting now, since it is
1962 possible that we will, in fact, be able to form the needed
1963 group even with this allocation. */
1965 if (i >= FIRST_PSEUDO_REGISTER
1966 && asm_noperands (chain->insn) < 0)
1967 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1968 if (potential_reload_regs[i] >= 0
1969 && TEST_HARD_REG_BIT (reg_class_contents[class],
1970 potential_reload_regs[i]))
1973 /* I should be the index in potential_reload_regs
1974 of the new reload reg we have found. */
1976 new_spill_reg (chain, i, class, 1, dumpfile);
1982 /* We know which hard regs to use, now mark the pseudos that live in them
1983 as needing to be kicked out. */
1984 EXECUTE_IF_SET_IN_REG_SET
1985 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1987 maybe_mark_pseudo_spilled (i);
1989 EXECUTE_IF_SET_IN_REG_SET
1990 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1992 maybe_mark_pseudo_spilled (i);
1995 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1999 dump_needs (chain, dumpfile)
2000 struct insn_chain *chain;
2003 static const char * const reg_class_names[] = REG_CLASS_NAMES;
2005 struct needs *n = &chain->need;
2007 for (i = 0; i < N_REG_CLASSES; i++)
2009 if (n->regs[i][0] > 0)
2011 ";; Need %d reg%s of class %s.\n",
2012 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2013 reg_class_names[i]);
2014 if (n->regs[i][1] > 0)
2016 ";; Need %d nongroup reg%s of class %s.\n",
2017 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2018 reg_class_names[i]);
2019 if (n->groups[i] > 0)
2021 ";; Need %d group%s (%smode) of class %s.\n",
2022 n->groups[i], n->groups[i] == 1 ? "" : "s",
2023 GET_MODE_NAME(chain->group_mode[i]),
2024 reg_class_names[i]);
2028 /* Delete all insns that were inserted by emit_caller_save_insns during
2031 delete_caller_save_insns ()
2033 struct insn_chain *c = reload_insn_chain;
2037 while (c != 0 && c->is_caller_save_insn)
2039 struct insn_chain *next = c->next;
2042 if (insn == BLOCK_HEAD (c->block))
2043 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2044 if (insn == BLOCK_END (c->block))
2045 BLOCK_END (c->block) = PREV_INSN (insn);
2046 if (c == reload_insn_chain)
2047 reload_insn_chain = next;
2049 if (NEXT_INSN (insn) != 0)
2050 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2051 if (PREV_INSN (insn) != 0)
2052 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2055 next->prev = c->prev;
2057 c->prev->next = next;
2058 c->next = unused_insn_chains;
2059 unused_insn_chains = c;
2067 /* Nonzero if, after spilling reg REGNO for non-groups,
2068 it will still be possible to find a group if we still need one. */
2071 possible_group_p (chain, regno)
2072 struct insn_chain *chain;
2076 int class = (int) NO_REGS;
2078 for (i = 0; i < (int) N_REG_CLASSES; i++)
2079 if (chain->need.groups[i] > 0)
2085 if (class == (int) NO_REGS)
2088 /* Consider each pair of consecutive registers. */
2089 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2091 /* Ignore pairs that include reg REGNO. */
2092 if (i == regno || i + 1 == regno)
2095 /* Ignore pairs that are outside the class that needs the group.
2096 ??? Here we fail to handle the case where two different classes
2097 independently need groups. But this never happens with our
2098 current machine descriptions. */
2099 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2100 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2103 /* A pair of consecutive regs we can still spill does the trick. */
2104 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2105 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2106 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2109 /* A pair of one already spilled and one we can spill does it
2110 provided the one already spilled is not otherwise reserved. */
2111 if (spill_reg_order[i] < 0
2112 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2113 && spill_reg_order[i + 1] >= 0
2114 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2115 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2117 if (spill_reg_order[i + 1] < 0
2118 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2119 && spill_reg_order[i] >= 0
2120 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2121 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2128 /* Count any groups of CLASS that can be formed from the registers recently
2132 count_possible_groups (chain, class)
2133 struct insn_chain *chain;
2139 /* Now find all consecutive groups of spilled registers
2140 and mark each group off against the need for such groups.
2141 But don't count them against ordinary need, yet. */
2143 if (chain->group_size[class] == 0)
2146 CLEAR_HARD_REG_SET (new);
2148 /* Make a mask of all the regs that are spill regs in class I. */
2149 for (i = 0; i < n_spills; i++)
2151 int regno = spill_regs[i];
2153 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2154 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2155 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2156 SET_HARD_REG_BIT (new, regno);
2159 /* Find each consecutive group of them. */
2160 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2161 if (TEST_HARD_REG_BIT (new, i)
2162 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2163 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2165 for (j = 1; j < chain->group_size[class]; j++)
2166 if (! TEST_HARD_REG_BIT (new, i + j))
2169 if (j == chain->group_size[class])
2171 /* We found a group. Mark it off against this class's need for
2172 groups, and against each superclass too. */
2173 register enum reg_class *p;
2175 chain->need.groups[class]--;
2176 p = reg_class_superclasses[class];
2177 while (*p != LIM_REG_CLASSES)
2179 if (chain->group_size [(int) *p] <= chain->group_size [class])
2180 chain->need.groups[(int) *p]--;
2184 /* Don't count these registers again. */
2185 for (j = 0; j < chain->group_size[class]; j++)
2186 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2189 /* Skip to the last reg in this group. When i is incremented above,
2190 it will then point to the first reg of the next possible group. */
2195 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2196 another mode that needs to be reloaded for the same register class CLASS.
2197 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2198 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2200 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2201 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2202 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2203 causes unnecessary failures on machines requiring alignment of register
2204 groups when the two modes are different sizes, because the larger mode has
2205 more strict alignment rules than the smaller mode. */
2208 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2209 enum machine_mode allocate_mode, other_mode;
2210 enum reg_class class;
2213 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2215 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2216 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2217 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2223 /* Handle the failure to find a register to spill.
2224 INSN should be one of the insns which needed this particular spill reg. */
2227 spill_failure (insn)
2230 if (asm_noperands (PATTERN (insn)) >= 0)
2231 error_for_asm (insn, "`asm' needs too many reloads");
2233 fatal_insn ("Unable to find a register to spill.", insn);
2236 /* Add a new register to the tables of available spill-registers.
2237 CHAIN is the insn for which the register will be used; we decrease the
2239 I is the index of this register in potential_reload_regs.
2240 CLASS is the regclass whose need is being satisfied.
2241 NONGROUP is 0 if this register is part of a group.
2242 DUMPFILE is the same as the one that `reload' got. */
2245 new_spill_reg (chain, i, class, nongroup, dumpfile)
2246 struct insn_chain *chain;
2252 register enum reg_class *p;
2253 int regno = potential_reload_regs[i];
2255 if (i >= FIRST_PSEUDO_REGISTER)
2257 spill_failure (chain->insn);
2262 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2264 static const char * const reg_class_names[] = REG_CLASS_NAMES;
2266 if (asm_noperands (PATTERN (chain->insn)) < 0)
2268 /* The error message is still correct - we know only that it wasn't
2269 an asm statement that caused the problem, but one of the global
2270 registers declared by the users might have screwed us. */
2271 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2272 regno, reg_names[regno], reg_class_names[class]);
2273 error ("This may be due to a compiler bug or to impossible asm");
2274 error ("statements or clauses.");
2275 fatal_insn ("This is the instruction:", chain->insn);
2277 error_for_asm (chain->insn, "Invalid `asm' statement:");
2278 error_for_asm (chain->insn,
2279 "fixed or forbidden register %d (%s) was spilled for class %s.",
2280 regno, reg_names[regno], reg_class_names[class]);
2285 /* Make reg REGNO an additional reload reg. */
2287 potential_reload_regs[i] = -1;
2288 spill_regs[n_spills] = regno;
2289 spill_reg_order[regno] = n_spills;
2291 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2292 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2294 /* Clear off the needs we just satisfied. */
2296 chain->need.regs[0][class]--;
2297 p = reg_class_superclasses[class];
2298 while (*p != LIM_REG_CLASSES)
2299 chain->need.regs[0][(int) *p++]--;
2301 if (nongroup && chain->need.regs[1][class] > 0)
2303 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2304 chain->need.regs[1][class]--;
2305 p = reg_class_superclasses[class];
2306 while (*p != LIM_REG_CLASSES)
2307 chain->need.regs[1][(int) *p++]--;
2313 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2314 data that is dead in INSN. */
2317 delete_dead_insn (insn)
2320 rtx prev = prev_real_insn (insn);
2323 /* If the previous insn sets a register that dies in our insn, delete it
2325 if (prev && GET_CODE (PATTERN (prev)) == SET
2326 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2327 && reg_mentioned_p (prev_dest, PATTERN (insn))
2328 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2329 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2330 delete_dead_insn (prev);
2332 PUT_CODE (insn, NOTE);
2333 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2334 NOTE_SOURCE_FILE (insn) = 0;
2337 /* Modify the home of pseudo-reg I.
2338 The new home is present in reg_renumber[I].
2340 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2341 or it may be -1, meaning there is none or it is not relevant.
2342 This is used so that all pseudos spilled from a given hard reg
2343 can share one stack slot. */
2346 alter_reg (i, from_reg)
2350 /* When outputting an inline function, this can happen
2351 for a reg that isn't actually used. */
2352 if (regno_reg_rtx[i] == 0)
2355 /* If the reg got changed to a MEM at rtl-generation time,
2357 if (GET_CODE (regno_reg_rtx[i]) != REG)
2360 /* Modify the reg-rtx to contain the new hard reg
2361 number or else to contain its pseudo reg number. */
2362 REGNO (regno_reg_rtx[i])
2363 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2365 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2366 allocate a stack slot for it. */
2368 if (reg_renumber[i] < 0
2369 && REG_N_REFS (i) > 0
2370 && reg_equiv_constant[i] == 0
2371 && reg_equiv_memory_loc[i] == 0)
2374 int inherent_size = PSEUDO_REGNO_BYTES (i);
2375 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2378 /* Each pseudo reg has an inherent size which comes from its own mode,
2379 and a total size which provides room for paradoxical subregs
2380 which refer to the pseudo reg in wider modes.
2382 We can use a slot already allocated if it provides both
2383 enough inherent space and enough total space.
2384 Otherwise, we allocate a new slot, making sure that it has no less
2385 inherent space, and no less total space, then the previous slot. */
2388 /* No known place to spill from => no slot to reuse. */
2389 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2390 inherent_size == total_size ? 0 : -1);
2391 if (BYTES_BIG_ENDIAN)
2392 /* Cancel the big-endian correction done in assign_stack_local.
2393 Get the address of the beginning of the slot.
2394 This is so we can do a big-endian correction unconditionally
2396 adjust = inherent_size - total_size;
2398 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2400 /* Reuse a stack slot if possible. */
2401 else if (spill_stack_slot[from_reg] != 0
2402 && spill_stack_slot_width[from_reg] >= total_size
2403 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2405 x = spill_stack_slot[from_reg];
2406 /* Allocate a bigger slot. */
2409 /* Compute maximum size needed, both for inherent size
2410 and for total size. */
2411 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2413 if (spill_stack_slot[from_reg])
2415 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2417 mode = GET_MODE (spill_stack_slot[from_reg]);
2418 if (spill_stack_slot_width[from_reg] > total_size)
2419 total_size = spill_stack_slot_width[from_reg];
2421 /* Make a slot with that size. */
2422 x = assign_stack_local (mode, total_size,
2423 inherent_size == total_size ? 0 : -1);
2425 if (BYTES_BIG_ENDIAN)
2427 /* Cancel the big-endian correction done in assign_stack_local.
2428 Get the address of the beginning of the slot.
2429 This is so we can do a big-endian correction unconditionally
2431 adjust = GET_MODE_SIZE (mode) - total_size;
2433 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2436 plus_constant (XEXP (x, 0), adjust));
2438 spill_stack_slot[from_reg] = stack_slot;
2439 spill_stack_slot_width[from_reg] = total_size;
2442 /* On a big endian machine, the "address" of the slot
2443 is the address of the low part that fits its inherent mode. */
2444 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2445 adjust += (total_size - inherent_size);
2447 /* If we have any adjustment to make, or if the stack slot is the
2448 wrong mode, make a new stack slot. */
2449 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2451 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2452 plus_constant (XEXP (x, 0), adjust));
2454 /* If this was shared among registers, must ensure we never
2455 set it readonly since that can cause scheduling
2456 problems. Note we would only have in this adjustment
2457 case in any event, since the code above doesn't set it. */
2460 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2463 /* Save the stack slot for later. */
2464 reg_equiv_memory_loc[i] = x;
2468 /* Mark the slots in regs_ever_live for the hard regs
2469 used by pseudo-reg number REGNO. */
2472 mark_home_live (regno)
2475 register int i, lim;
2476 i = reg_renumber[regno];
2479 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2481 regs_ever_live[i++] = 1;
2484 /* This function handles the tracking of elimination offsets around branches.
2486 X is a piece of RTL being scanned.
2488 INSN is the insn that it came from, if any.
2490 INITIAL_P is non-zero if we are to set the offset to be the initial
2491 offset and zero if we are setting the offset of the label to be the
2495 set_label_offsets (x, insn, initial_p)
2500 enum rtx_code code = GET_CODE (x);
2503 struct elim_table *p;
2508 if (LABEL_REF_NONLOCAL_P (x))
2513 /* ... fall through ... */
2516 /* If we know nothing about this label, set the desired offsets. Note
2517 that this sets the offset at a label to be the offset before a label
2518 if we don't know anything about the label. This is not correct for
2519 the label after a BARRIER, but is the best guess we can make. If
2520 we guessed wrong, we will suppress an elimination that might have
2521 been possible had we been able to guess correctly. */
2523 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2525 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2526 offsets_at[CODE_LABEL_NUMBER (x)][i]
2527 = (initial_p ? reg_eliminate[i].initial_offset
2528 : reg_eliminate[i].offset);
2529 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2532 /* Otherwise, if this is the definition of a label and it is
2533 preceded by a BARRIER, set our offsets to the known offset of
2537 && (tem = prev_nonnote_insn (insn)) != 0
2538 && GET_CODE (tem) == BARRIER)
2539 set_offsets_for_label (insn);
2541 /* If neither of the above cases is true, compare each offset
2542 with those previously recorded and suppress any eliminations
2543 where the offsets disagree. */
2545 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2546 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2547 != (initial_p ? reg_eliminate[i].initial_offset
2548 : reg_eliminate[i].offset))
2549 reg_eliminate[i].can_eliminate = 0;
2554 set_label_offsets (PATTERN (insn), insn, initial_p);
2556 /* ... fall through ... */
2560 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2561 and hence must have all eliminations at their initial offsets. */
2562 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2563 if (REG_NOTE_KIND (tem) == REG_LABEL)
2564 set_label_offsets (XEXP (tem, 0), insn, 1);
2569 /* Each of the labels in the address vector must be at their initial
2570 offsets. We want the first field for ADDR_VEC and the second
2571 field for ADDR_DIFF_VEC. */
2573 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2574 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2579 /* We only care about setting PC. If the source is not RETURN,
2580 IF_THEN_ELSE, or a label, disable any eliminations not at
2581 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2582 isn't one of those possibilities. For branches to a label,
2583 call ourselves recursively.
2585 Note that this can disable elimination unnecessarily when we have
2586 a non-local goto since it will look like a non-constant jump to
2587 someplace in the current function. This isn't a significant
2588 problem since such jumps will normally be when all elimination
2589 pairs are back to their initial offsets. */
2591 if (SET_DEST (x) != pc_rtx)
2594 switch (GET_CODE (SET_SRC (x)))
2601 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2605 tem = XEXP (SET_SRC (x), 1);
2606 if (GET_CODE (tem) == LABEL_REF)
2607 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2608 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2611 tem = XEXP (SET_SRC (x), 2);
2612 if (GET_CODE (tem) == LABEL_REF)
2613 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2614 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2622 /* If we reach here, all eliminations must be at their initial
2623 offset because we are doing a jump to a variable address. */
2624 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2625 if (p->offset != p->initial_offset)
2626 p->can_eliminate = 0;
2634 /* Scan X and replace any eliminable registers (such as fp) with a
2635 replacement (such as sp), plus an offset.
2637 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2638 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2639 MEM, we are allowed to replace a sum of a register and the constant zero
2640 with the register, which we cannot do outside a MEM. In addition, we need
2641 to record the fact that a register is referenced outside a MEM.
2643 If INSN is an insn, it is the insn containing X. If we replace a REG
2644 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2645 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2646 the REG is being modified.
2648 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2649 That's used when we eliminate in expressions stored in notes.
2650 This means, do not set ref_outside_mem even if the reference
2653 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2654 replacements done assuming all offsets are at their initial values. If
2655 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2656 encounter, return the actual location so that find_reloads will do
2657 the proper thing. */
2660 eliminate_regs (x, mem_mode, insn)
2662 enum machine_mode mem_mode;
2665 enum rtx_code code = GET_CODE (x);
2666 struct elim_table *ep;
2673 if (! current_function_decl)
2692 /* This is only for the benefit of the debugging backends, which call
2693 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2694 removed after CSE. */
2695 new = eliminate_regs (XEXP (x, 0), 0, insn);
2696 if (GET_CODE (new) == MEM)
2697 return XEXP (new, 0);
2703 /* First handle the case where we encounter a bare register that
2704 is eliminable. Replace it with a PLUS. */
2705 if (regno < FIRST_PSEUDO_REGISTER)
2707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2709 if (ep->from_rtx == x && ep->can_eliminate)
2710 return plus_constant (ep->to_rtx, ep->previous_offset);
2713 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2714 && reg_equiv_constant[regno]
2715 && ! CONSTANT_P (reg_equiv_constant[regno]))
2716 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2720 /* You might think handling MINUS in a manner similar to PLUS is a
2721 good idea. It is not. It has been tried multiple times and every
2722 time the change has had to have been reverted.
2724 Other parts of reload know a PLUS is special (gen_reload for example)
2725 and require special code to handle code a reloaded PLUS operand.
2727 Also consider backends where the flags register is clobbered by a
2728 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2729 lea instruction comes to mind). If we try to reload a MINUS, we
2730 may kill the flags register that was holding a useful value.
2732 So, please before trying to handle MINUS, consider reload as a
2733 whole instead of this little section as well as the backend issues. */
2735 /* If this is the sum of an eliminable register and a constant, rework
2737 if (GET_CODE (XEXP (x, 0)) == REG
2738 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2739 && CONSTANT_P (XEXP (x, 1)))
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2743 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2745 /* The only time we want to replace a PLUS with a REG (this
2746 occurs when the constant operand of the PLUS is the negative
2747 of the offset) is when we are inside a MEM. We won't want
2748 to do so at other times because that would change the
2749 structure of the insn in a way that reload can't handle.
2750 We special-case the commonest situation in
2751 eliminate_regs_in_insn, so just replace a PLUS with a
2752 PLUS here, unless inside a MEM. */
2753 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2754 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2757 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2758 plus_constant (XEXP (x, 1),
2759 ep->previous_offset));
2762 /* If the register is not eliminable, we are done since the other
2763 operand is a constant. */
2767 /* If this is part of an address, we want to bring any constant to the
2768 outermost PLUS. We will do this by doing register replacement in
2769 our operands and seeing if a constant shows up in one of them.
2771 Note that there is no risk of modifying the structure of the insn,
2772 since we only get called for its operands, thus we are either
2773 modifying the address inside a MEM, or something like an address
2774 operand of a load-address insn. */
2777 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2778 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2780 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2782 /* If one side is a PLUS and the other side is a pseudo that
2783 didn't get a hard register but has a reg_equiv_constant,
2784 we must replace the constant here since it may no longer
2785 be in the position of any operand. */
2786 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2787 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2788 && reg_renumber[REGNO (new1)] < 0
2789 && reg_equiv_constant != 0
2790 && reg_equiv_constant[REGNO (new1)] != 0)
2791 new1 = reg_equiv_constant[REGNO (new1)];
2792 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2793 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2794 && reg_renumber[REGNO (new0)] < 0
2795 && reg_equiv_constant[REGNO (new0)] != 0)
2796 new0 = reg_equiv_constant[REGNO (new0)];
2798 new = form_sum (new0, new1);
2800 /* As above, if we are not inside a MEM we do not want to
2801 turn a PLUS into something else. We might try to do so here
2802 for an addition of 0 if we aren't optimizing. */
2803 if (! mem_mode && GET_CODE (new) != PLUS)
2804 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2812 /* If this is the product of an eliminable register and a
2813 constant, apply the distribute law and move the constant out
2814 so that we have (plus (mult ..) ..). This is needed in order
2815 to keep load-address insns valid. This case is pathological.
2816 We ignore the possibility of overflow here. */
2817 if (GET_CODE (XEXP (x, 0)) == REG
2818 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2819 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2822 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2825 /* Refs inside notes don't count for this purpose. */
2826 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2827 || GET_CODE (insn) == INSN_LIST)))
2828 ep->ref_outside_mem = 1;
2831 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2832 ep->previous_offset * INTVAL (XEXP (x, 1)));
2835 /* ... fall through ... */
2839 /* See comments before PLUS about handling MINUS. */
2841 case DIV: case UDIV:
2842 case MOD: case UMOD:
2843 case AND: case IOR: case XOR:
2844 case ROTATERT: case ROTATE:
2845 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2847 case GE: case GT: case GEU: case GTU:
2848 case LE: case LT: case LEU: case LTU:
2850 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2852 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2854 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2855 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2860 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2863 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2864 if (new != XEXP (x, 0))
2866 /* If this is a REG_DEAD note, it is not valid anymore.
2867 Using the eliminated version could result in creating a
2868 REG_DEAD note for the stack or frame pointer. */
2869 if (GET_MODE (x) == REG_DEAD)
2871 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2874 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2878 /* ... fall through ... */
2881 /* Now do eliminations in the rest of the chain. If this was
2882 an EXPR_LIST, this might result in allocating more memory than is
2883 strictly needed, but it simplifies the code. */
2886 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2887 if (new != XEXP (x, 1))
2888 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2896 case STRICT_LOW_PART:
2898 case SIGN_EXTEND: case ZERO_EXTEND:
2899 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2900 case FLOAT: case FIX:
2901 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2905 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2906 if (new != XEXP (x, 0))
2907 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2911 /* Similar to above processing, but preserve SUBREG_WORD.
2912 Convert (subreg (mem)) to (mem) if not paradoxical.
2913 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2914 pseudo didn't get a hard reg, we must replace this with the
2915 eliminated version of the memory location because push_reloads
2916 may do the replacement in certain circumstances. */
2917 if (GET_CODE (SUBREG_REG (x)) == REG
2918 && (GET_MODE_SIZE (GET_MODE (x))
2919 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2920 && reg_equiv_memory_loc != 0
2921 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2923 new = SUBREG_REG (x);
2926 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2928 if (new != XEXP (x, 0))
2930 int x_size = GET_MODE_SIZE (GET_MODE (x));
2931 int new_size = GET_MODE_SIZE (GET_MODE (new));
2933 if (GET_CODE (new) == MEM
2934 && ((x_size < new_size
2935 #ifdef WORD_REGISTER_OPERATIONS
2936 /* On these machines, combine can create rtl of the form
2937 (set (subreg:m1 (reg:m2 R) 0) ...)
2938 where m1 < m2, and expects something interesting to
2939 happen to the entire word. Moreover, it will use the
2940 (reg:m2 R) later, expecting all bits to be preserved.
2941 So if the number of words is the same, preserve the
2942 subreg so that push_reloads can see it. */
2943 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2946 || (x_size == new_size))
2949 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2950 enum machine_mode mode = GET_MODE (x);
2952 if (BYTES_BIG_ENDIAN)
2953 offset += (MIN (UNITS_PER_WORD,
2954 GET_MODE_SIZE (GET_MODE (new)))
2955 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2957 PUT_MODE (new, mode);
2958 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2962 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2968 /* This is only for the benefit of the debugging backends, which call
2969 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2970 removed after CSE. */
2971 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2972 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2974 /* Our only special processing is to pass the mode of the MEM to our
2975 recursive call and copy the flags. While we are here, handle this
2976 case more efficiently. */
2977 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2978 if (new != XEXP (x, 0))
2980 new = gen_rtx_MEM (GET_MODE (x), new);
2981 new->volatil = x->volatil;
2982 new->unchanging = x->unchanging;
2983 new->in_struct = x->in_struct;
2999 /* Process each of our operands recursively. If any have changed, make a
3001 fmt = GET_RTX_FORMAT (code);
3002 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3006 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3007 if (new != XEXP (x, i) && ! copied)
3009 rtx new_x = rtx_alloc (code);
3010 bcopy ((char *) x, (char *) new_x,
3011 (sizeof (*new_x) - sizeof (new_x->fld)
3012 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3018 else if (*fmt == 'E')
3021 for (j = 0; j < XVECLEN (x, i); j++)
3023 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3024 if (new != XVECEXP (x, i, j) && ! copied_vec)
3026 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3030 rtx new_x = rtx_alloc (code);
3031 bcopy ((char *) x, (char *) new_x,
3032 (sizeof (*new_x) - sizeof (new_x->fld)
3033 + (sizeof (new_x->fld[0])
3034 * GET_RTX_LENGTH (code))));
3038 XVEC (x, i) = new_v;
3041 XVECEXP (x, i, j) = new;
3049 /* Scan rtx X for modifications of elimination target registers. Update
3050 the table of eliminables to reflect the changed state. MEM_MODE is
3051 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
3054 elimination_effects (x, mem_mode)
3056 enum machine_mode mem_mode;
3059 enum rtx_code code = GET_CODE (x);
3060 struct elim_table *ep;
3086 /* First handle the case where we encounter a bare register that
3087 is eliminable. Replace it with a PLUS. */
3088 if (regno < FIRST_PSEUDO_REGISTER)
3090 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3092 if (ep->from_rtx == x && ep->can_eliminate)
3095 ep->ref_outside_mem = 1;
3100 else if (reg_renumber[regno] < 0 && reg_equiv_constant
3101 && reg_equiv_constant[regno]
3102 && ! CONSTANT_P (reg_equiv_constant[regno]))
3103 elimination_effects (reg_equiv_constant[regno], mem_mode);
3110 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3111 if (ep->to_rtx == XEXP (x, 0))
3113 int size = GET_MODE_SIZE (mem_mode);
3115 /* If more bytes than MEM_MODE are pushed, account for them. */
3116 #ifdef PUSH_ROUNDING
3117 if (ep->to_rtx == stack_pointer_rtx)
3118 size = PUSH_ROUNDING (size);
3120 if (code == PRE_DEC || code == POST_DEC)
3126 /* Fall through to generic unary operation case. */
3127 case STRICT_LOW_PART:
3129 case SIGN_EXTEND: case ZERO_EXTEND:
3130 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3131 case FLOAT: case FIX:
3132 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3136 elimination_effects (XEXP (x, 0), mem_mode);
3140 if (GET_CODE (SUBREG_REG (x)) == REG
3141 && (GET_MODE_SIZE (GET_MODE (x))
3142 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3143 && reg_equiv_memory_loc != 0
3144 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3147 elimination_effects (SUBREG_REG (x), mem_mode);
3151 /* If using a register that is the source of an eliminate we still
3152 think can be performed, note it cannot be performed since we don't
3153 know how this register is used. */
3154 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3155 if (ep->from_rtx == XEXP (x, 0))
3156 ep->can_eliminate = 0;
3158 elimination_effects (XEXP (x, 0), mem_mode);
3162 /* If clobbering a register that is the replacement register for an
3163 elimination we still think can be performed, note that it cannot
3164 be performed. Otherwise, we need not be concerned about it. */
3165 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3166 if (ep->to_rtx == XEXP (x, 0))
3167 ep->can_eliminate = 0;
3169 elimination_effects (XEXP (x, 0), mem_mode);
3173 /* Check for setting a register that we know about. */
3174 if (GET_CODE (SET_DEST (x)) == REG)
3176 /* See if this is setting the replacement register for an
3179 If DEST is the hard frame pointer, we do nothing because we
3180 assume that all assignments to the frame pointer are for
3181 non-local gotos and are being done at a time when they are valid
3182 and do not disturb anything else. Some machines want to
3183 eliminate a fake argument pointer (or even a fake frame pointer)
3184 with either the real frame or the stack pointer. Assignments to
3185 the hard frame pointer must not prevent this elimination. */
3187 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3189 if (ep->to_rtx == SET_DEST (x)
3190 && SET_DEST (x) != hard_frame_pointer_rtx)
3192 /* If it is being incremented, adjust the offset. Otherwise,
3193 this elimination can't be done. */
3194 rtx src = SET_SRC (x);
3196 if (GET_CODE (src) == PLUS
3197 && XEXP (src, 0) == SET_DEST (x)
3198 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3199 ep->offset -= INTVAL (XEXP (src, 1));
3201 ep->can_eliminate = 0;
3205 elimination_effects (SET_DEST (x), 0);
3206 elimination_effects (SET_SRC (x), 0);
3210 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3213 /* Our only special processing is to pass the mode of the MEM to our
3215 elimination_effects (XEXP (x, 0), GET_MODE (x));
3222 fmt = GET_RTX_FORMAT (code);
3223 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3226 elimination_effects (XEXP (x, i), mem_mode);
3227 else if (*fmt == 'E')
3228 for (j = 0; j < XVECLEN (x, i); j++)
3229 elimination_effects (XVECEXP (x, i, j), mem_mode);
3233 /* Descend through rtx X and verify that no references to eliminable registers
3234 remain. If any do remain, mark the involved register as not
3237 check_eliminable_occurrences (x)
3247 code = GET_CODE (x);
3249 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3251 struct elim_table *ep;
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 if (ep->from_rtx == x && ep->can_eliminate)
3255 ep->can_eliminate = 0;
3259 fmt = GET_RTX_FORMAT (code);
3260 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3263 check_eliminable_occurrences (XEXP (x, i));
3264 else if (*fmt == 'E')
3267 for (j = 0; j < XVECLEN (x, i); j++)
3268 check_eliminable_occurrences (XVECEXP (x, i, j));
3273 /* Scan INSN and eliminate all eliminable registers in it.
3275 If REPLACE is nonzero, do the replacement destructively. Also
3276 delete the insn as dead it if it is setting an eliminable register.
3278 If REPLACE is zero, do all our allocations in reload_obstack.
3280 If no eliminations were done and this insn doesn't require any elimination
3281 processing (these are not identical conditions: it might be updating sp,
3282 but not referencing fp; this needs to be seen during reload_as_needed so
3283 that the offset between fp and sp can be taken into consideration), zero
3284 is returned. Otherwise, 1 is returned. */
3287 eliminate_regs_in_insn (insn, replace)
3291 int icode = recog_memoized (insn);
3292 rtx old_body = PATTERN (insn);
3293 int insn_is_asm = asm_noperands (old_body) >= 0;
3294 rtx old_set = single_set (insn);
3298 rtx substed_operand[MAX_RECOG_OPERANDS];
3299 rtx orig_operand[MAX_RECOG_OPERANDS];
3300 struct elim_table *ep;
3302 if (! insn_is_asm && icode < 0)
3304 if (GET_CODE (PATTERN (insn)) == USE
3305 || GET_CODE (PATTERN (insn)) == CLOBBER
3306 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3307 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3308 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
3314 push_obstacks (&reload_obstack, &reload_obstack);
3316 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3317 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3319 /* Check for setting an eliminable register. */
3320 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3321 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3323 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3324 /* If this is setting the frame pointer register to the
3325 hardware frame pointer register and this is an elimination
3326 that will be done (tested above), this insn is really
3327 adjusting the frame pointer downward to compensate for
3328 the adjustment done before a nonlocal goto. */
3329 if (ep->from == FRAME_POINTER_REGNUM
3330 && ep->to == HARD_FRAME_POINTER_REGNUM)
3332 rtx src = SET_SRC (old_set);
3333 int offset = 0, ok = 0;
3334 rtx prev_insn, prev_set;
3336 if (src == ep->to_rtx)
3338 else if (GET_CODE (src) == PLUS
3339 && GET_CODE (XEXP (src, 0)) == CONST_INT
3340 && XEXP (src, 1) == ep->to_rtx)
3341 offset = INTVAL (XEXP (src, 0)), ok = 1;
3342 else if (GET_CODE (src) == PLUS
3343 && GET_CODE (XEXP (src, 1)) == CONST_INT
3344 && XEXP (src, 0) == ep->to_rtx)
3345 offset = INTVAL (XEXP (src, 1)), ok = 1;
3346 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3347 && (prev_set = single_set (prev_insn)) != 0
3348 && rtx_equal_p (SET_DEST (prev_set), src))
3350 src = SET_SRC (prev_set);
3351 if (src == ep->to_rtx)
3353 else if (GET_CODE (src) == PLUS
3354 && GET_CODE (XEXP (src, 0)) == CONST_INT
3355 && XEXP (src, 1) == ep->to_rtx)
3356 offset = INTVAL (XEXP (src, 0)), ok = 1;
3357 else if (GET_CODE (src) == PLUS
3358 && GET_CODE (XEXP (src, 1)) == CONST_INT
3359 && XEXP (src, 0) == ep->to_rtx)
3360 offset = INTVAL (XEXP (src, 1)), ok = 1;
3368 = plus_constant (ep->to_rtx, offset - ep->offset);
3370 /* First see if this insn remains valid when we
3371 make the change. If not, keep the INSN_CODE
3372 the same and let reload fit it up. */
3373 validate_change (insn, &SET_SRC (old_set), src, 1);
3374 validate_change (insn, &SET_DEST (old_set),
3376 if (! apply_change_group ())
3378 SET_SRC (old_set) = src;
3379 SET_DEST (old_set) = ep->to_rtx;
3389 /* In this case this insn isn't serving a useful purpose. We
3390 will delete it in reload_as_needed once we know that this
3391 elimination is, in fact, being done.
3393 If REPLACE isn't set, we can't delete this insn, but needn't
3394 process it since it won't be used unless something changes. */
3397 delete_dead_insn (insn);
3404 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3405 in the insn is the negative of the offset in FROM. Substitute
3406 (set (reg) (reg to)) for the insn and change its code.
3408 We have to do this here, rather than in eliminate_regs, so that we can
3409 change the insn code. */
3411 if (GET_CODE (SET_SRC (old_set)) == PLUS
3412 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3413 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3414 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3416 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3417 && ep->can_eliminate)
3419 /* We must stop at the first elimination that will be used.
3420 If this one would replace the PLUS with a REG, do it
3421 now. Otherwise, quit the loop and let eliminate_regs
3422 do its normal replacement. */
3423 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3425 /* We assume here that we don't need a PARALLEL of
3426 any CLOBBERs for this assignment. There's not
3427 much we can do if we do need it. */
3428 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3431 INSN_CODE (insn) = -1;
3440 /* Determine the effects of this insn on elimination offsets. */
3441 elimination_effects (old_body, 0);
3443 /* Eliminate all eliminable registers occurring in operands that
3444 can be handled by reload. */
3445 extract_insn (insn);
3447 for (i = 0; i < recog_data.n_operands; i++)
3449 orig_operand[i] = recog_data.operand[i];
3450 substed_operand[i] = recog_data.operand[i];
3452 /* For an asm statement, every operand is eliminable. */
3453 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3455 /* Check for setting a register that we know about. */
3456 if (recog_data.operand_type[i] != OP_IN
3457 && GET_CODE (orig_operand[i]) == REG)
3459 /* If we are assigning to a register that can be eliminated, it
3460 must be as part of a PARALLEL, since the code above handles
3461 single SETs. We must indicate that we can no longer
3462 eliminate this reg. */
3463 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3465 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3466 ep->can_eliminate = 0;
3469 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3470 replace ? insn : NULL_RTX);
3471 if (substed_operand[i] != orig_operand[i])
3472 val = any_changes = 1;
3473 /* Terminate the search in check_eliminable_occurrences at
3475 *recog_data.operand_loc[i] = 0;
3477 /* If an output operand changed from a REG to a MEM and INSN is an
3478 insn, write a CLOBBER insn. */
3479 if (recog_data.operand_type[i] != OP_IN
3480 && GET_CODE (orig_operand[i]) == REG
3481 && GET_CODE (substed_operand[i]) == MEM
3483 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3488 for (i = 0; i < recog_data.n_dups; i++)
3489 *recog_data.dup_loc[i]
3490 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3492 /* If any eliminable remain, they aren't eliminable anymore. */
3493 check_eliminable_occurrences (old_body);
3495 /* Substitute the operands; the new values are in the substed_operand
3497 for (i = 0; i < recog_data.n_operands; i++)
3498 *recog_data.operand_loc[i] = substed_operand[i];
3499 for (i = 0; i < recog_data.n_dups; i++)
3500 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3502 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3503 re-recognize the insn. We do this in case we had a simple addition
3504 but now can do this as a load-address. This saves an insn in this
3506 If re-recognition fails, the old insn code number will still be used,
3507 and some register operands may have changed into PLUS expressions.
3508 These will be handled by find_reloads by loading them into a register
3513 /* If we aren't replacing things permanently and we changed something,
3514 make another copy to ensure that all the RTL is new. Otherwise
3515 things can go wrong if find_reload swaps commutative operands
3516 and one is inside RTL that has been copied while the other is not. */
3517 new_body = old_body;
3520 new_body = copy_insn (old_body);
3521 if (REG_NOTES (insn))
3522 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3524 PATTERN (insn) = new_body;
3526 /* If we had a move insn but now we don't, rerecognize it. This will
3527 cause spurious re-recognition if the old move had a PARALLEL since
3528 the new one still will, but we can't call single_set without
3529 having put NEW_BODY into the insn and the re-recognition won't
3530 hurt in this rare case. */
3531 /* ??? Why this huge if statement - why don't we just rerecognize the
3535 && ((GET_CODE (SET_SRC (old_set)) == REG
3536 && (GET_CODE (new_body) != SET
3537 || GET_CODE (SET_SRC (new_body)) != REG))
3538 /* If this was a load from or store to memory, compare
3539 the MEM in recog_data.operand to the one in the insn.
3540 If they are not equal, then rerecognize the insn. */
3542 && ((GET_CODE (SET_SRC (old_set)) == MEM
3543 && SET_SRC (old_set) != recog_data.operand[1])
3544 || (GET_CODE (SET_DEST (old_set)) == MEM
3545 && SET_DEST (old_set) != recog_data.operand[0])))
3546 /* If this was an add insn before, rerecognize. */
3547 || GET_CODE (SET_SRC (old_set)) == PLUS))
3549 int new_icode = recog (PATTERN (insn), insn, 0);
3551 INSN_CODE (insn) = icode;
3555 /* Restore the old body. If there were any changes to it, we made a copy
3556 of it while the changes were still in place, so we'll correctly return
3557 a modified insn below. */
3560 /* Restore the old body. */
3561 for (i = 0; i < recog_data.n_operands; i++)
3562 *recog_data.operand_loc[i] = orig_operand[i];
3563 for (i = 0; i < recog_data.n_dups; i++)
3564 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3567 /* Update all elimination pairs to reflect the status after the current
3568 insn. The changes we make were determined by the earlier call to
3569 elimination_effects.
3571 We also detect a cases where register elimination cannot be done,
3572 namely, if a register would be both changed and referenced outside a MEM
3573 in the resulting insn since such an insn is often undefined and, even if
3574 not, we cannot know what meaning will be given to it. Note that it is
3575 valid to have a register used in an address in an insn that changes it
3576 (presumably with a pre- or post-increment or decrement).
3578 If anything changes, return nonzero. */
3580 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3582 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3583 ep->can_eliminate = 0;
3585 ep->ref_outside_mem = 0;
3587 if (ep->previous_offset != ep->offset)
3592 /* If we changed something, perform elimination in REG_NOTES. This is
3593 needed even when REPLACE is zero because a REG_DEAD note might refer
3594 to a register that we eliminate and could cause a different number
3595 of spill registers to be needed in the final reload pass than in
3597 if (val && REG_NOTES (insn) != 0)
3598 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3606 /* Loop through all elimination pairs.
3607 Recalculate the number not at initial offset.
3609 Compute the maximum offset (minimum offset if the stack does not
3610 grow downward) for each elimination pair. */
3613 update_eliminable_offsets ()
3615 struct elim_table *ep;
3617 num_not_at_initial_offset = 0;
3618 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3620 ep->previous_offset = ep->offset;
3621 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3622 num_not_at_initial_offset++;
3626 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3627 replacement we currently believe is valid, mark it as not eliminable if X
3628 modifies DEST in any way other than by adding a constant integer to it.
3630 If DEST is the frame pointer, we do nothing because we assume that
3631 all assignments to the hard frame pointer are nonlocal gotos and are being
3632 done at a time when they are valid and do not disturb anything else.
3633 Some machines want to eliminate a fake argument pointer with either the
3634 frame or stack pointer. Assignments to the hard frame pointer must not
3635 prevent this elimination.
3637 Called via note_stores from reload before starting its passes to scan
3638 the insns of the function. */
3641 mark_not_eliminable (dest, x, data)
3644 void *data ATTRIBUTE_UNUSED;
3646 register unsigned int i;
3648 /* A SUBREG of a hard register here is just changing its mode. We should
3649 not see a SUBREG of an eliminable hard register, but check just in
3651 if (GET_CODE (dest) == SUBREG)
3652 dest = SUBREG_REG (dest);
3654 if (dest == hard_frame_pointer_rtx)
3657 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3658 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3659 && (GET_CODE (x) != SET
3660 || GET_CODE (SET_SRC (x)) != PLUS
3661 || XEXP (SET_SRC (x), 0) != dest
3662 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3664 reg_eliminate[i].can_eliminate_previous
3665 = reg_eliminate[i].can_eliminate = 0;
3670 /* Verify that the initial elimination offsets did not change since the
3671 last call to set_initial_elim_offsets. This is used to catch cases
3672 where something illegal happened during reload_as_needed that could
3673 cause incorrect code to be generated if we did not check for it. */
3675 verify_initial_elim_offsets ()
3679 #ifdef ELIMINABLE_REGS
3680 struct elim_table *ep;
3682 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3684 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3685 if (t != ep->initial_offset)
3689 INITIAL_FRAME_POINTER_OFFSET (t);
3690 if (t != reg_eliminate[0].initial_offset)
3695 /* Reset all offsets on eliminable registers to their initial values. */
3697 set_initial_elim_offsets ()
3699 struct elim_table *ep = reg_eliminate;
3701 #ifdef ELIMINABLE_REGS
3702 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3704 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3705 ep->previous_offset = ep->offset = ep->initial_offset;
3708 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3709 ep->previous_offset = ep->offset = ep->initial_offset;
3712 num_not_at_initial_offset = 0;
3715 /* Initialize the known label offsets.
3716 Set a known offset for each forced label to be at the initial offset
3717 of each elimination. We do this because we assume that all
3718 computed jumps occur from a location where each elimination is
3719 at its initial offset.
3720 For all other labels, show that we don't know the offsets. */
3723 set_initial_label_offsets ()
3726 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3728 for (x = forced_labels; x; x = XEXP (x, 1))
3730 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3733 /* Set all elimination offsets to the known values for the code label given
3736 set_offsets_for_label (insn)
3740 int label_nr = CODE_LABEL_NUMBER (insn);
3741 struct elim_table *ep;
3743 num_not_at_initial_offset = 0;
3744 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3746 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3747 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3748 num_not_at_initial_offset++;
3752 /* See if anything that happened changes which eliminations are valid.
3753 For example, on the Sparc, whether or not the frame pointer can
3754 be eliminated can depend on what registers have been used. We need
3755 not check some conditions again (such as flag_omit_frame_pointer)
3756 since they can't have changed. */
3759 update_eliminables (pset)
3762 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3763 int previous_frame_pointer_needed = frame_pointer_needed;
3765 struct elim_table *ep;
3767 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3768 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3769 #ifdef ELIMINABLE_REGS
3770 || ! CAN_ELIMINATE (ep->from, ep->to)
3773 ep->can_eliminate = 0;
3775 /* Look for the case where we have discovered that we can't replace
3776 register A with register B and that means that we will now be
3777 trying to replace register A with register C. This means we can
3778 no longer replace register C with register B and we need to disable
3779 such an elimination, if it exists. This occurs often with A == ap,
3780 B == sp, and C == fp. */
3782 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3784 struct elim_table *op;
3785 register int new_to = -1;
3787 if (! ep->can_eliminate && ep->can_eliminate_previous)
3789 /* Find the current elimination for ep->from, if there is a
3791 for (op = reg_eliminate;
3792 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3793 if (op->from == ep->from && op->can_eliminate)
3799 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3801 for (op = reg_eliminate;
3802 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3803 if (op->from == new_to && op->to == ep->to)
3804 op->can_eliminate = 0;
3808 /* See if any registers that we thought we could eliminate the previous
3809 time are no longer eliminable. If so, something has changed and we
3810 must spill the register. Also, recompute the number of eliminable
3811 registers and see if the frame pointer is needed; it is if there is
3812 no elimination of the frame pointer that we can perform. */
3814 frame_pointer_needed = 1;
3815 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3817 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3818 && ep->to != HARD_FRAME_POINTER_REGNUM)
3819 frame_pointer_needed = 0;
3821 if (! ep->can_eliminate && ep->can_eliminate_previous)
3823 ep->can_eliminate_previous = 0;
3824 SET_HARD_REG_BIT (*pset, ep->from);
3829 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3830 /* If we didn't need a frame pointer last time, but we do now, spill
3831 the hard frame pointer. */
3832 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3833 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3837 /* Initialize the table of registers to eliminate. */
3841 struct elim_table *ep;
3842 #ifdef ELIMINABLE_REGS
3843 struct elim_table_1 *ep1;
3847 reg_eliminate = (struct elim_table *)
3848 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3850 /* Does this function require a frame pointer? */
3852 frame_pointer_needed = (! flag_omit_frame_pointer
3853 #ifdef EXIT_IGNORE_STACK
3854 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3855 and restore sp for alloca. So we can't eliminate
3856 the frame pointer in that case. At some point,
3857 we should improve this by emitting the
3858 sp-adjusting insns for this case. */
3859 || (current_function_calls_alloca
3860 && EXIT_IGNORE_STACK)
3862 || FRAME_POINTER_REQUIRED);
3866 #ifdef ELIMINABLE_REGS
3867 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3868 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3870 ep->from = ep1->from;
3872 ep->can_eliminate = ep->can_eliminate_previous
3873 = (CAN_ELIMINATE (ep->from, ep->to)
3874 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3877 reg_eliminate[0].from = reg_eliminate_1[0].from;
3878 reg_eliminate[0].to = reg_eliminate_1[0].to;
3879 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3880 = ! frame_pointer_needed;
3883 /* Count the number of eliminable registers and build the FROM and TO
3884 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3885 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3886 We depend on this. */
3887 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3889 num_eliminable += ep->can_eliminate;
3890 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3891 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3895 /* Kick all pseudos out of hard register REGNO.
3896 If DUMPFILE is nonzero, log actions taken on that file.
3898 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3899 because we found we can't eliminate some register. In the case, no pseudos
3900 are allowed to be in the register, even if they are only in a block that
3901 doesn't require spill registers, unlike the case when we are spilling this
3902 hard reg to produce another spill register.
3904 Return nonzero if any pseudos needed to be kicked out. */
3907 spill_hard_reg (regno, dumpfile, cant_eliminate)
3909 FILE *dumpfile ATTRIBUTE_UNUSED;
3916 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3917 regs_ever_live[regno] = 1;
3920 /* Spill every pseudo reg that was allocated to this reg
3921 or to something that overlaps this reg. */
3923 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3924 if (reg_renumber[i] >= 0
3925 && reg_renumber[i] <= regno
3927 + HARD_REGNO_NREGS (reg_renumber[i],
3928 PSEUDO_REGNO_MODE (i))
3930 SET_REGNO_REG_SET (spilled_pseudos, i);
3933 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3934 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3936 ior_hard_reg_set (set1, set2)
3937 HARD_REG_SET *set1, *set2;
3939 IOR_HARD_REG_SET (*set1, *set2);
3942 /* After find_reload_regs has been run for all insn that need reloads,
3943 and/or spill_hard_regs was called, this function is used to actually
3944 spill pseudo registers and try to reallocate them. It also sets up the
3945 spill_regs array for use by choose_reload_regs. */
3948 finish_spills (global, dumpfile)
3952 struct insn_chain *chain;
3953 int something_changed = 0;
3956 /* Build the spill_regs array for the function. */
3957 /* If there are some registers still to eliminate and one of the spill regs
3958 wasn't ever used before, additional stack space may have to be
3959 allocated to store this register. Thus, we may have changed the offset
3960 between the stack and frame pointers, so mark that something has changed.
3962 One might think that we need only set VAL to 1 if this is a call-used
3963 register. However, the set of registers that must be saved by the
3964 prologue is not identical to the call-used set. For example, the
3965 register used by the call insn for the return PC is a call-used register,
3966 but must be saved by the prologue. */
3969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3970 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3972 spill_reg_order[i] = n_spills;
3973 spill_regs[n_spills++] = i;
3974 if (num_eliminable && ! regs_ever_live[i])
3975 something_changed = 1;
3976 regs_ever_live[i] = 1;
3979 spill_reg_order[i] = -1;
3981 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3982 if (REGNO_REG_SET_P (spilled_pseudos, i))
3984 /* Record the current hard register the pseudo is allocated to in
3985 pseudo_previous_regs so we avoid reallocating it to the same
3986 hard reg in a later pass. */
3987 if (reg_renumber[i] < 0)
3989 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3990 /* Mark it as no longer having a hard register home. */
3991 reg_renumber[i] = -1;
3992 /* We will need to scan everything again. */
3993 something_changed = 1;
3996 /* Retry global register allocation if possible. */
3999 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
4000 /* For every insn that needs reloads, set the registers used as spill
4001 regs in pseudo_forbidden_regs for every pseudo live across the
4003 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4005 EXECUTE_IF_SET_IN_REG_SET
4006 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
4008 ior_hard_reg_set (pseudo_forbidden_regs + i,
4009 &chain->used_spill_regs);
4011 EXECUTE_IF_SET_IN_REG_SET
4012 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
4014 ior_hard_reg_set (pseudo_forbidden_regs + i,
4015 &chain->used_spill_regs);
4019 /* Retry allocating the spilled pseudos. For each reg, merge the
4020 various reg sets that indicate which hard regs can't be used,
4021 and call retry_global_alloc.
4022 We change spill_pseudos here to only contain pseudos that did not
4023 get a new hard register. */
4024 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4025 if (reg_old_renumber[i] != reg_renumber[i])
4027 HARD_REG_SET forbidden;
4028 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
4029 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
4030 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
4031 retry_global_alloc (i, forbidden);
4032 if (reg_renumber[i] >= 0)
4033 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
4037 /* Fix up the register information in the insn chain.
4038 This involves deleting those of the spilled pseudos which did not get
4039 a new hard register home from the live_{before,after} sets. */
4040 for (chain = reload_insn_chain; chain; chain = chain->next)
4042 HARD_REG_SET used_by_pseudos;
4043 HARD_REG_SET used_by_pseudos2;
4045 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
4046 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
4048 /* Mark any unallocated hard regs as available for spills. That
4049 makes inheritance work somewhat better. */
4050 if (chain->need_reload)
4052 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
4053 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
4054 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4056 /* Save the old value for the sanity test below. */
4057 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
4059 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
4060 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
4061 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4062 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4064 /* Make sure we only enlarge the set. */
4065 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
4071 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4072 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4074 int regno = reg_renumber[i];
4075 if (reg_old_renumber[i] == regno)
4078 alter_reg (i, reg_old_renumber[i]);
4079 reg_old_renumber[i] = regno;
4083 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
4085 fprintf (dumpfile, " Register %d now in %d.\n\n",
4086 i, reg_renumber[i]);
4090 return something_changed;
4093 /* Find all paradoxical subregs within X and update reg_max_ref_width.
4094 Also mark any hard registers used to store user variables as
4095 forbidden from being used for spill registers. */
4098 scan_paradoxical_subregs (x)
4102 register const char *fmt;
4103 register enum rtx_code code = GET_CODE (x);
4109 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4110 && REG_USERVAR_P (x))
4111 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4127 if (GET_CODE (SUBREG_REG (x)) == REG
4128 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4129 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4130 = GET_MODE_SIZE (GET_MODE (x));
4137 fmt = GET_RTX_FORMAT (code);
4138 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4141 scan_paradoxical_subregs (XEXP (x, i));
4142 else if (fmt[i] == 'E')
4145 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4146 scan_paradoxical_subregs (XVECEXP (x, i, j));
4152 hard_reg_use_compare (p1p, p2p)
4156 const struct hard_reg_n_uses *p1 = (const struct hard_reg_n_uses *)p1p;
4157 const struct hard_reg_n_uses *p2 = (const struct hard_reg_n_uses *)p2p;
4158 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4159 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4161 return p1->regno - p2->regno;
4166 if (p1->uses > p2->uses)
4168 if (p1->uses < p2->uses)
4170 /* If regs are equally good, sort by regno,
4171 so that the results of qsort leave nothing to chance. */
4172 return p1->regno - p2->regno;
4175 /* Used for communication between order_regs_for_reload and count_pseudo.
4176 Used to avoid counting one pseudo twice. */
4177 static regset pseudos_counted;
4179 /* Update the costs in N_USES, considering that pseudo REG is live. */
4181 count_pseudo (n_uses, reg)
4182 struct hard_reg_n_uses *n_uses;
4185 int r = reg_renumber[reg];
4188 if (REGNO_REG_SET_P (pseudos_counted, reg))
4190 SET_REGNO_REG_SET (pseudos_counted, reg);
4195 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4197 n_uses[r++].uses += REG_N_REFS (reg);
4199 /* Choose the order to consider regs for use as reload registers
4200 based on how much trouble would be caused by spilling one.
4201 Store them in order of decreasing preference in potential_reload_regs. */
4204 order_regs_for_reload (chain)
4205 struct insn_chain *chain;
4209 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4211 pseudos_counted = ALLOCA_REG_SET ();
4213 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4215 /* Count number of uses of each hard reg by pseudo regs allocated to it
4216 and then order them by decreasing use. */
4218 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4220 hard_reg_n_uses[i].regno = i;
4221 hard_reg_n_uses[i].uses = 0;
4223 /* Test the various reasons why we can't use a register for
4224 spilling in this insn. */
4226 || REGNO_REG_SET_P (chain->live_before, i)
4227 || REGNO_REG_SET_P (chain->live_after, i))
4228 SET_HARD_REG_BIT (bad_spill_regs, i);
4231 /* Now compute hard_reg_n_uses. */
4232 CLEAR_REG_SET (pseudos_counted);
4234 EXECUTE_IF_SET_IN_REG_SET
4235 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
4237 count_pseudo (hard_reg_n_uses, i);
4239 EXECUTE_IF_SET_IN_REG_SET
4240 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
4242 count_pseudo (hard_reg_n_uses, i);
4245 FREE_REG_SET (pseudos_counted);
4247 /* Prefer registers not so far used, for use in temporary loading.
4248 Among them, if REG_ALLOC_ORDER is defined, use that order.
4249 Otherwise, prefer registers not preserved by calls. */
4251 #ifdef REG_ALLOC_ORDER
4252 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4254 int regno = reg_alloc_order[i];
4256 if (hard_reg_n_uses[regno].uses == 0
4257 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4258 potential_reload_regs[o++] = regno;
4261 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4263 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4264 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4265 potential_reload_regs[o++] = i;
4267 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4269 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4270 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4271 potential_reload_regs[o++] = i;
4275 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4276 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4278 /* Now add the regs that are already used,
4279 preferring those used less often. The fixed and otherwise forbidden
4280 registers will be at the end of this list. */
4282 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4283 if (hard_reg_n_uses[i].uses != 0
4284 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4285 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4287 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4288 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4291 /* Reload pseudo-registers into hard regs around each insn as needed.
4292 Additional register load insns are output before the insn that needs it
4293 and perhaps store insns after insns that modify the reloaded pseudo reg.
4295 reg_last_reload_reg and reg_reloaded_contents keep track of
4296 which registers are already available in reload registers.
4297 We update these for the reloads that we perform,
4298 as the insns are scanned. */
4301 reload_as_needed (live_known)
4304 struct insn_chain *chain;
4305 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4310 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4311 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4312 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
4313 reg_has_output_reload = (char *) xmalloc (max_regno);
4314 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4316 set_initial_elim_offsets ();
4318 for (chain = reload_insn_chain; chain; chain = chain->next)
4321 rtx insn = chain->insn;
4322 rtx old_next = NEXT_INSN (insn);
4324 /* If we pass a label, copy the offsets from the label information
4325 into the current offsets of each elimination. */
4326 if (GET_CODE (insn) == CODE_LABEL)
4327 set_offsets_for_label (insn);
4329 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4331 rtx oldpat = PATTERN (insn);
4333 /* If this is a USE and CLOBBER of a MEM, ensure that any
4334 references to eliminable registers have been removed. */
4336 if ((GET_CODE (PATTERN (insn)) == USE
4337 || GET_CODE (PATTERN (insn)) == CLOBBER)
4338 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4339 XEXP (XEXP (PATTERN (insn), 0), 0)
4340 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4341 GET_MODE (XEXP (PATTERN (insn), 0)),
4344 /* If we need to do register elimination processing, do so.
4345 This might delete the insn, in which case we are done. */
4346 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4348 eliminate_regs_in_insn (insn, 1);
4349 if (GET_CODE (insn) == NOTE)
4351 update_eliminable_offsets ();
4356 /* If need_elim is nonzero but need_reload is zero, one might think
4357 that we could simply set n_reloads to 0. However, find_reloads
4358 could have done some manipulation of the insn (such as swapping
4359 commutative operands), and these manipulations are lost during
4360 the first pass for every insn that needs register elimination.
4361 So the actions of find_reloads must be redone here. */
4363 if (! chain->need_elim && ! chain->need_reload
4364 && ! chain->need_operand_change)
4366 /* First find the pseudo regs that must be reloaded for this insn.
4367 This info is returned in the tables reload_... (see reload.h).
4368 Also modify the body of INSN by substituting RELOAD
4369 rtx's for those pseudo regs. */
4372 bzero (reg_has_output_reload, max_regno);
4373 CLEAR_HARD_REG_SET (reg_is_output_reload);
4375 find_reloads (insn, 1, spill_indirect_levels, live_known,
4379 if (num_eliminable && chain->need_elim)
4380 update_eliminable_offsets ();
4384 rtx next = NEXT_INSN (insn);
4387 prev = PREV_INSN (insn);
4389 /* Now compute which reload regs to reload them into. Perhaps
4390 reusing reload regs from previous insns, or else output
4391 load insns to reload them. Maybe output store insns too.
4392 Record the choices of reload reg in reload_reg_rtx. */
4393 choose_reload_regs (chain);
4395 /* Merge any reloads that we didn't combine for fear of
4396 increasing the number of spill registers needed but now
4397 discover can be safely merged. */
4398 if (SMALL_REGISTER_CLASSES)
4399 merge_assigned_reloads (insn);
4401 /* Generate the insns to reload operands into or out of
4402 their reload regs. */
4403 emit_reload_insns (chain);
4405 /* Substitute the chosen reload regs from reload_reg_rtx
4406 into the insn's body (or perhaps into the bodies of other
4407 load and store insn that we just made for reloading
4408 and that we moved the structure into). */
4411 /* If this was an ASM, make sure that all the reload insns
4412 we have generated are valid. If not, give an error
4415 if (asm_noperands (PATTERN (insn)) >= 0)
4416 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4417 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4418 && (recog_memoized (p) < 0
4419 || (extract_insn (p), ! constrain_operands (1))))
4421 error_for_asm (insn,
4422 "`asm' operand requires impossible reload");
4424 NOTE_SOURCE_FILE (p) = 0;
4425 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4428 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4429 is no longer validly lying around to save a future reload.
4430 Note that this does not detect pseudos that were reloaded
4431 for this insn in order to be stored in
4432 (obeying register constraints). That is correct; such reload
4433 registers ARE still valid. */
4434 note_stores (oldpat, forget_old_reloads_1, NULL);
4436 /* There may have been CLOBBER insns placed after INSN. So scan
4437 between INSN and NEXT and use them to forget old reloads. */
4438 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4439 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4440 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4443 /* Likewise for regs altered by auto-increment in this insn.
4444 REG_INC notes have been changed by reloading:
4445 find_reloads_address_1 records substitutions for them,
4446 which have been performed by subst_reloads above. */
4447 for (i = n_reloads - 1; i >= 0; i--)
4449 rtx in_reg = rld[i].in_reg;
4452 enum rtx_code code = GET_CODE (in_reg);
4453 /* PRE_INC / PRE_DEC will have the reload register ending up
4454 with the same value as the stack slot, but that doesn't
4455 hold true for POST_INC / POST_DEC. Either we have to
4456 convert the memory access to a true POST_INC / POST_DEC,
4457 or we can't use the reload register for inheritance. */
4458 if ((code == POST_INC || code == POST_DEC)
4459 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4460 REGNO (rld[i].reg_rtx))
4461 /* Make sure it is the inc/dec pseudo, and not
4462 some other (e.g. output operand) pseudo. */
4463 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4464 == REGNO (XEXP (in_reg, 0))))
4467 rtx reload_reg = rld[i].reg_rtx;
4468 enum machine_mode mode = GET_MODE (reload_reg);
4472 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4474 /* We really want to ignore REG_INC notes here, so
4475 use PATTERN (p) as argument to reg_set_p . */
4476 if (reg_set_p (reload_reg, PATTERN (p)))
4478 n = count_occurrences (PATTERN (p), reload_reg);
4483 n = validate_replace_rtx (reload_reg,
4484 gen_rtx (code, mode,
4488 /* We must also verify that the constraints
4489 are met after the replacement. */
4492 n = constrain_operands (1);
4496 /* If the constraints were not met, then
4497 undo the replacement. */
4500 validate_replace_rtx (gen_rtx (code, mode,
4512 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4514 /* Mark this as having an output reload so that the
4515 REG_INC processing code below won't invalidate
4516 the reload for inheritance. */
4517 SET_HARD_REG_BIT (reg_is_output_reload,
4518 REGNO (reload_reg));
4519 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4522 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4525 else if ((code == PRE_INC || code == PRE_DEC)
4526 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4527 REGNO (rld[i].reg_rtx))
4528 /* Make sure it is the inc/dec pseudo, and not
4529 some other (e.g. output operand) pseudo. */
4530 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4531 == REGNO (XEXP (in_reg, 0))))
4533 SET_HARD_REG_BIT (reg_is_output_reload,
4534 REGNO (rld[i].reg_rtx));
4535 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4539 /* If a pseudo that got a hard register is auto-incremented,
4540 we must purge records of copying it into pseudos without
4542 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4543 if (REG_NOTE_KIND (x) == REG_INC)
4545 /* See if this pseudo reg was reloaded in this insn.
4546 If so, its last-reload info is still valid
4547 because it is based on this insn's reload. */
4548 for (i = 0; i < n_reloads; i++)
4549 if (rld[i].out == XEXP (x, 0))
4553 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4557 /* A reload reg's contents are unknown after a label. */
4558 if (GET_CODE (insn) == CODE_LABEL)
4559 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4561 /* Don't assume a reload reg is still good after a call insn
4562 if it is a call-used reg. */
4563 else if (GET_CODE (insn) == CALL_INSN)
4564 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4566 /* In case registers overlap, allow certain insns to invalidate
4567 particular hard registers. */
4569 #ifdef INSN_CLOBBERS_REGNO_P
4570 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4571 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4572 && INSN_CLOBBERS_REGNO_P (insn, i))
4573 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4578 free (reg_last_reload_reg);
4579 free (reg_has_output_reload);
4582 /* Discard all record of any value reloaded from X,
4583 or reloaded in X from someplace else;
4584 unless X is an output reload reg of the current insn.
4586 X may be a hard reg (the reload reg)
4587 or it may be a pseudo reg that was reloaded from. */
4590 forget_old_reloads_1 (x, ignored, data)
4592 rtx ignored ATTRIBUTE_UNUSED;
4593 void *data ATTRIBUTE_UNUSED;
4599 /* note_stores does give us subregs of hard regs. */
4600 while (GET_CODE (x) == SUBREG)
4602 offset += SUBREG_WORD (x);
4606 if (GET_CODE (x) != REG)
4609 regno = REGNO (x) + offset;
4611 if (regno >= FIRST_PSEUDO_REGISTER)
4616 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4617 /* Storing into a spilled-reg invalidates its contents.
4618 This can happen if a block-local pseudo is allocated to that reg
4619 and it wasn't spilled because this block's total need is 0.
4620 Then some insn might have an optional reload and use this reg. */
4621 for (i = 0; i < nr; i++)
4622 /* But don't do this if the reg actually serves as an output
4623 reload reg in the current instruction. */
4625 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4626 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4629 /* Since value of X has changed,
4630 forget any value previously copied from it. */
4633 /* But don't forget a copy if this is the output reload
4634 that establishes the copy's validity. */
4635 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4636 reg_last_reload_reg[regno + nr] = 0;
4639 /* Comparison function for qsort to decide which of two reloads
4640 should be handled first. *P1 and *P2 are the reload numbers. */
4643 reload_reg_class_lower (r1p, r2p)
4647 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
4650 /* Consider required reloads before optional ones. */
4651 t = rld[r1].optional - rld[r2].optional;
4655 /* Count all solitary classes before non-solitary ones. */
4656 t = ((reg_class_size[(int) rld[r2].class] == 1)
4657 - (reg_class_size[(int) rld[r1].class] == 1));
4661 /* Aside from solitaires, consider all multi-reg groups first. */
4662 t = rld[r2].nregs - rld[r1].nregs;
4666 /* Consider reloads in order of increasing reg-class number. */
4667 t = (int) rld[r1].class - (int) rld[r2].class;
4671 /* If reloads are equally urgent, sort by reload number,
4672 so that the results of qsort leave nothing to chance. */
4676 /* The following HARD_REG_SETs indicate when each hard register is
4677 used for a reload of various parts of the current insn. */
4679 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4680 static HARD_REG_SET reload_reg_used;
4681 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4682 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4683 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4684 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4685 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4686 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4687 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4688 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4689 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4690 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4691 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4692 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4693 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4694 static HARD_REG_SET reload_reg_used_in_op_addr;
4695 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4696 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4697 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4698 static HARD_REG_SET reload_reg_used_in_insn;
4699 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4700 static HARD_REG_SET reload_reg_used_in_other_addr;
4702 /* If reg is in use as a reload reg for any sort of reload. */
4703 static HARD_REG_SET reload_reg_used_at_all;
4705 /* If reg is use as an inherited reload. We just mark the first register
4707 static HARD_REG_SET reload_reg_used_for_inherit;
4709 /* Records which hard regs are used in any way, either as explicit use or
4710 by being allocated to a pseudo during any point of the current insn. */
4711 static HARD_REG_SET reg_used_in_insn;
4713 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4714 TYPE. MODE is used to indicate how many consecutive regs are
4718 mark_reload_reg_in_use (regno, opnum, type, mode)
4721 enum reload_type type;
4722 enum machine_mode mode;
4724 int nregs = HARD_REGNO_NREGS (regno, mode);
4727 for (i = regno; i < nregs + regno; i++)
4732 SET_HARD_REG_BIT (reload_reg_used, i);
4735 case RELOAD_FOR_INPUT_ADDRESS:
4736 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4739 case RELOAD_FOR_INPADDR_ADDRESS:
4740 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4743 case RELOAD_FOR_OUTPUT_ADDRESS:
4744 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4747 case RELOAD_FOR_OUTADDR_ADDRESS:
4748 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4751 case RELOAD_FOR_OPERAND_ADDRESS:
4752 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4755 case RELOAD_FOR_OPADDR_ADDR:
4756 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4759 case RELOAD_FOR_OTHER_ADDRESS:
4760 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4763 case RELOAD_FOR_INPUT:
4764 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4767 case RELOAD_FOR_OUTPUT:
4768 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4771 case RELOAD_FOR_INSN:
4772 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4776 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4780 /* Similarly, but show REGNO is no longer in use for a reload. */
4783 clear_reload_reg_in_use (regno, opnum, type, mode)
4786 enum reload_type type;
4787 enum machine_mode mode;
4789 int nregs = HARD_REGNO_NREGS (regno, mode);
4790 int start_regno, end_regno;
4792 /* A complication is that for some reload types, inheritance might
4793 allow multiple reloads of the same types to share a reload register.
4794 We set check_opnum if we have to check only reloads with the same
4795 operand number, and check_any if we have to check all reloads. */
4796 int check_opnum = 0;
4798 HARD_REG_SET *used_in_set;
4803 used_in_set = &reload_reg_used;
4806 case RELOAD_FOR_INPUT_ADDRESS:
4807 used_in_set = &reload_reg_used_in_input_addr[opnum];
4810 case RELOAD_FOR_INPADDR_ADDRESS:
4812 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4815 case RELOAD_FOR_OUTPUT_ADDRESS:
4816 used_in_set = &reload_reg_used_in_output_addr[opnum];
4819 case RELOAD_FOR_OUTADDR_ADDRESS:
4821 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4824 case RELOAD_FOR_OPERAND_ADDRESS:
4825 used_in_set = &reload_reg_used_in_op_addr;
4828 case RELOAD_FOR_OPADDR_ADDR:
4830 used_in_set = &reload_reg_used_in_op_addr_reload;
4833 case RELOAD_FOR_OTHER_ADDRESS:
4834 used_in_set = &reload_reg_used_in_other_addr;
4838 case RELOAD_FOR_INPUT:
4839 used_in_set = &reload_reg_used_in_input[opnum];
4842 case RELOAD_FOR_OUTPUT:
4843 used_in_set = &reload_reg_used_in_output[opnum];
4846 case RELOAD_FOR_INSN:
4847 used_in_set = &reload_reg_used_in_insn;
4852 /* We resolve conflicts with remaining reloads of the same type by
4853 excluding the intervals of of reload registers by them from the
4854 interval of freed reload registers. Since we only keep track of
4855 one set of interval bounds, we might have to exclude somewhat
4856 more then what would be necessary if we used a HARD_REG_SET here.
4857 But this should only happen very infrequently, so there should
4858 be no reason to worry about it. */
4860 start_regno = regno;
4861 end_regno = regno + nregs;
4862 if (check_opnum || check_any)
4864 for (i = n_reloads - 1; i >= 0; i--)
4866 if (rld[i].when_needed == type
4867 && (check_any || rld[i].opnum == opnum)
4870 int conflict_start = true_regnum (rld[i].reg_rtx);
4873 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4875 /* If there is an overlap with the first to-be-freed register,
4876 adjust the interval start. */
4877 if (conflict_start <= start_regno && conflict_end > start_regno)
4878 start_regno = conflict_end;
4879 /* Otherwise, if there is a conflict with one of the other
4880 to-be-freed registers, adjust the interval end. */
4881 if (conflict_start > start_regno && conflict_start < end_regno)
4882 end_regno = conflict_start;
4886 for (i = start_regno; i < end_regno; i++)
4887 CLEAR_HARD_REG_BIT (*used_in_set, i);
4890 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4891 specified by OPNUM and TYPE. */
4894 reload_reg_free_p (regno, opnum, type)
4897 enum reload_type type;
4901 /* In use for a RELOAD_OTHER means it's not available for anything. */
4902 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4908 /* In use for anything means we can't use it for RELOAD_OTHER. */
4909 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4910 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4911 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4914 for (i = 0; i < reload_n_operands; i++)
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4916 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4917 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4918 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4919 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4920 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4925 case RELOAD_FOR_INPUT:
4926 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4927 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4930 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4933 /* If it is used for some other input, can't use it. */
4934 for (i = 0; i < reload_n_operands; i++)
4935 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4938 /* If it is used in a later operand's address, can't use it. */
4939 for (i = opnum + 1; i < reload_n_operands; i++)
4940 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4941 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4946 case RELOAD_FOR_INPUT_ADDRESS:
4947 /* Can't use a register if it is used for an input address for this
4948 operand or used as an input in an earlier one. */
4949 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4950 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4953 for (i = 0; i < opnum; i++)
4954 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4959 case RELOAD_FOR_INPADDR_ADDRESS:
4960 /* Can't use a register if it is used for an input address
4961 for this operand or used as an input in an earlier
4963 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4966 for (i = 0; i < opnum; i++)
4967 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4972 case RELOAD_FOR_OUTPUT_ADDRESS:
4973 /* Can't use a register if it is used for an output address for this
4974 operand or used as an output in this or a later operand. */
4975 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4978 for (i = opnum; i < reload_n_operands; i++)
4979 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4984 case RELOAD_FOR_OUTADDR_ADDRESS:
4985 /* Can't use a register if it is used for an output address
4986 for this operand or used as an output in this or a
4988 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4991 for (i = opnum; i < reload_n_operands; i++)
4992 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4997 case RELOAD_FOR_OPERAND_ADDRESS:
4998 for (i = 0; i < reload_n_operands; i++)
4999 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5002 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5003 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5005 case RELOAD_FOR_OPADDR_ADDR:
5006 for (i = 0; i < reload_n_operands; i++)
5007 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5010 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5012 case RELOAD_FOR_OUTPUT:
5013 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5014 outputs, or an operand address for this or an earlier output. */
5015 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5018 for (i = 0; i < reload_n_operands; i++)
5019 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5022 for (i = 0; i <= opnum; i++)
5023 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5024 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5029 case RELOAD_FOR_INSN:
5030 for (i = 0; i < reload_n_operands; i++)
5031 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5032 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5035 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5036 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5038 case RELOAD_FOR_OTHER_ADDRESS:
5039 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5044 /* Return 1 if the value in reload reg REGNO, as used by a reload
5045 needed for the part of the insn specified by OPNUM and TYPE,
5046 is still available in REGNO at the end of the insn.
5048 We can assume that the reload reg was already tested for availability
5049 at the time it is needed, and we should not check this again,
5050 in case the reg has already been marked in use. */
5053 reload_reg_reaches_end_p (regno, opnum, type)
5056 enum reload_type type;
5063 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5064 its value must reach the end. */
5067 /* If this use is for part of the insn,
5068 its value reaches if no subsequent part uses the same register.
5069 Just like the above function, don't try to do this with lots
5072 case RELOAD_FOR_OTHER_ADDRESS:
5073 /* Here we check for everything else, since these don't conflict
5074 with anything else and everything comes later. */
5076 for (i = 0; i < reload_n_operands; i++)
5077 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5078 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5079 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5080 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5081 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5082 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5085 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5086 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5087 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5089 case RELOAD_FOR_INPUT_ADDRESS:
5090 case RELOAD_FOR_INPADDR_ADDRESS:
5091 /* Similar, except that we check only for this and subsequent inputs
5092 and the address of only subsequent inputs and we do not need
5093 to check for RELOAD_OTHER objects since they are known not to
5096 for (i = opnum; i < reload_n_operands; i++)
5097 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5100 for (i = opnum + 1; i < reload_n_operands; i++)
5101 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5102 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5105 for (i = 0; i < reload_n_operands; i++)
5106 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5107 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5108 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5111 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5114 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5115 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5117 case RELOAD_FOR_INPUT:
5118 /* Similar to input address, except we start at the next operand for
5119 both input and input address and we do not check for
5120 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5123 for (i = opnum + 1; i < reload_n_operands; i++)
5124 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5125 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5126 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5129 /* ... fall through ... */
5131 case RELOAD_FOR_OPERAND_ADDRESS:
5132 /* Check outputs and their addresses. */
5134 for (i = 0; i < reload_n_operands; i++)
5135 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5136 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5137 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5142 case RELOAD_FOR_OPADDR_ADDR:
5143 for (i = 0; i < reload_n_operands; i++)
5144 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5145 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5146 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5149 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5150 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5152 case RELOAD_FOR_INSN:
5153 /* These conflict with other outputs with RELOAD_OTHER. So
5154 we need only check for output addresses. */
5158 /* ... fall through ... */
5160 case RELOAD_FOR_OUTPUT:
5161 case RELOAD_FOR_OUTPUT_ADDRESS:
5162 case RELOAD_FOR_OUTADDR_ADDRESS:
5163 /* We already know these can't conflict with a later output. So the
5164 only thing to check are later output addresses. */
5165 for (i = opnum + 1; i < reload_n_operands; i++)
5166 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5167 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5176 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5179 This function uses the same algorithm as reload_reg_free_p above. */
5182 reloads_conflict (r1, r2)
5185 enum reload_type r1_type = rld[r1].when_needed;
5186 enum reload_type r2_type = rld[r2].when_needed;
5187 int r1_opnum = rld[r1].opnum;
5188 int r2_opnum = rld[r2].opnum;
5190 /* RELOAD_OTHER conflicts with everything. */
5191 if (r2_type == RELOAD_OTHER)
5194 /* Otherwise, check conflicts differently for each type. */
5198 case RELOAD_FOR_INPUT:
5199 return (r2_type == RELOAD_FOR_INSN
5200 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5201 || r2_type == RELOAD_FOR_OPADDR_ADDR
5202 || r2_type == RELOAD_FOR_INPUT
5203 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5204 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5205 && r2_opnum > r1_opnum));
5207 case RELOAD_FOR_INPUT_ADDRESS:
5208 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5209 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5211 case RELOAD_FOR_INPADDR_ADDRESS:
5212 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5213 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5215 case RELOAD_FOR_OUTPUT_ADDRESS:
5216 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5217 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5219 case RELOAD_FOR_OUTADDR_ADDRESS:
5220 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5221 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5223 case RELOAD_FOR_OPERAND_ADDRESS:
5224 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5225 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5227 case RELOAD_FOR_OPADDR_ADDR:
5228 return (r2_type == RELOAD_FOR_INPUT
5229 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5231 case RELOAD_FOR_OUTPUT:
5232 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5233 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5234 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5235 && r2_opnum >= r1_opnum));
5237 case RELOAD_FOR_INSN:
5238 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5239 || r2_type == RELOAD_FOR_INSN
5240 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5242 case RELOAD_FOR_OTHER_ADDRESS:
5243 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5253 /* Vector of reload-numbers showing the order in which the reloads should
5255 short reload_order[MAX_RELOADS];
5257 /* Indexed by reload number, 1 if incoming value
5258 inherited from previous insns. */
5259 char reload_inherited[MAX_RELOADS];
5261 /* For an inherited reload, this is the insn the reload was inherited from,
5262 if we know it. Otherwise, this is 0. */
5263 rtx reload_inheritance_insn[MAX_RELOADS];
5265 /* If non-zero, this is a place to get the value of the reload,
5266 rather than using reload_in. */
5267 rtx reload_override_in[MAX_RELOADS];
5269 /* For each reload, the hard register number of the register used,
5270 or -1 if we did not need a register for this reload. */
5271 int reload_spill_index[MAX_RELOADS];
5273 /* Return 1 if the value in reload reg REGNO, as used by a reload
5274 needed for the part of the insn specified by OPNUM and TYPE,
5275 may be used to load VALUE into it.
5277 Other read-only reloads with the same value do not conflict
5278 unless OUT is non-zero and these other reloads have to live while
5279 output reloads live.
5280 If OUT is CONST0_RTX, this is a special case: it means that the
5281 test should not be for using register REGNO as reload register, but
5282 for copying from register REGNO into the reload register.
5284 RELOADNUM is the number of the reload we want to load this value for;
5285 a reload does not conflict with itself.
5287 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5288 reloads that load an address for the very reload we are considering.
5290 The caller has to make sure that there is no conflict with the return
5293 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5294 ignore_address_reloads)
5297 enum reload_type type;
5300 int ignore_address_reloads;
5303 /* Set if we see an input reload that must not share its reload register
5304 with any new earlyclobber, but might otherwise share the reload
5305 register with an output or input-output reload. */
5306 int check_earlyclobber = 0;
5310 /* ??? reload_reg_used is abused to hold the registers that are not
5311 available as spill registers, including hard registers that are
5312 earlyclobbered in asms. As a temporary measure, reject anything
5313 in reload_reg_used. */
5314 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
5317 if (out == const0_rtx)
5323 /* We use some pseudo 'time' value to check if the lifetimes of the
5324 new register use would overlap with the one of a previous reload
5325 that is not read-only or uses a different value.
5326 The 'time' used doesn't have to be linear in any shape or form, just
5328 Some reload types use different 'buckets' for each operand.
5329 So there are MAX_RECOG_OPERANDS different time values for each
5331 We compute TIME1 as the time when the register for the prospective
5332 new reload ceases to be live, and TIME2 for each existing
5333 reload as the time when that the reload register of that reload
5335 Where there is little to be gained by exact lifetime calculations,
5336 we just make conservative assumptions, i.e. a longer lifetime;
5337 this is done in the 'default:' cases. */
5340 case RELOAD_FOR_OTHER_ADDRESS:
5341 /* RELOAD_FOR_OTHER_ADDRESS conflits with RELOAD_OTHER reloads. */
5342 time1 = copy ? 0 : 1;
5345 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5347 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5348 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5349 respectively, to the time values for these, we get distinct time
5350 values. To get distinct time values for each operand, we have to
5351 multiply opnum by at least three. We round that up to four because
5352 multiply by four is often cheaper. */
5353 case RELOAD_FOR_INPADDR_ADDRESS:
5354 time1 = opnum * 4 + 2;
5356 case RELOAD_FOR_INPUT_ADDRESS:
5357 time1 = opnum * 4 + 3;
5359 case RELOAD_FOR_INPUT:
5360 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5361 executes (inclusive). */
5362 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5364 case RELOAD_FOR_OPADDR_ADDR:
5366 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5367 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5369 case RELOAD_FOR_OPERAND_ADDRESS:
5370 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5372 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5374 case RELOAD_FOR_OUTADDR_ADDRESS:
5375 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5377 case RELOAD_FOR_OUTPUT_ADDRESS:
5378 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5381 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5384 for (i = 0; i < n_reloads; i++)
5386 rtx reg = rld[i].reg_rtx;
5387 if (reg && GET_CODE (reg) == REG
5388 && ((unsigned) regno - true_regnum (reg)
5389 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5392 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
5393 || rld[i].out || out)
5396 switch (rld[i].when_needed)
5398 case RELOAD_FOR_OTHER_ADDRESS:
5401 case RELOAD_FOR_INPADDR_ADDRESS:
5402 /* find_reloads makes sure that a
5403 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5404 by at most one - the first -
5405 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5406 address reload is inherited, the address address reload
5407 goes away, so we can ignore this conflict. */
5408 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5409 && ignore_address_reloads
5410 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5411 Then the address address is still needed to store
5412 back the new address. */
5413 && ! rld[reloadnum].out)
5415 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5416 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5418 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5419 && ignore_address_reloads
5420 /* Unless we are reloading an auto_inc expression. */
5421 && ! rld[reloadnum].out)
5423 time2 = rld[i].opnum * 4 + 2;
5425 case RELOAD_FOR_INPUT_ADDRESS:
5426 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5427 && ignore_address_reloads
5428 && ! rld[reloadnum].out)
5430 time2 = rld[i].opnum * 4 + 3;
5432 case RELOAD_FOR_INPUT:
5433 time2 = rld[i].opnum * 4 + 4;
5434 check_earlyclobber = 1;
5436 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5437 == MAX_RECOG_OPERAND * 4 */
5438 case RELOAD_FOR_OPADDR_ADDR:
5439 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5440 && ignore_address_reloads
5441 && ! rld[reloadnum].out)
5443 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5445 case RELOAD_FOR_OPERAND_ADDRESS:
5446 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5447 check_earlyclobber = 1;
5449 case RELOAD_FOR_INSN:
5450 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5452 case RELOAD_FOR_OUTPUT:
5453 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5454 instruction is executed. */
5455 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5457 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5458 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5460 case RELOAD_FOR_OUTADDR_ADDRESS:
5461 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5462 && ignore_address_reloads
5463 && ! rld[reloadnum].out)
5465 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5467 case RELOAD_FOR_OUTPUT_ADDRESS:
5468 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5471 /* If there is no conflict in the input part, handle this
5472 like an output reload. */
5473 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
5475 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5476 /* Earlyclobbered outputs must conflict with inputs. */
5477 if (earlyclobber_operand_p (rld[i].out))
5478 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5483 /* RELOAD_OTHER might be live beyond instruction execution,
5484 but this is not obvious when we set time2 = 1. So check
5485 here if there might be a problem with the new reload
5486 clobbering the register used by the RELOAD_OTHER. */
5494 && (! rld[i].in || rld[i].out
5495 || ! rtx_equal_p (rld[i].in, value)))
5496 || (out && rld[reloadnum].out_reg
5497 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5503 /* Earlyclobbered outputs must conflict with inputs. */
5504 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5510 /* Give an error message saying we failed to find a reload for INSN,
5511 and clear out reload R. */
5513 failed_reload (insn, r)
5517 if (asm_noperands (PATTERN (insn)) < 0)
5518 /* It's the compiler's fault. */
5519 fatal_insn ("Could not find a spill register", insn);
5521 /* It's the user's fault; the operand's mode and constraint
5522 don't match. Disable this reload so we don't crash in final. */
5523 error_for_asm (insn,
5524 "`asm' operand constraint incompatible with operand size");
5528 rld[r].optional = 1;
5529 rld[r].secondary_p = 1;
5532 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5533 for reload R. If it's valid, get an rtx for it. Return nonzero if
5536 set_reload_reg (i, r)
5540 rtx reg = spill_reg_rtx[i];
5542 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5543 spill_reg_rtx[i] = reg
5544 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5546 regno = true_regnum (reg);
5548 /* Detect when the reload reg can't hold the reload mode.
5549 This used to be one `if', but Sequent compiler can't handle that. */
5550 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5552 enum machine_mode test_mode = VOIDmode;
5554 test_mode = GET_MODE (rld[r].in);
5555 /* If rld[r].in has VOIDmode, it means we will load it
5556 in whatever mode the reload reg has: to wit, rld[r].mode.
5557 We have already tested that for validity. */
5558 /* Aside from that, we need to test that the expressions
5559 to reload from or into have modes which are valid for this
5560 reload register. Otherwise the reload insns would be invalid. */
5561 if (! (rld[r].in != 0 && test_mode != VOIDmode
5562 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5563 if (! (rld[r].out != 0
5564 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5566 /* The reg is OK. */
5569 /* Mark as in use for this insn the reload regs we use
5571 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5572 rld[r].when_needed, rld[r].mode);
5574 rld[r].reg_rtx = reg;
5575 reload_spill_index[r] = spill_regs[i];
5582 /* Find a spill register to use as a reload register for reload R.
5583 LAST_RELOAD is non-zero if this is the last reload for the insn being
5586 Set rld[R].reg_rtx to the register allocated.
5588 If NOERROR is nonzero, we return 1 if successful,
5589 or 0 if we couldn't find a spill reg and we didn't change anything. */
5592 allocate_reload_reg (chain, r, last_reload, noerror)
5593 struct insn_chain *chain;
5598 rtx insn = chain->insn;
5601 /* If we put this reload ahead, thinking it is a group,
5602 then insist on finding a group. Otherwise we can grab a
5603 reg that some other reload needs.
5604 (That can happen when we have a 68000 DATA_OR_FP_REG
5605 which is a group of data regs or one fp reg.)
5606 We need not be so restrictive if there are no more reloads
5609 ??? Really it would be nicer to have smarter handling
5610 for that kind of reg class, where a problem like this is normal.
5611 Perhaps those classes should be avoided for reloading
5612 by use of more alternatives. */
5614 int force_group = rld[r].nregs > 1 && ! last_reload;
5616 /* If we want a single register and haven't yet found one,
5617 take any reg in the right class and not in use.
5618 If we want a consecutive group, here is where we look for it.
5620 We use two passes so we can first look for reload regs to
5621 reuse, which are already in use for other reloads in this insn,
5622 and only then use additional registers.
5623 I think that maximizing reuse is needed to make sure we don't
5624 run out of reload regs. Suppose we have three reloads, and
5625 reloads A and B can share regs. These need two regs.
5626 Suppose A and B are given different regs.
5627 That leaves none for C. */
5628 for (pass = 0; pass < 2; pass++)
5630 /* I is the index in spill_regs.
5631 We advance it round-robin between insns to use all spill regs
5632 equally, so that inherited reloads have a chance
5633 of leapfrogging each other. Don't do this, however, when we have
5634 group needs and failure would be fatal; if we only have a relatively
5635 small number of spill registers, and more than one of them has
5636 group needs, then by starting in the middle, we may end up
5637 allocating the first one in such a way that we are not left with
5638 sufficient groups to handle the rest. */
5640 if (noerror || ! force_group)
5645 for (count = 0; count < n_spills; count++)
5647 int class = (int) rld[r].class;
5653 regnum = spill_regs[i];
5655 if ((reload_reg_free_p (regnum, rld[r].opnum,
5658 /* We check reload_reg_used to make sure we
5659 don't clobber the return register. */
5660 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5661 && reload_reg_free_for_value_p (regnum,
5666 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5667 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5668 /* Look first for regs to share, then for unshared. But
5669 don't share regs used for inherited reloads; they are
5670 the ones we want to preserve. */
5672 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5674 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5677 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5678 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5679 (on 68000) got us two FP regs. If NR is 1,
5680 we would reject both of them. */
5683 /* If we need only one reg, we have already won. */
5686 /* But reject a single reg if we demand a group. */
5691 /* Otherwise check that as many consecutive regs as we need
5693 Also, don't use for a group registers that are
5694 needed for nongroups. */
5695 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5698 int regno = regnum + nr - 1;
5699 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5700 && spill_reg_order[regno] >= 0
5701 && reload_reg_free_p (regno, rld[r].opnum,
5703 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5713 /* If we found something on pass 1, omit pass 2. */
5714 if (count < n_spills)
5718 /* We should have found a spill register by now. */
5719 if (count == n_spills)
5726 if (set_reload_reg (i, r))
5729 /* The reg is not OK. */
5734 failed_reload (insn, r);
5739 /* Initialize all the tables needed to allocate reload registers.
5740 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5741 is the array we use to restore the reg_rtx field for every reload. */
5743 choose_reload_regs_init (chain, save_reload_reg_rtx)
5744 struct insn_chain *chain;
5745 rtx *save_reload_reg_rtx;
5749 for (i = 0; i < n_reloads; i++)
5750 rld[i].reg_rtx = save_reload_reg_rtx[i];
5752 bzero (reload_inherited, MAX_RELOADS);
5753 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5754 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5756 CLEAR_HARD_REG_SET (reload_reg_used);
5757 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5758 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5759 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5760 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5761 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5763 CLEAR_HARD_REG_SET (reg_used_in_insn);
5766 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5767 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5768 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5769 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5770 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5771 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5773 for (i = 0; i < reload_n_operands; i++)
5775 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5776 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5777 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5778 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5779 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5780 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5783 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5785 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5787 for (i = 0; i < n_reloads; i++)
5788 /* If we have already decided to use a certain register,
5789 don't use it in another way. */
5791 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5792 rld[i].when_needed, rld[i].mode);
5795 /* Assign hard reg targets for the pseudo-registers we must reload
5796 into hard regs for this insn.
5797 Also output the instructions to copy them in and out of the hard regs.
5799 For machines with register classes, we are responsible for
5800 finding a reload reg in the proper class. */
5803 choose_reload_regs (chain)
5804 struct insn_chain *chain;
5806 rtx insn = chain->insn;
5808 int max_group_size = 1;
5809 enum reg_class group_class = NO_REGS;
5813 rtx save_reload_reg_rtx[MAX_RELOADS];
5815 /* In order to be certain of getting the registers we need,
5816 we must sort the reloads into order of increasing register class.
5817 Then our grabbing of reload registers will parallel the process
5818 that provided the reload registers.
5820 Also note whether any of the reloads wants a consecutive group of regs.
5821 If so, record the maximum size of the group desired and what
5822 register class contains all the groups needed by this insn. */
5824 for (j = 0; j < n_reloads; j++)
5826 reload_order[j] = j;
5827 reload_spill_index[j] = -1;
5829 if (rld[j].nregs > 1)
5831 max_group_size = MAX (rld[j].nregs, max_group_size);
5832 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5835 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5839 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5841 /* If -O, try first with inheritance, then turning it off.
5842 If not -O, don't do inheritance.
5843 Using inheritance when not optimizing leads to paradoxes
5844 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5845 because one side of the comparison might be inherited. */
5847 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5849 choose_reload_regs_init (chain, save_reload_reg_rtx);
5851 /* Process the reloads in order of preference just found.
5852 Beyond this point, subregs can be found in reload_reg_rtx.
5854 This used to look for an existing reloaded home for all
5855 of the reloads, and only then perform any new reloads.
5856 But that could lose if the reloads were done out of reg-class order
5857 because a later reload with a looser constraint might have an old
5858 home in a register needed by an earlier reload with a tighter constraint.
5860 To solve this, we make two passes over the reloads, in the order
5861 described above. In the first pass we try to inherit a reload
5862 from a previous insn. If there is a later reload that needs a
5863 class that is a proper subset of the class being processed, we must
5864 also allocate a spill register during the first pass.
5866 Then make a second pass over the reloads to allocate any reloads
5867 that haven't been given registers yet. */
5869 for (j = 0; j < n_reloads; j++)
5871 register int r = reload_order[j];
5872 rtx search_equiv = NULL_RTX;
5874 /* Ignore reloads that got marked inoperative. */
5875 if (rld[r].out == 0 && rld[r].in == 0
5876 && ! rld[r].secondary_p)
5879 /* If find_reloads chose to use reload_in or reload_out as a reload
5880 register, we don't need to chose one. Otherwise, try even if it
5881 found one since we might save an insn if we find the value lying
5883 Try also when reload_in is a pseudo without a hard reg. */
5884 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5885 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5886 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5887 && GET_CODE (rld[r].in) != MEM
5888 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5891 #if 0 /* No longer needed for correct operation.
5892 It might give better code, or might not; worth an experiment? */
5893 /* If this is an optional reload, we can't inherit from earlier insns
5894 until we are sure that any non-optional reloads have been allocated.
5895 The following code takes advantage of the fact that optional reloads
5896 are at the end of reload_order. */
5897 if (rld[r].optional != 0)
5898 for (i = 0; i < j; i++)
5899 if ((rld[reload_order[i]].out != 0
5900 || rld[reload_order[i]].in != 0
5901 || rld[reload_order[i]].secondary_p)
5902 && ! rld[reload_order[i]].optional
5903 && rld[reload_order[i]].reg_rtx == 0)
5904 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5907 /* First see if this pseudo is already available as reloaded
5908 for a previous insn. We cannot try to inherit for reloads
5909 that are smaller than the maximum number of registers needed
5910 for groups unless the register we would allocate cannot be used
5913 We could check here to see if this is a secondary reload for
5914 an object that is already in a register of the desired class.
5915 This would avoid the need for the secondary reload register.
5916 But this is complex because we can't easily determine what
5917 objects might want to be loaded via this reload. So let a
5918 register be allocated here. In `emit_reload_insns' we suppress
5919 one of the loads in the case described above. */
5924 register int regno = -1;
5925 enum machine_mode mode = VOIDmode;
5929 else if (GET_CODE (rld[r].in) == REG)
5931 regno = REGNO (rld[r].in);
5932 mode = GET_MODE (rld[r].in);
5934 else if (GET_CODE (rld[r].in_reg) == REG)
5936 regno = REGNO (rld[r].in_reg);
5937 mode = GET_MODE (rld[r].in_reg);
5939 else if (GET_CODE (rld[r].in_reg) == SUBREG
5940 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5942 word = SUBREG_WORD (rld[r].in_reg);
5943 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5944 if (regno < FIRST_PSEUDO_REGISTER)
5946 mode = GET_MODE (rld[r].in_reg);
5949 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5950 || GET_CODE (rld[r].in_reg) == PRE_DEC
5951 || GET_CODE (rld[r].in_reg) == POST_INC
5952 || GET_CODE (rld[r].in_reg) == POST_DEC)
5953 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5955 regno = REGNO (XEXP (rld[r].in_reg, 0));
5956 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5957 rld[r].out = rld[r].in;
5961 /* This won't work, since REGNO can be a pseudo reg number.
5962 Also, it takes much more hair to keep track of all the things
5963 that can invalidate an inherited reload of part of a pseudoreg. */
5964 else if (GET_CODE (rld[r].in) == SUBREG
5965 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5966 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5969 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5971 enum reg_class class = rld[r].class, last_class;
5972 rtx last_reg = reg_last_reload_reg[regno];
5974 i = REGNO (last_reg) + word;
5975 last_class = REGNO_REG_CLASS (i);
5976 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5977 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5978 && reg_reloaded_contents[i] == regno
5979 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5980 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5981 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5982 /* Even if we can't use this register as a reload
5983 register, we might use it for reload_override_in,
5984 if copying it to the desired class is cheap
5986 || ((REGISTER_MOVE_COST (last_class, class)
5987 < MEMORY_MOVE_COST (mode, class, 1))
5988 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5989 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5993 #ifdef SECONDARY_MEMORY_NEEDED
5994 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5999 && (rld[r].nregs == max_group_size
6000 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6002 && reload_reg_free_for_value_p (i, rld[r].opnum,
6007 /* If a group is needed, verify that all the subsequent
6008 registers still have their values intact. */
6010 = HARD_REGNO_NREGS (i, rld[r].mode);
6013 for (k = 1; k < nr; k++)
6014 if (reg_reloaded_contents[i + k] != regno
6015 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6022 last_reg = (GET_MODE (last_reg) == mode
6023 ? last_reg : gen_rtx_REG (mode, i));
6025 /* We found a register that contains the
6026 value we need. If this register is the
6027 same as an `earlyclobber' operand of the
6028 current insn, just mark it as a place to
6029 reload from since we can't use it as the
6030 reload register itself. */
6032 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6033 if (reg_overlap_mentioned_for_reload_p
6034 (reg_last_reload_reg[regno],
6035 reload_earlyclobbers[i1]))
6038 if (i1 != n_earlyclobbers
6039 || ! (reload_reg_free_for_value_p
6040 (i, rld[r].opnum, rld[r].when_needed,
6041 rld[r].in, rld[r].out, r, 1))
6042 /* Don't use it if we'd clobber a pseudo reg. */
6043 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6045 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6046 /* Don't clobber the frame pointer. */
6047 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
6048 /* Don't really use the inherited spill reg
6049 if we need it wider than we've got it. */
6050 || (GET_MODE_SIZE (rld[r].mode)
6051 > GET_MODE_SIZE (mode))
6052 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6055 /* If find_reloads chose reload_out as reload
6056 register, stay with it - that leaves the
6057 inherited register for subsequent reloads. */
6058 || (rld[r].out && rld[r].reg_rtx
6059 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6061 reload_override_in[r] = last_reg;
6062 reload_inheritance_insn[r]
6063 = reg_reloaded_insn[i];
6068 /* We can use this as a reload reg. */
6069 /* Mark the register as in use for this part of
6071 mark_reload_reg_in_use (i,
6075 rld[r].reg_rtx = last_reg;
6076 reload_inherited[r] = 1;
6077 reload_inheritance_insn[r]
6078 = reg_reloaded_insn[i];
6079 reload_spill_index[r] = i;
6080 for (k = 0; k < nr; k++)
6081 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6089 /* Here's another way to see if the value is already lying around. */
6092 && ! reload_inherited[r]
6094 && (CONSTANT_P (rld[r].in)
6095 || GET_CODE (rld[r].in) == PLUS
6096 || GET_CODE (rld[r].in) == REG
6097 || GET_CODE (rld[r].in) == MEM)
6098 && (rld[r].nregs == max_group_size
6099 || ! reg_classes_intersect_p (rld[r].class, group_class)))
6100 search_equiv = rld[r].in;
6101 /* If this is an output reload from a simple move insn, look
6102 if an equivalence for the input is available. */
6103 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6105 rtx set = single_set (insn);
6108 && rtx_equal_p (rld[r].out, SET_DEST (set))
6109 && CONSTANT_P (SET_SRC (set)))
6110 search_equiv = SET_SRC (set);
6116 = find_equiv_reg (search_equiv, insn, rld[r].class,
6117 -1, NULL_PTR, 0, rld[r].mode);
6122 if (GET_CODE (equiv) == REG)
6123 regno = REGNO (equiv);
6124 else if (GET_CODE (equiv) == SUBREG)
6126 /* This must be a SUBREG of a hard register.
6127 Make a new REG since this might be used in an
6128 address and not all machines support SUBREGs
6130 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6131 equiv = gen_rtx_REG (rld[r].mode, regno);
6137 /* If we found a spill reg, reject it unless it is free
6138 and of the desired class. */
6140 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6141 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
6145 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6149 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6152 /* We found a register that contains the value we need.
6153 If this register is the same as an `earlyclobber' operand
6154 of the current insn, just mark it as a place to reload from
6155 since we can't use it as the reload register itself. */
6158 for (i = 0; i < n_earlyclobbers; i++)
6159 if (reg_overlap_mentioned_for_reload_p (equiv,
6160 reload_earlyclobbers[i]))
6162 reload_override_in[r] = equiv;
6167 /* If the equiv register we have found is explicitly clobbered
6168 in the current insn, it depends on the reload type if we
6169 can use it, use it for reload_override_in, or not at all.
6170 In particular, we then can't use EQUIV for a
6171 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6173 if (equiv != 0 && regno_clobbered_p (regno, insn))
6175 switch (rld[r].when_needed)
6177 case RELOAD_FOR_OTHER_ADDRESS:
6178 case RELOAD_FOR_INPADDR_ADDRESS:
6179 case RELOAD_FOR_INPUT_ADDRESS:
6180 case RELOAD_FOR_OPADDR_ADDR:
6183 case RELOAD_FOR_INPUT:
6184 case RELOAD_FOR_OPERAND_ADDRESS:
6185 reload_override_in[r] = equiv;
6193 /* If we found an equivalent reg, say no code need be generated
6194 to load it, and use it as our reload reg. */
6195 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6197 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
6199 rld[r].reg_rtx = equiv;
6200 reload_inherited[r] = 1;
6202 /* If reg_reloaded_valid is not set for this register,
6203 there might be a stale spill_reg_store lying around.
6204 We must clear it, since otherwise emit_reload_insns
6205 might delete the store. */
6206 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6207 spill_reg_store[regno] = NULL_RTX;
6208 /* If any of the hard registers in EQUIV are spill
6209 registers, mark them as in use for this insn. */
6210 for (k = 0; k < nr; k++)
6212 i = spill_reg_order[regno + k];
6215 mark_reload_reg_in_use (regno, rld[r].opnum,
6218 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6225 /* If we found a register to use already, or if this is an optional
6226 reload, we are done. */
6227 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6230 #if 0 /* No longer needed for correct operation. Might or might not
6231 give better code on the average. Want to experiment? */
6233 /* See if there is a later reload that has a class different from our
6234 class that intersects our class or that requires less register
6235 than our reload. If so, we must allocate a register to this
6236 reload now, since that reload might inherit a previous reload
6237 and take the only available register in our class. Don't do this
6238 for optional reloads since they will force all previous reloads
6239 to be allocated. Also don't do this for reloads that have been
6242 for (i = j + 1; i < n_reloads; i++)
6244 int s = reload_order[i];
6246 if ((rld[s].in == 0 && rld[s].out == 0
6247 && ! rld[s].secondary_p)
6251 if ((rld[s].class != rld[r].class
6252 && reg_classes_intersect_p (rld[r].class,
6254 || rld[s].nregs < rld[r].nregs)
6261 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6265 /* Now allocate reload registers for anything non-optional that
6266 didn't get one yet. */
6267 for (j = 0; j < n_reloads; j++)
6269 register int r = reload_order[j];
6271 /* Ignore reloads that got marked inoperative. */
6272 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6275 /* Skip reloads that already have a register allocated or are
6277 if (rld[r].reg_rtx != 0 || rld[r].optional)
6280 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6284 /* If that loop got all the way, we have won. */
6288 /* Loop around and try without any inheritance. */
6291 /* If we thought we could inherit a reload, because it seemed that
6292 nothing else wanted the same reload register earlier in the insn,
6293 verify that assumption, now that all reloads have been assigned.
6294 Likewise for reloads where reload_override_in has been set. */
6296 /* If doing expensive optimizations, do one preliminary pass that doesn't
6297 cancel any inheritance, but removes reloads that have been needed only
6298 for reloads that we know can be inherited. */
6299 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6301 for (j = 0; j < n_reloads; j++)
6303 register int r = reload_order[j];
6305 if (reload_inherited[r] && rld[r].reg_rtx)
6306 check_reg = rld[r].reg_rtx;
6307 else if (reload_override_in[r]
6308 && (GET_CODE (reload_override_in[r]) == REG
6309 || GET_CODE (reload_override_in[r]) == SUBREG))
6310 check_reg = reload_override_in[r];
6313 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6317 (reload_inherited[r]
6318 ? rld[r].out : const0_rtx),
6323 reload_inherited[r] = 0;
6324 reload_override_in[r] = 0;
6326 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6327 reload_override_in, then we do not need its related
6328 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6329 likewise for other reload types.
6330 We handle this by removing a reload when its only replacement
6331 is mentioned in reload_in of the reload we are going to inherit.
6332 A special case are auto_inc expressions; even if the input is
6333 inherited, we still need the address for the output. We can
6334 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6335 If we suceeded removing some reload and we are doing a preliminary
6336 pass just to remove such reloads, make another pass, since the
6337 removal of one reload might allow us to inherit another one. */
6339 && rld[r].out != rld[r].in
6340 && remove_address_replacements (rld[r].in) && pass)
6345 /* Now that reload_override_in is known valid,
6346 actually override reload_in. */
6347 for (j = 0; j < n_reloads; j++)
6348 if (reload_override_in[j])
6349 rld[j].in = reload_override_in[j];
6351 /* If this reload won't be done because it has been cancelled or is
6352 optional and not inherited, clear reload_reg_rtx so other
6353 routines (such as subst_reloads) don't get confused. */
6354 for (j = 0; j < n_reloads; j++)
6355 if (rld[j].reg_rtx != 0
6356 && ((rld[j].optional && ! reload_inherited[j])
6357 || (rld[j].in == 0 && rld[j].out == 0
6358 && ! rld[j].secondary_p)))
6360 int regno = true_regnum (rld[j].reg_rtx);
6362 if (spill_reg_order[regno] >= 0)
6363 clear_reload_reg_in_use (regno, rld[j].opnum,
6364 rld[j].when_needed, rld[j].mode);
6368 /* Record which pseudos and which spill regs have output reloads. */
6369 for (j = 0; j < n_reloads; j++)
6371 register int r = reload_order[j];
6373 i = reload_spill_index[r];
6375 /* I is nonneg if this reload uses a register.
6376 If rld[r].reg_rtx is 0, this is an optional reload
6377 that we opted to ignore. */
6378 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
6379 && rld[r].reg_rtx != 0)
6381 register int nregno = REGNO (rld[r].out_reg);
6384 if (nregno < FIRST_PSEUDO_REGISTER)
6385 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
6388 reg_has_output_reload[nregno + nr] = 1;
6392 nr = HARD_REGNO_NREGS (i, rld[r].mode);
6394 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6397 if (rld[r].when_needed != RELOAD_OTHER
6398 && rld[r].when_needed != RELOAD_FOR_OUTPUT
6399 && rld[r].when_needed != RELOAD_FOR_INSN)
6405 /* Deallocate the reload register for reload R. This is called from
6406 remove_address_replacements. */
6408 deallocate_reload_reg (r)
6413 if (! rld[r].reg_rtx)
6415 regno = true_regnum (rld[r].reg_rtx);
6417 if (spill_reg_order[regno] >= 0)
6418 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6420 reload_spill_index[r] = -1;
6423 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6424 reloads of the same item for fear that we might not have enough reload
6425 registers. However, normally they will get the same reload register
6426 and hence actually need not be loaded twice.
6428 Here we check for the most common case of this phenomenon: when we have
6429 a number of reloads for the same object, each of which were allocated
6430 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6431 reload, and is not modified in the insn itself. If we find such,
6432 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6433 This will not increase the number of spill registers needed and will
6434 prevent redundant code. */
6437 merge_assigned_reloads (insn)
6442 /* Scan all the reloads looking for ones that only load values and
6443 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6444 assigned and not modified by INSN. */
6446 for (i = 0; i < n_reloads; i++)
6448 int conflicting_input = 0;
6449 int max_input_address_opnum = -1;
6450 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6452 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6453 || rld[i].out != 0 || rld[i].reg_rtx == 0
6454 || reg_set_p (rld[i].reg_rtx, insn))
6457 /* Look at all other reloads. Ensure that the only use of this
6458 reload_reg_rtx is in a reload that just loads the same value
6459 as we do. Note that any secondary reloads must be of the identical
6460 class since the values, modes, and result registers are the
6461 same, so we need not do anything with any secondary reloads. */
6463 for (j = 0; j < n_reloads; j++)
6465 if (i == j || rld[j].reg_rtx == 0
6466 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6470 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6471 && rld[j].opnum > max_input_address_opnum)
6472 max_input_address_opnum = rld[j].opnum;
6474 /* If the reload regs aren't exactly the same (e.g, different modes)
6475 or if the values are different, we can't merge this reload.
6476 But if it is an input reload, we might still merge
6477 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6479 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6480 || rld[j].out != 0 || rld[j].in == 0
6481 || ! rtx_equal_p (rld[i].in, rld[j].in))
6483 if (rld[j].when_needed != RELOAD_FOR_INPUT
6484 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6485 || rld[i].opnum > rld[j].opnum)
6486 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6488 conflicting_input = 1;
6489 if (min_conflicting_input_opnum > rld[j].opnum)
6490 min_conflicting_input_opnum = rld[j].opnum;
6494 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6495 we, in fact, found any matching reloads. */
6498 && max_input_address_opnum <= min_conflicting_input_opnum)
6500 for (j = 0; j < n_reloads; j++)
6501 if (i != j && rld[j].reg_rtx != 0
6502 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6503 && (! conflicting_input
6504 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6505 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6507 rld[i].when_needed = RELOAD_OTHER;
6509 reload_spill_index[j] = -1;
6510 transfer_replacements (i, j);
6513 /* If this is now RELOAD_OTHER, look for any reloads that load
6514 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6515 if they were for inputs, RELOAD_OTHER for outputs. Note that
6516 this test is equivalent to looking for reloads for this operand
6519 if (rld[i].when_needed == RELOAD_OTHER)
6520 for (j = 0; j < n_reloads; j++)
6522 && rld[i].when_needed != RELOAD_OTHER
6523 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6526 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6527 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6528 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6534 /* Output insns to reload values in and out of the chosen reload regs. */
6537 emit_reload_insns (chain)
6538 struct insn_chain *chain;
6540 rtx insn = chain->insn;
6543 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6544 rtx other_input_address_reload_insns = 0;
6545 rtx other_input_reload_insns = 0;
6546 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6547 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6548 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6549 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6550 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6551 rtx operand_reload_insns = 0;
6552 rtx other_operand_reload_insns = 0;
6553 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6554 rtx following_insn = NEXT_INSN (insn);
6555 rtx before_insn = PREV_INSN (insn);
6557 /* Values to be put in spill_reg_store are put here first. */
6558 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6559 HARD_REG_SET reg_reloaded_died;
6561 CLEAR_HARD_REG_SET (reg_reloaded_died);
6563 for (j = 0; j < reload_n_operands; j++)
6564 input_reload_insns[j] = input_address_reload_insns[j]
6565 = inpaddr_address_reload_insns[j]
6566 = output_reload_insns[j] = output_address_reload_insns[j]
6567 = outaddr_address_reload_insns[j]
6568 = other_output_reload_insns[j] = 0;
6570 /* Now output the instructions to copy the data into and out of the
6571 reload registers. Do these in the order that the reloads were reported,
6572 since reloads of base and index registers precede reloads of operands
6573 and the operands may need the base and index registers reloaded. */
6575 for (j = 0; j < n_reloads; j++)
6578 rtx oldequiv_reg = 0;
6579 rtx this_reload_insn = 0;
6580 int expect_occurrences = 1;
6583 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6584 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6586 old = (rld[j].in && GET_CODE (rld[j].in) == MEM
6587 ? rld[j].in_reg : rld[j].in);
6590 /* AUTO_INC reloads need to be handled even if inherited. We got an
6591 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6592 && (! reload_inherited[j] || (rld[j].out && ! rld[j].out_reg))
6593 && ! rtx_equal_p (rld[j].reg_rtx, old)
6594 && rld[j].reg_rtx != 0)
6596 register rtx reloadreg = rld[j].reg_rtx;
6598 enum machine_mode mode;
6601 /* Determine the mode to reload in.
6602 This is very tricky because we have three to choose from.
6603 There is the mode the insn operand wants (rld[J].inmode).
6604 There is the mode of the reload register RELOADREG.
6605 There is the intrinsic mode of the operand, which we could find
6606 by stripping some SUBREGs.
6607 It turns out that RELOADREG's mode is irrelevant:
6608 we can change that arbitrarily.
6610 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6611 then the reload reg may not support QImode moves, so use SImode.
6612 If foo is in memory due to spilling a pseudo reg, this is safe,
6613 because the QImode value is in the least significant part of a
6614 slot big enough for a SImode. If foo is some other sort of
6615 memory reference, then it is impossible to reload this case,
6616 so previous passes had better make sure this never happens.
6618 Then consider a one-word union which has SImode and one of its
6619 members is a float, being fetched as (SUBREG:SF union:SI).
6620 We must fetch that as SFmode because we could be loading into
6621 a float-only register. In this case OLD's mode is correct.
6623 Consider an immediate integer: it has VOIDmode. Here we need
6624 to get a mode from something else.
6626 In some cases, there is a fourth mode, the operand's
6627 containing mode. If the insn specifies a containing mode for
6628 this operand, it overrides all others.
6630 I am not sure whether the algorithm here is always right,
6631 but it does the right things in those cases. */
6633 mode = GET_MODE (old);
6634 if (mode == VOIDmode)
6635 mode = rld[j].inmode;
6637 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6638 /* If we need a secondary register for this operation, see if
6639 the value is already in a register in that class. Don't
6640 do this if the secondary register will be used as a scratch
6643 if (rld[j].secondary_in_reload >= 0
6644 && rld[j].secondary_in_icode == CODE_FOR_nothing
6647 = find_equiv_reg (old, insn,
6648 rld[rld[j].secondary_in_reload].class,
6649 -1, NULL_PTR, 0, mode);
6652 /* If reloading from memory, see if there is a register
6653 that already holds the same value. If so, reload from there.
6654 We can pass 0 as the reload_reg_p argument because
6655 any other reload has either already been emitted,
6656 in which case find_equiv_reg will see the reload-insn,
6657 or has yet to be emitted, in which case it doesn't matter
6658 because we will use this equiv reg right away. */
6660 if (oldequiv == 0 && optimize
6661 && (GET_CODE (old) == MEM
6662 || (GET_CODE (old) == REG
6663 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6664 && reg_renumber[REGNO (old)] < 0)))
6665 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6666 -1, NULL_PTR, 0, mode);
6670 int regno = true_regnum (oldequiv);
6672 /* Don't use OLDEQUIV if any other reload changes it at an
6673 earlier stage of this insn or at this stage. */
6674 if (! reload_reg_free_for_value_p (regno, rld[j].opnum,
6676 rld[j].in, const0_rtx, j,
6680 /* If it is no cheaper to copy from OLDEQUIV into the
6681 reload register than it would be to move from memory,
6682 don't use it. Likewise, if we need a secondary register
6686 && ((REGNO_REG_CLASS (regno) != rld[j].class
6687 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6689 >= MEMORY_MOVE_COST (mode, rld[j].class, 1)))
6690 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6691 || (SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6695 #ifdef SECONDARY_MEMORY_NEEDED
6696 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6704 /* delete_output_reload is only invoked properly if old contains
6705 the original pseudo register. Since this is replaced with a
6706 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6707 find the pseudo in RELOAD_IN_REG. */
6709 && reload_override_in[j]
6710 && GET_CODE (rld[j].in_reg) == REG)
6713 old = rld[j].in_reg;
6717 else if (GET_CODE (oldequiv) == REG)
6718 oldequiv_reg = oldequiv;
6719 else if (GET_CODE (oldequiv) == SUBREG)
6720 oldequiv_reg = SUBREG_REG (oldequiv);
6722 /* If we are reloading from a register that was recently stored in
6723 with an output-reload, see if we can prove there was
6724 actually no need to store the old value in it. */
6726 if (optimize && GET_CODE (oldequiv) == REG
6727 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6728 && spill_reg_store[REGNO (oldequiv)]
6729 && GET_CODE (old) == REG
6730 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6731 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6733 delete_output_reload (insn, j, REGNO (oldequiv));
6735 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6736 then load RELOADREG from OLDEQUIV. Note that we cannot use
6737 gen_lowpart_common since it can do the wrong thing when
6738 RELOADREG has a multi-word mode. Note that RELOADREG
6739 must always be a REG here. */
6741 if (GET_MODE (reloadreg) != mode)
6742 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6743 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6744 oldequiv = SUBREG_REG (oldequiv);
6745 if (GET_MODE (oldequiv) != VOIDmode
6746 && mode != GET_MODE (oldequiv))
6747 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6749 /* Switch to the right place to emit the reload insns. */
6750 switch (rld[j].when_needed)
6753 where = &other_input_reload_insns;
6755 case RELOAD_FOR_INPUT:
6756 where = &input_reload_insns[rld[j].opnum];
6758 case RELOAD_FOR_INPUT_ADDRESS:
6759 where = &input_address_reload_insns[rld[j].opnum];
6761 case RELOAD_FOR_INPADDR_ADDRESS:
6762 where = &inpaddr_address_reload_insns[rld[j].opnum];
6764 case RELOAD_FOR_OUTPUT_ADDRESS:
6765 where = &output_address_reload_insns[rld[j].opnum];
6767 case RELOAD_FOR_OUTADDR_ADDRESS:
6768 where = &outaddr_address_reload_insns[rld[j].opnum];
6770 case RELOAD_FOR_OPERAND_ADDRESS:
6771 where = &operand_reload_insns;
6773 case RELOAD_FOR_OPADDR_ADDR:
6774 where = &other_operand_reload_insns;
6776 case RELOAD_FOR_OTHER_ADDRESS:
6777 where = &other_input_address_reload_insns;
6783 push_to_sequence (*where);
6786 /* Auto-increment addresses must be reloaded in a special way. */
6787 if (rld[j].out && ! rld[j].out_reg)
6789 /* We are not going to bother supporting the case where a
6790 incremented register can't be copied directly from
6791 OLDEQUIV since this seems highly unlikely. */
6792 if (rld[j].secondary_in_reload >= 0)
6795 if (reload_inherited[j])
6796 oldequiv = reloadreg;
6798 old = XEXP (rld[j].in_reg, 0);
6800 if (optimize && GET_CODE (oldequiv) == REG
6801 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6802 && spill_reg_store[REGNO (oldequiv)]
6803 && GET_CODE (old) == REG
6804 && (dead_or_set_p (insn,
6805 spill_reg_stored_to[REGNO (oldequiv)])
6806 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6808 delete_output_reload (insn, j, REGNO (oldequiv));
6810 /* Prevent normal processing of this reload. */
6812 /* Output a special code sequence for this case. */
6813 new_spill_reg_store[REGNO (reloadreg)]
6814 = inc_for_reload (reloadreg, oldequiv, rld[j].out,
6818 /* If we are reloading a pseudo-register that was set by the previous
6819 insn, see if we can get rid of that pseudo-register entirely
6820 by redirecting the previous insn into our reload register. */
6822 else if (optimize && GET_CODE (old) == REG
6823 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6824 && dead_or_set_p (insn, old)
6825 /* This is unsafe if some other reload
6826 uses the same reg first. */
6827 && reload_reg_free_for_value_p (REGNO (reloadreg),
6833 rtx temp = PREV_INSN (insn);
6834 while (temp && GET_CODE (temp) == NOTE)
6835 temp = PREV_INSN (temp);
6837 && GET_CODE (temp) == INSN
6838 && GET_CODE (PATTERN (temp)) == SET
6839 && SET_DEST (PATTERN (temp)) == old
6840 /* Make sure we can access insn_operand_constraint. */
6841 && asm_noperands (PATTERN (temp)) < 0
6842 /* This is unsafe if prev insn rejects our reload reg. */
6843 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6845 /* This is unsafe if operand occurs more than once in current
6846 insn. Perhaps some occurrences aren't reloaded. */
6847 && count_occurrences (PATTERN (insn), old) == 1
6848 /* Don't risk splitting a matching pair of operands. */
6849 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6851 /* Store into the reload register instead of the pseudo. */
6852 SET_DEST (PATTERN (temp)) = reloadreg;
6854 /* If the previous insn is an output reload, the source is
6855 a reload register, and its spill_reg_store entry will
6856 contain the previous destination. This is now
6858 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6859 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6861 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6862 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6865 /* If these are the only uses of the pseudo reg,
6866 pretend for GDB it lives in the reload reg we used. */
6867 if (REG_N_DEATHS (REGNO (old)) == 1
6868 && REG_N_SETS (REGNO (old)) == 1)
6870 reg_renumber[REGNO (old)] = REGNO (rld[j].reg_rtx);
6871 alter_reg (REGNO (old), -1);
6877 /* We can't do that, so output an insn to load RELOADREG. */
6881 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6882 rtx second_reload_reg = 0;
6883 enum insn_code icode;
6885 /* If we have a secondary reload, pick up the secondary register
6886 and icode, if any. If OLDEQUIV and OLD are different or
6887 if this is an in-out reload, recompute whether or not we
6888 still need a secondary register and what the icode should
6889 be. If we still need a secondary register and the class or
6890 icode is different, go back to reloading from OLD if using
6891 OLDEQUIV means that we got the wrong type of register. We
6892 cannot have different class or icode due to an in-out reload
6893 because we don't make such reloads when both the input and
6894 output need secondary reload registers. */
6896 if (rld[j].secondary_in_reload >= 0)
6898 int secondary_reload = rld[j].secondary_in_reload;
6899 rtx real_oldequiv = oldequiv;
6903 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6904 and similarly for OLD.
6905 See comments in get_secondary_reload in reload.c. */
6906 /* If it is a pseudo that cannot be replaced with its
6907 equivalent MEM, we must fall back to reload_in, which
6908 will have all the necessary substitutions registered.
6909 Likewise for a pseudo that can't be replaced with its
6910 equivalent constant.
6912 Take extra care for subregs of such pseudos. Note that
6913 we cannot use reg_equiv_mem in this case because it is
6914 not in the right mode. */
6917 if (GET_CODE (tmp) == SUBREG)
6918 tmp = SUBREG_REG (tmp);
6919 if (GET_CODE (tmp) == REG
6920 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6921 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6922 || reg_equiv_constant[REGNO (tmp)] != 0))
6924 if (! reg_equiv_mem[REGNO (tmp)]
6925 || num_not_at_initial_offset
6926 || GET_CODE (oldequiv) == SUBREG)
6927 real_oldequiv = rld[j].in;
6929 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6933 if (GET_CODE (tmp) == SUBREG)
6934 tmp = SUBREG_REG (tmp);
6935 if (GET_CODE (tmp) == REG
6936 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6937 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6938 || reg_equiv_constant[REGNO (tmp)] != 0))
6940 if (! reg_equiv_mem[REGNO (tmp)]
6941 || num_not_at_initial_offset
6942 || GET_CODE (old) == SUBREG)
6943 real_old = rld[j].in;
6945 real_old = reg_equiv_mem[REGNO (tmp)];
6948 second_reload_reg = rld[secondary_reload].reg_rtx;
6949 icode = rld[j].secondary_in_icode;
6951 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6952 || (rld[j].in != 0 && rld[j].out != 0))
6954 enum reg_class new_class
6955 = SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6956 mode, real_oldequiv);
6958 if (new_class == NO_REGS)
6959 second_reload_reg = 0;
6962 enum insn_code new_icode;
6963 enum machine_mode new_mode;
6965 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6966 REGNO (second_reload_reg)))
6967 oldequiv = old, real_oldequiv = real_old;
6970 new_icode = reload_in_optab[(int) mode];
6971 if (new_icode != CODE_FOR_nothing
6972 && ((insn_data[(int) new_icode].operand[0].predicate
6973 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6975 || (insn_data[(int) new_icode].operand[1].predicate
6976 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6977 (real_oldequiv, mode)))))
6978 new_icode = CODE_FOR_nothing;
6980 if (new_icode == CODE_FOR_nothing)
6983 new_mode = insn_data[(int) new_icode].operand[2].mode;
6985 if (GET_MODE (second_reload_reg) != new_mode)
6987 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6989 oldequiv = old, real_oldequiv = real_old;
6992 = gen_rtx_REG (new_mode,
6993 REGNO (second_reload_reg));
6999 /* If we still need a secondary reload register, check
7000 to see if it is being used as a scratch or intermediate
7001 register and generate code appropriately. If we need
7002 a scratch register, use REAL_OLDEQUIV since the form of
7003 the insn may depend on the actual address if it is
7006 if (second_reload_reg)
7008 if (icode != CODE_FOR_nothing)
7010 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7011 second_reload_reg));
7016 /* See if we need a scratch register to load the
7017 intermediate register (a tertiary reload). */
7018 enum insn_code tertiary_icode
7019 = rld[secondary_reload].secondary_in_icode;
7021 if (tertiary_icode != CODE_FOR_nothing)
7023 rtx third_reload_reg
7024 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
7026 emit_insn ((GEN_FCN (tertiary_icode)
7027 (second_reload_reg, real_oldequiv,
7028 third_reload_reg)));
7031 gen_reload (second_reload_reg, real_oldequiv,
7033 rld[j].when_needed);
7035 oldequiv = second_reload_reg;
7041 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7043 rtx real_oldequiv = oldequiv;
7045 if ((GET_CODE (oldequiv) == REG
7046 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7047 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7048 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7049 || (GET_CODE (oldequiv) == SUBREG
7050 && GET_CODE (SUBREG_REG (oldequiv)) == REG
7051 && (REGNO (SUBREG_REG (oldequiv))
7052 >= FIRST_PSEUDO_REGISTER)
7053 && ((reg_equiv_memory_loc
7054 [REGNO (SUBREG_REG (oldequiv))] != 0)
7055 || (reg_equiv_constant
7056 [REGNO (SUBREG_REG (oldequiv))] != 0))))
7057 real_oldequiv = rld[j].in;
7058 gen_reload (reloadreg, real_oldequiv, rld[j].opnum,
7059 rld[j].when_needed);
7064 this_reload_insn = get_last_insn ();
7065 /* End this sequence. */
7066 *where = get_insns ();
7069 /* Update reload_override_in so that delete_address_reloads_1
7070 can see the actual register usage. */
7072 reload_override_in[j] = oldequiv;
7075 /* When inheriting a wider reload, we have a MEM in rld[j].in,
7076 e.g. inheriting a SImode output reload for
7077 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7078 if (optimize && reload_inherited[j] && rld[j].in
7079 && GET_CODE (rld[j].in) == MEM
7080 && GET_CODE (rld[j].in_reg) == MEM
7081 && reload_spill_index[j] >= 0
7082 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7085 = count_occurrences (PATTERN (insn), rld[j].in) == 1 ? 0 : -1;
7087 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7090 /* If we are reloading a register that was recently stored in with an
7091 output-reload, see if we can prove there was
7092 actually no need to store the old value in it. */
7095 && (reload_inherited[j] || reload_override_in[j])
7097 && GET_CODE (rld[j].reg_rtx) == REG
7098 && spill_reg_store[REGNO (rld[j].reg_rtx)] != 0
7100 /* There doesn't seem to be any reason to restrict this to pseudos
7101 and doing so loses in the case where we are copying from a
7102 register of the wrong class. */
7103 && (REGNO (spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
7104 >= FIRST_PSEUDO_REGISTER)
7106 /* The insn might have already some references to stackslots
7107 replaced by MEMs, while reload_out_reg still names the
7109 && (dead_or_set_p (insn,
7110 spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
7111 || rtx_equal_p (spill_reg_stored_to[REGNO (rld[j].reg_rtx)],
7113 delete_output_reload (insn, j, REGNO (rld[j].reg_rtx));
7115 /* Input-reloading is done. Now do output-reloading,
7116 storing the value from the reload-register after the main insn
7117 if rld[j].out is nonzero.
7119 ??? At some point we need to support handling output reloads of
7120 JUMP_INSNs or insns that set cc0. */
7122 /* If this is an output reload that stores something that is
7123 not loaded in this same reload, see if we can eliminate a previous
7126 rtx pseudo = rld[j].out_reg;
7129 && GET_CODE (pseudo) == REG
7130 && ! rtx_equal_p (rld[j].in_reg, pseudo)
7131 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7132 && reg_last_reload_reg[REGNO (pseudo)])
7134 int pseudo_no = REGNO (pseudo);
7135 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7137 /* We don't need to test full validity of last_regno for
7138 inherit here; we only want to know if the store actually
7139 matches the pseudo. */
7140 if (reg_reloaded_contents[last_regno] == pseudo_no
7141 && spill_reg_store[last_regno]
7142 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7143 delete_output_reload (insn, j, last_regno);
7147 old = rld[j].out_reg;
7149 && rld[j].reg_rtx != old
7150 && rld[j].reg_rtx != 0)
7152 register rtx reloadreg = rld[j].reg_rtx;
7153 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7154 register rtx second_reloadreg = 0;
7157 enum machine_mode mode;
7160 /* An output operand that dies right away does need a reload,
7161 but need not be copied from it. Show the new location in the
7163 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7164 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7166 XEXP (note, 0) = rld[j].reg_rtx;
7169 /* Likewise for a SUBREG of an operand that dies. */
7170 else if (GET_CODE (old) == SUBREG
7171 && GET_CODE (SUBREG_REG (old)) == REG
7172 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7175 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7179 else if (GET_CODE (old) == SCRATCH)
7180 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7181 but we don't want to make an output reload. */
7185 /* Strip off of OLD any size-increasing SUBREGs such as
7186 (SUBREG:SI foo:QI 0). */
7188 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7189 && (GET_MODE_SIZE (GET_MODE (old))
7190 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7191 old = SUBREG_REG (old);
7194 /* If is a JUMP_INSN, we can't support output reloads yet. */
7195 if (GET_CODE (insn) == JUMP_INSN)
7198 if (rld[j].when_needed == RELOAD_OTHER)
7201 push_to_sequence (output_reload_insns[rld[j].opnum]);
7205 /* Determine the mode to reload in.
7206 See comments above (for input reloading). */
7208 mode = GET_MODE (old);
7209 if (mode == VOIDmode)
7211 /* VOIDmode should never happen for an output. */
7212 if (asm_noperands (PATTERN (insn)) < 0)
7213 /* It's the compiler's fault. */
7214 fatal_insn ("VOIDmode on an output", insn);
7215 error_for_asm (insn, "output operand is constant in `asm'");
7216 /* Prevent crash--use something we know is valid. */
7218 old = gen_rtx_REG (mode, REGNO (reloadreg));
7221 if (GET_MODE (reloadreg) != mode)
7222 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7224 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7226 /* If we need two reload regs, set RELOADREG to the intermediate
7227 one, since it will be stored into OLD. We might need a secondary
7228 register only for an input reload, so check again here. */
7230 if (rld[j].secondary_out_reload >= 0)
7234 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7235 && reg_equiv_mem[REGNO (old)] != 0)
7236 real_old = reg_equiv_mem[REGNO (old)];
7238 if((SECONDARY_OUTPUT_RELOAD_CLASS (rld[j].class,
7242 second_reloadreg = reloadreg;
7243 reloadreg = rld[rld[j].secondary_out_reload].reg_rtx;
7245 /* See if RELOADREG is to be used as a scratch register
7246 or as an intermediate register. */
7247 if (rld[j].secondary_out_icode != CODE_FOR_nothing)
7249 emit_insn ((GEN_FCN (rld[j].secondary_out_icode)
7250 (real_old, second_reloadreg, reloadreg)));
7255 /* See if we need both a scratch and intermediate reload
7258 int secondary_reload = rld[j].secondary_out_reload;
7259 enum insn_code tertiary_icode
7260 = rld[secondary_reload].secondary_out_icode;
7262 if (GET_MODE (reloadreg) != mode)
7263 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7265 if (tertiary_icode != CODE_FOR_nothing)
7268 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
7271 /* Copy primary reload reg to secondary reload reg.
7272 (Note that these have been swapped above, then
7273 secondary reload reg to OLD using our insn. */
7275 /* If REAL_OLD is a paradoxical SUBREG, remove it
7276 and try to put the opposite SUBREG on
7278 if (GET_CODE (real_old) == SUBREG
7279 && (GET_MODE_SIZE (GET_MODE (real_old))
7280 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7281 && 0 != (tem = gen_lowpart_common
7282 (GET_MODE (SUBREG_REG (real_old)),
7284 real_old = SUBREG_REG (real_old), reloadreg = tem;
7286 gen_reload (reloadreg, second_reloadreg,
7287 rld[j].opnum, rld[j].when_needed);
7288 emit_insn ((GEN_FCN (tertiary_icode)
7289 (real_old, reloadreg, third_reloadreg)));
7294 /* Copy between the reload regs here and then to
7297 gen_reload (reloadreg, second_reloadreg,
7298 rld[j].opnum, rld[j].when_needed);
7304 /* Output the last reload insn. */
7309 /* Don't output the last reload if OLD is not the dest of
7310 INSN and is in the src and is clobbered by INSN. */
7311 if (! flag_expensive_optimizations
7312 || GET_CODE (old) != REG
7313 || !(set = single_set (insn))
7314 || rtx_equal_p (old, SET_DEST (set))
7315 || !reg_mentioned_p (old, SET_SRC (set))
7316 || !regno_clobbered_p (REGNO (old), insn))
7317 gen_reload (old, reloadreg, rld[j].opnum,
7318 rld[j].when_needed);
7321 /* Look at all insns we emitted, just to be safe. */
7322 for (p = get_insns (); p; p = NEXT_INSN (p))
7323 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7325 rtx pat = PATTERN (p);
7327 /* If this output reload doesn't come from a spill reg,
7328 clear any memory of reloaded copies of the pseudo reg.
7329 If this output reload comes from a spill reg,
7330 reg_has_output_reload will make this do nothing. */
7331 note_stores (pat, forget_old_reloads_1, NULL);
7333 if (reg_mentioned_p (rld[j].reg_rtx, pat))
7335 rtx set = single_set (insn);
7336 if (reload_spill_index[j] < 0
7338 && SET_SRC (set) == rld[j].reg_rtx)
7340 int src = REGNO (SET_SRC (set));
7342 reload_spill_index[j] = src;
7343 SET_HARD_REG_BIT (reg_is_output_reload, src);
7344 if (find_regno_note (insn, REG_DEAD, src))
7345 SET_HARD_REG_BIT (reg_reloaded_died, src);
7347 if (REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7349 int s = rld[j].secondary_out_reload;
7350 set = single_set (p);
7351 /* If this reload copies only to the secondary reload
7352 register, the secondary reload does the actual
7354 if (s >= 0 && set == NULL_RTX)
7355 ; /* We can't tell what function the secondary reload
7356 has and where the actual store to the pseudo is
7357 made; leave new_spill_reg_store alone. */
7359 && SET_SRC (set) == rld[j].reg_rtx
7360 && SET_DEST (set) == rld[s].reg_rtx)
7362 /* Usually the next instruction will be the
7363 secondary reload insn; if we can confirm
7364 that it is, setting new_spill_reg_store to
7365 that insn will allow an extra optimization. */
7366 rtx s_reg = rld[s].reg_rtx;
7367 rtx next = NEXT_INSN (p);
7368 rld[s].out = rld[j].out;
7369 rld[s].out_reg = rld[j].out_reg;
7370 set = single_set (next);
7371 if (set && SET_SRC (set) == s_reg
7372 && ! new_spill_reg_store[REGNO (s_reg)])
7374 SET_HARD_REG_BIT (reg_is_output_reload,
7376 new_spill_reg_store[REGNO (s_reg)] = next;
7380 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = p;
7385 if (rld[j].when_needed == RELOAD_OTHER)
7387 emit_insns (other_output_reload_insns[rld[j].opnum]);
7388 other_output_reload_insns[rld[j].opnum] = get_insns ();
7391 output_reload_insns[rld[j].opnum] = get_insns ();
7397 /* Now write all the insns we made for reloads in the order expected by
7398 the allocation functions. Prior to the insn being reloaded, we write
7399 the following reloads:
7401 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7403 RELOAD_OTHER reloads.
7405 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7406 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7407 RELOAD_FOR_INPUT reload for the operand.
7409 RELOAD_FOR_OPADDR_ADDRS reloads.
7411 RELOAD_FOR_OPERAND_ADDRESS reloads.
7413 After the insn being reloaded, we write the following:
7415 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7416 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7417 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7418 reloads for the operand. The RELOAD_OTHER output reloads are
7419 output in descending order by reload number. */
7421 emit_insns_before (other_input_address_reload_insns, insn);
7422 emit_insns_before (other_input_reload_insns, insn);
7424 for (j = 0; j < reload_n_operands; j++)
7426 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7427 emit_insns_before (input_address_reload_insns[j], insn);
7428 emit_insns_before (input_reload_insns[j], insn);
7431 emit_insns_before (other_operand_reload_insns, insn);
7432 emit_insns_before (operand_reload_insns, insn);
7434 for (j = 0; j < reload_n_operands; j++)
7436 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7437 emit_insns_before (output_address_reload_insns[j], following_insn);
7438 emit_insns_before (output_reload_insns[j], following_insn);
7439 emit_insns_before (other_output_reload_insns[j], following_insn);
7442 /* Keep basic block info up to date. */
7445 if (BLOCK_HEAD (chain->block) == insn)
7446 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7447 if (BLOCK_END (chain->block) == insn)
7448 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7451 /* For all the spill regs newly reloaded in this instruction,
7452 record what they were reloaded from, so subsequent instructions
7453 can inherit the reloads.
7455 Update spill_reg_store for the reloads of this insn.
7456 Copy the elements that were updated in the loop above. */
7458 for (j = 0; j < n_reloads; j++)
7460 register int r = reload_order[j];
7461 register int i = reload_spill_index[r];
7463 /* If this is a non-inherited input reload from a pseudo, we must
7464 clear any memory of a previous store to the same pseudo. Only do
7465 something if there will not be an output reload for the pseudo
7467 if (rld[r].in_reg != 0
7468 && ! (reload_inherited[r] || reload_override_in[r]))
7470 rtx reg = rld[r].in_reg;
7472 if (GET_CODE (reg) == SUBREG)
7473 reg = SUBREG_REG (reg);
7475 if (GET_CODE (reg) == REG
7476 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7477 && ! reg_has_output_reload[REGNO (reg)])
7479 int nregno = REGNO (reg);
7481 if (reg_last_reload_reg[nregno])
7483 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7485 if (reg_reloaded_contents[last_regno] == nregno)
7486 spill_reg_store[last_regno] = 0;
7491 /* I is nonneg if this reload used a register.
7492 If rld[r].reg_rtx is 0, this is an optional reload
7493 that we opted to ignore. */
7495 if (i >= 0 && rld[r].reg_rtx != 0)
7498 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7500 int part_reaches_end = 0;
7501 int all_reaches_end = 1;
7503 /* For a multi register reload, we need to check if all or part
7504 of the value lives to the end. */
7505 for (k = 0; k < nr; k++)
7507 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7508 rld[r].when_needed))
7509 part_reaches_end = 1;
7511 all_reaches_end = 0;
7514 /* Ignore reloads that don't reach the end of the insn in
7516 if (all_reaches_end)
7518 /* First, clear out memory of what used to be in this spill reg.
7519 If consecutive registers are used, clear them all. */
7521 for (k = 0; k < nr; k++)
7522 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7524 /* Maybe the spill reg contains a copy of reload_out. */
7526 && (GET_CODE (rld[r].out) == REG
7530 || GET_CODE (rld[r].out_reg) == REG))
7532 rtx out = (GET_CODE (rld[r].out) == REG
7536 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7537 register int nregno = REGNO (out);
7538 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7539 : HARD_REGNO_NREGS (nregno,
7540 GET_MODE (rld[r].reg_rtx)));
7542 spill_reg_store[i] = new_spill_reg_store[i];
7543 spill_reg_stored_to[i] = out;
7544 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7546 /* If NREGNO is a hard register, it may occupy more than
7547 one register. If it does, say what is in the
7548 rest of the registers assuming that both registers
7549 agree on how many words the object takes. If not,
7550 invalidate the subsequent registers. */
7552 if (nregno < FIRST_PSEUDO_REGISTER)
7553 for (k = 1; k < nnr; k++)
7554 reg_last_reload_reg[nregno + k]
7556 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7557 REGNO (rld[r].reg_rtx) + k)
7560 /* Now do the inverse operation. */
7561 for (k = 0; k < nr; k++)
7563 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7564 reg_reloaded_contents[i + k]
7565 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7568 reg_reloaded_insn[i + k] = insn;
7569 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7573 /* Maybe the spill reg contains a copy of reload_in. Only do
7574 something if there will not be an output reload for
7575 the register being reloaded. */
7576 else if (rld[r].out_reg == 0
7578 && ((GET_CODE (rld[r].in) == REG
7579 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7580 && ! reg_has_output_reload[REGNO (rld[r].in)])
7581 || (GET_CODE (rld[r].in_reg) == REG
7582 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7583 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7585 register int nregno;
7588 if (GET_CODE (rld[r].in) == REG
7589 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7590 nregno = REGNO (rld[r].in);
7591 else if (GET_CODE (rld[r].in_reg) == REG)
7592 nregno = REGNO (rld[r].in_reg);
7594 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7596 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7597 : HARD_REGNO_NREGS (nregno,
7598 GET_MODE (rld[r].reg_rtx)));
7600 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7602 if (nregno < FIRST_PSEUDO_REGISTER)
7603 for (k = 1; k < nnr; k++)
7604 reg_last_reload_reg[nregno + k]
7606 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7607 REGNO (rld[r].reg_rtx) + k)
7610 /* Unless we inherited this reload, show we haven't
7611 recently done a store.
7612 Previous stores of inherited auto_inc expressions
7613 also have to be discarded. */
7614 if (! reload_inherited[r]
7615 || (rld[r].out && ! rld[r].out_reg))
7616 spill_reg_store[i] = 0;
7618 for (k = 0; k < nr; k++)
7620 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7621 reg_reloaded_contents[i + k]
7622 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7625 reg_reloaded_insn[i + k] = insn;
7626 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7631 /* However, if part of the reload reaches the end, then we must
7632 invalidate the old info for the part that survives to the end. */
7633 else if (part_reaches_end)
7635 for (k = 0; k < nr; k++)
7636 if (reload_reg_reaches_end_p (i + k,
7638 rld[r].when_needed))
7639 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7643 /* The following if-statement was #if 0'd in 1.34 (or before...).
7644 It's reenabled in 1.35 because supposedly nothing else
7645 deals with this problem. */
7647 /* If a register gets output-reloaded from a non-spill register,
7648 that invalidates any previous reloaded copy of it.
7649 But forget_old_reloads_1 won't get to see it, because
7650 it thinks only about the original insn. So invalidate it here. */
7651 if (i < 0 && rld[r].out != 0
7652 && (GET_CODE (rld[r].out) == REG
7653 || (GET_CODE (rld[r].out) == MEM
7654 && GET_CODE (rld[r].out_reg) == REG)))
7656 rtx out = (GET_CODE (rld[r].out) == REG
7657 ? rld[r].out : rld[r].out_reg);
7658 register int nregno = REGNO (out);
7659 if (nregno >= FIRST_PSEUDO_REGISTER)
7661 rtx src_reg, store_insn = NULL_RTX;
7663 reg_last_reload_reg[nregno] = 0;
7665 /* If we can find a hard register that is stored, record
7666 the storing insn so that we may delete this insn with
7667 delete_output_reload. */
7668 src_reg = rld[r].reg_rtx;
7670 /* If this is an optional reload, try to find the source reg
7671 from an input reload. */
7674 rtx set = single_set (insn);
7675 if (set && SET_DEST (set) == rld[r].out)
7679 src_reg = SET_SRC (set);
7681 for (k = 0; k < n_reloads; k++)
7683 if (rld[k].in == src_reg)
7685 src_reg = rld[k].reg_rtx;
7692 store_insn = new_spill_reg_store[REGNO (src_reg)];
7693 if (src_reg && GET_CODE (src_reg) == REG
7694 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7696 int src_regno = REGNO (src_reg);
7697 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7698 /* The place where to find a death note varies with
7699 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7700 necessarily checked exactly in the code that moves
7701 notes, so just check both locations. */
7702 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7704 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7707 spill_reg_store[src_regno + nr] = store_insn;
7708 spill_reg_stored_to[src_regno + nr] = out;
7709 reg_reloaded_contents[src_regno + nr] = nregno;
7710 reg_reloaded_insn[src_regno + nr] = store_insn;
7711 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7712 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7713 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7715 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7717 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7719 reg_last_reload_reg[nregno] = src_reg;
7724 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7726 while (num_regs-- > 0)
7727 reg_last_reload_reg[nregno + num_regs] = 0;
7731 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7734 /* Emit code to perform a reload from IN (which may be a reload register) to
7735 OUT (which may also be a reload register). IN or OUT is from operand
7736 OPNUM with reload type TYPE.
7738 Returns first insn emitted. */
7741 gen_reload (out, in, opnum, type)
7745 enum reload_type type;
7747 rtx last = get_last_insn ();
7750 /* If IN is a paradoxical SUBREG, remove it and try to put the
7751 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7752 if (GET_CODE (in) == SUBREG
7753 && (GET_MODE_SIZE (GET_MODE (in))
7754 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7755 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7756 in = SUBREG_REG (in), out = tem;
7757 else if (GET_CODE (out) == SUBREG
7758 && (GET_MODE_SIZE (GET_MODE (out))
7759 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7760 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7761 out = SUBREG_REG (out), in = tem;
7763 /* How to do this reload can get quite tricky. Normally, we are being
7764 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7765 register that didn't get a hard register. In that case we can just
7766 call emit_move_insn.
7768 We can also be asked to reload a PLUS that adds a register or a MEM to
7769 another register, constant or MEM. This can occur during frame pointer
7770 elimination and while reloading addresses. This case is handled by
7771 trying to emit a single insn to perform the add. If it is not valid,
7772 we use a two insn sequence.
7774 Finally, we could be called to handle an 'o' constraint by putting
7775 an address into a register. In that case, we first try to do this
7776 with a named pattern of "reload_load_address". If no such pattern
7777 exists, we just emit a SET insn and hope for the best (it will normally
7778 be valid on machines that use 'o').
7780 This entire process is made complex because reload will never
7781 process the insns we generate here and so we must ensure that
7782 they will fit their constraints and also by the fact that parts of
7783 IN might be being reloaded separately and replaced with spill registers.
7784 Because of this, we are, in some sense, just guessing the right approach
7785 here. The one listed above seems to work.
7787 ??? At some point, this whole thing needs to be rethought. */
7789 if (GET_CODE (in) == PLUS
7790 && (GET_CODE (XEXP (in, 0)) == REG
7791 || GET_CODE (XEXP (in, 0)) == SUBREG
7792 || GET_CODE (XEXP (in, 0)) == MEM)
7793 && (GET_CODE (XEXP (in, 1)) == REG
7794 || GET_CODE (XEXP (in, 1)) == SUBREG
7795 || CONSTANT_P (XEXP (in, 1))
7796 || GET_CODE (XEXP (in, 1)) == MEM))
7798 /* We need to compute the sum of a register or a MEM and another
7799 register, constant, or MEM, and put it into the reload
7800 register. The best possible way of doing this is if the machine
7801 has a three-operand ADD insn that accepts the required operands.
7803 The simplest approach is to try to generate such an insn and see if it
7804 is recognized and matches its constraints. If so, it can be used.
7806 It might be better not to actually emit the insn unless it is valid,
7807 but we need to pass the insn as an operand to `recog' and
7808 `extract_insn' and it is simpler to emit and then delete the insn if
7809 not valid than to dummy things up. */
7811 rtx op0, op1, tem, insn;
7814 op0 = find_replacement (&XEXP (in, 0));
7815 op1 = find_replacement (&XEXP (in, 1));
7817 /* Since constraint checking is strict, commutativity won't be
7818 checked, so we need to do that here to avoid spurious failure
7819 if the add instruction is two-address and the second operand
7820 of the add is the same as the reload reg, which is frequently
7821 the case. If the insn would be A = B + A, rearrange it so
7822 it will be A = A + B as constrain_operands expects. */
7824 if (GET_CODE (XEXP (in, 1)) == REG
7825 && REGNO (out) == REGNO (XEXP (in, 1)))
7826 tem = op0, op0 = op1, op1 = tem;
7828 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7829 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7831 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7832 code = recog_memoized (insn);
7836 extract_insn (insn);
7837 /* We want constrain operands to treat this insn strictly in
7838 its validity determination, i.e., the way it would after reload
7840 if (constrain_operands (1))
7844 delete_insns_since (last);
7846 /* If that failed, we must use a conservative two-insn sequence.
7848 Use a move to copy one operand into the reload register. Prefer
7849 to reload a constant, MEM or pseudo since the move patterns can
7850 handle an arbitrary operand. If OP1 is not a constant, MEM or
7851 pseudo and OP1 is not a valid operand for an add instruction, then
7854 After reloading one of the operands into the reload register, add
7855 the reload register to the output register.
7857 If there is another way to do this for a specific machine, a
7858 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7861 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7863 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7864 || (GET_CODE (op1) == REG
7865 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7866 || (code != CODE_FOR_nothing
7867 && ! ((*insn_data[code].operand[2].predicate)
7868 (op1, insn_data[code].operand[2].mode))))
7869 tem = op0, op0 = op1, op1 = tem;
7871 gen_reload (out, op0, opnum, type);
7873 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7874 This fixes a problem on the 32K where the stack pointer cannot
7875 be used as an operand of an add insn. */
7877 if (rtx_equal_p (op0, op1))
7880 insn = emit_insn (gen_add2_insn (out, op1));
7882 /* If that failed, copy the address register to the reload register.
7883 Then add the constant to the reload register. */
7885 code = recog_memoized (insn);
7889 extract_insn (insn);
7890 /* We want constrain operands to treat this insn strictly in
7891 its validity determination, i.e., the way it would after reload
7893 if (constrain_operands (1))
7895 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7897 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7902 delete_insns_since (last);
7904 gen_reload (out, op1, opnum, type);
7905 insn = emit_insn (gen_add2_insn (out, op0));
7906 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7909 #ifdef SECONDARY_MEMORY_NEEDED
7910 /* If we need a memory location to do the move, do it that way. */
7911 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7912 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7913 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7914 REGNO_REG_CLASS (REGNO (out)),
7917 /* Get the memory to use and rewrite both registers to its mode. */
7918 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7920 if (GET_MODE (loc) != GET_MODE (out))
7921 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7923 if (GET_MODE (loc) != GET_MODE (in))
7924 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7926 gen_reload (loc, in, opnum, type);
7927 gen_reload (out, loc, opnum, type);
7931 /* If IN is a simple operand, use gen_move_insn. */
7932 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7933 emit_insn (gen_move_insn (out, in));
7935 #ifdef HAVE_reload_load_address
7936 else if (HAVE_reload_load_address)
7937 emit_insn (gen_reload_load_address (out, in));
7940 /* Otherwise, just write (set OUT IN) and hope for the best. */
7942 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7944 /* Return the first insn emitted.
7945 We can not just return get_last_insn, because there may have
7946 been multiple instructions emitted. Also note that gen_move_insn may
7947 emit more than one insn itself, so we can not assume that there is one
7948 insn emitted per emit_insn_before call. */
7950 return last ? NEXT_INSN (last) : get_insns ();
7953 /* Delete a previously made output-reload
7954 whose result we now believe is not needed.
7955 First we double-check.
7957 INSN is the insn now being processed.
7958 LAST_RELOAD_REG is the hard register number for which we want to delete
7959 the last output reload.
7960 J is the reload-number that originally used REG. The caller has made
7961 certain that reload J doesn't use REG any longer for input. */
7964 delete_output_reload (insn, j, last_reload_reg)
7967 int last_reload_reg;
7969 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7970 rtx reg = spill_reg_stored_to[last_reload_reg];
7973 int n_inherited = 0;
7977 /* Get the raw pseudo-register referred to. */
7979 while (GET_CODE (reg) == SUBREG)
7980 reg = SUBREG_REG (reg);
7981 substed = reg_equiv_memory_loc[REGNO (reg)];
7983 /* This is unsafe if the operand occurs more often in the current
7984 insn than it is inherited. */
7985 for (k = n_reloads - 1; k >= 0; k--)
7987 rtx reg2 = rld[k].in;
7990 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7991 reg2 = rld[k].in_reg;
7993 if (rld[k].out && ! rld[k].out_reg)
7994 reg2 = XEXP (rld[k].in_reg, 0);
7996 while (GET_CODE (reg2) == SUBREG)
7997 reg2 = SUBREG_REG (reg2);
7998 if (rtx_equal_p (reg2, reg))
8000 if (reload_inherited[k] || reload_override_in[k] || k == j)
8003 reg2 = rld[k].out_reg;
8006 while (GET_CODE (reg2) == SUBREG)
8007 reg2 = XEXP (reg2, 0);
8008 if (rtx_equal_p (reg2, reg))
8015 n_occurrences = count_occurrences (PATTERN (insn), reg);
8017 n_occurrences += count_occurrences (PATTERN (insn), substed);
8018 if (n_occurrences > n_inherited)
8021 /* If the pseudo-reg we are reloading is no longer referenced
8022 anywhere between the store into it and here,
8023 and no jumps or labels intervene, then the value can get
8024 here through the reload reg alone.
8025 Otherwise, give up--return. */
8026 for (i1 = NEXT_INSN (output_reload_insn);
8027 i1 != insn; i1 = NEXT_INSN (i1))
8029 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
8031 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
8032 && reg_mentioned_p (reg, PATTERN (i1)))
8034 /* If this is USE in front of INSN, we only have to check that
8035 there are no more references than accounted for by inheritance. */
8036 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
8038 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8039 i1 = NEXT_INSN (i1);
8041 if (n_occurrences <= n_inherited && i1 == insn)
8047 /* The caller has already checked that REG dies or is set in INSN.
8048 It has also checked that we are optimizing, and thus some inaccurancies
8049 in the debugging information are acceptable.
8050 So we could just delete output_reload_insn.
8051 But in some cases we can improve the debugging information without
8052 sacrificing optimization - maybe even improving the code:
8053 See if the pseudo reg has been completely replaced
8054 with reload regs. If so, delete the store insn
8055 and forget we had a stack slot for the pseudo. */
8056 if (rld[j].out != rld[j].in
8057 && REG_N_DEATHS (REGNO (reg)) == 1
8058 && REG_N_SETS (REGNO (reg)) == 1
8059 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8060 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8064 /* We know that it was used only between here
8065 and the beginning of the current basic block.
8066 (We also know that the last use before INSN was
8067 the output reload we are thinking of deleting, but never mind that.)
8068 Search that range; see if any ref remains. */
8069 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8071 rtx set = single_set (i2);
8073 /* Uses which just store in the pseudo don't count,
8074 since if they are the only uses, they are dead. */
8075 if (set != 0 && SET_DEST (set) == reg)
8077 if (GET_CODE (i2) == CODE_LABEL
8078 || GET_CODE (i2) == JUMP_INSN)
8080 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
8081 && reg_mentioned_p (reg, PATTERN (i2)))
8083 /* Some other ref remains; just delete the output reload we
8085 delete_address_reloads (output_reload_insn, insn);
8086 PUT_CODE (output_reload_insn, NOTE);
8087 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8088 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8093 /* Delete the now-dead stores into this pseudo. */
8094 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8096 rtx set = single_set (i2);
8098 if (set != 0 && SET_DEST (set) == reg)
8100 delete_address_reloads (i2, insn);
8101 /* This might be a basic block head,
8102 thus don't use delete_insn. */
8103 PUT_CODE (i2, NOTE);
8104 NOTE_SOURCE_FILE (i2) = 0;
8105 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8107 if (GET_CODE (i2) == CODE_LABEL
8108 || GET_CODE (i2) == JUMP_INSN)
8112 /* For the debugging info,
8113 say the pseudo lives in this reload reg. */
8114 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8115 alter_reg (REGNO (reg), -1);
8117 delete_address_reloads (output_reload_insn, insn);
8118 PUT_CODE (output_reload_insn, NOTE);
8119 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8120 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8124 /* We are going to delete DEAD_INSN. Recursively delete loads of
8125 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8126 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8128 delete_address_reloads (dead_insn, current_insn)
8129 rtx dead_insn, current_insn;
8131 rtx set = single_set (dead_insn);
8132 rtx set2, dst, prev, next;
8135 rtx dst = SET_DEST (set);
8136 if (GET_CODE (dst) == MEM)
8137 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8139 /* If we deleted the store from a reloaded post_{in,de}c expression,
8140 we can delete the matching adds. */
8141 prev = PREV_INSN (dead_insn);
8142 next = NEXT_INSN (dead_insn);
8143 if (! prev || ! next)
8145 set = single_set (next);
8146 set2 = single_set (prev);
8148 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8149 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8150 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8152 dst = SET_DEST (set);
8153 if (! rtx_equal_p (dst, SET_DEST (set2))
8154 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8155 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8156 || (INTVAL (XEXP (SET_SRC (set), 1))
8157 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8163 /* Subfunction of delete_address_reloads: process registers found in X. */
8165 delete_address_reloads_1 (dead_insn, x, current_insn)
8166 rtx dead_insn, x, current_insn;
8168 rtx prev, set, dst, i2;
8170 enum rtx_code code = GET_CODE (x);
8174 const char *fmt= GET_RTX_FORMAT (code);
8175 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8178 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8179 else if (fmt[i] == 'E')
8181 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8182 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8189 if (spill_reg_order[REGNO (x)] < 0)
8192 /* Scan backwards for the insn that sets x. This might be a way back due
8194 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8196 code = GET_CODE (prev);
8197 if (code == CODE_LABEL || code == JUMP_INSN)
8199 if (GET_RTX_CLASS (code) != 'i')
8201 if (reg_set_p (x, PATTERN (prev)))
8203 if (reg_referenced_p (x, PATTERN (prev)))
8206 if (! prev || INSN_UID (prev) < reload_first_uid)
8208 /* Check that PREV only sets the reload register. */
8209 set = single_set (prev);
8212 dst = SET_DEST (set);
8213 if (GET_CODE (dst) != REG
8214 || ! rtx_equal_p (dst, x))
8216 if (! reg_set_p (dst, PATTERN (dead_insn)))
8218 /* Check if DST was used in a later insn -
8219 it might have been inherited. */
8220 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8222 if (GET_CODE (i2) == CODE_LABEL)
8224 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8226 if (reg_referenced_p (dst, PATTERN (i2)))
8228 /* If there is a reference to the register in the current insn,
8229 it might be loaded in a non-inherited reload. If no other
8230 reload uses it, that means the register is set before
8232 if (i2 == current_insn)
8234 for (j = n_reloads - 1; j >= 0; j--)
8235 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8236 || reload_override_in[j] == dst)
8238 for (j = n_reloads - 1; j >= 0; j--)
8239 if (rld[j].in && rld[j].reg_rtx == dst)
8246 if (GET_CODE (i2) == JUMP_INSN)
8248 /* If DST is still live at CURRENT_INSN, check if it is used for
8249 any reload. Note that even if CURRENT_INSN sets DST, we still
8250 have to check the reloads. */
8251 if (i2 == current_insn)
8253 for (j = n_reloads - 1; j >= 0; j--)
8254 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8255 || reload_override_in[j] == dst)
8257 /* ??? We can't finish the loop here, because dst might be
8258 allocated to a pseudo in this block if no reload in this
8259 block needs any of the clsses containing DST - see
8260 spill_hard_reg. There is no easy way to tell this, so we
8261 have to scan till the end of the basic block. */
8263 if (reg_set_p (dst, PATTERN (i2)))
8267 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8268 reg_reloaded_contents[REGNO (dst)] = -1;
8269 /* Can't use delete_insn here because PREV might be a basic block head. */
8270 PUT_CODE (prev, NOTE);
8271 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8272 NOTE_SOURCE_FILE (prev) = 0;
8275 /* Output reload-insns to reload VALUE into RELOADREG.
8276 VALUE is an autoincrement or autodecrement RTX whose operand
8277 is a register or memory location;
8278 so reloading involves incrementing that location.
8279 IN is either identical to VALUE, or some cheaper place to reload from.
8281 INC_AMOUNT is the number to increment or decrement by (always positive).
8282 This cannot be deduced from VALUE.
8284 Return the instruction that stores into RELOADREG. */
8287 inc_for_reload (reloadreg, in, value, inc_amount)
8292 /* REG or MEM to be copied and incremented. */
8293 rtx incloc = XEXP (value, 0);
8294 /* Nonzero if increment after copying. */
8295 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8301 rtx real_in = in == value ? XEXP (in, 0) : in;
8303 /* No hard register is equivalent to this register after
8304 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8305 we could inc/dec that register as well (maybe even using it for
8306 the source), but I'm not sure it's worth worrying about. */
8307 if (GET_CODE (incloc) == REG)
8308 reg_last_reload_reg[REGNO (incloc)] = 0;
8310 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8311 inc_amount = - inc_amount;
8313 inc = GEN_INT (inc_amount);
8315 /* If this is post-increment, first copy the location to the reload reg. */
8316 if (post && real_in != reloadreg)
8317 emit_insn (gen_move_insn (reloadreg, real_in));
8321 /* See if we can directly increment INCLOC. Use a method similar to
8322 that in gen_reload. */
8324 last = get_last_insn ();
8325 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8326 gen_rtx_PLUS (GET_MODE (incloc),
8329 code = recog_memoized (add_insn);
8332 extract_insn (add_insn);
8333 if (constrain_operands (1))
8335 /* If this is a pre-increment and we have incremented the value
8336 where it lives, copy the incremented value to RELOADREG to
8337 be used as an address. */
8340 emit_insn (gen_move_insn (reloadreg, incloc));
8345 delete_insns_since (last);
8348 /* If couldn't do the increment directly, must increment in RELOADREG.
8349 The way we do this depends on whether this is pre- or post-increment.
8350 For pre-increment, copy INCLOC to the reload register, increment it
8351 there, then save back. */
8355 if (in != reloadreg)
8356 emit_insn (gen_move_insn (reloadreg, real_in));
8357 emit_insn (gen_add2_insn (reloadreg, inc));
8358 store = emit_insn (gen_move_insn (incloc, reloadreg));
8363 Because this might be a jump insn or a compare, and because RELOADREG
8364 may not be available after the insn in an input reload, we must do
8365 the incrementation before the insn being reloaded for.
8367 We have already copied IN to RELOADREG. Increment the copy in
8368 RELOADREG, save that back, then decrement RELOADREG so it has
8369 the original value. */
8371 emit_insn (gen_add2_insn (reloadreg, inc));
8372 store = emit_insn (gen_move_insn (incloc, reloadreg));
8373 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8379 /* Return 1 if we are certain that the constraint-string STRING allows
8380 the hard register REG. Return 0 if we can't be sure of this. */
8383 constraint_accepts_reg_p (string, reg)
8388 int regno = true_regnum (reg);
8391 /* Initialize for first alternative. */
8393 /* Check that each alternative contains `g' or `r'. */
8395 switch (c = *string++)
8398 /* If an alternative lacks `g' or `r', we lose. */
8401 /* If an alternative lacks `g' or `r', we lose. */
8404 /* Initialize for next alternative. */
8409 /* Any general reg wins for this alternative. */
8410 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8414 /* Any reg in specified class wins for this alternative. */
8416 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8418 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8424 /* Return the number of places FIND appears within X, but don't count
8425 an occurrence if some SET_DEST is FIND. */
8428 count_occurrences (x, find)
8429 register rtx x, find;
8432 register enum rtx_code code;
8433 register const char *format_ptr;
8441 code = GET_CODE (x);
8456 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8460 if (SET_DEST (x) == find)
8461 return count_occurrences (SET_SRC (x), find);
8468 format_ptr = GET_RTX_FORMAT (code);
8471 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8473 switch (*format_ptr++)
8476 count += count_occurrences (XEXP (x, i), find);
8480 if (XVEC (x, i) != NULL)
8482 for (j = 0; j < XVECLEN (x, i); j++)
8483 count += count_occurrences (XVECEXP (x, i, j), find);
8491 /* This array holds values which are equivalent to a hard register
8492 during reload_cse_regs. Each array element is an EXPR_LIST of
8493 values. Each time a hard register is set, we set the corresponding
8494 array element to the value. Each time a hard register is copied
8495 into memory, we add the memory location to the corresponding array
8496 element. We don't store values or memory addresses with side
8497 effects in this array.
8499 If the value is a CONST_INT, then the mode of the containing
8500 EXPR_LIST is the mode in which that CONST_INT was referenced.
8502 We sometimes clobber a specific entry in a list. In that case, we
8503 just set XEXP (list-entry, 0) to 0. */
8505 static rtx *reg_values;
8507 /* This is a preallocated REG rtx which we use as a temporary in
8508 reload_cse_invalidate_regno, so that we don't need to allocate a
8509 new one each time through a loop in that function. */
8511 static rtx invalidate_regno_rtx;
8513 /* Invalidate any entries in reg_values which depend on REGNO,
8514 including those for REGNO itself. This is called if REGNO is
8515 changing. If CLOBBER is true, then always forget anything we
8516 currently know about REGNO. MODE is the mode of the assignment to
8517 REGNO, which is used to determine how many hard registers are being
8518 changed. If MODE is VOIDmode, then only REGNO is being changed;
8519 this is used when invalidating call clobbered registers across a
8523 reload_cse_invalidate_regno (regno, mode, clobber)
8525 enum machine_mode mode;
8531 /* Our callers don't always go through true_regnum; we may see a
8532 pseudo-register here from a CLOBBER or the like. We probably
8533 won't ever see a pseudo-register that has a real register number,
8534 for we check anyhow for safety. */
8535 if (regno >= FIRST_PSEUDO_REGISTER)
8536 regno = reg_renumber[regno];
8540 if (mode == VOIDmode)
8541 endregno = regno + 1;
8543 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8546 for (i = regno; i < endregno; i++)
8549 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8553 for (x = reg_values[i]; x; x = XEXP (x, 1))
8555 if (XEXP (x, 0) != 0
8556 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8558 /* If this is the only entry on the list, clear
8559 reg_values[i]. Otherwise, just clear this entry on
8561 if (XEXP (x, 1) == 0 && x == reg_values[i])
8571 /* We must look at earlier registers, in case REGNO is part of a
8572 multi word value but is not the first register. If an earlier
8573 register has a value in a mode which overlaps REGNO, then we must
8574 invalidate that earlier register. Note that we do not need to
8575 check REGNO or later registers (we must not check REGNO itself,
8576 because we would incorrectly conclude that there was a conflict). */
8578 for (i = 0; i < regno; i++)
8582 for (x = reg_values[i]; x; x = XEXP (x, 1))
8584 if (XEXP (x, 0) != 0)
8586 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8587 REGNO (invalidate_regno_rtx) = i;
8588 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8591 reload_cse_invalidate_regno (i, VOIDmode, 1);
8599 /* The memory at address MEM_BASE is being changed.
8600 Return whether this change will invalidate VAL. */
8603 reload_cse_mem_conflict_p (mem_base, val)
8611 code = GET_CODE (val);
8614 /* Get rid of a few simple cases quickly. */
8627 if (GET_MODE (mem_base) == BLKmode
8628 || GET_MODE (val) == BLKmode)
8630 if (anti_dependence (val, mem_base))
8632 /* The address may contain nested MEMs. */
8639 fmt = GET_RTX_FORMAT (code);
8641 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8645 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8648 else if (fmt[i] == 'E')
8652 for (j = 0; j < XVECLEN (val, i); j++)
8653 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8661 /* Invalidate any entries in reg_values which are changed because of a
8662 store to MEM_RTX. If this is called because of a non-const call
8663 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8666 reload_cse_invalidate_mem (mem_rtx)
8671 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8675 for (x = reg_values[i]; x; x = XEXP (x, 1))
8677 if (XEXP (x, 0) != 0
8678 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8680 /* If this is the only entry on the list, clear
8681 reg_values[i]. Otherwise, just clear this entry on
8683 if (XEXP (x, 1) == 0 && x == reg_values[i])
8694 /* Invalidate DEST, which is being assigned to or clobbered. The
8695 second parameter exists so that this function can be passed to
8696 note_stores; it is ignored. */
8699 reload_cse_invalidate_rtx (dest, ignore, data)
8701 rtx ignore ATTRIBUTE_UNUSED;
8702 void *data ATTRIBUTE_UNUSED;
8704 while (GET_CODE (dest) == STRICT_LOW_PART
8705 || GET_CODE (dest) == SIGN_EXTRACT
8706 || GET_CODE (dest) == ZERO_EXTRACT
8707 || GET_CODE (dest) == SUBREG)
8708 dest = XEXP (dest, 0);
8710 if (GET_CODE (dest) == REG)
8711 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8712 else if (GET_CODE (dest) == MEM)
8713 reload_cse_invalidate_mem (dest);
8716 /* Do a very simple CSE pass over the hard registers.
8718 This function detects no-op moves where we happened to assign two
8719 different pseudo-registers to the same hard register, and then
8720 copied one to the other. Reload will generate a useless
8721 instruction copying a register to itself.
8723 This function also detects cases where we load a value from memory
8724 into two different registers, and (if memory is more expensive than
8725 registers) changes it to simply copy the first register into the
8728 Another optimization is performed that scans the operands of each
8729 instruction to see whether the value is already available in a
8730 hard register. It then replaces the operand with the hard register
8731 if possible, much like an optional reload would. */
8734 reload_cse_regs_1 (first)
8742 init_alias_analysis ();
8744 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8745 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8747 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8748 free them when we are done. */
8749 push_obstacks (&reload_obstack, &reload_obstack);
8750 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8752 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8753 memory for a non-const call instruction. */
8754 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8756 /* This is used in reload_cse_invalidate_regno to avoid consing a
8757 new REG in a loop in that function. */
8758 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8760 for (insn = first; insn; insn = NEXT_INSN (insn))
8764 if (GET_CODE (insn) == CODE_LABEL)
8766 /* Forget all the register values at a code label. We don't
8767 try to do anything clever around jumps. */
8768 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8774 #ifdef NON_SAVING_SETJMP
8775 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8776 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8778 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8785 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8788 /* If this is a call instruction, forget anything stored in a
8789 call clobbered register, or, if this is not a const call, in
8791 if (GET_CODE (insn) == CALL_INSN)
8793 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8794 if (call_used_regs[i])
8795 reload_cse_invalidate_regno (i, VOIDmode, 1);
8797 if (! CONST_CALL_P (insn))
8798 reload_cse_invalidate_mem (callmem);
8802 /* Forget all the register values at a volatile asm. */
8803 if (GET_CODE (insn) == INSN
8804 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8805 && MEM_VOLATILE_P (PATTERN (insn)))
8806 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8809 body = PATTERN (insn);
8810 if (GET_CODE (body) == SET)
8813 if (reload_cse_noop_set_p (body, insn))
8815 /* If this sets the return value of the function, we must keep
8816 a USE around, in case this is in a different basic block
8817 than the final USE. Otherwise, we could loose important
8818 register lifeness information on SMALL_REGISTER_CLASSES
8819 machines, where return registers might be used as spills:
8820 subsequent passes assume that spill registers are dead at
8821 the end of a basic block. */
8822 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8825 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8826 INSN_CODE (insn) = -1;
8827 REG_NOTES (insn) = NULL_RTX;
8828 push_obstacks (&reload_obstack, &reload_obstack);
8832 PUT_CODE (insn, NOTE);
8833 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8834 NOTE_SOURCE_FILE (insn) = 0;
8837 /* We're done with this insn. */
8841 /* It's not a no-op, but we can try to simplify it. */
8842 count += reload_cse_simplify_set (body, insn);
8845 apply_change_group ();
8847 reload_cse_simplify_operands (insn);
8849 reload_cse_record_set (body, body);
8851 else if (GET_CODE (body) == PARALLEL)
8854 rtx value = NULL_RTX;
8856 /* If every action in a PARALLEL is a noop, we can delete
8857 the entire PARALLEL. */
8858 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8860 rtx part = XVECEXP (body, 0, i);
8861 if (GET_CODE (part) == SET)
8863 if (! reload_cse_noop_set_p (part, insn))
8865 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8869 value = SET_DEST (part);
8872 else if (GET_CODE (part) != CLOBBER)
8880 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8881 INSN_CODE (insn) = -1;
8882 REG_NOTES (insn) = NULL_RTX;
8883 push_obstacks (&reload_obstack, &reload_obstack);
8887 PUT_CODE (insn, NOTE);
8888 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8889 NOTE_SOURCE_FILE (insn) = 0;
8892 /* We're done with this insn. */
8896 /* It's not a no-op, but we can try to simplify it. */
8897 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8898 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8899 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8902 apply_change_group ();
8904 reload_cse_simplify_operands (insn);
8906 /* Look through the PARALLEL and record the values being
8907 set, if possible. Also handle any CLOBBERs. */
8908 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8910 rtx x = XVECEXP (body, 0, i);
8912 if (GET_CODE (x) == SET)
8913 reload_cse_record_set (x, body);
8915 note_stores (x, reload_cse_invalidate_rtx, NULL);
8919 note_stores (body, reload_cse_invalidate_rtx, NULL);
8922 /* Clobber any registers which appear in REG_INC notes. We
8923 could keep track of the changes to their values, but it is
8924 unlikely to help. */
8928 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8929 if (REG_NOTE_KIND (x) == REG_INC)
8930 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
8934 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8935 after we have processed the insn. */
8936 if (GET_CODE (insn) == CALL_INSN)
8940 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8941 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8942 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
8948 end_alias_analysis ();
8950 /* Free all the temporary structures we created, and go back to the
8951 regular obstacks. */
8952 obstack_free (&reload_obstack, firstobj);
8956 /* Call cse / combine like post-reload optimization phases.
8957 FIRST is the first instruction. */
8959 reload_cse_regs (first)
8962 reload_cse_regs_1 (first);
8964 reload_cse_move2add (first);
8965 if (flag_expensive_optimizations)
8966 reload_cse_regs_1 (first);
8969 /* Return whether the values known for REGNO are equal to VAL. MODE
8970 is the mode of the object that VAL is being copied to; this matters
8971 if VAL is a CONST_INT. */
8974 reload_cse_regno_equal_p (regno, val, mode)
8977 enum machine_mode mode;
8984 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8985 if (XEXP (x, 0) != 0
8986 && rtx_equal_p (XEXP (x, 0), val)
8987 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8988 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8989 && (GET_CODE (val) != CONST_INT
8990 || mode == GET_MODE (x)
8991 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8992 /* On a big endian machine if the value spans more than
8993 one register then this register holds the high part of
8994 it and we can't use it.
8996 ??? We should also compare with the high part of the
8998 && !(WORDS_BIG_ENDIAN
8999 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
9000 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
9001 GET_MODE_BITSIZE (GET_MODE (x))))))
9007 /* See whether a single set is a noop. SET is the set instruction we
9008 are should check, and INSN is the instruction from which it came. */
9011 reload_cse_noop_set_p (set, insn)
9013 rtx insn ATTRIBUTE_UNUSED;
9016 enum machine_mode dest_mode;
9020 src = SET_SRC (set);
9021 dest = SET_DEST (set);
9022 dest_mode = GET_MODE (dest);
9024 if (side_effects_p (src))
9027 dreg = true_regnum (dest);
9028 sreg = true_regnum (src);
9030 /* Check for setting a register to itself. In this case, we don't
9031 have to worry about REG_DEAD notes. */
9032 if (dreg >= 0 && dreg == sreg)
9038 /* Check for setting a register to itself. */
9042 /* Check for setting a register to a value which we already know
9043 is in the register. */
9044 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
9047 /* Check for setting a register DREG to another register SREG
9048 where SREG is equal to a value which is already in DREG. */
9053 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9057 if (XEXP (x, 0) == 0)
9060 if (dest_mode == GET_MODE (x))
9062 else if (GET_MODE_BITSIZE (dest_mode)
9063 < GET_MODE_BITSIZE (GET_MODE (x)))
9064 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9069 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
9077 else if (GET_CODE (dest) == MEM)
9079 /* Check for storing a register to memory when we know that the
9080 register is equivalent to the memory location. */
9082 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
9083 && ! side_effects_p (dest))
9090 /* Try to simplify a single SET instruction. SET is the set pattern.
9091 INSN is the instruction it came from.
9092 This function only handles one case: if we set a register to a value
9093 which is not a register, we try to find that value in some other register
9094 and change the set into a register copy. */
9097 reload_cse_simplify_set (set, insn)
9103 enum machine_mode dest_mode;
9104 enum reg_class dclass;
9107 dreg = true_regnum (SET_DEST (set));
9111 src = SET_SRC (set);
9112 if (side_effects_p (src) || true_regnum (src) >= 0)
9115 dclass = REGNO_REG_CLASS (dreg);
9117 /* If memory loads are cheaper than register copies, don't change them. */
9118 if (GET_CODE (src) == MEM
9119 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9122 /* If the constant is cheaper than a register, don't change it. */
9123 if (CONSTANT_P (src)
9124 && rtx_cost (src, SET) < 2)
9127 dest_mode = GET_MODE (SET_DEST (set));
9128 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9131 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9132 && reload_cse_regno_equal_p (i, src, dest_mode))
9136 /* Pop back to the real obstacks while changing the insn. */
9139 validated = validate_change (insn, &SET_SRC (set),
9140 gen_rtx_REG (dest_mode, i), 1);
9142 /* Go back to the obstack we are using for temporary
9144 push_obstacks (&reload_obstack, &reload_obstack);
9153 /* Try to replace operands in INSN with equivalent values that are already
9154 in registers. This can be viewed as optional reloading.
9156 For each non-register operand in the insn, see if any hard regs are
9157 known to be equivalent to that operand. Record the alternatives which
9158 can accept these hard registers. Among all alternatives, select the
9159 ones which are better or equal to the one currently matching, where
9160 "better" is in terms of '?' and '!' constraints. Among the remaining
9161 alternatives, select the one which replaces most operands with
9165 reload_cse_simplify_operands (insn)
9170 const char *constraints[MAX_RECOG_OPERANDS];
9172 /* Vector recording how bad an alternative is. */
9173 int *alternative_reject;
9174 /* Vector recording how many registers can be introduced by choosing
9175 this alternative. */
9176 int *alternative_nregs;
9177 /* Array of vectors recording, for each operand and each alternative,
9178 which hard register to substitute, or -1 if the operand should be
9180 int *op_alt_regno[MAX_RECOG_OPERANDS];
9181 /* Array of alternatives, sorted in order of decreasing desirability. */
9182 int *alternative_order;
9183 rtx reg = gen_rtx_REG (VOIDmode, -1);
9185 extract_insn (insn);
9187 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
9190 /* Figure out which alternative currently matches. */
9191 if (! constrain_operands (1))
9192 fatal_insn_not_found (insn);
9194 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9195 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9196 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9197 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
9198 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
9200 for (i = 0; i < recog_data.n_operands; i++)
9202 enum machine_mode mode;
9206 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9207 for (j = 0; j < recog_data.n_alternatives; j++)
9208 op_alt_regno[i][j] = -1;
9210 p = constraints[i] = recog_data.constraints[i];
9211 mode = recog_data.operand_mode[i];
9213 /* Add the reject values for each alternative given by the constraints
9214 for this operand. */
9222 alternative_reject[j] += 3;
9224 alternative_reject[j] += 300;
9227 /* We won't change operands which are already registers. We
9228 also don't want to modify output operands. */
9229 regno = true_regnum (recog_data.operand[i]);
9231 || constraints[i][0] == '='
9232 || constraints[i][0] == '+')
9235 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9237 int class = (int) NO_REGS;
9239 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
9242 REGNO (reg) = regno;
9243 PUT_MODE (reg, mode);
9245 /* We found a register equal to this operand. Now look for all
9246 alternatives that can accept this register and have not been
9247 assigned a register they can use yet. */
9256 case '=': case '+': case '?':
9257 case '#': case '&': case '!':
9259 case '0': case '1': case '2': case '3': case '4':
9260 case '5': case '6': case '7': case '8': case '9':
9261 case 'm': case '<': case '>': case 'V': case 'o':
9262 case 'E': case 'F': case 'G': case 'H':
9263 case 's': case 'i': case 'n':
9264 case 'I': case 'J': case 'K': case 'L':
9265 case 'M': case 'N': case 'O': case 'P':
9266 #ifdef EXTRA_CONSTRAINT
9267 case 'Q': case 'R': case 'S': case 'T': case 'U':
9270 /* These don't say anything we care about. */
9274 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9279 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9282 case ',': case '\0':
9283 /* See if REGNO fits this alternative, and set it up as the
9284 replacement register if we don't have one for this
9285 alternative yet and the operand being replaced is not
9286 a cheap CONST_INT. */
9287 if (op_alt_regno[i][j] == -1
9288 && reg_fits_class_p (reg, class, 0, mode)
9289 && (GET_CODE (recog_data.operand[i]) != CONST_INT
9290 || (rtx_cost (recog_data.operand[i], SET)
9291 > rtx_cost (reg, SET))))
9293 alternative_nregs[j]++;
9294 op_alt_regno[i][j] = regno;
9306 /* Record all alternatives which are better or equal to the currently
9307 matching one in the alternative_order array. */
9308 for (i = j = 0; i < recog_data.n_alternatives; i++)
9309 if (alternative_reject[i] <= alternative_reject[which_alternative])
9310 alternative_order[j++] = i;
9311 recog_data.n_alternatives = j;
9313 /* Sort it. Given a small number of alternatives, a dumb algorithm
9314 won't hurt too much. */
9315 for (i = 0; i < recog_data.n_alternatives - 1; i++)
9318 int best_reject = alternative_reject[alternative_order[i]];
9319 int best_nregs = alternative_nregs[alternative_order[i]];
9322 for (j = i + 1; j < recog_data.n_alternatives; j++)
9324 int this_reject = alternative_reject[alternative_order[j]];
9325 int this_nregs = alternative_nregs[alternative_order[j]];
9327 if (this_reject < best_reject
9328 || (this_reject == best_reject && this_nregs < best_nregs))
9331 best_reject = this_reject;
9332 best_nregs = this_nregs;
9336 tmp = alternative_order[best];
9337 alternative_order[best] = alternative_order[i];
9338 alternative_order[i] = tmp;
9341 /* Substitute the operands as determined by op_alt_regno for the best
9343 j = alternative_order[0];
9345 /* Pop back to the real obstacks while changing the insn. */
9348 for (i = 0; i < recog_data.n_operands; i++)
9350 enum machine_mode mode = recog_data.operand_mode[i];
9351 if (op_alt_regno[i][j] == -1)
9354 validate_change (insn, recog_data.operand_loc[i],
9355 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9358 for (i = recog_data.n_dups - 1; i >= 0; i--)
9360 int op = recog_data.dup_num[i];
9361 enum machine_mode mode = recog_data.operand_mode[op];
9363 if (op_alt_regno[op][j] == -1)
9366 validate_change (insn, recog_data.dup_loc[i],
9367 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9370 /* Go back to the obstack we are using for temporary
9372 push_obstacks (&reload_obstack, &reload_obstack);
9374 return apply_change_group ();
9377 /* These two variables are used to pass information from
9378 reload_cse_record_set to reload_cse_check_clobber. */
9380 static int reload_cse_check_clobbered;
9381 static rtx reload_cse_check_src;
9383 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9384 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9385 second argument, which is passed by note_stores, is ignored. */
9388 reload_cse_check_clobber (dest, ignore, data)
9390 rtx ignore ATTRIBUTE_UNUSED;
9391 void *data ATTRIBUTE_UNUSED;
9393 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9394 reload_cse_check_clobbered = 1;
9397 /* Record the result of a SET instruction. SET is the set pattern.
9398 BODY is the pattern of the insn that it came from. */
9401 reload_cse_record_set (set, body)
9407 enum machine_mode dest_mode;
9409 dest = SET_DEST (set);
9410 src = SET_SRC (set);
9411 dreg = true_regnum (dest);
9412 sreg = true_regnum (src);
9413 dest_mode = GET_MODE (dest);
9415 /* Some machines don't define AUTO_INC_DEC, but they still use push
9416 instructions. We need to catch that case here in order to
9417 invalidate the stack pointer correctly. Note that invalidating
9418 the stack pointer is different from invalidating DEST. */
9420 while (GET_CODE (x) == SUBREG
9421 || GET_CODE (x) == ZERO_EXTRACT
9422 || GET_CODE (x) == SIGN_EXTRACT
9423 || GET_CODE (x) == STRICT_LOW_PART)
9425 if (push_operand (x, GET_MODE (x)))
9427 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
9428 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9432 /* We can only handle an assignment to a register, or a store of a
9433 register to a memory location. For other cases, we just clobber
9434 the destination. We also have to just clobber if there are side
9435 effects in SRC or DEST. */
9436 if ((dreg < 0 && GET_CODE (dest) != MEM)
9437 || side_effects_p (src)
9438 || side_effects_p (dest))
9440 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9445 /* We don't try to handle values involving CC, because it's a pain
9446 to keep track of when they have to be invalidated. */
9447 if (reg_mentioned_p (cc0_rtx, src)
9448 || reg_mentioned_p (cc0_rtx, dest))
9450 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9455 /* If BODY is a PARALLEL, then we need to see whether the source of
9456 SET is clobbered by some other instruction in the PARALLEL. */
9457 if (GET_CODE (body) == PARALLEL)
9461 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9465 x = XVECEXP (body, 0, i);
9469 reload_cse_check_clobbered = 0;
9470 reload_cse_check_src = src;
9471 note_stores (x, reload_cse_check_clobber, NULL);
9472 if (reload_cse_check_clobbered)
9474 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
9484 /* This is an assignment to a register. Update the value we
9485 have stored for the register. */
9490 /* This is a copy from one register to another. Any values
9491 which were valid for SREG are now valid for DREG. If the
9492 mode changes, we use gen_lowpart_common to extract only
9493 the part of the value that is copied. */
9494 reg_values[dreg] = 0;
9495 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9499 if (XEXP (x, 0) == 0)
9501 if (dest_mode == GET_MODE (XEXP (x, 0)))
9503 else if (GET_MODE_BITSIZE (dest_mode)
9504 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9507 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9509 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9514 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9516 /* We've changed DREG, so invalidate any values held by other
9517 registers that depend upon it. */
9518 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9520 /* If this assignment changes more than one hard register,
9521 forget anything we know about the others. */
9522 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9523 reg_values[dreg + i] = 0;
9525 else if (GET_CODE (dest) == MEM)
9527 /* Invalidate conflicting memory locations. */
9528 reload_cse_invalidate_mem (dest);
9530 /* If we're storing a register to memory, add DEST to the list
9532 if (sreg >= 0 && ! side_effects_p (dest))
9533 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9538 /* We should have bailed out earlier. */
9543 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9545 This code might also be useful when reload gave up on reg+reg addresssing
9546 because of clashes between the return register and INDEX_REG_CLASS. */
9548 /* The maximum number of uses of a register we can keep track of to
9549 replace them with reg+reg addressing. */
9550 #define RELOAD_COMBINE_MAX_USES 6
9552 /* INSN is the insn where a register has ben used, and USEP points to the
9553 location of the register within the rtl. */
9554 struct reg_use { rtx insn, *usep; };
9556 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9557 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9558 indicates where it becomes live again.
9559 Otherwise, USE_INDEX is the index of the last encountered use of the
9560 register (which is first among these we have seen since we scan backwards),
9561 OFFSET contains the constant offset that is added to the register in
9562 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9563 last, of these uses.
9564 STORE_RUID is always meaningful if we only want to use a value in a
9565 register in a different place: it denotes the next insn in the insn
9566 stream (i.e. the last ecountered) that sets or clobbers the register. */
9569 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9574 } reg_state[FIRST_PSEUDO_REGISTER];
9576 /* Reverse linear uid. This is increased in reload_combine while scanning
9577 the instructions from last to first. It is used to set last_label_ruid
9578 and the store_ruid / use_ruid fields in reg_state. */
9579 static int reload_combine_ruid;
9581 #define LABEL_LIVE(LABEL) \
9582 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9588 int first_index_reg = 1, last_index_reg = 0;
9590 int last_label_ruid;
9591 int min_labelno, n_labels;
9592 HARD_REG_SET ever_live_at_start, *label_live;
9594 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9595 reload has already used it where appropriate, so there is no use in
9596 trying to generate it now. */
9597 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9600 /* To avoid wasting too much time later searching for an index register,
9601 determine the minimum and maximum index register numbers. */
9602 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9604 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9606 if (! last_index_reg)
9608 first_index_reg = i;
9611 /* If no index register is available, we can quit now. */
9612 if (first_index_reg > last_index_reg)
9615 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9616 information is a bit fuzzy immediately after reload, but it's
9617 still good enough to determine which registers are live at a jump
9619 min_labelno = get_first_label_num ();
9620 n_labels = max_label_num () - min_labelno;
9621 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9622 CLEAR_HARD_REG_SET (ever_live_at_start);
9623 for (i = n_basic_blocks - 1; i >= 0; i--)
9625 insn = BLOCK_HEAD (i);
9626 if (GET_CODE (insn) == CODE_LABEL)
9630 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9631 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9632 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9633 IOR_HARD_REG_SET (ever_live_at_start, live);
9637 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9638 last_label_ruid = reload_combine_ruid = 0;
9639 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9641 reg_state[i].store_ruid = reload_combine_ruid;
9643 reg_state[i].use_index = -1;
9645 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9648 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9652 /* We cannot do our optimization across labels. Invalidating all the use
9653 information we have would be costly, so we just note where the label
9654 is and then later disable any optimization that would cross it. */
9655 if (GET_CODE (insn) == CODE_LABEL)
9656 last_label_ruid = reload_combine_ruid;
9657 if (GET_CODE (insn) == BARRIER)
9659 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9660 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9662 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9664 reload_combine_ruid++;
9666 /* Look for (set (REGX) (CONST_INT))
9667 (set (REGX) (PLUS (REGX) (REGY)))
9669 ... (MEM (REGX)) ...
9671 (set (REGZ) (CONST_INT))
9673 ... (MEM (PLUS (REGZ) (REGY)))... .
9675 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9676 and that we know all uses of REGX before it dies. */
9677 set = single_set (insn);
9679 && GET_CODE (SET_DEST (set)) == REG
9680 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9681 GET_MODE (SET_DEST (set)))
9683 && GET_CODE (SET_SRC (set)) == PLUS
9684 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9685 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9686 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9688 rtx reg = SET_DEST (set);
9689 rtx plus = SET_SRC (set);
9690 rtx base = XEXP (plus, 1);
9691 rtx prev = prev_nonnote_insn (insn);
9692 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9693 int regno = REGNO (reg);
9694 rtx const_reg = NULL_RTX;
9695 rtx reg_sum = NULL_RTX;
9697 /* Now, we need an index register.
9698 We'll set index_reg to this index register, const_reg to the
9699 register that is to be loaded with the constant
9700 (denoted as REGZ in the substitution illustration above),
9701 and reg_sum to the register-register that we want to use to
9702 substitute uses of REG (typically in MEMs) with.
9703 First check REG and BASE for being index registers;
9704 we can use them even if they are not dead. */
9705 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9706 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9714 /* Otherwise, look for a free index register. Since we have
9715 checked above that neiter REG nor BASE are index registers,
9716 if we find anything at all, it will be different from these
9718 for (i = first_index_reg; i <= last_index_reg; i++)
9720 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9721 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9722 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9723 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9725 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9726 const_reg = index_reg;
9727 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9732 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9733 (REGY), i.e. BASE, is not clobbered before the last use we'll
9736 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9737 && rtx_equal_p (SET_DEST (prev_set), reg)
9738 && reg_state[regno].use_index >= 0
9739 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9744 /* Change destination register and - if necessary - the
9745 constant value in PREV, the constant loading instruction. */
9746 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9747 if (reg_state[regno].offset != const0_rtx)
9748 validate_change (prev,
9749 &SET_SRC (prev_set),
9750 GEN_INT (INTVAL (SET_SRC (prev_set))
9751 + INTVAL (reg_state[regno].offset)),
9753 /* Now for every use of REG that we have recorded, replace REG
9755 for (i = reg_state[regno].use_index;
9756 i < RELOAD_COMBINE_MAX_USES; i++)
9757 validate_change (reg_state[regno].reg_use[i].insn,
9758 reg_state[regno].reg_use[i].usep,
9761 if (apply_change_group ())
9765 /* Delete the reg-reg addition. */
9766 PUT_CODE (insn, NOTE);
9767 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9768 NOTE_SOURCE_FILE (insn) = 0;
9770 if (reg_state[regno].offset != const0_rtx)
9772 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9774 for (np = ®_NOTES (prev); *np; )
9776 if (REG_NOTE_KIND (*np) == REG_EQUAL
9777 || REG_NOTE_KIND (*np) == REG_EQUIV)
9778 *np = XEXP (*np, 1);
9780 np = &XEXP (*np, 1);
9783 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9784 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9789 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
9790 if (GET_CODE (insn) == CALL_INSN)
9794 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9796 if (call_used_regs[i])
9798 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9799 reg_state[i].store_ruid = reload_combine_ruid;
9802 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9803 link = XEXP (link, 1))
9805 rtx use = XEXP (link, 0);
9806 int regno = REGNO (XEXP (use, 0));
9807 if (GET_CODE (use) == CLOBBER)
9809 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9810 reg_state[regno].store_ruid = reload_combine_ruid;
9813 reg_state[regno].use_index = -1;
9816 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9818 /* Non-spill registers might be used at the call destination in
9819 some unknown fashion, so we have to mark the unknown use. */
9821 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9822 && JUMP_LABEL (insn))
9823 live = &LABEL_LIVE (JUMP_LABEL (insn));
9825 live = &ever_live_at_start;
9826 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9828 if (TEST_HARD_REG_BIT (*live, i))
9829 reg_state[i].use_index = -1;
9832 reload_combine_note_use (&PATTERN (insn), insn);
9833 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9835 if (REG_NOTE_KIND (note) == REG_INC
9836 && GET_CODE (XEXP (note, 0)) == REG)
9838 int regno = REGNO (XEXP (note, 0));
9840 reg_state[regno].store_ruid = reload_combine_ruid;
9841 reg_state[regno].use_index = -1;
9848 /* Check if DST is a register or a subreg of a register; if it is,
9849 update reg_state[regno].store_ruid and reg_state[regno].use_index
9850 accordingly. Called via note_stores from reload_combine. */
9852 reload_combine_note_store (dst, set, data)
9854 void *data ATTRIBUTE_UNUSED;
9858 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9860 if (GET_CODE (dst) == SUBREG)
9862 regno = SUBREG_WORD (dst);
9863 dst = SUBREG_REG (dst);
9865 if (GET_CODE (dst) != REG)
9867 regno += REGNO (dst);
9869 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9870 careful with registers / register parts that are not full words.
9872 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9873 if (GET_CODE (set) != SET
9874 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9875 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9876 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9878 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9880 reg_state[i].use_index = -1;
9881 reg_state[i].store_ruid = reload_combine_ruid;
9886 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9888 reg_state[i].store_ruid = reload_combine_ruid;
9889 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9894 /* XP points to a piece of rtl that has to be checked for any uses of
9896 *XP is the pattern of INSN, or a part of it.
9897 Called from reload_combine, and recursively by itself. */
9899 reload_combine_note_use (xp, insn)
9903 enum rtx_code code = x->code;
9906 rtx offset = const0_rtx; /* For the REG case below. */
9911 if (GET_CODE (SET_DEST (x)) == REG)
9913 reload_combine_note_use (&SET_SRC (x), insn);
9919 if (GET_CODE (SET_DEST (x)) == REG)
9924 /* We are interested in (plus (reg) (const_int)) . */
9925 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9927 offset = XEXP (x, 1);
9932 int regno = REGNO (x);
9935 /* Some spurious USEs of pseudo registers might remain.
9936 Just ignore them. */
9937 if (regno >= FIRST_PSEUDO_REGISTER)
9940 /* If this register is already used in some unknown fashion, we
9942 If we decrement the index from zero to -1, we can't store more
9943 uses, so this register becomes used in an unknown fashion. */
9944 use_index = --reg_state[regno].use_index;
9948 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9950 /* We have found another use for a register that is already
9951 used later. Check if the offsets match; if not, mark the
9952 register as used in an unknown fashion. */
9953 if (! rtx_equal_p (offset, reg_state[regno].offset))
9955 reg_state[regno].use_index = -1;
9961 /* This is the first use of this register we have seen since we
9962 marked it as dead. */
9963 reg_state[regno].offset = offset;
9964 reg_state[regno].use_ruid = reload_combine_ruid;
9966 reg_state[regno].reg_use[use_index].insn = insn;
9967 reg_state[regno].reg_use[use_index].usep = xp;
9975 /* Recursively process the components of X. */
9976 fmt = GET_RTX_FORMAT (code);
9977 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9980 reload_combine_note_use (&XEXP (x, i), insn);
9981 else if (fmt[i] == 'E')
9983 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9984 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9989 /* See if we can reduce the cost of a constant by replacing a move with
9991 /* We cannot do our optimization across labels. Invalidating all the
9992 information about register contents we have would be costly, so we
9993 use last_label_luid (local variable of reload_cse_move2add) to note
9994 where the label is and then later disable any optimization that would
9996 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9997 reg_set_luid[n] is larger than last_label_luid[n] . */
9998 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9999 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
10000 reg_mode[n] to be valid.
10001 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
10002 has been set to reg_offset[n] in mode reg_mode[n] .
10003 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
10004 register n has been set to the sum of reg_offset[n] and register
10005 reg_base_reg[n], calculated in mode reg_mode[n] . */
10006 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
10007 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
10008 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
10009 /* move2add_luid is linearily increased while scanning the instructions
10010 from first to last. It is used to set reg_set_luid in
10011 reload_cse_move2add and move2add_note_store. */
10012 static int move2add_luid;
10014 /* Generate a CONST_INT and force it in the range of MODE. */
10016 gen_mode_int (mode, value)
10017 enum machine_mode mode;
10018 HOST_WIDE_INT value;
10020 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
10021 int width = GET_MODE_BITSIZE (mode);
10023 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
10025 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
10026 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
10027 cval |= (HOST_WIDE_INT) -1 << width;
10029 return GEN_INT (cval);
10033 reload_cse_move2add (first)
10038 int last_label_luid;
10040 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10041 reg_set_luid[i] = 0;
10043 last_label_luid = 0;
10045 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
10049 if (GET_CODE (insn) == CODE_LABEL)
10050 last_label_luid = move2add_luid;
10051 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
10053 pat = PATTERN (insn);
10054 /* For simplicity, we only perform this optimization on
10055 straightforward SETs. */
10056 if (GET_CODE (pat) == SET
10057 && GET_CODE (SET_DEST (pat)) == REG)
10059 rtx reg = SET_DEST (pat);
10060 int regno = REGNO (reg);
10061 rtx src = SET_SRC (pat);
10063 /* Check if we have valid information on the contents of this
10064 register in the mode of REG. */
10065 /* ??? We don't know how zero / sign extension is handled, hence
10066 we can't go from a narrower to a wider mode. */
10067 if (reg_set_luid[regno] > last_label_luid
10068 && (GET_MODE_SIZE (GET_MODE (reg))
10069 <= GET_MODE_SIZE (reg_mode[regno]))
10070 && GET_CODE (reg_offset[regno]) == CONST_INT)
10072 /* Try to transform (set (REGX) (CONST_INT A))
10074 (set (REGX) (CONST_INT B))
10076 (set (REGX) (CONST_INT A))
10078 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10080 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
10084 = gen_mode_int (GET_MODE (reg),
10085 INTVAL (src) - INTVAL (reg_offset[regno]));
10086 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10087 use (set (reg) (reg)) instead.
10088 We don't delete this insn, nor do we convert it into a
10089 note, to avoid losing register notes or the return
10090 value flag. jump2 already knowns how to get rid of
10092 if (new_src == const0_rtx)
10093 success = validate_change (insn, &SET_SRC (pat), reg, 0);
10094 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
10095 && have_add2_insn (GET_MODE (reg)))
10096 success = validate_change (insn, &PATTERN (insn),
10097 gen_add2_insn (reg, new_src), 0);
10098 reg_set_luid[regno] = move2add_luid;
10099 reg_mode[regno] = GET_MODE (reg);
10100 reg_offset[regno] = src;
10104 /* Try to transform (set (REGX) (REGY))
10105 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10107 (set (REGX) (REGY))
10108 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10111 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10113 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10114 else if (GET_CODE (src) == REG
10115 && reg_base_reg[regno] == REGNO (src)
10116 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10118 rtx next = next_nonnote_insn (insn);
10119 rtx set = NULL_RTX;
10121 set = single_set (next);
10124 && SET_DEST (set) == reg
10125 && GET_CODE (SET_SRC (set)) == PLUS
10126 && XEXP (SET_SRC (set), 0) == reg
10127 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10129 rtx src3 = XEXP (SET_SRC (set), 1);
10131 = gen_mode_int (GET_MODE (reg),
10133 - INTVAL (reg_offset[regno]));
10136 if (new_src == const0_rtx)
10137 /* See above why we create (set (reg) (reg)) here. */
10139 = validate_change (next, &SET_SRC (set), reg, 0);
10140 else if ((rtx_cost (new_src, PLUS)
10141 < 2 + rtx_cost (src3, SET))
10142 && have_add2_insn (GET_MODE (reg)))
10144 = validate_change (next, &PATTERN (next),
10145 gen_add2_insn (reg, new_src), 0);
10148 /* INSN might be the first insn in a basic block
10149 if the preceding insn is a conditional jump
10150 or a possible-throwing call. */
10151 PUT_CODE (insn, NOTE);
10152 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10153 NOTE_SOURCE_FILE (insn) = 0;
10156 reg_set_luid[regno] = move2add_luid;
10157 reg_mode[regno] = GET_MODE (reg);
10158 reg_offset[regno] = src3;
10165 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10167 if (REG_NOTE_KIND (note) == REG_INC
10168 && GET_CODE (XEXP (note, 0)) == REG)
10170 /* Indicate that this register has been recently written to,
10171 but the exact contents are not available. */
10172 int regno = REGNO (XEXP (note, 0));
10173 if (regno < FIRST_PSEUDO_REGISTER)
10175 reg_set_luid[regno] = move2add_luid;
10176 reg_offset[regno] = note;
10180 note_stores (PATTERN (insn), move2add_note_store, NULL);
10181 /* If this is a CALL_INSN, all call used registers are stored with
10183 if (GET_CODE (insn) == CALL_INSN)
10185 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10187 if (call_used_regs[i])
10189 reg_set_luid[i] = move2add_luid;
10190 reg_offset[i] = insn; /* Invalidate contents. */
10197 /* SET is a SET or CLOBBER that sets DST.
10198 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10199 Called from reload_cse_move2add via note_stores. */
10201 move2add_note_store (dst, set, data)
10203 void *data ATTRIBUTE_UNUSED;
10208 enum machine_mode mode = GET_MODE (dst);
10209 if (GET_CODE (dst) == SUBREG)
10211 regno = SUBREG_WORD (dst);
10212 dst = SUBREG_REG (dst);
10214 if (GET_CODE (dst) != REG)
10217 regno += REGNO (dst);
10219 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10220 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10221 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10222 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10224 rtx src = SET_SRC (set);
10226 reg_mode[regno] = mode;
10227 switch (GET_CODE (src))
10231 rtx src0 = XEXP (src, 0);
10232 if (GET_CODE (src0) == REG)
10234 if (REGNO (src0) != regno
10235 || reg_offset[regno] != const0_rtx)
10237 reg_base_reg[regno] = REGNO (src0);
10238 reg_set_luid[regno] = move2add_luid;
10240 reg_offset[regno] = XEXP (src, 1);
10243 reg_set_luid[regno] = move2add_luid;
10244 reg_offset[regno] = set; /* Invalidate contents. */
10249 reg_base_reg[regno] = REGNO (SET_SRC (set));
10250 reg_offset[regno] = const0_rtx;
10251 reg_set_luid[regno] = move2add_luid;
10255 reg_base_reg[regno] = -1;
10256 reg_offset[regno] = SET_SRC (set);
10257 reg_set_luid[regno] = move2add_luid;
10263 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10265 /* Indicate that this register has been recently written to,
10266 but the exact contents are not available. */
10267 reg_set_luid[i] = move2add_luid;
10268 reg_offset[i] = dst;
10273 #ifdef AUTO_INC_DEC
10275 add_auto_inc_notes (insn, x)
10279 enum rtx_code code = GET_CODE (x);
10283 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10286 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10290 /* Scan all the operand sub-expressions. */
10291 fmt = GET_RTX_FORMAT (code);
10292 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10295 add_auto_inc_notes (insn, XEXP (x, i));
10296 else if (fmt[i] == 'E')
10297 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10298 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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