1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
286 extern tree current_function_decl;
288 extern union tree_node *current_function_decl;
291 /* List of all insns needing reloads. */
292 static struct insn_chain *insns_need_reload;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from; /* Register number to be eliminated. */
302 int to; /* Register number used as replacement. */
303 int initial_offset; /* Initial difference between values. */
304 int can_eliminate; /* Non-zero if this elimination can be done. */
305 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
306 insns made by reload. */
307 int offset; /* Current offset between the two regs. */
308 int previous_offset; /* Offset at end of previous insn. */
309 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx; /* REG rtx for the replacement. */
318 static struct elim_table * reg_eliminate = 0;
320 /* This is an intermediate structure to initialize the table. It has
321 exactly the members provided by ELIMINABLE_REGS. */
322 static struct elim_table_1
326 } reg_eliminate_1[] =
328 /* If a set of eliminable registers was specified, define the table from it.
329 Otherwise, default to the normal case of the frame pointer being
330 replaced by the stack pointer. */
332 #ifdef ELIMINABLE_REGS
335 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
338 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
340 /* Record the number of pending eliminations that have an offset not equal
341 to their initial offset. If non-zero, we use a new copy of each
342 replacement result in any insns encountered. */
343 int num_not_at_initial_offset;
345 /* Count the number of registers that we may be able to eliminate. */
346 static int num_eliminable;
347 /* And the number of registers that are equivalent to a constant that
348 can be eliminated to frame_pointer / arg_pointer + constant. */
349 static int num_eliminable_invariants;
351 /* For each label, we record the offset of each elimination. If we reach
352 a label by more than one path and an offset differs, we cannot do the
353 elimination. This information is indexed by the number of the label.
354 The first table is an array of flags that records whether we have yet
355 encountered a label and the second table is an array of arrays, one
356 entry in the latter array for each elimination. */
358 static char *offsets_known_at;
359 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
361 /* Number of labels in the current function. */
363 static int num_labels;
365 struct hard_reg_n_uses
371 static void maybe_fix_stack_asms PROTO((void));
372 static void calculate_needs_all_insns PROTO((int));
373 static void calculate_needs PROTO((struct insn_chain *));
374 static void find_reload_regs PROTO((struct insn_chain *chain,
376 static void find_tworeg_group PROTO((struct insn_chain *, int,
378 static void find_group PROTO((struct insn_chain *, int,
380 static int possible_group_p PROTO((struct insn_chain *, int));
381 static void count_possible_groups PROTO((struct insn_chain *, int));
382 static int modes_equiv_for_class_p PROTO((enum machine_mode,
385 static void delete_caller_save_insns PROTO((void));
387 static void spill_failure PROTO((rtx));
388 static void new_spill_reg PROTO((struct insn_chain *, int, int,
390 static void maybe_mark_pseudo_spilled PROTO((int));
391 static void delete_dead_insn PROTO((rtx));
392 static void alter_reg PROTO((int, int));
393 static void set_label_offsets PROTO((rtx, rtx, int));
394 static int eliminate_regs_in_insn PROTO((rtx, int));
395 static void update_eliminable_offsets PROTO((void));
396 static void mark_not_eliminable PROTO((rtx, rtx));
397 static void set_initial_elim_offsets PROTO((void));
398 static void verify_initial_elim_offsets PROTO((void));
399 static void set_initial_label_offsets PROTO((void));
400 static void set_offsets_for_label PROTO((rtx));
401 static void init_elim_table PROTO((void));
402 static void update_eliminables PROTO((HARD_REG_SET *));
403 static void spill_hard_reg PROTO((int, FILE *, int));
404 static int finish_spills PROTO((int, FILE *));
405 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
406 static void scan_paradoxical_subregs PROTO((rtx));
407 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
408 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
409 static void order_regs_for_reload PROTO((struct insn_chain *));
410 static void reload_as_needed PROTO((int));
411 static void forget_old_reloads_1 PROTO((rtx, rtx));
412 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
413 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
415 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
417 static int reload_reg_free_p PROTO((int, int, enum reload_type));
418 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
419 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
420 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
422 static void choose_reload_regs PROTO((struct insn_chain *));
423 static void merge_assigned_reloads PROTO((rtx));
424 static void emit_reload_insns PROTO((struct insn_chain *));
425 static void delete_output_reload PROTO((rtx, int, int));
426 static void delete_address_reloads PROTO((rtx, rtx));
427 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
428 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
429 static int constraint_accepts_reg_p PROTO((const char *, rtx));
430 static void reload_cse_regs_1 PROTO((rtx));
431 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
432 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
433 static void reload_cse_invalidate_mem PROTO((rtx));
434 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
435 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
436 static int reload_cse_noop_set_p PROTO((rtx, rtx));
437 static int reload_cse_simplify_set PROTO((rtx, rtx));
438 static int reload_cse_simplify_operands PROTO((rtx));
439 static void reload_cse_check_clobber PROTO((rtx, rtx));
440 static void reload_cse_record_set PROTO((rtx, rtx));
441 static void reload_combine PROTO((void));
442 static void reload_combine_note_use PROTO((rtx *, rtx));
443 static void reload_combine_note_store PROTO((rtx, rtx));
444 static void reload_cse_move2add PROTO((rtx));
445 static void move2add_note_store PROTO((rtx, rtx));
447 static void add_auto_inc_notes PROTO((rtx, rtx));
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
464 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
466 spill_indirect_levels = 0;
468 while (memory_address_p (QImode, tem))
470 spill_indirect_levels++;
471 tem = gen_rtx_MEM (Pmode, tem);
474 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
476 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
477 indirect_symref_ok = memory_address_p (QImode, tem);
479 /* See if reg+reg is a valid (and offsettable) address. */
481 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
483 tem = gen_rtx_PLUS (Pmode,
484 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
485 gen_rtx_REG (Pmode, i));
486 /* This way, we make sure that reg+reg is an offsettable address. */
487 tem = plus_constant (tem, 4);
489 if (memory_address_p (QImode, tem))
491 double_reg_address_ok = 1;
496 /* Initialize obstack for our rtl allocation. */
497 gcc_obstack_init (&reload_obstack);
498 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
501 /* List of insn chains that are currently unused. */
502 static struct insn_chain *unused_insn_chains = 0;
504 /* Allocate an empty insn_chain structure. */
508 struct insn_chain *c;
510 if (unused_insn_chains == 0)
512 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
513 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
514 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
518 c = unused_insn_chains;
519 unused_insn_chains = c->next;
521 c->is_caller_save_insn = 0;
522 c->need_operand_change = 0;
528 /* Small utility function to set all regs in hard reg set TO which are
529 allocated to pseudos in regset FROM. */
531 compute_use_by_pseudos (to, from)
536 EXECUTE_IF_SET_IN_REG_SET
537 (from, FIRST_PSEUDO_REGISTER, regno,
539 int r = reg_renumber[regno];
543 /* reload_combine uses the information from
544 BASIC_BLOCK->global_live_at_start, which might still
545 contain registers that have not actually been allocated
546 since they have an equivalence. */
547 if (! reload_completed)
552 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
554 SET_HARD_REG_BIT (*to, r + nregs);
559 /* Global variables used by reload and its subroutines. */
561 /* Set during calculate_needs if an insn needs register elimination. */
562 static int something_needs_elimination;
563 /* Set during calculate_needs if an insn needs an operand changed. */
564 int something_needs_operands_changed;
566 /* Nonzero means we couldn't get enough spill regs. */
569 /* Main entry point for the reload pass.
571 FIRST is the first insn of the function being compiled.
573 GLOBAL nonzero means we were called from global_alloc
574 and should attempt to reallocate any pseudoregs that we
575 displace from hard regs we will use for reloads.
576 If GLOBAL is zero, we do not have enough information to do that,
577 so any pseudo reg that is spilled must go to the stack.
579 DUMPFILE is the global-reg debugging dump file stream, or 0.
580 If it is nonzero, messages are written to it to describe
581 which registers are seized as reload regs, which pseudo regs
582 are spilled from them, and where the pseudo regs are reallocated to.
584 Return value is nonzero if reload failed
585 and we must not do any more for this function. */
588 reload (first, global, dumpfile)
595 register struct elim_table *ep;
597 /* The two pointers used to track the true location of the memory used
598 for label offsets. */
599 char *real_known_ptr = NULL_PTR;
600 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
602 /* Make sure even insns with volatile mem refs are recognizable. */
607 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
609 /* Make sure that the last insn in the chain
610 is not something that needs reloading. */
611 emit_note (NULL_PTR, NOTE_INSN_DELETED);
613 /* Enable find_equiv_reg to distinguish insns made by reload. */
614 reload_first_uid = get_max_uid ();
616 #ifdef SECONDARY_MEMORY_NEEDED
617 /* Initialize the secondary memory table. */
618 clear_secondary_mem ();
621 /* We don't have a stack slot for any spill reg yet. */
622 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
623 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
625 /* Initialize the save area information for caller-save, in case some
629 /* Compute which hard registers are now in use
630 as homes for pseudo registers.
631 This is done here rather than (eg) in global_alloc
632 because this point is reached even if not optimizing. */
633 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
636 /* A function that receives a nonlocal goto must save all call-saved
638 if (current_function_has_nonlocal_label)
639 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
641 if (! call_used_regs[i] && ! fixed_regs[i])
642 regs_ever_live[i] = 1;
645 /* Find all the pseudo registers that didn't get hard regs
646 but do have known equivalent constants or memory slots.
647 These include parameters (known equivalent to parameter slots)
648 and cse'd or loop-moved constant memory addresses.
650 Record constant equivalents in reg_equiv_constant
651 so they will be substituted by find_reloads.
652 Record memory equivalents in reg_mem_equiv so they can
653 be substituted eventually by altering the REG-rtx's. */
655 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
656 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
657 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
658 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
659 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
660 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
661 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
662 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
663 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
664 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
665 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
666 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
667 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
668 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
669 pseudo_forbidden_regs
670 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
672 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
674 CLEAR_HARD_REG_SET (bad_spill_regs_global);
675 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
677 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
678 Also find all paradoxical subregs and find largest such for each pseudo.
679 On machines with small register classes, record hard registers that
680 are used for user variables. These can never be used for spills.
681 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
682 caller-saved registers must be marked live. */
684 num_eliminable_invariants = 0;
685 for (insn = first; insn; insn = NEXT_INSN (insn))
687 rtx set = single_set (insn);
689 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
690 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
691 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
692 if (! call_used_regs[i])
693 regs_ever_live[i] = 1;
695 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
697 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
699 #ifdef LEGITIMATE_PIC_OPERAND_P
700 && (! function_invariant_p (XEXP (note, 0))
702 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
706 rtx x = XEXP (note, 0);
707 i = REGNO (SET_DEST (set));
708 if (i > LAST_VIRTUAL_REGISTER)
710 if (GET_CODE (x) == MEM)
712 /* If the operand is a PLUS, the MEM may be shared,
713 so make sure we have an unshared copy here. */
714 if (GET_CODE (XEXP (x, 0)) == PLUS)
717 reg_equiv_memory_loc[i] = x;
719 else if (function_invariant_p (x))
721 if (GET_CODE (x) == PLUS)
723 /* This is PLUS of frame pointer and a constant,
724 and might be shared. Unshare it. */
725 reg_equiv_constant[i] = copy_rtx (x);
726 num_eliminable_invariants++;
728 else if (x == frame_pointer_rtx
729 || x == arg_pointer_rtx)
731 reg_equiv_constant[i] = x;
732 num_eliminable_invariants++;
734 else if (LEGITIMATE_CONSTANT_P (x))
735 reg_equiv_constant[i] = x;
737 reg_equiv_memory_loc[i]
738 = force_const_mem (GET_MODE (SET_DEST (set)), x);
743 /* If this register is being made equivalent to a MEM
744 and the MEM is not SET_SRC, the equivalencing insn
745 is one with the MEM as a SET_DEST and it occurs later.
746 So don't mark this insn now. */
747 if (GET_CODE (x) != MEM
748 || rtx_equal_p (SET_SRC (set), x))
750 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
755 /* If this insn is setting a MEM from a register equivalent to it,
756 this is the equivalencing insn. */
757 else if (set && GET_CODE (SET_DEST (set)) == MEM
758 && GET_CODE (SET_SRC (set)) == REG
759 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
760 && rtx_equal_p (SET_DEST (set),
761 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
762 reg_equiv_init[REGNO (SET_SRC (set))]
763 = gen_rtx_INSN_LIST (VOIDmode, insn,
764 reg_equiv_init[REGNO (SET_SRC (set))]);
766 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
767 scan_paradoxical_subregs (PATTERN (insn));
772 num_labels = max_label_num () - get_first_label_num ();
774 /* Allocate the tables used to store offset information at labels. */
775 /* We used to use alloca here, but the size of what it would try to
776 allocate would occasionally cause it to exceed the stack limit and
777 cause a core dump. */
778 real_known_ptr = xmalloc (num_labels);
780 = (int (*)[NUM_ELIMINABLE_REGS])
781 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
783 offsets_known_at = real_known_ptr - get_first_label_num ();
785 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
787 /* Alter each pseudo-reg rtx to contain its hard reg number.
788 Assign stack slots to the pseudos that lack hard regs or equivalents.
789 Do not touch virtual registers. */
791 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
794 /* If we have some registers we think can be eliminated, scan all insns to
795 see if there is an insn that sets one of these registers to something
796 other than itself plus a constant. If so, the register cannot be
797 eliminated. Doing this scan here eliminates an extra pass through the
798 main reload loop in the most common case where register elimination
800 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
801 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
802 || GET_CODE (insn) == CALL_INSN)
803 note_stores (PATTERN (insn), mark_not_eliminable);
805 #ifndef REGISTER_CONSTRAINTS
806 /* If all the pseudo regs have hard regs,
807 except for those that are never referenced,
808 we know that no reloads are needed. */
809 /* But that is not true if there are register constraints, since
810 in that case some pseudos might be in the wrong kind of hard reg. */
812 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
813 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
816 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
818 free (real_known_ptr);
820 free (reg_equiv_constant);
821 free (reg_equiv_memory_loc);
822 free (reg_equiv_mem);
823 free (reg_equiv_init);
824 free (reg_equiv_address);
825 free (reg_max_ref_width);
826 free (reg_old_renumber);
827 free (pseudo_previous_regs);
828 free (pseudo_forbidden_regs);
833 maybe_fix_stack_asms ();
835 insns_need_reload = 0;
836 something_needs_elimination = 0;
838 /* Initialize to -1, which means take the first spill register. */
841 spilled_pseudos = ALLOCA_REG_SET ();
843 /* Spill any hard regs that we know we can't eliminate. */
844 CLEAR_HARD_REG_SET (used_spill_regs);
845 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
846 if (! ep->can_eliminate)
847 spill_hard_reg (ep->from, dumpfile, 1);
849 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
850 if (frame_pointer_needed)
851 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
853 finish_spills (global, dumpfile);
855 /* From now on, we may need to generate moves differently. We may also
856 allow modifications of insns which cause them to not be recognized.
857 Any such modifications will be cleaned up during reload itself. */
858 reload_in_progress = 1;
860 /* This loop scans the entire function each go-round
861 and repeats until one repetition spills no additional hard regs. */
864 int something_changed;
866 struct insn_chain *chain;
868 HOST_WIDE_INT starting_frame_size;
870 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
871 here because the stack size may be a part of the offset computation
872 for register elimination, and there might have been new stack slots
873 created in the last iteration of this loop. */
874 assign_stack_local (BLKmode, 0, 0);
876 starting_frame_size = get_frame_size ();
878 set_initial_elim_offsets ();
879 set_initial_label_offsets ();
881 /* For each pseudo register that has an equivalent location defined,
882 try to eliminate any eliminable registers (such as the frame pointer)
883 assuming initial offsets for the replacement register, which
886 If the resulting location is directly addressable, substitute
887 the MEM we just got directly for the old REG.
889 If it is not addressable but is a constant or the sum of a hard reg
890 and constant, it is probably not addressable because the constant is
891 out of range, in that case record the address; we will generate
892 hairy code to compute the address in a register each time it is
893 needed. Similarly if it is a hard register, but one that is not
894 valid as an address register.
896 If the location is not addressable, but does not have one of the
897 above forms, assign a stack slot. We have to do this to avoid the
898 potential of producing lots of reloads if, e.g., a location involves
899 a pseudo that didn't get a hard register and has an equivalent memory
900 location that also involves a pseudo that didn't get a hard register.
902 Perhaps at some point we will improve reload_when_needed handling
903 so this problem goes away. But that's very hairy. */
905 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
906 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
908 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
910 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
912 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
913 else if (CONSTANT_P (XEXP (x, 0))
914 || (GET_CODE (XEXP (x, 0)) == REG
915 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
916 || (GET_CODE (XEXP (x, 0)) == PLUS
917 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
918 && (REGNO (XEXP (XEXP (x, 0), 0))
919 < FIRST_PSEUDO_REGISTER)
920 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
921 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
924 /* Make a new stack slot. Then indicate that something
925 changed so we go back and recompute offsets for
926 eliminable registers because the allocation of memory
927 below might change some offset. reg_equiv_{mem,address}
928 will be set up for this pseudo on the next pass around
930 reg_equiv_memory_loc[i] = 0;
931 reg_equiv_init[i] = 0;
936 if (caller_save_needed)
939 /* If we allocated another stack slot, redo elimination bookkeeping. */
940 if (starting_frame_size != get_frame_size ())
943 if (caller_save_needed)
945 save_call_clobbered_regs ();
946 /* That might have allocated new insn_chain structures. */
947 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
950 calculate_needs_all_insns (global);
952 CLEAR_REG_SET (spilled_pseudos);
955 something_changed = 0;
957 /* If we allocated any new memory locations, make another pass
958 since it might have changed elimination offsets. */
959 if (starting_frame_size != get_frame_size ())
960 something_changed = 1;
963 HARD_REG_SET to_spill;
964 CLEAR_HARD_REG_SET (to_spill);
965 update_eliminables (&to_spill);
966 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
967 if (TEST_HARD_REG_BIT (to_spill, i))
969 spill_hard_reg (i, dumpfile, 1);
972 /* Regardless of the state of spills, if we previously had
973 a register that we thought we could eliminate, but no can
974 not eliminate, we must run another pass.
976 Consider pseudos which have an entry in reg_equiv_* which
977 reference an eliminable register. We must make another pass
978 to update reg_equiv_* so that we do not substitute in the
979 old value from when we thought the elimination could be
981 something_changed = 1;
985 CLEAR_HARD_REG_SET (used_spill_regs);
986 /* Try to satisfy the needs for each insn. */
987 for (chain = insns_need_reload; chain != 0;
988 chain = chain->next_need_reload)
989 find_reload_regs (chain, dumpfile);
994 if (insns_need_reload != 0 || did_spill)
995 something_changed |= finish_spills (global, dumpfile);
997 if (! something_changed)
1000 if (caller_save_needed)
1001 delete_caller_save_insns ();
1004 /* If global-alloc was run, notify it of any register eliminations we have
1007 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1008 if (ep->can_eliminate)
1009 mark_elimination (ep->from, ep->to);
1011 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1012 If that insn didn't set the register (i.e., it copied the register to
1013 memory), just delete that insn instead of the equivalencing insn plus
1014 anything now dead. If we call delete_dead_insn on that insn, we may
1015 delete the insn that actually sets the register if the register dies
1016 there and that is incorrect. */
1018 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1020 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1023 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1025 rtx equiv_insn = XEXP (list, 0);
1026 if (GET_CODE (equiv_insn) == NOTE)
1028 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1029 delete_dead_insn (equiv_insn);
1032 PUT_CODE (equiv_insn, NOTE);
1033 NOTE_SOURCE_FILE (equiv_insn) = 0;
1034 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1040 /* Use the reload registers where necessary
1041 by generating move instructions to move the must-be-register
1042 values into or out of the reload registers. */
1044 if (insns_need_reload != 0 || something_needs_elimination
1045 || something_needs_operands_changed)
1047 int old_frame_size = get_frame_size ();
1049 reload_as_needed (global);
1051 if (old_frame_size != get_frame_size ())
1055 verify_initial_elim_offsets ();
1058 /* If we were able to eliminate the frame pointer, show that it is no
1059 longer live at the start of any basic block. If it ls live by
1060 virtue of being in a pseudo, that pseudo will be marked live
1061 and hence the frame pointer will be known to be live via that
1064 if (! frame_pointer_needed)
1065 for (i = 0; i < n_basic_blocks; i++)
1066 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1067 HARD_FRAME_POINTER_REGNUM);
1069 /* Come here (with failure set nonzero) if we can't get enough spill regs
1070 and we decide not to abort about it. */
1073 reload_in_progress = 0;
1075 /* Now eliminate all pseudo regs by modifying them into
1076 their equivalent memory references.
1077 The REG-rtx's for the pseudos are modified in place,
1078 so all insns that used to refer to them now refer to memory.
1080 For a reg that has a reg_equiv_address, all those insns
1081 were changed by reloading so that no insns refer to it any longer;
1082 but the DECL_RTL of a variable decl may refer to it,
1083 and if so this causes the debugging info to mention the variable. */
1085 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1090 int is_readonly = 0;
1092 if (reg_equiv_memory_loc[i])
1094 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1095 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1096 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1099 if (reg_equiv_mem[i])
1100 addr = XEXP (reg_equiv_mem[i], 0);
1102 if (reg_equiv_address[i])
1103 addr = reg_equiv_address[i];
1107 if (reg_renumber[i] < 0)
1109 rtx reg = regno_reg_rtx[i];
1110 XEXP (reg, 0) = addr;
1111 REG_USERVAR_P (reg) = 0;
1112 RTX_UNCHANGING_P (reg) = is_readonly;
1113 MEM_IN_STRUCT_P (reg) = in_struct;
1114 MEM_SCALAR_P (reg) = is_scalar;
1115 /* We have no alias information about this newly created
1117 MEM_ALIAS_SET (reg) = 0;
1118 PUT_CODE (reg, MEM);
1120 else if (reg_equiv_mem[i])
1121 XEXP (reg_equiv_mem[i], 0) = addr;
1125 /* We must set reload_completed now since the cleanup_subreg_operands call
1126 below will re-recognize each insn and reload may have generated insns
1127 which are only valid during and after reload. */
1128 reload_completed = 1;
1130 /* Make a pass over all the insns and delete all USEs which we
1131 inserted only to tag a REG_EQUAL note on them. Remove all
1132 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1133 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1134 REG_LIBCALL notes since they are no longer useful or accurate.
1135 Strip and regenerate REG_INC notes that may have been moved
1138 for (insn = first; insn; insn = NEXT_INSN (insn))
1139 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1143 if ((GET_CODE (PATTERN (insn)) == USE
1144 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1145 || GET_CODE (PATTERN (insn)) == CLOBBER)
1147 PUT_CODE (insn, NOTE);
1148 NOTE_SOURCE_FILE (insn) = 0;
1149 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1153 pnote = ®_NOTES (insn);
1156 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1157 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1158 || REG_NOTE_KIND (*pnote) == REG_INC
1159 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1160 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1161 *pnote = XEXP (*pnote, 1);
1163 pnote = &XEXP (*pnote, 1);
1167 add_auto_inc_notes (insn, PATTERN (insn));
1170 /* And simplify (subreg (reg)) if it appears as an operand. */
1171 cleanup_subreg_operands (insn);
1174 /* If we are doing stack checking, give a warning if this function's
1175 frame size is larger than we expect. */
1176 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1178 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1180 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1181 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1182 size += UNITS_PER_WORD;
1184 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1185 warning ("frame size too large for reliable stack checking");
1188 /* If we are doing stack checking, give a warning if this function's
1189 frame size is larger than we expect. */
1190 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1192 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1193 static int verbose_warned = 0;
1195 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1196 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1197 size += UNITS_PER_WORD;
1199 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1201 warning ("frame size too large for reliable stack checking");
1202 if (! verbose_warned)
1204 warning ("try reducing the number of local variables");
1210 /* Indicate that we no longer have known memory locations or constants. */
1211 if (reg_equiv_constant)
1212 free (reg_equiv_constant);
1213 reg_equiv_constant = 0;
1214 if (reg_equiv_memory_loc)
1215 free (reg_equiv_memory_loc);
1216 reg_equiv_memory_loc = 0;
1219 free (real_known_ptr);
1223 free (reg_equiv_mem);
1224 free (reg_equiv_init);
1225 free (reg_equiv_address);
1226 free (reg_max_ref_width);
1227 free (reg_old_renumber);
1228 free (pseudo_previous_regs);
1229 free (pseudo_forbidden_regs);
1231 FREE_REG_SET (spilled_pseudos);
1233 CLEAR_HARD_REG_SET (used_spill_regs);
1234 for (i = 0; i < n_spills; i++)
1235 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1237 /* Free all the insn_chain structures at once. */
1238 obstack_free (&reload_obstack, reload_startobj);
1239 unused_insn_chains = 0;
1244 /* Yet another special case. Unfortunately, reg-stack forces people to
1245 write incorrect clobbers in asm statements. These clobbers must not
1246 cause the register to appear in bad_spill_regs, otherwise we'll call
1247 fatal_insn later. We clear the corresponding regnos in the live
1248 register sets to avoid this.
1249 The whole thing is rather sick, I'm afraid. */
1251 maybe_fix_stack_asms ()
1254 char *constraints[MAX_RECOG_OPERANDS];
1255 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1256 struct insn_chain *chain;
1258 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1261 HARD_REG_SET clobbered, allowed;
1264 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1265 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1267 pat = PATTERN (chain->insn);
1268 if (GET_CODE (pat) != PARALLEL)
1271 CLEAR_HARD_REG_SET (clobbered);
1272 CLEAR_HARD_REG_SET (allowed);
1274 /* First, make a mask of all stack regs that are clobbered. */
1275 for (i = 0; i < XVECLEN (pat, 0); i++)
1277 rtx t = XVECEXP (pat, 0, i);
1278 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1279 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1282 /* Get the operand values and constraints out of the insn. */
1283 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1284 constraints, operand_mode);
1286 /* For every operand, see what registers are allowed. */
1287 for (i = 0; i < noperands; i++)
1289 char *p = constraints[i];
1290 /* For every alternative, we compute the class of registers allowed
1291 for reloading in CLS, and merge its contents into the reg set
1293 int cls = (int) NO_REGS;
1299 if (c == '\0' || c == ',' || c == '#')
1301 /* End of one alternative - mark the regs in the current
1302 class, and reset the class. */
1303 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1308 } while (c != '\0' && c != ',');
1316 case '=': case '+': case '*': case '%': case '?': case '!':
1317 case '0': case '1': case '2': case '3': case '4': case 'm':
1318 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1319 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1320 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1322 #ifdef EXTRA_CONSTRAINT
1323 case 'Q': case 'R': case 'S': case 'T': case 'U':
1328 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1333 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1337 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1342 /* Those of the registers which are clobbered, but allowed by the
1343 constraints, must be usable as reload registers. So clear them
1344 out of the life information. */
1345 AND_HARD_REG_SET (allowed, clobbered);
1346 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1347 if (TEST_HARD_REG_BIT (allowed, i))
1349 CLEAR_REGNO_REG_SET (chain->live_before, i);
1350 CLEAR_REGNO_REG_SET (chain->live_after, i);
1358 /* Walk the chain of insns, and determine for each whether it needs reloads
1359 and/or eliminations. Build the corresponding insns_need_reload list, and
1360 set something_needs_elimination as appropriate. */
1362 calculate_needs_all_insns (global)
1365 struct insn_chain **pprev_reload = &insns_need_reload;
1366 struct insn_chain **pchain;
1368 something_needs_elimination = 0;
1370 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1373 struct insn_chain *chain;
1378 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1379 include REG_LABEL), we need to see what effects this has on the
1380 known offsets at labels. */
1382 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1383 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1384 && REG_NOTES (insn) != 0))
1385 set_label_offsets (insn, insn, 0);
1387 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1389 rtx old_body = PATTERN (insn);
1390 int old_code = INSN_CODE (insn);
1391 rtx old_notes = REG_NOTES (insn);
1392 int did_elimination = 0;
1393 int operands_changed = 0;
1394 rtx set = single_set (insn);
1396 /* Skip insns that only set an equivalence. */
1397 if (set && GET_CODE (SET_DEST (set)) == REG
1398 && reg_renumber[REGNO (SET_DEST (set))] < 0
1399 && reg_equiv_constant[REGNO (SET_DEST (set))])
1401 /* Must clear out the shortcuts, in case they were set last
1403 chain->need_elim = 0;
1404 chain->need_reload = 0;
1405 chain->need_operand_change = 0;
1409 /* If needed, eliminate any eliminable registers. */
1410 if (num_eliminable || num_eliminable_invariants)
1411 did_elimination = eliminate_regs_in_insn (insn, 0);
1413 /* Analyze the instruction. */
1414 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1415 global, spill_reg_order);
1417 /* If a no-op set needs more than one reload, this is likely
1418 to be something that needs input address reloads. We
1419 can't get rid of this cleanly later, and it is of no use
1420 anyway, so discard it now.
1421 We only do this when expensive_optimizations is enabled,
1422 since this complements reload inheritance / output
1423 reload deletion, and it can make debugging harder. */
1424 if (flag_expensive_optimizations && n_reloads > 1)
1426 rtx set = single_set (insn);
1428 && SET_SRC (set) == SET_DEST (set)
1429 && GET_CODE (SET_SRC (set)) == REG
1430 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1432 PUT_CODE (insn, NOTE);
1433 NOTE_SOURCE_FILE (insn) = 0;
1434 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1439 update_eliminable_offsets ();
1441 /* Remember for later shortcuts which insns had any reloads or
1442 register eliminations. */
1443 chain->need_elim = did_elimination;
1444 chain->need_reload = n_reloads > 0;
1445 chain->need_operand_change = operands_changed;
1447 /* Discard any register replacements done. */
1448 if (did_elimination)
1450 obstack_free (&reload_obstack, reload_firstobj);
1451 PATTERN (insn) = old_body;
1452 INSN_CODE (insn) = old_code;
1453 REG_NOTES (insn) = old_notes;
1454 something_needs_elimination = 1;
1457 something_needs_operands_changed |= operands_changed;
1461 *pprev_reload = chain;
1462 pprev_reload = &chain->next_need_reload;
1464 calculate_needs (chain);
1471 /* Compute the most additional registers needed by one instruction,
1472 given by CHAIN. Collect information separately for each class of regs.
1474 To compute the number of reload registers of each class needed for an
1475 insn, we must simulate what choose_reload_regs can do. We do this by
1476 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1477 reloads are used in both. The input part uses those reloads,
1478 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1479 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1480 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1482 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1483 which are live for the entire output portion, and the maximum of all the
1484 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1486 The total number of registers needed is the maximum of the
1487 inputs and outputs. */
1490 calculate_needs (chain)
1491 struct insn_chain *chain;
1495 /* Each `struct needs' corresponds to one RELOAD_... type. */
1499 struct needs output;
1501 struct needs other_addr;
1502 struct needs op_addr;
1503 struct needs op_addr_reload;
1504 struct needs in_addr[MAX_RECOG_OPERANDS];
1505 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1506 struct needs out_addr[MAX_RECOG_OPERANDS];
1507 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1510 bzero ((char *) chain->group_size, sizeof chain->group_size);
1511 for (i = 0; i < N_REG_CLASSES; i++)
1512 chain->group_mode[i] = VOIDmode;
1513 bzero ((char *) &insn_needs, sizeof insn_needs);
1515 /* Count each reload once in every class
1516 containing the reload's own class. */
1518 for (i = 0; i < n_reloads; i++)
1520 register enum reg_class *p;
1521 enum reg_class class = reload_reg_class[i];
1523 enum machine_mode mode;
1524 struct needs *this_needs;
1526 /* Don't count the dummy reloads, for which one of the
1527 regs mentioned in the insn can be used for reloading.
1528 Don't count optional reloads.
1529 Don't count reloads that got combined with others. */
1530 if (reload_reg_rtx[i] != 0
1531 || reload_optional[i] != 0
1532 || (reload_out[i] == 0 && reload_in[i] == 0
1533 && ! reload_secondary_p[i]))
1536 mode = reload_inmode[i];
1537 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1538 mode = reload_outmode[i];
1539 size = CLASS_MAX_NREGS (class, mode);
1541 /* Decide which time-of-use to count this reload for. */
1542 switch (reload_when_needed[i])
1545 this_needs = &insn_needs.other;
1547 case RELOAD_FOR_INPUT:
1548 this_needs = &insn_needs.input;
1550 case RELOAD_FOR_OUTPUT:
1551 this_needs = &insn_needs.output;
1553 case RELOAD_FOR_INSN:
1554 this_needs = &insn_needs.insn;
1556 case RELOAD_FOR_OTHER_ADDRESS:
1557 this_needs = &insn_needs.other_addr;
1559 case RELOAD_FOR_INPUT_ADDRESS:
1560 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1562 case RELOAD_FOR_INPADDR_ADDRESS:
1563 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1565 case RELOAD_FOR_OUTPUT_ADDRESS:
1566 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1568 case RELOAD_FOR_OUTADDR_ADDRESS:
1569 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1571 case RELOAD_FOR_OPERAND_ADDRESS:
1572 this_needs = &insn_needs.op_addr;
1574 case RELOAD_FOR_OPADDR_ADDR:
1575 this_needs = &insn_needs.op_addr_reload;
1583 enum machine_mode other_mode, allocate_mode;
1585 /* Count number of groups needed separately from
1586 number of individual regs needed. */
1587 this_needs->groups[(int) class]++;
1588 p = reg_class_superclasses[(int) class];
1589 while (*p != LIM_REG_CLASSES)
1590 this_needs->groups[(int) *p++]++;
1592 /* Record size and mode of a group of this class. */
1593 /* If more than one size group is needed,
1594 make all groups the largest needed size. */
1595 if (chain->group_size[(int) class] < size)
1597 other_mode = chain->group_mode[(int) class];
1598 allocate_mode = mode;
1600 chain->group_size[(int) class] = size;
1601 chain->group_mode[(int) class] = mode;
1606 allocate_mode = chain->group_mode[(int) class];
1609 /* Crash if two dissimilar machine modes both need
1610 groups of consecutive regs of the same class. */
1612 if (other_mode != VOIDmode && other_mode != allocate_mode
1613 && ! modes_equiv_for_class_p (allocate_mode,
1615 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1620 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1621 p = reg_class_superclasses[(int) class];
1622 while (*p != LIM_REG_CLASSES)
1623 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1629 /* All reloads have been counted for this insn;
1630 now merge the various times of use.
1631 This sets insn_needs, etc., to the maximum total number
1632 of registers needed at any point in this insn. */
1634 for (i = 0; i < N_REG_CLASSES; i++)
1636 int j, in_max, out_max;
1638 /* Compute normal and nongroup needs. */
1639 for (j = 0; j <= 1; j++)
1642 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1644 in_max = MAX (in_max,
1645 (insn_needs.in_addr[k].regs[j][i]
1646 + insn_needs.in_addr_addr[k].regs[j][i]));
1647 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1648 out_max = MAX (out_max,
1649 insn_needs.out_addr_addr[k].regs[j][i]);
1652 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1653 and operand addresses but not things used to reload
1654 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1655 don't conflict with things needed to reload inputs or
1658 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1659 insn_needs.op_addr_reload.regs[j][i]),
1662 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1664 insn_needs.input.regs[j][i]
1665 = MAX (insn_needs.input.regs[j][i]
1666 + insn_needs.op_addr.regs[j][i]
1667 + insn_needs.insn.regs[j][i],
1668 in_max + insn_needs.input.regs[j][i]);
1670 insn_needs.output.regs[j][i] += out_max;
1671 insn_needs.other.regs[j][i]
1672 += MAX (MAX (insn_needs.input.regs[j][i],
1673 insn_needs.output.regs[j][i]),
1674 insn_needs.other_addr.regs[j][i]);
1678 /* Now compute group needs. */
1679 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1681 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1682 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1683 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1684 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1687 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1688 insn_needs.op_addr_reload.groups[i]),
1690 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1692 insn_needs.input.groups[i]
1693 = MAX (insn_needs.input.groups[i]
1694 + insn_needs.op_addr.groups[i]
1695 + insn_needs.insn.groups[i],
1696 in_max + insn_needs.input.groups[i]);
1698 insn_needs.output.groups[i] += out_max;
1699 insn_needs.other.groups[i]
1700 += MAX (MAX (insn_needs.input.groups[i],
1701 insn_needs.output.groups[i]),
1702 insn_needs.other_addr.groups[i]);
1705 /* Record the needs for later. */
1706 chain->need = insn_needs.other;
1709 /* Find a group of exactly 2 registers.
1711 First try to fill out the group by spilling a single register which
1712 would allow completion of the group.
1714 Then try to create a new group from a pair of registers, neither of
1715 which are explicitly used.
1717 Then try to create a group from any pair of registers. */
1720 find_tworeg_group (chain, class, dumpfile)
1721 struct insn_chain *chain;
1726 /* First, look for a register that will complete a group. */
1727 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1731 j = potential_reload_regs[i];
1732 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1733 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1734 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1735 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1736 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1737 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1738 /* We don't want one part of another group.
1739 We could get "two groups" that overlap! */
1740 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1741 || (j < FIRST_PSEUDO_REGISTER - 1
1742 && (other = j + 1, spill_reg_order[other] >= 0)
1743 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1744 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1745 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1746 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1747 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1749 register enum reg_class *p;
1751 /* We have found one that will complete a group,
1752 so count off one group as provided. */
1753 chain->need.groups[class]--;
1754 p = reg_class_superclasses[class];
1755 while (*p != LIM_REG_CLASSES)
1757 if (chain->group_size [(int) *p] <= chain->group_size [class])
1758 chain->need.groups[(int) *p]--;
1762 /* Indicate both these regs are part of a group. */
1763 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1764 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1768 /* We can't complete a group, so start one. */
1769 if (i == FIRST_PSEUDO_REGISTER)
1770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1773 j = potential_reload_regs[i];
1774 /* Verify that J+1 is a potential reload reg. */
1775 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1776 if (potential_reload_regs[k] == j + 1)
1778 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1779 && k < FIRST_PSEUDO_REGISTER
1780 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1781 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1782 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1783 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1784 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1785 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1789 /* I should be the index in potential_reload_regs
1790 of the new reload reg we have found. */
1792 new_spill_reg (chain, i, class, 0, dumpfile);
1795 /* Find a group of more than 2 registers.
1796 Look for a sufficient sequence of unspilled registers, and spill them all
1800 find_group (chain, class, dumpfile)
1801 struct insn_chain *chain;
1807 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1809 int j = potential_reload_regs[i];
1812 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1813 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1816 /* Check each reg in the sequence. */
1817 for (k = 0; k < chain->group_size[class]; k++)
1818 if (! (spill_reg_order[j + k] < 0
1819 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1820 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1822 /* We got a full sequence, so spill them all. */
1823 if (k == chain->group_size[class])
1825 register enum reg_class *p;
1826 for (k = 0; k < chain->group_size[class]; k++)
1829 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1830 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1831 if (potential_reload_regs[idx] == j + k)
1833 new_spill_reg (chain, idx, class, 0, dumpfile);
1836 /* We have found one that will complete a group,
1837 so count off one group as provided. */
1838 chain->need.groups[class]--;
1839 p = reg_class_superclasses[class];
1840 while (*p != LIM_REG_CLASSES)
1842 if (chain->group_size [(int) *p]
1843 <= chain->group_size [class])
1844 chain->need.groups[(int) *p]--;
1851 /* There are no groups left. */
1852 spill_failure (chain->insn);
1856 /* If pseudo REG conflicts with one of our reload registers, mark it as
1859 maybe_mark_pseudo_spilled (reg)
1863 int r = reg_renumber[reg];
1868 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1869 for (i = 0; i < n_spills; i++)
1870 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1872 SET_REGNO_REG_SET (spilled_pseudos, reg);
1877 /* Find more reload regs to satisfy the remaining need of an insn, which
1879 Do it by ascending class number, since otherwise a reg
1880 might be spilled for a big class and might fail to count
1881 for a smaller class even though it belongs to that class.
1883 Count spilled regs in `spills', and add entries to
1884 `spill_regs' and `spill_reg_order'.
1886 ??? Note there is a problem here.
1887 When there is a need for a group in a high-numbered class,
1888 and also need for non-group regs that come from a lower class,
1889 the non-group regs are chosen first. If there aren't many regs,
1890 they might leave no room for a group.
1892 This was happening on the 386. To fix it, we added the code
1893 that calls possible_group_p, so that the lower class won't
1894 break up the last possible group.
1896 Really fixing the problem would require changes above
1897 in counting the regs already spilled, and in choose_reload_regs.
1898 It might be hard to avoid introducing bugs there. */
1901 find_reload_regs (chain, dumpfile)
1902 struct insn_chain *chain;
1906 short *group_needs = chain->need.groups;
1907 short *simple_needs = chain->need.regs[0];
1908 short *nongroup_needs = chain->need.regs[1];
1911 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1913 /* Compute the order of preference for hard registers to spill.
1914 Store them by decreasing preference in potential_reload_regs. */
1916 order_regs_for_reload (chain);
1918 /* So far, no hard regs have been spilled. */
1920 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1921 spill_reg_order[i] = -1;
1923 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1924 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1925 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1927 for (class = 0; class < N_REG_CLASSES; class++)
1929 /* First get the groups of registers.
1930 If we got single registers first, we might fragment
1932 while (group_needs[class] > 0)
1934 /* If any single spilled regs happen to form groups,
1935 count them now. Maybe we don't really need
1936 to spill another group. */
1937 count_possible_groups (chain, class);
1939 if (group_needs[class] <= 0)
1942 /* Groups of size 2, the only groups used on most machines,
1943 are treated specially. */
1944 if (chain->group_size[class] == 2)
1945 find_tworeg_group (chain, class, dumpfile);
1947 find_group (chain, class, dumpfile);
1952 /* Now similarly satisfy all need for single registers. */
1954 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1956 /* If we spilled enough regs, but they weren't counted
1957 against the non-group need, see if we can count them now.
1958 If so, we can avoid some actual spilling. */
1959 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1960 for (i = 0; i < n_spills; i++)
1962 int regno = spill_regs[i];
1963 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1964 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1965 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1966 && nongroup_needs[class] > 0)
1968 register enum reg_class *p;
1970 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1971 nongroup_needs[class]--;
1972 p = reg_class_superclasses[class];
1973 while (*p != LIM_REG_CLASSES)
1974 nongroup_needs[(int) *p++]--;
1978 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1981 /* Consider the potential reload regs that aren't
1982 yet in use as reload regs, in order of preference.
1983 Find the most preferred one that's in this class. */
1985 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1987 int regno = potential_reload_regs[i];
1989 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1990 /* If this reg will not be available for groups,
1991 pick one that does not foreclose possible groups.
1992 This is a kludge, and not very general,
1993 but it should be sufficient to make the 386 work,
1994 and the problem should not occur on machines with
1996 && (nongroup_needs[class] == 0
1997 || possible_group_p (chain, regno)))
2001 /* If we couldn't get a register, try to get one even if we
2002 might foreclose possible groups. This may cause problems
2003 later, but that's better than aborting now, since it is
2004 possible that we will, in fact, be able to form the needed
2005 group even with this allocation. */
2007 if (i >= FIRST_PSEUDO_REGISTER
2008 && asm_noperands (chain->insn) < 0)
2009 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2010 if (potential_reload_regs[i] >= 0
2011 && TEST_HARD_REG_BIT (reg_class_contents[class],
2012 potential_reload_regs[i]))
2015 /* I should be the index in potential_reload_regs
2016 of the new reload reg we have found. */
2018 new_spill_reg (chain, i, class, 1, dumpfile);
2024 /* We know which hard regs to use, now mark the pseudos that live in them
2025 as needing to be kicked out. */
2026 EXECUTE_IF_SET_IN_REG_SET
2027 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
2029 maybe_mark_pseudo_spilled (i);
2031 EXECUTE_IF_SET_IN_REG_SET
2032 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
2034 maybe_mark_pseudo_spilled (i);
2037 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
2041 dump_needs (chain, dumpfile)
2042 struct insn_chain *chain;
2045 static char *reg_class_names[] = REG_CLASS_NAMES;
2047 struct needs *n = &chain->need;
2049 for (i = 0; i < N_REG_CLASSES; i++)
2051 if (n->regs[i][0] > 0)
2053 ";; Need %d reg%s of class %s.\n",
2054 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2055 reg_class_names[i]);
2056 if (n->regs[i][1] > 0)
2058 ";; Need %d nongroup reg%s of class %s.\n",
2059 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2060 reg_class_names[i]);
2061 if (n->groups[i] > 0)
2063 ";; Need %d group%s (%smode) of class %s.\n",
2064 n->groups[i], n->groups[i] == 1 ? "" : "s",
2065 mode_name[(int) chain->group_mode[i]],
2066 reg_class_names[i]);
2070 /* Delete all insns that were inserted by emit_caller_save_insns during
2073 delete_caller_save_insns ()
2075 struct insn_chain *c = reload_insn_chain;
2079 while (c != 0 && c->is_caller_save_insn)
2081 struct insn_chain *next = c->next;
2084 if (insn == BLOCK_HEAD (c->block))
2085 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2086 if (insn == BLOCK_END (c->block))
2087 BLOCK_END (c->block) = PREV_INSN (insn);
2088 if (c == reload_insn_chain)
2089 reload_insn_chain = next;
2091 if (NEXT_INSN (insn) != 0)
2092 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2093 if (PREV_INSN (insn) != 0)
2094 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2097 next->prev = c->prev;
2099 c->prev->next = next;
2100 c->next = unused_insn_chains;
2101 unused_insn_chains = c;
2109 /* Nonzero if, after spilling reg REGNO for non-groups,
2110 it will still be possible to find a group if we still need one. */
2113 possible_group_p (chain, regno)
2114 struct insn_chain *chain;
2118 int class = (int) NO_REGS;
2120 for (i = 0; i < (int) N_REG_CLASSES; i++)
2121 if (chain->need.groups[i] > 0)
2127 if (class == (int) NO_REGS)
2130 /* Consider each pair of consecutive registers. */
2131 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2133 /* Ignore pairs that include reg REGNO. */
2134 if (i == regno || i + 1 == regno)
2137 /* Ignore pairs that are outside the class that needs the group.
2138 ??? Here we fail to handle the case where two different classes
2139 independently need groups. But this never happens with our
2140 current machine descriptions. */
2141 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2142 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2145 /* A pair of consecutive regs we can still spill does the trick. */
2146 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2147 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2148 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2151 /* A pair of one already spilled and one we can spill does it
2152 provided the one already spilled is not otherwise reserved. */
2153 if (spill_reg_order[i] < 0
2154 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2155 && spill_reg_order[i + 1] >= 0
2156 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2157 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2159 if (spill_reg_order[i + 1] < 0
2160 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2161 && spill_reg_order[i] >= 0
2162 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2163 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2170 /* Count any groups of CLASS that can be formed from the registers recently
2174 count_possible_groups (chain, class)
2175 struct insn_chain *chain;
2181 /* Now find all consecutive groups of spilled registers
2182 and mark each group off against the need for such groups.
2183 But don't count them against ordinary need, yet. */
2185 if (chain->group_size[class] == 0)
2188 CLEAR_HARD_REG_SET (new);
2190 /* Make a mask of all the regs that are spill regs in class I. */
2191 for (i = 0; i < n_spills; i++)
2193 int regno = spill_regs[i];
2195 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2196 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2197 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2198 SET_HARD_REG_BIT (new, regno);
2201 /* Find each consecutive group of them. */
2202 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2203 if (TEST_HARD_REG_BIT (new, i)
2204 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2205 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2207 for (j = 1; j < chain->group_size[class]; j++)
2208 if (! TEST_HARD_REG_BIT (new, i + j))
2211 if (j == chain->group_size[class])
2213 /* We found a group. Mark it off against this class's need for
2214 groups, and against each superclass too. */
2215 register enum reg_class *p;
2217 chain->need.groups[class]--;
2218 p = reg_class_superclasses[class];
2219 while (*p != LIM_REG_CLASSES)
2221 if (chain->group_size [(int) *p] <= chain->group_size [class])
2222 chain->need.groups[(int) *p]--;
2226 /* Don't count these registers again. */
2227 for (j = 0; j < chain->group_size[class]; j++)
2228 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2231 /* Skip to the last reg in this group. When i is incremented above,
2232 it will then point to the first reg of the next possible group. */
2237 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2238 another mode that needs to be reloaded for the same register class CLASS.
2239 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2240 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2242 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2243 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2244 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2245 causes unnecessary failures on machines requiring alignment of register
2246 groups when the two modes are different sizes, because the larger mode has
2247 more strict alignment rules than the smaller mode. */
2250 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2251 enum machine_mode allocate_mode, other_mode;
2252 enum reg_class class;
2255 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2257 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2258 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2259 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2265 /* Handle the failure to find a register to spill.
2266 INSN should be one of the insns which needed this particular spill reg. */
2269 spill_failure (insn)
2272 if (asm_noperands (PATTERN (insn)) >= 0)
2273 error_for_asm (insn, "`asm' needs too many reloads");
2275 fatal_insn ("Unable to find a register to spill.", insn);
2278 /* Add a new register to the tables of available spill-registers.
2279 CHAIN is the insn for which the register will be used; we decrease the
2281 I is the index of this register in potential_reload_regs.
2282 CLASS is the regclass whose need is being satisfied.
2283 NONGROUP is 0 if this register is part of a group.
2284 DUMPFILE is the same as the one that `reload' got. */
2287 new_spill_reg (chain, i, class, nongroup, dumpfile)
2288 struct insn_chain *chain;
2294 register enum reg_class *p;
2295 int regno = potential_reload_regs[i];
2297 if (i >= FIRST_PSEUDO_REGISTER)
2299 spill_failure (chain->insn);
2304 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2306 static char *reg_class_names[] = REG_CLASS_NAMES;
2308 if (asm_noperands (PATTERN (chain->insn)) < 0)
2310 /* The error message is still correct - we know only that it wasn't
2311 an asm statement that caused the problem, but one of the global
2312 registers declared by the users might have screwed us. */
2313 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2314 regno, reg_names[regno], reg_class_names[class]);
2315 error ("This may be due to a compiler bug or to impossible asm");
2316 error ("statements or clauses.");
2317 fatal_insn ("This is the instruction:", chain->insn);
2319 error_for_asm (chain->insn, "Invalid `asm' statement:");
2320 error_for_asm (chain->insn,
2321 "fixed or forbidden register %d (%s) was spilled for class %s.",
2322 regno, reg_names[regno], reg_class_names[class]);
2327 /* Make reg REGNO an additional reload reg. */
2329 potential_reload_regs[i] = -1;
2330 spill_regs[n_spills] = regno;
2331 spill_reg_order[regno] = n_spills;
2333 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2334 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2336 /* Clear off the needs we just satisfied. */
2338 chain->need.regs[0][class]--;
2339 p = reg_class_superclasses[class];
2340 while (*p != LIM_REG_CLASSES)
2341 chain->need.regs[0][(int) *p++]--;
2343 if (nongroup && chain->need.regs[1][class] > 0)
2345 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2346 chain->need.regs[1][class]--;
2347 p = reg_class_superclasses[class];
2348 while (*p != LIM_REG_CLASSES)
2349 chain->need.regs[1][(int) *p++]--;
2355 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2356 data that is dead in INSN. */
2359 delete_dead_insn (insn)
2362 rtx prev = prev_real_insn (insn);
2365 /* If the previous insn sets a register that dies in our insn, delete it
2367 if (prev && GET_CODE (PATTERN (prev)) == SET
2368 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2369 && reg_mentioned_p (prev_dest, PATTERN (insn))
2370 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2371 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2372 delete_dead_insn (prev);
2374 PUT_CODE (insn, NOTE);
2375 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2376 NOTE_SOURCE_FILE (insn) = 0;
2379 /* Modify the home of pseudo-reg I.
2380 The new home is present in reg_renumber[I].
2382 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2383 or it may be -1, meaning there is none or it is not relevant.
2384 This is used so that all pseudos spilled from a given hard reg
2385 can share one stack slot. */
2388 alter_reg (i, from_reg)
2392 /* When outputting an inline function, this can happen
2393 for a reg that isn't actually used. */
2394 if (regno_reg_rtx[i] == 0)
2397 /* If the reg got changed to a MEM at rtl-generation time,
2399 if (GET_CODE (regno_reg_rtx[i]) != REG)
2402 /* Modify the reg-rtx to contain the new hard reg
2403 number or else to contain its pseudo reg number. */
2404 REGNO (regno_reg_rtx[i])
2405 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2407 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2408 allocate a stack slot for it. */
2410 if (reg_renumber[i] < 0
2411 && REG_N_REFS (i) > 0
2412 && reg_equiv_constant[i] == 0
2413 && reg_equiv_memory_loc[i] == 0)
2416 int inherent_size = PSEUDO_REGNO_BYTES (i);
2417 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2420 /* Each pseudo reg has an inherent size which comes from its own mode,
2421 and a total size which provides room for paradoxical subregs
2422 which refer to the pseudo reg in wider modes.
2424 We can use a slot already allocated if it provides both
2425 enough inherent space and enough total space.
2426 Otherwise, we allocate a new slot, making sure that it has no less
2427 inherent space, and no less total space, then the previous slot. */
2430 /* No known place to spill from => no slot to reuse. */
2431 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2432 inherent_size == total_size ? 0 : -1);
2433 if (BYTES_BIG_ENDIAN)
2434 /* Cancel the big-endian correction done in assign_stack_local.
2435 Get the address of the beginning of the slot.
2436 This is so we can do a big-endian correction unconditionally
2438 adjust = inherent_size - total_size;
2440 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2442 /* Reuse a stack slot if possible. */
2443 else if (spill_stack_slot[from_reg] != 0
2444 && spill_stack_slot_width[from_reg] >= total_size
2445 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2447 x = spill_stack_slot[from_reg];
2448 /* Allocate a bigger slot. */
2451 /* Compute maximum size needed, both for inherent size
2452 and for total size. */
2453 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2455 if (spill_stack_slot[from_reg])
2457 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2459 mode = GET_MODE (spill_stack_slot[from_reg]);
2460 if (spill_stack_slot_width[from_reg] > total_size)
2461 total_size = spill_stack_slot_width[from_reg];
2463 /* Make a slot with that size. */
2464 x = assign_stack_local (mode, total_size,
2465 inherent_size == total_size ? 0 : -1);
2467 if (BYTES_BIG_ENDIAN)
2469 /* Cancel the big-endian correction done in assign_stack_local.
2470 Get the address of the beginning of the slot.
2471 This is so we can do a big-endian correction unconditionally
2473 adjust = GET_MODE_SIZE (mode) - total_size;
2475 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2478 plus_constant (XEXP (x, 0), adjust));
2480 spill_stack_slot[from_reg] = stack_slot;
2481 spill_stack_slot_width[from_reg] = total_size;
2484 /* On a big endian machine, the "address" of the slot
2485 is the address of the low part that fits its inherent mode. */
2486 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2487 adjust += (total_size - inherent_size);
2489 /* If we have any adjustment to make, or if the stack slot is the
2490 wrong mode, make a new stack slot. */
2491 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2493 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2494 plus_constant (XEXP (x, 0), adjust));
2496 /* If this was shared among registers, must ensure we never
2497 set it readonly since that can cause scheduling
2498 problems. Note we would only have in this adjustment
2499 case in any event, since the code above doesn't set it. */
2502 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2505 /* Save the stack slot for later. */
2506 reg_equiv_memory_loc[i] = x;
2510 /* Mark the slots in regs_ever_live for the hard regs
2511 used by pseudo-reg number REGNO. */
2514 mark_home_live (regno)
2517 register int i, lim;
2518 i = reg_renumber[regno];
2521 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2523 regs_ever_live[i++] = 1;
2526 /* This function handles the tracking of elimination offsets around branches.
2528 X is a piece of RTL being scanned.
2530 INSN is the insn that it came from, if any.
2532 INITIAL_P is non-zero if we are to set the offset to be the initial
2533 offset and zero if we are setting the offset of the label to be the
2537 set_label_offsets (x, insn, initial_p)
2542 enum rtx_code code = GET_CODE (x);
2545 struct elim_table *p;
2550 if (LABEL_REF_NONLOCAL_P (x))
2555 /* ... fall through ... */
2558 /* If we know nothing about this label, set the desired offsets. Note
2559 that this sets the offset at a label to be the offset before a label
2560 if we don't know anything about the label. This is not correct for
2561 the label after a BARRIER, but is the best guess we can make. If
2562 we guessed wrong, we will suppress an elimination that might have
2563 been possible had we been able to guess correctly. */
2565 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2567 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2568 offsets_at[CODE_LABEL_NUMBER (x)][i]
2569 = (initial_p ? reg_eliminate[i].initial_offset
2570 : reg_eliminate[i].offset);
2571 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2574 /* Otherwise, if this is the definition of a label and it is
2575 preceded by a BARRIER, set our offsets to the known offset of
2579 && (tem = prev_nonnote_insn (insn)) != 0
2580 && GET_CODE (tem) == BARRIER)
2581 set_offsets_for_label (insn);
2583 /* If neither of the above cases is true, compare each offset
2584 with those previously recorded and suppress any eliminations
2585 where the offsets disagree. */
2587 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2588 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2589 != (initial_p ? reg_eliminate[i].initial_offset
2590 : reg_eliminate[i].offset))
2591 reg_eliminate[i].can_eliminate = 0;
2596 set_label_offsets (PATTERN (insn), insn, initial_p);
2598 /* ... fall through ... */
2602 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2603 and hence must have all eliminations at their initial offsets. */
2604 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2605 if (REG_NOTE_KIND (tem) == REG_LABEL)
2606 set_label_offsets (XEXP (tem, 0), insn, 1);
2611 /* Each of the labels in the address vector must be at their initial
2612 offsets. We want the first field for ADDR_VEC and the second
2613 field for ADDR_DIFF_VEC. */
2615 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2616 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2621 /* We only care about setting PC. If the source is not RETURN,
2622 IF_THEN_ELSE, or a label, disable any eliminations not at
2623 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2624 isn't one of those possibilities. For branches to a label,
2625 call ourselves recursively.
2627 Note that this can disable elimination unnecessarily when we have
2628 a non-local goto since it will look like a non-constant jump to
2629 someplace in the current function. This isn't a significant
2630 problem since such jumps will normally be when all elimination
2631 pairs are back to their initial offsets. */
2633 if (SET_DEST (x) != pc_rtx)
2636 switch (GET_CODE (SET_SRC (x)))
2643 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2647 tem = XEXP (SET_SRC (x), 1);
2648 if (GET_CODE (tem) == LABEL_REF)
2649 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2650 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2653 tem = XEXP (SET_SRC (x), 2);
2654 if (GET_CODE (tem) == LABEL_REF)
2655 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2656 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2664 /* If we reach here, all eliminations must be at their initial
2665 offset because we are doing a jump to a variable address. */
2666 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2667 if (p->offset != p->initial_offset)
2668 p->can_eliminate = 0;
2676 /* Used for communication between the next two function to properly share
2677 the vector for an ASM_OPERANDS. */
2679 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2681 /* Scan X and replace any eliminable registers (such as fp) with a
2682 replacement (such as sp), plus an offset.
2684 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2685 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2686 MEM, we are allowed to replace a sum of a register and the constant zero
2687 with the register, which we cannot do outside a MEM. In addition, we need
2688 to record the fact that a register is referenced outside a MEM.
2690 If INSN is an insn, it is the insn containing X. If we replace a REG
2691 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2692 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2693 the REG is being modified.
2695 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2696 That's used when we eliminate in expressions stored in notes.
2697 This means, do not set ref_outside_mem even if the reference
2700 If we see a modification to a register we know about, take the
2701 appropriate action (see case SET, below).
2703 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2704 replacements done assuming all offsets are at their initial values. If
2705 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2706 encounter, return the actual location so that find_reloads will do
2707 the proper thing. */
2710 eliminate_regs (x, mem_mode, insn)
2712 enum machine_mode mem_mode;
2715 enum rtx_code code = GET_CODE (x);
2716 struct elim_table *ep;
2723 if (! current_function_decl)
2742 /* This is only for the benefit of the debugging backends, which call
2743 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2744 removed after CSE. */
2745 new = eliminate_regs (XEXP (x, 0), 0, insn);
2746 if (GET_CODE (new) == MEM)
2747 return XEXP (new, 0);
2753 /* First handle the case where we encounter a bare register that
2754 is eliminable. Replace it with a PLUS. */
2755 if (regno < FIRST_PSEUDO_REGISTER)
2757 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2759 if (ep->from_rtx == x && ep->can_eliminate)
2762 /* Refs inside notes don't count for this purpose. */
2763 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2764 || GET_CODE (insn) == INSN_LIST)))
2765 ep->ref_outside_mem = 1;
2766 return plus_constant (ep->to_rtx, ep->previous_offset);
2770 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2771 && reg_equiv_constant[regno]
2772 && ! CONSTANT_P (reg_equiv_constant[regno]))
2773 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2778 /* If this is the sum of an eliminable register and a constant, rework
2780 if (GET_CODE (XEXP (x, 0)) == REG
2781 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2782 && CONSTANT_P (XEXP (x, 1)))
2784 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2786 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2789 /* Refs inside notes don't count for this purpose. */
2790 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2791 || GET_CODE (insn) == INSN_LIST)))
2792 ep->ref_outside_mem = 1;
2794 /* The only time we want to replace a PLUS with a REG (this
2795 occurs when the constant operand of the PLUS is the negative
2796 of the offset) is when we are inside a MEM. We won't want
2797 to do so at other times because that would change the
2798 structure of the insn in a way that reload can't handle.
2799 We special-case the commonest situation in
2800 eliminate_regs_in_insn, so just replace a PLUS with a
2801 PLUS here, unless inside a MEM. */
2802 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2803 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2806 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2807 plus_constant (XEXP (x, 1),
2808 ep->previous_offset));
2811 /* If the register is not eliminable, we are done since the other
2812 operand is a constant. */
2816 /* If this is part of an address, we want to bring any constant to the
2817 outermost PLUS. We will do this by doing register replacement in
2818 our operands and seeing if a constant shows up in one of them.
2820 We assume here this is part of an address (or a "load address" insn)
2821 since an eliminable register is not likely to appear in any other
2824 If we have (plus (eliminable) (reg)), we want to produce
2825 (plus (plus (replacement) (reg) (const))). If this was part of a
2826 normal add insn, (plus (replacement) (reg)) will be pushed as a
2827 reload. This is the desired action. */
2830 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2831 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2833 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2835 /* If one side is a PLUS and the other side is a pseudo that
2836 didn't get a hard register but has a reg_equiv_constant,
2837 we must replace the constant here since it may no longer
2838 be in the position of any operand. */
2839 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2840 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2841 && reg_renumber[REGNO (new1)] < 0
2842 && reg_equiv_constant != 0
2843 && reg_equiv_constant[REGNO (new1)] != 0)
2844 new1 = reg_equiv_constant[REGNO (new1)];
2845 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2846 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2847 && reg_renumber[REGNO (new0)] < 0
2848 && reg_equiv_constant[REGNO (new0)] != 0)
2849 new0 = reg_equiv_constant[REGNO (new0)];
2851 new = form_sum (new0, new1);
2853 /* As above, if we are not inside a MEM we do not want to
2854 turn a PLUS into something else. We might try to do so here
2855 for an addition of 0 if we aren't optimizing. */
2856 if (! mem_mode && GET_CODE (new) != PLUS)
2857 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2865 /* If this is the product of an eliminable register and a
2866 constant, apply the distribute law and move the constant out
2867 so that we have (plus (mult ..) ..). This is needed in order
2868 to keep load-address insns valid. This case is pathological.
2869 We ignore the possibility of overflow here. */
2870 if (GET_CODE (XEXP (x, 0)) == REG
2871 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2872 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2873 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2875 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2878 /* Refs inside notes don't count for this purpose. */
2879 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2880 || GET_CODE (insn) == INSN_LIST)))
2881 ep->ref_outside_mem = 1;
2884 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2885 ep->previous_offset * INTVAL (XEXP (x, 1)));
2888 /* ... fall through ... */
2893 case DIV: case UDIV:
2894 case MOD: case UMOD:
2895 case AND: case IOR: case XOR:
2896 case ROTATERT: case ROTATE:
2897 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2899 case GE: case GT: case GEU: case GTU:
2900 case LE: case LT: case LEU: case LTU:
2902 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2904 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2906 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2907 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2912 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2915 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2916 if (new != XEXP (x, 0))
2918 /* If this is a REG_DEAD note, it is not valid anymore.
2919 Using the eliminated version could result in creating a
2920 REG_DEAD note for the stack or frame pointer. */
2921 if (GET_MODE (x) == REG_DEAD)
2923 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2926 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2930 /* ... fall through ... */
2933 /* Now do eliminations in the rest of the chain. If this was
2934 an EXPR_LIST, this might result in allocating more memory than is
2935 strictly needed, but it simplifies the code. */
2938 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2939 if (new != XEXP (x, 1))
2940 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2948 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2949 if (ep->to_rtx == XEXP (x, 0))
2951 int size = GET_MODE_SIZE (mem_mode);
2953 /* If more bytes than MEM_MODE are pushed, account for them. */
2954 #ifdef PUSH_ROUNDING
2955 if (ep->to_rtx == stack_pointer_rtx)
2956 size = PUSH_ROUNDING (size);
2958 if (code == PRE_DEC || code == POST_DEC)
2964 /* Fall through to generic unary operation case. */
2965 case STRICT_LOW_PART:
2967 case SIGN_EXTEND: case ZERO_EXTEND:
2968 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2969 case FLOAT: case FIX:
2970 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2974 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2975 if (new != XEXP (x, 0))
2976 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2980 /* Similar to above processing, but preserve SUBREG_WORD.
2981 Convert (subreg (mem)) to (mem) if not paradoxical.
2982 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2983 pseudo didn't get a hard reg, we must replace this with the
2984 eliminated version of the memory location because push_reloads
2985 may do the replacement in certain circumstances. */
2986 if (GET_CODE (SUBREG_REG (x)) == REG
2987 && (GET_MODE_SIZE (GET_MODE (x))
2988 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2989 && reg_equiv_memory_loc != 0
2990 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2993 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2996 /* If we didn't change anything, we must retain the pseudo. */
2997 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2998 new = SUBREG_REG (x);
3001 /* In this case, we must show that the pseudo is used in this
3002 insn so that delete_output_reload will do the right thing. */
3003 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3004 && GET_CODE (insn) != INSN_LIST)
3005 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3008 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3010 /* Ensure NEW isn't shared in case we have to reload it. */
3011 new = copy_rtx (new);
3014 new = SUBREG_REG (x);
3018 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3020 if (new != XEXP (x, 0))
3022 int x_size = GET_MODE_SIZE (GET_MODE (x));
3023 int new_size = GET_MODE_SIZE (GET_MODE (new));
3025 if (GET_CODE (new) == MEM
3026 && ((x_size < new_size
3027 #ifdef WORD_REGISTER_OPERATIONS
3028 /* On these machines, combine can create rtl of the form
3029 (set (subreg:m1 (reg:m2 R) 0) ...)
3030 where m1 < m2, and expects something interesting to
3031 happen to the entire word. Moreover, it will use the
3032 (reg:m2 R) later, expecting all bits to be preserved.
3033 So if the number of words is the same, preserve the
3034 subreg so that push_reloads can see it. */
3035 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3038 || (x_size == new_size))
3041 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3042 enum machine_mode mode = GET_MODE (x);
3044 if (BYTES_BIG_ENDIAN)
3045 offset += (MIN (UNITS_PER_WORD,
3046 GET_MODE_SIZE (GET_MODE (new)))
3047 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3049 PUT_MODE (new, mode);
3050 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3054 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3060 /* If using a register that is the source of an eliminate we still
3061 think can be performed, note it cannot be performed since we don't
3062 know how this register is used. */
3063 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3064 if (ep->from_rtx == XEXP (x, 0))
3065 ep->can_eliminate = 0;
3067 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3068 if (new != XEXP (x, 0))
3069 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3073 /* If clobbering a register that is the replacement register for an
3074 elimination we still think can be performed, note that it cannot
3075 be performed. Otherwise, we need not be concerned about it. */
3076 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3077 if (ep->to_rtx == XEXP (x, 0))
3078 ep->can_eliminate = 0;
3080 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3081 if (new != XEXP (x, 0))
3082 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3088 /* Properly handle sharing input and constraint vectors. */
3089 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3091 /* When we come to a new vector not seen before,
3092 scan all its elements; keep the old vector if none
3093 of them changes; otherwise, make a copy. */
3094 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3095 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3096 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3097 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3100 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3101 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3104 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3105 new_asm_operands_vec = old_asm_operands_vec;
3107 new_asm_operands_vec
3108 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3111 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3112 if (new_asm_operands_vec == old_asm_operands_vec)
3115 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3116 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3117 ASM_OPERANDS_OUTPUT_IDX (x),
3118 new_asm_operands_vec,
3119 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3120 ASM_OPERANDS_SOURCE_FILE (x),
3121 ASM_OPERANDS_SOURCE_LINE (x));
3122 new->volatil = x->volatil;
3127 /* Check for setting a register that we know about. */
3128 if (GET_CODE (SET_DEST (x)) == REG)
3130 /* See if this is setting the replacement register for an
3133 If DEST is the hard frame pointer, we do nothing because we
3134 assume that all assignments to the frame pointer are for
3135 non-local gotos and are being done at a time when they are valid
3136 and do not disturb anything else. Some machines want to
3137 eliminate a fake argument pointer (or even a fake frame pointer)
3138 with either the real frame or the stack pointer. Assignments to
3139 the hard frame pointer must not prevent this elimination. */
3141 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3143 if (ep->to_rtx == SET_DEST (x)
3144 && SET_DEST (x) != hard_frame_pointer_rtx)
3146 /* If it is being incremented, adjust the offset. Otherwise,
3147 this elimination can't be done. */
3148 rtx src = SET_SRC (x);
3150 if (GET_CODE (src) == PLUS
3151 && XEXP (src, 0) == SET_DEST (x)
3152 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3153 ep->offset -= INTVAL (XEXP (src, 1));
3155 ep->can_eliminate = 0;
3158 /* Now check to see we are assigning to a register that can be
3159 eliminated. If so, it must be as part of a PARALLEL, since we
3160 will not have been called if this is a single SET. So indicate
3161 that we can no longer eliminate this reg. */
3162 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3164 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3165 ep->can_eliminate = 0;
3168 /* Now avoid the loop below in this common case. */
3170 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3171 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3173 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3174 write a CLOBBER insn. */
3175 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3176 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3177 && GET_CODE (insn) != INSN_LIST)
3178 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3180 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3181 return gen_rtx_SET (VOIDmode, new0, new1);
3187 /* This is only for the benefit of the debugging backends, which call
3188 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3189 removed after CSE. */
3190 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3191 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3193 /* Our only special processing is to pass the mode of the MEM to our
3194 recursive call and copy the flags. While we are here, handle this
3195 case more efficiently. */
3196 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3197 if (new != XEXP (x, 0))
3199 new = gen_rtx_MEM (GET_MODE (x), new);
3200 new->volatil = x->volatil;
3201 new->unchanging = x->unchanging;
3202 new->in_struct = x->in_struct;
3212 /* Process each of our operands recursively. If any have changed, make a
3214 fmt = GET_RTX_FORMAT (code);
3215 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3219 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3220 if (new != XEXP (x, i) && ! copied)
3222 rtx new_x = rtx_alloc (code);
3223 bcopy ((char *) x, (char *) new_x,
3224 (sizeof (*new_x) - sizeof (new_x->fld)
3225 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3231 else if (*fmt == 'E')
3234 for (j = 0; j < XVECLEN (x, i); j++)
3236 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3237 if (new != XVECEXP (x, i, j) && ! copied_vec)
3239 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3243 rtx new_x = rtx_alloc (code);
3244 bcopy ((char *) x, (char *) new_x,
3245 (sizeof (*new_x) - sizeof (new_x->fld)
3246 + (sizeof (new_x->fld[0])
3247 * GET_RTX_LENGTH (code))));
3251 XVEC (x, i) = new_v;
3254 XVECEXP (x, i, j) = new;
3262 /* Scan INSN and eliminate all eliminable registers in it.
3264 If REPLACE is nonzero, do the replacement destructively. Also
3265 delete the insn as dead it if it is setting an eliminable register.
3267 If REPLACE is zero, do all our allocations in reload_obstack.
3269 If no eliminations were done and this insn doesn't require any elimination
3270 processing (these are not identical conditions: it might be updating sp,
3271 but not referencing fp; this needs to be seen during reload_as_needed so
3272 that the offset between fp and sp can be taken into consideration), zero
3273 is returned. Otherwise, 1 is returned. */
3276 eliminate_regs_in_insn (insn, replace)
3280 rtx old_body = PATTERN (insn);
3281 rtx old_set = single_set (insn);
3284 struct elim_table *ep;
3287 push_obstacks (&reload_obstack, &reload_obstack);
3289 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3290 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3292 /* Check for setting an eliminable register. */
3293 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3294 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3296 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3297 /* If this is setting the frame pointer register to the
3298 hardware frame pointer register and this is an elimination
3299 that will be done (tested above), this insn is really
3300 adjusting the frame pointer downward to compensate for
3301 the adjustment done before a nonlocal goto. */
3302 if (ep->from == FRAME_POINTER_REGNUM
3303 && ep->to == HARD_FRAME_POINTER_REGNUM)
3305 rtx src = SET_SRC (old_set);
3306 int offset = 0, ok = 0;
3307 rtx prev_insn, prev_set;
3309 if (src == ep->to_rtx)
3311 else if (GET_CODE (src) == PLUS
3312 && GET_CODE (XEXP (src, 0)) == CONST_INT
3313 && XEXP (src, 1) == ep->to_rtx)
3314 offset = INTVAL (XEXP (src, 0)), ok = 1;
3315 else if (GET_CODE (src) == PLUS
3316 && GET_CODE (XEXP (src, 1)) == CONST_INT
3317 && XEXP (src, 0) == ep->to_rtx)
3318 offset = INTVAL (XEXP (src, 1)), ok = 1;
3319 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3320 && (prev_set = single_set (prev_insn)) != 0
3321 && rtx_equal_p (SET_DEST (prev_set), src))
3323 src = SET_SRC (prev_set);
3324 if (src == ep->to_rtx)
3326 else if (GET_CODE (src) == PLUS
3327 && GET_CODE (XEXP (src, 0)) == CONST_INT
3328 && XEXP (src, 1) == ep->to_rtx)
3329 offset = INTVAL (XEXP (src, 0)), ok = 1;
3330 else if (GET_CODE (src) == PLUS
3331 && GET_CODE (XEXP (src, 1)) == CONST_INT
3332 && XEXP (src, 0) == ep->to_rtx)
3333 offset = INTVAL (XEXP (src, 1)), ok = 1;
3341 = plus_constant (ep->to_rtx, offset - ep->offset);
3343 /* First see if this insn remains valid when we
3344 make the change. If not, keep the INSN_CODE
3345 the same and let reload fit it up. */
3346 validate_change (insn, &SET_SRC (old_set), src, 1);
3347 validate_change (insn, &SET_DEST (old_set),
3349 if (! apply_change_group ())
3351 SET_SRC (old_set) = src;
3352 SET_DEST (old_set) = ep->to_rtx;
3362 /* In this case this insn isn't serving a useful purpose. We
3363 will delete it in reload_as_needed once we know that this
3364 elimination is, in fact, being done.
3366 If REPLACE isn't set, we can't delete this insn, but needn't
3367 process it since it won't be used unless something changes. */
3369 delete_dead_insn (insn);
3374 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3375 in the insn is the negative of the offset in FROM. Substitute
3376 (set (reg) (reg to)) for the insn and change its code.
3378 We have to do this here, rather than in eliminate_regs, so that we can
3379 change the insn code. */
3381 if (GET_CODE (SET_SRC (old_set)) == PLUS
3382 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3383 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3384 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3386 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3387 && ep->can_eliminate)
3389 /* We must stop at the first elimination that will be used.
3390 If this one would replace the PLUS with a REG, do it
3391 now. Otherwise, quit the loop and let eliminate_regs
3392 do its normal replacement. */
3393 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3395 /* We assume here that we don't need a PARALLEL of
3396 any CLOBBERs for this assignment. There's not
3397 much we can do if we do need it. */
3398 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3401 INSN_CODE (insn) = -1;
3410 old_asm_operands_vec = 0;
3412 /* Replace the body of this insn with a substituted form. If we changed
3413 something, return non-zero.
3415 If we are replacing a body that was a (set X (plus Y Z)), try to
3416 re-recognize the insn. We do this in case we had a simple addition
3417 but now can do this as a load-address. This saves an insn in this
3420 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3421 if (new_body != old_body)
3423 /* If we aren't replacing things permanently and we changed something,
3424 make another copy to ensure that all the RTL is new. Otherwise
3425 things can go wrong if find_reload swaps commutative operands
3426 and one is inside RTL that has been copied while the other is not. */
3428 /* Don't copy an asm_operands because (1) there's no need and (2)
3429 copy_rtx can't do it properly when there are multiple outputs. */
3430 if (! replace && asm_noperands (old_body) < 0)
3431 new_body = copy_rtx (new_body);
3433 /* If we had a move insn but now we don't, rerecognize it. This will
3434 cause spurious re-recognition if the old move had a PARALLEL since
3435 the new one still will, but we can't call single_set without
3436 having put NEW_BODY into the insn and the re-recognition won't
3437 hurt in this rare case. */
3439 && ((GET_CODE (SET_SRC (old_set)) == REG
3440 && (GET_CODE (new_body) != SET
3441 || GET_CODE (SET_SRC (new_body)) != REG))
3442 /* If this was a load from or store to memory, compare
3443 the MEM in recog_operand to the one in the insn. If they
3444 are not equal, then rerecognize the insn. */
3446 && ((GET_CODE (SET_SRC (old_set)) == MEM
3447 && SET_SRC (old_set) != recog_operand[1])
3448 || (GET_CODE (SET_DEST (old_set)) == MEM
3449 && SET_DEST (old_set) != recog_operand[0])))
3450 /* If this was an add insn before, rerecognize. */
3451 || GET_CODE (SET_SRC (old_set)) == PLUS))
3453 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3454 /* If recognition fails, store the new body anyway.
3455 It's normal to have recognition failures here
3456 due to bizarre memory addresses; reloading will fix them. */
3457 PATTERN (insn) = new_body;
3460 PATTERN (insn) = new_body;
3465 /* Loop through all elimination pairs. See if any have changed.
3467 We also detect a cases where register elimination cannot be done,
3468 namely, if a register would be both changed and referenced outside a MEM
3469 in the resulting insn since such an insn is often undefined and, even if
3470 not, we cannot know what meaning will be given to it. Note that it is
3471 valid to have a register used in an address in an insn that changes it
3472 (presumably with a pre- or post-increment or decrement).
3474 If anything changes, return nonzero. */
3476 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3478 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3479 ep->can_eliminate = 0;
3481 ep->ref_outside_mem = 0;
3483 if (ep->previous_offset != ep->offset)
3488 /* If we changed something, perform elimination in REG_NOTES. This is
3489 needed even when REPLACE is zero because a REG_DEAD note might refer
3490 to a register that we eliminate and could cause a different number
3491 of spill registers to be needed in the final reload pass than in
3493 if (val && REG_NOTES (insn) != 0)
3494 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3502 /* Loop through all elimination pairs.
3503 Recalculate the number not at initial offset.
3505 Compute the maximum offset (minimum offset if the stack does not
3506 grow downward) for each elimination pair. */
3509 update_eliminable_offsets ()
3511 struct elim_table *ep;
3513 num_not_at_initial_offset = 0;
3514 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3516 ep->previous_offset = ep->offset;
3517 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3518 num_not_at_initial_offset++;
3522 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3523 replacement we currently believe is valid, mark it as not eliminable if X
3524 modifies DEST in any way other than by adding a constant integer to it.
3526 If DEST is the frame pointer, we do nothing because we assume that
3527 all assignments to the hard frame pointer are nonlocal gotos and are being
3528 done at a time when they are valid and do not disturb anything else.
3529 Some machines want to eliminate a fake argument pointer with either the
3530 frame or stack pointer. Assignments to the hard frame pointer must not
3531 prevent this elimination.
3533 Called via note_stores from reload before starting its passes to scan
3534 the insns of the function. */
3537 mark_not_eliminable (dest, x)
3541 register unsigned int i;
3543 /* A SUBREG of a hard register here is just changing its mode. We should
3544 not see a SUBREG of an eliminable hard register, but check just in
3546 if (GET_CODE (dest) == SUBREG)
3547 dest = SUBREG_REG (dest);
3549 if (dest == hard_frame_pointer_rtx)
3552 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3553 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3554 && (GET_CODE (x) != SET
3555 || GET_CODE (SET_SRC (x)) != PLUS
3556 || XEXP (SET_SRC (x), 0) != dest
3557 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3559 reg_eliminate[i].can_eliminate_previous
3560 = reg_eliminate[i].can_eliminate = 0;
3565 /* Verify that the initial elimination offsets did not change since the
3566 last call to set_initial_elim_offsets. This is used to catch cases
3567 where something illegal happened during reload_as_needed that could
3568 cause incorrect code to be generated if we did not check for it. */
3570 verify_initial_elim_offsets ()
3574 #ifdef ELIMINABLE_REGS
3575 struct elim_table *ep;
3577 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3579 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3580 if (t != ep->initial_offset)
3584 INITIAL_FRAME_POINTER_OFFSET (t);
3585 if (t != reg_eliminate[0].initial_offset)
3590 /* Reset all offsets on eliminable registers to their initial values. */
3592 set_initial_elim_offsets ()
3594 struct elim_table *ep = reg_eliminate;
3596 #ifdef ELIMINABLE_REGS
3597 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3599 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3600 ep->previous_offset = ep->offset = ep->initial_offset;
3603 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3604 ep->previous_offset = ep->offset = ep->initial_offset;
3607 num_not_at_initial_offset = 0;
3610 /* Initialize the known label offsets.
3611 Set a known offset for each forced label to be at the initial offset
3612 of each elimination. We do this because we assume that all
3613 computed jumps occur from a location where each elimination is
3614 at its initial offset.
3615 For all other labels, show that we don't know the offsets. */
3618 set_initial_label_offsets ()
3621 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3623 for (x = forced_labels; x; x = XEXP (x, 1))
3625 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3628 /* Set all elimination offsets to the known values for the code label given
3631 set_offsets_for_label (insn)
3635 int label_nr = CODE_LABEL_NUMBER (insn);
3636 struct elim_table *ep;
3638 num_not_at_initial_offset = 0;
3639 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3641 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3642 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3643 num_not_at_initial_offset++;
3647 /* See if anything that happened changes which eliminations are valid.
3648 For example, on the Sparc, whether or not the frame pointer can
3649 be eliminated can depend on what registers have been used. We need
3650 not check some conditions again (such as flag_omit_frame_pointer)
3651 since they can't have changed. */
3654 update_eliminables (pset)
3657 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3658 int previous_frame_pointer_needed = frame_pointer_needed;
3660 struct elim_table *ep;
3662 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3663 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3664 #ifdef ELIMINABLE_REGS
3665 || ! CAN_ELIMINATE (ep->from, ep->to)
3668 ep->can_eliminate = 0;
3670 /* Look for the case where we have discovered that we can't replace
3671 register A with register B and that means that we will now be
3672 trying to replace register A with register C. This means we can
3673 no longer replace register C with register B and we need to disable
3674 such an elimination, if it exists. This occurs often with A == ap,
3675 B == sp, and C == fp. */
3677 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3679 struct elim_table *op;
3680 register int new_to = -1;
3682 if (! ep->can_eliminate && ep->can_eliminate_previous)
3684 /* Find the current elimination for ep->from, if there is a
3686 for (op = reg_eliminate;
3687 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3688 if (op->from == ep->from && op->can_eliminate)
3694 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3696 for (op = reg_eliminate;
3697 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3698 if (op->from == new_to && op->to == ep->to)
3699 op->can_eliminate = 0;
3703 /* See if any registers that we thought we could eliminate the previous
3704 time are no longer eliminable. If so, something has changed and we
3705 must spill the register. Also, recompute the number of eliminable
3706 registers and see if the frame pointer is needed; it is if there is
3707 no elimination of the frame pointer that we can perform. */
3709 frame_pointer_needed = 1;
3710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3712 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3713 && ep->to != HARD_FRAME_POINTER_REGNUM)
3714 frame_pointer_needed = 0;
3716 if (! ep->can_eliminate && ep->can_eliminate_previous)
3718 ep->can_eliminate_previous = 0;
3719 SET_HARD_REG_BIT (*pset, ep->from);
3724 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3725 /* If we didn't need a frame pointer last time, but we do now, spill
3726 the hard frame pointer. */
3727 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3728 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3732 /* Initialize the table of registers to eliminate. */
3736 struct elim_table *ep;
3737 #ifdef ELIMINABLE_REGS
3738 struct elim_table_1 *ep1;
3743 reg_eliminate = (struct elim_table *)
3744 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3745 bzero ((PTR) reg_eliminate,
3746 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3749 /* Does this function require a frame pointer? */
3751 frame_pointer_needed = (! flag_omit_frame_pointer
3752 #ifdef EXIT_IGNORE_STACK
3753 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3754 and restore sp for alloca. So we can't eliminate
3755 the frame pointer in that case. At some point,
3756 we should improve this by emitting the
3757 sp-adjusting insns for this case. */
3758 || (current_function_calls_alloca
3759 && EXIT_IGNORE_STACK)
3761 || FRAME_POINTER_REQUIRED);
3765 #ifdef ELIMINABLE_REGS
3766 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3767 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3769 ep->from = ep1->from;
3771 ep->can_eliminate = ep->can_eliminate_previous
3772 = (CAN_ELIMINATE (ep->from, ep->to)
3773 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3776 reg_eliminate[0].from = reg_eliminate_1[0].from;
3777 reg_eliminate[0].to = reg_eliminate_1[0].to;
3778 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3779 = ! frame_pointer_needed;
3782 /* Count the number of eliminable registers and build the FROM and TO
3783 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3784 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3785 We depend on this. */
3786 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3788 num_eliminable += ep->can_eliminate;
3789 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3790 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3794 /* Kick all pseudos out of hard register REGNO.
3795 If DUMPFILE is nonzero, log actions taken on that file.
3797 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3798 because we found we can't eliminate some register. In the case, no pseudos
3799 are allowed to be in the register, even if they are only in a block that
3800 doesn't require spill registers, unlike the case when we are spilling this
3801 hard reg to produce another spill register.
3803 Return nonzero if any pseudos needed to be kicked out. */
3806 spill_hard_reg (regno, dumpfile, cant_eliminate)
3815 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3816 regs_ever_live[regno] = 1;
3819 /* Spill every pseudo reg that was allocated to this reg
3820 or to something that overlaps this reg. */
3822 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3823 if (reg_renumber[i] >= 0
3824 && reg_renumber[i] <= regno
3826 + HARD_REGNO_NREGS (reg_renumber[i],
3827 PSEUDO_REGNO_MODE (i))
3829 SET_REGNO_REG_SET (spilled_pseudos, i);
3832 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3833 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3835 ior_hard_reg_set (set1, set2)
3836 HARD_REG_SET *set1, *set2;
3838 IOR_HARD_REG_SET (*set1, *set2);
3841 /* After find_reload_regs has been run for all insn that need reloads,
3842 and/or spill_hard_regs was called, this function is used to actually
3843 spill pseudo registers and try to reallocate them. It also sets up the
3844 spill_regs array for use by choose_reload_regs. */
3847 finish_spills (global, dumpfile)
3851 struct insn_chain *chain;
3852 int something_changed = 0;
3855 /* Build the spill_regs array for the function. */
3856 /* If there are some registers still to eliminate and one of the spill regs
3857 wasn't ever used before, additional stack space may have to be
3858 allocated to store this register. Thus, we may have changed the offset
3859 between the stack and frame pointers, so mark that something has changed.
3861 One might think that we need only set VAL to 1 if this is a call-used
3862 register. However, the set of registers that must be saved by the
3863 prologue is not identical to the call-used set. For example, the
3864 register used by the call insn for the return PC is a call-used register,
3865 but must be saved by the prologue. */
3868 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3869 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3871 spill_reg_order[i] = n_spills;
3872 spill_regs[n_spills++] = i;
3873 if (num_eliminable && ! regs_ever_live[i])
3874 something_changed = 1;
3875 regs_ever_live[i] = 1;
3878 spill_reg_order[i] = -1;
3880 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3881 if (REGNO_REG_SET_P (spilled_pseudos, i))
3883 /* Record the current hard register the pseudo is allocated to in
3884 pseudo_previous_regs so we avoid reallocating it to the same
3885 hard reg in a later pass. */
3886 if (reg_renumber[i] < 0)
3888 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3889 /* Mark it as no longer having a hard register home. */
3890 reg_renumber[i] = -1;
3891 /* We will need to scan everything again. */
3892 something_changed = 1;
3895 /* Retry global register allocation if possible. */
3898 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3899 /* For every insn that needs reloads, set the registers used as spill
3900 regs in pseudo_forbidden_regs for every pseudo live across the
3902 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3904 EXECUTE_IF_SET_IN_REG_SET
3905 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3907 ior_hard_reg_set (pseudo_forbidden_regs + i,
3908 &chain->used_spill_regs);
3910 EXECUTE_IF_SET_IN_REG_SET
3911 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3913 ior_hard_reg_set (pseudo_forbidden_regs + i,
3914 &chain->used_spill_regs);
3918 /* Retry allocating the spilled pseudos. For each reg, merge the
3919 various reg sets that indicate which hard regs can't be used,
3920 and call retry_global_alloc.
3921 We change spill_pseudos here to only contain pseudos that did not
3922 get a new hard register. */
3923 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3924 if (reg_old_renumber[i] != reg_renumber[i])
3926 HARD_REG_SET forbidden;
3927 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3928 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3929 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3930 retry_global_alloc (i, forbidden);
3931 if (reg_renumber[i] >= 0)
3932 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3936 /* Fix up the register information in the insn chain.
3937 This involves deleting those of the spilled pseudos which did not get
3938 a new hard register home from the live_{before,after} sets. */
3939 for (chain = reload_insn_chain; chain; chain = chain->next)
3941 HARD_REG_SET used_by_pseudos;
3942 HARD_REG_SET used_by_pseudos2;
3944 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3945 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3947 /* Mark any unallocated hard regs as available for spills. That
3948 makes inheritance work somewhat better. */
3949 if (chain->need_reload)
3951 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3952 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3953 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3955 /* Save the old value for the sanity test below. */
3956 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3958 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3959 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3960 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3961 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3963 /* Make sure we only enlarge the set. */
3964 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3970 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3971 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3973 int regno = reg_renumber[i];
3974 if (reg_old_renumber[i] == regno)
3977 alter_reg (i, reg_old_renumber[i]);
3978 reg_old_renumber[i] = regno;
3982 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3984 fprintf (dumpfile, " Register %d now in %d.\n\n",
3985 i, reg_renumber[i]);
3989 return something_changed;
3992 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3993 Also mark any hard registers used to store user variables as
3994 forbidden from being used for spill registers. */
3997 scan_paradoxical_subregs (x)
4002 register enum rtx_code code = GET_CODE (x);
4008 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4009 && REG_USERVAR_P (x))
4010 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4026 if (GET_CODE (SUBREG_REG (x)) == REG
4027 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4028 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4029 = GET_MODE_SIZE (GET_MODE (x));
4036 fmt = GET_RTX_FORMAT (code);
4037 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4040 scan_paradoxical_subregs (XEXP (x, i));
4041 else if (fmt[i] == 'E')
4044 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4045 scan_paradoxical_subregs (XVECEXP (x, i, j));
4051 hard_reg_use_compare (p1p, p2p)
4052 const GENERIC_PTR p1p;
4053 const GENERIC_PTR p2p;
4055 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
4056 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
4057 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4058 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4060 return p1->regno - p2->regno;
4065 if (p1->uses > p2->uses)
4067 if (p1->uses < p2->uses)
4069 /* If regs are equally good, sort by regno,
4070 so that the results of qsort leave nothing to chance. */
4071 return p1->regno - p2->regno;
4074 /* Used for communication between order_regs_for_reload and count_pseudo.
4075 Used to avoid counting one pseudo twice. */
4076 static regset pseudos_counted;
4078 /* Update the costs in N_USES, considering that pseudo REG is live. */
4080 count_pseudo (n_uses, reg)
4081 struct hard_reg_n_uses *n_uses;
4084 int r = reg_renumber[reg];
4087 if (REGNO_REG_SET_P (pseudos_counted, reg))
4089 SET_REGNO_REG_SET (pseudos_counted, reg);
4094 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4096 n_uses[r++].uses += REG_N_REFS (reg);
4098 /* Choose the order to consider regs for use as reload registers
4099 based on how much trouble would be caused by spilling one.
4100 Store them in order of decreasing preference in potential_reload_regs. */
4103 order_regs_for_reload (chain)
4104 struct insn_chain *chain;
4108 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4110 pseudos_counted = ALLOCA_REG_SET ();
4112 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4114 /* Count number of uses of each hard reg by pseudo regs allocated to it
4115 and then order them by decreasing use. */
4117 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4121 hard_reg_n_uses[i].regno = i;
4122 hard_reg_n_uses[i].uses = 0;
4124 /* Test the various reasons why we can't use a register for
4125 spilling in this insn. */
4127 || REGNO_REG_SET_P (chain->live_before, i)
4128 || REGNO_REG_SET_P (chain->live_after, i))
4130 SET_HARD_REG_BIT (bad_spill_regs, i);
4134 /* Now find out which pseudos are allocated to it, and update
4136 CLEAR_REG_SET (pseudos_counted);
4138 EXECUTE_IF_SET_IN_REG_SET
4139 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4141 count_pseudo (hard_reg_n_uses, j);
4143 EXECUTE_IF_SET_IN_REG_SET
4144 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4146 count_pseudo (hard_reg_n_uses, j);
4150 FREE_REG_SET (pseudos_counted);
4152 /* Prefer registers not so far used, for use in temporary loading.
4153 Among them, if REG_ALLOC_ORDER is defined, use that order.
4154 Otherwise, prefer registers not preserved by calls. */
4156 #ifdef REG_ALLOC_ORDER
4157 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4159 int regno = reg_alloc_order[i];
4161 if (hard_reg_n_uses[regno].uses == 0
4162 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4163 potential_reload_regs[o++] = regno;
4166 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4168 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4169 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4170 potential_reload_regs[o++] = i;
4172 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4174 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4175 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4176 potential_reload_regs[o++] = i;
4180 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4181 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4183 /* Now add the regs that are already used,
4184 preferring those used less often. The fixed and otherwise forbidden
4185 registers will be at the end of this list. */
4187 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4188 if (hard_reg_n_uses[i].uses != 0
4189 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4190 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4191 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4192 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4193 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4196 /* Reload pseudo-registers into hard regs around each insn as needed.
4197 Additional register load insns are output before the insn that needs it
4198 and perhaps store insns after insns that modify the reloaded pseudo reg.
4200 reg_last_reload_reg and reg_reloaded_contents keep track of
4201 which registers are already available in reload registers.
4202 We update these for the reloads that we perform,
4203 as the insns are scanned. */
4206 reload_as_needed (live_known)
4209 struct insn_chain *chain;
4210 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4215 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4216 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4217 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4218 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4219 reg_has_output_reload = (char *) alloca (max_regno);
4220 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4222 set_initial_elim_offsets ();
4224 for (chain = reload_insn_chain; chain; chain = chain->next)
4227 rtx insn = chain->insn;
4228 rtx old_next = NEXT_INSN (insn);
4230 /* If we pass a label, copy the offsets from the label information
4231 into the current offsets of each elimination. */
4232 if (GET_CODE (insn) == CODE_LABEL)
4233 set_offsets_for_label (insn);
4235 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4237 rtx oldpat = PATTERN (insn);
4239 /* If this is a USE and CLOBBER of a MEM, ensure that any
4240 references to eliminable registers have been removed. */
4242 if ((GET_CODE (PATTERN (insn)) == USE
4243 || GET_CODE (PATTERN (insn)) == CLOBBER)
4244 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4245 XEXP (XEXP (PATTERN (insn), 0), 0)
4246 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4247 GET_MODE (XEXP (PATTERN (insn), 0)),
4250 /* If we need to do register elimination processing, do so.
4251 This might delete the insn, in which case we are done. */
4252 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4254 eliminate_regs_in_insn (insn, 1);
4255 if (GET_CODE (insn) == NOTE)
4257 update_eliminable_offsets ();
4262 /* If need_elim is nonzero but need_reload is zero, one might think
4263 that we could simply set n_reloads to 0. However, find_reloads
4264 could have done some manipulation of the insn (such as swapping
4265 commutative operands), and these manipulations are lost during
4266 the first pass for every insn that needs register elimination.
4267 So the actions of find_reloads must be redone here. */
4269 if (! chain->need_elim && ! chain->need_reload
4270 && ! chain->need_operand_change)
4272 /* First find the pseudo regs that must be reloaded for this insn.
4273 This info is returned in the tables reload_... (see reload.h).
4274 Also modify the body of INSN by substituting RELOAD
4275 rtx's for those pseudo regs. */
4278 bzero (reg_has_output_reload, max_regno);
4279 CLEAR_HARD_REG_SET (reg_is_output_reload);
4281 find_reloads (insn, 1, spill_indirect_levels, live_known,
4285 if (num_eliminable && chain->need_elim)
4286 update_eliminable_offsets ();
4290 rtx next = NEXT_INSN (insn);
4293 prev = PREV_INSN (insn);
4295 /* Now compute which reload regs to reload them into. Perhaps
4296 reusing reload regs from previous insns, or else output
4297 load insns to reload them. Maybe output store insns too.
4298 Record the choices of reload reg in reload_reg_rtx. */
4299 choose_reload_regs (chain);
4301 /* Merge any reloads that we didn't combine for fear of
4302 increasing the number of spill registers needed but now
4303 discover can be safely merged. */
4304 if (SMALL_REGISTER_CLASSES)
4305 merge_assigned_reloads (insn);
4307 /* Generate the insns to reload operands into or out of
4308 their reload regs. */
4309 emit_reload_insns (chain);
4311 /* Substitute the chosen reload regs from reload_reg_rtx
4312 into the insn's body (or perhaps into the bodies of other
4313 load and store insn that we just made for reloading
4314 and that we moved the structure into). */
4317 /* If this was an ASM, make sure that all the reload insns
4318 we have generated are valid. If not, give an error
4321 if (asm_noperands (PATTERN (insn)) >= 0)
4322 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4323 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4324 && (recog_memoized (p) < 0
4325 || (extract_insn (p), ! constrain_operands (1))))
4327 error_for_asm (insn,
4328 "`asm' operand requires impossible reload");
4330 NOTE_SOURCE_FILE (p) = 0;
4331 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4334 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4335 is no longer validly lying around to save a future reload.
4336 Note that this does not detect pseudos that were reloaded
4337 for this insn in order to be stored in
4338 (obeying register constraints). That is correct; such reload
4339 registers ARE still valid. */
4340 note_stores (oldpat, forget_old_reloads_1);
4342 /* There may have been CLOBBER insns placed after INSN. So scan
4343 between INSN and NEXT and use them to forget old reloads. */
4344 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4345 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4346 note_stores (PATTERN (x), forget_old_reloads_1);
4349 /* Likewise for regs altered by auto-increment in this insn.
4350 REG_INC notes have been changed by reloading:
4351 find_reloads_address_1 records substitutions for them,
4352 which have been performed by subst_reloads above. */
4353 for (i = n_reloads - 1; i >= 0; i--)
4355 rtx in_reg = reload_in_reg[i];
4358 enum rtx_code code = GET_CODE (in_reg);
4359 /* PRE_INC / PRE_DEC will have the reload register ending up
4360 with the same value as the stack slot, but that doesn't
4361 hold true for POST_INC / POST_DEC. Either we have to
4362 convert the memory access to a true POST_INC / POST_DEC,
4363 or we can't use the reload register for inheritance. */
4364 if ((code == POST_INC || code == POST_DEC)
4365 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4366 REGNO (reload_reg_rtx[i]))
4367 /* Make sure it is the inc/dec pseudo, and not
4368 some other (e.g. output operand) pseudo. */
4369 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4370 == REGNO (XEXP (in_reg, 0))))
4373 rtx reload_reg = reload_reg_rtx[i];
4374 enum machine_mode mode = GET_MODE (reload_reg);
4378 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4380 /* We really want to ignore REG_INC notes here, so
4381 use PATTERN (p) as argument to reg_set_p . */
4382 if (reg_set_p (reload_reg, PATTERN (p)))
4384 n = count_occurrences (PATTERN (p), reload_reg);
4389 n = validate_replace_rtx (reload_reg,
4390 gen_rtx (code, mode,
4394 /* We must also verify that the constraints
4395 are met after the replacement. */
4398 n = constrain_operands (1);
4402 /* If the constraints were not met, then
4403 undo the replacement. */
4406 validate_replace_rtx (gen_rtx (code, mode,
4416 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4419 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4423 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4424 /* Likewise for regs altered by auto-increment in this insn.
4425 But note that the reg-notes are not changed by reloading:
4426 they still contain the pseudo-regs, not the spill regs. */
4427 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4428 if (REG_NOTE_KIND (x) == REG_INC)
4430 /* See if this pseudo reg was reloaded in this insn.
4431 If so, its last-reload info is still valid
4432 because it is based on this insn's reload. */
4433 for (i = 0; i < n_reloads; i++)
4434 if (reload_out[i] == XEXP (x, 0))
4438 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4443 /* A reload reg's contents are unknown after a label. */
4444 if (GET_CODE (insn) == CODE_LABEL)
4445 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4447 /* Don't assume a reload reg is still good after a call insn
4448 if it is a call-used reg. */
4449 else if (GET_CODE (insn) == CALL_INSN)
4450 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4452 /* In case registers overlap, allow certain insns to invalidate
4453 particular hard registers. */
4455 #ifdef INSN_CLOBBERS_REGNO_P
4456 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4457 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4458 && INSN_CLOBBERS_REGNO_P (insn, i))
4459 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4468 /* Discard all record of any value reloaded from X,
4469 or reloaded in X from someplace else;
4470 unless X is an output reload reg of the current insn.
4472 X may be a hard reg (the reload reg)
4473 or it may be a pseudo reg that was reloaded from. */
4476 forget_old_reloads_1 (x, ignored)
4478 rtx ignored ATTRIBUTE_UNUSED;
4484 /* note_stores does give us subregs of hard regs. */
4485 while (GET_CODE (x) == SUBREG)
4487 offset += SUBREG_WORD (x);
4491 if (GET_CODE (x) != REG)
4494 regno = REGNO (x) + offset;
4496 if (regno >= FIRST_PSEUDO_REGISTER)
4501 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4502 /* Storing into a spilled-reg invalidates its contents.
4503 This can happen if a block-local pseudo is allocated to that reg
4504 and it wasn't spilled because this block's total need is 0.
4505 Then some insn might have an optional reload and use this reg. */
4506 for (i = 0; i < nr; i++)
4507 /* But don't do this if the reg actually serves as an output
4508 reload reg in the current instruction. */
4510 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4511 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4514 /* Since value of X has changed,
4515 forget any value previously copied from it. */
4518 /* But don't forget a copy if this is the output reload
4519 that establishes the copy's validity. */
4520 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4521 reg_last_reload_reg[regno + nr] = 0;
4524 /* For each reload, the mode of the reload register. */
4525 static enum machine_mode reload_mode[MAX_RELOADS];
4527 /* For each reload, the largest number of registers it will require. */
4528 static int reload_nregs[MAX_RELOADS];
4530 /* Comparison function for qsort to decide which of two reloads
4531 should be handled first. *P1 and *P2 are the reload numbers. */
4534 reload_reg_class_lower (r1p, r2p)
4535 const GENERIC_PTR r1p;
4536 const GENERIC_PTR r2p;
4538 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4541 /* Consider required reloads before optional ones. */
4542 t = reload_optional[r1] - reload_optional[r2];
4546 /* Count all solitary classes before non-solitary ones. */
4547 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4548 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4552 /* Aside from solitaires, consider all multi-reg groups first. */
4553 t = reload_nregs[r2] - reload_nregs[r1];
4557 /* Consider reloads in order of increasing reg-class number. */
4558 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4562 /* If reloads are equally urgent, sort by reload number,
4563 so that the results of qsort leave nothing to chance. */
4567 /* The following HARD_REG_SETs indicate when each hard register is
4568 used for a reload of various parts of the current insn. */
4570 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4571 static HARD_REG_SET reload_reg_used;
4572 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4573 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4574 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4575 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4576 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4577 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4578 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4579 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4580 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4581 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4582 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4583 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4584 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4585 static HARD_REG_SET reload_reg_used_in_op_addr;
4586 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4587 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4588 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4589 static HARD_REG_SET reload_reg_used_in_insn;
4590 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4591 static HARD_REG_SET reload_reg_used_in_other_addr;
4593 /* If reg is in use as a reload reg for any sort of reload. */
4594 static HARD_REG_SET reload_reg_used_at_all;
4596 /* If reg is use as an inherited reload. We just mark the first register
4598 static HARD_REG_SET reload_reg_used_for_inherit;
4600 /* Records which hard regs are used in any way, either as explicit use or
4601 by being allocated to a pseudo during any point of the current insn. */
4602 static HARD_REG_SET reg_used_in_insn;
4604 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4605 TYPE. MODE is used to indicate how many consecutive regs are
4609 mark_reload_reg_in_use (regno, opnum, type, mode)
4612 enum reload_type type;
4613 enum machine_mode mode;
4615 int nregs = HARD_REGNO_NREGS (regno, mode);
4618 for (i = regno; i < nregs + regno; i++)
4623 SET_HARD_REG_BIT (reload_reg_used, i);
4626 case RELOAD_FOR_INPUT_ADDRESS:
4627 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4630 case RELOAD_FOR_INPADDR_ADDRESS:
4631 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4634 case RELOAD_FOR_OUTPUT_ADDRESS:
4635 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4638 case RELOAD_FOR_OUTADDR_ADDRESS:
4639 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4642 case RELOAD_FOR_OPERAND_ADDRESS:
4643 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4646 case RELOAD_FOR_OPADDR_ADDR:
4647 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4650 case RELOAD_FOR_OTHER_ADDRESS:
4651 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4654 case RELOAD_FOR_INPUT:
4655 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4658 case RELOAD_FOR_OUTPUT:
4659 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4662 case RELOAD_FOR_INSN:
4663 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4667 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4671 /* Similarly, but show REGNO is no longer in use for a reload. */
4674 clear_reload_reg_in_use (regno, opnum, type, mode)
4677 enum reload_type type;
4678 enum machine_mode mode;
4680 int nregs = HARD_REGNO_NREGS (regno, mode);
4681 int start_regno, end_regno;
4683 /* A complication is that for some reload types, inheritance might
4684 allow multiple reloads of the same types to share a reload register.
4685 We set check_opnum if we have to check only reloads with the same
4686 operand number, and check_any if we have to check all reloads. */
4687 int check_opnum = 0;
4689 HARD_REG_SET *used_in_set;
4694 used_in_set = &reload_reg_used;
4697 case RELOAD_FOR_INPUT_ADDRESS:
4698 used_in_set = &reload_reg_used_in_input_addr[opnum];
4701 case RELOAD_FOR_INPADDR_ADDRESS:
4703 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4706 case RELOAD_FOR_OUTPUT_ADDRESS:
4707 used_in_set = &reload_reg_used_in_output_addr[opnum];
4710 case RELOAD_FOR_OUTADDR_ADDRESS:
4712 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4715 case RELOAD_FOR_OPERAND_ADDRESS:
4716 used_in_set = &reload_reg_used_in_op_addr;
4719 case RELOAD_FOR_OPADDR_ADDR:
4721 used_in_set = &reload_reg_used_in_op_addr_reload;
4724 case RELOAD_FOR_OTHER_ADDRESS:
4725 used_in_set = &reload_reg_used_in_other_addr;
4729 case RELOAD_FOR_INPUT:
4730 used_in_set = &reload_reg_used_in_input[opnum];
4733 case RELOAD_FOR_OUTPUT:
4734 used_in_set = &reload_reg_used_in_output[opnum];
4737 case RELOAD_FOR_INSN:
4738 used_in_set = &reload_reg_used_in_insn;
4743 /* We resolve conflicts with remaining reloads of the same type by
4744 excluding the intervals of of reload registers by them from the
4745 interval of freed reload registers. Since we only keep track of
4746 one set of interval bounds, we might have to exclude somewhat
4747 more then what would be necessary if we used a HARD_REG_SET here.
4748 But this should only happen very infrequently, so there should
4749 be no reason to worry about it. */
4751 start_regno = regno;
4752 end_regno = regno + nregs;
4753 if (check_opnum || check_any)
4755 for (i = n_reloads - 1; i >= 0; i--)
4757 if (reload_when_needed[i] == type
4758 && (check_any || reload_opnum[i] == opnum)
4759 && reload_reg_rtx[i])
4761 int conflict_start = true_regnum (reload_reg_rtx[i]);
4764 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4766 /* If there is an overlap with the first to-be-freed register,
4767 adjust the interval start. */
4768 if (conflict_start <= start_regno && conflict_end > start_regno)
4769 start_regno = conflict_end;
4770 /* Otherwise, if there is a conflict with one of the other
4771 to-be-freed registers, adjust the interval end. */
4772 if (conflict_start > start_regno && conflict_start < end_regno)
4773 end_regno = conflict_start;
4777 for (i = start_regno; i < end_regno; i++)
4778 CLEAR_HARD_REG_BIT (*used_in_set, i);
4781 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4782 specified by OPNUM and TYPE. */
4785 reload_reg_free_p (regno, opnum, type)
4788 enum reload_type type;
4792 /* In use for a RELOAD_OTHER means it's not available for anything. */
4793 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4799 /* In use for anything means we can't use it for RELOAD_OTHER. */
4800 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4801 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4805 for (i = 0; i < reload_n_operands; i++)
4806 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4807 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4808 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4809 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4816 case RELOAD_FOR_INPUT:
4817 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4824 /* If it is used for some other input, can't use it. */
4825 for (i = 0; i < reload_n_operands; i++)
4826 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4829 /* If it is used in a later operand's address, can't use it. */
4830 for (i = opnum + 1; i < reload_n_operands; i++)
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4837 case RELOAD_FOR_INPUT_ADDRESS:
4838 /* Can't use a register if it is used for an input address for this
4839 operand or used as an input in an earlier one. */
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4841 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4844 for (i = 0; i < opnum; i++)
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4850 case RELOAD_FOR_INPADDR_ADDRESS:
4851 /* Can't use a register if it is used for an input address
4852 for this operand or used as an input in an earlier
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4857 for (i = 0; i < opnum; i++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4863 case RELOAD_FOR_OUTPUT_ADDRESS:
4864 /* Can't use a register if it is used for an output address for this
4865 operand or used as an output in this or a later operand. */
4866 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4869 for (i = opnum; i < reload_n_operands; i++)
4870 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4875 case RELOAD_FOR_OUTADDR_ADDRESS:
4876 /* Can't use a register if it is used for an output address
4877 for this operand or used as an output in this or a
4879 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4882 for (i = opnum; i < reload_n_operands; i++)
4883 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4888 case RELOAD_FOR_OPERAND_ADDRESS:
4889 for (i = 0; i < reload_n_operands; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4893 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4894 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4896 case RELOAD_FOR_OPADDR_ADDR:
4897 for (i = 0; i < reload_n_operands; i++)
4898 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4901 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4903 case RELOAD_FOR_OUTPUT:
4904 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4905 outputs, or an operand address for this or an earlier output. */
4906 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4909 for (i = 0; i < reload_n_operands; i++)
4910 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4913 for (i = 0; i <= opnum; i++)
4914 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4915 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4920 case RELOAD_FOR_INSN:
4921 for (i = 0; i < reload_n_operands; i++)
4922 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4923 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4926 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4927 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4929 case RELOAD_FOR_OTHER_ADDRESS:
4930 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4935 /* Return 1 if the value in reload reg REGNO, as used by a reload
4936 needed for the part of the insn specified by OPNUM and TYPE,
4937 is still available in REGNO at the end of the insn.
4939 We can assume that the reload reg was already tested for availability
4940 at the time it is needed, and we should not check this again,
4941 in case the reg has already been marked in use. */
4944 reload_reg_reaches_end_p (regno, opnum, type)
4947 enum reload_type type;
4954 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4955 its value must reach the end. */
4958 /* If this use is for part of the insn,
4959 its value reaches if no subsequent part uses the same register.
4960 Just like the above function, don't try to do this with lots
4963 case RELOAD_FOR_OTHER_ADDRESS:
4964 /* Here we check for everything else, since these don't conflict
4965 with anything else and everything comes later. */
4967 for (i = 0; i < reload_n_operands; i++)
4968 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4969 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4970 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4971 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4972 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4973 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4976 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4977 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4978 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4980 case RELOAD_FOR_INPUT_ADDRESS:
4981 case RELOAD_FOR_INPADDR_ADDRESS:
4982 /* Similar, except that we check only for this and subsequent inputs
4983 and the address of only subsequent inputs and we do not need
4984 to check for RELOAD_OTHER objects since they are known not to
4987 for (i = opnum; i < reload_n_operands; i++)
4988 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4991 for (i = opnum + 1; i < reload_n_operands; i++)
4992 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4996 for (i = 0; i < reload_n_operands; i++)
4997 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4998 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4999 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5002 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5005 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5006 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5008 case RELOAD_FOR_INPUT:
5009 /* Similar to input address, except we start at the next operand for
5010 both input and input address and we do not check for
5011 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5014 for (i = opnum + 1; i < reload_n_operands; i++)
5015 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5016 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5017 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5020 /* ... fall through ... */
5022 case RELOAD_FOR_OPERAND_ADDRESS:
5023 /* Check outputs and their addresses. */
5025 for (i = 0; i < reload_n_operands; i++)
5026 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5028 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5033 case RELOAD_FOR_OPADDR_ADDR:
5034 for (i = 0; i < reload_n_operands; i++)
5035 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5036 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5040 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5041 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5043 case RELOAD_FOR_INSN:
5044 /* These conflict with other outputs with RELOAD_OTHER. So
5045 we need only check for output addresses. */
5049 /* ... fall through ... */
5051 case RELOAD_FOR_OUTPUT:
5052 case RELOAD_FOR_OUTPUT_ADDRESS:
5053 case RELOAD_FOR_OUTADDR_ADDRESS:
5054 /* We already know these can't conflict with a later output. So the
5055 only thing to check are later output addresses. */
5056 for (i = opnum + 1; i < reload_n_operands; i++)
5057 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5058 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5067 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5070 This function uses the same algorithm as reload_reg_free_p above. */
5073 reloads_conflict (r1, r2)
5076 enum reload_type r1_type = reload_when_needed[r1];
5077 enum reload_type r2_type = reload_when_needed[r2];
5078 int r1_opnum = reload_opnum[r1];
5079 int r2_opnum = reload_opnum[r2];
5081 /* RELOAD_OTHER conflicts with everything. */
5082 if (r2_type == RELOAD_OTHER)
5085 /* Otherwise, check conflicts differently for each type. */
5089 case RELOAD_FOR_INPUT:
5090 return (r2_type == RELOAD_FOR_INSN
5091 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5092 || r2_type == RELOAD_FOR_OPADDR_ADDR
5093 || r2_type == RELOAD_FOR_INPUT
5094 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5095 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5096 && r2_opnum > r1_opnum));
5098 case RELOAD_FOR_INPUT_ADDRESS:
5099 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5100 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5102 case RELOAD_FOR_INPADDR_ADDRESS:
5103 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5104 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5106 case RELOAD_FOR_OUTPUT_ADDRESS:
5107 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5108 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5110 case RELOAD_FOR_OUTADDR_ADDRESS:
5111 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5112 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5114 case RELOAD_FOR_OPERAND_ADDRESS:
5115 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5116 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5118 case RELOAD_FOR_OPADDR_ADDR:
5119 return (r2_type == RELOAD_FOR_INPUT
5120 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5122 case RELOAD_FOR_OUTPUT:
5123 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5124 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5125 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5126 && r2_opnum >= r1_opnum));
5128 case RELOAD_FOR_INSN:
5129 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5130 || r2_type == RELOAD_FOR_INSN
5131 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5133 case RELOAD_FOR_OTHER_ADDRESS:
5134 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5144 /* Vector of reload-numbers showing the order in which the reloads should
5146 short reload_order[MAX_RELOADS];
5148 /* Indexed by reload number, 1 if incoming value
5149 inherited from previous insns. */
5150 char reload_inherited[MAX_RELOADS];
5152 /* For an inherited reload, this is the insn the reload was inherited from,
5153 if we know it. Otherwise, this is 0. */
5154 rtx reload_inheritance_insn[MAX_RELOADS];
5156 /* If non-zero, this is a place to get the value of the reload,
5157 rather than using reload_in. */
5158 rtx reload_override_in[MAX_RELOADS];
5160 /* For each reload, the hard register number of the register used,
5161 or -1 if we did not need a register for this reload. */
5162 int reload_spill_index[MAX_RELOADS];
5164 /* Return 1 if the value in reload reg REGNO, as used by a reload
5165 needed for the part of the insn specified by OPNUM and TYPE,
5166 may be used to load VALUE into it.
5168 Other read-only reloads with the same value do not conflict
5169 unless OUT is non-zero and these other reloads have to live while
5170 output reloads live.
5171 If OUT is CONST0_RTX, this is a special case: it means that the
5172 test should not be for using register REGNO as reload register, but
5173 for copying from register REGNO into the reload register.
5175 RELOADNUM is the number of the reload we want to load this value for;
5176 a reload does not conflict with itself.
5178 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5179 reloads that load an address for the very reload we are considering.
5181 The caller has to make sure that there is no conflict with the return
5184 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5185 ignore_address_reloads)
5188 enum reload_type type;
5191 int ignore_address_reloads;
5197 if (out == const0_rtx)
5203 /* We use some pseudo 'time' value to check if the lifetimes of the
5204 new register use would overlap with the one of a previous reload
5205 that is not read-only or uses a different value.
5206 The 'time' used doesn't have to be linear in any shape or form, just
5208 Some reload types use different 'buckets' for each operand.
5209 So there are MAX_RECOG_OPERANDS different time values for each
5211 We compute TIME1 as the time when the register for the prospective
5212 new reload ceases to be live, and TIME2 for each existing
5213 reload as the time when that the reload register of that reload
5215 Where there is little to be gained by exact lifetime calculations,
5216 we just make conservative assumptions, i.e. a longer lifetime;
5217 this is done in the 'default:' cases. */
5220 case RELOAD_FOR_OTHER_ADDRESS:
5224 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5226 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5227 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5228 respectively, to the time values for these, we get distinct time
5229 values. To get distinct time values for each operand, we have to
5230 multiply opnum by at least three. We round that up to four because
5231 multiply by four is often cheaper. */
5232 case RELOAD_FOR_INPADDR_ADDRESS:
5233 time1 = opnum * 4 + 2;
5235 case RELOAD_FOR_INPUT_ADDRESS:
5236 time1 = opnum * 4 + 3;
5238 case RELOAD_FOR_INPUT:
5239 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5240 executes (inclusive). */
5241 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5243 case RELOAD_FOR_OPADDR_ADDR:
5245 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5246 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5248 case RELOAD_FOR_OPERAND_ADDRESS:
5249 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5251 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5253 case RELOAD_FOR_OUTADDR_ADDRESS:
5254 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5256 case RELOAD_FOR_OUTPUT_ADDRESS:
5257 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5260 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5263 for (i = 0; i < n_reloads; i++)
5265 rtx reg = reload_reg_rtx[i];
5266 if (reg && GET_CODE (reg) == REG
5267 && ((unsigned) regno - true_regnum (reg)
5268 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5271 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5272 || reload_out[i] || out)
5275 switch (reload_when_needed[i])
5277 case RELOAD_FOR_OTHER_ADDRESS:
5280 case RELOAD_FOR_INPADDR_ADDRESS:
5281 /* find_reloads makes sure that a
5282 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5283 by at most one - the first -
5284 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5285 address reload is inherited, the address address reload
5286 goes away, so we can ignore this conflict. */
5287 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5288 && ignore_address_reloads
5289 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5290 Then the address address is still needed to store
5291 back the new address. */
5292 && ! reload_out[reloadnum])
5294 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5295 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5297 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5298 && ignore_address_reloads
5299 /* Unless we are reloading an auto_inc expression. */
5300 && ! reload_out[reloadnum])
5302 time2 = reload_opnum[i] * 4 + 2;
5304 case RELOAD_FOR_INPUT_ADDRESS:
5305 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5306 && ignore_address_reloads
5307 && ! reload_out[reloadnum])
5309 time2 = reload_opnum[i] * 4 + 3;
5311 case RELOAD_FOR_INPUT:
5312 time2 = reload_opnum[i] * 4 + 4;
5314 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5315 == MAX_RECOG_OPERAND * 4 */
5316 case RELOAD_FOR_OPADDR_ADDR:
5317 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5318 && ignore_address_reloads
5319 && ! reload_out[reloadnum])
5321 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5323 case RELOAD_FOR_OPERAND_ADDRESS:
5324 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5326 case RELOAD_FOR_INSN:
5327 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5329 case RELOAD_FOR_OUTPUT:
5330 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5331 instruction is executed. */
5332 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5334 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5335 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5337 case RELOAD_FOR_OUTADDR_ADDRESS:
5338 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5339 && ignore_address_reloads
5340 && ! reload_out[reloadnum])
5342 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5344 case RELOAD_FOR_OUTPUT_ADDRESS:
5345 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5348 /* If there is no conflict in the input part, handle this
5349 like an output reload. */
5350 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5352 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5356 /* RELOAD_OTHER might be live beyond instruction execution,
5357 but this is not obvious when we set time2 = 1. So check
5358 here if there might be a problem with the new reload
5359 clobbering the register used by the RELOAD_OTHER. */
5367 && (! reload_in[i] || reload_out[i]
5368 || ! rtx_equal_p (reload_in[i], value)))
5369 || (out && reload_out_reg[reloadnum]
5370 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5378 /* Find a spill register to use as a reload register for reload R.
5379 LAST_RELOAD is non-zero if this is the last reload for the insn being
5382 Set reload_reg_rtx[R] to the register allocated.
5384 If NOERROR is nonzero, we return 1 if successful,
5385 or 0 if we couldn't find a spill reg and we didn't change anything. */
5388 allocate_reload_reg (chain, r, last_reload, noerror)
5389 struct insn_chain *chain;
5394 rtx insn = chain->insn;
5395 int i, pass, count, regno;
5398 /* If we put this reload ahead, thinking it is a group,
5399 then insist on finding a group. Otherwise we can grab a
5400 reg that some other reload needs.
5401 (That can happen when we have a 68000 DATA_OR_FP_REG
5402 which is a group of data regs or one fp reg.)
5403 We need not be so restrictive if there are no more reloads
5406 ??? Really it would be nicer to have smarter handling
5407 for that kind of reg class, where a problem like this is normal.
5408 Perhaps those classes should be avoided for reloading
5409 by use of more alternatives. */
5411 int force_group = reload_nregs[r] > 1 && ! last_reload;
5413 /* If we want a single register and haven't yet found one,
5414 take any reg in the right class and not in use.
5415 If we want a consecutive group, here is where we look for it.
5417 We use two passes so we can first look for reload regs to
5418 reuse, which are already in use for other reloads in this insn,
5419 and only then use additional registers.
5420 I think that maximizing reuse is needed to make sure we don't
5421 run out of reload regs. Suppose we have three reloads, and
5422 reloads A and B can share regs. These need two regs.
5423 Suppose A and B are given different regs.
5424 That leaves none for C. */
5425 for (pass = 0; pass < 2; pass++)
5427 /* I is the index in spill_regs.
5428 We advance it round-robin between insns to use all spill regs
5429 equally, so that inherited reloads have a chance
5430 of leapfrogging each other. Don't do this, however, when we have
5431 group needs and failure would be fatal; if we only have a relatively
5432 small number of spill registers, and more than one of them has
5433 group needs, then by starting in the middle, we may end up
5434 allocating the first one in such a way that we are not left with
5435 sufficient groups to handle the rest. */
5437 if (noerror || ! force_group)
5442 for (count = 0; count < n_spills; count++)
5444 int class = (int) reload_reg_class[r];
5450 regnum = spill_regs[i];
5452 if ((reload_reg_free_p (regnum, reload_opnum[r],
5453 reload_when_needed[r])
5455 /* We check reload_reg_used to make sure we
5456 don't clobber the return register. */
5457 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5458 && reload_reg_free_for_value_p (regnum,
5460 reload_when_needed[r],
5462 reload_out[r], r, 1)))
5463 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5464 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5465 /* Look first for regs to share, then for unshared. But
5466 don't share regs used for inherited reloads; they are
5467 the ones we want to preserve. */
5469 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5471 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5474 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5475 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5476 (on 68000) got us two FP regs. If NR is 1,
5477 we would reject both of them. */
5479 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5480 /* If we need only one reg, we have already won. */
5483 /* But reject a single reg if we demand a group. */
5488 /* Otherwise check that as many consecutive regs as we need
5490 Also, don't use for a group registers that are
5491 needed for nongroups. */
5492 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5495 regno = regnum + nr - 1;
5496 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5497 && spill_reg_order[regno] >= 0
5498 && reload_reg_free_p (regno, reload_opnum[r],
5499 reload_when_needed[r])
5500 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5510 /* If we found something on pass 1, omit pass 2. */
5511 if (count < n_spills)
5515 /* We should have found a spill register by now. */
5516 if (count == n_spills)
5523 /* I is the index in SPILL_REG_RTX of the reload register we are to
5524 allocate. Get an rtx for it and find its register number. */
5526 new = spill_reg_rtx[i];
5528 if (new == 0 || GET_MODE (new) != reload_mode[r])
5529 spill_reg_rtx[i] = new
5530 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5532 regno = true_regnum (new);
5534 /* Detect when the reload reg can't hold the reload mode.
5535 This used to be one `if', but Sequent compiler can't handle that. */
5536 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5538 enum machine_mode test_mode = VOIDmode;
5540 test_mode = GET_MODE (reload_in[r]);
5541 /* If reload_in[r] has VOIDmode, it means we will load it
5542 in whatever mode the reload reg has: to wit, reload_mode[r].
5543 We have already tested that for validity. */
5544 /* Aside from that, we need to test that the expressions
5545 to reload from or into have modes which are valid for this
5546 reload register. Otherwise the reload insns would be invalid. */
5547 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5548 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5549 if (! (reload_out[r] != 0
5550 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5552 /* The reg is OK. */
5555 /* Mark as in use for this insn the reload regs we use
5557 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5558 reload_when_needed[r], reload_mode[r]);
5560 reload_reg_rtx[r] = new;
5561 reload_spill_index[r] = spill_regs[i];
5566 /* The reg is not OK. */
5571 if (asm_noperands (PATTERN (insn)) < 0)
5572 /* It's the compiler's fault. */
5573 fatal_insn ("Could not find a spill register", insn);
5575 /* It's the user's fault; the operand's mode and constraint
5576 don't match. Disable this reload so we don't crash in final. */
5577 error_for_asm (insn,
5578 "`asm' operand constraint incompatible with operand size");
5581 reload_reg_rtx[r] = 0;
5582 reload_optional[r] = 1;
5583 reload_secondary_p[r] = 1;
5588 /* Assign hard reg targets for the pseudo-registers we must reload
5589 into hard regs for this insn.
5590 Also output the instructions to copy them in and out of the hard regs.
5592 For machines with register classes, we are responsible for
5593 finding a reload reg in the proper class. */
5596 choose_reload_regs (chain)
5597 struct insn_chain *chain;
5599 rtx insn = chain->insn;
5601 int max_group_size = 1;
5602 enum reg_class group_class = NO_REGS;
5606 rtx save_reload_reg_rtx[MAX_RELOADS];
5607 char save_reload_inherited[MAX_RELOADS];
5608 rtx save_reload_inheritance_insn[MAX_RELOADS];
5609 rtx save_reload_override_in[MAX_RELOADS];
5610 int save_reload_spill_index[MAX_RELOADS];
5611 HARD_REG_SET save_reload_reg_used;
5612 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5613 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5614 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5615 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5616 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5617 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5618 HARD_REG_SET save_reload_reg_used_in_op_addr;
5619 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5620 HARD_REG_SET save_reload_reg_used_in_insn;
5621 HARD_REG_SET save_reload_reg_used_in_other_addr;
5622 HARD_REG_SET save_reload_reg_used_at_all;
5624 bzero (reload_inherited, MAX_RELOADS);
5625 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5626 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5628 CLEAR_HARD_REG_SET (reload_reg_used);
5629 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5630 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5631 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5632 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5633 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5635 CLEAR_HARD_REG_SET (reg_used_in_insn);
5638 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5639 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5640 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5641 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5642 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5643 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5645 for (i = 0; i < reload_n_operands; i++)
5647 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5648 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5649 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5650 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5651 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5652 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5655 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5657 #if 0 /* Not needed, now that we can always retry without inheritance. */
5658 /* See if we have more mandatory reloads than spill regs.
5659 If so, then we cannot risk optimizations that could prevent
5660 reloads from sharing one spill register.
5662 Since we will try finding a better register than reload_reg_rtx
5663 unless it is equal to reload_in or reload_out, count such reloads. */
5667 for (j = 0; j < n_reloads; j++)
5668 if (! reload_optional[j]
5669 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5670 && (reload_reg_rtx[j] == 0
5671 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5672 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5679 /* In order to be certain of getting the registers we need,
5680 we must sort the reloads into order of increasing register class.
5681 Then our grabbing of reload registers will parallel the process
5682 that provided the reload registers.
5684 Also note whether any of the reloads wants a consecutive group of regs.
5685 If so, record the maximum size of the group desired and what
5686 register class contains all the groups needed by this insn. */
5688 for (j = 0; j < n_reloads; j++)
5690 reload_order[j] = j;
5691 reload_spill_index[j] = -1;
5694 = (reload_inmode[j] == VOIDmode
5695 || (GET_MODE_SIZE (reload_outmode[j])
5696 > GET_MODE_SIZE (reload_inmode[j])))
5697 ? reload_outmode[j] : reload_inmode[j];
5699 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5701 if (reload_nregs[j] > 1)
5703 max_group_size = MAX (reload_nregs[j], max_group_size);
5704 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5707 /* If we have already decided to use a certain register,
5708 don't use it in another way. */
5709 if (reload_reg_rtx[j])
5710 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5711 reload_when_needed[j], reload_mode[j]);
5715 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5717 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5718 sizeof reload_reg_rtx);
5719 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5720 bcopy ((char *) reload_inheritance_insn,
5721 (char *) save_reload_inheritance_insn,
5722 sizeof reload_inheritance_insn);
5723 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5724 sizeof reload_override_in);
5725 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5726 sizeof reload_spill_index);
5727 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5728 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5729 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5730 reload_reg_used_in_op_addr);
5732 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5733 reload_reg_used_in_op_addr_reload);
5735 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5736 reload_reg_used_in_insn);
5737 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5738 reload_reg_used_in_other_addr);
5740 for (i = 0; i < reload_n_operands; i++)
5742 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5743 reload_reg_used_in_output[i]);
5744 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5745 reload_reg_used_in_input[i]);
5746 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5747 reload_reg_used_in_input_addr[i]);
5748 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5749 reload_reg_used_in_inpaddr_addr[i]);
5750 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5751 reload_reg_used_in_output_addr[i]);
5752 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5753 reload_reg_used_in_outaddr_addr[i]);
5756 /* If -O, try first with inheritance, then turning it off.
5757 If not -O, don't do inheritance.
5758 Using inheritance when not optimizing leads to paradoxes
5759 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5760 because one side of the comparison might be inherited. */
5762 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5764 /* Process the reloads in order of preference just found.
5765 Beyond this point, subregs can be found in reload_reg_rtx.
5767 This used to look for an existing reloaded home for all
5768 of the reloads, and only then perform any new reloads.
5769 But that could lose if the reloads were done out of reg-class order
5770 because a later reload with a looser constraint might have an old
5771 home in a register needed by an earlier reload with a tighter constraint.
5773 To solve this, we make two passes over the reloads, in the order
5774 described above. In the first pass we try to inherit a reload
5775 from a previous insn. If there is a later reload that needs a
5776 class that is a proper subset of the class being processed, we must
5777 also allocate a spill register during the first pass.
5779 Then make a second pass over the reloads to allocate any reloads
5780 that haven't been given registers yet. */
5782 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5784 for (j = 0; j < n_reloads; j++)
5786 register int r = reload_order[j];
5788 /* Ignore reloads that got marked inoperative. */
5789 if (reload_out[r] == 0 && reload_in[r] == 0
5790 && ! reload_secondary_p[r])
5793 /* If find_reloads chose to use reload_in or reload_out as a reload
5794 register, we don't need to chose one. Otherwise, try even if it
5795 found one since we might save an insn if we find the value lying
5797 Try also when reload_in is a pseudo without a hard reg. */
5798 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5799 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5800 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5801 && GET_CODE (reload_in[r]) != MEM
5802 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5805 #if 0 /* No longer needed for correct operation.
5806 It might give better code, or might not; worth an experiment? */
5807 /* If this is an optional reload, we can't inherit from earlier insns
5808 until we are sure that any non-optional reloads have been allocated.
5809 The following code takes advantage of the fact that optional reloads
5810 are at the end of reload_order. */
5811 if (reload_optional[r] != 0)
5812 for (i = 0; i < j; i++)
5813 if ((reload_out[reload_order[i]] != 0
5814 || reload_in[reload_order[i]] != 0
5815 || reload_secondary_p[reload_order[i]])
5816 && ! reload_optional[reload_order[i]]
5817 && reload_reg_rtx[reload_order[i]] == 0)
5818 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5821 /* First see if this pseudo is already available as reloaded
5822 for a previous insn. We cannot try to inherit for reloads
5823 that are smaller than the maximum number of registers needed
5824 for groups unless the register we would allocate cannot be used
5827 We could check here to see if this is a secondary reload for
5828 an object that is already in a register of the desired class.
5829 This would avoid the need for the secondary reload register.
5830 But this is complex because we can't easily determine what
5831 objects might want to be loaded via this reload. So let a
5832 register be allocated here. In `emit_reload_insns' we suppress
5833 one of the loads in the case described above. */
5838 register int regno = -1;
5839 enum machine_mode mode;
5841 if (reload_in[r] == 0)
5843 else if (GET_CODE (reload_in[r]) == REG)
5845 regno = REGNO (reload_in[r]);
5846 mode = GET_MODE (reload_in[r]);
5848 else if (GET_CODE (reload_in_reg[r]) == REG)
5850 regno = REGNO (reload_in_reg[r]);
5851 mode = GET_MODE (reload_in_reg[r]);
5853 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5854 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5856 word = SUBREG_WORD (reload_in_reg[r]);
5857 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5858 if (regno < FIRST_PSEUDO_REGISTER)
5860 mode = GET_MODE (reload_in_reg[r]);
5863 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5864 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5865 || GET_CODE (reload_in_reg[r]) == POST_INC
5866 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5867 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5869 regno = REGNO (XEXP (reload_in_reg[r], 0));
5870 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5871 reload_out[r] = reload_in[r];
5875 /* This won't work, since REGNO can be a pseudo reg number.
5876 Also, it takes much more hair to keep track of all the things
5877 that can invalidate an inherited reload of part of a pseudoreg. */
5878 else if (GET_CODE (reload_in[r]) == SUBREG
5879 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5880 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5883 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5885 enum reg_class class = reload_reg_class[r], last_class;
5886 rtx last_reg = reg_last_reload_reg[regno];
5888 i = REGNO (last_reg) + word;
5889 last_class = REGNO_REG_CLASS (i);
5890 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5891 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5892 && reg_reloaded_contents[i] == regno
5893 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5894 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5895 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5896 /* Even if we can't use this register as a reload
5897 register, we might use it for reload_override_in,
5898 if copying it to the desired class is cheap
5900 || ((REGISTER_MOVE_COST (last_class, class)
5901 < MEMORY_MOVE_COST (mode, class, 1))
5902 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5903 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5907 #ifdef SECONDARY_MEMORY_NEEDED
5908 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5913 && (reload_nregs[r] == max_group_size
5914 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5916 && reload_reg_free_for_value_p (i, reload_opnum[r],
5917 reload_when_needed[r],
5921 /* If a group is needed, verify that all the subsequent
5922 registers still have their values intact. */
5924 = HARD_REGNO_NREGS (i, reload_mode[r]);
5927 for (k = 1; k < nr; k++)
5928 if (reg_reloaded_contents[i + k] != regno
5929 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5936 last_reg = (GET_MODE (last_reg) == mode
5937 ? last_reg : gen_rtx_REG (mode, i));
5939 /* We found a register that contains the
5940 value we need. If this register is the
5941 same as an `earlyclobber' operand of the
5942 current insn, just mark it as a place to
5943 reload from since we can't use it as the
5944 reload register itself. */
5946 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5947 if (reg_overlap_mentioned_for_reload_p
5948 (reg_last_reload_reg[regno],
5949 reload_earlyclobbers[i1]))
5952 if (i1 != n_earlyclobbers
5953 || ! (reload_reg_free_for_value_p
5954 (i, reload_opnum[r], reload_when_needed[r],
5955 reload_in[r], reload_out[r], r, 1))
5956 /* Don't use it if we'd clobber a pseudo reg. */
5957 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5959 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5960 /* Don't clobber the frame pointer. */
5961 || (i == HARD_FRAME_POINTER_REGNUM
5963 /* Don't really use the inherited spill reg
5964 if we need it wider than we've got it. */
5965 || (GET_MODE_SIZE (reload_mode[r])
5966 > GET_MODE_SIZE (mode))
5967 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5970 /* If find_reloads chose reload_out as reload
5971 register, stay with it - that leaves the
5972 inherited register for subsequent reloads. */
5973 || (reload_out[r] && reload_reg_rtx[r]
5974 && rtx_equal_p (reload_out[r],
5975 reload_reg_rtx[r])))
5977 reload_override_in[r] = last_reg;
5978 reload_inheritance_insn[r]
5979 = reg_reloaded_insn[i];
5984 /* We can use this as a reload reg. */
5985 /* Mark the register as in use for this part of
5987 mark_reload_reg_in_use (i,
5989 reload_when_needed[r],
5991 reload_reg_rtx[r] = last_reg;
5992 reload_inherited[r] = 1;
5993 reload_inheritance_insn[r]
5994 = reg_reloaded_insn[i];
5995 reload_spill_index[r] = i;
5996 for (k = 0; k < nr; k++)
5997 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6005 /* Here's another way to see if the value is already lying around. */
6007 && reload_in[r] != 0
6008 && ! reload_inherited[r]
6009 && reload_out[r] == 0
6010 && (CONSTANT_P (reload_in[r])
6011 || GET_CODE (reload_in[r]) == PLUS
6012 || GET_CODE (reload_in[r]) == REG
6013 || GET_CODE (reload_in[r]) == MEM)
6014 && (reload_nregs[r] == max_group_size
6015 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
6018 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
6019 -1, NULL_PTR, 0, reload_mode[r]);
6024 if (GET_CODE (equiv) == REG)
6025 regno = REGNO (equiv);
6026 else if (GET_CODE (equiv) == SUBREG)
6028 /* This must be a SUBREG of a hard register.
6029 Make a new REG since this might be used in an
6030 address and not all machines support SUBREGs
6032 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6033 equiv = gen_rtx_REG (reload_mode[r], regno);
6039 /* If we found a spill reg, reject it unless it is free
6040 and of the desired class. */
6042 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6043 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
6044 reload_when_needed[r],
6046 reload_out[r], r, 1))
6047 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6051 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
6054 /* We found a register that contains the value we need.
6055 If this register is the same as an `earlyclobber' operand
6056 of the current insn, just mark it as a place to reload from
6057 since we can't use it as the reload register itself. */
6060 for (i = 0; i < n_earlyclobbers; i++)
6061 if (reg_overlap_mentioned_for_reload_p (equiv,
6062 reload_earlyclobbers[i]))
6064 reload_override_in[r] = equiv;
6069 /* If the equiv register we have found is explicitly clobbered
6070 in the current insn, it depends on the reload type if we
6071 can use it, use it for reload_override_in, or not at all.
6072 In particular, we then can't use EQUIV for a
6073 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6075 if (equiv != 0 && regno_clobbered_p (regno, insn))
6077 switch (reload_when_needed[r])
6079 case RELOAD_FOR_OTHER_ADDRESS:
6080 case RELOAD_FOR_INPADDR_ADDRESS:
6081 case RELOAD_FOR_INPUT_ADDRESS:
6082 case RELOAD_FOR_OPADDR_ADDR:
6085 case RELOAD_FOR_INPUT:
6086 case RELOAD_FOR_OPERAND_ADDRESS:
6087 reload_override_in[r] = equiv;
6095 /* If we found an equivalent reg, say no code need be generated
6096 to load it, and use it as our reload reg. */
6097 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6099 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6101 reload_reg_rtx[r] = equiv;
6102 reload_inherited[r] = 1;
6104 /* If reg_reloaded_valid is not set for this register,
6105 there might be a stale spill_reg_store lying around.
6106 We must clear it, since otherwise emit_reload_insns
6107 might delete the store. */
6108 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6109 spill_reg_store[regno] = NULL_RTX;
6110 /* If any of the hard registers in EQUIV are spill
6111 registers, mark them as in use for this insn. */
6112 for (k = 0; k < nr; k++)
6114 i = spill_reg_order[regno + k];
6117 mark_reload_reg_in_use (regno, reload_opnum[r],
6118 reload_when_needed[r],
6120 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6127 /* If we found a register to use already, or if this is an optional
6128 reload, we are done. */
6129 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6132 #if 0 /* No longer needed for correct operation. Might or might not
6133 give better code on the average. Want to experiment? */
6135 /* See if there is a later reload that has a class different from our
6136 class that intersects our class or that requires less register
6137 than our reload. If so, we must allocate a register to this
6138 reload now, since that reload might inherit a previous reload
6139 and take the only available register in our class. Don't do this
6140 for optional reloads since they will force all previous reloads
6141 to be allocated. Also don't do this for reloads that have been
6144 for (i = j + 1; i < n_reloads; i++)
6146 int s = reload_order[i];
6148 if ((reload_in[s] == 0 && reload_out[s] == 0
6149 && ! reload_secondary_p[s])
6150 || reload_optional[s])
6153 if ((reload_reg_class[s] != reload_reg_class[r]
6154 && reg_classes_intersect_p (reload_reg_class[r],
6155 reload_reg_class[s]))
6156 || reload_nregs[s] < reload_nregs[r])
6163 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6167 /* Now allocate reload registers for anything non-optional that
6168 didn't get one yet. */
6169 for (j = 0; j < n_reloads; j++)
6171 register int r = reload_order[j];
6173 /* Ignore reloads that got marked inoperative. */
6174 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6177 /* Skip reloads that already have a register allocated or are
6179 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6182 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6186 /* If that loop got all the way, we have won. */
6190 /* Loop around and try without any inheritance. */
6191 /* First undo everything done by the failed attempt
6192 to allocate with inheritance. */
6193 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6194 sizeof reload_reg_rtx);
6195 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6196 sizeof reload_inherited);
6197 bcopy ((char *) save_reload_inheritance_insn,
6198 (char *) reload_inheritance_insn,
6199 sizeof reload_inheritance_insn);
6200 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6201 sizeof reload_override_in);
6202 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6203 sizeof reload_spill_index);
6204 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6205 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6206 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6207 save_reload_reg_used_in_op_addr);
6208 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6209 save_reload_reg_used_in_op_addr_reload);
6210 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6211 save_reload_reg_used_in_insn);
6212 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6213 save_reload_reg_used_in_other_addr);
6215 for (i = 0; i < reload_n_operands; i++)
6217 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6218 save_reload_reg_used_in_input[i]);
6219 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6220 save_reload_reg_used_in_output[i]);
6221 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6222 save_reload_reg_used_in_input_addr[i]);
6223 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6224 save_reload_reg_used_in_inpaddr_addr[i]);
6225 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6226 save_reload_reg_used_in_output_addr[i]);
6227 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6228 save_reload_reg_used_in_outaddr_addr[i]);
6232 /* If we thought we could inherit a reload, because it seemed that
6233 nothing else wanted the same reload register earlier in the insn,
6234 verify that assumption, now that all reloads have been assigned.
6235 Likewise for reloads where reload_override_in has been set. */
6237 /* If doing expensive optimizations, do one preliminary pass that doesn't
6238 cancel any inheritance, but removes reloads that have been needed only
6239 for reloads that we know can be inherited. */
6240 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6242 for (j = 0; j < n_reloads; j++)
6244 register int r = reload_order[j];
6246 if (reload_inherited[r] && reload_reg_rtx[r])
6247 check_reg = reload_reg_rtx[r];
6248 else if (reload_override_in[r]
6249 && (GET_CODE (reload_override_in[r]) == REG
6250 || GET_CODE (reload_override_in[r]) == SUBREG))
6251 check_reg = reload_override_in[r];
6254 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6256 reload_when_needed[r],
6258 (reload_inherited[r]
6259 ? reload_out[r] : const0_rtx),
6264 reload_inherited[r] = 0;
6265 reload_override_in[r] = 0;
6267 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6268 reload_override_in, then we do not need its related
6269 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6270 likewise for other reload types.
6271 We handle this by removing a reload when its only replacement
6272 is mentioned in reload_in of the reload we are going to inherit.
6273 A special case are auto_inc expressions; even if the input is
6274 inherited, we still need the address for the output. We can
6275 recognize them because they have RELOAD_OUT set but not
6277 If we suceeded removing some reload and we are doing a preliminary
6278 pass just to remove such reloads, make another pass, since the
6279 removal of one reload might allow us to inherit another one. */
6280 else if ((! reload_out[r] || reload_out_reg[r])
6281 && remove_address_replacements (reload_in[r]) && pass)
6286 /* Now that reload_override_in is known valid,
6287 actually override reload_in. */
6288 for (j = 0; j < n_reloads; j++)
6289 if (reload_override_in[j])
6290 reload_in[j] = reload_override_in[j];
6292 /* If this reload won't be done because it has been cancelled or is
6293 optional and not inherited, clear reload_reg_rtx so other
6294 routines (such as subst_reloads) don't get confused. */
6295 for (j = 0; j < n_reloads; j++)
6296 if (reload_reg_rtx[j] != 0
6297 && ((reload_optional[j] && ! reload_inherited[j])
6298 || (reload_in[j] == 0 && reload_out[j] == 0
6299 && ! reload_secondary_p[j])))
6301 int regno = true_regnum (reload_reg_rtx[j]);
6303 if (spill_reg_order[regno] >= 0)
6304 clear_reload_reg_in_use (regno, reload_opnum[j],
6305 reload_when_needed[j], reload_mode[j]);
6306 reload_reg_rtx[j] = 0;
6309 /* Record which pseudos and which spill regs have output reloads. */
6310 for (j = 0; j < n_reloads; j++)
6312 register int r = reload_order[j];
6314 i = reload_spill_index[r];
6316 /* I is nonneg if this reload uses a register.
6317 If reload_reg_rtx[r] is 0, this is an optional reload
6318 that we opted to ignore. */
6319 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6320 && reload_reg_rtx[r] != 0)
6322 register int nregno = REGNO (reload_out_reg[r]);
6325 if (nregno < FIRST_PSEUDO_REGISTER)
6326 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6329 reg_has_output_reload[nregno + nr] = 1;
6333 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6335 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6338 if (reload_when_needed[r] != RELOAD_OTHER
6339 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6340 && reload_when_needed[r] != RELOAD_FOR_INSN)
6346 /* Deallocate the reload register for reload R. This is called from
6347 remove_address_replacements. */
6349 deallocate_reload_reg (r)
6354 if (! reload_reg_rtx[r])
6356 regno = true_regnum (reload_reg_rtx[r]);
6357 reload_reg_rtx[r] = 0;
6358 if (spill_reg_order[regno] >= 0)
6359 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6361 reload_spill_index[r] = -1;
6364 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6365 reloads of the same item for fear that we might not have enough reload
6366 registers. However, normally they will get the same reload register
6367 and hence actually need not be loaded twice.
6369 Here we check for the most common case of this phenomenon: when we have
6370 a number of reloads for the same object, each of which were allocated
6371 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6372 reload, and is not modified in the insn itself. If we find such,
6373 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6374 This will not increase the number of spill registers needed and will
6375 prevent redundant code. */
6378 merge_assigned_reloads (insn)
6383 /* Scan all the reloads looking for ones that only load values and
6384 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6385 assigned and not modified by INSN. */
6387 for (i = 0; i < n_reloads; i++)
6389 int conflicting_input = 0;
6390 int max_input_address_opnum = -1;
6391 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6393 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6394 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6395 || reg_set_p (reload_reg_rtx[i], insn))
6398 /* Look at all other reloads. Ensure that the only use of this
6399 reload_reg_rtx is in a reload that just loads the same value
6400 as we do. Note that any secondary reloads must be of the identical
6401 class since the values, modes, and result registers are the
6402 same, so we need not do anything with any secondary reloads. */
6404 for (j = 0; j < n_reloads; j++)
6406 if (i == j || reload_reg_rtx[j] == 0
6407 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6411 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6412 && reload_opnum[j] > max_input_address_opnum)
6413 max_input_address_opnum = reload_opnum[j];
6415 /* If the reload regs aren't exactly the same (e.g, different modes)
6416 or if the values are different, we can't merge this reload.
6417 But if it is an input reload, we might still merge
6418 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6420 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6421 || reload_out[j] != 0 || reload_in[j] == 0
6422 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6424 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6425 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6426 || reload_opnum[i] > reload_opnum[j])
6427 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6429 conflicting_input = 1;
6430 if (min_conflicting_input_opnum > reload_opnum[j])
6431 min_conflicting_input_opnum = reload_opnum[j];
6435 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6436 we, in fact, found any matching reloads. */
6439 && max_input_address_opnum <= min_conflicting_input_opnum)
6441 for (j = 0; j < n_reloads; j++)
6442 if (i != j && reload_reg_rtx[j] != 0
6443 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6444 && (! conflicting_input
6445 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6446 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6448 reload_when_needed[i] = RELOAD_OTHER;
6450 reload_spill_index[j] = -1;
6451 transfer_replacements (i, j);
6454 /* If this is now RELOAD_OTHER, look for any reloads that load
6455 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6456 if they were for inputs, RELOAD_OTHER for outputs. Note that
6457 this test is equivalent to looking for reloads for this operand
6460 if (reload_when_needed[i] == RELOAD_OTHER)
6461 for (j = 0; j < n_reloads; j++)
6462 if (reload_in[j] != 0
6463 && reload_when_needed[i] != RELOAD_OTHER
6464 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6466 reload_when_needed[j]
6467 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6468 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6469 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6475 /* Output insns to reload values in and out of the chosen reload regs. */
6478 emit_reload_insns (chain)
6479 struct insn_chain *chain;
6481 rtx insn = chain->insn;
6484 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6485 rtx other_input_address_reload_insns = 0;
6486 rtx other_input_reload_insns = 0;
6487 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6488 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6489 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6490 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6491 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6492 rtx operand_reload_insns = 0;
6493 rtx other_operand_reload_insns = 0;
6494 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6495 rtx following_insn = NEXT_INSN (insn);
6496 rtx before_insn = PREV_INSN (insn);
6498 /* Values to be put in spill_reg_store are put here first. */
6499 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6500 HARD_REG_SET reg_reloaded_died;
6502 CLEAR_HARD_REG_SET (reg_reloaded_died);
6504 for (j = 0; j < reload_n_operands; j++)
6505 input_reload_insns[j] = input_address_reload_insns[j]
6506 = inpaddr_address_reload_insns[j]
6507 = output_reload_insns[j] = output_address_reload_insns[j]
6508 = outaddr_address_reload_insns[j]
6509 = other_output_reload_insns[j] = 0;
6511 /* Now output the instructions to copy the data into and out of the
6512 reload registers. Do these in the order that the reloads were reported,
6513 since reloads of base and index registers precede reloads of operands
6514 and the operands may need the base and index registers reloaded. */
6516 for (j = 0; j < n_reloads; j++)
6519 rtx oldequiv_reg = 0;
6520 rtx this_reload_insn = 0;
6521 int expect_occurrences = 1;
6523 if (reload_reg_rtx[j]
6524 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6525 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6527 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6528 ? reload_in_reg[j] : reload_in[j]);
6531 /* AUTO_INC reloads need to be handled even if inherited. We got an
6532 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6533 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6534 && ! rtx_equal_p (reload_reg_rtx[j], old)
6535 && reload_reg_rtx[j] != 0)
6537 register rtx reloadreg = reload_reg_rtx[j];
6539 enum machine_mode mode;
6542 /* Determine the mode to reload in.
6543 This is very tricky because we have three to choose from.
6544 There is the mode the insn operand wants (reload_inmode[J]).
6545 There is the mode of the reload register RELOADREG.
6546 There is the intrinsic mode of the operand, which we could find
6547 by stripping some SUBREGs.
6548 It turns out that RELOADREG's mode is irrelevant:
6549 we can change that arbitrarily.
6551 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6552 then the reload reg may not support QImode moves, so use SImode.
6553 If foo is in memory due to spilling a pseudo reg, this is safe,
6554 because the QImode value is in the least significant part of a
6555 slot big enough for a SImode. If foo is some other sort of
6556 memory reference, then it is impossible to reload this case,
6557 so previous passes had better make sure this never happens.
6559 Then consider a one-word union which has SImode and one of its
6560 members is a float, being fetched as (SUBREG:SF union:SI).
6561 We must fetch that as SFmode because we could be loading into
6562 a float-only register. In this case OLD's mode is correct.
6564 Consider an immediate integer: it has VOIDmode. Here we need
6565 to get a mode from something else.
6567 In some cases, there is a fourth mode, the operand's
6568 containing mode. If the insn specifies a containing mode for
6569 this operand, it overrides all others.
6571 I am not sure whether the algorithm here is always right,
6572 but it does the right things in those cases. */
6574 mode = GET_MODE (old);
6575 if (mode == VOIDmode)
6576 mode = reload_inmode[j];
6578 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6579 /* If we need a secondary register for this operation, see if
6580 the value is already in a register in that class. Don't
6581 do this if the secondary register will be used as a scratch
6584 if (reload_secondary_in_reload[j] >= 0
6585 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6588 = find_equiv_reg (old, insn,
6589 reload_reg_class[reload_secondary_in_reload[j]],
6590 -1, NULL_PTR, 0, mode);
6593 /* If reloading from memory, see if there is a register
6594 that already holds the same value. If so, reload from there.
6595 We can pass 0 as the reload_reg_p argument because
6596 any other reload has either already been emitted,
6597 in which case find_equiv_reg will see the reload-insn,
6598 or has yet to be emitted, in which case it doesn't matter
6599 because we will use this equiv reg right away. */
6601 if (oldequiv == 0 && optimize
6602 && (GET_CODE (old) == MEM
6603 || (GET_CODE (old) == REG
6604 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6605 && reg_renumber[REGNO (old)] < 0)))
6606 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6607 -1, NULL_PTR, 0, mode);
6611 int regno = true_regnum (oldequiv);
6613 /* Don't use OLDEQUIV if any other reload changes it at an
6614 earlier stage of this insn or at this stage. */
6615 if (! reload_reg_free_for_value_p (regno, reload_opnum[j],
6616 reload_when_needed[j],
6617 reload_in[j], const0_rtx, j,
6621 /* If it is no cheaper to copy from OLDEQUIV into the
6622 reload register than it would be to move from memory,
6623 don't use it. Likewise, if we need a secondary register
6627 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6628 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6629 reload_reg_class[j])
6630 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6631 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6632 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6636 #ifdef SECONDARY_MEMORY_NEEDED
6637 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6638 reload_reg_class[j],
6645 /* delete_output_reload is only invoked properly if old contains
6646 the original pseudo register. Since this is replaced with a
6647 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6648 find the pseudo in RELOAD_IN_REG. */
6650 && reload_override_in[j]
6651 && GET_CODE (reload_in_reg[j]) == REG)
6654 old = reload_in_reg[j];
6658 else if (GET_CODE (oldequiv) == REG)
6659 oldequiv_reg = oldequiv;
6660 else if (GET_CODE (oldequiv) == SUBREG)
6661 oldequiv_reg = SUBREG_REG (oldequiv);
6663 /* If we are reloading from a register that was recently stored in
6664 with an output-reload, see if we can prove there was
6665 actually no need to store the old value in it. */
6667 if (optimize && GET_CODE (oldequiv) == REG
6668 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6669 && spill_reg_store[REGNO (oldequiv)]
6670 && GET_CODE (old) == REG
6671 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6672 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6673 reload_out_reg[j])))
6674 delete_output_reload (insn, j, REGNO (oldequiv));
6676 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6677 then load RELOADREG from OLDEQUIV. Note that we cannot use
6678 gen_lowpart_common since it can do the wrong thing when
6679 RELOADREG has a multi-word mode. Note that RELOADREG
6680 must always be a REG here. */
6682 if (GET_MODE (reloadreg) != mode)
6683 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6684 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6685 oldequiv = SUBREG_REG (oldequiv);
6686 if (GET_MODE (oldequiv) != VOIDmode
6687 && mode != GET_MODE (oldequiv))
6688 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6690 /* Switch to the right place to emit the reload insns. */
6691 switch (reload_when_needed[j])
6694 where = &other_input_reload_insns;
6696 case RELOAD_FOR_INPUT:
6697 where = &input_reload_insns[reload_opnum[j]];
6699 case RELOAD_FOR_INPUT_ADDRESS:
6700 where = &input_address_reload_insns[reload_opnum[j]];
6702 case RELOAD_FOR_INPADDR_ADDRESS:
6703 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6705 case RELOAD_FOR_OUTPUT_ADDRESS:
6706 where = &output_address_reload_insns[reload_opnum[j]];
6708 case RELOAD_FOR_OUTADDR_ADDRESS:
6709 where = &outaddr_address_reload_insns[reload_opnum[j]];
6711 case RELOAD_FOR_OPERAND_ADDRESS:
6712 where = &operand_reload_insns;
6714 case RELOAD_FOR_OPADDR_ADDR:
6715 where = &other_operand_reload_insns;
6717 case RELOAD_FOR_OTHER_ADDRESS:
6718 where = &other_input_address_reload_insns;
6724 push_to_sequence (*where);
6727 /* Auto-increment addresses must be reloaded in a special way. */
6728 if (reload_out[j] && ! reload_out_reg[j])
6730 /* We are not going to bother supporting the case where a
6731 incremented register can't be copied directly from
6732 OLDEQUIV since this seems highly unlikely. */
6733 if (reload_secondary_in_reload[j] >= 0)
6736 if (reload_inherited[j])
6737 oldequiv = reloadreg;
6739 old = XEXP (reload_in_reg[j], 0);
6741 if (optimize && GET_CODE (oldequiv) == REG
6742 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6743 && spill_reg_store[REGNO (oldequiv)]
6744 && GET_CODE (old) == REG
6745 && (dead_or_set_p (insn,
6746 spill_reg_stored_to[REGNO (oldequiv)])
6747 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6749 delete_output_reload (insn, j, REGNO (oldequiv));
6751 /* Prevent normal processing of this reload. */
6753 /* Output a special code sequence for this case. */
6754 new_spill_reg_store[REGNO (reloadreg)]
6755 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6759 /* If we are reloading a pseudo-register that was set by the previous
6760 insn, see if we can get rid of that pseudo-register entirely
6761 by redirecting the previous insn into our reload register. */
6763 else if (optimize && GET_CODE (old) == REG
6764 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6765 && dead_or_set_p (insn, old)
6766 /* This is unsafe if some other reload
6767 uses the same reg first. */
6768 && reload_reg_free_for_value_p (REGNO (reloadreg),
6770 reload_when_needed[j],
6774 rtx temp = PREV_INSN (insn);
6775 while (temp && GET_CODE (temp) == NOTE)
6776 temp = PREV_INSN (temp);
6778 && GET_CODE (temp) == INSN
6779 && GET_CODE (PATTERN (temp)) == SET
6780 && SET_DEST (PATTERN (temp)) == old
6781 /* Make sure we can access insn_operand_constraint. */
6782 && asm_noperands (PATTERN (temp)) < 0
6783 /* This is unsafe if prev insn rejects our reload reg. */
6784 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6786 /* This is unsafe if operand occurs more than once in current
6787 insn. Perhaps some occurrences aren't reloaded. */
6788 && count_occurrences (PATTERN (insn), old) == 1
6789 /* Don't risk splitting a matching pair of operands. */
6790 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6792 /* Store into the reload register instead of the pseudo. */
6793 SET_DEST (PATTERN (temp)) = reloadreg;
6795 /* If the previous insn is an output reload, the source is
6796 a reload register, and its spill_reg_store entry will
6797 contain the previous destination. This is now
6799 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6800 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6802 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6803 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6806 /* If these are the only uses of the pseudo reg,
6807 pretend for GDB it lives in the reload reg we used. */
6808 if (REG_N_DEATHS (REGNO (old)) == 1
6809 && REG_N_SETS (REGNO (old)) == 1)
6811 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6812 alter_reg (REGNO (old), -1);
6818 /* We can't do that, so output an insn to load RELOADREG. */
6822 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6823 rtx second_reload_reg = 0;
6824 enum insn_code icode;
6826 /* If we have a secondary reload, pick up the secondary register
6827 and icode, if any. If OLDEQUIV and OLD are different or
6828 if this is an in-out reload, recompute whether or not we
6829 still need a secondary register and what the icode should
6830 be. If we still need a secondary register and the class or
6831 icode is different, go back to reloading from OLD if using
6832 OLDEQUIV means that we got the wrong type of register. We
6833 cannot have different class or icode due to an in-out reload
6834 because we don't make such reloads when both the input and
6835 output need secondary reload registers. */
6837 if (reload_secondary_in_reload[j] >= 0)
6839 int secondary_reload = reload_secondary_in_reload[j];
6840 rtx real_oldequiv = oldequiv;
6843 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6844 and similarly for OLD.
6845 See comments in get_secondary_reload in reload.c. */
6846 /* If it is a pseudo that cannot be replaced with its
6847 equivalent MEM, we must fall back to reload_in, which
6848 will have all the necessary substitutions registered.
6849 Likewise for a pseudo that can't be replaced with its
6850 equivalent constant. */
6852 if (GET_CODE (oldequiv) == REG
6853 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6854 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6855 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6857 if (! reg_equiv_mem[REGNO (oldequiv)]
6858 || num_not_at_initial_offset)
6859 real_oldequiv = reload_in[j];
6861 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6864 if (GET_CODE (old) == REG
6865 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6866 && (reg_equiv_memory_loc[REGNO (old)] != 0
6867 || reg_equiv_constant[REGNO (old)] != 0))
6869 if (! reg_equiv_mem[REGNO (old)]
6870 || num_not_at_initial_offset)
6871 real_old = reload_in[j];
6873 real_old = reg_equiv_mem[REGNO (old)];
6876 second_reload_reg = reload_reg_rtx[secondary_reload];
6877 icode = reload_secondary_in_icode[j];
6879 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6880 || (reload_in[j] != 0 && reload_out[j] != 0))
6882 enum reg_class new_class
6883 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6884 mode, real_oldequiv);
6886 if (new_class == NO_REGS)
6887 second_reload_reg = 0;
6890 enum insn_code new_icode;
6891 enum machine_mode new_mode;
6893 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6894 REGNO (second_reload_reg)))
6895 oldequiv = old, real_oldequiv = real_old;
6898 new_icode = reload_in_optab[(int) mode];
6899 if (new_icode != CODE_FOR_nothing
6900 && ((insn_operand_predicate[(int) new_icode][0]
6901 && ! ((*insn_operand_predicate[(int) new_icode][0])
6903 || (insn_operand_predicate[(int) new_icode][1]
6904 && ! ((*insn_operand_predicate[(int) new_icode][1])
6905 (real_oldequiv, mode)))))
6906 new_icode = CODE_FOR_nothing;
6908 if (new_icode == CODE_FOR_nothing)
6911 new_mode = insn_operand_mode[(int) new_icode][2];
6913 if (GET_MODE (second_reload_reg) != new_mode)
6915 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6917 oldequiv = old, real_oldequiv = real_old;
6920 = gen_rtx_REG (new_mode,
6921 REGNO (second_reload_reg));
6927 /* If we still need a secondary reload register, check
6928 to see if it is being used as a scratch or intermediate
6929 register and generate code appropriately. If we need
6930 a scratch register, use REAL_OLDEQUIV since the form of
6931 the insn may depend on the actual address if it is
6934 if (second_reload_reg)
6936 if (icode != CODE_FOR_nothing)
6938 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6939 second_reload_reg));
6944 /* See if we need a scratch register to load the
6945 intermediate register (a tertiary reload). */
6946 enum insn_code tertiary_icode
6947 = reload_secondary_in_icode[secondary_reload];
6949 if (tertiary_icode != CODE_FOR_nothing)
6951 rtx third_reload_reg
6952 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6954 emit_insn ((GEN_FCN (tertiary_icode)
6955 (second_reload_reg, real_oldequiv,
6956 third_reload_reg)));
6959 gen_reload (second_reload_reg, real_oldequiv,
6961 reload_when_needed[j]);
6963 oldequiv = second_reload_reg;
6969 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6971 rtx real_oldequiv = oldequiv;
6973 if ((GET_CODE (oldequiv) == REG
6974 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6975 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6976 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6977 || (GET_CODE (oldequiv) == SUBREG
6978 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6979 && (REGNO (SUBREG_REG (oldequiv))
6980 >= FIRST_PSEUDO_REGISTER)
6981 && ((reg_equiv_memory_loc
6982 [REGNO (SUBREG_REG (oldequiv))] != 0)
6983 || (reg_equiv_constant
6984 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6985 real_oldequiv = reload_in[j];
6986 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6987 reload_when_needed[j]);
6992 this_reload_insn = get_last_insn ();
6993 /* End this sequence. */
6994 *where = get_insns ();
6997 /* Update reload_override_in so that delete_address_reloads_1
6998 can see the actual register usage. */
7000 reload_override_in[j] = oldequiv;
7003 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7004 e.g. inheriting a SImode output reload for
7005 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7006 if (optimize && reload_inherited[j] && reload_in[j]
7007 && GET_CODE (reload_in[j]) == MEM
7008 && GET_CODE (reload_in_reg[j]) == MEM
7009 && reload_spill_index[j] >= 0
7010 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7013 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
7015 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7018 /* If we are reloading a register that was recently stored in with an
7019 output-reload, see if we can prove there was
7020 actually no need to store the old value in it. */
7023 && (reload_inherited[j] || reload_override_in[j])
7024 && reload_reg_rtx[j]
7025 && GET_CODE (reload_reg_rtx[j]) == REG
7026 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
7028 /* There doesn't seem to be any reason to restrict this to pseudos
7029 and doing so loses in the case where we are copying from a
7030 register of the wrong class. */
7031 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7032 >= FIRST_PSEUDO_REGISTER
7034 /* The insn might have already some references to stackslots
7035 replaced by MEMs, while reload_out_reg still names the
7037 && (dead_or_set_p (insn,
7038 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7039 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
7040 reload_out_reg[j])))
7041 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
7043 /* Input-reloading is done. Now do output-reloading,
7044 storing the value from the reload-register after the main insn
7045 if reload_out[j] is nonzero.
7047 ??? At some point we need to support handling output reloads of
7048 JUMP_INSNs or insns that set cc0. */
7050 /* If this is an output reload that stores something that is
7051 not loaded in this same reload, see if we can eliminate a previous
7054 rtx pseudo = reload_out_reg[j];
7057 && GET_CODE (pseudo) == REG
7058 && ! rtx_equal_p (reload_in_reg[j], pseudo)
7059 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7060 && reg_last_reload_reg[REGNO (pseudo)])
7062 int pseudo_no = REGNO (pseudo);
7063 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7065 /* We don't need to test full validity of last_regno for
7066 inherit here; we only want to know if the store actually
7067 matches the pseudo. */
7068 if (reg_reloaded_contents[last_regno] == pseudo_no
7069 && spill_reg_store[last_regno]
7070 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7071 delete_output_reload (insn, j, last_regno);
7075 old = reload_out_reg[j];
7077 && reload_reg_rtx[j] != old
7078 && reload_reg_rtx[j] != 0)
7080 register rtx reloadreg = reload_reg_rtx[j];
7081 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7082 register rtx second_reloadreg = 0;
7085 enum machine_mode mode;
7088 /* An output operand that dies right away does need a reload,
7089 but need not be copied from it. Show the new location in the
7091 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7092 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7094 XEXP (note, 0) = reload_reg_rtx[j];
7097 /* Likewise for a SUBREG of an operand that dies. */
7098 else if (GET_CODE (old) == SUBREG
7099 && GET_CODE (SUBREG_REG (old)) == REG
7100 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7103 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7107 else if (GET_CODE (old) == SCRATCH)
7108 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7109 but we don't want to make an output reload. */
7113 /* Strip off of OLD any size-increasing SUBREGs such as
7114 (SUBREG:SI foo:QI 0). */
7116 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7117 && (GET_MODE_SIZE (GET_MODE (old))
7118 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7119 old = SUBREG_REG (old);
7122 /* If is a JUMP_INSN, we can't support output reloads yet. */
7123 if (GET_CODE (insn) == JUMP_INSN)
7126 if (reload_when_needed[j] == RELOAD_OTHER)
7129 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7131 old = reload_out[j];
7133 /* Determine the mode to reload in.
7134 See comments above (for input reloading). */
7136 mode = GET_MODE (old);
7137 if (mode == VOIDmode)
7139 /* VOIDmode should never happen for an output. */
7140 if (asm_noperands (PATTERN (insn)) < 0)
7141 /* It's the compiler's fault. */
7142 fatal_insn ("VOIDmode on an output", insn);
7143 error_for_asm (insn, "output operand is constant in `asm'");
7144 /* Prevent crash--use something we know is valid. */
7146 old = gen_rtx_REG (mode, REGNO (reloadreg));
7149 if (GET_MODE (reloadreg) != mode)
7150 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7152 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7154 /* If we need two reload regs, set RELOADREG to the intermediate
7155 one, since it will be stored into OLD. We might need a secondary
7156 register only for an input reload, so check again here. */
7158 if (reload_secondary_out_reload[j] >= 0)
7162 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7163 && reg_equiv_mem[REGNO (old)] != 0)
7164 real_old = reg_equiv_mem[REGNO (old)];
7166 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7170 second_reloadreg = reloadreg;
7171 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7173 /* See if RELOADREG is to be used as a scratch register
7174 or as an intermediate register. */
7175 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7177 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7178 (real_old, second_reloadreg, reloadreg)));
7183 /* See if we need both a scratch and intermediate reload
7186 int secondary_reload = reload_secondary_out_reload[j];
7187 enum insn_code tertiary_icode
7188 = reload_secondary_out_icode[secondary_reload];
7190 if (GET_MODE (reloadreg) != mode)
7191 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7193 if (tertiary_icode != CODE_FOR_nothing)
7196 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7199 /* Copy primary reload reg to secondary reload reg.
7200 (Note that these have been swapped above, then
7201 secondary reload reg to OLD using our insn. */
7203 /* If REAL_OLD is a paradoxical SUBREG, remove it
7204 and try to put the opposite SUBREG on
7206 if (GET_CODE (real_old) == SUBREG
7207 && (GET_MODE_SIZE (GET_MODE (real_old))
7208 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7209 && 0 != (tem = gen_lowpart_common
7210 (GET_MODE (SUBREG_REG (real_old)),
7212 real_old = SUBREG_REG (real_old), reloadreg = tem;
7214 gen_reload (reloadreg, second_reloadreg,
7215 reload_opnum[j], reload_when_needed[j]);
7216 emit_insn ((GEN_FCN (tertiary_icode)
7217 (real_old, reloadreg, third_reloadreg)));
7222 /* Copy between the reload regs here and then to
7225 gen_reload (reloadreg, second_reloadreg,
7226 reload_opnum[j], reload_when_needed[j]);
7232 /* Output the last reload insn. */
7237 /* Don't output the last reload if OLD is not the dest of
7238 INSN and is in the src and is clobbered by INSN. */
7239 if (! flag_expensive_optimizations
7240 || GET_CODE (old) != REG
7241 || !(set = single_set (insn))
7242 || rtx_equal_p (old, SET_DEST (set))
7243 || !reg_mentioned_p (old, SET_SRC (set))
7244 || !regno_clobbered_p (REGNO (old), insn))
7245 gen_reload (old, reloadreg, reload_opnum[j],
7246 reload_when_needed[j]);
7249 /* Look at all insns we emitted, just to be safe. */
7250 for (p = get_insns (); p; p = NEXT_INSN (p))
7251 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7253 rtx pat = PATTERN (p);
7255 /* If this output reload doesn't come from a spill reg,
7256 clear any memory of reloaded copies of the pseudo reg.
7257 If this output reload comes from a spill reg,
7258 reg_has_output_reload will make this do nothing. */
7259 note_stores (pat, forget_old_reloads_1);
7261 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7263 rtx set = single_set (insn);
7264 if (reload_spill_index[j] < 0
7266 && SET_SRC (set) == reload_reg_rtx[j])
7268 int src = REGNO (SET_SRC (set));
7270 reload_spill_index[j] = src;
7271 SET_HARD_REG_BIT (reg_is_output_reload, src);
7272 if (find_regno_note (insn, REG_DEAD, src))
7273 SET_HARD_REG_BIT (reg_reloaded_died, src);
7275 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7277 int s = reload_secondary_out_reload[j];
7278 set = single_set (p);
7279 /* If this reload copies only to the secondary reload
7280 register, the secondary reload does the actual
7282 if (s >= 0 && set == NULL_RTX)
7283 ; /* We can't tell what function the secondary reload
7284 has and where the actual store to the pseudo is
7285 made; leave new_spill_reg_store alone. */
7287 && SET_SRC (set) == reload_reg_rtx[j]
7288 && SET_DEST (set) == reload_reg_rtx[s])
7290 /* Usually the next instruction will be the
7291 secondary reload insn; if we can confirm
7292 that it is, setting new_spill_reg_store to
7293 that insn will allow an extra optimization. */
7294 rtx s_reg = reload_reg_rtx[s];
7295 rtx next = NEXT_INSN (p);
7296 reload_out[s] = reload_out[j];
7297 reload_out_reg[s] = reload_out_reg[j];
7298 set = single_set (next);
7299 if (set && SET_SRC (set) == s_reg
7300 && ! new_spill_reg_store[REGNO (s_reg)])
7302 SET_HARD_REG_BIT (reg_is_output_reload,
7304 new_spill_reg_store[REGNO (s_reg)] = next;
7308 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7313 if (reload_when_needed[j] == RELOAD_OTHER)
7315 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7316 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7319 output_reload_insns[reload_opnum[j]] = get_insns ();
7325 /* Now write all the insns we made for reloads in the order expected by
7326 the allocation functions. Prior to the insn being reloaded, we write
7327 the following reloads:
7329 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7331 RELOAD_OTHER reloads.
7333 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7334 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7335 RELOAD_FOR_INPUT reload for the operand.
7337 RELOAD_FOR_OPADDR_ADDRS reloads.
7339 RELOAD_FOR_OPERAND_ADDRESS reloads.
7341 After the insn being reloaded, we write the following:
7343 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7344 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7345 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7346 reloads for the operand. The RELOAD_OTHER output reloads are
7347 output in descending order by reload number. */
7349 emit_insns_before (other_input_address_reload_insns, insn);
7350 emit_insns_before (other_input_reload_insns, insn);
7352 for (j = 0; j < reload_n_operands; j++)
7354 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7355 emit_insns_before (input_address_reload_insns[j], insn);
7356 emit_insns_before (input_reload_insns[j], insn);
7359 emit_insns_before (other_operand_reload_insns, insn);
7360 emit_insns_before (operand_reload_insns, insn);
7362 for (j = 0; j < reload_n_operands; j++)
7364 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7365 emit_insns_before (output_address_reload_insns[j], following_insn);
7366 emit_insns_before (output_reload_insns[j], following_insn);
7367 emit_insns_before (other_output_reload_insns[j], following_insn);
7370 /* Keep basic block info up to date. */
7373 if (BLOCK_HEAD (chain->block) == insn)
7374 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7375 if (BLOCK_END (chain->block) == insn)
7376 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7379 /* For all the spill regs newly reloaded in this instruction,
7380 record what they were reloaded from, so subsequent instructions
7381 can inherit the reloads.
7383 Update spill_reg_store for the reloads of this insn.
7384 Copy the elements that were updated in the loop above. */
7386 for (j = 0; j < n_reloads; j++)
7388 register int r = reload_order[j];
7389 register int i = reload_spill_index[r];
7391 /* If this is a non-inherited input reload from a pseudo, we must
7392 clear any memory of a previous store to the same pseudo. Only do
7393 something if there will not be an output reload for the pseudo
7395 if (reload_in_reg[r] != 0
7396 && ! (reload_inherited[r] || reload_override_in[r]))
7398 rtx reg = reload_in_reg[r];
7400 if (GET_CODE (reg) == SUBREG)
7401 reg = SUBREG_REG (reg);
7403 if (GET_CODE (reg) == REG
7404 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7405 && ! reg_has_output_reload[REGNO (reg)])
7407 int nregno = REGNO (reg);
7409 if (reg_last_reload_reg[nregno])
7411 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7413 if (reg_reloaded_contents[last_regno] == nregno)
7414 spill_reg_store[last_regno] = 0;
7419 /* I is nonneg if this reload used a register.
7420 If reload_reg_rtx[r] is 0, this is an optional reload
7421 that we opted to ignore. */
7423 if (i >= 0 && reload_reg_rtx[r] != 0)
7426 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7428 int part_reaches_end = 0;
7429 int all_reaches_end = 1;
7431 /* For a multi register reload, we need to check if all or part
7432 of the value lives to the end. */
7433 for (k = 0; k < nr; k++)
7435 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7436 reload_when_needed[r]))
7437 part_reaches_end = 1;
7439 all_reaches_end = 0;
7442 /* Ignore reloads that don't reach the end of the insn in
7444 if (all_reaches_end)
7446 /* First, clear out memory of what used to be in this spill reg.
7447 If consecutive registers are used, clear them all. */
7449 for (k = 0; k < nr; k++)
7450 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7452 /* Maybe the spill reg contains a copy of reload_out. */
7453 if (reload_out[r] != 0
7454 && (GET_CODE (reload_out[r]) == REG
7456 || ! reload_out_reg[r]
7458 || GET_CODE (reload_out_reg[r]) == REG))
7460 rtx out = (GET_CODE (reload_out[r]) == REG
7464 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7465 register int nregno = REGNO (out);
7466 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7467 : HARD_REGNO_NREGS (nregno,
7468 GET_MODE (reload_reg_rtx[r])));
7470 spill_reg_store[i] = new_spill_reg_store[i];
7471 spill_reg_stored_to[i] = out;
7472 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7474 /* If NREGNO is a hard register, it may occupy more than
7475 one register. If it does, say what is in the
7476 rest of the registers assuming that both registers
7477 agree on how many words the object takes. If not,
7478 invalidate the subsequent registers. */
7480 if (nregno < FIRST_PSEUDO_REGISTER)
7481 for (k = 1; k < nnr; k++)
7482 reg_last_reload_reg[nregno + k]
7484 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7485 REGNO (reload_reg_rtx[r]) + k)
7488 /* Now do the inverse operation. */
7489 for (k = 0; k < nr; k++)
7491 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7492 reg_reloaded_contents[i + k]
7493 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7496 reg_reloaded_insn[i + k] = insn;
7497 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7501 /* Maybe the spill reg contains a copy of reload_in. Only do
7502 something if there will not be an output reload for
7503 the register being reloaded. */
7504 else if (reload_out_reg[r] == 0
7505 && reload_in[r] != 0
7506 && ((GET_CODE (reload_in[r]) == REG
7507 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7508 && ! reg_has_output_reload[REGNO (reload_in[r])])
7509 || (GET_CODE (reload_in_reg[r]) == REG
7510 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7511 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7513 register int nregno;
7516 if (GET_CODE (reload_in[r]) == REG
7517 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7518 nregno = REGNO (reload_in[r]);
7519 else if (GET_CODE (reload_in_reg[r]) == REG)
7520 nregno = REGNO (reload_in_reg[r]);
7522 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7524 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7525 : HARD_REGNO_NREGS (nregno,
7526 GET_MODE (reload_reg_rtx[r])));
7528 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7530 if (nregno < FIRST_PSEUDO_REGISTER)
7531 for (k = 1; k < nnr; k++)
7532 reg_last_reload_reg[nregno + k]
7534 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7535 REGNO (reload_reg_rtx[r]) + k)
7538 /* Unless we inherited this reload, show we haven't
7539 recently done a store.
7540 Previous stores of inherited auto_inc expressions
7541 also have to be discarded. */
7542 if (! reload_inherited[r]
7543 || (reload_out[r] && ! reload_out_reg[r]))
7544 spill_reg_store[i] = 0;
7546 for (k = 0; k < nr; k++)
7548 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7549 reg_reloaded_contents[i + k]
7550 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7553 reg_reloaded_insn[i + k] = insn;
7554 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7559 /* However, if part of the reload reaches the end, then we must
7560 invalidate the old info for the part that survives to the end. */
7561 else if (part_reaches_end)
7563 for (k = 0; k < nr; k++)
7564 if (reload_reg_reaches_end_p (i + k,
7566 reload_when_needed[r]))
7567 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7571 /* The following if-statement was #if 0'd in 1.34 (or before...).
7572 It's reenabled in 1.35 because supposedly nothing else
7573 deals with this problem. */
7575 /* If a register gets output-reloaded from a non-spill register,
7576 that invalidates any previous reloaded copy of it.
7577 But forget_old_reloads_1 won't get to see it, because
7578 it thinks only about the original insn. So invalidate it here. */
7579 if (i < 0 && reload_out[r] != 0
7580 && (GET_CODE (reload_out[r]) == REG
7581 || (GET_CODE (reload_out[r]) == MEM
7582 && GET_CODE (reload_out_reg[r]) == REG)))
7584 rtx out = (GET_CODE (reload_out[r]) == REG
7585 ? reload_out[r] : reload_out_reg[r]);
7586 register int nregno = REGNO (out);
7587 if (nregno >= FIRST_PSEUDO_REGISTER)
7589 rtx src_reg, store_insn;
7591 reg_last_reload_reg[nregno] = 0;
7593 /* If we can find a hard register that is stored, record
7594 the storing insn so that we may delete this insn with
7595 delete_output_reload. */
7596 src_reg = reload_reg_rtx[r];
7598 /* If this is an optional reload, try to find the source reg
7599 from an input reload. */
7602 rtx set = single_set (insn);
7603 if (set && SET_DEST (set) == reload_out[r])
7607 src_reg = SET_SRC (set);
7609 for (k = 0; k < n_reloads; k++)
7611 if (reload_in[k] == src_reg)
7613 src_reg = reload_reg_rtx[k];
7620 store_insn = new_spill_reg_store[REGNO (src_reg)];
7621 if (src_reg && GET_CODE (src_reg) == REG
7622 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7624 int src_regno = REGNO (src_reg);
7625 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7626 /* The place where to find a death note varies with
7627 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7628 necessarily checked exactly in the code that moves
7629 notes, so just check both locations. */
7630 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7632 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7635 spill_reg_store[src_regno + nr] = store_insn;
7636 spill_reg_stored_to[src_regno + nr] = out;
7637 reg_reloaded_contents[src_regno + nr] = nregno;
7638 reg_reloaded_insn[src_regno + nr] = store_insn;
7639 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7640 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7641 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7643 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7645 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7647 reg_last_reload_reg[nregno] = src_reg;
7652 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7654 while (num_regs-- > 0)
7655 reg_last_reload_reg[nregno + num_regs] = 0;
7659 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7662 /* Emit code to perform a reload from IN (which may be a reload register) to
7663 OUT (which may also be a reload register). IN or OUT is from operand
7664 OPNUM with reload type TYPE.
7666 Returns first insn emitted. */
7669 gen_reload (out, in, opnum, type)
7673 enum reload_type type;
7675 rtx last = get_last_insn ();
7678 /* If IN is a paradoxical SUBREG, remove it and try to put the
7679 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7680 if (GET_CODE (in) == SUBREG
7681 && (GET_MODE_SIZE (GET_MODE (in))
7682 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7683 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7684 in = SUBREG_REG (in), out = tem;
7685 else if (GET_CODE (out) == SUBREG
7686 && (GET_MODE_SIZE (GET_MODE (out))
7687 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7688 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7689 out = SUBREG_REG (out), in = tem;
7691 /* How to do this reload can get quite tricky. Normally, we are being
7692 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7693 register that didn't get a hard register. In that case we can just
7694 call emit_move_insn.
7696 We can also be asked to reload a PLUS that adds a register or a MEM to
7697 another register, constant or MEM. This can occur during frame pointer
7698 elimination and while reloading addresses. This case is handled by
7699 trying to emit a single insn to perform the add. If it is not valid,
7700 we use a two insn sequence.
7702 Finally, we could be called to handle an 'o' constraint by putting
7703 an address into a register. In that case, we first try to do this
7704 with a named pattern of "reload_load_address". If no such pattern
7705 exists, we just emit a SET insn and hope for the best (it will normally
7706 be valid on machines that use 'o').
7708 This entire process is made complex because reload will never
7709 process the insns we generate here and so we must ensure that
7710 they will fit their constraints and also by the fact that parts of
7711 IN might be being reloaded separately and replaced with spill registers.
7712 Because of this, we are, in some sense, just guessing the right approach
7713 here. The one listed above seems to work.
7715 ??? At some point, this whole thing needs to be rethought. */
7717 if (GET_CODE (in) == PLUS
7718 && (GET_CODE (XEXP (in, 0)) == REG
7719 || GET_CODE (XEXP (in, 0)) == SUBREG
7720 || GET_CODE (XEXP (in, 0)) == MEM)
7721 && (GET_CODE (XEXP (in, 1)) == REG
7722 || GET_CODE (XEXP (in, 1)) == SUBREG
7723 || CONSTANT_P (XEXP (in, 1))
7724 || GET_CODE (XEXP (in, 1)) == MEM))
7726 /* We need to compute the sum of a register or a MEM and another
7727 register, constant, or MEM, and put it into the reload
7728 register. The best possible way of doing this is if the machine
7729 has a three-operand ADD insn that accepts the required operands.
7731 The simplest approach is to try to generate such an insn and see if it
7732 is recognized and matches its constraints. If so, it can be used.
7734 It might be better not to actually emit the insn unless it is valid,
7735 but we need to pass the insn as an operand to `recog' and
7736 `extract_insn' and it is simpler to emit and then delete the insn if
7737 not valid than to dummy things up. */
7739 rtx op0, op1, tem, insn;
7742 op0 = find_replacement (&XEXP (in, 0));
7743 op1 = find_replacement (&XEXP (in, 1));
7745 /* Since constraint checking is strict, commutativity won't be
7746 checked, so we need to do that here to avoid spurious failure
7747 if the add instruction is two-address and the second operand
7748 of the add is the same as the reload reg, which is frequently
7749 the case. If the insn would be A = B + A, rearrange it so
7750 it will be A = A + B as constrain_operands expects. */
7752 if (GET_CODE (XEXP (in, 1)) == REG
7753 && REGNO (out) == REGNO (XEXP (in, 1)))
7754 tem = op0, op0 = op1, op1 = tem;
7756 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7757 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7759 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7760 code = recog_memoized (insn);
7764 extract_insn (insn);
7765 /* We want constrain operands to treat this insn strictly in
7766 its validity determination, i.e., the way it would after reload
7768 if (constrain_operands (1))
7772 delete_insns_since (last);
7774 /* If that failed, we must use a conservative two-insn sequence.
7775 use move to copy constant, MEM, or pseudo register to the reload
7776 register since "move" will be able to handle an arbitrary operand,
7777 unlike add which can't, in general. Then add the registers.
7779 If there is another way to do this for a specific machine, a
7780 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7783 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7784 || (GET_CODE (op1) == REG
7785 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7786 tem = op0, op0 = op1, op1 = tem;
7788 gen_reload (out, op0, opnum, type);
7790 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7791 This fixes a problem on the 32K where the stack pointer cannot
7792 be used as an operand of an add insn. */
7794 if (rtx_equal_p (op0, op1))
7797 insn = emit_insn (gen_add2_insn (out, op1));
7799 /* If that failed, copy the address register to the reload register.
7800 Then add the constant to the reload register. */
7802 code = recog_memoized (insn);
7806 extract_insn (insn);
7807 /* We want constrain operands to treat this insn strictly in
7808 its validity determination, i.e., the way it would after reload
7810 if (constrain_operands (1))
7812 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7814 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7819 delete_insns_since (last);
7821 gen_reload (out, op1, opnum, type);
7822 insn = emit_insn (gen_add2_insn (out, op0));
7823 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7826 #ifdef SECONDARY_MEMORY_NEEDED
7827 /* If we need a memory location to do the move, do it that way. */
7828 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7829 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7830 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7831 REGNO_REG_CLASS (REGNO (out)),
7834 /* Get the memory to use and rewrite both registers to its mode. */
7835 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7837 if (GET_MODE (loc) != GET_MODE (out))
7838 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7840 if (GET_MODE (loc) != GET_MODE (in))
7841 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7843 gen_reload (loc, in, opnum, type);
7844 gen_reload (out, loc, opnum, type);
7848 /* If IN is a simple operand, use gen_move_insn. */
7849 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7850 emit_insn (gen_move_insn (out, in));
7852 #ifdef HAVE_reload_load_address
7853 else if (HAVE_reload_load_address)
7854 emit_insn (gen_reload_load_address (out, in));
7857 /* Otherwise, just write (set OUT IN) and hope for the best. */
7859 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7861 /* Return the first insn emitted.
7862 We can not just return get_last_insn, because there may have
7863 been multiple instructions emitted. Also note that gen_move_insn may
7864 emit more than one insn itself, so we can not assume that there is one
7865 insn emitted per emit_insn_before call. */
7867 return last ? NEXT_INSN (last) : get_insns ();
7870 /* Delete a previously made output-reload
7871 whose result we now believe is not needed.
7872 First we double-check.
7874 INSN is the insn now being processed.
7875 LAST_RELOAD_REG is the hard register number for which we want to delete
7876 the last output reload.
7877 J is the reload-number that originally used REG. The caller has made
7878 certain that reload J doesn't use REG any longer for input. */
7881 delete_output_reload (insn, j, last_reload_reg)
7884 int last_reload_reg;
7886 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7887 rtx reg = spill_reg_stored_to[last_reload_reg];
7890 int n_inherited = 0;
7894 /* Get the raw pseudo-register referred to. */
7896 while (GET_CODE (reg) == SUBREG)
7897 reg = SUBREG_REG (reg);
7898 substed = reg_equiv_memory_loc[REGNO (reg)];
7900 /* This is unsafe if the operand occurs more often in the current
7901 insn than it is inherited. */
7902 for (k = n_reloads - 1; k >= 0; k--)
7904 rtx reg2 = reload_in[k];
7907 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7908 reg2 = reload_in_reg[k];
7910 if (reload_out[k] && ! reload_out_reg[k])
7911 reg2 = XEXP (reload_in_reg[k], 0);
7913 while (GET_CODE (reg2) == SUBREG)
7914 reg2 = SUBREG_REG (reg2);
7915 if (rtx_equal_p (reg2, reg))
7917 if (reload_inherited[k] || reload_override_in[k] || k == j)
7920 reg2 = reload_out_reg[k];
7923 while (GET_CODE (reg2) == SUBREG)
7924 reg2 = XEXP (reg2, 0);
7925 if (rtx_equal_p (reg2, reg))
7932 n_occurrences = count_occurrences (PATTERN (insn), reg);
7934 n_occurrences += count_occurrences (PATTERN (insn), substed);
7935 if (n_occurrences > n_inherited)
7938 /* If the pseudo-reg we are reloading is no longer referenced
7939 anywhere between the store into it and here,
7940 and no jumps or labels intervene, then the value can get
7941 here through the reload reg alone.
7942 Otherwise, give up--return. */
7943 for (i1 = NEXT_INSN (output_reload_insn);
7944 i1 != insn; i1 = NEXT_INSN (i1))
7946 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7948 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7949 && reg_mentioned_p (reg, PATTERN (i1)))
7951 /* If this is USE in front of INSN, we only have to check that
7952 there are no more references than accounted for by inheritance. */
7953 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7955 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7956 i1 = NEXT_INSN (i1);
7958 if (n_occurrences <= n_inherited && i1 == insn)
7964 /* The caller has already checked that REG dies or is set in INSN.
7965 It has also checked that we are optimizing, and thus some inaccurancies
7966 in the debugging information are acceptable.
7967 So we could just delete output_reload_insn.
7968 But in some cases we can improve the debugging information without
7969 sacrificing optimization - maybe even improving the code:
7970 See if the pseudo reg has been completely replaced
7971 with reload regs. If so, delete the store insn
7972 and forget we had a stack slot for the pseudo. */
7973 if (reload_out[j] != reload_in[j]
7974 && REG_N_DEATHS (REGNO (reg)) == 1
7975 && REG_N_SETS (REGNO (reg)) == 1
7976 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7977 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7981 /* We know that it was used only between here
7982 and the beginning of the current basic block.
7983 (We also know that the last use before INSN was
7984 the output reload we are thinking of deleting, but never mind that.)
7985 Search that range; see if any ref remains. */
7986 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7988 rtx set = single_set (i2);
7990 /* Uses which just store in the pseudo don't count,
7991 since if they are the only uses, they are dead. */
7992 if (set != 0 && SET_DEST (set) == reg)
7994 if (GET_CODE (i2) == CODE_LABEL
7995 || GET_CODE (i2) == JUMP_INSN)
7997 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7998 && reg_mentioned_p (reg, PATTERN (i2)))
8000 /* Some other ref remains; just delete the output reload we
8002 delete_address_reloads (output_reload_insn, insn);
8003 PUT_CODE (output_reload_insn, NOTE);
8004 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8005 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8010 /* Delete the now-dead stores into this pseudo. */
8011 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8013 rtx set = single_set (i2);
8015 if (set != 0 && SET_DEST (set) == reg)
8017 delete_address_reloads (i2, insn);
8018 /* This might be a basic block head,
8019 thus don't use delete_insn. */
8020 PUT_CODE (i2, NOTE);
8021 NOTE_SOURCE_FILE (i2) = 0;
8022 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8024 if (GET_CODE (i2) == CODE_LABEL
8025 || GET_CODE (i2) == JUMP_INSN)
8029 /* For the debugging info,
8030 say the pseudo lives in this reload reg. */
8031 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
8032 alter_reg (REGNO (reg), -1);
8034 delete_address_reloads (output_reload_insn, insn);
8035 PUT_CODE (output_reload_insn, NOTE);
8036 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8037 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8041 /* We are going to delete DEAD_INSN. Recursively delete loads of
8042 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8043 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8045 delete_address_reloads (dead_insn, current_insn)
8046 rtx dead_insn, current_insn;
8048 rtx set = single_set (dead_insn);
8049 rtx set2, dst, prev, next;
8052 rtx dst = SET_DEST (set);
8053 if (GET_CODE (dst) == MEM)
8054 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8056 /* If we deleted the store from a reloaded post_{in,de}c expression,
8057 we can delete the matching adds. */
8058 prev = PREV_INSN (dead_insn);
8059 next = NEXT_INSN (dead_insn);
8060 if (! prev || ! next)
8062 set = single_set (next);
8063 set2 = single_set (prev);
8065 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8066 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8067 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8069 dst = SET_DEST (set);
8070 if (! rtx_equal_p (dst, SET_DEST (set2))
8071 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8072 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8073 || (INTVAL (XEXP (SET_SRC (set), 1))
8074 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8080 /* Subfunction of delete_address_reloads: process registers found in X. */
8082 delete_address_reloads_1 (dead_insn, x, current_insn)
8083 rtx dead_insn, x, current_insn;
8085 rtx prev, set, dst, i2;
8087 enum rtx_code code = GET_CODE (x);
8091 char *fmt= GET_RTX_FORMAT (code);
8092 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8095 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8096 else if (fmt[i] == 'E')
8098 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8099 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8106 if (spill_reg_order[REGNO (x)] < 0)
8109 /* Scan backwards for the insn that sets x. This might be a way back due
8111 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8113 code = GET_CODE (prev);
8114 if (code == CODE_LABEL || code == JUMP_INSN)
8116 if (GET_RTX_CLASS (code) != 'i')
8118 if (reg_set_p (x, PATTERN (prev)))
8120 if (reg_referenced_p (x, PATTERN (prev)))
8123 if (! prev || INSN_UID (prev) < reload_first_uid)
8125 /* Check that PREV only sets the reload register. */
8126 set = single_set (prev);
8129 dst = SET_DEST (set);
8130 if (GET_CODE (dst) != REG
8131 || ! rtx_equal_p (dst, x))
8133 if (! reg_set_p (dst, PATTERN (dead_insn)))
8135 /* Check if DST was used in a later insn -
8136 it might have been inherited. */
8137 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8139 if (GET_CODE (i2) == CODE_LABEL)
8141 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8143 if (reg_referenced_p (dst, PATTERN (i2)))
8145 /* If there is a reference to the register in the current insn,
8146 it might be loaded in a non-inherited reload. If no other
8147 reload uses it, that means the register is set before
8149 if (i2 == current_insn)
8151 for (j = n_reloads - 1; j >= 0; j--)
8152 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8153 || reload_override_in[j] == dst)
8155 for (j = n_reloads - 1; j >= 0; j--)
8156 if (reload_in[j] && reload_reg_rtx[j] == dst)
8163 if (GET_CODE (i2) == JUMP_INSN)
8165 /* If DST is still live at CURRENT_INSN, check if it is used for
8166 any reload. Note that even if CURRENT_INSN sets DST, we still
8167 have to check the reloads. */
8168 if (i2 == current_insn)
8170 for (j = n_reloads - 1; j >= 0; j--)
8171 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8172 || reload_override_in[j] == dst)
8174 /* ??? We can't finish the loop here, because dst might be
8175 allocated to a pseudo in this block if no reload in this
8176 block needs any of the clsses containing DST - see
8177 spill_hard_reg. There is no easy way to tell this, so we
8178 have to scan till the end of the basic block. */
8180 if (reg_set_p (dst, PATTERN (i2)))
8184 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8185 reg_reloaded_contents[REGNO (dst)] = -1;
8186 /* Can't use delete_insn here because PREV might be a basic block head. */
8187 PUT_CODE (prev, NOTE);
8188 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8189 NOTE_SOURCE_FILE (prev) = 0;
8192 /* Output reload-insns to reload VALUE into RELOADREG.
8193 VALUE is an autoincrement or autodecrement RTX whose operand
8194 is a register or memory location;
8195 so reloading involves incrementing that location.
8196 IN is either identical to VALUE, or some cheaper place to reload from.
8198 INC_AMOUNT is the number to increment or decrement by (always positive).
8199 This cannot be deduced from VALUE.
8201 Return the instruction that stores into RELOADREG. */
8204 inc_for_reload (reloadreg, in, value, inc_amount)
8209 /* REG or MEM to be copied and incremented. */
8210 rtx incloc = XEXP (value, 0);
8211 /* Nonzero if increment after copying. */
8212 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8218 rtx real_in = in == value ? XEXP (in, 0) : in;
8220 /* No hard register is equivalent to this register after
8221 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8222 we could inc/dec that register as well (maybe even using it for
8223 the source), but I'm not sure it's worth worrying about. */
8224 if (GET_CODE (incloc) == REG)
8225 reg_last_reload_reg[REGNO (incloc)] = 0;
8227 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8228 inc_amount = - inc_amount;
8230 inc = GEN_INT (inc_amount);
8232 /* If this is post-increment, first copy the location to the reload reg. */
8233 if (post && real_in != reloadreg)
8234 emit_insn (gen_move_insn (reloadreg, real_in));
8238 /* See if we can directly increment INCLOC. Use a method similar to
8239 that in gen_reload. */
8241 last = get_last_insn ();
8242 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8243 gen_rtx_PLUS (GET_MODE (incloc),
8246 code = recog_memoized (add_insn);
8249 extract_insn (add_insn);
8250 if (constrain_operands (1))
8252 /* If this is a pre-increment and we have incremented the value
8253 where it lives, copy the incremented value to RELOADREG to
8254 be used as an address. */
8257 emit_insn (gen_move_insn (reloadreg, incloc));
8262 delete_insns_since (last);
8265 /* If couldn't do the increment directly, must increment in RELOADREG.
8266 The way we do this depends on whether this is pre- or post-increment.
8267 For pre-increment, copy INCLOC to the reload register, increment it
8268 there, then save back. */
8272 if (in != reloadreg)
8273 emit_insn (gen_move_insn (reloadreg, real_in));
8274 emit_insn (gen_add2_insn (reloadreg, inc));
8275 store = emit_insn (gen_move_insn (incloc, reloadreg));
8280 Because this might be a jump insn or a compare, and because RELOADREG
8281 may not be available after the insn in an input reload, we must do
8282 the incrementation before the insn being reloaded for.
8284 We have already copied IN to RELOADREG. Increment the copy in
8285 RELOADREG, save that back, then decrement RELOADREG so it has
8286 the original value. */
8288 emit_insn (gen_add2_insn (reloadreg, inc));
8289 store = emit_insn (gen_move_insn (incloc, reloadreg));
8290 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8296 /* Return 1 if we are certain that the constraint-string STRING allows
8297 the hard register REG. Return 0 if we can't be sure of this. */
8300 constraint_accepts_reg_p (string, reg)
8305 int regno = true_regnum (reg);
8308 /* Initialize for first alternative. */
8310 /* Check that each alternative contains `g' or `r'. */
8312 switch (c = *string++)
8315 /* If an alternative lacks `g' or `r', we lose. */
8318 /* If an alternative lacks `g' or `r', we lose. */
8321 /* Initialize for next alternative. */
8326 /* Any general reg wins for this alternative. */
8327 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8331 /* Any reg in specified class wins for this alternative. */
8333 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8335 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8341 /* Return the number of places FIND appears within X, but don't count
8342 an occurrence if some SET_DEST is FIND. */
8345 count_occurrences (x, find)
8346 register rtx x, find;
8349 register enum rtx_code code;
8350 register char *format_ptr;
8358 code = GET_CODE (x);
8373 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8377 if (SET_DEST (x) == find)
8378 return count_occurrences (SET_SRC (x), find);
8385 format_ptr = GET_RTX_FORMAT (code);
8388 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8390 switch (*format_ptr++)
8393 count += count_occurrences (XEXP (x, i), find);
8397 if (XVEC (x, i) != NULL)
8399 for (j = 0; j < XVECLEN (x, i); j++)
8400 count += count_occurrences (XVECEXP (x, i, j), find);
8408 /* This array holds values which are equivalent to a hard register
8409 during reload_cse_regs. Each array element is an EXPR_LIST of
8410 values. Each time a hard register is set, we set the corresponding
8411 array element to the value. Each time a hard register is copied
8412 into memory, we add the memory location to the corresponding array
8413 element. We don't store values or memory addresses with side
8414 effects in this array.
8416 If the value is a CONST_INT, then the mode of the containing
8417 EXPR_LIST is the mode in which that CONST_INT was referenced.
8419 We sometimes clobber a specific entry in a list. In that case, we
8420 just set XEXP (list-entry, 0) to 0. */
8422 static rtx *reg_values;
8424 /* This is a preallocated REG rtx which we use as a temporary in
8425 reload_cse_invalidate_regno, so that we don't need to allocate a
8426 new one each time through a loop in that function. */
8428 static rtx invalidate_regno_rtx;
8430 /* Invalidate any entries in reg_values which depend on REGNO,
8431 including those for REGNO itself. This is called if REGNO is
8432 changing. If CLOBBER is true, then always forget anything we
8433 currently know about REGNO. MODE is the mode of the assignment to
8434 REGNO, which is used to determine how many hard registers are being
8435 changed. If MODE is VOIDmode, then only REGNO is being changed;
8436 this is used when invalidating call clobbered registers across a
8440 reload_cse_invalidate_regno (regno, mode, clobber)
8442 enum machine_mode mode;
8448 /* Our callers don't always go through true_regnum; we may see a
8449 pseudo-register here from a CLOBBER or the like. We probably
8450 won't ever see a pseudo-register that has a real register number,
8451 for we check anyhow for safety. */
8452 if (regno >= FIRST_PSEUDO_REGISTER)
8453 regno = reg_renumber[regno];
8457 if (mode == VOIDmode)
8458 endregno = regno + 1;
8460 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8463 for (i = regno; i < endregno; i++)
8466 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8470 for (x = reg_values[i]; x; x = XEXP (x, 1))
8472 if (XEXP (x, 0) != 0
8473 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8475 /* If this is the only entry on the list, clear
8476 reg_values[i]. Otherwise, just clear this entry on
8478 if (XEXP (x, 1) == 0 && x == reg_values[i])
8488 /* We must look at earlier registers, in case REGNO is part of a
8489 multi word value but is not the first register. If an earlier
8490 register has a value in a mode which overlaps REGNO, then we must
8491 invalidate that earlier register. Note that we do not need to
8492 check REGNO or later registers (we must not check REGNO itself,
8493 because we would incorrectly conclude that there was a conflict). */
8495 for (i = 0; i < regno; i++)
8499 for (x = reg_values[i]; x; x = XEXP (x, 1))
8501 if (XEXP (x, 0) != 0)
8503 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8504 REGNO (invalidate_regno_rtx) = i;
8505 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8508 reload_cse_invalidate_regno (i, VOIDmode, 1);
8516 /* The memory at address MEM_BASE is being changed.
8517 Return whether this change will invalidate VAL. */
8520 reload_cse_mem_conflict_p (mem_base, val)
8528 code = GET_CODE (val);
8531 /* Get rid of a few simple cases quickly. */
8544 if (GET_MODE (mem_base) == BLKmode
8545 || GET_MODE (val) == BLKmode)
8547 if (anti_dependence (val, mem_base))
8549 /* The address may contain nested MEMs. */
8556 fmt = GET_RTX_FORMAT (code);
8558 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8562 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8565 else if (fmt[i] == 'E')
8569 for (j = 0; j < XVECLEN (val, i); j++)
8570 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8578 /* Invalidate any entries in reg_values which are changed because of a
8579 store to MEM_RTX. If this is called because of a non-const call
8580 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8583 reload_cse_invalidate_mem (mem_rtx)
8588 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8592 for (x = reg_values[i]; x; x = XEXP (x, 1))
8594 if (XEXP (x, 0) != 0
8595 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8597 /* If this is the only entry on the list, clear
8598 reg_values[i]. Otherwise, just clear this entry on
8600 if (XEXP (x, 1) == 0 && x == reg_values[i])
8611 /* Invalidate DEST, which is being assigned to or clobbered. The
8612 second parameter exists so that this function can be passed to
8613 note_stores; it is ignored. */
8616 reload_cse_invalidate_rtx (dest, ignore)
8618 rtx ignore ATTRIBUTE_UNUSED;
8620 while (GET_CODE (dest) == STRICT_LOW_PART
8621 || GET_CODE (dest) == SIGN_EXTRACT
8622 || GET_CODE (dest) == ZERO_EXTRACT
8623 || GET_CODE (dest) == SUBREG)
8624 dest = XEXP (dest, 0);
8626 if (GET_CODE (dest) == REG)
8627 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8628 else if (GET_CODE (dest) == MEM)
8629 reload_cse_invalidate_mem (dest);
8632 /* Do a very simple CSE pass over the hard registers.
8634 This function detects no-op moves where we happened to assign two
8635 different pseudo-registers to the same hard register, and then
8636 copied one to the other. Reload will generate a useless
8637 instruction copying a register to itself.
8639 This function also detects cases where we load a value from memory
8640 into two different registers, and (if memory is more expensive than
8641 registers) changes it to simply copy the first register into the
8644 Another optimization is performed that scans the operands of each
8645 instruction to see whether the value is already available in a
8646 hard register. It then replaces the operand with the hard register
8647 if possible, much like an optional reload would. */
8650 reload_cse_regs_1 (first)
8658 init_alias_analysis ();
8660 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8661 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8663 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8664 free them when we are done. */
8665 push_obstacks (&reload_obstack, &reload_obstack);
8666 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8668 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8669 memory for a non-const call instruction. */
8670 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8672 /* This is used in reload_cse_invalidate_regno to avoid consing a
8673 new REG in a loop in that function. */
8674 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8676 for (insn = first; insn; insn = NEXT_INSN (insn))
8680 if (GET_CODE (insn) == CODE_LABEL)
8682 /* Forget all the register values at a code label. We don't
8683 try to do anything clever around jumps. */
8684 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8690 #ifdef NON_SAVING_SETJMP
8691 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8692 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8701 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8704 /* If this is a call instruction, forget anything stored in a
8705 call clobbered register, or, if this is not a const call, in
8707 if (GET_CODE (insn) == CALL_INSN)
8709 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8710 if (call_used_regs[i])
8711 reload_cse_invalidate_regno (i, VOIDmode, 1);
8713 if (! CONST_CALL_P (insn))
8714 reload_cse_invalidate_mem (callmem);
8717 body = PATTERN (insn);
8718 if (GET_CODE (body) == SET)
8721 if (reload_cse_noop_set_p (body, insn))
8723 /* If this sets the return value of the function, we must keep
8724 a USE around, in case this is in a different basic block
8725 than the final USE. Otherwise, we could loose important
8726 register lifeness information on SMALL_REGISTER_CLASSES
8727 machines, where return registers might be used as spills:
8728 subsequent passes assume that spill registers are dead at
8729 the end of a basic block. */
8730 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8733 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8734 INSN_CODE (insn) = -1;
8735 REG_NOTES (insn) = NULL_RTX;
8736 push_obstacks (&reload_obstack, &reload_obstack);
8740 PUT_CODE (insn, NOTE);
8741 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8742 NOTE_SOURCE_FILE (insn) = 0;
8745 /* We're done with this insn. */
8749 /* It's not a no-op, but we can try to simplify it. */
8750 count += reload_cse_simplify_set (body, insn);
8753 apply_change_group ();
8755 reload_cse_simplify_operands (insn);
8757 reload_cse_record_set (body, body);
8759 else if (GET_CODE (body) == PARALLEL)
8762 rtx value = NULL_RTX;
8764 /* If every action in a PARALLEL is a noop, we can delete
8765 the entire PARALLEL. */
8766 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8768 rtx part = XVECEXP (body, 0, i);
8769 if (GET_CODE (part) == SET)
8771 if (! reload_cse_noop_set_p (part, insn))
8773 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8777 value = SET_DEST (part);
8780 else if (GET_CODE (part) != CLOBBER)
8788 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8789 INSN_CODE (insn) = -1;
8790 REG_NOTES (insn) = NULL_RTX;
8791 push_obstacks (&reload_obstack, &reload_obstack);
8795 PUT_CODE (insn, NOTE);
8796 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8797 NOTE_SOURCE_FILE (insn) = 0;
8800 /* We're done with this insn. */
8804 /* It's not a no-op, but we can try to simplify it. */
8805 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8806 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8807 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8810 apply_change_group ();
8812 reload_cse_simplify_operands (insn);
8814 /* Look through the PARALLEL and record the values being
8815 set, if possible. Also handle any CLOBBERs. */
8816 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8818 rtx x = XVECEXP (body, 0, i);
8820 if (GET_CODE (x) == SET)
8821 reload_cse_record_set (x, body);
8823 note_stores (x, reload_cse_invalidate_rtx);
8827 note_stores (body, reload_cse_invalidate_rtx);
8830 /* Clobber any registers which appear in REG_INC notes. We
8831 could keep track of the changes to their values, but it is
8832 unlikely to help. */
8836 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8837 if (REG_NOTE_KIND (x) == REG_INC)
8838 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8842 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8843 after we have processed the insn. */
8844 if (GET_CODE (insn) == CALL_INSN)
8848 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8849 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8850 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8854 /* Free all the temporary structures we created, and go back to the
8855 regular obstacks. */
8856 obstack_free (&reload_obstack, firstobj);
8860 /* Call cse / combine like post-reload optimization phases.
8861 FIRST is the first instruction. */
8863 reload_cse_regs (first)
8866 reload_cse_regs_1 (first);
8868 reload_cse_move2add (first);
8869 if (flag_expensive_optimizations)
8870 reload_cse_regs_1 (first);
8873 /* Return whether the values known for REGNO are equal to VAL. MODE
8874 is the mode of the object that VAL is being copied to; this matters
8875 if VAL is a CONST_INT. */
8878 reload_cse_regno_equal_p (regno, val, mode)
8881 enum machine_mode mode;
8888 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8889 if (XEXP (x, 0) != 0
8890 && rtx_equal_p (XEXP (x, 0), val)
8891 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8892 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8893 && (GET_CODE (val) != CONST_INT
8894 || mode == GET_MODE (x)
8895 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8896 /* On a big endian machine if the value spans more than
8897 one register then this register holds the high part of
8898 it and we can't use it.
8900 ??? We should also compare with the high part of the
8902 && !(WORDS_BIG_ENDIAN
8903 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8904 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8905 GET_MODE_BITSIZE (GET_MODE (x))))))
8911 /* See whether a single set is a noop. SET is the set instruction we
8912 are should check, and INSN is the instruction from which it came. */
8915 reload_cse_noop_set_p (set, insn)
8920 enum machine_mode dest_mode;
8924 src = SET_SRC (set);
8925 dest = SET_DEST (set);
8926 dest_mode = GET_MODE (dest);
8928 if (side_effects_p (src))
8931 dreg = true_regnum (dest);
8932 sreg = true_regnum (src);
8934 /* Check for setting a register to itself. In this case, we don't
8935 have to worry about REG_DEAD notes. */
8936 if (dreg >= 0 && dreg == sreg)
8942 /* Check for setting a register to itself. */
8946 /* Check for setting a register to a value which we already know
8947 is in the register. */
8948 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8951 /* Check for setting a register DREG to another register SREG
8952 where SREG is equal to a value which is already in DREG. */
8957 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8961 if (XEXP (x, 0) == 0)
8964 if (dest_mode == GET_MODE (x))
8966 else if (GET_MODE_BITSIZE (dest_mode)
8967 < GET_MODE_BITSIZE (GET_MODE (x)))
8968 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8973 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8981 else if (GET_CODE (dest) == MEM)
8983 /* Check for storing a register to memory when we know that the
8984 register is equivalent to the memory location. */
8986 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8987 && ! side_effects_p (dest))
8994 /* Try to simplify a single SET instruction. SET is the set pattern.
8995 INSN is the instruction it came from.
8996 This function only handles one case: if we set a register to a value
8997 which is not a register, we try to find that value in some other register
8998 and change the set into a register copy. */
9001 reload_cse_simplify_set (set, insn)
9007 enum machine_mode dest_mode;
9008 enum reg_class dclass;
9011 dreg = true_regnum (SET_DEST (set));
9015 src = SET_SRC (set);
9016 if (side_effects_p (src) || true_regnum (src) >= 0)
9019 dclass = REGNO_REG_CLASS (dreg);
9021 /* If memory loads are cheaper than register copies, don't change them. */
9022 if (GET_CODE (src) == MEM
9023 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9026 /* If the constant is cheaper than a register, don't change it. */
9027 if (CONSTANT_P (src)
9028 && rtx_cost (src, SET) < 2)
9031 dest_mode = GET_MODE (SET_DEST (set));
9032 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9035 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9036 && reload_cse_regno_equal_p (i, src, dest_mode))
9040 /* Pop back to the real obstacks while changing the insn. */
9043 validated = validate_change (insn, &SET_SRC (set),
9044 gen_rtx_REG (dest_mode, i), 1);
9046 /* Go back to the obstack we are using for temporary
9048 push_obstacks (&reload_obstack, &reload_obstack);
9057 /* Try to replace operands in INSN with equivalent values that are already
9058 in registers. This can be viewed as optional reloading.
9060 For each non-register operand in the insn, see if any hard regs are
9061 known to be equivalent to that operand. Record the alternatives which
9062 can accept these hard registers. Among all alternatives, select the
9063 ones which are better or equal to the one currently matching, where
9064 "better" is in terms of '?' and '!' constraints. Among the remaining
9065 alternatives, select the one which replaces most operands with
9069 reload_cse_simplify_operands (insn)
9072 #ifdef REGISTER_CONSTRAINTS
9075 const char *constraints[MAX_RECOG_OPERANDS];
9077 /* Vector recording how bad an alternative is. */
9078 int *alternative_reject;
9079 /* Vector recording how many registers can be introduced by choosing
9080 this alternative. */
9081 int *alternative_nregs;
9082 /* Array of vectors recording, for each operand and each alternative,
9083 which hard register to substitute, or -1 if the operand should be
9085 int *op_alt_regno[MAX_RECOG_OPERANDS];
9086 /* Array of alternatives, sorted in order of decreasing desirability. */
9087 int *alternative_order;
9088 rtx reg = gen_rtx_REG (VOIDmode, -1);
9090 extract_insn (insn);
9092 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9095 /* Figure out which alternative currently matches. */
9096 if (! constrain_operands (1))
9097 fatal_insn_not_found (insn);
9099 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9100 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9101 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9102 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9103 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9105 for (i = 0; i < recog_n_operands; i++)
9107 enum machine_mode mode;
9111 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9112 for (j = 0; j < recog_n_alternatives; j++)
9113 op_alt_regno[i][j] = -1;
9115 p = constraints[i] = recog_constraints[i];
9116 mode = recog_operand_mode[i];
9118 /* Add the reject values for each alternative given by the constraints
9119 for this operand. */
9127 alternative_reject[j] += 3;
9129 alternative_reject[j] += 300;
9132 /* We won't change operands which are already registers. We
9133 also don't want to modify output operands. */
9134 regno = true_regnum (recog_operand[i]);
9136 || constraints[i][0] == '='
9137 || constraints[i][0] == '+')
9140 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9142 int class = (int) NO_REGS;
9144 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9147 REGNO (reg) = regno;
9148 PUT_MODE (reg, mode);
9150 /* We found a register equal to this operand. Now look for all
9151 alternatives that can accept this register and have not been
9152 assigned a register they can use yet. */
9161 case '=': case '+': case '?':
9162 case '#': case '&': case '!':
9164 case '0': case '1': case '2': case '3': case '4':
9165 case 'm': case '<': case '>': case 'V': case 'o':
9166 case 'E': case 'F': case 'G': case 'H':
9167 case 's': case 'i': case 'n':
9168 case 'I': case 'J': case 'K': case 'L':
9169 case 'M': case 'N': case 'O': case 'P':
9170 #ifdef EXTRA_CONSTRAINT
9171 case 'Q': case 'R': case 'S': case 'T': case 'U':
9174 /* These don't say anything we care about. */
9178 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9183 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9186 case ',': case '\0':
9187 /* See if REGNO fits this alternative, and set it up as the
9188 replacement register if we don't have one for this
9189 alternative yet and the operand being replaced is not
9190 a cheap CONST_INT. */
9191 if (op_alt_regno[i][j] == -1
9192 && reg_fits_class_p (reg, class, 0, mode)
9193 && (GET_CODE (recog_operand[i]) != CONST_INT
9194 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9196 alternative_nregs[j]++;
9197 op_alt_regno[i][j] = regno;
9209 /* Record all alternatives which are better or equal to the currently
9210 matching one in the alternative_order array. */
9211 for (i = j = 0; i < recog_n_alternatives; i++)
9212 if (alternative_reject[i] <= alternative_reject[which_alternative])
9213 alternative_order[j++] = i;
9214 recog_n_alternatives = j;
9216 /* Sort it. Given a small number of alternatives, a dumb algorithm
9217 won't hurt too much. */
9218 for (i = 0; i < recog_n_alternatives - 1; i++)
9221 int best_reject = alternative_reject[alternative_order[i]];
9222 int best_nregs = alternative_nregs[alternative_order[i]];
9225 for (j = i + 1; j < recog_n_alternatives; j++)
9227 int this_reject = alternative_reject[alternative_order[j]];
9228 int this_nregs = alternative_nregs[alternative_order[j]];
9230 if (this_reject < best_reject
9231 || (this_reject == best_reject && this_nregs < best_nregs))
9234 best_reject = this_reject;
9235 best_nregs = this_nregs;
9239 tmp = alternative_order[best];
9240 alternative_order[best] = alternative_order[i];
9241 alternative_order[i] = tmp;
9244 /* Substitute the operands as determined by op_alt_regno for the best
9246 j = alternative_order[0];
9248 /* Pop back to the real obstacks while changing the insn. */
9251 for (i = 0; i < recog_n_operands; i++)
9253 enum machine_mode mode = recog_operand_mode[i];
9254 if (op_alt_regno[i][j] == -1)
9257 validate_change (insn, recog_operand_loc[i],
9258 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9261 for (i = recog_n_dups - 1; i >= 0; i--)
9263 int op = recog_dup_num[i];
9264 enum machine_mode mode = recog_operand_mode[op];
9266 if (op_alt_regno[op][j] == -1)
9269 validate_change (insn, recog_dup_loc[i],
9270 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9273 /* Go back to the obstack we are using for temporary
9275 push_obstacks (&reload_obstack, &reload_obstack);
9277 return apply_change_group ();
9283 /* These two variables are used to pass information from
9284 reload_cse_record_set to reload_cse_check_clobber. */
9286 static int reload_cse_check_clobbered;
9287 static rtx reload_cse_check_src;
9289 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9290 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9291 second argument, which is passed by note_stores, is ignored. */
9294 reload_cse_check_clobber (dest, ignore)
9296 rtx ignore ATTRIBUTE_UNUSED;
9298 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9299 reload_cse_check_clobbered = 1;
9302 /* Record the result of a SET instruction. SET is the set pattern.
9303 BODY is the pattern of the insn that it came from. */
9306 reload_cse_record_set (set, body)
9312 enum machine_mode dest_mode;
9314 dest = SET_DEST (set);
9315 src = SET_SRC (set);
9316 dreg = true_regnum (dest);
9317 sreg = true_regnum (src);
9318 dest_mode = GET_MODE (dest);
9320 /* Some machines don't define AUTO_INC_DEC, but they still use push
9321 instructions. We need to catch that case here in order to
9322 invalidate the stack pointer correctly. Note that invalidating
9323 the stack pointer is different from invalidating DEST. */
9325 while (GET_CODE (x) == SUBREG
9326 || GET_CODE (x) == ZERO_EXTRACT
9327 || GET_CODE (x) == SIGN_EXTRACT
9328 || GET_CODE (x) == STRICT_LOW_PART)
9330 if (push_operand (x, GET_MODE (x)))
9332 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9333 reload_cse_invalidate_rtx (dest, NULL_RTX);
9337 /* We can only handle an assignment to a register, or a store of a
9338 register to a memory location. For other cases, we just clobber
9339 the destination. We also have to just clobber if there are side
9340 effects in SRC or DEST. */
9341 if ((dreg < 0 && GET_CODE (dest) != MEM)
9342 || side_effects_p (src)
9343 || side_effects_p (dest))
9345 reload_cse_invalidate_rtx (dest, NULL_RTX);
9350 /* We don't try to handle values involving CC, because it's a pain
9351 to keep track of when they have to be invalidated. */
9352 if (reg_mentioned_p (cc0_rtx, src)
9353 || reg_mentioned_p (cc0_rtx, dest))
9355 reload_cse_invalidate_rtx (dest, NULL_RTX);
9360 /* If BODY is a PARALLEL, then we need to see whether the source of
9361 SET is clobbered by some other instruction in the PARALLEL. */
9362 if (GET_CODE (body) == PARALLEL)
9366 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9370 x = XVECEXP (body, 0, i);
9374 reload_cse_check_clobbered = 0;
9375 reload_cse_check_src = src;
9376 note_stores (x, reload_cse_check_clobber);
9377 if (reload_cse_check_clobbered)
9379 reload_cse_invalidate_rtx (dest, NULL_RTX);
9389 /* This is an assignment to a register. Update the value we
9390 have stored for the register. */
9395 /* This is a copy from one register to another. Any values
9396 which were valid for SREG are now valid for DREG. If the
9397 mode changes, we use gen_lowpart_common to extract only
9398 the part of the value that is copied. */
9399 reg_values[dreg] = 0;
9400 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9404 if (XEXP (x, 0) == 0)
9406 if (dest_mode == GET_MODE (XEXP (x, 0)))
9408 else if (GET_MODE_BITSIZE (dest_mode)
9409 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9412 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9414 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9419 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9421 /* We've changed DREG, so invalidate any values held by other
9422 registers that depend upon it. */
9423 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9425 /* If this assignment changes more than one hard register,
9426 forget anything we know about the others. */
9427 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9428 reg_values[dreg + i] = 0;
9430 else if (GET_CODE (dest) == MEM)
9432 /* Invalidate conflicting memory locations. */
9433 reload_cse_invalidate_mem (dest);
9435 /* If we're storing a register to memory, add DEST to the list
9437 if (sreg >= 0 && ! side_effects_p (dest))
9438 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9443 /* We should have bailed out earlier. */
9448 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9450 This code might also be useful when reload gave up on reg+reg addresssing
9451 because of clashes between the return register and INDEX_REG_CLASS. */
9453 /* The maximum number of uses of a register we can keep track of to
9454 replace them with reg+reg addressing. */
9455 #define RELOAD_COMBINE_MAX_USES 6
9457 /* INSN is the insn where a register has ben used, and USEP points to the
9458 location of the register within the rtl. */
9459 struct reg_use { rtx insn, *usep; };
9461 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9462 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9463 indicates where it becomes live again.
9464 Otherwise, USE_INDEX is the index of the last encountered use of the
9465 register (which is first among these we have seen since we scan backwards),
9466 OFFSET contains the constant offset that is added to the register in
9467 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9468 last, of these uses.
9469 STORE_RUID is always meaningful if we only want to use a value in a
9470 register in a different place: it denotes the next insn in the insn
9471 stream (i.e. the last ecountered) that sets or clobbers the register. */
9474 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9479 } reg_state[FIRST_PSEUDO_REGISTER];
9481 /* Reverse linear uid. This is increased in reload_combine while scanning
9482 the instructions from last to first. It is used to set last_label_ruid
9483 and the store_ruid / use_ruid fields in reg_state. */
9484 static int reload_combine_ruid;
9486 #define LABEL_LIVE(LABEL) \
9487 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9493 int first_index_reg = 1, last_index_reg = 0;
9495 int last_label_ruid;
9496 int min_labelno, n_labels;
9497 HARD_REG_SET ever_live_at_start, *label_live;
9499 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9500 reload has already used it where appropriate, so there is no use in
9501 trying to generate it now. */
9502 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9505 /* To avoid wasting too much time later searching for an index register,
9506 determine the minimum and maximum index register numbers. */
9507 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9509 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9511 if (! last_index_reg)
9513 first_index_reg = i;
9516 /* If no index register is available, we can quit now. */
9517 if (first_index_reg > last_index_reg)
9520 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9521 information is a bit fuzzy immediately after reload, but it's
9522 still good enough to determine which registers are live at a jump
9524 min_labelno = get_first_label_num ();
9525 n_labels = max_label_num () - min_labelno;
9526 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9527 CLEAR_HARD_REG_SET (ever_live_at_start);
9528 for (i = n_basic_blocks - 1; i >= 0; i--)
9530 insn = BLOCK_HEAD (i);
9531 if (GET_CODE (insn) == CODE_LABEL)
9535 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9536 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9537 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9538 IOR_HARD_REG_SET (ever_live_at_start, live);
9542 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9543 last_label_ruid = reload_combine_ruid = 0;
9544 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9546 reg_state[i].store_ruid = reload_combine_ruid;
9548 reg_state[i].use_index = -1;
9550 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9553 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9557 /* We cannot do our optimization across labels. Invalidating all the use
9558 information we have would be costly, so we just note where the label
9559 is and then later disable any optimization that would cross it. */
9560 if (GET_CODE (insn) == CODE_LABEL)
9561 last_label_ruid = reload_combine_ruid;
9562 if (GET_CODE (insn) == BARRIER)
9564 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9565 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9567 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9569 reload_combine_ruid++;
9571 /* Look for (set (REGX) (CONST_INT))
9572 (set (REGX) (PLUS (REGX) (REGY)))
9574 ... (MEM (REGX)) ...
9576 (set (REGZ) (CONST_INT))
9578 ... (MEM (PLUS (REGZ) (REGY)))... .
9580 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9581 and that we know all uses of REGX before it dies. */
9582 set = single_set (insn);
9584 && GET_CODE (SET_DEST (set)) == REG
9585 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9586 GET_MODE (SET_DEST (set)))
9588 && GET_CODE (SET_SRC (set)) == PLUS
9589 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9590 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9591 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9593 rtx reg = SET_DEST (set);
9594 rtx plus = SET_SRC (set);
9595 rtx base = XEXP (plus, 1);
9596 rtx prev = prev_nonnote_insn (insn);
9597 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9598 int regno = REGNO (reg);
9600 rtx reg_sum = NULL_RTX;
9602 /* Now, we need an index register.
9603 We'll set index_reg to this index register, const_reg to the
9604 register that is to be loaded with the constant
9605 (denoted as REGZ in the substitution illustration above),
9606 and reg_sum to the register-register that we want to use to
9607 substitute uses of REG (typically in MEMs) with.
9608 First check REG and BASE for being index registers;
9609 we can use them even if they are not dead. */
9610 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9611 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9619 /* Otherwise, look for a free index register. Since we have
9620 checked above that neiter REG nor BASE are index registers,
9621 if we find anything at all, it will be different from these
9623 for (i = first_index_reg; i <= last_index_reg; i++)
9625 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9626 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9627 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9628 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9630 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9631 const_reg = index_reg;
9632 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9637 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9638 (REGY), i.e. BASE, is not clobbered before the last use we'll
9641 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9642 && rtx_equal_p (SET_DEST (prev_set), reg)
9643 && reg_state[regno].use_index >= 0
9644 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9649 /* Change destination register and - if necessary - the
9650 constant value in PREV, the constant loading instruction. */
9651 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9652 if (reg_state[regno].offset != const0_rtx)
9653 validate_change (prev,
9654 &SET_SRC (prev_set),
9655 GEN_INT (INTVAL (SET_SRC (prev_set))
9656 + INTVAL (reg_state[regno].offset)),
9658 /* Now for every use of REG that we have recorded, replace REG
9660 for (i = reg_state[regno].use_index;
9661 i < RELOAD_COMBINE_MAX_USES; i++)
9662 validate_change (reg_state[regno].reg_use[i].insn,
9663 reg_state[regno].reg_use[i].usep,
9666 if (apply_change_group ())
9670 /* Delete the reg-reg addition. */
9671 PUT_CODE (insn, NOTE);
9672 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9673 NOTE_SOURCE_FILE (insn) = 0;
9675 if (reg_state[regno].offset != const0_rtx)
9677 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9679 for (np = ®_NOTES (prev); *np; )
9681 if (REG_NOTE_KIND (*np) == REG_EQUAL
9682 || REG_NOTE_KIND (*np) == REG_EQUIV)
9683 *np = XEXP (*np, 1);
9685 np = &XEXP (*np, 1);
9688 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9689 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9694 note_stores (PATTERN (insn), reload_combine_note_store);
9695 if (GET_CODE (insn) == CALL_INSN)
9699 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9701 if (call_used_regs[i])
9703 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9704 reg_state[i].store_ruid = reload_combine_ruid;
9707 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9708 link = XEXP (link, 1))
9710 rtx use = XEXP (link, 0);
9711 int regno = REGNO (XEXP (use, 0));
9712 if (GET_CODE (use) == CLOBBER)
9714 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9715 reg_state[regno].store_ruid = reload_combine_ruid;
9718 reg_state[regno].use_index = -1;
9721 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9723 /* Non-spill registers might be used at the call destination in
9724 some unknown fashion, so we have to mark the unknown use. */
9726 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9727 && JUMP_LABEL (insn))
9728 live = &LABEL_LIVE (JUMP_LABEL (insn));
9730 live = &ever_live_at_start;
9731 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9733 if (TEST_HARD_REG_BIT (*live, i))
9734 reg_state[i].use_index = -1;
9737 reload_combine_note_use (&PATTERN (insn), insn);
9738 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9740 if (REG_NOTE_KIND (note) == REG_INC
9741 && GET_CODE (XEXP (note, 0)) == REG)
9743 int regno = REGNO (XEXP (note, 0));
9745 reg_state[regno].store_ruid = reload_combine_ruid;
9746 reg_state[regno].use_index = -1;
9753 /* Check if DST is a register or a subreg of a register; if it is,
9754 update reg_state[regno].store_ruid and reg_state[regno].use_index
9755 accordingly. Called via note_stores from reload_combine. */
9757 reload_combine_note_store (dst, set)
9762 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9764 if (GET_CODE (dst) == SUBREG)
9766 regno = SUBREG_WORD (dst);
9767 dst = SUBREG_REG (dst);
9769 if (GET_CODE (dst) != REG)
9771 regno += REGNO (dst);
9773 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9774 careful with registers / register parts that are not full words.
9776 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9777 if (GET_CODE (set) != SET
9778 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9779 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9780 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9782 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9784 reg_state[i].use_index = -1;
9785 reg_state[i].store_ruid = reload_combine_ruid;
9790 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9792 reg_state[i].store_ruid = reload_combine_ruid;
9793 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9798 /* XP points to a piece of rtl that has to be checked for any uses of
9800 *XP is the pattern of INSN, or a part of it.
9801 Called from reload_combine, and recursively by itself. */
9803 reload_combine_note_use (xp, insn)
9807 enum rtx_code code = x->code;
9810 rtx offset = const0_rtx; /* For the REG case below. */
9815 if (GET_CODE (SET_DEST (x)) == REG)
9817 reload_combine_note_use (&SET_SRC (x), insn);
9823 if (GET_CODE (SET_DEST (x)) == REG)
9828 /* We are interested in (plus (reg) (const_int)) . */
9829 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9831 offset = XEXP (x, 1);
9836 int regno = REGNO (x);
9839 /* Some spurious USEs of pseudo registers might remain.
9840 Just ignore them. */
9841 if (regno >= FIRST_PSEUDO_REGISTER)
9844 /* If this register is already used in some unknown fashion, we
9846 If we decrement the index from zero to -1, we can't store more
9847 uses, so this register becomes used in an unknown fashion. */
9848 use_index = --reg_state[regno].use_index;
9852 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9854 /* We have found another use for a register that is already
9855 used later. Check if the offsets match; if not, mark the
9856 register as used in an unknown fashion. */
9857 if (! rtx_equal_p (offset, reg_state[regno].offset))
9859 reg_state[regno].use_index = -1;
9865 /* This is the first use of this register we have seen since we
9866 marked it as dead. */
9867 reg_state[regno].offset = offset;
9868 reg_state[regno].use_ruid = reload_combine_ruid;
9870 reg_state[regno].reg_use[use_index].insn = insn;
9871 reg_state[regno].reg_use[use_index].usep = xp;
9879 /* Recursively process the components of X. */
9880 fmt = GET_RTX_FORMAT (code);
9881 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9884 reload_combine_note_use (&XEXP (x, i), insn);
9885 else if (fmt[i] == 'E')
9887 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9888 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9893 /* See if we can reduce the cost of a constant by replacing a move with
9895 /* We cannot do our optimization across labels. Invalidating all the
9896 information about register contents we have would be costly, so we
9897 use last_label_luid (local variable of reload_cse_move2add) to note
9898 where the label is and then later disable any optimization that would
9900 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9901 reg_set_luid[n] is larger than last_label_luid[n] . */
9902 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9903 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9904 reg_mode[n] to be valid.
9905 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9906 has been set to reg_offset[n] in mode reg_mode[n] .
9907 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9908 register n has been set to the sum of reg_offset[n] and register
9909 reg_base_reg[n], calculated in mode reg_mode[n] . */
9910 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9911 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9912 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9913 /* move2add_luid is linearily increased while scanning the instructions
9914 from first to last. It is used to set reg_set_luid in
9915 reload_cse_move2add and move2add_note_store. */
9916 static int move2add_luid;
9919 reload_cse_move2add (first)
9924 int last_label_luid;
9926 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9927 reg_set_luid[i] = 0;
9929 last_label_luid = 0;
9931 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9935 if (GET_CODE (insn) == CODE_LABEL)
9936 last_label_luid = move2add_luid;
9937 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9939 pat = PATTERN (insn);
9940 /* For simplicity, we only perform this optimization on
9941 straightforward SETs. */
9942 if (GET_CODE (pat) == SET
9943 && GET_CODE (SET_DEST (pat)) == REG)
9945 rtx reg = SET_DEST (pat);
9946 int regno = REGNO (reg);
9947 rtx src = SET_SRC (pat);
9949 /* Check if we have valid information on the contents of this
9950 register in the mode of REG. */
9951 /* ??? We don't know how zero / sign extension is handled, hence
9952 we can't go from a narrower to a wider mode. */
9953 if (reg_set_luid[regno] > last_label_luid
9954 && (GET_MODE_SIZE (GET_MODE (reg))
9955 <= GET_MODE_SIZE (reg_mode[regno]))
9956 && GET_CODE (reg_offset[regno]) == CONST_INT)
9958 /* Try to transform (set (REGX) (CONST_INT A))
9960 (set (REGX) (CONST_INT B))
9962 (set (REGX) (CONST_INT A))
9964 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9966 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9969 rtx new_src = GEN_INT (INTVAL (src)
9970 - INTVAL (reg_offset[regno]));
9971 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9972 use (set (reg) (reg)) instead.
9973 We don't delete this insn, nor do we convert it into a
9974 note, to avoid losing register notes or the return
9975 value flag. jump2 already knowns how to get rid of
9977 if (new_src == const0_rtx)
9978 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9979 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9980 && have_add2_insn (GET_MODE (reg)))
9981 success = validate_change (insn, &PATTERN (insn),
9982 gen_add2_insn (reg, new_src), 0);
9983 reg_set_luid[regno] = move2add_luid;
9984 reg_mode[regno] = GET_MODE (reg);
9985 reg_offset[regno] = src;
9989 /* Try to transform (set (REGX) (REGY))
9990 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9993 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9996 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9998 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9999 else if (GET_CODE (src) == REG
10000 && reg_base_reg[regno] == REGNO (src)
10001 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10003 rtx next = next_nonnote_insn (insn);
10006 set = single_set (next);
10009 && SET_DEST (set) == reg
10010 && GET_CODE (SET_SRC (set)) == PLUS
10011 && XEXP (SET_SRC (set), 0) == reg
10012 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10014 rtx src3 = XEXP (SET_SRC (set), 1);
10015 rtx new_src = GEN_INT (INTVAL (src3)
10016 - INTVAL (reg_offset[regno]));
10019 if (new_src == const0_rtx)
10020 /* See above why we create (set (reg) (reg)) here. */
10022 = validate_change (next, &SET_SRC (set), reg, 0);
10023 else if ((rtx_cost (new_src, PLUS)
10024 < 2 + rtx_cost (src3, SET))
10025 && have_add2_insn (GET_MODE (reg)))
10027 = validate_change (next, &PATTERN (next),
10028 gen_add2_insn (reg, new_src), 0);
10031 /* INSN might be the first insn in a basic block
10032 if the preceding insn is a conditional jump
10033 or a possible-throwing call. */
10034 PUT_CODE (insn, NOTE);
10035 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10036 NOTE_SOURCE_FILE (insn) = 0;
10039 reg_set_luid[regno] = move2add_luid;
10040 reg_mode[regno] = GET_MODE (reg);
10041 reg_offset[regno] = src3;
10048 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10050 if (REG_NOTE_KIND (note) == REG_INC
10051 && GET_CODE (XEXP (note, 0)) == REG)
10053 /* Indicate that this register has been recently written to,
10054 but the exact contents are not available. */
10055 int regno = REGNO (XEXP (note, 0));
10056 if (regno < FIRST_PSEUDO_REGISTER)
10058 reg_set_luid[regno] = move2add_luid;
10059 reg_offset[regno] = note;
10063 note_stores (PATTERN (insn), move2add_note_store);
10064 /* If this is a CALL_INSN, all call used registers are stored with
10066 if (GET_CODE (insn) == CALL_INSN)
10068 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10070 if (call_used_regs[i])
10072 reg_set_luid[i] = move2add_luid;
10073 reg_offset[i] = insn; /* Invalidate contents. */
10080 /* SET is a SET or CLOBBER that sets DST.
10081 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10082 Called from reload_cse_move2add via note_stores. */
10084 move2add_note_store (dst, set)
10090 enum machine_mode mode = GET_MODE (dst);
10091 if (GET_CODE (dst) == SUBREG)
10093 regno = SUBREG_WORD (dst);
10094 dst = SUBREG_REG (dst);
10096 if (GET_CODE (dst) != REG)
10099 regno += REGNO (dst);
10101 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10102 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10103 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10104 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10106 rtx src = SET_SRC (set);
10108 reg_mode[regno] = mode;
10109 switch (GET_CODE (src))
10113 rtx src0 = XEXP (src, 0);
10114 if (GET_CODE (src0) == REG)
10116 if (REGNO (src0) != regno
10117 || reg_offset[regno] != const0_rtx)
10119 reg_base_reg[regno] = REGNO (src0);
10120 reg_set_luid[regno] = move2add_luid;
10122 reg_offset[regno] = XEXP (src, 1);
10125 reg_set_luid[regno] = move2add_luid;
10126 reg_offset[regno] = set; /* Invalidate contents. */
10131 reg_base_reg[regno] = REGNO (SET_SRC (set));
10132 reg_offset[regno] = const0_rtx;
10133 reg_set_luid[regno] = move2add_luid;
10137 reg_base_reg[regno] = -1;
10138 reg_offset[regno] = SET_SRC (set);
10139 reg_set_luid[regno] = move2add_luid;
10145 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10147 /* Indicate that this register has been recently written to,
10148 but the exact contents are not available. */
10149 reg_set_luid[i] = move2add_luid;
10150 reg_offset[i] = dst;
10155 #ifdef AUTO_INC_DEC
10157 add_auto_inc_notes (insn, x)
10161 enum rtx_code code = GET_CODE (x);
10165 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10168 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10172 /* Scan all the operand sub-expressions. */
10173 fmt = GET_RTX_FORMAT (code);
10174 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10177 add_auto_inc_notes (insn, XEXP (x, i));
10178 else if (fmt[i] == 'E')
10179 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10180 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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