1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
71 #ifndef REGISTER_MOVE_COST
72 #define REGISTER_MOVE_COST(x, y) 2
75 #ifndef MEMORY_MOVE_COST
76 #define MEMORY_MOVE_COST(x) 4
79 /* During reload_as_needed, element N contains a REG rtx for the hard reg
80 into which reg N has been reloaded (perhaps for a previous insn). */
81 static rtx *reg_last_reload_reg;
83 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84 for an output reload that stores into reg N. */
85 static char *reg_has_output_reload;
87 /* Indicates which hard regs are reload-registers for an output reload
88 in the current insn. */
89 static HARD_REG_SET reg_is_output_reload;
91 /* Element N is the constant value to which pseudo reg N is equivalent,
92 or zero if pseudo reg N is not equivalent to a constant.
93 find_reloads looks at this in order to replace pseudo reg N
94 with the constant it stands for. */
95 rtx *reg_equiv_constant;
97 /* Element N is a memory location to which pseudo reg N is equivalent,
98 prior to any register elimination (such as frame pointer to stack
99 pointer). Depending on whether or not it is a valid address, this value
100 is transferred to either reg_equiv_address or reg_equiv_mem. */
101 rtx *reg_equiv_memory_loc;
103 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104 This is used when the address is not valid as a memory address
105 (because its displacement is too big for the machine.) */
106 rtx *reg_equiv_address;
108 /* Element N is the memory slot to which pseudo reg N is equivalent,
109 or zero if pseudo reg N is not equivalent to a memory slot. */
112 /* Widest width in which each pseudo reg is referred to (via subreg). */
113 static int *reg_max_ref_width;
115 /* Element N is the insn that initialized reg N from its equivalent
116 constant or memory slot. */
117 static rtx *reg_equiv_init;
119 /* During reload_as_needed, element N contains the last pseudo regno
120 reloaded into the Nth reload register. This vector is in parallel
121 with spill_regs. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 the Nth reload register was last used. This vector is in parallel
128 with spill_regs, and its contents are significant only when
129 reg_reloaded_contents is significant. */
130 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
132 /* Number of spill-regs so far; number of valid elements of spill_regs. */
135 /* In parallel with spill_regs, contains REG rtx's for those regs.
136 Holds the last rtx used for any given reg, or 0 if it has never
137 been used for spilling yet. This rtx is reused, provided it has
139 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
141 /* In parallel with spill_regs, contains nonzero for a spill reg
142 that was stored after the last time it was used.
143 The precise value is the insn generated to do the store. */
144 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs. */
150 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
152 /* This reg set indicates registers that may not be used for retrying global
153 allocation. The registers that may not be used include all spill registers
154 and the frame pointer (if we are using one). */
155 HARD_REG_SET forbidden_regs;
157 /* This reg set indicates registers that are not good for spill registers.
158 They will not be used to complete groups of spill registers. This includes
159 all fixed registers, registers that may be eliminated, and, if
160 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
162 (spill_reg_order prevents these registers from being used to start a
164 static HARD_REG_SET bad_spill_regs;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `spills' is the number of
168 elements that are actually valid; new ones are added at the end. */
169 static short spill_regs[FIRST_PSEUDO_REGISTER];
171 /* Describes order of preference for putting regs into spill_regs.
172 Contains the numbers of all the hard regs, in order most preferred first.
173 This order is different for each function.
174 It is set up by order_regs_for_reload.
175 Empty elements at the end contain -1. */
176 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
178 /* 1 for a hard register that appears explicitly in the rtl
179 (for example, function value registers, special registers
180 used by insns, structure value pointer registers). */
181 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
183 /* Indicates if a register was counted against the need for
184 groups. 0 means it can count against max_nongroup instead. */
185 static HARD_REG_SET counted_for_groups;
187 /* Indicates if a register was counted against the need for
188 non-groups. 0 means it can become part of a new group.
189 During choose_reload_regs, 1 here means don't use this reg
190 as part of a group, even if it seems to be otherwise ok. */
191 static HARD_REG_SET counted_for_nongroups;
193 /* Nonzero if indirect addressing is supported on the machine; this means
194 that spilling (REG n) does not require reloading it into a register in
195 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
196 value indicates the level of indirect addressing supported, e.g., two
197 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
200 static char spill_indirect_levels;
202 /* Nonzero if indirect addressing is supported when the innermost MEM is
203 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
204 which these are valid is the same as spill_indirect_levels, above. */
206 char indirect_symref_ok;
208 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
210 char double_reg_address_ok;
212 /* Record the stack slot for each spilled hard register. */
214 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
216 /* Width allocated so far for that stack slot. */
218 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
220 /* Indexed by register class and basic block number, nonzero if there is
221 any need for a spill register of that class in that basic block.
222 The pointer is 0 if we did stupid allocation and don't know
223 the structure of basic blocks. */
225 char *basic_block_needs[N_REG_CLASSES];
227 /* First uid used by insns created by reload in this function.
228 Used in find_equiv_reg. */
229 int reload_first_uid;
231 /* Flag set by local-alloc or global-alloc if anything is live in
232 a call-clobbered reg across calls. */
234 int caller_save_needed;
236 /* Set to 1 while reload_as_needed is operating.
237 Required by some machines to handle any generated moves differently. */
239 int reload_in_progress = 0;
241 /* These arrays record the insn_code of insns that may be needed to
242 perform input and output reloads of special objects. They provide a
243 place to pass a scratch register. */
245 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
246 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
248 /* This obstack is used for allocation of rtl during register elimination.
249 The allocated storage can be freed once find_reloads has processed the
252 struct obstack reload_obstack;
253 char *reload_firstobj;
255 #define obstack_chunk_alloc xmalloc
256 #define obstack_chunk_free free
258 /* List of labels that must never be deleted. */
259 extern rtx forced_labels;
261 /* This structure is used to record information about register eliminations.
262 Each array entry describes one possible way of eliminating a register
263 in favor of another. If there is more than one way of eliminating a
264 particular register, the most preferred should be specified first. */
266 static struct elim_table
268 int from; /* Register number to be eliminated. */
269 int to; /* Register number used as replacement. */
270 int initial_offset; /* Initial difference between values. */
271 int can_eliminate; /* Non-zero if this elimination can be done. */
272 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
273 insns made by reload. */
274 int offset; /* Current offset between the two regs. */
275 int max_offset; /* Maximum offset between the two regs. */
276 int previous_offset; /* Offset at end of previous insn. */
277 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
278 rtx from_rtx; /* REG rtx for the register to be eliminated.
279 We cannot simply compare the number since
280 we might then spuriously replace a hard
281 register corresponding to a pseudo
282 assigned to the reg to be eliminated. */
283 rtx to_rtx; /* REG rtx for the replacement. */
286 /* If a set of eliminable registers was specified, define the table from it.
287 Otherwise, default to the normal case of the frame pointer being
288 replaced by the stack pointer. */
290 #ifdef ELIMINABLE_REGS
293 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
296 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
298 /* Record the number of pending eliminations that have an offset not equal
299 to their initial offset. If non-zero, we use a new copy of each
300 replacement result in any insns encountered. */
301 static int num_not_at_initial_offset;
303 /* Count the number of registers that we may be able to eliminate. */
304 static int num_eliminable;
306 /* For each label, we record the offset of each elimination. If we reach
307 a label by more than one path and an offset differs, we cannot do the
308 elimination. This information is indexed by the number of the label.
309 The first table is an array of flags that records whether we have yet
310 encountered a label and the second table is an array of arrays, one
311 entry in the latter array for each elimination. */
313 static char *offsets_known_at;
314 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
316 /* Number of labels in the current function. */
318 static int num_labels;
320 struct hard_reg_n_uses { int regno; int uses; };
322 static int possible_group_p PROTO((int, int *));
323 static void count_possible_groups PROTO((int *, enum machine_mode *,
325 static int modes_equiv_for_class_p PROTO((enum machine_mode,
328 static void spill_failure PROTO((rtx));
329 static int new_spill_reg PROTO((int, int, int *, int *, int,
331 static void delete_dead_insn PROTO((rtx));
332 static void alter_reg PROTO((int, int));
333 static void set_label_offsets PROTO((rtx, rtx, int));
334 static int eliminate_regs_in_insn PROTO((rtx, int));
335 static void mark_not_eliminable PROTO((rtx, rtx));
336 static int spill_hard_reg PROTO((int, int, FILE *, int));
337 static void scan_paradoxical_subregs PROTO((rtx));
338 static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
339 struct hard_reg_n_uses *));
340 static void order_regs_for_reload PROTO((void));
341 static void reload_as_needed PROTO((rtx, int));
342 static void forget_old_reloads_1 PROTO((rtx));
343 static int reload_reg_class_lower PROTO((short *, short *));
344 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
346 static int reload_reg_free_p PROTO((int, int, enum reload_type));
347 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
348 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
349 static int allocate_reload_reg PROTO((int, rtx, int, int));
350 static void choose_reload_regs PROTO((rtx, rtx));
351 static void merge_assigned_reloads PROTO((rtx));
352 static void emit_reload_insns PROTO((rtx));
353 static void delete_output_reload PROTO((rtx, int, rtx));
354 static void inc_for_reload PROTO((rtx, rtx, int));
355 static int constraint_accepts_reg_p PROTO((char *, rtx));
356 static int count_occurrences PROTO((rtx, rtx));
358 /* Initialize the reload pass once per compilation. */
365 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
366 Set spill_indirect_levels to the number of levels such addressing is
367 permitted, zero if it is not permitted at all. */
370 = gen_rtx (MEM, Pmode,
371 gen_rtx (PLUS, Pmode,
372 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
374 spill_indirect_levels = 0;
376 while (memory_address_p (QImode, tem))
378 spill_indirect_levels++;
379 tem = gen_rtx (MEM, Pmode, tem);
382 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
384 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
385 indirect_symref_ok = memory_address_p (QImode, tem);
387 /* See if reg+reg is a valid (and offsettable) address. */
389 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
391 tem = gen_rtx (PLUS, Pmode,
392 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
393 gen_rtx (REG, Pmode, i));
394 /* This way, we make sure that reg+reg is an offsettable address. */
395 tem = plus_constant (tem, 4);
397 if (memory_address_p (QImode, tem))
399 double_reg_address_ok = 1;
404 /* Initialize obstack for our rtl allocation. */
405 gcc_obstack_init (&reload_obstack);
406 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
409 /* Main entry point for the reload pass.
411 FIRST is the first insn of the function being compiled.
413 GLOBAL nonzero means we were called from global_alloc
414 and should attempt to reallocate any pseudoregs that we
415 displace from hard regs we will use for reloads.
416 If GLOBAL is zero, we do not have enough information to do that,
417 so any pseudo reg that is spilled must go to the stack.
419 DUMPFILE is the global-reg debugging dump file stream, or 0.
420 If it is nonzero, messages are written to it to describe
421 which registers are seized as reload regs, which pseudo regs
422 are spilled from them, and where the pseudo regs are reallocated to.
424 Return value is nonzero if reload failed
425 and we must not do any more for this function. */
428 reload (first, global, dumpfile)
436 register struct elim_table *ep;
438 int something_changed;
439 int something_needs_reloads;
440 int something_needs_elimination;
441 int new_basic_block_needs;
442 enum reg_class caller_save_spill_class = NO_REGS;
443 int caller_save_group_size = 1;
445 /* Nonzero means we couldn't get enough spill regs. */
448 /* The basic block number currently being processed for INSN. */
451 /* Make sure even insns with volatile mem refs are recognizable. */
454 /* Enable find_equiv_reg to distinguish insns made by reload. */
455 reload_first_uid = get_max_uid ();
457 for (i = 0; i < N_REG_CLASSES; i++)
458 basic_block_needs[i] = 0;
460 #ifdef SECONDARY_MEMORY_NEEDED
461 /* Initialize the secondary memory table. */
462 clear_secondary_mem ();
465 /* Remember which hard regs appear explicitly
466 before we merge into `regs_ever_live' the ones in which
467 pseudo regs have been allocated. */
468 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
470 /* We don't have a stack slot for any spill reg yet. */
471 bzero (spill_stack_slot, sizeof spill_stack_slot);
472 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
474 /* Initialize the save area information for caller-save, in case some
478 /* Compute which hard registers are now in use
479 as homes for pseudo registers.
480 This is done here rather than (eg) in global_alloc
481 because this point is reached even if not optimizing. */
483 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
486 /* Make sure that the last insn in the chain
487 is not something that needs reloading. */
488 emit_note (NULL_PTR, NOTE_INSN_DELETED);
490 /* Find all the pseudo registers that didn't get hard regs
491 but do have known equivalent constants or memory slots.
492 These include parameters (known equivalent to parameter slots)
493 and cse'd or loop-moved constant memory addresses.
495 Record constant equivalents in reg_equiv_constant
496 so they will be substituted by find_reloads.
497 Record memory equivalents in reg_mem_equiv so they can
498 be substituted eventually by altering the REG-rtx's. */
500 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
501 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
502 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
503 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
504 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
505 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
506 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
507 bzero (reg_equiv_init, max_regno * sizeof (rtx));
508 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
509 bzero (reg_equiv_address, max_regno * sizeof (rtx));
510 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
511 bzero (reg_max_ref_width, max_regno * sizeof (int));
513 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
514 Also find all paradoxical subregs
515 and find largest such for each pseudo. */
517 for (insn = first; insn; insn = NEXT_INSN (insn))
519 rtx set = single_set (insn);
521 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
523 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
525 #ifdef LEGITIMATE_PIC_OPERAND_P
526 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
527 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
531 rtx x = XEXP (note, 0);
532 i = REGNO (SET_DEST (set));
533 if (i > LAST_VIRTUAL_REGISTER)
535 if (GET_CODE (x) == MEM)
536 reg_equiv_memory_loc[i] = x;
537 else if (CONSTANT_P (x))
539 if (LEGITIMATE_CONSTANT_P (x))
540 reg_equiv_constant[i] = x;
542 reg_equiv_memory_loc[i]
543 = force_const_mem (GET_MODE (SET_DEST (set)), x);
548 /* If this register is being made equivalent to a MEM
549 and the MEM is not SET_SRC, the equivalencing insn
550 is one with the MEM as a SET_DEST and it occurs later.
551 So don't mark this insn now. */
552 if (GET_CODE (x) != MEM
553 || rtx_equal_p (SET_SRC (set), x))
554 reg_equiv_init[i] = insn;
559 /* If this insn is setting a MEM from a register equivalent to it,
560 this is the equivalencing insn. */
561 else if (set && GET_CODE (SET_DEST (set)) == MEM
562 && GET_CODE (SET_SRC (set)) == REG
563 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
564 && rtx_equal_p (SET_DEST (set),
565 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
566 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
568 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
569 scan_paradoxical_subregs (PATTERN (insn));
572 /* Does this function require a frame pointer? */
574 frame_pointer_needed = (! flag_omit_frame_pointer
575 #ifdef EXIT_IGNORE_STACK
576 /* ?? If EXIT_IGNORE_STACK is set, we will not save
577 and restore sp for alloca. So we can't eliminate
578 the frame pointer in that case. At some point,
579 we should improve this by emitting the
580 sp-adjusting insns for this case. */
581 || (current_function_calls_alloca
582 && EXIT_IGNORE_STACK)
584 || FRAME_POINTER_REQUIRED);
588 /* Initialize the table of registers to eliminate. The way we do this
589 depends on how the eliminable registers were defined. */
590 #ifdef ELIMINABLE_REGS
591 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
593 ep->can_eliminate = ep->can_eliminate_previous
594 = (CAN_ELIMINATE (ep->from, ep->to)
595 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
598 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
599 = ! frame_pointer_needed;
602 /* Count the number of eliminable registers and build the FROM and TO
603 REG rtx's. Note that code in gen_rtx will cause, e.g.,
604 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
605 We depend on this. */
606 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
608 num_eliminable += ep->can_eliminate;
609 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
610 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
613 num_labels = max_label_num () - get_first_label_num ();
615 /* Allocate the tables used to store offset information at labels. */
616 offsets_known_at = (char *) alloca (num_labels);
618 = (int (*)[NUM_ELIMINABLE_REGS])
619 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
621 offsets_known_at -= get_first_label_num ();
622 offsets_at -= get_first_label_num ();
624 /* Alter each pseudo-reg rtx to contain its hard reg number.
625 Assign stack slots to the pseudos that lack hard regs or equivalents.
626 Do not touch virtual registers. */
628 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
631 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
632 because the stack size may be a part of the offset computation for
633 register elimination. */
634 assign_stack_local (BLKmode, 0, 0);
636 /* If we have some registers we think can be eliminated, scan all insns to
637 see if there is an insn that sets one of these registers to something
638 other than itself plus a constant. If so, the register cannot be
639 eliminated. Doing this scan here eliminates an extra pass through the
640 main reload loop in the most common case where register elimination
642 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
643 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
644 || GET_CODE (insn) == CALL_INSN)
645 note_stores (PATTERN (insn), mark_not_eliminable);
647 #ifndef REGISTER_CONSTRAINTS
648 /* If all the pseudo regs have hard regs,
649 except for those that are never referenced,
650 we know that no reloads are needed. */
651 /* But that is not true if there are register constraints, since
652 in that case some pseudos might be in the wrong kind of hard reg. */
654 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
655 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
658 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
662 /* Compute the order of preference for hard registers to spill.
663 Store them by decreasing preference in potential_reload_regs. */
665 order_regs_for_reload ();
667 /* So far, no hard regs have been spilled. */
669 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
670 spill_reg_order[i] = -1;
672 /* On most machines, we can't use any register explicitly used in the
673 rtl as a spill register. But on some, we have to. Those will have
674 taken care to keep the life of hard regs as short as possible. */
676 #ifdef SMALL_REGISTER_CLASSES
677 CLEAR_HARD_REG_SET (forbidden_regs);
679 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
682 /* Spill any hard regs that we know we can't eliminate. */
683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
684 if (! ep->can_eliminate)
686 spill_hard_reg (ep->from, global, dumpfile, 1);
687 regs_ever_live[ep->from] = 1;
691 for (i = 0; i < N_REG_CLASSES; i++)
693 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
694 bzero (basic_block_needs[i], n_basic_blocks);
697 /* From now on, we need to emit any moves without making new pseudos. */
698 reload_in_progress = 1;
700 /* This loop scans the entire function each go-round
701 and repeats until one repetition spills no additional hard regs. */
703 /* This flag is set when a pseudo reg is spilled,
704 to require another pass. Note that getting an additional reload
705 reg does not necessarily imply any pseudo reg was spilled;
706 sometimes we find a reload reg that no pseudo reg was allocated in. */
707 something_changed = 1;
708 /* This flag is set if there are any insns that require reloading. */
709 something_needs_reloads = 0;
710 /* This flag is set if there are any insns that require register
712 something_needs_elimination = 0;
713 while (something_changed)
717 /* For each class, number of reload regs needed in that class.
718 This is the maximum over all insns of the needs in that class
719 of the individual insn. */
720 int max_needs[N_REG_CLASSES];
721 /* For each class, size of group of consecutive regs
722 that is needed for the reloads of this class. */
723 int group_size[N_REG_CLASSES];
724 /* For each class, max number of consecutive groups needed.
725 (Each group contains group_size[CLASS] consecutive registers.) */
726 int max_groups[N_REG_CLASSES];
727 /* For each class, max number needed of regs that don't belong
728 to any of the groups. */
729 int max_nongroups[N_REG_CLASSES];
730 /* For each class, the machine mode which requires consecutive
731 groups of regs of that class.
732 If two different modes ever require groups of one class,
733 they must be the same size and equally restrictive for that class,
734 otherwise we can't handle the complexity. */
735 enum machine_mode group_mode[N_REG_CLASSES];
736 /* Record the insn where each maximum need is first found. */
737 rtx max_needs_insn[N_REG_CLASSES];
738 rtx max_groups_insn[N_REG_CLASSES];
739 rtx max_nongroups_insn[N_REG_CLASSES];
741 int starting_frame_size = get_frame_size ();
742 static char *reg_class_names[] = REG_CLASS_NAMES;
744 something_changed = 0;
745 bzero (max_needs, sizeof max_needs);
746 bzero (max_groups, sizeof max_groups);
747 bzero (max_nongroups, sizeof max_nongroups);
748 bzero (max_needs_insn, sizeof max_needs_insn);
749 bzero (max_groups_insn, sizeof max_groups_insn);
750 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
751 bzero (group_size, sizeof group_size);
752 for (i = 0; i < N_REG_CLASSES; i++)
753 group_mode[i] = VOIDmode;
755 /* Keep track of which basic blocks are needing the reloads. */
758 /* Remember whether any element of basic_block_needs
759 changes from 0 to 1 in this pass. */
760 new_basic_block_needs = 0;
762 /* Reset all offsets on eliminable registers to their initial values. */
763 #ifdef ELIMINABLE_REGS
764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
766 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
767 ep->previous_offset = ep->offset
768 = ep->max_offset = ep->initial_offset;
771 #ifdef INITIAL_FRAME_POINTER_OFFSET
772 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
774 if (!FRAME_POINTER_REQUIRED)
776 reg_eliminate[0].initial_offset = 0;
778 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
779 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
782 num_not_at_initial_offset = 0;
784 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
786 /* Set a known offset for each forced label to be at the initial offset
787 of each elimination. We do this because we assume that all
788 computed jumps occur from a location where each elimination is
789 at its initial offset. */
791 for (x = forced_labels; x; x = XEXP (x, 1))
793 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
795 /* For each pseudo register that has an equivalent location defined,
796 try to eliminate any eliminable registers (such as the frame pointer)
797 assuming initial offsets for the replacement register, which
800 If the resulting location is directly addressable, substitute
801 the MEM we just got directly for the old REG.
803 If it is not addressable but is a constant or the sum of a hard reg
804 and constant, it is probably not addressable because the constant is
805 out of range, in that case record the address; we will generate
806 hairy code to compute the address in a register each time it is
809 If the location is not addressable, but does not have one of the
810 above forms, assign a stack slot. We have to do this to avoid the
811 potential of producing lots of reloads if, e.g., a location involves
812 a pseudo that didn't get a hard register and has an equivalent memory
813 location that also involves a pseudo that didn't get a hard register.
815 Perhaps at some point we will improve reload_when_needed handling
816 so this problem goes away. But that's very hairy. */
818 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
819 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
821 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
823 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
825 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
826 else if (CONSTANT_P (XEXP (x, 0))
827 || (GET_CODE (XEXP (x, 0)) == PLUS
828 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
829 && (REGNO (XEXP (XEXP (x, 0), 0))
830 < FIRST_PSEUDO_REGISTER)
831 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
832 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
835 /* Make a new stack slot. Then indicate that something
836 changed so we go back and recompute offsets for
837 eliminable registers because the allocation of memory
838 below might change some offset. reg_equiv_{mem,address}
839 will be set up for this pseudo on the next pass around
841 reg_equiv_memory_loc[i] = 0;
842 reg_equiv_init[i] = 0;
844 something_changed = 1;
848 /* If we allocated another pseudo to the stack, redo elimination
850 if (something_changed)
853 /* If caller-saves needs a group, initialize the group to include
854 the size and mode required for caller-saves. */
856 if (caller_save_group_size > 1)
858 group_mode[(int) caller_save_spill_class] = Pmode;
859 group_size[(int) caller_save_spill_class] = caller_save_group_size;
862 /* Compute the most additional registers needed by any instruction.
863 Collect information separately for each class of regs. */
865 for (insn = first; insn; insn = NEXT_INSN (insn))
867 if (global && this_block + 1 < n_basic_blocks
868 && insn == basic_block_head[this_block+1])
871 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
872 might include REG_LABEL), we need to see what effects this
873 has on the known offsets at labels. */
875 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
876 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
877 && REG_NOTES (insn) != 0))
878 set_label_offsets (insn, insn, 0);
880 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
882 /* Nonzero means don't use a reload reg that overlaps
883 the place where a function value can be returned. */
884 rtx avoid_return_reg = 0;
886 rtx old_body = PATTERN (insn);
887 int old_code = INSN_CODE (insn);
888 rtx old_notes = REG_NOTES (insn);
889 int did_elimination = 0;
890 int max_total_input_groups = 0, max_total_output_groups = 0;
892 /* To compute the number of reload registers of each class
893 needed for an insn, we must similate what choose_reload_regs
894 can do. We do this by splitting an insn into an "input" and
895 an "output" part. RELOAD_OTHER reloads are used in both.
896 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
897 which must be live over the entire input section of reloads,
898 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
899 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
902 The registers needed for output are RELOAD_OTHER and
903 RELOAD_FOR_OUTPUT, which are live for the entire output
904 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
905 reloads for each operand.
907 The total number of registers needed is the maximum of the
908 inputs and outputs. */
910 /* These just count RELOAD_OTHER. */
911 int insn_needs[N_REG_CLASSES];
912 int insn_groups[N_REG_CLASSES];
913 int insn_total_groups = 0;
915 /* Count RELOAD_FOR_INPUT reloads. */
916 int insn_needs_for_inputs[N_REG_CLASSES];
917 int insn_groups_for_inputs[N_REG_CLASSES];
918 int insn_total_groups_for_inputs = 0;
920 /* Count RELOAD_FOR_OUTPUT reloads. */
921 int insn_needs_for_outputs[N_REG_CLASSES];
922 int insn_groups_for_outputs[N_REG_CLASSES];
923 int insn_total_groups_for_outputs = 0;
925 /* Count RELOAD_FOR_INSN reloads. */
926 int insn_needs_for_insn[N_REG_CLASSES];
927 int insn_groups_for_insn[N_REG_CLASSES];
928 int insn_total_groups_for_insn = 0;
930 /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
931 int insn_needs_for_other_addr[N_REG_CLASSES];
932 int insn_groups_for_other_addr[N_REG_CLASSES];
933 int insn_total_groups_for_other_addr = 0;
935 /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
936 int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
937 int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
938 int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS];
940 /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
941 int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
942 int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
943 int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS];
945 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
946 int insn_needs_for_op_addr[N_REG_CLASSES];
947 int insn_groups_for_op_addr[N_REG_CLASSES];
948 int insn_total_groups_for_op_addr = 0;
950 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
951 looks for non-strict memory addresses. */
952 /* Optimization: a bit-field instruction whose field
953 happens to be a byte or halfword in memory
954 can be changed to a move instruction. */
956 if (GET_CODE (PATTERN (insn)) == SET)
958 rtx dest = SET_DEST (PATTERN (insn));
959 rtx src = SET_SRC (PATTERN (insn));
961 if (GET_CODE (dest) == ZERO_EXTRACT
962 || GET_CODE (dest) == SIGN_EXTRACT)
963 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
964 if (GET_CODE (src) == ZERO_EXTRACT
965 || GET_CODE (src) == SIGN_EXTRACT)
966 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
970 /* If needed, eliminate any eliminable registers. */
972 did_elimination = eliminate_regs_in_insn (insn, 0);
974 #ifdef SMALL_REGISTER_CLASSES
975 /* Set avoid_return_reg if this is an insn
976 that might use the value of a function call. */
977 if (GET_CODE (insn) == CALL_INSN)
979 if (GET_CODE (PATTERN (insn)) == SET)
980 after_call = SET_DEST (PATTERN (insn));
981 else if (GET_CODE (PATTERN (insn)) == PARALLEL
982 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
983 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
987 else if (after_call != 0
988 && !(GET_CODE (PATTERN (insn)) == SET
989 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
991 if (reg_mentioned_p (after_call, PATTERN (insn)))
992 avoid_return_reg = after_call;
995 #endif /* SMALL_REGISTER_CLASSES */
997 /* Analyze the instruction. */
998 find_reloads (insn, 0, spill_indirect_levels, global,
1001 /* Remember for later shortcuts which insns had any reloads or
1002 register eliminations.
1004 One might think that it would be worthwhile to mark insns
1005 that need register replacements but not reloads, but this is
1006 not safe because find_reloads may do some manipulation of
1007 the insn (such as swapping commutative operands), which would
1008 be lost when we restore the old pattern after register
1009 replacement. So the actions of find_reloads must be redone in
1010 subsequent passes or in reload_as_needed.
1012 However, it is safe to mark insns that need reloads
1013 but not register replacement. */
1015 PUT_MODE (insn, (did_elimination ? QImode
1016 : n_reloads ? HImode
1017 : GET_MODE (insn) == DImode ? DImode
1020 /* Discard any register replacements done. */
1021 if (did_elimination)
1023 obstack_free (&reload_obstack, reload_firstobj);
1024 PATTERN (insn) = old_body;
1025 INSN_CODE (insn) = old_code;
1026 REG_NOTES (insn) = old_notes;
1027 something_needs_elimination = 1;
1030 /* If this insn has no reloads, we need not do anything except
1031 in the case of a CALL_INSN when we have caller-saves and
1032 caller-save needs reloads. */
1035 && ! (GET_CODE (insn) == CALL_INSN
1036 && caller_save_spill_class != NO_REGS))
1039 something_needs_reloads = 1;
1041 for (i = 0; i < N_REG_CLASSES; i++)
1043 insn_needs[i] = 0, insn_groups[i] = 0;
1044 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1045 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1046 insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0;
1047 insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0;
1048 insn_needs_for_other_addr[i] = 0;
1049 insn_groups_for_other_addr[i] = 0;
1052 for (i = 0; i < reload_n_operands; i++)
1054 insn_total_groups_for_in_addr[i] = 0;
1055 insn_total_groups_for_out_addr[i] = 0;
1057 for (j = 0; j < N_REG_CLASSES; j++)
1059 insn_needs_for_in_addr[i][j] = 0;
1060 insn_needs_for_out_addr[i][j] = 0;
1061 insn_groups_for_in_addr[i][j] = 0;
1062 insn_groups_for_out_addr[i][j] = 0;
1066 /* Count each reload once in every class
1067 containing the reload's own class. */
1069 for (i = 0; i < n_reloads; i++)
1071 register enum reg_class *p;
1072 enum reg_class class = reload_reg_class[i];
1074 enum machine_mode mode;
1077 int *this_total_groups;
1079 /* Don't count the dummy reloads, for which one of the
1080 regs mentioned in the insn can be used for reloading.
1081 Don't count optional reloads.
1082 Don't count reloads that got combined with others. */
1083 if (reload_reg_rtx[i] != 0
1084 || reload_optional[i] != 0
1085 || (reload_out[i] == 0 && reload_in[i] == 0
1086 && ! reload_secondary_p[i]))
1089 /* Show that a reload register of this class is needed
1090 in this basic block. We do not use insn_needs and
1091 insn_groups because they are overly conservative for
1093 if (global && ! basic_block_needs[(int) class][this_block])
1095 basic_block_needs[(int) class][this_block] = 1;
1096 new_basic_block_needs = 1;
1099 /* Decide which time-of-use to count this reload for. */
1100 switch (reload_when_needed[i])
1103 this_needs = insn_needs;
1104 this_groups = insn_groups;
1105 this_total_groups = &insn_total_groups;
1108 case RELOAD_FOR_INPUT:
1109 this_needs = insn_needs_for_inputs;
1110 this_groups = insn_groups_for_inputs;
1111 this_total_groups = &insn_total_groups_for_inputs;
1114 case RELOAD_FOR_OUTPUT:
1115 this_needs = insn_needs_for_outputs;
1116 this_groups = insn_groups_for_outputs;
1117 this_total_groups = &insn_total_groups_for_outputs;
1120 case RELOAD_FOR_INSN:
1121 this_needs = insn_needs_for_insn;
1122 this_groups = insn_groups_for_outputs;
1123 this_total_groups = &insn_total_groups_for_insn;
1126 case RELOAD_FOR_OTHER_ADDRESS:
1127 this_needs = insn_needs_for_other_addr;
1128 this_groups = insn_groups_for_other_addr;
1129 this_total_groups = &insn_total_groups_for_other_addr;
1132 case RELOAD_FOR_INPUT_ADDRESS:
1133 this_needs = insn_needs_for_in_addr[reload_opnum[i]];
1134 this_groups = insn_groups_for_in_addr[reload_opnum[i]];
1136 = &insn_total_groups_for_in_addr[reload_opnum[i]];
1139 case RELOAD_FOR_OUTPUT_ADDRESS:
1140 this_needs = insn_needs_for_out_addr[reload_opnum[i]];
1141 this_groups = insn_groups_for_out_addr[reload_opnum[i]];
1143 = &insn_total_groups_for_out_addr[reload_opnum[i]];
1146 case RELOAD_FOR_OPERAND_ADDRESS:
1147 this_needs = insn_needs_for_op_addr;
1148 this_groups = insn_groups_for_op_addr;
1149 this_total_groups = &insn_total_groups_for_op_addr;
1153 mode = reload_inmode[i];
1154 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1155 mode = reload_outmode[i];
1156 size = CLASS_MAX_NREGS (class, mode);
1159 enum machine_mode other_mode, allocate_mode;
1161 /* Count number of groups needed separately from
1162 number of individual regs needed. */
1163 this_groups[(int) class]++;
1164 p = reg_class_superclasses[(int) class];
1165 while (*p != LIM_REG_CLASSES)
1166 this_groups[(int) *p++]++;
1167 (*this_total_groups)++;
1169 /* Record size and mode of a group of this class. */
1170 /* If more than one size group is needed,
1171 make all groups the largest needed size. */
1172 if (group_size[(int) class] < size)
1174 other_mode = group_mode[(int) class];
1175 allocate_mode = mode;
1177 group_size[(int) class] = size;
1178 group_mode[(int) class] = mode;
1183 allocate_mode = group_mode[(int) class];
1186 /* Crash if two dissimilar machine modes both need
1187 groups of consecutive regs of the same class. */
1189 if (other_mode != VOIDmode
1190 && other_mode != allocate_mode
1191 && ! modes_equiv_for_class_p (allocate_mode,
1198 this_needs[(int) class] += 1;
1199 p = reg_class_superclasses[(int) class];
1200 while (*p != LIM_REG_CLASSES)
1201 this_needs[(int) *p++] += 1;
1207 /* All reloads have been counted for this insn;
1208 now merge the various times of use.
1209 This sets insn_needs, etc., to the maximum total number
1210 of registers needed at any point in this insn. */
1212 for (i = 0; i < N_REG_CLASSES; i++)
1214 int in_max, out_max;
1216 for (in_max = 0, out_max = 0, j = 0;
1217 j < reload_n_operands; j++)
1219 in_max = MAX (in_max, insn_needs_for_in_addr[j][i]);
1220 out_max = MAX (out_max, insn_needs_for_out_addr[j][i]);
1223 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1224 and operand addresses but not things used to reload them.
1225 Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1226 conflict with things needed to reload inputs or
1229 in_max = MAX (in_max, insn_needs_for_op_addr[i]);
1230 out_max = MAX (out_max, insn_needs_for_insn[i]);
1232 insn_needs_for_inputs[i]
1233 = MAX (insn_needs_for_inputs[i]
1234 + insn_needs_for_op_addr[i]
1235 + insn_needs_for_insn[i],
1236 in_max + insn_needs_for_inputs[i]);
1238 insn_needs_for_outputs[i] += out_max;
1239 insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i],
1240 insn_needs_for_outputs[i]),
1241 insn_needs_for_other_addr[i]);
1243 for (in_max = 0, out_max = 0, j = 0;
1244 j < reload_n_operands; j++)
1246 in_max = MAX (in_max, insn_groups_for_in_addr[j][i]);
1247 out_max = MAX (out_max, insn_groups_for_out_addr[j][i]);
1250 in_max = MAX (in_max, insn_groups_for_op_addr[i]);
1251 out_max = MAX (out_max, insn_groups_for_insn[i]);
1253 insn_groups_for_inputs[i]
1254 = MAX (insn_groups_for_inputs[i]
1255 + insn_groups_for_op_addr[i]
1256 + insn_groups_for_insn[i],
1257 in_max + insn_groups_for_inputs[i]);
1259 insn_groups_for_outputs[i] += out_max;
1260 insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i],
1261 insn_groups_for_outputs[i]),
1262 insn_groups_for_other_addr[i]);
1265 for (i = 0; i < reload_n_operands; i++)
1267 max_total_input_groups
1268 = MAX (max_total_input_groups,
1269 insn_total_groups_for_in_addr[i]);
1270 max_total_output_groups
1271 = MAX (max_total_output_groups,
1272 insn_total_groups_for_out_addr[i]);
1275 max_total_input_groups = MAX (max_total_input_groups,
1276 insn_total_groups_for_op_addr);
1277 max_total_output_groups = MAX (max_total_output_groups,
1278 insn_total_groups_for_insn);
1280 insn_total_groups_for_inputs
1281 = MAX (max_total_input_groups + insn_total_groups_for_op_addr
1282 + insn_total_groups_for_insn,
1283 max_total_input_groups + insn_total_groups_for_inputs);
1285 insn_total_groups_for_outputs += max_total_output_groups;
1287 insn_total_groups += MAX (MAX (insn_total_groups_for_outputs,
1288 insn_total_groups_for_inputs),
1289 insn_total_groups_for_other_addr);
1291 /* If this is a CALL_INSN and caller-saves will need
1292 a spill register, act as if the spill register is
1293 needed for this insn. However, the spill register
1294 can be used by any reload of this insn, so we only
1295 need do something if no need for that class has
1298 The assumption that every CALL_INSN will trigger a
1299 caller-save is highly conservative, however, the number
1300 of cases where caller-saves will need a spill register but
1301 a block containing a CALL_INSN won't need a spill register
1302 of that class should be quite rare.
1304 If a group is needed, the size and mode of the group will
1305 have been set up at the beginning of this loop. */
1307 if (GET_CODE (insn) == CALL_INSN
1308 && caller_save_spill_class != NO_REGS)
1310 int *caller_save_needs
1311 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1313 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1315 register enum reg_class *p
1316 = reg_class_superclasses[(int) caller_save_spill_class];
1318 caller_save_needs[(int) caller_save_spill_class]++;
1320 while (*p != LIM_REG_CLASSES)
1321 caller_save_needs[(int) *p++] += 1;
1324 if (caller_save_group_size > 1)
1325 insn_total_groups = MAX (insn_total_groups, 1);
1328 /* Show that this basic block will need a register of
1332 && ! (basic_block_needs[(int) caller_save_spill_class]
1335 basic_block_needs[(int) caller_save_spill_class]
1337 new_basic_block_needs = 1;
1341 #ifdef SMALL_REGISTER_CLASSES
1342 /* If this insn stores the value of a function call,
1343 and that value is in a register that has been spilled,
1344 and if the insn needs a reload in a class
1345 that might use that register as the reload register,
1346 then add add an extra need in that class.
1347 This makes sure we have a register available that does
1348 not overlap the return value. */
1349 if (avoid_return_reg)
1351 int regno = REGNO (avoid_return_reg);
1353 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1355 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1357 /* First compute the "basic needs", which counts a
1358 need only in the smallest class in which it
1361 bcopy (insn_needs, basic_needs, sizeof basic_needs);
1362 bcopy (insn_groups, basic_groups, sizeof basic_groups);
1364 for (i = 0; i < N_REG_CLASSES; i++)
1368 if (basic_needs[i] >= 0)
1369 for (p = reg_class_superclasses[i];
1370 *p != LIM_REG_CLASSES; p++)
1371 basic_needs[(int) *p] -= basic_needs[i];
1373 if (basic_groups[i] >= 0)
1374 for (p = reg_class_superclasses[i];
1375 *p != LIM_REG_CLASSES; p++)
1376 basic_groups[(int) *p] -= basic_groups[i];
1379 /* Now count extra regs if there might be a conflict with
1380 the return value register.
1382 ??? This is not quite correct because we don't properly
1383 handle the case of groups, but if we end up doing
1384 something wrong, it either will end up not mattering or
1385 we will abort elsewhere. */
1387 for (r = regno; r < regno + nregs; r++)
1388 if (spill_reg_order[r] >= 0)
1389 for (i = 0; i < N_REG_CLASSES; i++)
1390 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1392 if (basic_needs[i] > 0 || basic_groups[i] > 0)
1397 p = reg_class_superclasses[i];
1398 while (*p != LIM_REG_CLASSES)
1399 insn_needs[(int) *p++]++;
1403 #endif /* SMALL_REGISTER_CLASSES */
1405 /* For each class, collect maximum need of any insn. */
1407 for (i = 0; i < N_REG_CLASSES; i++)
1409 if (max_needs[i] < insn_needs[i])
1411 max_needs[i] = insn_needs[i];
1412 max_needs_insn[i] = insn;
1414 if (max_groups[i] < insn_groups[i])
1416 max_groups[i] = insn_groups[i];
1417 max_groups_insn[i] = insn;
1419 if (insn_total_groups > 0)
1420 if (max_nongroups[i] < insn_needs[i])
1422 max_nongroups[i] = insn_needs[i];
1423 max_nongroups_insn[i] = insn;
1427 /* Note that there is a continue statement above. */
1430 /* If we allocated any new memory locations, make another pass
1431 since it might have changed elimination offsets. */
1432 if (starting_frame_size != get_frame_size ())
1433 something_changed = 1;
1436 for (i = 0; i < N_REG_CLASSES; i++)
1438 if (max_needs[i] > 0)
1440 ";; Need %d reg%s of class %s (for insn %d).\n",
1441 max_needs[i], max_needs[i] == 1 ? "" : "s",
1442 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1443 if (max_nongroups[i] > 0)
1445 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1446 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1447 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1448 if (max_groups[i] > 0)
1450 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1451 max_groups[i], max_groups[i] == 1 ? "" : "s",
1452 mode_name[(int) group_mode[i]],
1453 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1456 /* If we have caller-saves, set up the save areas and see if caller-save
1457 will need a spill register. */
1459 if (caller_save_needed
1460 && ! setup_save_areas (&something_changed)
1461 && caller_save_spill_class == NO_REGS)
1463 /* The class we will need depends on whether the machine
1464 supports the sum of two registers for an address; see
1465 find_address_reloads for details. */
1467 caller_save_spill_class
1468 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1469 caller_save_group_size
1470 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1471 something_changed = 1;
1474 /* See if anything that happened changes which eliminations are valid.
1475 For example, on the Sparc, whether or not the frame pointer can
1476 be eliminated can depend on what registers have been used. We need
1477 not check some conditions again (such as flag_omit_frame_pointer)
1478 since they can't have changed. */
1480 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1481 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1482 #ifdef ELIMINABLE_REGS
1483 || ! CAN_ELIMINATE (ep->from, ep->to)
1486 ep->can_eliminate = 0;
1488 /* Look for the case where we have discovered that we can't replace
1489 register A with register B and that means that we will now be
1490 trying to replace register A with register C. This means we can
1491 no longer replace register C with register B and we need to disable
1492 such an elimination, if it exists. This occurs often with A == ap,
1493 B == sp, and C == fp. */
1495 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1497 struct elim_table *op;
1498 register int new_to = -1;
1500 if (! ep->can_eliminate && ep->can_eliminate_previous)
1502 /* Find the current elimination for ep->from, if there is a
1504 for (op = reg_eliminate;
1505 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1506 if (op->from == ep->from && op->can_eliminate)
1512 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1514 for (op = reg_eliminate;
1515 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1516 if (op->from == new_to && op->to == ep->to)
1517 op->can_eliminate = 0;
1521 /* See if any registers that we thought we could eliminate the previous
1522 time are no longer eliminable. If so, something has changed and we
1523 must spill the register. Also, recompute the number of eliminable
1524 registers and see if the frame pointer is needed; it is if there is
1525 no elimination of the frame pointer that we can perform. */
1527 frame_pointer_needed = 1;
1528 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1530 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1531 frame_pointer_needed = 0;
1533 if (! ep->can_eliminate && ep->can_eliminate_previous)
1535 ep->can_eliminate_previous = 0;
1536 spill_hard_reg (ep->from, global, dumpfile, 1);
1537 regs_ever_live[ep->from] = 1;
1538 something_changed = 1;
1543 /* If all needs are met, we win. */
1545 for (i = 0; i < N_REG_CLASSES; i++)
1546 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1548 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1551 /* Not all needs are met; must spill some hard regs. */
1553 /* Put all registers spilled so far back in potential_reload_regs, but
1554 put them at the front, since we've already spilled most of the
1555 psuedos in them (we might have left some pseudos unspilled if they
1556 were in a block that didn't need any spill registers of a conflicting
1557 class. We used to try to mark off the need for those registers,
1558 but doing so properly is very complex and reallocating them is the
1559 simpler approach. First, "pack" potential_reload_regs by pushing
1560 any nonnegative entries towards the end. That will leave room
1561 for the registers we already spilled.
1563 Also, undo the marking of the spill registers from the last time
1564 around in FORBIDDEN_REGS since we will be probably be allocating
1567 ??? It is theoretically possible that we might end up not using one
1568 of our previously-spilled registers in this allocation, even though
1569 they are at the head of the list. It's not clear what to do about
1570 this, but it was no better before, when we marked off the needs met
1571 by the previously-spilled registers. With the current code, globals
1572 can be allocated into these registers, but locals cannot. */
1576 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1577 if (potential_reload_regs[i] != -1)
1578 potential_reload_regs[j--] = potential_reload_regs[i];
1580 for (i = 0; i < n_spills; i++)
1582 potential_reload_regs[i] = spill_regs[i];
1583 spill_reg_order[spill_regs[i]] = -1;
1584 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1590 /* Now find more reload regs to satisfy the remaining need
1591 Do it by ascending class number, since otherwise a reg
1592 might be spilled for a big class and might fail to count
1593 for a smaller class even though it belongs to that class.
1595 Count spilled regs in `spills', and add entries to
1596 `spill_regs' and `spill_reg_order'.
1598 ??? Note there is a problem here.
1599 When there is a need for a group in a high-numbered class,
1600 and also need for non-group regs that come from a lower class,
1601 the non-group regs are chosen first. If there aren't many regs,
1602 they might leave no room for a group.
1604 This was happening on the 386. To fix it, we added the code
1605 that calls possible_group_p, so that the lower class won't
1606 break up the last possible group.
1608 Really fixing the problem would require changes above
1609 in counting the regs already spilled, and in choose_reload_regs.
1610 It might be hard to avoid introducing bugs there. */
1612 CLEAR_HARD_REG_SET (counted_for_groups);
1613 CLEAR_HARD_REG_SET (counted_for_nongroups);
1615 for (class = 0; class < N_REG_CLASSES; class++)
1617 /* First get the groups of registers.
1618 If we got single registers first, we might fragment
1620 while (max_groups[class] > 0)
1622 /* If any single spilled regs happen to form groups,
1623 count them now. Maybe we don't really need
1624 to spill another group. */
1625 count_possible_groups (group_size, group_mode, max_groups);
1627 if (max_groups[class] <= 0)
1630 /* Groups of size 2 (the only groups used on most machines)
1631 are treated specially. */
1632 if (group_size[class] == 2)
1634 /* First, look for a register that will complete a group. */
1635 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1639 j = potential_reload_regs[i];
1640 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1642 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1643 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1644 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1645 && HARD_REGNO_MODE_OK (other, group_mode[class])
1646 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1648 /* We don't want one part of another group.
1649 We could get "two groups" that overlap! */
1650 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1652 (j < FIRST_PSEUDO_REGISTER - 1
1653 && (other = j + 1, spill_reg_order[other] >= 0)
1654 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1655 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1656 && HARD_REGNO_MODE_OK (j, group_mode[class])
1657 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1659 && ! TEST_HARD_REG_BIT (counted_for_groups,
1662 register enum reg_class *p;
1664 /* We have found one that will complete a group,
1665 so count off one group as provided. */
1666 max_groups[class]--;
1667 p = reg_class_superclasses[class];
1668 while (*p != LIM_REG_CLASSES)
1669 max_groups[(int) *p++]--;
1671 /* Indicate both these regs are part of a group. */
1672 SET_HARD_REG_BIT (counted_for_groups, j);
1673 SET_HARD_REG_BIT (counted_for_groups, other);
1677 /* We can't complete a group, so start one. */
1678 if (i == FIRST_PSEUDO_REGISTER)
1679 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1681 j = potential_reload_regs[i];
1682 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1683 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1684 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1685 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1686 && HARD_REGNO_MODE_OK (j, group_mode[class])
1687 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1692 /* I should be the index in potential_reload_regs
1693 of the new reload reg we have found. */
1695 if (i >= FIRST_PSEUDO_REGISTER)
1697 /* There are no groups left to spill. */
1698 spill_failure (max_groups_insn[class]);
1704 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1709 /* For groups of more than 2 registers,
1710 look for a sufficient sequence of unspilled registers,
1711 and spill them all at once. */
1712 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1716 j = potential_reload_regs[i];
1718 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1719 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1721 /* Check each reg in the sequence. */
1722 for (k = 0; k < group_size[class]; k++)
1723 if (! (spill_reg_order[j + k] < 0
1724 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1725 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1727 /* We got a full sequence, so spill them all. */
1728 if (k == group_size[class])
1730 register enum reg_class *p;
1731 for (k = 0; k < group_size[class]; k++)
1734 SET_HARD_REG_BIT (counted_for_groups, j + k);
1735 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1736 if (potential_reload_regs[idx] == j + k)
1739 |= new_spill_reg (idx, class,
1740 max_needs, NULL_PTR,
1744 /* We have found one that will complete a group,
1745 so count off one group as provided. */
1746 max_groups[class]--;
1747 p = reg_class_superclasses[class];
1748 while (*p != LIM_REG_CLASSES)
1749 max_groups[(int) *p++]--;
1755 /* We couldn't find any registers for this reload.
1756 Avoid going into an infinite loop. */
1757 if (i >= FIRST_PSEUDO_REGISTER)
1759 /* There are no groups left. */
1760 spill_failure (max_groups_insn[class]);
1767 /* Now similarly satisfy all need for single registers. */
1769 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1771 /* Consider the potential reload regs that aren't
1772 yet in use as reload regs, in order of preference.
1773 Find the most preferred one that's in this class. */
1775 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1776 if (potential_reload_regs[i] >= 0
1777 && TEST_HARD_REG_BIT (reg_class_contents[class],
1778 potential_reload_regs[i])
1779 /* If this reg will not be available for groups,
1780 pick one that does not foreclose possible groups.
1781 This is a kludge, and not very general,
1782 but it should be sufficient to make the 386 work,
1783 and the problem should not occur on machines with
1785 && (max_nongroups[class] == 0
1786 || possible_group_p (potential_reload_regs[i], max_groups)))
1789 /* If we couldn't get a register, try to get one even if we
1790 might foreclose possible groups. This may cause problems
1791 later, but that's better than aborting now, since it is
1792 possible that we will, in fact, be able to form the needed
1793 group even with this allocation. */
1795 if (i >= FIRST_PSEUDO_REGISTER
1796 && (asm_noperands (max_needs[class] > 0
1797 ? max_needs_insn[class]
1798 : max_nongroups_insn[class])
1800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1801 if (potential_reload_regs[i] >= 0
1802 && TEST_HARD_REG_BIT (reg_class_contents[class],
1803 potential_reload_regs[i]))
1806 /* I should be the index in potential_reload_regs
1807 of the new reload reg we have found. */
1809 if (i >= FIRST_PSEUDO_REGISTER)
1811 /* There are no possible registers left to spill. */
1812 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1813 : max_nongroups_insn[class]);
1819 |= new_spill_reg (i, class, max_needs, max_nongroups,
1825 /* If global-alloc was run, notify it of any register eliminations we have
1828 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1829 if (ep->can_eliminate)
1830 mark_elimination (ep->from, ep->to);
1832 /* Insert code to save and restore call-clobbered hard regs
1833 around calls. Tell if what mode to use so that we will process
1834 those insns in reload_as_needed if we have to. */
1836 if (caller_save_needed)
1837 save_call_clobbered_regs (num_eliminable ? QImode
1838 : caller_save_spill_class != NO_REGS ? HImode
1841 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1842 If that insn didn't set the register (i.e., it copied the register to
1843 memory), just delete that insn instead of the equivalencing insn plus
1844 anything now dead. If we call delete_dead_insn on that insn, we may
1845 delete the insn that actually sets the register if the register die
1846 there and that is incorrect. */
1848 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1849 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1850 && GET_CODE (reg_equiv_init[i]) != NOTE)
1852 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1853 delete_dead_insn (reg_equiv_init[i]);
1856 PUT_CODE (reg_equiv_init[i], NOTE);
1857 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1858 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1862 /* Use the reload registers where necessary
1863 by generating move instructions to move the must-be-register
1864 values into or out of the reload registers. */
1866 if (something_needs_reloads || something_needs_elimination
1867 || (caller_save_needed && num_eliminable)
1868 || caller_save_spill_class != NO_REGS)
1869 reload_as_needed (first, global);
1871 /* If we were able to eliminate the frame pointer, show that it is no
1872 longer live at the start of any basic block. If it ls live by
1873 virtue of being in a pseudo, that pseudo will be marked live
1874 and hence the frame pointer will be known to be live via that
1877 if (! frame_pointer_needed)
1878 for (i = 0; i < n_basic_blocks; i++)
1879 basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1880 &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS));
1882 /* Come here (with failure set nonzero) if we can't get enough spill regs
1883 and we decide not to abort about it. */
1886 reload_in_progress = 0;
1888 /* Now eliminate all pseudo regs by modifying them into
1889 their equivalent memory references.
1890 The REG-rtx's for the pseudos are modified in place,
1891 so all insns that used to refer to them now refer to memory.
1893 For a reg that has a reg_equiv_address, all those insns
1894 were changed by reloading so that no insns refer to it any longer;
1895 but the DECL_RTL of a variable decl may refer to it,
1896 and if so this causes the debugging info to mention the variable. */
1898 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1902 if (reg_equiv_mem[i])
1904 addr = XEXP (reg_equiv_mem[i], 0);
1905 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1907 if (reg_equiv_address[i])
1908 addr = reg_equiv_address[i];
1911 if (reg_renumber[i] < 0)
1913 rtx reg = regno_reg_rtx[i];
1914 XEXP (reg, 0) = addr;
1915 REG_USERVAR_P (reg) = 0;
1916 MEM_IN_STRUCT_P (reg) = in_struct;
1917 PUT_CODE (reg, MEM);
1919 else if (reg_equiv_mem[i])
1920 XEXP (reg_equiv_mem[i], 0) = addr;
1924 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1925 /* Make a pass over all the insns and remove death notes for things that
1926 are no longer registers or no longer die in the insn (e.g., an input
1927 and output pseudo being tied). */
1929 for (insn = first; insn; insn = NEXT_INSN (insn))
1930 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1934 for (note = REG_NOTES (insn); note; note = next)
1936 next = XEXP (note, 1);
1937 if (REG_NOTE_KIND (note) == REG_DEAD
1938 && (GET_CODE (XEXP (note, 0)) != REG
1939 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1940 remove_note (insn, note);
1945 /* Indicate that we no longer have known memory locations or constants. */
1946 reg_equiv_constant = 0;
1947 reg_equiv_memory_loc = 0;
1952 /* Nonzero if, after spilling reg REGNO for non-groups,
1953 it will still be possible to find a group if we still need one. */
1956 possible_group_p (regno, max_groups)
1961 int class = (int) NO_REGS;
1963 for (i = 0; i < (int) N_REG_CLASSES; i++)
1964 if (max_groups[i] > 0)
1970 if (class == (int) NO_REGS)
1973 /* Consider each pair of consecutive registers. */
1974 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1976 /* Ignore pairs that include reg REGNO. */
1977 if (i == regno || i + 1 == regno)
1980 /* Ignore pairs that are outside the class that needs the group.
1981 ??? Here we fail to handle the case where two different classes
1982 independently need groups. But this never happens with our
1983 current machine descriptions. */
1984 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1985 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1988 /* A pair of consecutive regs we can still spill does the trick. */
1989 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1990 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1991 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1994 /* A pair of one already spilled and one we can spill does it
1995 provided the one already spilled is not otherwise reserved. */
1996 if (spill_reg_order[i] < 0
1997 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1998 && spill_reg_order[i + 1] >= 0
1999 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2000 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2002 if (spill_reg_order[i + 1] < 0
2003 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2004 && spill_reg_order[i] >= 0
2005 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2006 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2013 /* Count any groups that can be formed from the registers recently spilled.
2014 This is done class by class, in order of ascending class number. */
2017 count_possible_groups (group_size, group_mode, max_groups)
2019 enum machine_mode *group_mode;
2023 /* Now find all consecutive groups of spilled registers
2024 and mark each group off against the need for such groups.
2025 But don't count them against ordinary need, yet. */
2027 for (i = 0; i < N_REG_CLASSES; i++)
2028 if (group_size[i] > 1)
2033 CLEAR_HARD_REG_SET (new);
2035 /* Make a mask of all the regs that are spill regs in class I. */
2036 for (j = 0; j < n_spills; j++)
2037 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
2038 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
2039 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
2041 SET_HARD_REG_BIT (new, spill_regs[j]);
2043 /* Find each consecutive group of them. */
2044 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
2045 if (TEST_HARD_REG_BIT (new, j)
2046 && j + group_size[i] <= FIRST_PSEUDO_REGISTER
2047 /* Next line in case group-mode for this class
2048 demands an even-odd pair. */
2049 && HARD_REGNO_MODE_OK (j, group_mode[i]))
2052 for (k = 1; k < group_size[i]; k++)
2053 if (! TEST_HARD_REG_BIT (new, j + k))
2055 if (k == group_size[i])
2057 /* We found a group. Mark it off against this class's
2058 need for groups, and against each superclass too. */
2059 register enum reg_class *p;
2061 p = reg_class_superclasses[i];
2062 while (*p != LIM_REG_CLASSES)
2063 max_groups[(int) *p++]--;
2064 /* Don't count these registers again. */
2065 for (k = 0; k < group_size[i]; k++)
2066 SET_HARD_REG_BIT (counted_for_groups, j + k);
2068 /* Skip to the last reg in this group. When j is incremented
2069 above, it will then point to the first reg of the next
2077 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2078 another mode that needs to be reloaded for the same register class CLASS.
2079 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2080 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2082 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2083 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2084 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2085 causes unnecessary failures on machines requiring alignment of register
2086 groups when the two modes are different sizes, because the larger mode has
2087 more strict alignment rules than the smaller mode. */
2090 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2091 enum machine_mode allocate_mode, other_mode;
2092 enum reg_class class;
2095 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2097 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2098 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2099 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2105 /* Handle the failure to find a register to spill.
2106 INSN should be one of the insns which needed this particular spill reg. */
2109 spill_failure (insn)
2112 if (asm_noperands (PATTERN (insn)) >= 0)
2113 error_for_asm (insn, "`asm' needs too many reloads");
2118 /* Add a new register to the tables of available spill-registers
2119 (as well as spilling all pseudos allocated to the register).
2120 I is the index of this register in potential_reload_regs.
2121 CLASS is the regclass whose need is being satisfied.
2122 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2123 so that this register can count off against them.
2124 MAX_NONGROUPS is 0 if this register is part of a group.
2125 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2128 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2136 register enum reg_class *p;
2138 int regno = potential_reload_regs[i];
2140 if (i >= FIRST_PSEUDO_REGISTER)
2141 abort (); /* Caller failed to find any register. */
2143 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2144 fatal ("fixed or forbidden register was spilled.\n\
2145 This may be due to a compiler bug or to impossible asm statements.");
2147 /* Make reg REGNO an additional reload reg. */
2149 potential_reload_regs[i] = -1;
2150 spill_regs[n_spills] = regno;
2151 spill_reg_order[regno] = n_spills;
2153 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2155 /* Clear off the needs we just satisfied. */
2158 p = reg_class_superclasses[class];
2159 while (*p != LIM_REG_CLASSES)
2160 max_needs[(int) *p++]--;
2162 if (max_nongroups && max_nongroups[class] > 0)
2164 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2165 max_nongroups[class]--;
2166 p = reg_class_superclasses[class];
2167 while (*p != LIM_REG_CLASSES)
2168 max_nongroups[(int) *p++]--;
2171 /* Spill every pseudo reg that was allocated to this reg
2172 or to something that overlaps this reg. */
2174 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2176 /* If there are some registers still to eliminate and this register
2177 wasn't ever used before, additional stack space may have to be
2178 allocated to store this register. Thus, we may have changed the offset
2179 between the stack and frame pointers, so mark that something has changed.
2180 (If new pseudos were spilled, thus requiring more space, VAL would have
2181 been set non-zero by the call to spill_hard_reg above since additional
2182 reloads may be needed in that case.
2184 One might think that we need only set VAL to 1 if this is a call-used
2185 register. However, the set of registers that must be saved by the
2186 prologue is not identical to the call-used set. For example, the
2187 register used by the call insn for the return PC is a call-used register,
2188 but must be saved by the prologue. */
2189 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2192 regs_ever_live[spill_regs[n_spills]] = 1;
2198 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2199 data that is dead in INSN. */
2202 delete_dead_insn (insn)
2205 rtx prev = prev_real_insn (insn);
2208 /* If the previous insn sets a register that dies in our insn, delete it
2210 if (prev && GET_CODE (PATTERN (prev)) == SET
2211 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2212 && reg_mentioned_p (prev_dest, PATTERN (insn))
2213 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2214 delete_dead_insn (prev);
2216 PUT_CODE (insn, NOTE);
2217 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2218 NOTE_SOURCE_FILE (insn) = 0;
2221 /* Modify the home of pseudo-reg I.
2222 The new home is present in reg_renumber[I].
2224 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2225 or it may be -1, meaning there is none or it is not relevant.
2226 This is used so that all pseudos spilled from a given hard reg
2227 can share one stack slot. */
2230 alter_reg (i, from_reg)
2234 /* When outputting an inline function, this can happen
2235 for a reg that isn't actually used. */
2236 if (regno_reg_rtx[i] == 0)
2239 /* If the reg got changed to a MEM at rtl-generation time,
2241 if (GET_CODE (regno_reg_rtx[i]) != REG)
2244 /* Modify the reg-rtx to contain the new hard reg
2245 number or else to contain its pseudo reg number. */
2246 REGNO (regno_reg_rtx[i])
2247 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2249 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2250 allocate a stack slot for it. */
2252 if (reg_renumber[i] < 0
2253 && reg_n_refs[i] > 0
2254 && reg_equiv_constant[i] == 0
2255 && reg_equiv_memory_loc[i] == 0)
2258 int inherent_size = PSEUDO_REGNO_BYTES (i);
2259 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2262 /* Each pseudo reg has an inherent size which comes from its own mode,
2263 and a total size which provides room for paradoxical subregs
2264 which refer to the pseudo reg in wider modes.
2266 We can use a slot already allocated if it provides both
2267 enough inherent space and enough total space.
2268 Otherwise, we allocate a new slot, making sure that it has no less
2269 inherent space, and no less total space, then the previous slot. */
2272 /* No known place to spill from => no slot to reuse. */
2273 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2274 #if BYTES_BIG_ENDIAN
2275 /* Cancel the big-endian correction done in assign_stack_local.
2276 Get the address of the beginning of the slot.
2277 This is so we can do a big-endian correction unconditionally
2279 adjust = inherent_size - total_size;
2282 /* Reuse a stack slot if possible. */
2283 else if (spill_stack_slot[from_reg] != 0
2284 && spill_stack_slot_width[from_reg] >= total_size
2285 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2287 x = spill_stack_slot[from_reg];
2288 /* Allocate a bigger slot. */
2291 /* Compute maximum size needed, both for inherent size
2292 and for total size. */
2293 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2294 if (spill_stack_slot[from_reg])
2296 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2298 mode = GET_MODE (spill_stack_slot[from_reg]);
2299 if (spill_stack_slot_width[from_reg] > total_size)
2300 total_size = spill_stack_slot_width[from_reg];
2302 /* Make a slot with that size. */
2303 x = assign_stack_local (mode, total_size, -1);
2304 #if BYTES_BIG_ENDIAN
2305 /* Cancel the big-endian correction done in assign_stack_local.
2306 Get the address of the beginning of the slot.
2307 This is so we can do a big-endian correction unconditionally
2309 adjust = GET_MODE_SIZE (mode) - total_size;
2311 spill_stack_slot[from_reg] = x;
2312 spill_stack_slot_width[from_reg] = total_size;
2315 #if BYTES_BIG_ENDIAN
2316 /* On a big endian machine, the "address" of the slot
2317 is the address of the low part that fits its inherent mode. */
2318 if (inherent_size < total_size)
2319 adjust += (total_size - inherent_size);
2320 #endif /* BYTES_BIG_ENDIAN */
2322 /* If we have any adjustment to make, or if the stack slot is the
2323 wrong mode, make a new stack slot. */
2324 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2326 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2327 plus_constant (XEXP (x, 0), adjust));
2328 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2331 /* Save the stack slot for later. */
2332 reg_equiv_memory_loc[i] = x;
2336 /* Mark the slots in regs_ever_live for the hard regs
2337 used by pseudo-reg number REGNO. */
2340 mark_home_live (regno)
2343 register int i, lim;
2344 i = reg_renumber[regno];
2347 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2349 regs_ever_live[i++] = 1;
2352 /* This function handles the tracking of elimination offsets around branches.
2354 X is a piece of RTL being scanned.
2356 INSN is the insn that it came from, if any.
2358 INITIAL_P is non-zero if we are to set the offset to be the initial
2359 offset and zero if we are setting the offset of the label to be the
2363 set_label_offsets (x, insn, initial_p)
2368 enum rtx_code code = GET_CODE (x);
2371 struct elim_table *p;
2376 if (LABEL_REF_NONLOCAL_P (x))
2381 /* ... fall through ... */
2384 /* If we know nothing about this label, set the desired offsets. Note
2385 that this sets the offset at a label to be the offset before a label
2386 if we don't know anything about the label. This is not correct for
2387 the label after a BARRIER, but is the best guess we can make. If
2388 we guessed wrong, we will suppress an elimination that might have
2389 been possible had we been able to guess correctly. */
2391 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2393 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2394 offsets_at[CODE_LABEL_NUMBER (x)][i]
2395 = (initial_p ? reg_eliminate[i].initial_offset
2396 : reg_eliminate[i].offset);
2397 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2400 /* Otherwise, if this is the definition of a label and it is
2401 preceded by a BARRIER, set our offsets to the known offset of
2405 && (tem = prev_nonnote_insn (insn)) != 0
2406 && GET_CODE (tem) == BARRIER)
2408 num_not_at_initial_offset = 0;
2409 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2411 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2412 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2413 if (reg_eliminate[i].can_eliminate
2414 && (reg_eliminate[i].offset
2415 != reg_eliminate[i].initial_offset))
2416 num_not_at_initial_offset++;
2421 /* If neither of the above cases is true, compare each offset
2422 with those previously recorded and suppress any eliminations
2423 where the offsets disagree. */
2425 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2426 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2427 != (initial_p ? reg_eliminate[i].initial_offset
2428 : reg_eliminate[i].offset))
2429 reg_eliminate[i].can_eliminate = 0;
2434 set_label_offsets (PATTERN (insn), insn, initial_p);
2436 /* ... fall through ... */
2440 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2441 and hence must have all eliminations at their initial offsets. */
2442 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2443 if (REG_NOTE_KIND (tem) == REG_LABEL)
2444 set_label_offsets (XEXP (tem, 0), insn, 1);
2449 /* Each of the labels in the address vector must be at their initial
2450 offsets. We want the first first for ADDR_VEC and the second
2451 field for ADDR_DIFF_VEC. */
2453 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2454 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2459 /* We only care about setting PC. If the source is not RETURN,
2460 IF_THEN_ELSE, or a label, disable any eliminations not at
2461 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2462 isn't one of those possibilities. For branches to a label,
2463 call ourselves recursively.
2465 Note that this can disable elimination unnecessarily when we have
2466 a non-local goto since it will look like a non-constant jump to
2467 someplace in the current function. This isn't a significant
2468 problem since such jumps will normally be when all elimination
2469 pairs are back to their initial offsets. */
2471 if (SET_DEST (x) != pc_rtx)
2474 switch (GET_CODE (SET_SRC (x)))
2481 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2485 tem = XEXP (SET_SRC (x), 1);
2486 if (GET_CODE (tem) == LABEL_REF)
2487 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2488 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2491 tem = XEXP (SET_SRC (x), 2);
2492 if (GET_CODE (tem) == LABEL_REF)
2493 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2494 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2499 /* If we reach here, all eliminations must be at their initial
2500 offset because we are doing a jump to a variable address. */
2501 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2502 if (p->offset != p->initial_offset)
2503 p->can_eliminate = 0;
2507 /* Used for communication between the next two function to properly share
2508 the vector for an ASM_OPERANDS. */
2510 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2512 /* Scan X and replace any eliminable registers (such as fp) with a
2513 replacement (such as sp), plus an offset.
2515 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2516 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2517 MEM, we are allowed to replace a sum of a register and the constant zero
2518 with the register, which we cannot do outside a MEM. In addition, we need
2519 to record the fact that a register is referenced outside a MEM.
2521 If INSN is nonzero, it is the insn containing X. If we replace a REG
2522 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2523 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2524 that the REG is being modified.
2526 If we see a modification to a register we know about, take the
2527 appropriate action (see case SET, below).
2529 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2530 replacements done assuming all offsets are at their initial values. If
2531 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2532 encounter, return the actual location so that find_reloads will do
2533 the proper thing. */
2536 eliminate_regs (x, mem_mode, insn)
2538 enum machine_mode mem_mode;
2541 enum rtx_code code = GET_CODE (x);
2542 struct elim_table *ep;
2567 /* First handle the case where we encounter a bare register that
2568 is eliminable. Replace it with a PLUS. */
2569 if (regno < FIRST_PSEUDO_REGISTER)
2571 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2573 if (ep->from_rtx == x && ep->can_eliminate)
2576 ep->ref_outside_mem = 1;
2577 return plus_constant (ep->to_rtx, ep->previous_offset);
2581 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2582 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2584 /* In this case, find_reloads would attempt to either use an
2585 incorrect address (if something is not at its initial offset)
2586 or substitute an replaced address into an insn (which loses
2587 if the offset is changed by some later action). So we simply
2588 return the replaced stack slot (assuming it is changed by
2589 elimination) and ignore the fact that this is actually a
2590 reference to the pseudo. Ensure we make a copy of the
2591 address in case it is shared. */
2592 new = eliminate_regs (reg_equiv_memory_loc[regno],
2593 mem_mode, NULL_RTX);
2594 if (new != reg_equiv_memory_loc[regno])
2595 return copy_rtx (new);
2600 /* If this is the sum of an eliminable register and a constant, rework
2602 if (GET_CODE (XEXP (x, 0)) == REG
2603 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2604 && CONSTANT_P (XEXP (x, 1)))
2606 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2608 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2611 ep->ref_outside_mem = 1;
2613 /* The only time we want to replace a PLUS with a REG (this
2614 occurs when the constant operand of the PLUS is the negative
2615 of the offset) is when we are inside a MEM. We won't want
2616 to do so at other times because that would change the
2617 structure of the insn in a way that reload can't handle.
2618 We special-case the commonest situation in
2619 eliminate_regs_in_insn, so just replace a PLUS with a
2620 PLUS here, unless inside a MEM. */
2621 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2622 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2625 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2626 plus_constant (XEXP (x, 1),
2627 ep->previous_offset));
2630 /* If the register is not eliminable, we are done since the other
2631 operand is a constant. */
2635 /* If this is part of an address, we want to bring any constant to the
2636 outermost PLUS. We will do this by doing register replacement in
2637 our operands and seeing if a constant shows up in one of them.
2639 We assume here this is part of an address (or a "load address" insn)
2640 since an eliminable register is not likely to appear in any other
2643 If we have (plus (eliminable) (reg)), we want to produce
2644 (plus (plus (replacement) (reg) (const))). If this was part of a
2645 normal add insn, (plus (replacement) (reg)) will be pushed as a
2646 reload. This is the desired action. */
2649 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2650 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2652 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2654 /* If one side is a PLUS and the other side is a pseudo that
2655 didn't get a hard register but has a reg_equiv_constant,
2656 we must replace the constant here since it may no longer
2657 be in the position of any operand. */
2658 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2659 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2660 && reg_renumber[REGNO (new1)] < 0
2661 && reg_equiv_constant != 0
2662 && reg_equiv_constant[REGNO (new1)] != 0)
2663 new1 = reg_equiv_constant[REGNO (new1)];
2664 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2665 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2666 && reg_renumber[REGNO (new0)] < 0
2667 && reg_equiv_constant[REGNO (new0)] != 0)
2668 new0 = reg_equiv_constant[REGNO (new0)];
2670 new = form_sum (new0, new1);
2672 /* As above, if we are not inside a MEM we do not want to
2673 turn a PLUS into something else. We might try to do so here
2674 for an addition of 0 if we aren't optimizing. */
2675 if (! mem_mode && GET_CODE (new) != PLUS)
2676 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2684 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2687 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2688 if (new != XEXP (x, 0))
2689 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2692 /* ... fall through ... */
2695 /* Now do eliminations in the rest of the chain. If this was
2696 an EXPR_LIST, this might result in allocating more memory than is
2697 strictly needed, but it simplifies the code. */
2700 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2701 if (new != XEXP (x, 1))
2702 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2710 case DIV: case UDIV:
2711 case MOD: case UMOD:
2712 case AND: case IOR: case XOR:
2713 case LSHIFT: case ASHIFT: case ROTATE:
2714 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2716 case GE: case GT: case GEU: case GTU:
2717 case LE: case LT: case LEU: case LTU:
2719 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2721 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2723 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2724 return gen_rtx (code, GET_MODE (x), new0, new1);
2732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2733 if (ep->to_rtx == XEXP (x, 0))
2735 if (code == PRE_DEC || code == POST_DEC)
2736 ep->offset += GET_MODE_SIZE (mem_mode);
2738 ep->offset -= GET_MODE_SIZE (mem_mode);
2741 /* Fall through to generic unary operation case. */
2743 case STRICT_LOW_PART:
2745 case SIGN_EXTEND: case ZERO_EXTEND:
2746 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2747 case FLOAT: case FIX:
2748 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2752 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2753 if (new != XEXP (x, 0))
2754 return gen_rtx (code, GET_MODE (x), new);
2758 /* Similar to above processing, but preserve SUBREG_WORD.
2759 Convert (subreg (mem)) to (mem) if not paradoxical.
2760 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2761 pseudo didn't get a hard reg, we must replace this with the
2762 eliminated version of the memory location because push_reloads
2763 may do the replacement in certain circumstances. */
2764 if (GET_CODE (SUBREG_REG (x)) == REG
2765 && (GET_MODE_SIZE (GET_MODE (x))
2766 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2767 && reg_equiv_memory_loc != 0
2768 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2770 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2771 mem_mode, NULL_RTX);
2773 /* If we didn't change anything, we must retain the pseudo. */
2774 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2777 /* Otherwise, ensure NEW isn't shared in case we have to reload
2779 new = copy_rtx (new);
2782 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2784 if (new != XEXP (x, 0))
2786 if (GET_CODE (new) == MEM
2787 && (GET_MODE_SIZE (GET_MODE (x))
2788 <= GET_MODE_SIZE (GET_MODE (new))))
2790 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2791 enum machine_mode mode = GET_MODE (x);
2793 #if BYTES_BIG_ENDIAN
2794 offset += (MIN (UNITS_PER_WORD,
2795 GET_MODE_SIZE (GET_MODE (new)))
2796 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2799 PUT_MODE (new, mode);
2800 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2804 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2810 /* If clobbering a register that is the replacement register for an
2811 elimination we still think can be performed, note that it cannot
2812 be performed. Otherwise, we need not be concerned about it. */
2813 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2814 if (ep->to_rtx == XEXP (x, 0))
2815 ep->can_eliminate = 0;
2817 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2818 if (new != XEXP (x, 0))
2819 return gen_rtx (code, GET_MODE (x), new);
2825 /* Properly handle sharing input and constraint vectors. */
2826 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2828 /* When we come to a new vector not seen before,
2829 scan all its elements; keep the old vector if none
2830 of them changes; otherwise, make a copy. */
2831 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2832 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2833 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2834 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2835 mem_mode, NULL_RTX);
2837 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2838 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2841 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2842 new_asm_operands_vec = old_asm_operands_vec;
2844 new_asm_operands_vec
2845 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2848 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2849 if (new_asm_operands_vec == old_asm_operands_vec)
2852 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2853 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2854 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2855 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2856 ASM_OPERANDS_SOURCE_FILE (x),
2857 ASM_OPERANDS_SOURCE_LINE (x));
2858 new->volatil = x->volatil;
2863 /* Check for setting a register that we know about. */
2864 if (GET_CODE (SET_DEST (x)) == REG)
2866 /* See if this is setting the replacement register for an
2869 If DEST is the frame pointer, we do nothing because we assume that
2870 all assignments to the frame pointer are for non-local gotos and
2871 are being done at a time when they are valid and do not disturb
2872 anything else. Some machines want to eliminate a fake argument
2873 pointer with either the frame or stack pointer. Assignments to
2874 the frame pointer must not prevent this elimination. */
2876 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2878 if (ep->to_rtx == SET_DEST (x)
2879 && SET_DEST (x) != frame_pointer_rtx)
2881 /* If it is being incremented, adjust the offset. Otherwise,
2882 this elimination can't be done. */
2883 rtx src = SET_SRC (x);
2885 if (GET_CODE (src) == PLUS
2886 && XEXP (src, 0) == SET_DEST (x)
2887 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2888 ep->offset -= INTVAL (XEXP (src, 1));
2890 ep->can_eliminate = 0;
2893 /* Now check to see we are assigning to a register that can be
2894 eliminated. If so, it must be as part of a PARALLEL, since we
2895 will not have been called if this is a single SET. So indicate
2896 that we can no longer eliminate this reg. */
2897 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2899 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2900 ep->can_eliminate = 0;
2903 /* Now avoid the loop below in this common case. */
2905 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2906 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
2908 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2909 write a CLOBBER insn. */
2910 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2912 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2914 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2915 return gen_rtx (SET, VOIDmode, new0, new1);
2921 /* Our only special processing is to pass the mode of the MEM to our
2922 recursive call and copy the flags. While we are here, handle this
2923 case more efficiently. */
2924 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
2925 if (new != XEXP (x, 0))
2927 new = gen_rtx (MEM, GET_MODE (x), new);
2928 new->volatil = x->volatil;
2929 new->unchanging = x->unchanging;
2930 new->in_struct = x->in_struct;
2937 /* Process each of our operands recursively. If any have changed, make a
2939 fmt = GET_RTX_FORMAT (code);
2940 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2944 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
2945 if (new != XEXP (x, i) && ! copied)
2947 rtx new_x = rtx_alloc (code);
2948 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2949 + (sizeof (new_x->fld[0])
2950 * GET_RTX_LENGTH (code))));
2956 else if (*fmt == 'E')
2959 for (j = 0; j < XVECLEN (x, i); j++)
2961 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2962 if (new != XVECEXP (x, i, j) && ! copied_vec)
2964 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2965 &XVECEXP (x, i, 0));
2968 rtx new_x = rtx_alloc (code);
2969 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2970 + (sizeof (new_x->fld[0])
2971 * GET_RTX_LENGTH (code))));
2975 XVEC (x, i) = new_v;
2978 XVECEXP (x, i, j) = new;
2986 /* Scan INSN and eliminate all eliminable registers in it.
2988 If REPLACE is nonzero, do the replacement destructively. Also
2989 delete the insn as dead it if it is setting an eliminable register.
2991 If REPLACE is zero, do all our allocations in reload_obstack.
2993 If no eliminations were done and this insn doesn't require any elimination
2994 processing (these are not identical conditions: it might be updating sp,
2995 but not referencing fp; this needs to be seen during reload_as_needed so
2996 that the offset between fp and sp can be taken into consideration), zero
2997 is returned. Otherwise, 1 is returned. */
3000 eliminate_regs_in_insn (insn, replace)
3004 rtx old_body = PATTERN (insn);
3007 struct elim_table *ep;
3010 push_obstacks (&reload_obstack, &reload_obstack);
3012 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
3013 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
3015 /* Check for setting an eliminable register. */
3016 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3017 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
3019 /* In this case this insn isn't serving a useful purpose. We
3020 will delete it in reload_as_needed once we know that this
3021 elimination is, in fact, being done.
3023 If REPLACE isn't set, we can't delete this insn, but neededn't
3024 process it since it won't be used unless something changes. */
3026 delete_dead_insn (insn);
3031 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3032 in the insn is the negative of the offset in FROM. Substitute
3033 (set (reg) (reg to)) for the insn and change its code.
3035 We have to do this here, rather than in eliminate_regs, do that we can
3036 change the insn code. */
3038 if (GET_CODE (SET_SRC (old_body)) == PLUS
3039 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
3040 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
3041 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3043 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
3044 && ep->can_eliminate
3045 && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
3047 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3048 SET_DEST (old_body), ep->to_rtx);
3049 INSN_CODE (insn) = -1;
3055 old_asm_operands_vec = 0;
3057 /* Replace the body of this insn with a substituted form. If we changed
3058 something, return non-zero. If this is the final call for this
3059 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
3061 If we are replacing a body that was a (set X (plus Y Z)), try to
3062 re-recognize the insn. We do this in case we had a simple addition
3063 but now can do this as a load-address. This saves an insn in this
3066 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3067 if (new_body != old_body)
3069 /* If we aren't replacing things permanently and we changed something,
3070 make another copy to ensure that all the RTL is new. Otherwise
3071 things can go wrong if find_reload swaps commutative operands
3072 and one is inside RTL that has been copied while the other is not. */
3074 /* Don't copy an asm_operands because (1) there's no need and (2)
3075 copy_rtx can't do it properly when there are multiple outputs. */
3076 if (! replace && asm_noperands (old_body) < 0)
3077 new_body = copy_rtx (new_body);
3079 /* If we had a move insn but now we don't, rerecognize it. */
3080 if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3081 && (GET_CODE (new_body) != SET
3082 || GET_CODE (SET_SRC (new_body)) != REG))
3083 /* If this was an add insn before, rerecognize. */
3085 (GET_CODE (old_body) == SET
3086 && GET_CODE (SET_SRC (old_body)) == PLUS))
3088 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3089 /* If recognition fails, store the new body anyway.
3090 It's normal to have recognition failures here
3091 due to bizarre memory addresses; reloading will fix them. */
3092 PATTERN (insn) = new_body;
3095 PATTERN (insn) = new_body;
3097 if (replace && REG_NOTES (insn))
3098 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
3102 /* Loop through all elimination pairs. See if any have changed and
3103 recalculate the number not at initial offset.
3105 Compute the maximum offset (minimum offset if the stack does not
3106 grow downward) for each elimination pair.
3108 We also detect a cases where register elimination cannot be done,
3109 namely, if a register would be both changed and referenced outside a MEM
3110 in the resulting insn since such an insn is often undefined and, even if
3111 not, we cannot know what meaning will be given to it. Note that it is
3112 valid to have a register used in an address in an insn that changes it
3113 (presumably with a pre- or post-increment or decrement).
3115 If anything changes, return nonzero. */
3117 num_not_at_initial_offset = 0;
3118 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3120 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3121 ep->can_eliminate = 0;
3123 ep->ref_outside_mem = 0;
3125 if (ep->previous_offset != ep->offset)
3128 ep->previous_offset = ep->offset;
3129 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3130 num_not_at_initial_offset++;
3132 #ifdef STACK_GROWS_DOWNWARD
3133 ep->max_offset = MAX (ep->max_offset, ep->offset);
3135 ep->max_offset = MIN (ep->max_offset, ep->offset);
3146 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3147 replacement we currently believe is valid, mark it as not eliminable if X
3148 modifies DEST in any way other than by adding a constant integer to it.
3150 If DEST is the frame pointer, we do nothing because we assume that
3151 all assignments to the frame pointer are nonlocal gotos and are being done
3152 at a time when they are valid and do not disturb anything else.
3153 Some machines want to eliminate a fake argument pointer with either the
3154 frame or stack pointer. Assignments to the frame pointer must not prevent
3157 Called via note_stores from reload before starting its passes to scan
3158 the insns of the function. */
3161 mark_not_eliminable (dest, x)
3167 /* A SUBREG of a hard register here is just changing its mode. We should
3168 not see a SUBREG of an eliminable hard register, but check just in
3170 if (GET_CODE (dest) == SUBREG)
3171 dest = SUBREG_REG (dest);
3173 if (dest == frame_pointer_rtx)
3176 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3177 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3178 && (GET_CODE (x) != SET
3179 || GET_CODE (SET_SRC (x)) != PLUS
3180 || XEXP (SET_SRC (x), 0) != dest
3181 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3183 reg_eliminate[i].can_eliminate_previous
3184 = reg_eliminate[i].can_eliminate = 0;
3189 /* Kick all pseudos out of hard register REGNO.
3190 If GLOBAL is nonzero, try to find someplace else to put them.
3191 If DUMPFILE is nonzero, log actions taken on that file.
3193 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3194 because we found we can't eliminate some register. In the case, no pseudos
3195 are allowed to be in the register, even if they are only in a block that
3196 doesn't require spill registers, unlike the case when we are spilling this
3197 hard reg to produce another spill register.
3199 Return nonzero if any pseudos needed to be kicked out. */
3202 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3208 int something_changed = 0;
3211 SET_HARD_REG_BIT (forbidden_regs, regno);
3213 /* Spill every pseudo reg that was allocated to this reg
3214 or to something that overlaps this reg. */
3216 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3217 if (reg_renumber[i] >= 0
3218 && reg_renumber[i] <= regno
3220 + HARD_REGNO_NREGS (reg_renumber[i],
3221 PSEUDO_REGNO_MODE (i))
3224 enum reg_class class = REGNO_REG_CLASS (regno);
3226 /* If this register belongs solely to a basic block which needed no
3227 spilling of any class that this register is contained in,
3228 leave it be, unless we are spilling this register because
3229 it was a hard register that can't be eliminated. */
3231 if (! cant_eliminate
3232 && basic_block_needs[0]
3233 && reg_basic_block[i] >= 0
3234 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3238 for (p = reg_class_superclasses[(int) class];
3239 *p != LIM_REG_CLASSES; p++)
3240 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3243 if (*p == LIM_REG_CLASSES)
3247 /* Mark it as no longer having a hard register home. */
3248 reg_renumber[i] = -1;
3249 /* We will need to scan everything again. */
3250 something_changed = 1;
3252 retry_global_alloc (i, forbidden_regs);
3254 alter_reg (i, regno);
3257 if (reg_renumber[i] == -1)
3258 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3260 fprintf (dumpfile, " Register %d now in %d.\n\n",
3261 i, reg_renumber[i]);
3265 return something_changed;
3268 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3271 scan_paradoxical_subregs (x)
3276 register enum rtx_code code = GET_CODE (x);
3293 if (GET_CODE (SUBREG_REG (x)) == REG
3294 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3295 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3296 = GET_MODE_SIZE (GET_MODE (x));
3300 fmt = GET_RTX_FORMAT (code);
3301 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3304 scan_paradoxical_subregs (XEXP (x, i));
3305 else if (fmt[i] == 'E')
3308 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3309 scan_paradoxical_subregs (XVECEXP (x, i, j));
3315 hard_reg_use_compare (p1, p2)
3316 struct hard_reg_n_uses *p1, *p2;
3318 int tem = p1->uses - p2->uses;
3319 if (tem != 0) return tem;
3320 /* If regs are equally good, sort by regno,
3321 so that the results of qsort leave nothing to chance. */
3322 return p1->regno - p2->regno;
3325 /* Choose the order to consider regs for use as reload registers
3326 based on how much trouble would be caused by spilling one.
3327 Store them in order of decreasing preference in potential_reload_regs. */
3330 order_regs_for_reload ()
3336 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3338 CLEAR_HARD_REG_SET (bad_spill_regs);
3340 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3341 potential_reload_regs[i] = -1;
3343 /* Count number of uses of each hard reg by pseudo regs allocated to it
3344 and then order them by decreasing use. */
3346 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3348 hard_reg_n_uses[i].uses = 0;
3349 hard_reg_n_uses[i].regno = i;
3352 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3354 int regno = reg_renumber[i];
3357 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3359 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3361 large += reg_n_refs[i];
3364 /* Now fixed registers (which cannot safely be used for reloading)
3365 get a very high use count so they will be considered least desirable.
3366 Registers used explicitly in the rtl code are almost as bad. */
3368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3372 hard_reg_n_uses[i].uses += 2 * large + 2;
3373 SET_HARD_REG_BIT (bad_spill_regs, i);
3375 else if (regs_explicitly_used[i])
3377 hard_reg_n_uses[i].uses += large + 1;
3378 #ifndef SMALL_REGISTER_CLASSES
3379 /* ??? We are doing this here because of the potential that
3380 bad code may be generated if a register explicitly used in
3381 an insn was used as a spill register for that insn. But
3382 not using these are spill registers may lose on some machine.
3383 We'll have to see how this works out. */
3384 SET_HARD_REG_BIT (bad_spill_regs, i);
3388 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3389 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3391 #ifdef ELIMINABLE_REGS
3392 /* If registers other than the frame pointer are eliminable, mark them as
3394 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3396 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3397 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3401 /* Prefer registers not so far used, for use in temporary loading.
3402 Among them, if REG_ALLOC_ORDER is defined, use that order.
3403 Otherwise, prefer registers not preserved by calls. */
3405 #ifdef REG_ALLOC_ORDER
3406 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3408 int regno = reg_alloc_order[i];
3410 if (hard_reg_n_uses[regno].uses == 0)
3411 potential_reload_regs[o++] = regno;
3414 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3416 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3417 potential_reload_regs[o++] = i;
3419 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3421 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3422 potential_reload_regs[o++] = i;
3426 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3427 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3429 /* Now add the regs that are already used,
3430 preferring those used less often. The fixed and otherwise forbidden
3431 registers will be at the end of this list. */
3433 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3434 if (hard_reg_n_uses[i].uses != 0)
3435 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3438 /* Reload pseudo-registers into hard regs around each insn as needed.
3439 Additional register load insns are output before the insn that needs it
3440 and perhaps store insns after insns that modify the reloaded pseudo reg.
3442 reg_last_reload_reg and reg_reloaded_contents keep track of
3443 which registers are already available in reload registers.
3444 We update these for the reloads that we perform,
3445 as the insns are scanned. */
3448 reload_as_needed (first, live_known)
3458 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3459 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3460 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3461 reg_has_output_reload = (char *) alloca (max_regno);
3462 for (i = 0; i < n_spills; i++)
3464 reg_reloaded_contents[i] = -1;
3465 reg_reloaded_insn[i] = 0;
3468 /* Reset all offsets on eliminable registers to their initial values. */
3469 #ifdef ELIMINABLE_REGS
3470 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3472 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3473 reg_eliminate[i].initial_offset);
3474 reg_eliminate[i].previous_offset
3475 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3478 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3479 reg_eliminate[0].previous_offset
3480 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3483 num_not_at_initial_offset = 0;
3485 for (insn = first; insn;)
3487 register rtx next = NEXT_INSN (insn);
3489 /* Notice when we move to a new basic block. */
3490 if (live_known && this_block + 1 < n_basic_blocks
3491 && insn == basic_block_head[this_block+1])
3494 /* If we pass a label, copy the offsets from the label information
3495 into the current offsets of each elimination. */
3496 if (GET_CODE (insn) == CODE_LABEL)
3498 num_not_at_initial_offset = 0;
3499 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3501 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3502 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3503 if (reg_eliminate[i].can_eliminate
3504 && (reg_eliminate[i].offset
3505 != reg_eliminate[i].initial_offset))
3506 num_not_at_initial_offset++;
3510 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3512 rtx avoid_return_reg = 0;
3514 #ifdef SMALL_REGISTER_CLASSES
3515 /* Set avoid_return_reg if this is an insn
3516 that might use the value of a function call. */
3517 if (GET_CODE (insn) == CALL_INSN)
3519 if (GET_CODE (PATTERN (insn)) == SET)
3520 after_call = SET_DEST (PATTERN (insn));
3521 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3522 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3523 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3527 else if (after_call != 0
3528 && !(GET_CODE (PATTERN (insn)) == SET
3529 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3531 if (reg_mentioned_p (after_call, PATTERN (insn)))
3532 avoid_return_reg = after_call;
3535 #endif /* SMALL_REGISTER_CLASSES */
3537 /* If this is a USE and CLOBBER of a MEM, ensure that any
3538 references to eliminable registers have been removed. */
3540 if ((GET_CODE (PATTERN (insn)) == USE
3541 || GET_CODE (PATTERN (insn)) == CLOBBER)
3542 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3543 XEXP (XEXP (PATTERN (insn), 0), 0)
3544 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3545 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3547 /* If we need to do register elimination processing, do so.
3548 This might delete the insn, in which case we are done. */
3549 if (num_eliminable && GET_MODE (insn) == QImode)
3551 eliminate_regs_in_insn (insn, 1);
3552 if (GET_CODE (insn) == NOTE)
3559 if (GET_MODE (insn) == VOIDmode)
3561 /* First find the pseudo regs that must be reloaded for this insn.
3562 This info is returned in the tables reload_... (see reload.h).
3563 Also modify the body of INSN by substituting RELOAD
3564 rtx's for those pseudo regs. */
3567 bzero (reg_has_output_reload, max_regno);
3568 CLEAR_HARD_REG_SET (reg_is_output_reload);
3570 find_reloads (insn, 1, spill_indirect_levels, live_known,
3576 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3580 /* If this block has not had spilling done for a
3581 particular clas and we have any non-optionals that need a
3582 spill reg in that class, abort. */
3584 for (class = 0; class < N_REG_CLASSES; class++)
3585 if (basic_block_needs[class] != 0
3586 && basic_block_needs[class][this_block] == 0)
3587 for (i = 0; i < n_reloads; i++)
3588 if (class == (int) reload_reg_class[i]
3589 && reload_reg_rtx[i] == 0
3590 && ! reload_optional[i]
3591 && (reload_in[i] != 0 || reload_out[i] != 0
3592 || reload_secondary_p[i] != 0))
3595 /* Now compute which reload regs to reload them into. Perhaps
3596 reusing reload regs from previous insns, or else output
3597 load insns to reload them. Maybe output store insns too.
3598 Record the choices of reload reg in reload_reg_rtx. */
3599 choose_reload_regs (insn, avoid_return_reg);
3601 #ifdef SMALL_REGISTER_CLASSES
3602 /* Merge any reloads that we didn't combine for fear of
3603 increasing the number of spill registers needed but now
3604 discover can be safely merged. */
3605 merge_assigned_reloads (insn);
3608 /* Generate the insns to reload operands into or out of
3609 their reload regs. */
3610 emit_reload_insns (insn);
3612 /* Substitute the chosen reload regs from reload_reg_rtx
3613 into the insn's body (or perhaps into the bodies of other
3614 load and store insn that we just made for reloading
3615 and that we moved the structure into). */
3618 /* If this was an ASM, make sure that all the reload insns
3619 we have generated are valid. If not, give an error
3622 if (asm_noperands (PATTERN (insn)) >= 0)
3623 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3624 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3625 && (recog_memoized (p) < 0
3626 || (insn_extract (p),
3627 ! constrain_operands (INSN_CODE (p), 1))))
3629 error_for_asm (insn,
3630 "`asm' operand requires impossible reload");
3632 NOTE_SOURCE_FILE (p) = 0;
3633 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3636 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3637 is no longer validly lying around to save a future reload.
3638 Note that this does not detect pseudos that were reloaded
3639 for this insn in order to be stored in
3640 (obeying register constraints). That is correct; such reload
3641 registers ARE still valid. */
3642 note_stores (PATTERN (insn), forget_old_reloads_1);
3644 /* There may have been CLOBBER insns placed after INSN. So scan
3645 between INSN and NEXT and use them to forget old reloads. */
3646 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3647 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3648 note_stores (PATTERN (x), forget_old_reloads_1);
3651 /* Likewise for regs altered by auto-increment in this insn.
3652 But note that the reg-notes are not changed by reloading:
3653 they still contain the pseudo-regs, not the spill regs. */
3654 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3655 if (REG_NOTE_KIND (x) == REG_INC)
3657 /* See if this pseudo reg was reloaded in this insn.
3658 If so, its last-reload info is still valid
3659 because it is based on this insn's reload. */
3660 for (i = 0; i < n_reloads; i++)
3661 if (reload_out[i] == XEXP (x, 0))
3665 forget_old_reloads_1 (XEXP (x, 0));
3669 /* A reload reg's contents are unknown after a label. */
3670 if (GET_CODE (insn) == CODE_LABEL)
3671 for (i = 0; i < n_spills; i++)
3673 reg_reloaded_contents[i] = -1;
3674 reg_reloaded_insn[i] = 0;
3677 /* Don't assume a reload reg is still good after a call insn
3678 if it is a call-used reg. */
3679 else if (GET_CODE (insn) == CALL_INSN)
3680 for (i = 0; i < n_spills; i++)
3681 if (call_used_regs[spill_regs[i]])
3683 reg_reloaded_contents[i] = -1;
3684 reg_reloaded_insn[i] = 0;
3687 /* In case registers overlap, allow certain insns to invalidate
3688 particular hard registers. */
3690 #ifdef INSN_CLOBBERS_REGNO_P
3691 for (i = 0 ; i < n_spills ; i++)
3692 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3694 reg_reloaded_contents[i] = -1;
3695 reg_reloaded_insn[i] = 0;
3707 /* Discard all record of any value reloaded from X,
3708 or reloaded in X from someplace else;
3709 unless X is an output reload reg of the current insn.
3711 X may be a hard reg (the reload reg)
3712 or it may be a pseudo reg that was reloaded from. */
3715 forget_old_reloads_1 (x)
3722 /* note_stores does give us subregs of hard regs. */
3723 while (GET_CODE (x) == SUBREG)
3725 offset += SUBREG_WORD (x);
3729 if (GET_CODE (x) != REG)
3732 regno = REGNO (x) + offset;
3734 if (regno >= FIRST_PSEUDO_REGISTER)
3739 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3740 /* Storing into a spilled-reg invalidates its contents.
3741 This can happen if a block-local pseudo is allocated to that reg
3742 and it wasn't spilled because this block's total need is 0.
3743 Then some insn might have an optional reload and use this reg. */
3744 for (i = 0; i < nr; i++)
3745 if (spill_reg_order[regno + i] >= 0
3746 /* But don't do this if the reg actually serves as an output
3747 reload reg in the current instruction. */
3749 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3751 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3752 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3756 /* Since value of X has changed,
3757 forget any value previously copied from it. */
3760 /* But don't forget a copy if this is the output reload
3761 that establishes the copy's validity. */
3762 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3763 reg_last_reload_reg[regno + nr] = 0;
3766 /* For each reload, the mode of the reload register. */
3767 static enum machine_mode reload_mode[MAX_RELOADS];
3769 /* For each reload, the largest number of registers it will require. */
3770 static int reload_nregs[MAX_RELOADS];
3772 /* Comparison function for qsort to decide which of two reloads
3773 should be handled first. *P1 and *P2 are the reload numbers. */
3776 reload_reg_class_lower (p1, p2)
3779 register int r1 = *p1, r2 = *p2;
3782 /* Consider required reloads before optional ones. */
3783 t = reload_optional[r1] - reload_optional[r2];
3787 /* Count all solitary classes before non-solitary ones. */
3788 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3789 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3793 /* Aside from solitaires, consider all multi-reg groups first. */
3794 t = reload_nregs[r2] - reload_nregs[r1];
3798 /* Consider reloads in order of increasing reg-class number. */
3799 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3803 /* If reloads are equally urgent, sort by reload number,
3804 so that the results of qsort leave nothing to chance. */
3808 /* The following HARD_REG_SETs indicate when each hard register is
3809 used for a reload of various parts of the current insn. */
3811 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3812 static HARD_REG_SET reload_reg_used;
3813 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3814 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
3815 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
3816 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
3817 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
3818 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
3819 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
3820 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
3821 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3822 static HARD_REG_SET reload_reg_used_in_op_addr;
3823 /* If reg is in use for a RELOAD_FOR_INSN reload. */
3824 static HARD_REG_SET reload_reg_used_in_insn;
3825 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
3826 static HARD_REG_SET reload_reg_used_in_other_addr;
3828 /* If reg is in use as a reload reg for any sort of reload. */
3829 static HARD_REG_SET reload_reg_used_at_all;
3831 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
3832 TYPE. MODE is used to indicate how many consecutive regs are
3836 mark_reload_reg_in_use (regno, opnum, type, mode)
3839 enum reload_type type;
3840 enum machine_mode mode;
3842 int nregs = HARD_REGNO_NREGS (regno, mode);
3845 for (i = regno; i < nregs + regno; i++)
3850 SET_HARD_REG_BIT (reload_reg_used, i);
3853 case RELOAD_FOR_INPUT_ADDRESS:
3854 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
3857 case RELOAD_FOR_OUTPUT_ADDRESS:
3858 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
3861 case RELOAD_FOR_OPERAND_ADDRESS:
3862 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3865 case RELOAD_FOR_OTHER_ADDRESS:
3866 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
3869 case RELOAD_FOR_INPUT:
3870 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
3873 case RELOAD_FOR_OUTPUT:
3874 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
3877 case RELOAD_FOR_INSN:
3878 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
3882 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3886 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3887 specified by OPNUM and TYPE. */
3890 reload_reg_free_p (regno, opnum, type)
3893 enum reload_type type;
3897 /* In use for a RELOAD_OTHER means it's not available for anything except
3898 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
3899 to be used only for inputs. */
3901 if (type != RELOAD_FOR_OTHER_ADDRESS
3902 && TEST_HARD_REG_BIT (reload_reg_used, regno))
3908 /* In use for anything means not available for a RELOAD_OTHER. */
3909 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3911 /* The other kinds of use can sometimes share a register. */
3912 case RELOAD_FOR_INPUT:
3913 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
3914 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3917 /* If it is used for some other input, can't use it. */
3918 for (i = 0; i < reload_n_operands; i++)
3919 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
3922 /* If it is used in a later operand's address, can't use it. */
3923 for (i = opnum + 1; i < reload_n_operands; i++)
3924 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
3929 case RELOAD_FOR_INPUT_ADDRESS:
3930 /* Can't use a register if it is used for an input address for this
3931 operand or used as an input in an earlier one. */
3932 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
3935 for (i = 0; i < opnum; i++)
3936 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
3941 case RELOAD_FOR_OUTPUT_ADDRESS:
3942 /* Can't use a register if it is used for an output address for this
3943 operand or used as an output in this or a later operand. */
3944 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
3947 for (i = opnum; i < reload_n_operands; i++)
3948 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
3953 case RELOAD_FOR_OPERAND_ADDRESS:
3954 for (i = 0; i < reload_n_operands; i++)
3955 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
3958 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
3959 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
3961 case RELOAD_FOR_OUTPUT:
3962 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
3963 outputs, or an operand address for this or an earlier output. */
3964 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
3967 for (i = 0; i < reload_n_operands; i++)
3968 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
3971 for (i = 0; i <= opnum; i++)
3972 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
3977 case RELOAD_FOR_INSN:
3978 for (i = 0; i < reload_n_operands; i++)
3979 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
3980 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
3983 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
3984 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
3986 case RELOAD_FOR_OTHER_ADDRESS:
3987 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
3992 /* Return 1 if the value in reload reg REGNO, as used by a reload
3993 needed for the part of the insn specified by OPNUM and TYPE,
3994 is not in use for a reload in any prior part of the insn.
3996 We can assume that the reload reg was already tested for availability
3997 at the time it is needed, and we should not check this again,
3998 in case the reg has already been marked in use. */
4001 reload_reg_free_before_p (regno, opnum, type)
4004 enum reload_type type;
4010 case RELOAD_FOR_OTHER_ADDRESS:
4011 /* These always come first. */
4015 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4017 /* If this use is for part of the insn,
4018 check the reg is not in use for any prior part. It is tempting
4019 to try to do this by falling through from objecs that occur
4020 later in the insn to ones that occur earlier, but that will not
4021 correctly take into account the fact that here we MUST ignore
4022 things that would prevent the register from being allocated in
4023 the first place, since we know that it was allocated. */
4025 case RELOAD_FOR_OUTPUT_ADDRESS:
4026 /* Earlier reloads are for earlier outputs or their addresses,
4027 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4028 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4030 for (i = 0; i < opnum; i++)
4031 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4032 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4035 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4038 for (i = 0; i < reload_n_operands; i++)
4039 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4040 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4043 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4044 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4045 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4047 case RELOAD_FOR_OUTPUT:
4048 /* This can't be used in the output address for this operand and
4049 anything that can't be used for it, except that we've already
4050 tested for RELOAD_FOR_INSN objects. */
4052 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4055 for (i = 0; i < opnum; i++)
4056 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4057 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4060 for (i = 0; i < reload_n_operands; i++)
4061 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4062 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4063 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4066 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4068 case RELOAD_FOR_OPERAND_ADDRESS:
4069 case RELOAD_FOR_INSN:
4070 /* These can't conflict with inputs, or each other, so all we have to
4071 test is input addresses and the addresses of OTHER items. */
4073 for (i = 0; i < reload_n_operands; i++)
4074 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4077 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4079 case RELOAD_FOR_INPUT:
4080 /* The only things earlier are the address for this and
4081 earlier inputs, other inputs (which we know we don't conflict
4082 with), and addresses of RELOAD_OTHER objects. */
4084 for (i = 0; i <= opnum; i++)
4085 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4088 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4090 case RELOAD_FOR_INPUT_ADDRESS:
4091 /* Similarly, all we have to check is for use in earlier inputs'
4093 for (i = 0; i < opnum; i++)
4094 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4097 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4102 /* Return 1 if the value in reload reg REGNO, as used by a reload
4103 needed for the part of the insn specified by OPNUM and TYPE,
4104 is still available in REGNO at the end of the insn.
4106 We can assume that the reload reg was already tested for availability
4107 at the time it is needed, and we should not check this again,
4108 in case the reg has already been marked in use. */
4111 reload_reg_reaches_end_p (regno, opnum, type)
4114 enum reload_type type;
4121 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4122 its value must reach the end. */
4125 /* If this use is for part of the insn,
4126 its value reaches if no subsequent part uses the same register.
4127 Just like the above function, don't try to do this with lots
4130 case RELOAD_FOR_OTHER_ADDRESS:
4131 /* Here we check for everything else, since these don't conflict
4132 with anything else and everything comes later. */
4134 for (i = 0; i < reload_n_operands; i++)
4135 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4136 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4137 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4138 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4141 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4142 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4143 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4145 case RELOAD_FOR_INPUT_ADDRESS:
4146 /* Similar, except that we check only for this and subsequent inputs
4147 and the address of only subsequent inputs and we do not need
4148 to check for RELOAD_OTHER objects since they are known not to
4151 for (i = opnum; i < reload_n_operands; i++)
4152 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4155 for (i = opnum + 1; i < reload_n_operands; i++)
4156 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4159 for (i = 0; i < reload_n_operands; i++)
4160 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4161 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4164 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4165 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4167 case RELOAD_FOR_INPUT:
4168 /* Similar to input address, except we start at the next operand for
4169 both input and input address and we do not check for
4170 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4173 for (i = opnum + 1; i < reload_n_operands; i++)
4174 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4175 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4178 /* ... fall through ... */
4180 case RELOAD_FOR_OPERAND_ADDRESS:
4181 /* Check outputs and their addresses. */
4183 for (i = 0; i < reload_n_operands; i++)
4184 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4185 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4190 case RELOAD_FOR_INSN:
4191 /* These conflict with other outputs with with RELOAD_OTHER. So
4192 we need only check for output addresses. */
4196 /* ... fall through ... */
4198 case RELOAD_FOR_OUTPUT:
4199 case RELOAD_FOR_OUTPUT_ADDRESS:
4200 /* We already know these can't conflict with a later output. So the
4201 only thing to check are later output addresses. */
4202 for (i = opnum + 1; i < reload_n_operands; i++)
4203 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4212 /* Vector of reload-numbers showing the order in which the reloads should
4214 short reload_order[MAX_RELOADS];
4216 /* Indexed by reload number, 1 if incoming value
4217 inherited from previous insns. */
4218 char reload_inherited[MAX_RELOADS];
4220 /* For an inherited reload, this is the insn the reload was inherited from,
4221 if we know it. Otherwise, this is 0. */
4222 rtx reload_inheritance_insn[MAX_RELOADS];
4224 /* If non-zero, this is a place to get the value of the reload,
4225 rather than using reload_in. */
4226 rtx reload_override_in[MAX_RELOADS];
4228 /* For each reload, the index in spill_regs of the spill register used,
4229 or -1 if we did not need one of the spill registers for this reload. */
4230 int reload_spill_index[MAX_RELOADS];
4232 /* Index of last register assigned as a spill register. We allocate in
4233 a round-robin fashio. */
4235 static last_spill_reg = 0;
4237 /* Find a spill register to use as a reload register for reload R.
4238 LAST_RELOAD is non-zero if this is the last reload for the insn being
4241 Set reload_reg_rtx[R] to the register allocated.
4243 If NOERROR is nonzero, we return 1 if successful,
4244 or 0 if we couldn't find a spill reg and we didn't change anything. */
4247 allocate_reload_reg (r, insn, last_reload, noerror)
4259 /* If we put this reload ahead, thinking it is a group,
4260 then insist on finding a group. Otherwise we can grab a
4261 reg that some other reload needs.
4262 (That can happen when we have a 68000 DATA_OR_FP_REG
4263 which is a group of data regs or one fp reg.)
4264 We need not be so restrictive if there are no more reloads
4267 ??? Really it would be nicer to have smarter handling
4268 for that kind of reg class, where a problem like this is normal.
4269 Perhaps those classes should be avoided for reloading
4270 by use of more alternatives. */
4272 int force_group = reload_nregs[r] > 1 && ! last_reload;
4274 /* If we want a single register and haven't yet found one,
4275 take any reg in the right class and not in use.
4276 If we want a consecutive group, here is where we look for it.
4278 We use two passes so we can first look for reload regs to
4279 reuse, which are already in use for other reloads in this insn,
4280 and only then use additional registers.
4281 I think that maximizing reuse is needed to make sure we don't
4282 run out of reload regs. Suppose we have three reloads, and
4283 reloads A and B can share regs. These need two regs.
4284 Suppose A and B are given different regs.
4285 That leaves none for C. */
4286 for (pass = 0; pass < 2; pass++)
4288 /* I is the index in spill_regs.
4289 We advance it round-robin between insns to use all spill regs
4290 equally, so that inherited reloads have a chance
4291 of leapfrogging each other. */
4293 for (count = 0, i = last_spill_reg; count < n_spills; count++)
4295 int class = (int) reload_reg_class[r];
4297 i = (i + 1) % n_spills;
4299 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4300 reload_when_needed[r])
4301 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4302 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4303 /* Look first for regs to share, then for unshared. */
4304 && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all,
4307 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4308 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4309 (on 68000) got us two FP regs. If NR is 1,
4310 we would reject both of them. */
4312 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4313 /* If we need only one reg, we have already won. */
4316 /* But reject a single reg if we demand a group. */
4321 /* Otherwise check that as many consecutive regs as we need
4323 Also, don't use for a group registers that are
4324 needed for nongroups. */
4325 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4328 regno = spill_regs[i] + nr - 1;
4329 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4330 && spill_reg_order[regno] >= 0
4331 && reload_reg_free_p (regno, reload_opnum[r],
4332 reload_when_needed[r])
4333 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4343 /* If we found something on pass 1, omit pass 2. */
4344 if (count < n_spills)
4348 /* We should have found a spill register by now. */
4349 if (count == n_spills)
4358 /* Mark as in use for this insn the reload regs we use for this. */
4359 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4360 reload_when_needed[r], reload_mode[r]);
4362 new = spill_reg_rtx[i];
4364 if (new == 0 || GET_MODE (new) != reload_mode[r])
4365 spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4367 reload_reg_rtx[r] = new;
4368 reload_spill_index[r] = i;
4369 regno = true_regnum (new);
4371 /* Detect when the reload reg can't hold the reload mode.
4372 This used to be one `if', but Sequent compiler can't handle that. */
4373 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4375 enum machine_mode test_mode = VOIDmode;
4377 test_mode = GET_MODE (reload_in[r]);
4378 /* If reload_in[r] has VOIDmode, it means we will load it
4379 in whatever mode the reload reg has: to wit, reload_mode[r].
4380 We have already tested that for validity. */
4381 /* Aside from that, we need to test that the expressions
4382 to reload from or into have modes which are valid for this
4383 reload register. Otherwise the reload insns would be invalid. */
4384 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4385 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4386 if (! (reload_out[r] != 0
4387 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4388 /* The reg is OK. */
4392 /* The reg is not OK. */
4397 if (asm_noperands (PATTERN (insn)) < 0)
4398 /* It's the compiler's fault. */
4401 /* It's the user's fault; the operand's mode and constraint
4402 don't match. Disable this reload so we don't crash in final. */
4403 error_for_asm (insn,
4404 "`asm' operand constraint incompatible with operand size");
4407 reload_reg_rtx[r] = 0;
4408 reload_optional[r] = 1;
4409 reload_secondary_p[r] = 1;
4414 /* Assign hard reg targets for the pseudo-registers we must reload
4415 into hard regs for this insn.
4416 Also output the instructions to copy them in and out of the hard regs.
4418 For machines with register classes, we are responsible for
4419 finding a reload reg in the proper class. */
4422 choose_reload_regs (insn, avoid_return_reg)
4424 rtx avoid_return_reg;
4427 int max_group_size = 1;
4428 enum reg_class group_class = NO_REGS;
4431 rtx save_reload_reg_rtx[MAX_RELOADS];
4432 char save_reload_inherited[MAX_RELOADS];
4433 rtx save_reload_inheritance_insn[MAX_RELOADS];
4434 rtx save_reload_override_in[MAX_RELOADS];
4435 int save_reload_spill_index[MAX_RELOADS];
4436 HARD_REG_SET save_reload_reg_used;
4437 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4438 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4439 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4440 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4441 HARD_REG_SET save_reload_reg_used_in_op_addr;
4442 HARD_REG_SET save_reload_reg_used_in_insn;
4443 HARD_REG_SET save_reload_reg_used_in_other_addr;
4444 HARD_REG_SET save_reload_reg_used_at_all;
4446 bzero (reload_inherited, MAX_RELOADS);
4447 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4448 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4450 CLEAR_HARD_REG_SET (reload_reg_used);
4451 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4452 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4453 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4454 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4456 for (i = 0; i < reload_n_operands; i++)
4458 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4459 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4460 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4461 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4464 #ifdef SMALL_REGISTER_CLASSES
4465 /* Don't bother with avoiding the return reg
4466 if we have no mandatory reload that could use it. */
4467 if (avoid_return_reg)
4470 int regno = REGNO (avoid_return_reg);
4472 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4475 for (r = regno; r < regno + nregs; r++)
4476 if (spill_reg_order[r] >= 0)
4477 for (j = 0; j < n_reloads; j++)
4478 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4479 && (reload_in[j] != 0 || reload_out[j] != 0
4480 || reload_secondary_p[j])
4482 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4485 avoid_return_reg = 0;
4487 #endif /* SMALL_REGISTER_CLASSES */
4489 #if 0 /* Not needed, now that we can always retry without inheritance. */
4490 /* See if we have more mandatory reloads than spill regs.
4491 If so, then we cannot risk optimizations that could prevent
4492 reloads from sharing one spill register.
4494 Since we will try finding a better register than reload_reg_rtx
4495 unless it is equal to reload_in or reload_out, count such reloads. */
4499 #ifdef SMALL_REGISTER_CLASSES
4500 int tem = (avoid_return_reg != 0);
4502 for (j = 0; j < n_reloads; j++)
4503 if (! reload_optional[j]
4504 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4505 && (reload_reg_rtx[j] == 0
4506 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4507 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4514 #ifdef SMALL_REGISTER_CLASSES
4515 /* Don't use the subroutine call return reg for a reload
4516 if we are supposed to avoid it. */
4517 if (avoid_return_reg)
4519 int regno = REGNO (avoid_return_reg);
4521 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4524 for (r = regno; r < regno + nregs; r++)
4525 if (spill_reg_order[r] >= 0)
4526 SET_HARD_REG_BIT (reload_reg_used, r);
4528 #endif /* SMALL_REGISTER_CLASSES */
4530 /* In order to be certain of getting the registers we need,
4531 we must sort the reloads into order of increasing register class.
4532 Then our grabbing of reload registers will parallel the process
4533 that provided the reload registers.
4535 Also note whether any of the reloads wants a consecutive group of regs.
4536 If so, record the maximum size of the group desired and what
4537 register class contains all the groups needed by this insn. */
4539 for (j = 0; j < n_reloads; j++)
4541 reload_order[j] = j;
4542 reload_spill_index[j] = -1;
4545 = (reload_inmode[j] == VOIDmode
4546 || (GET_MODE_SIZE (reload_outmode[j])
4547 > GET_MODE_SIZE (reload_inmode[j])))
4548 ? reload_outmode[j] : reload_inmode[j];
4550 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4552 if (reload_nregs[j] > 1)
4554 max_group_size = MAX (reload_nregs[j], max_group_size);
4555 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4558 /* If we have already decided to use a certain register,
4559 don't use it in another way. */
4560 if (reload_reg_rtx[j])
4561 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
4562 reload_when_needed[j], reload_mode[j]);
4566 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4568 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4569 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4570 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4571 sizeof reload_inheritance_insn);
4572 bcopy (reload_override_in, save_reload_override_in,
4573 sizeof reload_override_in);
4574 bcopy (reload_spill_index, save_reload_spill_index,
4575 sizeof reload_spill_index);
4576 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4577 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4578 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4579 reload_reg_used_in_op_addr);
4580 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
4581 reload_reg_used_in_insn);
4582 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
4583 reload_reg_used_in_other_addr);
4585 for (i = 0; i < reload_n_operands; i++)
4587 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
4588 reload_reg_used_in_output[i]);
4589 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
4590 reload_reg_used_in_input[i]);
4591 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
4592 reload_reg_used_in_input_addr[i]);
4593 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
4594 reload_reg_used_in_output_addr[i]);
4597 /* If -O, try first with inheritance, then turning it off.
4598 If not -O, don't do inheritance.
4599 Using inheritance when not optimizing leads to paradoxes
4600 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4601 because one side of the comparison might be inherited. */
4603 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
4605 /* Process the reloads in order of preference just found.
4606 Beyond this point, subregs can be found in reload_reg_rtx.
4608 This used to look for an existing reloaded home for all
4609 of the reloads, and only then perform any new reloads.
4610 But that could lose if the reloads were done out of reg-class order
4611 because a later reload with a looser constraint might have an old
4612 home in a register needed by an earlier reload with a tighter constraint.
4614 To solve this, we make two passes over the reloads, in the order
4615 described above. In the first pass we try to inherit a reload
4616 from a previous insn. If there is a later reload that needs a
4617 class that is a proper subset of the class being processed, we must
4618 also allocate a spill register during the first pass.
4620 Then make a second pass over the reloads to allocate any reloads
4621 that haven't been given registers yet. */
4623 for (j = 0; j < n_reloads; j++)
4625 register int r = reload_order[j];
4627 /* Ignore reloads that got marked inoperative. */
4628 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4631 /* If find_reloads chose a to use reload_in or reload_out as a reload
4632 register, we don't need to chose one. Otherwise, try even if it found
4633 one since we might save an insn if we find the value lying around. */
4634 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4635 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4636 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4639 #if 0 /* No longer needed for correct operation.
4640 It might give better code, or might not; worth an experiment? */
4641 /* If this is an optional reload, we can't inherit from earlier insns
4642 until we are sure that any non-optional reloads have been allocated.
4643 The following code takes advantage of the fact that optional reloads
4644 are at the end of reload_order. */
4645 if (reload_optional[r] != 0)
4646 for (i = 0; i < j; i++)
4647 if ((reload_out[reload_order[i]] != 0
4648 || reload_in[reload_order[i]] != 0
4649 || reload_secondary_p[reload_order[i]])
4650 && ! reload_optional[reload_order[i]]
4651 && reload_reg_rtx[reload_order[i]] == 0)
4652 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4655 /* First see if this pseudo is already available as reloaded
4656 for a previous insn. We cannot try to inherit for reloads
4657 that are smaller than the maximum number of registers needed
4658 for groups unless the register we would allocate cannot be used
4661 We could check here to see if this is a secondary reload for
4662 an object that is already in a register of the desired class.
4663 This would avoid the need for the secondary reload register.
4664 But this is complex because we can't easily determine what
4665 objects might want to be loaded via this reload. So let a register
4666 be allocated here. In `emit_reload_insns' we suppress one of the
4667 loads in the case described above. */
4671 register int regno = -1;
4672 enum machine_mode mode;
4674 if (reload_in[r] == 0)
4676 else if (GET_CODE (reload_in[r]) == REG)
4678 regno = REGNO (reload_in[r]);
4679 mode = GET_MODE (reload_in[r]);
4681 else if (GET_CODE (reload_in_reg[r]) == REG)
4683 regno = REGNO (reload_in_reg[r]);
4684 mode = GET_MODE (reload_in_reg[r]);
4687 /* This won't work, since REGNO can be a pseudo reg number.
4688 Also, it takes much more hair to keep track of all the things
4689 that can invalidate an inherited reload of part of a pseudoreg. */
4690 else if (GET_CODE (reload_in[r]) == SUBREG
4691 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4692 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4695 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4697 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4699 if (reg_reloaded_contents[i] == regno
4700 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
4701 >= GET_MODE_SIZE (mode))
4702 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4703 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4705 && (reload_nregs[r] == max_group_size
4706 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4708 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
4709 reload_when_needed[r])
4710 && reload_reg_free_before_p (spill_regs[i],
4712 reload_when_needed[r]))
4714 /* If a group is needed, verify that all the subsequent
4715 registers still have their values intact. */
4717 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4720 for (k = 1; k < nr; k++)
4721 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4727 /* Mark the register as in use for this part of
4729 mark_reload_reg_in_use (spill_regs[i],
4731 reload_when_needed[r],
4733 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4734 reload_inherited[r] = 1;
4735 reload_inheritance_insn[r] = reg_reloaded_insn[i];
4736 reload_spill_index[r] = i;
4742 /* Here's another way to see if the value is already lying around. */
4744 && reload_in[r] != 0
4745 && ! reload_inherited[r]
4746 && reload_out[r] == 0
4747 && (CONSTANT_P (reload_in[r])
4748 || GET_CODE (reload_in[r]) == PLUS
4749 || GET_CODE (reload_in[r]) == REG
4750 || GET_CODE (reload_in[r]) == MEM)
4751 && (reload_nregs[r] == max_group_size
4752 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4755 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4756 -1, NULL_PTR, 0, reload_mode[r]);
4761 if (GET_CODE (equiv) == REG)
4762 regno = REGNO (equiv);
4763 else if (GET_CODE (equiv) == SUBREG)
4765 regno = REGNO (SUBREG_REG (equiv));
4766 if (regno < FIRST_PSEUDO_REGISTER)
4767 regno += SUBREG_WORD (equiv);
4773 /* If we found a spill reg, reject it unless it is free
4774 and of the desired class. */
4776 && ((spill_reg_order[regno] >= 0
4777 && ! reload_reg_free_before_p (regno, reload_opnum[r],
4778 reload_when_needed[r]))
4779 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4783 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4786 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4789 /* We found a register that contains the value we need.
4790 If this register is the same as an `earlyclobber' operand
4791 of the current insn, just mark it as a place to reload from
4792 since we can't use it as the reload register itself. */
4795 for (i = 0; i < n_earlyclobbers; i++)
4796 if (reg_overlap_mentioned_for_reload_p (equiv,
4797 reload_earlyclobbers[i]))
4799 reload_override_in[r] = equiv;
4804 /* JRV: If the equiv register we have found is explicitly
4805 clobbered in the current insn, mark but don't use, as above. */
4807 if (equiv != 0 && regno_clobbered_p (regno, insn))
4809 reload_override_in[r] = equiv;
4813 /* If we found an equivalent reg, say no code need be generated
4814 to load it, and use it as our reload reg. */
4815 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4817 reload_reg_rtx[r] = equiv;
4818 reload_inherited[r] = 1;
4819 /* If it is a spill reg,
4820 mark the spill reg as in use for this insn. */
4821 i = spill_reg_order[regno];
4823 mark_reload_reg_in_use (regno, reload_opnum[r],
4824 reload_when_needed[r],
4829 /* If we found a register to use already, or if this is an optional
4830 reload, we are done. */
4831 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4834 #if 0 /* No longer needed for correct operation. Might or might not
4835 give better code on the average. Want to experiment? */
4837 /* See if there is a later reload that has a class different from our
4838 class that intersects our class or that requires less register
4839 than our reload. If so, we must allocate a register to this
4840 reload now, since that reload might inherit a previous reload
4841 and take the only available register in our class. Don't do this
4842 for optional reloads since they will force all previous reloads
4843 to be allocated. Also don't do this for reloads that have been
4846 for (i = j + 1; i < n_reloads; i++)
4848 int s = reload_order[i];
4850 if ((reload_in[s] == 0 && reload_out[s] == 0
4851 && ! reload_secondary_p[s])
4852 || reload_optional[s])
4855 if ((reload_reg_class[s] != reload_reg_class[r]
4856 && reg_classes_intersect_p (reload_reg_class[r],
4857 reload_reg_class[s]))
4858 || reload_nregs[s] < reload_nregs[r])
4865 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4869 /* Now allocate reload registers for anything non-optional that
4870 didn't get one yet. */
4871 for (j = 0; j < n_reloads; j++)
4873 register int r = reload_order[j];
4875 /* Ignore reloads that got marked inoperative. */
4876 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4879 /* Skip reloads that already have a register allocated or are
4881 if (reload_reg_rtx[r] != 0 || reload_optional[r])
4884 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4888 /* If that loop got all the way, we have won. */
4893 /* Loop around and try without any inheritance. */
4894 /* First undo everything done by the failed attempt
4895 to allocate with inheritance. */
4896 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4897 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4898 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4899 sizeof reload_inheritance_insn);
4900 bcopy (save_reload_override_in, reload_override_in,
4901 sizeof reload_override_in);
4902 bcopy (save_reload_spill_index, reload_spill_index,
4903 sizeof reload_spill_index);
4904 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4905 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4906 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4907 save_reload_reg_used_in_op_addr);
4908 COPY_HARD_REG_SET (reload_reg_used_in_insn,
4909 save_reload_reg_used_in_insn);
4910 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
4911 save_reload_reg_used_in_other_addr);
4913 for (i = 0; i < reload_n_operands; i++)
4915 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
4916 save_reload_reg_used_in_input[i]);
4917 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
4918 save_reload_reg_used_in_output[i]);
4919 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
4920 save_reload_reg_used_in_input_addr[i]);
4921 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
4922 save_reload_reg_used_in_output_addr[i]);
4926 /* If we thought we could inherit a reload, because it seemed that
4927 nothing else wanted the same reload register earlier in the insn,
4928 verify that assumption, now that all reloads have been assigned. */
4930 for (j = 0; j < n_reloads; j++)
4932 register int r = reload_order[j];
4934 if (reload_inherited[r] && reload_reg_rtx[r] != 0
4935 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
4937 reload_when_needed[r]))
4938 reload_inherited[r] = 0;
4940 /* If we found a better place to reload from,
4941 validate it in the same fashion, if it is a reload reg. */
4942 if (reload_override_in[r]
4943 && (GET_CODE (reload_override_in[r]) == REG
4944 || GET_CODE (reload_override_in[r]) == SUBREG))
4946 int regno = true_regnum (reload_override_in[r]);
4947 if (spill_reg_order[regno] >= 0
4948 && ! reload_reg_free_before_p (regno, reload_opnum[r],
4949 reload_when_needed[r]))
4950 reload_override_in[r] = 0;
4954 /* Now that reload_override_in is known valid,
4955 actually override reload_in. */
4956 for (j = 0; j < n_reloads; j++)
4957 if (reload_override_in[j])
4958 reload_in[j] = reload_override_in[j];
4960 /* If this reload won't be done because it has been cancelled or is
4961 optional and not inherited, clear reload_reg_rtx so other
4962 routines (such as subst_reloads) don't get confused. */
4963 for (j = 0; j < n_reloads; j++)
4964 if ((reload_optional[j] && ! reload_inherited[j])
4965 || (reload_in[j] == 0 && reload_out[j] == 0
4966 && ! reload_secondary_p[j]))
4967 reload_reg_rtx[j] = 0;
4969 /* Record which pseudos and which spill regs have output reloads. */
4970 for (j = 0; j < n_reloads; j++)
4972 register int r = reload_order[j];
4974 i = reload_spill_index[r];
4976 /* I is nonneg if this reload used one of the spill regs.
4977 If reload_reg_rtx[r] is 0, this is an optional reload
4978 that we opted to ignore. */
4979 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
4980 && reload_reg_rtx[r] != 0)
4982 register int nregno = REGNO (reload_out[r]);
4985 if (nregno < FIRST_PSEUDO_REGISTER)
4986 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
4989 reg_has_output_reload[nregno + nr] = 1;
4993 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4995 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
4998 if (reload_when_needed[r] != RELOAD_OTHER
4999 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5000 && reload_when_needed[r] != RELOAD_FOR_INSN)
5006 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5007 reloads of the same item for fear that we might not have enough reload
5008 registers. However, normally they will get the same reload register
5009 and hence actually need not be loaded twice.
5011 Here we check for the most common case of this phenomenon: when we have
5012 a number of reloads for the same object, each of which were allocated
5013 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5014 reload, and is not modified in the insn itself. If we find such,
5015 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5016 This will not increase the number of spill registers needed and will
5017 prevent redundant code. */
5019 #ifdef SMALL_REGISTER_CLASSES
5022 merge_assigned_reloads (insn)
5027 /* Scan all the reloads looking for ones that only load values and
5028 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5029 assigned and not modified by INSN. */
5031 for (i = 0; i < n_reloads; i++)
5033 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5034 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5035 || reg_set_p (reload_reg_rtx[i], insn))
5038 /* Look at all other reloads. Ensure that the only use of this
5039 reload_reg_rtx is in a reload that just loads the same value
5040 as we do. Note that any secondary reloads must be of the identical
5041 class since the values, modes, and result registers are the
5042 same, so we need not do anything with any secondary reloads. */
5044 for (j = 0; j < n_reloads; j++)
5046 if (i == j || reload_reg_rtx[j] == 0
5047 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5051 /* If the reload regs aren't exactly the same (e.g, different modes)
5052 or if the values are different, we can't merge anything with this
5055 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5056 || reload_out[j] != 0 || reload_in[j] == 0
5057 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5061 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5062 we, in fact, found any matching reloads. */
5066 for (j = 0; j < n_reloads; j++)
5067 if (i != j && reload_reg_rtx[j] != 0
5068 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5070 reload_when_needed[i] = RELOAD_OTHER;
5072 transfer_replacements (i, j);
5075 /* If this is now RELOAD_OTHER, look for any reloads that load
5076 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5077 if they were for inputs, RELOAD_OTHER for outputs. Note that
5078 this test is equivalent to looking for reloads for this operand
5081 if (reload_when_needed[i] == RELOAD_OTHER)
5082 for (j = 0; j < n_reloads; j++)
5083 if (reload_in[j] != 0
5084 && reload_when_needed[i] != RELOAD_OTHER
5085 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5087 reload_when_needed[j]
5088 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5089 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5093 #endif /* SMALL_RELOAD_CLASSES */
5095 /* Output insns to reload values in and out of the chosen reload regs. */
5098 emit_reload_insns (insn)
5102 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5103 rtx other_input_address_reload_insns = 0;
5104 rtx other_input_reload_insns = 0;
5105 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5106 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5107 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5108 rtx operand_reload_insns = 0;
5109 rtx following_insn = NEXT_INSN (insn);
5110 rtx before_insn = insn;
5112 /* Values to be put in spill_reg_store are put here first. */
5113 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5115 for (j = 0; j < reload_n_operands; j++)
5116 input_reload_insns[j] = input_address_reload_insns[j]
5117 = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5119 /* If this is a CALL_INSN preceded by USE insns, any reload insns
5120 must go in front of the first USE insn, not in front of INSN. */
5122 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
5123 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
5124 while (GET_CODE (PREV_INSN (before_insn)) == INSN
5125 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
5126 before_insn = PREV_INSN (before_insn);
5128 /* If this insn is followed by any CLOBBER insns made by find_reloads,
5129 put our reloads after them since they may otherwise be
5132 while (NEXT_INSN (following_insn) != 0
5133 && GET_CODE (NEXT_INSN (following_insn)) == INSN
5134 && GET_MODE (NEXT_INSN (following_insn)) == DImode
5135 && GET_CODE (PATTERN (NEXT_INSN (following_insn))) == CLOBBER)
5136 following_insn = NEXT_INSN (following_insn);
5138 /* Now output the instructions to copy the data into and out of the
5139 reload registers. Do these in the order that the reloads were reported,
5140 since reloads of base and index registers precede reloads of operands
5141 and the operands may need the base and index registers reloaded. */
5143 for (j = 0; j < n_reloads; j++)
5146 rtx oldequiv_reg = 0;
5150 if (old != 0 && ! reload_inherited[j]
5151 && ! rtx_equal_p (reload_reg_rtx[j], old)
5152 && reload_reg_rtx[j] != 0)
5154 register rtx reloadreg = reload_reg_rtx[j];
5156 enum machine_mode mode;
5159 /* Determine the mode to reload in.
5160 This is very tricky because we have three to choose from.
5161 There is the mode the insn operand wants (reload_inmode[J]).
5162 There is the mode of the reload register RELOADREG.
5163 There is the intrinsic mode of the operand, which we could find
5164 by stripping some SUBREGs.
5165 It turns out that RELOADREG's mode is irrelevant:
5166 we can change that arbitrarily.
5168 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5169 then the reload reg may not support QImode moves, so use SImode.
5170 If foo is in memory due to spilling a pseudo reg, this is safe,
5171 because the QImode value is in the least significant part of a
5172 slot big enough for a SImode. If foo is some other sort of
5173 memory reference, then it is impossible to reload this case,
5174 so previous passes had better make sure this never happens.
5176 Then consider a one-word union which has SImode and one of its
5177 members is a float, being fetched as (SUBREG:SF union:SI).
5178 We must fetch that as SFmode because we could be loading into
5179 a float-only register. In this case OLD's mode is correct.
5181 Consider an immediate integer: it has VOIDmode. Here we need
5182 to get a mode from something else.
5184 In some cases, there is a fourth mode, the operand's
5185 containing mode. If the insn specifies a containing mode for
5186 this operand, it overrides all others.
5188 I am not sure whether the algorithm here is always right,
5189 but it does the right things in those cases. */
5191 mode = GET_MODE (old);
5192 if (mode == VOIDmode)
5193 mode = reload_inmode[j];
5195 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5196 /* If we need a secondary register for this operation, see if
5197 the value is already in a register in that class. Don't
5198 do this if the secondary register will be used as a scratch
5201 if (reload_secondary_reload[j] >= 0
5202 && reload_secondary_icode[j] == CODE_FOR_nothing
5205 = find_equiv_reg (old, insn,
5206 reload_reg_class[reload_secondary_reload[j]],
5207 -1, NULL_PTR, 0, mode);
5210 /* If reloading from memory, see if there is a register
5211 that already holds the same value. If so, reload from there.
5212 We can pass 0 as the reload_reg_p argument because
5213 any other reload has either already been emitted,
5214 in which case find_equiv_reg will see the reload-insn,
5215 or has yet to be emitted, in which case it doesn't matter
5216 because we will use this equiv reg right away. */
5218 if (oldequiv == 0 && optimize
5219 && (GET_CODE (old) == MEM
5220 || (GET_CODE (old) == REG
5221 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5222 && reg_renumber[REGNO (old)] < 0)))
5223 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5224 -1, NULL_PTR, 0, mode);
5228 int regno = true_regnum (oldequiv);
5230 /* If OLDEQUIV is a spill register, don't use it for this
5231 if any other reload needs it at an earlier stage of this insn
5232 or at this stage. */
5233 if (spill_reg_order[regno] >= 0
5234 && (! reload_reg_free_p (regno, reload_opnum[j],
5235 reload_when_needed[j])
5236 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5237 reload_when_needed[j])))
5240 /* If OLDEQUIV is not a spill register,
5241 don't use it if any other reload wants it. */
5242 if (spill_reg_order[regno] < 0)
5245 for (k = 0; k < n_reloads; k++)
5246 if (reload_reg_rtx[k] != 0 && k != j
5247 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5255 /* If it is no cheaper to copy from OLDEQUIV into the
5256 reload register than it would be to move from memory,
5257 don't use it. Likewise, if we need a secondary register
5261 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5262 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5263 reload_reg_class[j])
5264 >= MEMORY_MOVE_COST (mode)))
5265 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5266 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5270 #ifdef SECONDARY_MEMORY_NEEDED
5271 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5272 REGNO_REG_CLASS (regno),
5281 else if (GET_CODE (oldequiv) == REG)
5282 oldequiv_reg = oldequiv;
5283 else if (GET_CODE (oldequiv) == SUBREG)
5284 oldequiv_reg = SUBREG_REG (oldequiv);
5286 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5287 then load RELOADREG from OLDEQUIV. */
5289 if (GET_MODE (reloadreg) != mode)
5290 reloadreg = gen_lowpart_common (mode, reloadreg);
5291 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5292 oldequiv = SUBREG_REG (oldequiv);
5293 if (GET_MODE (oldequiv) != VOIDmode
5294 && mode != GET_MODE (oldequiv))
5295 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5297 /* Switch to the right place to emit the reload insns. */
5298 switch (reload_when_needed[j])
5301 where = &other_input_reload_insns;
5303 case RELOAD_FOR_INPUT:
5304 where = &input_reload_insns[reload_opnum[j]];
5306 case RELOAD_FOR_INPUT_ADDRESS:
5307 where = &input_address_reload_insns[reload_opnum[j]];
5309 case RELOAD_FOR_OUTPUT_ADDRESS:
5310 where = &output_address_reload_insns[reload_opnum[j]];
5312 case RELOAD_FOR_OPERAND_ADDRESS:
5313 where = &operand_reload_insns;
5315 case RELOAD_FOR_OTHER_ADDRESS:
5316 where = &other_input_address_reload_insns;
5322 push_to_sequence (*where);
5325 /* Auto-increment addresses must be reloaded in a special way. */
5326 if (GET_CODE (oldequiv) == POST_INC
5327 || GET_CODE (oldequiv) == POST_DEC
5328 || GET_CODE (oldequiv) == PRE_INC
5329 || GET_CODE (oldequiv) == PRE_DEC)
5331 /* We are not going to bother supporting the case where a
5332 incremented register can't be copied directly from
5333 OLDEQUIV since this seems highly unlikely. */
5334 if (reload_secondary_reload[j] >= 0)
5336 /* Prevent normal processing of this reload. */
5338 /* Output a special code sequence for this case. */
5339 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5342 /* If we are reloading a pseudo-register that was set by the previous
5343 insn, see if we can get rid of that pseudo-register entirely
5344 by redirecting the previous insn into our reload register. */
5346 else if (optimize && GET_CODE (old) == REG
5347 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5348 && dead_or_set_p (insn, old)
5349 /* This is unsafe if some other reload
5350 uses the same reg first. */
5351 && reload_reg_free_before_p (REGNO (reloadreg),
5353 reload_when_needed[j]))
5355 rtx temp = PREV_INSN (insn);
5356 while (temp && GET_CODE (temp) == NOTE)
5357 temp = PREV_INSN (temp);
5359 && GET_CODE (temp) == INSN
5360 && GET_CODE (PATTERN (temp)) == SET
5361 && SET_DEST (PATTERN (temp)) == old
5362 /* Make sure we can access insn_operand_constraint. */
5363 && asm_noperands (PATTERN (temp)) < 0
5364 /* This is unsafe if prev insn rejects our reload reg. */
5365 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5367 /* This is unsafe if operand occurs more than once in current
5368 insn. Perhaps some occurrences aren't reloaded. */
5369 && count_occurrences (PATTERN (insn), old) == 1
5370 /* Don't risk splitting a matching pair of operands. */
5371 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5373 /* Store into the reload register instead of the pseudo. */
5374 SET_DEST (PATTERN (temp)) = reloadreg;
5375 /* If these are the only uses of the pseudo reg,
5376 pretend for GDB it lives in the reload reg we used. */
5377 if (reg_n_deaths[REGNO (old)] == 1
5378 && reg_n_sets[REGNO (old)] == 1)
5380 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5381 alter_reg (REGNO (old), -1);
5387 /* We can't do that, so output an insn to load RELOADREG. */
5391 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5392 rtx second_reload_reg = 0;
5393 enum insn_code icode;
5395 /* If we have a secondary reload, pick up the secondary register
5396 and icode, if any. If OLDEQUIV and OLD are different or
5397 if this is an in-out reload, recompute whether or not we
5398 still need a secondary register and what the icode should
5399 be. If we still need a secondary register and the class or
5400 icode is different, go back to reloading from OLD if using
5401 OLDEQUIV means that we got the wrong type of register. We
5402 cannot have different class or icode due to an in-out reload
5403 because we don't make such reloads when both the input and
5404 output need secondary reload registers. */
5406 if (reload_secondary_reload[j] >= 0)
5408 int secondary_reload = reload_secondary_reload[j];
5409 rtx real_oldequiv = oldequiv;
5412 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5413 and similarly for OLD.
5414 See comments in find_secondary_reload in reload.c. */
5415 if (GET_CODE (oldequiv) == REG
5416 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5417 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5418 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5420 if (GET_CODE (old) == REG
5421 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5422 && reg_equiv_mem[REGNO (old)] != 0)
5423 real_old = reg_equiv_mem[REGNO (old)];
5425 second_reload_reg = reload_reg_rtx[secondary_reload];
5426 icode = reload_secondary_icode[j];
5428 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5429 || (reload_in[j] != 0 && reload_out[j] != 0))
5431 enum reg_class new_class
5432 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5433 mode, real_oldequiv);
5435 if (new_class == NO_REGS)
5436 second_reload_reg = 0;
5439 enum insn_code new_icode;
5440 enum machine_mode new_mode;
5442 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5443 REGNO (second_reload_reg)))
5444 oldequiv = old, real_oldequiv = real_old;
5447 new_icode = reload_in_optab[(int) mode];
5448 if (new_icode != CODE_FOR_nothing
5449 && ((insn_operand_predicate[(int) new_icode][0]
5450 && ! ((*insn_operand_predicate[(int) new_icode][0])
5452 || (insn_operand_predicate[(int) new_icode][1]
5453 && ! ((*insn_operand_predicate[(int) new_icode][1])
5454 (real_oldequiv, mode)))))
5455 new_icode = CODE_FOR_nothing;
5457 if (new_icode == CODE_FOR_nothing)
5460 new_mode = insn_operand_mode[new_icode][2];
5462 if (GET_MODE (second_reload_reg) != new_mode)
5464 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5466 oldequiv = old, real_oldequiv = real_old;
5469 = gen_rtx (REG, new_mode,
5470 REGNO (second_reload_reg));
5476 /* If we still need a secondary reload register, check
5477 to see if it is being used as a scratch or intermediate
5478 register and generate code appropriately. If we need
5479 a scratch register, use REAL_OLDEQUIV since the form of
5480 the insn may depend on the actual address if it is
5483 if (second_reload_reg)
5485 if (icode != CODE_FOR_nothing)
5487 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
5488 second_reload_reg));
5493 /* See if we need a scratch register to load the
5494 intermediate register (a tertiary reload). */
5495 enum insn_code tertiary_icode
5496 = reload_secondary_icode[secondary_reload];
5498 if (tertiary_icode != CODE_FOR_nothing)
5500 rtx third_reload_reg
5501 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5503 emit_insn ((GEN_FCN (tertiary_icode)
5504 (second_reload_reg, real_oldequiv,
5505 third_reload_reg)));
5508 gen_input_reload (second_reload_reg, oldequiv,
5510 reload_when_needed[j]);
5512 oldequiv = second_reload_reg;
5519 gen_input_reload (reloadreg, oldequiv, reload_opnum[j],
5520 reload_when_needed[j]);
5522 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5523 /* We may have to make a REG_DEAD note for the secondary reload
5524 register in the insns we just made. Find the last insn that
5525 mentioned the register. */
5526 if (! special && second_reload_reg
5527 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5531 for (prev = get_last_insn (); prev;
5532 prev = PREV_INSN (prev))
5533 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5534 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5537 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5546 /* End this sequence. */
5547 *where = get_insns ();
5551 /* Add a note saying the input reload reg
5552 dies in this insn, if anyone cares. */
5553 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5555 && reload_reg_rtx[j] != old
5556 && reload_reg_rtx[j] != 0
5557 && reload_out[j] == 0
5558 && ! reload_inherited[j]
5559 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5561 register rtx reloadreg = reload_reg_rtx[j];
5564 /* We can't abort here because we need to support this for sched.c.
5565 It's not terrible to miss a REG_DEAD note, but we should try
5566 to figure out how to do this correctly. */
5567 /* The code below is incorrect for address-only reloads. */
5568 if (reload_when_needed[j] != RELOAD_OTHER
5569 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5573 /* Add a death note to this insn, for an input reload. */
5575 if ((reload_when_needed[j] == RELOAD_OTHER
5576 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5577 && ! dead_or_set_p (insn, reloadreg))
5579 = gen_rtx (EXPR_LIST, REG_DEAD,
5580 reloadreg, REG_NOTES (insn));
5583 /* When we inherit a reload, the last marked death of the reload reg
5584 may no longer really be a death. */
5585 if (reload_reg_rtx[j] != 0
5586 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5587 && reload_inherited[j])
5589 /* Handle inheriting an output reload.
5590 Remove the death note from the output reload insn. */
5591 if (reload_spill_index[j] >= 0
5592 && GET_CODE (reload_in[j]) == REG
5593 && spill_reg_store[reload_spill_index[j]] != 0
5594 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5595 REG_DEAD, REGNO (reload_reg_rtx[j])))
5596 remove_death (REGNO (reload_reg_rtx[j]),
5597 spill_reg_store[reload_spill_index[j]]);
5598 /* Likewise for input reloads that were inherited. */
5599 else if (reload_spill_index[j] >= 0
5600 && GET_CODE (reload_in[j]) == REG
5601 && spill_reg_store[reload_spill_index[j]] == 0
5602 && reload_inheritance_insn[j] != 0
5603 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5604 REGNO (reload_reg_rtx[j])))
5605 remove_death (REGNO (reload_reg_rtx[j]),
5606 reload_inheritance_insn[j]);
5611 /* We got this register from find_equiv_reg.
5612 Search back for its last death note and get rid of it.
5613 But don't search back too far.
5614 Don't go past a place where this reg is set,
5615 since a death note before that remains valid. */
5616 for (prev = PREV_INSN (insn);
5617 prev && GET_CODE (prev) != CODE_LABEL;
5618 prev = PREV_INSN (prev))
5619 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5620 && dead_or_set_p (prev, reload_reg_rtx[j]))
5622 if (find_regno_note (prev, REG_DEAD,
5623 REGNO (reload_reg_rtx[j])))
5624 remove_death (REGNO (reload_reg_rtx[j]), prev);
5630 /* We might have used find_equiv_reg above to choose an alternate
5631 place from which to reload. If so, and it died, we need to remove
5632 that death and move it to one of the insns we just made. */
5634 if (oldequiv_reg != 0
5635 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5639 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5640 prev = PREV_INSN (prev))
5641 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5642 && dead_or_set_p (prev, oldequiv_reg))
5644 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5646 for (prev1 = this_reload_insn;
5647 prev1; prev1 = PREV_INSN (prev1))
5648 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5649 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5652 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5657 remove_death (REGNO (oldequiv_reg), prev);
5664 /* If we are reloading a register that was recently stored in with an
5665 output-reload, see if we can prove there was
5666 actually no need to store the old value in it. */
5668 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5669 && reload_in[j] != 0
5670 && GET_CODE (reload_in[j]) == REG
5672 /* There doesn't seem to be any reason to restrict this to pseudos
5673 and doing so loses in the case where we are copying from a
5674 register of the wrong class. */
5675 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5677 && spill_reg_store[reload_spill_index[j]] != 0
5678 /* This is unsafe if some other reload uses the same reg first. */
5679 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
5680 reload_opnum[j], reload_when_needed[j])
5681 && dead_or_set_p (insn, reload_in[j])
5682 /* This is unsafe if operand occurs more than once in current
5683 insn. Perhaps some occurrences weren't reloaded. */
5684 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5685 delete_output_reload (insn, j,
5686 spill_reg_store[reload_spill_index[j]]);
5688 /* Input-reloading is done. Now do output-reloading,
5689 storing the value from the reload-register after the main insn
5690 if reload_out[j] is nonzero.
5692 ??? At some point we need to support handling output reloads of
5693 JUMP_INSNs or insns that set cc0. */
5694 old = reload_out[j];
5696 && reload_reg_rtx[j] != old
5697 && reload_reg_rtx[j] != 0)
5699 register rtx reloadreg = reload_reg_rtx[j];
5700 register rtx second_reloadreg = 0;
5702 enum machine_mode mode;
5705 /* An output operand that dies right away does need a reload,
5706 but need not be copied from it. Show the new location in the
5708 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5709 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5711 XEXP (note, 0) = reload_reg_rtx[j];
5714 else if (GET_CODE (old) == SCRATCH)
5715 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5716 but we don't want to make an output reload. */
5720 /* Strip off of OLD any size-increasing SUBREGs such as
5721 (SUBREG:SI foo:QI 0). */
5723 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5724 && (GET_MODE_SIZE (GET_MODE (old))
5725 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5726 old = SUBREG_REG (old);
5729 /* If is a JUMP_INSN, we can't support output reloads yet. */
5730 if (GET_CODE (insn) == JUMP_INSN)
5733 push_to_sequence (output_reload_insns[reload_opnum[j]]);
5735 /* Determine the mode to reload in.
5736 See comments above (for input reloading). */
5738 mode = GET_MODE (old);
5739 if (mode == VOIDmode)
5741 /* VOIDmode should never happen for an output. */
5742 if (asm_noperands (PATTERN (insn)) < 0)
5743 /* It's the compiler's fault. */
5745 error_for_asm (insn, "output operand is constant in `asm'");
5746 /* Prevent crash--use something we know is valid. */
5748 old = gen_rtx (REG, mode, REGNO (reloadreg));
5751 if (GET_MODE (reloadreg) != mode)
5752 reloadreg = gen_lowpart_common (mode, reloadreg);
5754 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5756 /* If we need two reload regs, set RELOADREG to the intermediate
5757 one, since it will be stored into OUT. We might need a secondary
5758 register only for an input reload, so check again here. */
5760 if (reload_secondary_reload[j] >= 0)
5764 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5765 && reg_equiv_mem[REGNO (old)] != 0)
5766 real_old = reg_equiv_mem[REGNO (old)];
5768 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5772 second_reloadreg = reloadreg;
5773 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
5775 /* See if RELOADREG is to be used as a scratch register
5776 or as an intermediate register. */
5777 if (reload_secondary_icode[j] != CODE_FOR_nothing)
5779 emit_insn ((GEN_FCN (reload_secondary_icode[j])
5780 (real_old, second_reloadreg, reloadreg)));
5785 /* See if we need both a scratch and intermediate reload
5787 int secondary_reload = reload_secondary_reload[j];
5788 enum insn_code tertiary_icode
5789 = reload_secondary_icode[secondary_reload];
5792 if (GET_MODE (reloadreg) != mode)
5793 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5795 if (tertiary_icode != CODE_FOR_nothing)
5798 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5799 pat = (GEN_FCN (tertiary_icode)
5800 (reloadreg, second_reloadreg, third_reloadreg));
5802 #ifdef SECONDARY_MEMORY_NEEDED
5803 /* If we need a memory location to do the move, do it that way. */
5804 else if (GET_CODE (reloadreg) == REG
5805 && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
5806 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
5807 REGNO_REG_CLASS (REGNO (second_reloadreg)),
5808 GET_MODE (second_reloadreg)))
5810 /* Get the memory to use and rewrite both registers
5813 = get_secondary_mem (reloadreg,
5814 GET_MODE (second_reloadreg),
5816 reload_when_needed[j]);
5819 if (GET_MODE (loc) != GET_MODE (second_reloadreg))
5820 second_reloadreg = gen_rtx (REG, GET_MODE (loc),
5821 REGNO (second_reloadreg));
5823 if (GET_MODE (loc) != GET_MODE (reloadreg))
5824 tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
5827 tmp_reloadreg = reloadreg;
5829 emit_move_insn (loc, second_reloadreg);
5830 pat = gen_move_insn (tmp_reloadreg, loc);
5834 pat = gen_move_insn (reloadreg, second_reloadreg);
5842 /* Output the last reload insn. */
5845 #ifdef SECONDARY_MEMORY_NEEDED
5846 /* If we need a memory location to do the move, do it that way. */
5847 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
5848 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
5849 REGNO_REG_CLASS (REGNO (reloadreg)),
5850 GET_MODE (reloadreg)))
5852 /* Get the memory to use and rewrite both registers to
5854 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg),
5856 reload_when_needed[j]);
5858 if (GET_MODE (loc) != GET_MODE (reloadreg))
5859 reloadreg = gen_rtx (REG, GET_MODE (loc),
5862 if (GET_MODE (loc) != GET_MODE (old))
5863 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
5865 emit_insn (gen_move_insn (loc, reloadreg));
5866 emit_insn (gen_move_insn (old, loc));
5870 emit_insn (gen_move_insn (old, reloadreg));
5873 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5874 /* If final will look at death notes for this reg,
5875 put one on the last output-reload insn to use it. Similarly
5876 for any secondary register. */
5877 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5878 for (p = get_last_insn (); p; p = PREV_INSN (p))
5879 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5880 && reg_overlap_mentioned_for_reload_p (reloadreg,
5882 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5883 reloadreg, REG_NOTES (p));
5885 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5887 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5888 for (p = get_last_insn (); p; p = PREV_INSN (p))
5889 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5890 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
5892 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5893 second_reloadreg, REG_NOTES (p));
5896 /* Look at all insns we emitted, just to be safe. */
5897 for (p = get_insns (); p; p = NEXT_INSN (p))
5898 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5900 /* If this output reload doesn't come from a spill reg,
5901 clear any memory of reloaded copies of the pseudo reg.
5902 If this output reload comes from a spill reg,
5903 reg_has_output_reload will make this do nothing. */
5904 note_stores (PATTERN (p), forget_old_reloads_1);
5906 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5910 output_reload_insns[reload_opnum[j]] = get_insns ();
5915 if (reload_spill_index[j] >= 0)
5916 new_spill_reg_store[reload_spill_index[j]] = store_insn;
5919 /* Now write all the insns we made for reloads in the order expected by
5920 the allocation functions. Prior to the insn being reloaded, we write
5921 the following reloads:
5923 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
5925 RELOAD_OTHER reloads.
5927 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
5928 the RELOAD_FOR_INPUT reload for the operand.
5930 RELOAD_FOR_OPERAND_ADDRESS reloads.
5932 After the insn being reloaded, we write the following:
5934 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
5935 the RELOAD_FOR_OUTPUT reload for that operand. */
5937 emit_insns_before (other_input_address_reload_insns, before_insn);
5938 emit_insns_before (other_input_reload_insns, before_insn);
5940 for (j = 0; j < reload_n_operands; j++)
5942 emit_insns_before (input_address_reload_insns[j], before_insn);
5943 emit_insns_before (input_reload_insns[j], before_insn);
5946 emit_insns_before (operand_reload_insns, before_insn);
5948 for (j = 0; j < reload_n_operands; j++)
5950 emit_insns_before (output_address_reload_insns[j], following_insn);
5951 emit_insns_before (output_reload_insns[j], following_insn);
5954 /* Move death notes from INSN
5955 to output-operand-address and output reload insns. */
5956 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5959 /* Loop over those insns, last ones first. */
5960 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
5961 insn1 = PREV_INSN (insn1))
5962 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
5964 rtx source = SET_SRC (PATTERN (insn1));
5965 rtx dest = SET_DEST (PATTERN (insn1));
5967 /* The note we will examine next. */
5968 rtx reg_notes = REG_NOTES (insn);
5969 /* The place that pointed to this note. */
5970 rtx *prev_reg_note = ®_NOTES (insn);
5972 /* If the note is for something used in the source of this
5973 reload insn, or in the output address, move the note. */
5976 rtx next_reg_notes = XEXP (reg_notes, 1);
5977 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
5978 && GET_CODE (XEXP (reg_notes, 0)) == REG
5979 && ((GET_CODE (dest) != REG
5980 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5982 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5985 *prev_reg_note = next_reg_notes;
5986 XEXP (reg_notes, 1) = REG_NOTES (insn1);
5987 REG_NOTES (insn1) = reg_notes;
5990 prev_reg_note = &XEXP (reg_notes, 1);
5992 reg_notes = next_reg_notes;
5998 /* For all the spill regs newly reloaded in this instruction,
5999 record what they were reloaded from, so subsequent instructions
6000 can inherit the reloads.
6002 Update spill_reg_store for the reloads of this insn.
6003 Copy the elements that were updated in the loop above. */
6005 for (j = 0; j < n_reloads; j++)
6007 register int r = reload_order[j];
6008 register int i = reload_spill_index[r];
6010 /* I is nonneg if this reload used one of the spill regs.
6011 If reload_reg_rtx[r] is 0, this is an optional reload
6012 that we opted to ignore.
6014 Also ignore reloads that don't reach the end of the insn,
6015 since we will eventually see the one that does. */
6017 if (i >= 0 && reload_reg_rtx[r] != 0
6018 && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6019 reload_when_needed[r]))
6021 /* First, clear out memory of what used to be in this spill reg.
6022 If consecutive registers are used, clear them all. */
6024 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6027 for (k = 0; k < nr; k++)
6029 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6030 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6033 /* Maybe the spill reg contains a copy of reload_out. */
6034 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6036 register int nregno = REGNO (reload_out[r]);
6037 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6038 : HARD_REGNO_NREGS (nregno,
6039 GET_MODE (reload_reg_rtx[r])));
6041 spill_reg_store[i] = new_spill_reg_store[i];
6042 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6044 /* If NREGNO is a hard register, it may occupy more than
6045 one register. If it does, say what is in the
6046 rest of the registers assuming that both registers
6047 agree on how many words the object takes. If not,
6048 invalidate the subsequent registers. */
6050 if (nregno < FIRST_PSEUDO_REGISTER)
6051 for (k = 1; k < nnr; k++)
6052 reg_last_reload_reg[nregno + k]
6053 = (nr == nnr ? gen_rtx (REG, word_mode,
6054 REGNO (reload_reg_rtx[r]) + k)
6057 /* Now do the inverse operation. */
6058 for (k = 0; k < nr; k++)
6060 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6061 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6063 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6067 /* Maybe the spill reg contains a copy of reload_in. */
6068 else if (reload_out[r] == 0
6069 && reload_in[r] != 0
6070 && (GET_CODE (reload_in[r]) == REG
6071 || GET_CODE (reload_in_reg[r]) == REG))
6073 register int nregno;
6076 if (GET_CODE (reload_in[r]) == REG)
6077 nregno = REGNO (reload_in[r]);
6079 nregno = REGNO (reload_in_reg[r]);
6081 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6082 : HARD_REGNO_NREGS (nregno,
6083 GET_MODE (reload_reg_rtx[r])));
6085 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6087 if (nregno < FIRST_PSEUDO_REGISTER)
6088 for (k = 1; k < nnr; k++)
6089 reg_last_reload_reg[nregno + k]
6090 = (nr == nnr ? gen_rtx (REG, word_mode,
6091 REGNO (reload_reg_rtx[r]) + k)
6094 /* Unless we inherited this reload, show we haven't
6095 recently done a store. */
6096 if (! reload_inherited[r])
6097 spill_reg_store[i] = 0;
6099 for (k = 0; k < nr; k++)
6101 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6102 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6104 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6110 /* The following if-statement was #if 0'd in 1.34 (or before...).
6111 It's reenabled in 1.35 because supposedly nothing else
6112 deals with this problem. */
6114 /* If a register gets output-reloaded from a non-spill register,
6115 that invalidates any previous reloaded copy of it.
6116 But forget_old_reloads_1 won't get to see it, because
6117 it thinks only about the original insn. So invalidate it here. */
6118 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6120 register int nregno = REGNO (reload_out[r]);
6121 reg_last_reload_reg[nregno] = 0;
6126 /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6127 operand OPNUM with reload type TYPE.
6129 Returns first insn emitted. */
6132 gen_input_reload (reloadreg, in, opnum, type)
6136 enum reload_type type;
6138 rtx last = get_last_insn ();
6140 /* How to do this reload can get quite tricky. Normally, we are being
6141 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6142 register that didn't get a hard register. In that case we can just
6143 call emit_move_insn.
6145 We can also be asked to reload a PLUS that adds either two registers, or
6146 a register and a constant or MEM, or a MEM and a constant. This can
6147 occur during frame pointer elimination and while reloading addresses.
6148 This case is handled by trying to emit a single insn
6149 to perform the add. If it is not valid, we use a two insn sequence.
6151 Finally, we could be called to handle an 'o' constraint by putting
6152 an address into a register. In that case, we first try to do this
6153 with a named pattern of "reload_load_address". If no such pattern
6154 exists, we just emit a SET insn and hope for the best (it will normally
6155 be valid on machines that use 'o').
6157 This entire process is made complex because reload will never
6158 process the insns we generate here and so we must ensure that
6159 they will fit their constraints and also by the fact that parts of
6160 IN might be being reloaded separately and replaced with spill registers.
6161 Because of this, we are, in some sense, just guessing the right approach
6162 here. The one listed above seems to work.
6164 ??? At some point, this whole thing needs to be rethought. */
6166 if (GET_CODE (in) == PLUS
6167 && ((GET_CODE (XEXP (in, 0)) == REG
6168 && (GET_CODE (XEXP (in, 1)) == REG
6169 || CONSTANT_P (XEXP (in, 1))
6170 || GET_CODE (XEXP (in, 1)) == MEM))
6171 || (GET_CODE (XEXP (in, 0)) == MEM
6172 && CONSTANT_P (XEXP (in, 1)))))
6174 /* We need to compute the sum of what is either a register and a
6175 constant, a register and memory, a hard register and a pseudo
6176 register, or memory and a constant and put it into the reload
6177 register. The best possible way of doing this is if the machine
6178 has a three-operand ADD insn that accepts the required operands.
6180 The simplest approach is to try to generate such an insn and see if it
6181 is recognized and matches its constraints. If so, it can be used.
6183 It might be better not to actually emit the insn unless it is valid,
6184 but we need to pass the insn as an operand to `recog' and
6185 `insn_extract' and it is simpler to emit and then delete the insn if
6186 not valid than to dummy things up. */
6188 rtx op0, op1, tem, insn;
6191 op0 = find_replacement (&XEXP (in, 0));
6192 op1 = find_replacement (&XEXP (in, 1));
6194 /* Since constraint checking is strict, commutativity won't be
6195 checked, so we need to do that here to avoid spurious failure
6196 if the add instruction is two-address and the second operand
6197 of the add is the same as the reload reg, which is frequently
6198 the case. If the insn would be A = B + A, rearrange it so
6199 it will be A = A + B as constrain_operands expects. */
6201 if (GET_CODE (XEXP (in, 1)) == REG
6202 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
6203 tem = op0, op0 = op1, op1 = tem;
6205 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6206 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6208 insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6209 code = recog_memoized (insn);
6213 insn_extract (insn);
6214 /* We want constrain operands to treat this insn strictly in
6215 its validity determination, i.e., the way it would after reload
6217 if (constrain_operands (code, 1))
6221 delete_insns_since (last);
6223 /* If that failed, we must use a conservative two-insn sequence.
6224 use move to copy constant, MEM, or pseudo register to the reload
6225 register since "move" will be able to handle an arbitrary operand,
6226 unlike add which can't, in general. Then add the registers.
6228 If there is another way to do this for a specific machine, a
6229 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6232 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6233 || (GET_CODE (op1) == REG
6234 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6235 tem = op0, op0 = op1, op1 = tem;
6237 emit_insn (gen_move_insn (reloadreg, op0));
6239 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6240 This fixes a problem on the 32K where the stack pointer cannot
6241 be used as an operand of an add insn. */
6243 if (rtx_equal_p (op0, op1))
6246 emit_insn (gen_add2_insn (reloadreg, op1));
6249 #ifdef SECONDARY_MEMORY_NEEDED
6250 /* If we need a memory location to do the move, do it that way. */
6251 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6252 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6253 REGNO_REG_CLASS (REGNO (reloadreg)),
6254 GET_MODE (reloadreg)))
6256 /* Get the memory to use and rewrite both registers to its mode. */
6257 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type);
6259 if (GET_MODE (loc) != GET_MODE (reloadreg))
6260 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
6262 if (GET_MODE (loc) != GET_MODE (in))
6263 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6265 emit_insn (gen_move_insn (loc, in));
6266 emit_insn (gen_move_insn (reloadreg, loc));
6270 /* If IN is a simple operand, use gen_move_insn. */
6271 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6272 emit_insn (gen_move_insn (reloadreg, in));
6274 #ifdef HAVE_reload_load_address
6275 else if (HAVE_reload_load_address)
6276 emit_insn (gen_reload_load_address (reloadreg, in));
6279 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6281 emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6283 /* Return the first insn emitted.
6284 We can not just return get_last_insn, because there may have
6285 been multiple instructions emitted. Also note that gen_move_insn may
6286 emit more than one insn itself, so we can not assume that there is one
6287 insn emitted per emit_insn_before call. */
6289 return last ? NEXT_INSN (last) : get_insns ();
6292 /* Delete a previously made output-reload
6293 whose result we now believe is not needed.
6294 First we double-check.
6296 INSN is the insn now being processed.
6297 OUTPUT_RELOAD_INSN is the insn of the output reload.
6298 J is the reload-number for this insn. */
6301 delete_output_reload (insn, j, output_reload_insn)
6304 rtx output_reload_insn;
6308 /* Get the raw pseudo-register referred to. */
6310 rtx reg = reload_in[j];
6311 while (GET_CODE (reg) == SUBREG)
6312 reg = SUBREG_REG (reg);
6314 /* If the pseudo-reg we are reloading is no longer referenced
6315 anywhere between the store into it and here,
6316 and no jumps or labels intervene, then the value can get
6317 here through the reload reg alone.
6318 Otherwise, give up--return. */
6319 for (i1 = NEXT_INSN (output_reload_insn);
6320 i1 != insn; i1 = NEXT_INSN (i1))
6322 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6324 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6325 && reg_mentioned_p (reg, PATTERN (i1)))
6329 /* If this insn will store in the pseudo again,
6330 the previous store can be removed. */
6331 if (reload_out[j] == reload_in[j])
6332 delete_insn (output_reload_insn);
6334 /* See if the pseudo reg has been completely replaced
6335 with reload regs. If so, delete the store insn
6336 and forget we had a stack slot for the pseudo. */
6337 else if (reg_n_deaths[REGNO (reg)] == 1
6338 && reg_basic_block[REGNO (reg)] >= 0
6339 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6343 /* We know that it was used only between here
6344 and the beginning of the current basic block.
6345 (We also know that the last use before INSN was
6346 the output reload we are thinking of deleting, but never mind that.)
6347 Search that range; see if any ref remains. */
6348 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6350 rtx set = single_set (i2);
6352 /* Uses which just store in the pseudo don't count,
6353 since if they are the only uses, they are dead. */
6354 if (set != 0 && SET_DEST (set) == reg)
6356 if (GET_CODE (i2) == CODE_LABEL
6357 || GET_CODE (i2) == JUMP_INSN)
6359 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6360 && reg_mentioned_p (reg, PATTERN (i2)))
6361 /* Some other ref remains;
6362 we can't do anything. */
6366 /* Delete the now-dead stores into this pseudo. */
6367 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6369 rtx set = single_set (i2);
6371 if (set != 0 && SET_DEST (set) == reg)
6373 if (GET_CODE (i2) == CODE_LABEL
6374 || GET_CODE (i2) == JUMP_INSN)
6378 /* For the debugging info,
6379 say the pseudo lives in this reload reg. */
6380 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6381 alter_reg (REGNO (reg), -1);
6385 /* Output reload-insns to reload VALUE into RELOADREG.
6386 VALUE is an autoincrement or autodecrement RTX whose operand
6387 is a register or memory location;
6388 so reloading involves incrementing that location.
6390 INC_AMOUNT is the number to increment or decrement by (always positive).
6391 This cannot be deduced from VALUE. */
6394 inc_for_reload (reloadreg, value, inc_amount)
6399 /* REG or MEM to be copied and incremented. */
6400 rtx incloc = XEXP (value, 0);
6401 /* Nonzero if increment after copying. */
6402 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
6408 /* No hard register is equivalent to this register after
6409 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6410 we could inc/dec that register as well (maybe even using it for
6411 the source), but I'm not sure it's worth worrying about. */
6412 if (GET_CODE (incloc) == REG)
6413 reg_last_reload_reg[REGNO (incloc)] = 0;
6415 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6416 inc_amount = - inc_amount;
6418 inc = GEN_INT (inc_amount);
6420 /* If this is post-increment, first copy the location to the reload reg. */
6422 emit_insn (gen_move_insn (reloadreg, incloc));
6424 /* See if we can directly increment INCLOC. Use a method similar to that
6425 in gen_input_reload. */
6427 last = get_last_insn ();
6428 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
6429 gen_rtx (PLUS, GET_MODE (incloc),
6432 code = recog_memoized (add_insn);
6435 insn_extract (add_insn);
6436 if (constrain_operands (code, 1))
6438 /* If this is a pre-increment and we have incremented the value
6439 where it lives, copy the incremented value to RELOADREG to
6440 be used as an address. */
6443 emit_insn (gen_move_insn (reloadreg, incloc));
6449 delete_insns_since (last);
6451 /* If couldn't do the increment directly, must increment in RELOADREG.
6452 The way we do this depends on whether this is pre- or post-increment.
6453 For pre-increment, copy INCLOC to the reload register, increment it
6454 there, then save back. */
6458 emit_insn (gen_move_insn (reloadreg, incloc));
6459 emit_insn (gen_add2_insn (reloadreg, inc));
6460 emit_insn (gen_move_insn (incloc, reloadreg));
6465 Because this might be a jump insn or a compare, and because RELOADREG
6466 may not be available after the insn in an input reload, we must do
6467 the incrementation before the insn being reloaded for.
6469 We have already copied INCLOC to RELOADREG. Increment the copy in
6470 RELOADREG, save that back, then decrement RELOADREG so it has
6471 the original value. */
6473 emit_insn (gen_add2_insn (reloadreg, inc));
6474 emit_insn (gen_move_insn (incloc, reloadreg));
6475 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
6481 /* Return 1 if we are certain that the constraint-string STRING allows
6482 the hard register REG. Return 0 if we can't be sure of this. */
6485 constraint_accepts_reg_p (string, reg)
6490 int regno = true_regnum (reg);
6493 /* Initialize for first alternative. */
6495 /* Check that each alternative contains `g' or `r'. */
6497 switch (c = *string++)
6500 /* If an alternative lacks `g' or `r', we lose. */
6503 /* If an alternative lacks `g' or `r', we lose. */
6506 /* Initialize for next alternative. */
6511 /* Any general reg wins for this alternative. */
6512 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
6516 /* Any reg in specified class wins for this alternative. */
6518 enum reg_class class = REG_CLASS_FROM_LETTER (c);
6520 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
6526 /* Return the number of places FIND appears within X, but don't count
6527 an occurrence if some SET_DEST is FIND. */
6530 count_occurrences (x, find)
6531 register rtx x, find;
6534 register enum rtx_code code;
6535 register char *format_ptr;
6543 code = GET_CODE (x);
6558 if (SET_DEST (x) == find)
6559 return count_occurrences (SET_SRC (x), find);
6563 format_ptr = GET_RTX_FORMAT (code);
6566 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6568 switch (*format_ptr++)
6571 count += count_occurrences (XEXP (x, i), find);
6575 if (XVEC (x, i) != NULL)
6577 for (j = 0; j < XVECLEN (x, i); j++)
6578 count += count_occurrences (XVECEXP (x, i, j), find);
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