1 /* Search an insn for pseudo regs that must be in hard regs and are not.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This file contains subroutines used only from the file reload1.c.
22 It knows how to scan one insn for operands and values
23 that need to be copied into registers to make valid code.
24 It also finds other operands and values which are valid
25 but for which equivalent values in registers exist and
26 ought to be used instead.
28 Before processing the first insn of the function, call `init_reload'.
30 To scan an insn, call `find_reloads'. This does two things:
31 1. sets up tables describing which values must be reloaded
32 for this insn, and what kind of hard regs they must be reloaded into;
33 2. optionally record the locations where those values appear in
34 the data, so they can be replaced properly later.
35 This is done only if the second arg to `find_reloads' is nonzero.
37 The third arg to `find_reloads' specifies the number of levels
38 of indirect addressing supported by the machine. If it is zero,
39 indirect addressing is not valid. If it is one, (MEM (REG n))
40 is valid even if (REG n) did not get a hard register; if it is two,
41 (MEM (MEM (REG n))) is also valid even if (REG n) did not get a
42 hard register, and similarly for higher values.
44 Then you must choose the hard regs to reload those pseudo regs into,
45 and generate appropriate load insns before this insn and perhaps
46 also store insns after this insn. Set up the array `reload_reg_rtx'
47 to contain the REG rtx's for the registers you used. In some
48 cases `find_reloads' will return a nonzero value in `reload_reg_rtx'
49 for certain reloads. Then that tells you which register to use,
50 so you do not need to allocate one. But you still do need to add extra
51 instructions to copy the value into and out of that register.
53 Finally you must call `subst_reloads' to substitute the reload reg rtx's
54 into the locations already recorded.
58 find_reloads can alter the operands of the instruction it is called on.
60 1. Two operands of any sort may be interchanged, if they are in a
61 commutative instruction.
62 This happens only if find_reloads thinks the instruction will compile
65 2. Pseudo-registers that are equivalent to constants are replaced
66 with those constants if they are not in hard registers.
68 1 happens every time find_reloads is called.
69 2 happens only when REPLACE is 1, which is only when
70 actually doing the reloads, not when just counting them.
73 Using a reload register for several reloads in one insn:
75 When an insn has reloads, it is considered as having three parts:
76 the input reloads, the insn itself after reloading, and the output reloads.
77 Reloads of values used in memory addresses are often needed for only one part.
79 When this is so, reload_when_needed records which part needs the reload.
80 Two reloads for different parts of the insn can share the same reload
83 When a reload is used for addresses in multiple parts, or when it is
84 an ordinary operand, it is classified as RELOAD_OTHER, and cannot share
85 a register with any other reload. */
91 #include "insn-config.h"
92 #include "insn-codes.h"
96 #include "hard-reg-set.h"
100 #ifndef REGISTER_MOVE_COST
101 #define REGISTER_MOVE_COST(x, y) 2
104 /* The variables set up by `find_reloads' are:
106 n_reloads number of distinct reloads needed; max reload # + 1
107 tables indexed by reload number
108 reload_in rtx for value to reload from
109 reload_out rtx for where to store reload-reg afterward if nec
110 (often the same as reload_in)
111 reload_reg_class enum reg_class, saying what regs to reload into
112 reload_inmode enum machine_mode; mode this operand should have
113 when reloaded, on input.
114 reload_outmode enum machine_mode; mode this operand should have
115 when reloaded, on output.
116 reload_strict_low char; currently always zero; used to mean that this
117 reload is inside a STRICT_LOW_PART, but we don't
118 need to know this anymore.
119 reload_optional char, nonzero for an optional reload.
120 Optional reloads are ignored unless the
121 value is already sitting in a register.
122 reload_inc int, positive amount to increment or decrement by if
123 reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC.
124 Ignored otherwise (don't assume it is zero).
125 reload_in_reg rtx. A reg for which reload_in is the equivalent.
126 If reload_in is a symbol_ref which came from
127 reg_equiv_constant, then this is the pseudo
128 which has that symbol_ref as equivalent.
129 reload_reg_rtx rtx. This is the register to reload into.
130 If it is zero when `find_reloads' returns,
131 you must find a suitable register in the class
132 specified by reload_reg_class, and store here
133 an rtx for that register with mode from
134 reload_inmode or reload_outmode.
135 reload_nocombine char, nonzero if this reload shouldn't be
136 combined with another reload.
137 reload_needed_for rtx, operand this reload is needed for address of.
138 0 means it isn't needed for addressing.
139 reload_needed_for_multiple
140 int, 1 if this reload needed for more than one thing.
141 reload_when_needed enum, classifies reload as needed either for
142 addressing an input reload, addressing an output,
143 for addressing a non-reloaded mem ref,
144 or for unspecified purposes (i.e., more than one
146 reload_secondary_reload int, gives the reload number of a secondary
147 reload, when needed; otherwise -1
148 reload_secondary_p int, 1 if this is a secondary register for one
150 reload_secondary_icode enum insn_code, if a secondary reload is required,
151 gives the INSN_CODE that uses the secondary
152 reload as a scratch register, or CODE_FOR_nothing
153 if the secondary reload register is to be an
154 intermediate register. */
157 rtx reload_in[MAX_RELOADS];
158 rtx reload_out[MAX_RELOADS];
159 enum reg_class reload_reg_class[MAX_RELOADS];
160 enum machine_mode reload_inmode[MAX_RELOADS];
161 enum machine_mode reload_outmode[MAX_RELOADS];
162 char reload_strict_low[MAX_RELOADS];
163 rtx reload_reg_rtx[MAX_RELOADS];
164 char reload_optional[MAX_RELOADS];
165 int reload_inc[MAX_RELOADS];
166 rtx reload_in_reg[MAX_RELOADS];
167 char reload_nocombine[MAX_RELOADS];
168 int reload_needed_for_multiple[MAX_RELOADS];
169 rtx reload_needed_for[MAX_RELOADS];
170 enum reload_when_needed reload_when_needed[MAX_RELOADS];
171 int reload_secondary_reload[MAX_RELOADS];
172 int reload_secondary_p[MAX_RELOADS];
173 enum insn_code reload_secondary_icode[MAX_RELOADS];
175 /* All the "earlyclobber" operands of the current insn
176 are recorded here. */
178 rtx reload_earlyclobbers[MAX_RECOG_OPERANDS];
180 /* Replacing reloads.
182 If `replace_reloads' is nonzero, then as each reload is recorded
183 an entry is made for it in the table `replacements'.
184 Then later `subst_reloads' can look through that table and
185 perform all the replacements needed. */
187 /* Nonzero means record the places to replace. */
188 static int replace_reloads;
190 /* Each replacement is recorded with a structure like this. */
193 rtx *where; /* Location to store in */
194 rtx *subreg_loc; /* Location of SUBREG if WHERE is inside
195 a SUBREG; 0 otherwise. */
196 int what; /* which reload this is for */
197 enum machine_mode mode; /* mode it must have */
200 static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
202 /* Number of replacements currently recorded. */
203 static int n_replacements;
205 /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable;
206 (see reg_equiv_address). */
207 static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
208 static int n_memlocs;
210 /* The instruction we are doing reloads for;
211 so we can test whether a register dies in it. */
212 static rtx this_insn;
214 /* Nonzero if this instruction is a user-specified asm with operands. */
215 static int this_insn_is_asm;
217 /* If hard_regs_live_known is nonzero,
218 we can tell which hard regs are currently live,
219 at least enough to succeed in choosing dummy reloads. */
220 static int hard_regs_live_known;
222 /* Indexed by hard reg number,
223 element is nonegative if hard reg has been spilled.
224 This vector is passed to `find_reloads' as an argument
225 and is not changed here. */
226 static short *static_reload_reg_p;
228 /* Set to 1 in subst_reg_equivs if it changes anything. */
229 static int subst_reg_equivs_changed;
231 /* On return from push_reload, holds the reload-number for the OUT
232 operand, which can be different for that from the input operand. */
233 static int output_reloadnum;
235 static int alternative_allows_memconst ();
236 static rtx find_dummy_reload ();
237 static rtx find_reloads_toplev ();
238 static int find_reloads_address ();
239 static int find_reloads_address_1 ();
240 static void find_reloads_address_part ();
241 static int hard_reg_set_here_p ();
242 /* static rtx forget_volatility (); */
243 static rtx subst_reg_equivs ();
244 static rtx subst_indexed_address ();
245 rtx find_equiv_reg ();
246 static int find_inc_amount ();
248 #ifdef HAVE_SECONDARY_RELOADS
250 /* Determine if any secondary reloads are needed for loading (if IN_P is
251 non-zero) or storing (if IN_P is zero) X to or from a reload register of
252 register class RELOAD_CLASS in mode RELOAD_MODE.
254 Return the register class of a secondary reload register, or NO_REGS if
255 none. *PMODE is set to the mode that the register is required in.
256 If the reload register is needed as a scratch register instead of an
257 intermediate register, *PICODE is set to the insn_code of the insn to be
258 used to load or store the primary reload register; otherwise *PICODE
259 is set to CODE_FOR_nothing.
261 In some cases (such as storing MQ into an external memory location on
262 the RT), both an intermediate register and a scratch register. In that
263 case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate
264 register is returned, and the *PTERTIARY_... variables are set to describe
265 the scratch register. */
267 static enum reg_class
268 find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode,
269 ptertiary_class, ptertiary_icode, ptertiary_mode)
271 enum reg_class reload_class;
272 enum machine_mode reload_mode;
274 enum insn_code *picode;
275 enum machine_mode *pmode;
276 enum reg_class *ptertiary_class;
277 enum insn_code *ptertiary_icode;
278 enum machine_mode *ptertiary_mode;
280 enum reg_class class = NO_REGS;
281 enum machine_mode mode = reload_mode;
282 enum insn_code icode = CODE_FOR_nothing;
283 enum reg_class t_class = NO_REGS;
284 enum machine_mode t_mode = VOIDmode;
285 enum insn_code t_icode = CODE_FOR_nothing;
287 /* If X is a pseudo-register that has an equivalent MEM (actually, if it
288 is still a pseudo-register by now, it *must* have an equivalent MEM
289 but we don't want to assume that), use that equivalent when seeing if
290 a secondary reload is needed since whether or not a reload is needed
291 might be sensitive to the form of the MEM. */
293 if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
294 && reg_equiv_mem[REGNO (x)] != 0)
295 x = reg_equiv_mem[REGNO (x)];
297 #ifdef SECONDARY_INPUT_RELOAD_CLASS
299 class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x);
302 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
304 class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x);
307 /* If we don't need any secondary registers, go away; the rest of the
308 values won't be used. */
309 if (class == NO_REGS)
312 /* Get a possible insn to use. If the predicate doesn't accept X, don't
315 icode = (in_p ? reload_in_optab[(int) reload_mode]
316 : reload_out_optab[(int) reload_mode]);
318 if (icode != CODE_FOR_nothing
319 && insn_operand_predicate[(int) icode][in_p]
320 && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode)))
321 icode = CODE_FOR_nothing;
323 /* If we will be using an insn, see if it can directly handle the reload
324 register we will be using. If it can, the secondary reload is for a
325 scratch register. If it can't, we will use the secondary reload for
326 an intermediate register and require a tertiary reload for the scratch
329 if (icode != CODE_FOR_nothing)
331 /* If IN_P is non-zero, the reload register will be the output in
332 operand 0. If IN_P is zero, the reload register will be the input
333 in operand 1. Outputs should have an initial "=", which we must
336 char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p];
337 enum reg_class insn_class
338 = (insn_letter == 'r' ? GENERAL_REGS
339 : REG_CLASS_FROM_LETTER (insn_letter));
341 if (insn_class == NO_REGS
342 || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=')
343 /* The scratch register's constraint must start with "=&". */
344 || insn_operand_constraint[(int) icode][2][0] != '='
345 || insn_operand_constraint[(int) icode][2][1] != '&')
348 if (reg_class_subset_p (reload_class, insn_class))
349 mode = insn_operand_mode[(int) icode][2];
352 char t_letter = insn_operand_constraint[(int) icode][2][2];
354 t_mode = insn_operand_mode[(int) icode][2];
355 t_class = (t_letter == 'r' ? GENERAL_REGS
356 : REG_CLASS_FROM_LETTER (t_letter));
358 icode = CODE_FOR_nothing;
364 *ptertiary_class = t_class;
365 *ptertiary_mode = t_mode;
366 *ptertiary_icode = t_icode;
370 #endif /* HAVE_SECONDARY_RELOADS */
372 /* Record one (sometimes two) reload that needs to be performed.
373 IN is an rtx saying where the data are to be found before this instruction.
374 OUT says where they must be stored after the instruction.
375 (IN is zero for data not read, and OUT is zero for data not written.)
376 INLOC and OUTLOC point to the places in the instructions where
377 IN and OUT were found.
378 CLASS is a register class required for the reloaded data.
379 INMODE is the machine mode that the instruction requires
380 for the reg that replaces IN and OUTMODE is likewise for OUT.
382 If IN is zero, then OUT's location and mode should be passed as
385 STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx.
387 OPTIONAL nonzero means this reload does not need to be performed:
388 it can be discarded if that is more convenient.
390 The return value is the reload-number for this reload.
392 If both IN and OUT are nonzero, in some rare cases we might
393 want to make two separate reloads. (Actually we never do this now.)
394 Therefore, the reload-number for OUT is stored in
395 output_reloadnum when we return; the return value applies to IN.
396 Usually (presently always), when IN and OUT are nonzero,
397 the two reload-numbers are equal, but the caller should be careful to
401 push_reload (in, out, inloc, outloc, class,
402 inmode, outmode, strict_low, optional, needed_for)
403 register rtx in, out;
405 enum reg_class class;
406 enum machine_mode inmode, outmode;
413 rtx *in_subreg_loc = 0, *out_subreg_loc = 0;
414 int secondary_reload = -1;
415 enum insn_code secondary_icode = CODE_FOR_nothing;
417 /* Compare two RTX's. */
418 #define MATCHES(x, y) \
419 (x == y || (x != 0 && (GET_CODE (x) == REG \
420 ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \
421 : rtx_equal_p (x, y) && ! side_effects_p (x))))
423 /* INMODE and/or OUTMODE could be VOIDmode if no mode
424 has been specified for the operand. In that case,
425 use the operand's mode as the mode to reload. */
426 if (inmode == VOIDmode && in != 0)
427 inmode = GET_MODE (in);
428 if (outmode == VOIDmode && out != 0)
429 outmode = GET_MODE (out);
431 /* If IN is a pseudo register everywhere-equivalent to a constant, and
432 it is not in a hard register, reload straight from the constant,
433 since we want to get rid of such pseudo registers.
434 Often this is done earlier, but not always in find_reloads_address. */
435 if (in != 0 && GET_CODE (in) == REG)
437 register int regno = REGNO (in);
439 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
440 && reg_equiv_constant[regno] != 0)
441 in = reg_equiv_constant[regno];
444 /* Likewise for OUT. Of course, OUT will never be equivalent to
445 an actual constant, but it might be equivalent to a memory location
446 (in the case of a parameter). */
447 if (out != 0 && GET_CODE (out) == REG)
449 register int regno = REGNO (out);
451 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
452 && reg_equiv_constant[regno] != 0)
453 out = reg_equiv_constant[regno];
456 /* If we have a read-write operand with an address side-effect,
457 change either IN or OUT so the side-effect happens only once. */
458 if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out))
460 if (GET_CODE (XEXP (in, 0)) == POST_INC
461 || GET_CODE (XEXP (in, 0)) == POST_DEC)
462 in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0));
463 if (GET_CODE (XEXP (in, 0)) == PRE_INC
464 || GET_CODE (XEXP (in, 0)) == PRE_DEC)
465 out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0));
468 /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...),
469 really reload just the inside expression in its own mode.
470 If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the
471 register is a pseudo, this will become the same as the above case.
472 Do the same for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
473 either M1 is not valid for R or M2 is wider than a word but we only
474 need one word to store an M2-sized quantity in R.
475 Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere;
476 we can't handle it here because CONST_INT does not indicate a mode.
478 Similarly, we must reload the inside expression if we have a
479 STRICT_LOW_PART (presumably, in == out in the cas).
481 Also reload the inner expression if it does not require a secondary
482 reload but the SUBREG does. */
484 if (in != 0 && GET_CODE (in) == SUBREG
485 && (GET_CODE (SUBREG_REG (in)) != REG
487 || (GET_CODE (SUBREG_REG (in)) == REG
488 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER
489 && (GET_MODE_SIZE (inmode)
490 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))))
491 || (GET_CODE (SUBREG_REG (in)) == REG
492 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
493 && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode)
494 || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
495 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
497 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
499 != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)),
500 GET_MODE (SUBREG_REG (in)))))))
501 #ifdef SECONDARY_INPUT_RELOAD_CLASS
502 || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS
503 && (SECONDARY_INPUT_RELOAD_CLASS (class,
504 GET_MODE (SUBREG_REG (in)),
510 in_subreg_loc = inloc;
511 inloc = &SUBREG_REG (in);
513 if (GET_CODE (in) == MEM)
514 /* This is supposed to happen only for paradoxical subregs made by
515 combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
516 if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode))
518 inmode = GET_MODE (in);
521 /* Similarly for paradoxical and problematical SUBREGs on the output.
522 Note that there is no reason we need worry about the previous value
523 of SUBREG_REG (out); even if wider than out,
524 storing in a subreg is entitled to clobber it all
525 (except in the case of STRICT_LOW_PART,
526 and in that case the constraint should label it input-output.) */
527 if (out != 0 && GET_CODE (out) == SUBREG
528 && (GET_CODE (SUBREG_REG (out)) != REG
530 || (GET_CODE (SUBREG_REG (out)) == REG
531 && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER
532 && (GET_MODE_SIZE (outmode)
533 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))))
534 || (GET_CODE (SUBREG_REG (out)) == REG
535 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
536 && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode)
537 || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
538 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
540 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
542 != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)),
543 GET_MODE (SUBREG_REG (out)))))))
544 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
545 || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS
546 && (SECONDARY_OUTPUT_RELOAD_CLASS (class,
547 GET_MODE (SUBREG_REG (out)),
553 out_subreg_loc = outloc;
554 outloc = &SUBREG_REG (out);
556 if (GET_CODE (out) == MEM
557 && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
559 outmode = GET_MODE (out);
562 /* That's all we use STRICT_LOW for, so clear it. At some point,
563 we may want to get rid of reload_strict_low. */
566 /* If IN appears in OUT, we can't share any input-only reload for IN. */
567 if (in != 0 && out != 0 && GET_CODE (out) == MEM
568 && (GET_CODE (in) == REG || GET_CODE (in) == MEM)
569 && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0)))
572 /* Narrow down the class of register wanted if that is
573 desirable on this machine for efficiency. */
575 class = PREFERRED_RELOAD_CLASS (in, class);
577 /* Make sure we use a class that can handle the actual pseudo
578 inside any subreg. For example, on the 386, QImode regs
579 can appear within SImode subregs. Although GENERAL_REGS
580 can handle SImode, QImode needs a smaller class. */
581 #ifdef LIMIT_RELOAD_CLASS
583 class = LIMIT_RELOAD_CLASS (inmode, class);
584 else if (in != 0 && GET_CODE (in) == SUBREG)
585 class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class);
588 class = LIMIT_RELOAD_CLASS (outmode, class);
589 if (out != 0 && GET_CODE (out) == SUBREG)
590 class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class);
593 if (class == NO_REGS)
596 /* Verify that this class is at least possible for the mode that
598 if (this_insn_is_asm)
600 enum machine_mode mode;
601 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
605 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
606 if (HARD_REGNO_MODE_OK (i, mode)
607 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i))
609 int nregs = HARD_REGNO_NREGS (i, mode);
612 for (j = 1; j < nregs; j++)
613 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j))
618 if (i == FIRST_PSEUDO_REGISTER)
620 error_for_asm (this_insn, "impossible register constraint in `asm'");
625 /* We can use an existing reload if the class is right
626 and at least one of IN and OUT is a match
627 and the other is at worst neutral.
628 (A zero compared against anything is neutral.) */
629 for (i = 0; i < n_reloads; i++)
630 if ((reg_class_subset_p (class, reload_reg_class[i])
631 || reg_class_subset_p (reload_reg_class[i], class))
632 && reload_strict_low[i] == strict_low
633 /* If the existing reload has a register, it must fit our class. */
634 && (reload_reg_rtx[i] == 0
635 || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
636 true_regnum (reload_reg_rtx[i])))
637 && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share
638 && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out)))
640 (out != 0 && MATCHES (reload_out[i], out)
641 && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))))
644 /* Reloading a plain reg for input can match a reload to postincrement
645 that reg, since the postincrement's value is the right value.
646 Likewise, it can match a preincrement reload, since we regard
647 the preincrementation as happening before any ref in this insn
650 for (i = 0; i < n_reloads; i++)
651 if ((reg_class_subset_p (class, reload_reg_class[i])
652 || reg_class_subset_p (reload_reg_class[i], class))
653 /* If the existing reload has a register, it must fit our class. */
654 && (reload_reg_rtx[i] == 0
655 || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
656 true_regnum (reload_reg_rtx[i])))
657 && reload_strict_low[i] == strict_low
658 && out == 0 && reload_out[i] == 0 && reload_in[i] != 0
659 && ((GET_CODE (in) == REG
660 && (GET_CODE (reload_in[i]) == POST_INC
661 || GET_CODE (reload_in[i]) == POST_DEC
662 || GET_CODE (reload_in[i]) == PRE_INC
663 || GET_CODE (reload_in[i]) == PRE_DEC)
664 && MATCHES (XEXP (reload_in[i], 0), in))
666 (GET_CODE (reload_in[i]) == REG
667 && (GET_CODE (in) == POST_INC
668 || GET_CODE (in) == POST_DEC
669 || GET_CODE (in) == PRE_INC
670 || GET_CODE (in) == PRE_DEC)
671 && MATCHES (XEXP (in, 0), reload_in[i]))))
673 /* Make sure reload_in ultimately has the increment,
674 not the plain register. */
675 if (GET_CODE (in) == REG)
682 #ifdef HAVE_SECONDARY_RELOADS
683 enum reg_class secondary_class = NO_REGS;
684 enum reg_class secondary_out_class = NO_REGS;
685 enum machine_mode secondary_mode = inmode;
686 enum machine_mode secondary_out_mode = outmode;
687 enum insn_code secondary_icode;
688 enum insn_code secondary_out_icode = CODE_FOR_nothing;
689 enum reg_class tertiary_class = NO_REGS;
690 enum reg_class tertiary_out_class = NO_REGS;
691 enum machine_mode tertiary_mode;
692 enum machine_mode tertiary_out_mode;
693 enum insn_code tertiary_icode;
694 enum insn_code tertiary_out_icode = CODE_FOR_nothing;
695 int tertiary_reload = -1;
697 /* See if we need a secondary reload register to move between
698 CLASS and IN or CLASS and OUT. Get the modes and icodes to
699 use for each of them if so. */
701 #ifdef SECONDARY_INPUT_RELOAD_CLASS
704 = find_secondary_reload (in, class, inmode, 1, &secondary_icode,
705 &secondary_mode, &tertiary_class,
706 &tertiary_icode, &tertiary_mode);
709 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
710 if (out != 0 && GET_CODE (out) != SCRATCH)
712 = find_secondary_reload (out, class, outmode, 0,
713 &secondary_out_icode, &secondary_out_mode,
714 &tertiary_out_class, &tertiary_out_icode,
718 /* We can only record one secondary and one tertiary reload. If both
719 IN and OUT need secondary reloads, we can only make an in-out
720 reload if neither need an insn and if the classes are compatible. */
722 if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
723 && reg_class_subset_p (secondary_out_class, secondary_class))
724 secondary_class = secondary_out_class;
726 if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
727 && (! reg_class_subset_p (secondary_class, secondary_out_class)
728 || secondary_icode != CODE_FOR_nothing
729 || secondary_out_icode != CODE_FOR_nothing))
731 push_reload (NULL_RTX, out, NULL_PTR, outloc, class,
732 VOIDmode, outmode, strict_low, optional, needed_for);
738 /* If we need a secondary reload for OUT but not IN, copy the
740 if (secondary_class == NO_REGS && secondary_out_class != NO_REGS)
742 secondary_class = secondary_out_class;
743 secondary_icode = secondary_out_icode;
744 tertiary_class = tertiary_out_class;
745 tertiary_icode = tertiary_out_icode;
746 tertiary_mode = tertiary_out_mode;
749 if (secondary_class != NO_REGS)
751 /* If we need a tertiary reload, see if we have one we can reuse
754 if (tertiary_class != NO_REGS)
756 for (tertiary_reload = 0; tertiary_reload < n_reloads;
758 if (reload_secondary_p[tertiary_reload]
759 && (reg_class_subset_p (tertiary_class,
760 reload_reg_class[tertiary_reload])
761 || reg_class_subset_p (reload_reg_class[tertiary_reload],
763 && ((reload_inmode[tertiary_reload] == tertiary_mode)
764 || reload_inmode[tertiary_reload] == VOIDmode)
765 && ((reload_outmode[tertiary_reload] == tertiary_mode)
766 || reload_outmode[tertiary_reload] == VOIDmode)
767 && (reload_secondary_icode[tertiary_reload]
768 == CODE_FOR_nothing))
771 if (tertiary_mode != VOIDmode)
772 reload_inmode[tertiary_reload] = tertiary_mode;
773 if (tertiary_out_mode != VOIDmode)
774 reload_outmode[tertiary_reload] = tertiary_mode;
775 if (reg_class_subset_p (tertiary_class,
776 reload_reg_class[tertiary_reload]))
777 reload_reg_class[tertiary_reload] = tertiary_class;
778 if (reload_needed_for[tertiary_reload] != needed_for)
779 reload_needed_for_multiple[tertiary_reload] = 1;
780 reload_optional[tertiary_reload] &= optional;
781 reload_secondary_p[tertiary_reload] = 1;
784 if (tertiary_reload == n_reloads)
786 /* We need to make a new tertiary reload for this register
788 reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0;
789 reload_reg_class[tertiary_reload] = tertiary_class;
790 reload_inmode[tertiary_reload] = tertiary_mode;
791 reload_outmode[tertiary_reload] = tertiary_mode;
792 reload_reg_rtx[tertiary_reload] = 0;
793 reload_optional[tertiary_reload] = optional;
794 reload_inc[tertiary_reload] = 0;
795 reload_strict_low[tertiary_reload] = 0;
796 /* Maybe we could combine these, but it seems too tricky. */
797 reload_nocombine[tertiary_reload] = 1;
798 reload_in_reg[tertiary_reload] = 0;
799 reload_needed_for[tertiary_reload] = needed_for;
800 reload_needed_for_multiple[tertiary_reload] = 0;
801 reload_secondary_reload[tertiary_reload] = -1;
802 reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing;
803 reload_secondary_p[tertiary_reload] = 1;
810 /* See if we can reuse an existing secondary reload. */
811 for (secondary_reload = 0; secondary_reload < n_reloads;
813 if (reload_secondary_p[secondary_reload]
814 && (reg_class_subset_p (secondary_class,
815 reload_reg_class[secondary_reload])
816 || reg_class_subset_p (reload_reg_class[secondary_reload],
818 && ((reload_inmode[secondary_reload] == secondary_mode)
819 || reload_inmode[secondary_reload] == VOIDmode)
820 && ((reload_outmode[secondary_reload] == secondary_out_mode)
821 || reload_outmode[secondary_reload] == VOIDmode)
822 && reload_secondary_reload[secondary_reload] == tertiary_reload
823 && reload_secondary_icode[secondary_reload] == tertiary_icode)
825 if (secondary_mode != VOIDmode)
826 reload_inmode[secondary_reload] = secondary_mode;
827 if (secondary_out_mode != VOIDmode)
828 reload_outmode[secondary_reload] = secondary_out_mode;
829 if (reg_class_subset_p (secondary_class,
830 reload_reg_class[secondary_reload]))
831 reload_reg_class[secondary_reload] = secondary_class;
832 if (reload_needed_for[secondary_reload] != needed_for)
833 reload_needed_for_multiple[secondary_reload] = 1;
834 reload_optional[secondary_reload] &= optional;
835 reload_secondary_p[secondary_reload] = 1;
838 if (secondary_reload == n_reloads)
840 /* We need to make a new secondary reload for this register
842 reload_in[secondary_reload] = reload_out[secondary_reload] = 0;
843 reload_reg_class[secondary_reload] = secondary_class;
844 reload_inmode[secondary_reload] = secondary_mode;
845 reload_outmode[secondary_reload] = secondary_out_mode;
846 reload_reg_rtx[secondary_reload] = 0;
847 reload_optional[secondary_reload] = optional;
848 reload_inc[secondary_reload] = 0;
849 reload_strict_low[secondary_reload] = 0;
850 /* Maybe we could combine these, but it seems too tricky. */
851 reload_nocombine[secondary_reload] = 1;
852 reload_in_reg[secondary_reload] = 0;
853 reload_needed_for[secondary_reload] = needed_for;
854 reload_needed_for_multiple[secondary_reload] = 0;
855 reload_secondary_reload[secondary_reload] = tertiary_reload;
856 reload_secondary_icode[secondary_reload] = tertiary_icode;
857 reload_secondary_p[secondary_reload] = 1;
865 /* We found no existing reload suitable for re-use.
866 So add an additional reload. */
870 reload_reg_class[i] = class;
871 reload_inmode[i] = inmode;
872 reload_outmode[i] = outmode;
873 reload_reg_rtx[i] = 0;
874 reload_optional[i] = optional;
876 reload_strict_low[i] = strict_low;
877 reload_nocombine[i] = 0;
878 reload_in_reg[i] = inloc ? *inloc : 0;
879 reload_needed_for[i] = needed_for;
880 reload_needed_for_multiple[i] = 0;
881 reload_secondary_reload[i] = secondary_reload;
882 reload_secondary_icode[i] = secondary_icode;
883 reload_secondary_p[i] = 0;
889 /* We are reusing an existing reload,
890 but we may have additional information for it.
891 For example, we may now have both IN and OUT
892 while the old one may have just one of them. */
894 if (inmode != VOIDmode)
895 reload_inmode[i] = inmode;
896 if (outmode != VOIDmode)
897 reload_outmode[i] = outmode;
902 if (reg_class_subset_p (class, reload_reg_class[i]))
903 reload_reg_class[i] = class;
904 reload_optional[i] &= optional;
905 if (reload_needed_for[i] != needed_for)
906 reload_needed_for_multiple[i] = 1;
909 /* If the ostensible rtx being reload differs from the rtx found
910 in the location to substitute, this reload is not safe to combine
911 because we cannot reliably tell whether it appears in the insn. */
913 if (in != 0 && in != *inloc)
914 reload_nocombine[i] = 1;
917 /* This was replaced by changes in find_reloads_address_1 and the new
918 function inc_for_reload, which go with a new meaning of reload_inc. */
920 /* If this is an IN/OUT reload in an insn that sets the CC,
921 it must be for an autoincrement. It doesn't work to store
922 the incremented value after the insn because that would clobber the CC.
923 So we must do the increment of the value reloaded from,
924 increment it, store it back, then decrement again. */
925 if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
929 reload_inc[i] = find_inc_amount (PATTERN (this_insn), in);
930 /* If we did not find a nonzero amount-to-increment-by,
931 that contradicts the belief that IN is being incremented
932 in an address in this insn. */
933 if (reload_inc[i] == 0)
938 /* If we will replace IN and OUT with the reload-reg,
939 record where they are located so that substitution need
940 not do a tree walk. */
946 register struct replacement *r = &replacements[n_replacements++];
948 r->subreg_loc = in_subreg_loc;
952 if (outloc != 0 && outloc != inloc)
954 register struct replacement *r = &replacements[n_replacements++];
957 r->subreg_loc = out_subreg_loc;
962 /* If this reload is just being introduced and it has both
963 an incoming quantity and an outgoing quantity that are
964 supposed to be made to match, see if either one of the two
965 can serve as the place to reload into.
967 If one of them is acceptable, set reload_reg_rtx[i]
970 if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0)
972 reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc,
973 reload_reg_class[i], i);
975 /* If the outgoing register already contains the same value
976 as the incoming one, we can dispense with loading it.
977 The easiest way to tell the caller that is to give a phony
978 value for the incoming operand (same as outgoing one). */
979 if (reload_reg_rtx[i] == out
980 && (GET_CODE (in) == REG || CONSTANT_P (in))
981 && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out),
982 static_reload_reg_p, i, inmode))
986 /* If this is an input reload and the operand contains a register that
987 dies in this insn and is used nowhere else, see if it is the right class
988 to be used for this reload. Use it if so. (This occurs most commonly
989 in the case of paradoxical SUBREGs and in-out reloads). We cannot do
990 this if it is also an output reload that mentions the register unless
991 the output is a SUBREG that clobbers an entire register.
993 Note that the operand might be one of the spill regs, if it is a
994 pseudo reg and we are in a block where spilling has not taken place.
995 But if there is no spilling in this block, that is OK.
996 An explicitly used hard reg cannot be a spill reg. */
998 if (reload_reg_rtx[i] == 0 && in != 0)
1003 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1004 if (REG_NOTE_KIND (note) == REG_DEAD
1005 && GET_CODE (XEXP (note, 0)) == REG
1006 && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
1007 && reg_mentioned_p (XEXP (note, 0), in)
1008 && ! refers_to_regno_for_reload_p (regno,
1010 + HARD_REGNO_NREGS (regno,
1012 PATTERN (this_insn), inloc)
1014 || (GET_CODE (in) == SUBREG
1015 && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
1017 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1018 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
1019 /* Make sure the operand fits in the reg that dies. */
1020 && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
1021 && HARD_REGNO_MODE_OK (regno, inmode)
1022 && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
1023 && HARD_REGNO_MODE_OK (regno, outmode)
1024 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1025 && !fixed_regs[regno])
1027 reload_reg_rtx[i] = gen_rtx (REG, inmode, regno);
1033 output_reloadnum = i;
1038 /* Record an additional place we must replace a value
1039 for which we have already recorded a reload.
1040 RELOADNUM is the value returned by push_reload
1041 when the reload was recorded.
1042 This is used in insn patterns that use match_dup. */
1045 push_replacement (loc, reloadnum, mode)
1048 enum machine_mode mode;
1050 if (replace_reloads)
1052 register struct replacement *r = &replacements[n_replacements++];
1053 r->what = reloadnum;
1060 /* If there is only one output reload, and it is not for an earlyclobber
1061 operand, try to combine it with a (logically unrelated) input reload
1062 to reduce the number of reload registers needed.
1064 This is safe if the input reload does not appear in
1065 the value being output-reloaded, because this implies
1066 it is not needed any more once the original insn completes.
1068 If that doesn't work, see we can use any of the registers that
1069 die in this insn as a reload register. We can if it is of the right
1070 class and does not appear in the value being output-reloaded. */
1076 int output_reload = -1;
1079 /* Find the output reload; return unless there is exactly one
1080 and that one is mandatory. */
1082 for (i = 0; i < n_reloads; i++)
1083 if (reload_out[i] != 0)
1085 if (output_reload >= 0)
1090 if (output_reload < 0 || reload_optional[output_reload])
1093 /* An input-output reload isn't combinable. */
1095 if (reload_in[output_reload] != 0)
1098 /* If this reload is for an earlyclobber operand, we can't do anything. */
1100 for (i = 0; i < n_earlyclobbers; i++)
1101 if (reload_out[output_reload] == reload_earlyclobbers[i])
1104 /* Check each input reload; can we combine it? */
1106 for (i = 0; i < n_reloads; i++)
1107 if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i]
1108 /* Life span of this reload must not extend past main insn. */
1109 && reload_when_needed[i] != RELOAD_FOR_OUTPUT_RELOAD_ADDRESS
1110 && reload_inmode[i] == reload_outmode[output_reload]
1111 && reload_inc[i] == 0
1112 && reload_reg_rtx[i] == 0
1113 && reload_strict_low[i] == 0
1114 /* Don't combine two reloads with different secondary reloads. */
1115 && (reload_secondary_reload[i] == reload_secondary_reload[output_reload]
1116 || reload_secondary_reload[i] == -1
1117 || reload_secondary_reload[output_reload] == -1)
1118 && (reg_class_subset_p (reload_reg_class[i],
1119 reload_reg_class[output_reload])
1120 || reg_class_subset_p (reload_reg_class[output_reload],
1121 reload_reg_class[i]))
1122 && (MATCHES (reload_in[i], reload_out[output_reload])
1123 /* Args reversed because the first arg seems to be
1124 the one that we imagine being modified
1125 while the second is the one that might be affected. */
1126 || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload],
1128 /* However, if the input is a register that appears inside
1129 the output, then we also can't share.
1130 Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1131 If the same reload reg is used for both reg 69 and the
1132 result to be stored in memory, then that result
1133 will clobber the address of the memory ref. */
1134 && ! (GET_CODE (reload_in[i]) == REG
1135 && reg_overlap_mentioned_for_reload_p (reload_in[i],
1136 reload_out[output_reload])))))
1140 /* We have found a reload to combine with! */
1141 reload_out[i] = reload_out[output_reload];
1142 reload_outmode[i] = reload_outmode[output_reload];
1143 /* Mark the old output reload as inoperative. */
1144 reload_out[output_reload] = 0;
1145 /* The combined reload is needed for the entire insn. */
1146 reload_needed_for_multiple[i] = 1;
1147 reload_when_needed[i] = RELOAD_OTHER;
1148 /* If the output reload had a secondary reload, copy it. */
1149 if (reload_secondary_reload[output_reload] != -1)
1150 reload_secondary_reload[i] = reload_secondary_reload[output_reload];
1151 /* If required, minimize the register class. */
1152 if (reg_class_subset_p (reload_reg_class[output_reload],
1153 reload_reg_class[i]))
1154 reload_reg_class[i] = reload_reg_class[output_reload];
1156 /* Transfer all replacements from the old reload to the combined. */
1157 for (j = 0; j < n_replacements; j++)
1158 if (replacements[j].what == output_reload)
1159 replacements[j].what = i;
1164 /* If this insn has only one operand that is modified or written (assumed
1165 to be the first), it must be the one corresponding to this reload. It
1166 is safe to use anything that dies in this insn for that output provided
1167 that it does not occur in the output (we already know it isn't an
1168 earlyclobber. If this is an asm insn, give up. */
1170 if (INSN_CODE (this_insn) == -1)
1173 for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++)
1174 if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '='
1175 || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+')
1178 /* See if some hard register that dies in this insn and is not used in
1179 the output is the right class. Only works if the register we pick
1180 up can fully hold our output reload. */
1181 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1182 if (REG_NOTE_KIND (note) == REG_DEAD
1183 && GET_CODE (XEXP (note, 0)) == REG
1184 && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
1185 reload_out[output_reload])
1186 && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1187 && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1188 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]],
1189 REGNO (XEXP (note, 0)))
1190 && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1191 <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
1192 && ! fixed_regs[REGNO (XEXP (note, 0))])
1194 reload_reg_rtx[output_reload] = gen_rtx (REG,
1195 reload_outmode[output_reload],
1196 REGNO (XEXP (note, 0)));
1201 /* Try to find a reload register for an in-out reload (expressions IN and OUT).
1202 See if one of IN and OUT is a register that may be used;
1203 this is desirable since a spill-register won't be needed.
1204 If so, return the register rtx that proves acceptable.
1206 INLOC and OUTLOC are locations where IN and OUT appear in the insn.
1207 CLASS is the register class required for the reload.
1209 If FOR_REAL is >= 0, it is the number of the reload,
1210 and in some cases when it can be discovered that OUT doesn't need
1211 to be computed, clear out reload_out[FOR_REAL].
1213 If FOR_REAL is -1, this should not be done, because this call
1214 is just to see if a register can be found, not to find and install it. */
1217 find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real)
1218 rtx real_in, real_out;
1219 rtx *inloc, *outloc;
1220 enum reg_class class;
1229 /* If operands exceed a word, we can't use either of them
1230 unless they have the same size. */
1231 if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in))
1232 && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD
1233 || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD))
1236 /* Find the inside of any subregs. */
1237 while (GET_CODE (out) == SUBREG)
1239 out_offset = SUBREG_WORD (out);
1240 out = SUBREG_REG (out);
1242 while (GET_CODE (in) == SUBREG)
1244 in_offset = SUBREG_WORD (in);
1245 in = SUBREG_REG (in);
1248 /* Narrow down the reg class, the same way push_reload will;
1249 otherwise we might find a dummy now, but push_reload won't. */
1250 class = PREFERRED_RELOAD_CLASS (in, class);
1252 /* See if OUT will do. */
1253 if (GET_CODE (out) == REG
1254 && REGNO (out) < FIRST_PSEUDO_REGISTER)
1256 register int regno = REGNO (out) + out_offset;
1257 int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out));
1259 /* When we consider whether the insn uses OUT,
1260 ignore references within IN. They don't prevent us
1261 from copying IN into OUT, because those refs would
1262 move into the insn that reloads IN.
1264 However, we only ignore IN in its role as this reload.
1265 If the insn uses IN elsewhere and it contains OUT,
1266 that counts. We can't be sure it's the "same" operand
1267 so it might not go through this reload. */
1268 *inloc = const0_rtx;
1270 if (regno < FIRST_PSEUDO_REGISTER
1271 /* A fixed reg that can overlap other regs better not be used
1272 for reloading in any way. */
1273 #ifdef OVERLAPPING_REGNO_P
1274 && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno))
1276 && ! refers_to_regno_for_reload_p (regno, regno + nwords,
1277 PATTERN (this_insn), outloc))
1280 for (i = 0; i < nwords; i++)
1281 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1287 if (GET_CODE (real_out) == REG)
1290 value = gen_rtx (REG, GET_MODE (real_out), regno);
1297 /* Consider using IN if OUT was not acceptable
1298 or if OUT dies in this insn (like the quotient in a divmod insn).
1299 We can't use IN unless it is dies in this insn,
1300 which means we must know accurately which hard regs are live.
1301 Also, the result can't go in IN if IN is used within OUT. */
1302 if (hard_regs_live_known
1303 && GET_CODE (in) == REG
1304 && REGNO (in) < FIRST_PSEUDO_REGISTER
1306 || find_reg_note (this_insn, REG_UNUSED, real_out))
1307 && find_reg_note (this_insn, REG_DEAD, real_in)
1308 && !fixed_regs[REGNO (in)]
1309 && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out)))
1311 register int regno = REGNO (in) + in_offset;
1312 int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in));
1314 if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR)
1315 && ! hard_reg_set_here_p (regno, regno + nwords,
1316 PATTERN (this_insn)))
1319 for (i = 0; i < nwords; i++)
1320 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1326 /* If we were going to use OUT as the reload reg
1327 and changed our mind, it means OUT is a dummy that
1328 dies here. So don't bother copying value to it. */
1329 if (for_real >= 0 && value == real_out)
1330 reload_out[for_real] = 0;
1331 if (GET_CODE (real_in) == REG)
1334 value = gen_rtx (REG, GET_MODE (real_in), regno);
1342 /* This page contains subroutines used mainly for determining
1343 whether the IN or an OUT of a reload can serve as the
1346 /* Return 1 if expression X alters a hard reg in the range
1347 from BEG_REGNO (inclusive) to END_REGNO (exclusive),
1348 either explicitly or in the guise of a pseudo-reg allocated to REGNO.
1349 X should be the body of an instruction. */
1352 hard_reg_set_here_p (beg_regno, end_regno, x)
1353 register int beg_regno, end_regno;
1356 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1358 register rtx op0 = SET_DEST (x);
1359 while (GET_CODE (op0) == SUBREG)
1360 op0 = SUBREG_REG (op0);
1361 if (GET_CODE (op0) == REG)
1363 register int r = REGNO (op0);
1364 /* See if this reg overlaps range under consideration. */
1366 && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno)
1370 else if (GET_CODE (x) == PARALLEL)
1372 register int i = XVECLEN (x, 0) - 1;
1374 if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i)))
1381 /* Return 1 if ADDR is a valid memory address for mode MODE,
1382 and check that each pseudo reg has the proper kind of
1386 strict_memory_address_p (mode, addr)
1387 enum machine_mode mode;
1390 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1398 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
1399 if they are the same hard reg, and has special hacks for
1400 autoincrement and autodecrement.
1401 This is specifically intended for find_reloads to use
1402 in determining whether two operands match.
1403 X is the operand whose number is the lower of the two.
1405 The value is 2 if Y contains a pre-increment that matches
1406 a non-incrementing address in X. */
1408 /* ??? To be completely correct, we should arrange to pass
1409 for X the output operand and for Y the input operand.
1410 For now, we assume that the output operand has the lower number
1411 because that is natural in (SET output (... input ...)). */
1414 operands_match_p (x, y)
1418 register RTX_CODE code = GET_CODE (x);
1424 if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
1425 && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
1426 && GET_CODE (SUBREG_REG (y)) == REG)))
1432 i = REGNO (SUBREG_REG (x));
1433 if (i >= FIRST_PSEUDO_REGISTER)
1435 i += SUBREG_WORD (x);
1440 if (GET_CODE (y) == SUBREG)
1442 j = REGNO (SUBREG_REG (y));
1443 if (j >= FIRST_PSEUDO_REGISTER)
1445 j += SUBREG_WORD (y);
1452 /* If two operands must match, because they are really a single
1453 operand of an assembler insn, then two postincrements are invalid
1454 because the assembler insn would increment only once.
1455 On the other hand, an postincrement matches ordinary indexing
1456 if the postincrement is the output operand. */
1457 if (code == POST_DEC || code == POST_INC)
1458 return operands_match_p (XEXP (x, 0), y);
1459 /* Two preincrements are invalid
1460 because the assembler insn would increment only once.
1461 On the other hand, an preincrement matches ordinary indexing
1462 if the preincrement is the input operand.
1463 In this case, return 2, since some callers need to do special
1464 things when this happens. */
1465 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC)
1466 return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
1470 /* Now we have disposed of all the cases
1471 in which different rtx codes can match. */
1472 if (code != GET_CODE (y))
1474 if (code == LABEL_REF)
1475 return XEXP (x, 0) == XEXP (y, 0);
1476 if (code == SYMBOL_REF)
1477 return XSTR (x, 0) == XSTR (y, 0);
1479 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
1481 if (GET_MODE (x) != GET_MODE (y))
1484 /* Compare the elements. If any pair of corresponding elements
1485 fail to match, return 0 for the whole things. */
1488 fmt = GET_RTX_FORMAT (code);
1489 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1495 if (XWINT (x, i) != XWINT (y, i))
1500 if (XINT (x, i) != XINT (y, i))
1505 val = operands_match_p (XEXP (x, i), XEXP (y, i));
1508 /* If any subexpression returns 2,
1509 we should return 2 if we are successful. */
1517 /* It is believed that rtx's at this level will never
1518 contain anything but integers and other rtx's,
1519 except for within LABEL_REFs and SYMBOL_REFs. */
1524 return 1 + success_2;
1527 /* Return the number of times character C occurs in string S. */
1530 n_occurrences (c, s)
1540 struct decomposition
1545 HOST_WIDE_INT start;
1549 /* Describe the range of registers or memory referenced by X.
1550 If X is a register, set REG_FLAG and put the first register
1551 number into START and the last plus one into END.
1552 If X is a memory reference, put a base address into BASE
1553 and a range of integer offsets into START and END.
1554 If X is pushing on the stack, we can assume it causes no trouble,
1555 so we set the SAFE field. */
1557 static struct decomposition
1561 struct decomposition val;
1566 if (GET_CODE (x) == MEM)
1568 rtx base, offset = 0;
1569 rtx addr = XEXP (x, 0);
1571 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
1572 || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
1574 val.base = XEXP (addr, 0);
1575 val.start = - GET_MODE_SIZE (GET_MODE (x));
1576 val.end = GET_MODE_SIZE (GET_MODE (x));
1577 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
1581 if (GET_CODE (addr) == CONST)
1583 addr = XEXP (addr, 0);
1586 if (GET_CODE (addr) == PLUS)
1588 if (CONSTANT_P (XEXP (addr, 0)))
1590 base = XEXP (addr, 1);
1591 offset = XEXP (addr, 0);
1593 else if (CONSTANT_P (XEXP (addr, 1)))
1595 base = XEXP (addr, 0);
1596 offset = XEXP (addr, 1);
1603 offset = const0_rtx;
1605 if (GET_CODE (offset) == CONST)
1606 offset = XEXP (offset, 0);
1607 if (GET_CODE (offset) == PLUS)
1609 if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
1611 base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1));
1612 offset = XEXP (offset, 0);
1614 else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
1616 base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0));
1617 offset = XEXP (offset, 1);
1621 base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1622 offset = const0_rtx;
1625 else if (GET_CODE (offset) != CONST_INT)
1627 base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1628 offset = const0_rtx;
1631 if (all_const && GET_CODE (base) == PLUS)
1632 base = gen_rtx (CONST, GET_MODE (base), base);
1634 if (GET_CODE (offset) != CONST_INT)
1637 val.start = INTVAL (offset);
1638 val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
1642 else if (GET_CODE (x) == REG)
1645 val.start = true_regnum (x);
1648 /* A pseudo with no hard reg. */
1649 val.start = REGNO (x);
1650 val.end = val.start + 1;
1654 val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1656 else if (GET_CODE (x) == SUBREG)
1658 if (GET_CODE (SUBREG_REG (x)) != REG)
1659 /* This could be more precise, but it's good enough. */
1660 return decompose (SUBREG_REG (x));
1662 val.start = true_regnum (x);
1664 return decompose (SUBREG_REG (x));
1667 val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1669 else if (CONSTANT_P (x)
1670 /* This hasn't been assigned yet, so it can't conflict yet. */
1671 || GET_CODE (x) == SCRATCH)
1678 /* Return 1 if altering Y will not modify the value of X.
1679 Y is also described by YDATA, which should be decompose (Y). */
1682 immune_p (x, y, ydata)
1684 struct decomposition ydata;
1686 struct decomposition xdata;
1689 return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR);
1693 if (GET_CODE (y) != MEM)
1695 /* If Y is memory and X is not, Y can't affect X. */
1696 if (GET_CODE (x) != MEM)
1699 xdata = decompose (x);
1701 if (! rtx_equal_p (xdata.base, ydata.base))
1703 /* If bases are distinct symbolic constants, there is no overlap. */
1704 if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))
1706 /* Constants and stack slots never overlap. */
1707 if (CONSTANT_P (xdata.base)
1708 && (ydata.base == frame_pointer_rtx
1709 || ydata.base == stack_pointer_rtx))
1711 if (CONSTANT_P (ydata.base)
1712 && (xdata.base == frame_pointer_rtx
1713 || xdata.base == stack_pointer_rtx))
1715 /* If either base is variable, we don't know anything. */
1720 return (xdata.start >= ydata.end || ydata.start >= xdata.end);
1723 /* Similar, but calls decompose. */
1726 safe_from_earlyclobber (op, clobber)
1729 struct decomposition early_data;
1731 early_data = decompose (clobber);
1732 return immune_p (op, clobber, early_data);
1735 /* Main entry point of this file: search the body of INSN
1736 for values that need reloading and record them with push_reload.
1737 REPLACE nonzero means record also where the values occur
1738 so that subst_reloads can be used.
1740 IND_LEVELS says how many levels of indirection are supported by this
1741 machine; a value of zero means that a memory reference is not a valid
1744 LIVE_KNOWN says we have valid information about which hard
1745 regs are live at each point in the program; this is true when
1746 we are called from global_alloc but false when stupid register
1747 allocation has been done.
1749 RELOAD_REG_P if nonzero is a vector indexed by hard reg number
1750 which is nonnegative if the reg has been commandeered for reloading into.
1751 It is copied into STATIC_RELOAD_REG_P and referenced from there
1752 by various subroutines. */
1755 find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
1757 int replace, ind_levels;
1759 short *reload_reg_p;
1761 rtx non_reloaded_operands[MAX_RECOG_OPERANDS];
1762 int n_non_reloaded_operands = 0;
1763 #ifdef REGISTER_CONSTRAINTS
1765 enum reload_modified { RELOAD_NOTHING, RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE };
1767 register int insn_code_number;
1770 /* These are the constraints for the insn. We don't change them. */
1771 char *constraints1[MAX_RECOG_OPERANDS];
1772 /* These start out as the constraints for the insn
1773 and they are chewed up as we consider alternatives. */
1774 char *constraints[MAX_RECOG_OPERANDS];
1775 /* These are the preferred classes for an operand, or NO_REGS if it isn't
1777 enum reg_class preferred_class[MAX_RECOG_OPERANDS];
1778 char pref_or_nothing[MAX_RECOG_OPERANDS];
1779 /* Nonzero for a MEM operand whose entire address needs a reload. */
1780 int address_reloaded[MAX_RECOG_OPERANDS];
1781 int no_input_reloads = 0, no_output_reloads = 0;
1783 int this_alternative[MAX_RECOG_OPERANDS];
1784 char this_alternative_win[MAX_RECOG_OPERANDS];
1785 char this_alternative_offmemok[MAX_RECOG_OPERANDS];
1786 char this_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1787 int this_alternative_matches[MAX_RECOG_OPERANDS];
1789 int goal_alternative[MAX_RECOG_OPERANDS];
1790 int this_alternative_number;
1791 int goal_alternative_number;
1792 int operand_reloadnum[MAX_RECOG_OPERANDS];
1793 int goal_alternative_matches[MAX_RECOG_OPERANDS];
1794 int goal_alternative_matched[MAX_RECOG_OPERANDS];
1795 char goal_alternative_win[MAX_RECOG_OPERANDS];
1796 char goal_alternative_offmemok[MAX_RECOG_OPERANDS];
1797 char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1798 int goal_alternative_swapped;
1799 enum reload_modified modified[MAX_RECOG_OPERANDS];
1802 char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
1803 rtx substed_operand[MAX_RECOG_OPERANDS];
1804 rtx body = PATTERN (insn);
1805 rtx set = single_set (insn);
1806 int goal_earlyclobber, this_earlyclobber;
1807 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1810 this_insn_is_asm = 0; /* Tentative. */
1814 n_earlyclobbers = 0;
1815 replace_reloads = replace;
1816 hard_regs_live_known = live_known;
1817 static_reload_reg_p = reload_reg_p;
1819 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
1820 neither are insns that SET cc0. Insns that use CC0 are not allowed
1821 to have any input reloads. */
1822 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)
1823 no_output_reloads = 1;
1826 if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
1827 no_input_reloads = 1;
1828 if (reg_set_p (cc0_rtx, PATTERN (insn)))
1829 no_output_reloads = 1;
1832 /* Find what kind of insn this is. NOPERANDS gets number of operands.
1833 Make OPERANDS point to a vector of operand values.
1834 Make OPERAND_LOCS point to a vector of pointers to
1835 where the operands were found.
1836 Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the
1837 constraint-strings for this insn.
1838 Return if the insn needs no reload processing. */
1840 switch (GET_CODE (body))
1850 /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
1851 is cheap to move between them. If it is not, there may not be an insn
1852 to do the copy, so we may need a reload. */
1853 if (GET_CODE (SET_DEST (body)) == REG
1854 && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
1855 && GET_CODE (SET_SRC (body)) == REG
1856 && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
1857 && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))),
1858 REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
1862 noperands = asm_noperands (body);
1865 /* This insn is an `asm' with operands. */
1867 insn_code_number = -1;
1868 this_insn_is_asm = 1;
1870 /* expand_asm_operands makes sure there aren't too many operands. */
1871 if (noperands > MAX_RECOG_OPERANDS)
1874 /* Now get the operand values and constraints out of the insn. */
1876 decode_asm_operands (body, recog_operand, recog_operand_loc,
1877 constraints, operand_mode);
1880 bcopy (constraints, constraints1, noperands * sizeof (char *));
1881 n_alternatives = n_occurrences (',', constraints[0]) + 1;
1882 for (i = 1; i < noperands; i++)
1883 if (n_alternatives != n_occurrences (',', constraints[i]) + 1)
1885 error_for_asm (insn, "operand constraints differ in number of alternatives");
1886 /* Avoid further trouble with this insn. */
1887 PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
1896 /* Ordinary insn: recognize it, get the operands via insn_extract
1897 and get the constraints. */
1899 insn_code_number = recog_memoized (insn);
1900 if (insn_code_number < 0)
1901 fatal_insn_not_found (insn);
1903 noperands = insn_n_operands[insn_code_number];
1904 n_alternatives = insn_n_alternatives[insn_code_number];
1905 /* Just return "no reloads" if insn has no operands with constraints. */
1906 if (n_alternatives == 0)
1908 insn_extract (insn);
1909 for (i = 0; i < noperands; i++)
1911 constraints[i] = constraints1[i]
1912 = insn_operand_constraint[insn_code_number][i];
1913 operand_mode[i] = insn_operand_mode[insn_code_number][i];
1922 /* If we will need to know, later, whether some pair of operands
1923 are the same, we must compare them now and save the result.
1924 Reloading the base and index registers will clobber them
1925 and afterward they will fail to match. */
1927 for (i = 0; i < noperands; i++)
1932 substed_operand[i] = recog_operand[i];
1935 /* Scan this operand's constraint to see if it should match another. */
1940 /* The last operand should not be marked commutative. */
1941 if (i == noperands - 1)
1943 if (this_insn_is_asm)
1944 warning_for_asm (this_insn,
1945 "`%%' constraint used with last operand");
1952 else if (c >= '0' && c <= '9')
1955 operands_match[c][i]
1956 = operands_match_p (recog_operand[c], recog_operand[i]);
1957 /* If C can be commuted with C+1, and C might need to match I,
1958 then C+1 might also need to match I. */
1959 if (commutative >= 0)
1961 if (c == commutative || c == commutative + 1)
1963 int other = c + (c == commutative ? 1 : -1);
1964 operands_match[other][i]
1965 = operands_match_p (recog_operand[other], recog_operand[i]);
1967 if (i == commutative || i == commutative + 1)
1969 int other = i + (i == commutative ? 1 : -1);
1970 operands_match[c][other]
1971 = operands_match_p (recog_operand[c], recog_operand[other]);
1973 /* Note that C is supposed to be less than I.
1974 No need to consider altering both C and I
1975 because in that case we would alter one into the other. */
1980 /* Examine each operand that is a memory reference or memory address
1981 and reload parts of the addresses into index registers.
1982 While we are at it, initialize the array `modified'.
1983 Also here any references to pseudo regs that didn't get hard regs
1984 but are equivalent to constants get replaced in the insn itself
1985 with those constants. Nobody will ever see them again.
1987 Finally, set up the preferred classes of each operand. */
1989 for (i = 0; i < noperands; i++)
1991 register RTX_CODE code = GET_CODE (recog_operand[i]);
1992 modified[i] = RELOAD_READ;
1993 address_reloaded[i] = 0;
1995 if (constraints[i][0] == 'p')
1997 find_reloads_address (VOIDmode, NULL_PTR,
1998 recog_operand[i], recog_operand_loc[i],
1999 recog_operand[i], ind_levels);
2000 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2002 else if (code == MEM)
2004 if (find_reloads_address (GET_MODE (recog_operand[i]),
2005 recog_operand_loc[i],
2006 XEXP (recog_operand[i], 0),
2007 &XEXP (recog_operand[i], 0),
2008 recog_operand[i], ind_levels))
2009 address_reloaded[i] = 1;
2010 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2012 else if (code == SUBREG)
2013 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]
2014 = find_reloads_toplev (recog_operand[i], ind_levels,
2016 && &SET_DEST (set) == recog_operand_loc[i]);
2017 else if (code == REG)
2019 /* This is equivalent to calling find_reloads_toplev.
2020 The code is duplicated for speed.
2021 When we find a pseudo always equivalent to a constant,
2022 we replace it by the constant. We must be sure, however,
2023 that we don't try to replace it in the insn in which it
2025 register int regno = REGNO (recog_operand[i]);
2026 if (reg_equiv_constant[regno] != 0
2027 && (set == 0 || &SET_DEST (set) != recog_operand_loc[i]))
2028 substed_operand[i] = recog_operand[i]
2029 = reg_equiv_constant[regno];
2030 #if 0 /* This might screw code in reload1.c to delete prior output-reload
2031 that feeds this insn. */
2032 if (reg_equiv_mem[regno] != 0)
2033 substed_operand[i] = recog_operand[i]
2034 = reg_equiv_mem[regno];
2036 if (reg_equiv_address[regno] != 0)
2038 /* If reg_equiv_address is not a constant address, copy it,
2039 since it may be shared. */
2040 rtx address = reg_equiv_address[regno];
2042 if (rtx_varies_p (address))
2043 address = copy_rtx (address);
2045 /* If this is an output operand, we must output a CLOBBER
2046 after INSN so find_equiv_reg knows REGNO is being written. */
2047 if (constraints[i][0] == '='
2048 || constraints[i][0] == '+')
2049 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, recog_operand[i]),
2052 *recog_operand_loc[i] = recog_operand[i]
2053 = gen_rtx (MEM, GET_MODE (recog_operand[i]), address);
2054 RTX_UNCHANGING_P (recog_operand[i])
2055 = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
2056 find_reloads_address (GET_MODE (recog_operand[i]),
2057 recog_operand_loc[i],
2058 XEXP (recog_operand[i], 0),
2059 &XEXP (recog_operand[i], 0),
2060 recog_operand[i], ind_levels);
2061 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2064 /* If the operand is still a register (we didn't replace it with an
2065 equivalent), get the preferred class to reload it into. */
2066 code = GET_CODE (recog_operand[i]);
2068 = ((code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER)
2069 ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS);
2071 = (code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER
2072 && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS);
2075 /* If this is simply a copy from operand 1 to operand 0, merge the
2076 preferred classes for the operands. */
2077 if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set)
2078 && recog_operand[1] == SET_SRC (set))
2080 preferred_class[0] = preferred_class[1]
2081 = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]];
2082 pref_or_nothing[0] |= pref_or_nothing[1];
2083 pref_or_nothing[1] |= pref_or_nothing[0];
2086 /* Now see what we need for pseudo-regs that didn't get hard regs
2087 or got the wrong kind of hard reg. For this, we must consider
2088 all the operands together against the register constraints. */
2090 best = MAX_RECOG_OPERANDS + 300;
2093 goal_alternative_swapped = 0;
2096 /* The constraints are made of several alternatives.
2097 Each operand's constraint looks like foo,bar,... with commas
2098 separating the alternatives. The first alternatives for all
2099 operands go together, the second alternatives go together, etc.
2101 First loop over alternatives. */
2103 for (this_alternative_number = 0;
2104 this_alternative_number < n_alternatives;
2105 this_alternative_number++)
2107 /* Loop over operands for one constraint alternative. */
2108 /* LOSERS counts those that don't fit this alternative
2109 and would require loading. */
2111 /* BAD is set to 1 if it some operand can't fit this alternative
2112 even after reloading. */
2114 /* REJECT is a count of how undesirable this alternative says it is
2115 if any reloading is required. If the alternative matches exactly
2116 then REJECT is ignored, but otherwise it gets this much
2117 counted against it in addition to the reloading needed. Each
2118 ? counts three times here since we want the disparaging caused by
2119 a bad register class to only count 1/3 as much. */
2122 this_earlyclobber = 0;
2124 for (i = 0; i < noperands; i++)
2126 register char *p = constraints[i];
2127 register int win = 0;
2128 /* 0 => this operand can be reloaded somehow for this alternative */
2130 /* 0 => this operand can be reloaded if the alternative allows regs. */
2133 register rtx operand = recog_operand[i];
2135 /* Nonzero means this is a MEM that must be reloaded into a reg
2136 regardless of what the constraint says. */
2137 int force_reload = 0;
2139 int earlyclobber = 0;
2141 /* If the operand is a SUBREG, extract
2142 the REG or MEM (or maybe even a constant) within.
2143 (Constants can occur as a result of reg_equiv_constant.) */
2145 while (GET_CODE (operand) == SUBREG)
2147 offset += SUBREG_WORD (operand);
2148 operand = SUBREG_REG (operand);
2149 /* Force reload if this is not a register or if there may may
2150 be a problem accessing the register in the outer mode. */
2151 if (GET_CODE (operand) != REG
2152 #ifdef BYTE_LOADS_ZERO_EXTEND
2153 /* Nonparadoxical subreg of a pseudoreg.
2154 Don't to load the full width if on this machine
2155 we expected the fetch to zero-extend. */
2156 || ((GET_MODE_SIZE (operand_mode[i])
2157 > GET_MODE_SIZE (GET_MODE (operand)))
2158 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
2159 #endif /* BYTE_LOADS_ZERO_EXTEND */
2160 /* Subreg of a hard reg which can't handle the subreg's mode
2161 or which would handle that mode in the wrong number of
2162 registers for subregging to work. */
2163 || (REGNO (operand) < FIRST_PSEUDO_REGISTER
2164 && (! HARD_REGNO_MODE_OK (REGNO (operand),
2166 || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
2167 && (GET_MODE_SIZE (GET_MODE (operand))
2169 && ((GET_MODE_SIZE (GET_MODE (operand))
2171 != HARD_REGNO_NREGS (REGNO (operand),
2172 GET_MODE (operand)))))))
2176 this_alternative[i] = (int) NO_REGS;
2177 this_alternative_win[i] = 0;
2178 this_alternative_offmemok[i] = 0;
2179 this_alternative_earlyclobber[i] = 0;
2180 this_alternative_matches[i] = -1;
2182 /* An empty constraint or empty alternative
2183 allows anything which matched the pattern. */
2184 if (*p == 0 || *p == ',')
2187 /* Scan this alternative's specs for this operand;
2188 set WIN if the operand fits any letter in this alternative.
2189 Otherwise, clear BADOP if this operand could
2190 fit some letter after reloads,
2191 or set WINREG if this operand could fit after reloads
2192 provided the constraint allows some registers. */
2194 while (*p && (c = *p++) != ',')
2198 modified[i] = RELOAD_WRITE;
2202 modified[i] = RELOAD_READ_WRITE;
2221 /* Ignore rest of this alternative as far as
2222 reloading is concerned. */
2223 while (*p && *p != ',') p++;
2232 this_alternative_matches[i] = c;
2233 /* We are supposed to match a previous operand.
2234 If we do, we win if that one did.
2235 If we do not, count both of the operands as losers.
2236 (This is too conservative, since most of the time
2237 only a single reload insn will be needed to make
2238 the two operands win. As a result, this alternative
2239 may be rejected when it is actually desirable.) */
2240 if ((swapped && (c != commutative || i != commutative + 1))
2241 /* If we are matching as if two operands were swapped,
2242 also pretend that operands_match had been computed
2244 But if I is the second of those and C is the first,
2245 don't exchange them, because operands_match is valid
2246 only on one side of its diagonal. */
2248 [(c == commutative || c == commutative + 1)
2249 ? 2*commutative + 1 - c : c]
2250 [(i == commutative || i == commutative + 1)
2251 ? 2*commutative + 1 - i : i])
2252 : operands_match[c][i])
2253 win = this_alternative_win[c];
2256 /* Operands don't match. */
2258 /* Retroactively mark the operand we had to match
2259 as a loser, if it wasn't already. */
2260 if (this_alternative_win[c])
2262 this_alternative_win[c] = 0;
2263 if (this_alternative[c] == (int) NO_REGS)
2265 /* But count the pair only once in the total badness of
2266 this alternative, if the pair can be a dummy reload. */
2268 = find_dummy_reload (recog_operand[i], recog_operand[c],
2269 recog_operand_loc[i], recog_operand_loc[c],
2270 this_alternative[c], -1);
2275 /* This can be fixed with reloads if the operand
2276 we are supposed to match can be fixed with reloads. */
2278 this_alternative[i] = this_alternative[c];
2282 /* All necessary reloads for an address_operand
2283 were handled in find_reloads_address. */
2284 this_alternative[i] = (int) ALL_REGS;
2291 if (GET_CODE (operand) == MEM
2292 || (GET_CODE (operand) == REG
2293 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2294 && reg_renumber[REGNO (operand)] < 0))
2296 if (CONSTANT_P (operand))
2301 if (GET_CODE (operand) == MEM
2302 && ! address_reloaded[i]
2303 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
2304 || GET_CODE (XEXP (operand, 0)) == POST_DEC))
2309 if (GET_CODE (operand) == MEM
2310 && ! address_reloaded[i]
2311 && (GET_CODE (XEXP (operand, 0)) == PRE_INC
2312 || GET_CODE (XEXP (operand, 0)) == POST_INC))
2316 /* Memory operand whose address is not offsettable. */
2320 if (GET_CODE (operand) == MEM
2321 && ! (ind_levels ? offsettable_memref_p (operand)
2322 : offsettable_nonstrict_memref_p (operand))
2323 /* Certain mem addresses will become offsettable
2324 after they themselves are reloaded. This is important;
2325 we don't want our own handling of unoffsettables
2326 to override the handling of reg_equiv_address. */
2327 && !(GET_CODE (XEXP (operand, 0)) == REG
2329 || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
2333 /* Memory operand whose address is offsettable. */
2337 if ((GET_CODE (operand) == MEM
2338 /* If IND_LEVELS, find_reloads_address won't reload a
2339 pseudo that didn't get a hard reg, so we have to
2340 reject that case. */
2341 && (ind_levels ? offsettable_memref_p (operand)
2342 : offsettable_nonstrict_memref_p (operand)))
2343 /* Certain mem addresses will become offsettable
2344 after they themselves are reloaded. This is important;
2345 we don't want our own handling of unoffsettables
2346 to override the handling of reg_equiv_address. */
2347 || (GET_CODE (operand) == MEM
2348 && GET_CODE (XEXP (operand, 0)) == REG
2350 || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))
2351 || (GET_CODE (operand) == REG
2352 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2353 && reg_renumber[REGNO (operand)] < 0))
2355 if (CONSTANT_P (operand) || GET_CODE (operand) == MEM)
2361 /* Output operand that is stored before the need for the
2362 input operands (and their index registers) is over. */
2363 earlyclobber = 1, this_earlyclobber = 1;
2367 /* Match any floating double constant, but only if
2368 we can examine the bits of it reliably. */
2369 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2370 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2371 && GET_MODE (operand) != VOIDmode && ! flag_pretend_float)
2373 if (GET_CODE (operand) == CONST_DOUBLE)
2378 if (GET_CODE (operand) == CONST_DOUBLE)
2384 if (GET_CODE (operand) == CONST_DOUBLE
2385 && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c))
2390 if (GET_CODE (operand) == CONST_INT
2391 || (GET_CODE (operand) == CONST_DOUBLE
2392 && GET_MODE (operand) == VOIDmode))
2395 if (CONSTANT_P (operand)
2396 #ifdef LEGITIMATE_PIC_OPERAND_P
2397 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))
2404 if (GET_CODE (operand) == CONST_INT
2405 || (GET_CODE (operand) == CONST_DOUBLE
2406 && GET_MODE (operand) == VOIDmode))
2418 if (GET_CODE (operand) == CONST_INT
2419 && CONST_OK_FOR_LETTER_P (INTVAL (operand), c))
2429 /* A PLUS is never a valid operand, but reload can make
2430 it from a register when eliminating registers. */
2431 && GET_CODE (operand) != PLUS
2432 /* A SCRATCH is not a valid operand. */
2433 && GET_CODE (operand) != SCRATCH
2434 #ifdef LEGITIMATE_PIC_OPERAND_P
2435 && (! CONSTANT_P (operand)
2437 || LEGITIMATE_PIC_OPERAND_P (operand))
2439 && (GENERAL_REGS == ALL_REGS
2440 || GET_CODE (operand) != REG
2441 || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (operand)] < 0)))
2444 /* Drop through into 'r' case */
2448 = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];
2451 #ifdef EXTRA_CONSTRAINT
2457 if (EXTRA_CONSTRAINT (operand, c))
2464 = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)];
2467 if (GET_MODE (operand) == BLKmode)
2470 if (GET_CODE (operand) == REG
2471 && reg_fits_class_p (operand, this_alternative[i],
2472 offset, GET_MODE (recog_operand[i])))
2479 /* If this operand could be handled with a reg,
2480 and some reg is allowed, then this operand can be handled. */
2481 if (winreg && this_alternative[i] != (int) NO_REGS)
2484 /* Record which operands fit this alternative. */
2485 this_alternative_earlyclobber[i] = earlyclobber;
2486 if (win && ! force_reload)
2487 this_alternative_win[i] = 1;
2490 this_alternative_offmemok[i] = offmemok;
2494 /* Alternative loses if it has no regs for a reg operand. */
2495 if (GET_CODE (operand) == REG
2496 && this_alternative[i] == (int) NO_REGS
2497 && this_alternative_matches[i] < 0)
2500 /* Alternative loses if it requires a type of reload not
2501 permitted for this insn. We can always reload SCRATCH
2502 and objects with a REG_UNUSED note. */
2503 if (GET_CODE (operand) != SCRATCH && modified[i] != RELOAD_READ
2504 && no_output_reloads
2505 && ! find_reg_note (insn, REG_UNUSED, operand))
2507 else if (modified[i] != RELOAD_WRITE && no_input_reloads)
2510 /* We prefer to reload pseudos over reloading other things,
2511 since such reloads may be able to be eliminated later.
2512 If we are reloading a SCRATCH, we won't be generating any
2513 insns, just using a register, so it is also preferred.
2514 So bump REJECT in other cases. */
2515 if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH)
2519 /* If this operand is a pseudo register that didn't get a hard
2520 reg and this alternative accepts some register, see if the
2521 class that we want is a subset of the preferred class for this
2522 register. If not, but it intersects that class, use the
2523 preferred class instead. If it does not intersect the preferred
2524 class, show that usage of this alternative should be discouraged;
2525 it will be discouraged more still if the register is `preferred
2526 or nothing'. We do this because it increases the chance of
2527 reusing our spill register in a later insn and avoiding a pair
2528 of memory stores and loads.
2530 Don't bother with this if this alternative will accept this
2533 Don't do this if the preferred class has only one register
2534 because we might otherwise exhaust the class. */
2537 if (! win && this_alternative[i] != (int) NO_REGS
2538 && reg_class_size[(int) preferred_class[i]] > 1)
2540 if (! reg_class_subset_p (this_alternative[i],
2541 preferred_class[i]))
2543 /* Since we don't have a way of forming the intersection,
2544 we just do something special if the preferred class
2545 is a subset of the class we have; that's the most
2546 common case anyway. */
2547 if (reg_class_subset_p (preferred_class[i],
2548 this_alternative[i]))
2549 this_alternative[i] = (int) preferred_class[i];
2551 reject += (1 + pref_or_nothing[i]);
2556 /* Now see if any output operands that are marked "earlyclobber"
2557 in this alternative conflict with any input operands
2558 or any memory addresses. */
2560 for (i = 0; i < noperands; i++)
2561 if (this_alternative_earlyclobber[i]
2562 && this_alternative_win[i])
2564 struct decomposition early_data;
2567 early_data = decompose (recog_operand[i]);
2569 if (modified[i] == RELOAD_READ)
2571 if (this_insn_is_asm)
2572 warning_for_asm (this_insn,
2573 "`&' constraint used with input operand");
2579 if (this_alternative[i] == NO_REGS)
2581 this_alternative_earlyclobber[i] = 0;
2582 if (this_insn_is_asm)
2583 error_for_asm (this_insn,
2584 "`&' constraint used with no register class");
2589 for (j = 0; j < noperands; j++)
2590 /* Is this an input operand or a memory ref? */
2591 if ((GET_CODE (recog_operand[j]) == MEM
2592 || modified[j] != RELOAD_WRITE)
2594 /* Ignore things like match_operator operands. */
2595 && *constraints1[j] != 0
2596 /* Don't count an input operand that is constrained to match
2597 the early clobber operand. */
2598 && ! (this_alternative_matches[j] == i
2599 && rtx_equal_p (recog_operand[i], recog_operand[j]))
2600 /* Is it altered by storing the earlyclobber operand? */
2601 && !immune_p (recog_operand[j], recog_operand[i], early_data))
2603 /* If the output is in a single-reg class,
2604 it's costly to reload it, so reload the input instead. */
2605 if (reg_class_size[this_alternative[i]] == 1
2606 && (GET_CODE (recog_operand[j]) == REG
2607 || GET_CODE (recog_operand[j]) == SUBREG))
2610 this_alternative_win[j] = 0;
2615 /* If an earlyclobber operand conflicts with something,
2616 it must be reloaded, so request this and count the cost. */
2620 this_alternative_win[i] = 0;
2621 for (j = 0; j < noperands; j++)
2622 if (this_alternative_matches[j] == i
2623 && this_alternative_win[j])
2625 this_alternative_win[j] = 0;
2631 /* If one alternative accepts all the operands, no reload required,
2632 choose that alternative; don't consider the remaining ones. */
2635 /* Unswap these so that they are never swapped at `finish'. */
2636 if (commutative >= 0)
2638 recog_operand[commutative] = substed_operand[commutative];
2639 recog_operand[commutative + 1]
2640 = substed_operand[commutative + 1];
2642 for (i = 0; i < noperands; i++)
2644 goal_alternative_win[i] = 1;
2645 goal_alternative[i] = this_alternative[i];
2646 goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2647 goal_alternative_matches[i] = this_alternative_matches[i];
2648 goal_alternative_earlyclobber[i]
2649 = this_alternative_earlyclobber[i];
2651 goal_alternative_number = this_alternative_number;
2652 goal_alternative_swapped = swapped;
2653 goal_earlyclobber = this_earlyclobber;
2657 /* REJECT, set by the ! and ? constraint characters and when a register
2658 would be reloaded into a non-preferred class, discourages the use of
2659 this alternative for a reload goal. REJECT is incremented by three
2660 for each ? and one for each non-preferred class. */
2661 losers = losers * 3 + reject;
2663 /* If this alternative can be made to work by reloading,
2664 and it needs less reloading than the others checked so far,
2665 record it as the chosen goal for reloading. */
2666 if (! bad && best > losers)
2668 for (i = 0; i < noperands; i++)
2670 goal_alternative[i] = this_alternative[i];
2671 goal_alternative_win[i] = this_alternative_win[i];
2672 goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2673 goal_alternative_matches[i] = this_alternative_matches[i];
2674 goal_alternative_earlyclobber[i]
2675 = this_alternative_earlyclobber[i];
2677 goal_alternative_swapped = swapped;
2679 goal_alternative_number = this_alternative_number;
2680 goal_earlyclobber = this_earlyclobber;
2684 /* If insn is commutative (it's safe to exchange a certain pair of operands)
2685 then we need to try each alternative twice,
2686 the second time matching those two operands
2687 as if we had exchanged them.
2688 To do this, really exchange them in operands.
2690 If we have just tried the alternatives the second time,
2691 return operands to normal and drop through. */
2693 if (commutative >= 0)
2698 register enum reg_class tclass;
2701 recog_operand[commutative] = substed_operand[commutative + 1];
2702 recog_operand[commutative + 1] = substed_operand[commutative];
2704 tclass = preferred_class[commutative];
2705 preferred_class[commutative] = preferred_class[commutative + 1];
2706 preferred_class[commutative + 1] = tclass;
2708 t = pref_or_nothing[commutative];
2709 pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
2710 pref_or_nothing[commutative + 1] = t;
2712 bcopy (constraints1, constraints, noperands * sizeof (char *));
2717 recog_operand[commutative] = substed_operand[commutative];
2718 recog_operand[commutative + 1] = substed_operand[commutative + 1];
2722 /* The operands don't meet the constraints.
2723 goal_alternative describes the alternative
2724 that we could reach by reloading the fewest operands.
2725 Reload so as to fit it. */
2727 if (best == MAX_RECOG_OPERANDS + 300)
2729 /* No alternative works with reloads?? */
2730 if (insn_code_number >= 0)
2732 error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2733 /* Avoid further trouble with this insn. */
2734 PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2739 /* Jump to `finish' from above if all operands are valid already.
2740 In that case, goal_alternative_win is all 1. */
2743 /* Right now, for any pair of operands I and J that are required to match,
2745 goal_alternative_matches[J] is I.
2746 Set up goal_alternative_matched as the inverse function:
2747 goal_alternative_matched[I] = J. */
2749 for (i = 0; i < noperands; i++)
2750 goal_alternative_matched[i] = -1;
2752 for (i = 0; i < noperands; i++)
2753 if (! goal_alternative_win[i]
2754 && goal_alternative_matches[i] >= 0)
2755 goal_alternative_matched[goal_alternative_matches[i]] = i;
2757 /* If the best alternative is with operands 1 and 2 swapped,
2758 consider them swapped before reporting the reloads. */
2760 if (goal_alternative_swapped)
2764 tem = substed_operand[commutative];
2765 substed_operand[commutative] = substed_operand[commutative + 1];
2766 substed_operand[commutative + 1] = tem;
2767 tem = recog_operand[commutative];
2768 recog_operand[commutative] = recog_operand[commutative + 1];
2769 recog_operand[commutative + 1] = tem;
2772 /* Perform whatever substitutions on the operands we are supposed
2773 to make due to commutativity or replacement of registers
2774 with equivalent constants or memory slots. */
2776 for (i = 0; i < noperands; i++)
2778 *recog_operand_loc[i] = substed_operand[i];
2779 /* While we are looping on operands, initialize this. */
2780 operand_reloadnum[i] = -1;
2783 /* Any constants that aren't allowed and can't be reloaded
2784 into registers are here changed into memory references. */
2785 for (i = 0; i < noperands; i++)
2786 if (! goal_alternative_win[i]
2787 && CONSTANT_P (recog_operand[i])
2788 && (PREFERRED_RELOAD_CLASS (recog_operand[i],
2789 (enum reg_class) goal_alternative[i])
2791 && operand_mode[i] != VOIDmode)
2793 *recog_operand_loc[i] = recog_operand[i]
2794 = find_reloads_toplev (force_const_mem (operand_mode[i],
2797 if (alternative_allows_memconst (constraints1[i],
2798 goal_alternative_number))
2799 goal_alternative_win[i] = 1;
2802 /* Now record reloads for all the operands that need them. */
2803 for (i = 0; i < noperands; i++)
2804 if (! goal_alternative_win[i])
2806 /* Operands that match previous ones have already been handled. */
2807 if (goal_alternative_matches[i] >= 0)
2809 /* Handle an operand with a nonoffsettable address
2810 appearing where an offsettable address will do
2811 by reloading the address into a base register. */
2812 else if (goal_alternative_matched[i] == -1
2813 && goal_alternative_offmemok[i]
2814 && GET_CODE (recog_operand[i]) == MEM)
2816 operand_reloadnum[i]
2817 = push_reload (XEXP (recog_operand[i], 0), NULL_RTX,
2818 &XEXP (recog_operand[i], 0), NULL_PTR,
2819 BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)),
2820 VOIDmode, 0, 0, NULL_RTX);
2821 reload_inc[operand_reloadnum[i]]
2822 = GET_MODE_SIZE (GET_MODE (recog_operand[i]));
2824 else if (goal_alternative_matched[i] == -1)
2825 operand_reloadnum[i] =
2826 push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2827 modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2828 modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2829 modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2830 (enum reg_class) goal_alternative[i],
2831 (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2832 (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2833 (insn_code_number < 0 ? 0
2834 : insn_operand_strict_low[insn_code_number][i]),
2836 /* In a matching pair of operands, one must be input only
2837 and the other must be output only.
2838 Pass the input operand as IN and the other as OUT. */
2839 else if (modified[i] == RELOAD_READ
2840 && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
2842 operand_reloadnum[i]
2843 = push_reload (recog_operand[i],
2844 recog_operand[goal_alternative_matched[i]],
2845 recog_operand_loc[i],
2846 recog_operand_loc[goal_alternative_matched[i]],
2847 (enum reg_class) goal_alternative[i],
2849 operand_mode[goal_alternative_matched[i]],
2851 operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
2853 else if (modified[i] == RELOAD_WRITE
2854 && modified[goal_alternative_matched[i]] == RELOAD_READ)
2856 operand_reloadnum[goal_alternative_matched[i]]
2857 = push_reload (recog_operand[goal_alternative_matched[i]],
2859 recog_operand_loc[goal_alternative_matched[i]],
2860 recog_operand_loc[i],
2861 (enum reg_class) goal_alternative[i],
2862 operand_mode[goal_alternative_matched[i]],
2865 operand_reloadnum[i] = output_reloadnum;
2867 else if (insn_code_number >= 0)
2871 error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2872 /* Avoid further trouble with this insn. */
2873 PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2878 else if (goal_alternative_matched[i] < 0
2879 && goal_alternative_matches[i] < 0
2882 rtx operand = recog_operand[i];
2883 /* For each non-matching operand that's a pseudo-register
2884 that didn't get a hard register, make an optional reload.
2885 This may get done even if the insn needs no reloads otherwise. */
2886 /* (It would be safe to make an optional reload for a matching pair
2887 of operands, but we don't bother yet.) */
2888 while (GET_CODE (operand) == SUBREG)
2889 operand = XEXP (operand, 0);
2890 if (GET_CODE (operand) == REG
2891 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2892 && reg_renumber[REGNO (operand)] < 0
2893 && (enum reg_class) goal_alternative[i] != NO_REGS
2894 /* Don't make optional output reloads for jump insns
2895 (such as aobjeq on the vax). */
2896 && (modified[i] == RELOAD_READ
2897 || GET_CODE (insn) != JUMP_INSN))
2898 operand_reloadnum[i]
2899 = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2900 modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2901 modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2902 modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2903 (enum reg_class) goal_alternative[i],
2904 (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2905 (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2906 (insn_code_number < 0 ? 0
2907 : insn_operand_strict_low[insn_code_number][i]),
2909 /* Make an optional reload for an explicit mem ref. */
2910 else if (GET_CODE (operand) == MEM
2911 && (enum reg_class) goal_alternative[i] != NO_REGS
2912 /* Don't make optional output reloads for jump insns
2913 (such as aobjeq on the vax). */
2914 && (modified[i] == RELOAD_READ
2915 || GET_CODE (insn) != JUMP_INSN))
2916 operand_reloadnum[i]
2917 = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2918 modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2919 modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2920 modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2921 (enum reg_class) goal_alternative[i],
2922 (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2923 (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2924 (insn_code_number < 0 ? 0
2925 : insn_operand_strict_low[insn_code_number][i]),
2928 non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
2930 else if (goal_alternative_matched[i] < 0
2931 && goal_alternative_matches[i] < 0)
2932 non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
2934 /* Record the values of the earlyclobber operands for the caller. */
2935 if (goal_earlyclobber)
2936 for (i = 0; i < noperands; i++)
2937 if (goal_alternative_earlyclobber[i])
2938 reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i];
2940 /* If this insn pattern contains any MATCH_DUP's, make sure that
2941 they will be substituted if the operands they match are substituted.
2942 Also do now any substitutions we already did on the operands.
2944 Don't do this if we aren't making replacements because we might be
2945 propagating things allocated by frame pointer elimination into places
2946 it doesn't expect. */
2948 if (insn_code_number >= 0 && replace)
2949 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
2951 int opno = recog_dup_num[i];
2952 *recog_dup_loc[i] = *recog_operand_loc[opno];
2953 if (operand_reloadnum[opno] >= 0)
2954 push_replacement (recog_dup_loc[i], operand_reloadnum[opno],
2955 insn_operand_mode[insn_code_number][opno]);
2959 /* This loses because reloading of prior insns can invalidate the equivalence
2960 (or at least find_equiv_reg isn't smart enough to find it any more),
2961 causing this insn to need more reload regs than it needed before.
2962 It may be too late to make the reload regs available.
2963 Now this optimization is done safely in choose_reload_regs. */
2965 /* For each reload of a reg into some other class of reg,
2966 search for an existing equivalent reg (same value now) in the right class.
2967 We can use it as long as we don't need to change its contents. */
2968 for (i = 0; i < n_reloads; i++)
2969 if (reload_reg_rtx[i] == 0
2970 && reload_in[i] != 0
2971 && GET_CODE (reload_in[i]) == REG
2972 && reload_out[i] == 0)
2975 = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1,
2976 static_reload_reg_p, 0, reload_inmode[i]);
2977 /* Prevent generation of insn to load the value
2978 because the one we found already has the value. */
2979 if (reload_reg_rtx[i])
2980 reload_in[i] = reload_reg_rtx[i];
2984 #else /* no REGISTER_CONSTRAINTS */
2986 int insn_code_number;
2987 int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */
2989 rtx body = PATTERN (insn);
2993 n_earlyclobbers = 0;
2994 replace_reloads = replace;
2997 /* Find what kind of insn this is. NOPERANDS gets number of operands.
2998 Store the operand values in RECOG_OPERAND and the locations
2999 of the words in the insn that point to them in RECOG_OPERAND_LOC.
3000 Return if the insn needs no reload processing. */
3002 switch (GET_CODE (body))
3013 noperands = asm_noperands (body);
3016 /* This insn is an `asm' with operands.
3017 First, find out how many operands, and allocate space. */
3019 insn_code_number = -1;
3020 /* ??? This is a bug! ???
3021 Give up and delete this insn if it has too many operands. */
3022 if (noperands > MAX_RECOG_OPERANDS)
3025 /* Now get the operand values out of the insn. */
3027 decode_asm_operands (body, recog_operand, recog_operand_loc,
3028 NULL_PTR, NULL_PTR);
3033 /* Ordinary insn: recognize it, allocate space for operands and
3034 constraints, and get them out via insn_extract. */
3036 insn_code_number = recog_memoized (insn);
3037 noperands = insn_n_operands[insn_code_number];
3038 insn_extract (insn);
3044 for (i = 0; i < noperands; i++)
3046 register RTX_CODE code = GET_CODE (recog_operand[i]);
3047 int is_set_dest = GET_CODE (body) == SET && (i == 0);
3049 if (insn_code_number >= 0)
3050 if (insn_operand_address_p[insn_code_number][i])
3051 find_reloads_address (VOIDmode, NULL_PTR,
3052 recog_operand[i], recog_operand_loc[i],
3053 recog_operand[i], ind_levels);
3055 find_reloads_address (GET_MODE (recog_operand[i]),
3056 recog_operand_loc[i],
3057 XEXP (recog_operand[i], 0),
3058 &XEXP (recog_operand[i], 0),
3059 recog_operand[i], ind_levels);
3061 recog_operand[i] = *recog_operand_loc[i]
3062 = find_reloads_toplev (recog_operand[i], ind_levels, is_set_dest);
3065 register int regno = REGNO (recog_operand[i]);
3066 if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3067 recog_operand[i] = *recog_operand_loc[i]
3068 = reg_equiv_constant[regno];
3069 #if 0 /* This might screw code in reload1.c to delete prior output-reload
3070 that feeds this insn. */
3071 if (reg_equiv_mem[regno] != 0)
3072 recog_operand[i] = *recog_operand_loc[i]
3073 = reg_equiv_mem[regno];
3076 /* All operands are non-reloaded. */
3077 non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
3079 #endif /* no REGISTER_CONSTRAINTS */
3081 /* Determine which part of the insn each reload is needed for,
3082 based on which operand the reload is needed for.
3083 Reloads of entire operands are classified as RELOAD_OTHER.
3084 So are reloads for which a unique purpose is not known. */
3086 for (i = 0; i < n_reloads; i++)
3088 reload_when_needed[i] = RELOAD_OTHER;
3090 if (reload_needed_for[i] != 0 && ! reload_needed_for_multiple[i])
3093 int output_address = 0;
3094 int input_address = 0;
3095 int operand_address = 0;
3097 /* This reload is needed only for the address of something.
3098 Determine whether it is needed for addressing an operand
3099 being reloaded for input, whether it is needed for an
3100 operand being reloaded for output, and whether it is needed
3101 for addressing an operand that won't really be reloaded.
3103 Note that we know that this reload is needed in only one address,
3104 but we have not yet checked for the case where that same address
3105 is used in both input and output reloads.
3106 The following code detects this case. */
3108 for (j = 0; j < n_reloads; j++)
3109 if (reload_needed_for[i] == reload_in[j]
3110 || reload_needed_for[i] == reload_out[j])
3112 if (reload_optional[j])
3113 operand_address = 1;
3116 if (reload_needed_for[i] == reload_in[j])
3118 if (reload_needed_for[i] == reload_out[j])
3122 /* Don't ignore memrefs without optional reloads. */
3123 for (j = 0; j < n_non_reloaded_operands; j++)
3124 if (reload_needed_for[i] == non_reloaded_operands[j])
3125 operand_address = 1;
3127 /* If it is needed for only one of those, record which one. */
3129 if (input_address && ! output_address && ! operand_address)
3130 reload_when_needed[i] = RELOAD_FOR_INPUT_RELOAD_ADDRESS;
3131 if (output_address && ! input_address && ! operand_address)
3132 reload_when_needed[i] = RELOAD_FOR_OUTPUT_RELOAD_ADDRESS;
3133 if (operand_address && ! input_address && ! output_address)
3134 reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS;
3136 /* Indicate those RELOAD_OTHER reloads which, though they have
3137 0 for reload_output, still cannot overlap an output reload. */
3139 if (output_address && reload_when_needed[i] == RELOAD_OTHER)
3140 reload_needed_for_multiple[i] = 1;
3144 /* Perhaps an output reload can be combined with another
3145 to reduce needs by one. */
3146 if (!goal_earlyclobber)
3150 /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT
3151 accepts a memory operand with constant address. */
3154 alternative_allows_memconst (constraint, altnum)
3159 /* Skip alternatives before the one requested. */
3162 while (*constraint++ != ',');
3165 /* Scan the requested alternative for 'm' or 'o'.
3166 If one of them is present, this alternative accepts memory constants. */
3167 while ((c = *constraint++) && c != ',' && c != '#')
3168 if (c == 'm' || c == 'o')
3173 /* Scan X for memory references and scan the addresses for reloading.
3174 Also checks for references to "constant" regs that we want to eliminate
3175 and replaces them with the values they stand for.
3176 We may alter X destructively if it contains a reference to such.
3177 If X is just a constant reg, we return the equivalent value
3180 IND_LEVELS says how many levels of indirect addressing this machine
3183 IS_SET_DEST is true if X is the destination of a SET, which is not
3184 appropriate to be replaced by a constant. */
3187 find_reloads_toplev (x, ind_levels, is_set_dest)
3192 register RTX_CODE code = GET_CODE (x);
3194 register char *fmt = GET_RTX_FORMAT (code);
3199 /* This code is duplicated for speed in find_reloads. */
3200 register int regno = REGNO (x);
3201 if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3202 x = reg_equiv_constant[regno];
3204 /* This creates (subreg (mem...)) which would cause an unnecessary
3205 reload of the mem. */
3206 else if (reg_equiv_mem[regno] != 0)
3207 x = reg_equiv_mem[regno];
3209 else if (reg_equiv_address[regno] != 0)
3211 /* If reg_equiv_address varies, it may be shared, so copy it. */
3212 rtx addr = reg_equiv_address[regno];
3214 if (rtx_varies_p (addr))
3215 addr = copy_rtx (addr);
3217 x = gen_rtx (MEM, GET_MODE (x), addr);
3218 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3219 find_reloads_address (GET_MODE (x), NULL_PTR,
3221 &XEXP (x, 0), x, ind_levels);
3228 find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
3233 if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
3235 /* Check for SUBREG containing a REG that's equivalent to a constant.
3236 If the constant has a known value, truncate it right now.
3237 Similarly if we are extracting a single-word of a multi-word
3238 constant. If the constant is symbolic, allow it to be substituted
3239 normally. push_reload will strip the subreg later. If the
3240 constant is VOIDmode, abort because we will lose the mode of
3241 the register (this should never happen because one of the cases
3242 above should handle it). */
3244 register int regno = REGNO (SUBREG_REG (x));
3247 if (subreg_lowpart_p (x)
3248 && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3249 && reg_equiv_constant[regno] != 0
3250 && (tem = gen_lowpart_common (GET_MODE (x),
3251 reg_equiv_constant[regno])) != 0)
3254 if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD
3255 && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3256 && reg_equiv_constant[regno] != 0
3257 && (tem = operand_subword (reg_equiv_constant[regno],
3259 GET_MODE (SUBREG_REG (x)))) != 0)
3262 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3263 && reg_equiv_constant[regno] != 0
3264 && GET_MODE (reg_equiv_constant[regno]) == VOIDmode)
3267 /* If the subreg contains a reg that will be converted to a mem,
3268 convert the subreg to a narrower memref now.
3269 Otherwise, we would get (subreg (mem ...) ...),
3270 which would force reload of the mem.
3272 We also need to do this if there is an equivalent MEM that is
3273 not offsettable. In that case, alter_subreg would produce an
3274 invalid address on big-endian machines.
3276 For machines that zero-extend byte loads, we must not reload using
3277 a wider mode if we have a paradoxical SUBREG. find_reloads will
3278 force a reload in that case. So we should not do anything here. */
3280 else if (regno >= FIRST_PSEUDO_REGISTER
3281 #ifdef BYTE_LOADS_ZERO_EXTEND
3282 && (GET_MODE_SIZE (GET_MODE (x))
3283 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3285 && (reg_equiv_address[regno] != 0
3286 || (reg_equiv_mem[regno] != 0
3287 && ! offsettable_memref_p (reg_equiv_mem[regno]))))
3289 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3290 rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno]
3291 : XEXP (reg_equiv_mem[regno], 0));
3292 #if BYTES_BIG_ENDIAN
3294 size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
3295 offset += MIN (size, UNITS_PER_WORD);
3296 size = GET_MODE_SIZE (GET_MODE (x));
3297 offset -= MIN (size, UNITS_PER_WORD);
3299 addr = plus_constant (addr, offset);
3300 x = gen_rtx (MEM, GET_MODE (x), addr);
3301 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3302 find_reloads_address (GET_MODE (x), NULL_PTR,
3304 &XEXP (x, 0), x, ind_levels);
3309 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3312 XEXP (x, i) = find_reloads_toplev (XEXP (x, i),
3313 ind_levels, is_set_dest);
3319 make_memloc (ad, regno)
3324 rtx tem = reg_equiv_address[regno];
3325 for (i = 0; i < n_memlocs; i++)
3326 if (rtx_equal_p (tem, XEXP (memlocs[i], 0)))
3329 /* If TEM might contain a pseudo, we must copy it to avoid
3330 modifying it when we do the substitution for the reload. */
3331 if (rtx_varies_p (tem))
3332 tem = copy_rtx (tem);
3334 tem = gen_rtx (MEM, GET_MODE (ad), tem);
3335 RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3336 memlocs[n_memlocs++] = tem;
3340 /* Record all reloads needed for handling memory address AD
3341 which appears in *LOC in a memory reference to mode MODE
3342 which itself is found in location *MEMREFLOC.
3343 Note that we take shortcuts assuming that no multi-reg machine mode
3344 occurs as part of an address.
3346 OPERAND is the operand of the insn within which this address appears.
3348 IND_LEVELS says how many levels of indirect addressing this machine
3351 Value is nonzero if this address is reloaded or replaced as a whole.
3352 This is interesting to the caller if the address is an autoincrement.
3354 Note that there is no verification that the address will be valid after
3355 this routine does its work. Instead, we rely on the fact that the address
3356 was valid when reload started. So we need only undo things that reload
3357 could have broken. These are wrong register types, pseudos not allocated
3358 to a hard register, and frame pointer elimination. */
3361 find_reloads_address (mode, memrefloc, ad, loc, operand, ind_levels)
3362 enum machine_mode mode;
3372 /* If the address is a register, see if it is a legitimate address and
3373 reload if not. We first handle the cases where we need not reload
3374 or where we must reload in a non-standard way. */
3376 if (GET_CODE (ad) == REG)
3380 if (reg_equiv_constant[regno] != 0
3381 && strict_memory_address_p (mode, reg_equiv_constant[regno]))
3383 *loc = ad = reg_equiv_constant[regno];
3387 else if (reg_equiv_address[regno] != 0)
3389 tem = make_memloc (ad, regno);
3390 find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0),
3391 &XEXP (tem, 0), operand, ind_levels);
3392 push_reload (tem, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS,
3393 GET_MODE (ad), VOIDmode, 0, 0,
3398 else if (reg_equiv_mem[regno] != 0)
3400 tem = XEXP (reg_equiv_mem[regno], 0);
3402 /* If we can't indirect any more, a pseudo must be reloaded.
3403 If the pseudo's address in its MEM is a SYMBOL_REF, it
3404 must be reloaded unless indirect_symref_ok. Otherwise, it
3405 can be reloaded if the address is REG or REG + CONST_INT. */
3408 && ! (GET_CODE (tem) == SYMBOL_REF && ! indirect_symref_ok)
3409 && ((GET_CODE (tem) == REG
3410 && REGNO (tem) < FIRST_PSEUDO_REGISTER)
3411 || (GET_CODE (tem) == PLUS
3412 && GET_CODE (XEXP (tem, 0)) == REG
3413 && REGNO (XEXP (tem, 0)) < FIRST_PSEUDO_REGISTER
3414 && GET_CODE (XEXP (tem, 1)) == CONST_INT)))
3418 /* The only remaining case where we can avoid a reload is if this is a
3419 hard register that is valid as a base register and which is not the
3420 subject of a CLOBBER in this insn. */
3422 else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno)
3423 && ! regno_clobbered_p (regno, this_insn))
3426 /* If we do not have one of the cases above, we must do the reload. */
3427 push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS,
3428 GET_MODE (ad), VOIDmode, 0, 0, operand);
3432 if (strict_memory_address_p (mode, ad))
3434 /* The address appears valid, so reloads are not needed.
3435 But the address may contain an eliminable register.
3436 This can happen because a machine with indirect addressing
3437 may consider a pseudo register by itself a valid address even when
3438 it has failed to get a hard reg.
3439 So do a tree-walk to find and eliminate all such regs. */
3441 /* But first quickly dispose of a common case. */
3442 if (GET_CODE (ad) == PLUS
3443 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3444 && GET_CODE (XEXP (ad, 0)) == REG
3445 && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
3448 subst_reg_equivs_changed = 0;
3449 *loc = subst_reg_equivs (ad);
3451 if (! subst_reg_equivs_changed)
3454 /* Check result for validity after substitution. */
3455 if (strict_memory_address_p (mode, ad))
3459 /* The address is not valid. We have to figure out why. One possibility
3460 is that it is itself a MEM. This can happen when the frame pointer is
3461 being eliminated, a pseudo is not allocated to a hard register, and the
3462 offset between the frame and stack pointers is not its initial value.
3463 In that case the pseudo will have been replaced by a MEM referring to
3464 the stack pointer. */
3465 if (GET_CODE (ad) == MEM)
3467 /* First ensure that the address in this MEM is valid. Then, unless
3468 indirect addresses are valid, reload the MEM into a register. */
3470 find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
3471 operand, ind_levels == 0 ? 0 : ind_levels - 1);
3472 /* Check similar cases as for indirect addresses as above except
3473 that we can allow pseudos and a MEM since they should have been
3474 taken care of above. */
3477 || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
3478 || GET_CODE (XEXP (tem, 0)) == MEM
3479 || ! (GET_CODE (XEXP (tem, 0)) == REG
3480 || (GET_CODE (XEXP (tem, 0)) == PLUS
3481 && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
3482 && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT)))
3484 /* Must use TEM here, not AD, since it is the one that will
3485 have any subexpressions reloaded, if needed. */
3486 push_reload (tem, NULL_RTX, loc, NULL_PTR,
3487 BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0,
3495 /* If we have address of a stack slot but it's not valid
3496 (displacement is too large), compute the sum in a register. */
3497 else if (GET_CODE (ad) == PLUS
3498 && (XEXP (ad, 0) == frame_pointer_rtx
3499 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3500 || XEXP (ad, 0) == arg_pointer_rtx
3502 || XEXP (ad, 0) == stack_pointer_rtx)
3503 && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3505 /* Unshare the MEM rtx so we can safely alter it. */
3508 rtx oldref = *memrefloc;
3509 *memrefloc = copy_rtx (*memrefloc);
3510 loc = &XEXP (*memrefloc, 0);
3511 if (operand == oldref)
3512 operand = *memrefloc;
3514 if (double_reg_address_ok)
3516 /* Unshare the sum as well. */
3517 *loc = ad = copy_rtx (ad);
3518 /* Reload the displacement into an index reg.
3519 We assume the frame pointer or arg pointer is a base reg. */
3520 find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
3521 INDEX_REG_CLASS, GET_MODE (ad), operand,
3526 /* If the sum of two regs is not necessarily valid,
3527 reload the sum into a base reg.
3528 That will at least work. */
3529 find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode,
3530 operand, ind_levels);
3535 /* If we have an indexed stack slot, there are three possible reasons why
3536 it might be invalid: The index might need to be reloaded, the address
3537 might have been made by frame pointer elimination and hence have a
3538 constant out of range, or both reasons might apply.
3540 We can easily check for an index needing reload, but even if that is the
3541 case, we might also have an invalid constant. To avoid making the
3542 conservative assumption and requiring two reloads, we see if this address
3543 is valid when not interpreted strictly. If it is, the only problem is
3544 that the index needs a reload and find_reloads_address_1 will take care
3547 There is still a case when we might generate an extra reload,
3548 however. In certain cases eliminate_regs will return a MEM for a REG
3549 (see the code there for details). In those cases, memory_address_p
3550 applied to our address will return 0 so we will think that our offset
3551 must be too large. But it might indeed be valid and the only problem
3552 is that a MEM is present where a REG should be. This case should be
3553 very rare and there doesn't seem to be any way to avoid it.
3555 If we decide to do something here, it must be that
3556 `double_reg_address_ok' is true and that this address rtl was made by
3557 eliminate_regs. We generate a reload of the fp/sp/ap + constant and
3558 rework the sum so that the reload register will be added to the index.
3559 This is safe because we know the address isn't shared.
3561 We check for fp/ap/sp as both the first and second operand of the
3564 else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3565 && GET_CODE (XEXP (ad, 0)) == PLUS
3566 && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx
3567 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3568 || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx
3570 || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx)
3571 && ! memory_address_p (mode, ad))
3573 *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3574 plus_constant (XEXP (XEXP (ad, 0), 0),
3575 INTVAL (XEXP (ad, 1))),
3576 XEXP (XEXP (ad, 0), 1));
3577 find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3578 GET_MODE (ad), operand, ind_levels);
3579 find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3584 else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3585 && GET_CODE (XEXP (ad, 0)) == PLUS
3586 && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
3587 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3588 || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx
3590 || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx)
3591 && ! memory_address_p (mode, ad))
3593 *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3594 plus_constant (XEXP (XEXP (ad, 0), 1),
3595 INTVAL (XEXP (ad, 1))),
3596 XEXP (XEXP (ad, 0), 0));
3597 find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3598 GET_MODE (ad), operand, ind_levels);
3599 find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3604 /* See if address becomes valid when an eliminable register
3605 in a sum is replaced. */
3608 if (GET_CODE (ad) == PLUS)
3609 tem = subst_indexed_address (ad);
3610 if (tem != ad && strict_memory_address_p (mode, tem))
3612 /* Ok, we win that way. Replace any additional eliminable
3615 subst_reg_equivs_changed = 0;
3616 tem = subst_reg_equivs (tem);
3618 /* Make sure that didn't make the address invalid again. */
3620 if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem))
3627 /* If constants aren't valid addresses, reload the constant address
3629 if (CONSTANT_ADDRESS_P (ad) && ! strict_memory_address_p (mode, ad))
3631 /* If AD is in address in the constant pool, the MEM rtx may be shared.
3632 Unshare it so we can safely alter it. */
3633 if (memrefloc && GET_CODE (ad) == SYMBOL_REF
3634 && CONSTANT_POOL_ADDRESS_P (ad))
3636 rtx oldref = *memrefloc;
3637 *memrefloc = copy_rtx (*memrefloc);
3638 loc = &XEXP (*memrefloc, 0);
3639 if (operand == oldref)
3640 operand = *memrefloc;
3643 find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, operand,
3648 return find_reloads_address_1 (ad, 0, loc, operand, ind_levels);
3651 /* Find all pseudo regs appearing in AD
3652 that are eliminable in favor of equivalent values
3653 and do not have hard regs; replace them by their equivalents. */
3656 subst_reg_equivs (ad)
3659 register RTX_CODE code = GET_CODE (ad);
3677 register int regno = REGNO (ad);
3679 if (reg_equiv_constant[regno] != 0)
3681 subst_reg_equivs_changed = 1;
3682 return reg_equiv_constant[regno];
3688 /* Quickly dispose of a common case. */
3689 if (XEXP (ad, 0) == frame_pointer_rtx
3690 && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3694 fmt = GET_RTX_FORMAT (code);
3695 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3697 XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i));
3701 /* Compute the sum of X and Y, making canonicalizations assumed in an
3702 address, namely: sum constant integers, surround the sum of two
3703 constants with a CONST, put the constant as the second operand, and
3704 group the constant on the outermost sum.
3706 This routine assumes both inputs are already in canonical form. */
3714 if (GET_CODE (x) == CONST_INT)
3715 return plus_constant (y, INTVAL (x));
3716 else if (GET_CODE (y) == CONST_INT)
3717 return plus_constant (x, INTVAL (y));
3718 else if (CONSTANT_P (x))
3719 tem = x, x = y, y = tem;
3721 if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
3722 return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));
3724 /* Note that if the operands of Y are specified in the opposite
3725 order in the recursive calls below, infinite recursion will occur. */
3726 if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
3727 return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));
3729 /* If both constant, encapsulate sum. Otherwise, just form sum. A
3730 constant will have been placed second. */
3731 if (CONSTANT_P (x) && CONSTANT_P (y))
3733 if (GET_CODE (x) == CONST)
3735 if (GET_CODE (y) == CONST)
3738 return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, Pmode, x, y));
3741 return gen_rtx (PLUS, Pmode, x, y);
3744 /* If ADDR is a sum containing a pseudo register that should be
3745 replaced with a constant (from reg_equiv_constant),
3746 return the result of doing so, and also apply the associative
3747 law so that the result is more likely to be a valid address.
3748 (But it is not guaranteed to be one.)
3750 Note that at most one register is replaced, even if more are
3751 replaceable. Also, we try to put the result into a canonical form
3752 so it is more likely to be a valid address.
3754 In all other cases, return ADDR. */
3757 subst_indexed_address (addr)
3760 rtx op0 = 0, op1 = 0, op2 = 0;
3764 if (GET_CODE (addr) == PLUS)
3766 /* Try to find a register to replace. */
3767 op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
3768 if (GET_CODE (op0) == REG
3769 && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
3770 && reg_renumber[regno] < 0
3771 && reg_equiv_constant[regno] != 0)
3772 op0 = reg_equiv_constant[regno];
3773 else if (GET_CODE (op1) == REG
3774 && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
3775 && reg_renumber[regno] < 0
3776 && reg_equiv_constant[regno] != 0)
3777 op1 = reg_equiv_constant[regno];
3778 else if (GET_CODE (op0) == PLUS
3779 && (tem = subst_indexed_address (op0)) != op0)
3781 else if (GET_CODE (op1) == PLUS
3782 && (tem = subst_indexed_address (op1)) != op1)
3787 /* Pick out up to three things to add. */
3788 if (GET_CODE (op1) == PLUS)
3789 op2 = XEXP (op1, 1), op1 = XEXP (op1, 0);
3790 else if (GET_CODE (op0) == PLUS)
3791 op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3793 /* Compute the sum. */
3795 op1 = form_sum (op1, op2);
3797 op0 = form_sum (op0, op1);
3804 /* Record the pseudo registers we must reload into hard registers
3805 in a subexpression of a would-be memory address, X.
3806 (This function is not called if the address we find is strictly valid.)
3807 CONTEXT = 1 means we are considering regs as index regs,
3808 = 0 means we are considering them as base regs.
3810 OPERAND is the operand of the insn within which this address appears.
3812 IND_LEVELS says how many levels of indirect addressing are
3813 supported at this point in the address.
3815 We return nonzero if X, as a whole, is reloaded or replaced. */
3817 /* Note that we take shortcuts assuming that no multi-reg machine mode
3818 occurs as part of an address.
3819 Also, this is not fully machine-customizable; it works for machines
3820 such as vaxes and 68000's and 32000's, but other possible machines
3821 could have addressing modes that this does not handle right. */
3824 find_reloads_address_1 (x, context, loc, operand, ind_levels)
3831 register RTX_CODE code = GET_CODE (x);
3835 register rtx op0 = XEXP (x, 0);
3836 register rtx op1 = XEXP (x, 1);
3837 register RTX_CODE code0 = GET_CODE (op0);
3838 register RTX_CODE code1 = GET_CODE (op1);
3839 if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM)
3841 find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3842 find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3844 else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM)
3846 find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3847 find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3849 else if (code0 == CONST_INT || code0 == CONST
3850 || code0 == SYMBOL_REF || code0 == LABEL_REF)
3852 find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3854 else if (code1 == CONST_INT || code1 == CONST
3855 || code1 == SYMBOL_REF || code1 == LABEL_REF)
3857 find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3859 else if (code0 == REG && code1 == REG)
3861 if (REG_OK_FOR_INDEX_P (op0)
3862 && REG_OK_FOR_BASE_P (op1))
3864 else if (REG_OK_FOR_INDEX_P (op1)
3865 && REG_OK_FOR_BASE_P (op0))
3867 else if (REG_OK_FOR_BASE_P (op1))
3868 find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3869 else if (REG_OK_FOR_BASE_P (op0))
3870 find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3871 else if (REG_OK_FOR_INDEX_P (op1))
3872 find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3873 else if (REG_OK_FOR_INDEX_P (op0))
3874 find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3877 find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand,
3879 find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand,
3883 else if (code0 == REG)
3885 find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3886 find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3888 else if (code1 == REG)
3890 find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3891 find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3894 else if (code == POST_INC || code == POST_DEC
3895 || code == PRE_INC || code == PRE_DEC)
3897 if (GET_CODE (XEXP (x, 0)) == REG)
3899 register int regno = REGNO (XEXP (x, 0));
3903 /* A register that is incremented cannot be constant! */
3904 if (regno >= FIRST_PSEUDO_REGISTER
3905 && reg_equiv_constant[regno] != 0)
3908 /* Handle a register that is equivalent to a memory location
3909 which cannot be addressed directly. */
3910 if (reg_equiv_address[regno] != 0)
3912 rtx tem = make_memloc (XEXP (x, 0), regno);
3913 /* First reload the memory location's address. */
3914 find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0),
3915 &XEXP (tem, 0), operand, ind_levels);
3916 /* Put this inside a new increment-expression. */
3917 x = gen_rtx (GET_CODE (x), GET_MODE (x), tem);
3918 /* Proceed to reload that, as if it contained a register. */
3921 /* If we have a hard register that is ok as an index,
3922 don't make a reload. If an autoincrement of a nice register
3923 isn't "valid", it must be that no autoincrement is "valid".
3924 If that is true and something made an autoincrement anyway,
3925 this must be a special context where one is allowed.
3926 (For example, a "push" instruction.)
3927 We can't improve this address, so leave it alone. */
3929 /* Otherwise, reload the autoincrement into a suitable hard reg
3930 and record how much to increment by. */
3932 if (reg_renumber[regno] >= 0)
3933 regno = reg_renumber[regno];
3934 if ((regno >= FIRST_PSEUDO_REGISTER
3935 || !(context ? REGNO_OK_FOR_INDEX_P (regno)
3936 : REGNO_OK_FOR_BASE_P (regno))))
3941 = push_reload (x, NULL_RTX, loc, NULL_PTR,
3942 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3943 GET_MODE (x), GET_MODE (x), VOIDmode, 0, operand);
3944 reload_inc[reloadnum]
3945 = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
3950 /* Update the REG_INC notes. */
3952 for (link = REG_NOTES (this_insn);
3953 link; link = XEXP (link, 1))
3954 if (REG_NOTE_KIND (link) == REG_INC
3955 && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0)))
3956 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
3961 else if (GET_CODE (XEXP (x, 0)) == MEM)
3963 /* This is probably the result of a substitution, by eliminate_regs,
3964 of an equivalent address for a pseudo that was not allocated to a
3965 hard register. Verify that the specified address is valid and
3966 reload it into a register. */
3967 rtx tem = XEXP (x, 0);
3971 /* Since we know we are going to reload this item, don't decrement
3972 for the indirection level.
3974 Note that this is actually conservative: it would be slightly
3975 more efficient to use the value of SPILL_INDIRECT_LEVELS from
3977 find_reloads_address (GET_MODE (x), &XEXP (x, 0),
3978 XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0),
3979 operand, ind_levels);
3981 reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR,
3982 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3983 GET_MODE (x), VOIDmode, 0, 0, operand);
3984 reload_inc[reloadnum]
3985 = find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
3987 link = FIND_REG_INC_NOTE (this_insn, tem);
3989 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
3994 else if (code == MEM)
3996 /* This is probably the result of a substitution, by eliminate_regs,
3997 of an equivalent address for a pseudo that was not allocated to a
3998 hard register. Verify that the specified address is valid and reload
4001 Since we know we are going to reload this item, don't decrement
4002 for the indirection level.
4004 Note that this is actually conservative: it would be slightly more
4005 efficient to use the value of SPILL_INDIRECT_LEVELS from
4008 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
4009 operand, ind_levels);
4011 push_reload (*loc, NULL_RTX, loc, NULL_PTR,
4012 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4013 GET_MODE (x), VOIDmode, 0, 0, operand);
4016 else if (code == REG)
4018 register int regno = REGNO (x);
4020 if (reg_equiv_constant[regno] != 0)
4022 push_reload (reg_equiv_constant[regno], NULL_RTX, loc, NULL_PTR,
4023 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4024 GET_MODE (x), VOIDmode, 0, 0, operand);
4028 #if 0 /* This might screw code in reload1.c to delete prior output-reload
4029 that feeds this insn. */
4030 if (reg_equiv_mem[regno] != 0)
4032 push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR,
4033 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4034 GET_MODE (x), VOIDmode, 0, 0, operand);
4038 if (reg_equiv_address[regno] != 0)
4040 x = make_memloc (x, regno);
4041 find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0),
4042 operand, ind_levels);
4045 if (reg_renumber[regno] >= 0)
4046 regno = reg_renumber[regno];
4047 if ((regno >= FIRST_PSEUDO_REGISTER
4048 || !(context ? REGNO_OK_FOR_INDEX_P (regno)
4049 : REGNO_OK_FOR_BASE_P (regno))))
4051 push_reload (x, NULL_RTX, loc, NULL_PTR,
4052 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4053 GET_MODE (x), VOIDmode, 0, 0, operand);
4057 /* If a register appearing in an address is the subject of a CLOBBER
4058 in this insn, reload it into some other register to be safe.
4059 The CLOBBER is supposed to make the register unavailable
4060 from before this insn to after it. */
4061 if (regno_clobbered_p (regno, this_insn))
4063 push_reload (x, NULL_RTX, loc, NULL_PTR,
4064 context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4065 GET_MODE (x), VOIDmode, 0, 0, operand);
4071 register char *fmt = GET_RTX_FORMAT (code);
4073 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4076 find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i),
4077 operand, ind_levels);
4084 /* X, which is found at *LOC, is a part of an address that needs to be
4085 reloaded into a register of class CLASS. If X is a constant, or if
4086 X is a PLUS that contains a constant, check that the constant is a
4087 legitimate operand and that we are supposed to be able to load
4088 it into the register.
4090 If not, force the constant into memory and reload the MEM instead.
4092 MODE is the mode to use, in case X is an integer constant.
4094 NEEDED_FOR says which operand this reload is needed for.
4096 IND_LEVELS says how many levels of indirect addressing this machine
4100 find_reloads_address_part (x, loc, class, mode, needed_for, ind_levels)
4103 enum reg_class class;
4104 enum machine_mode mode;
4109 && (! LEGITIMATE_CONSTANT_P (x)
4110 || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS))
4112 rtx tem = x = force_const_mem (mode, x);
4113 find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4114 needed_for, ind_levels);
4117 else if (GET_CODE (x) == PLUS
4118 && CONSTANT_P (XEXP (x, 1))
4119 && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
4120 || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS))
4122 rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1));
4124 x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem);
4125 find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4126 needed_for, ind_levels);
4129 push_reload (x, NULL_RTX, loc, NULL_PTR, class,
4130 mode, VOIDmode, 0, 0, needed_for);
4133 /* Substitute into X the registers into which we have reloaded
4134 the things that need reloading. The array `replacements'
4135 says contains the locations of all pointers that must be changed
4136 and says what to replace them with.
4138 Return the rtx that X translates into; usually X, but modified. */
4145 for (i = 0; i < n_replacements; i++)
4147 register struct replacement *r = &replacements[i];
4148 register rtx reloadreg = reload_reg_rtx[r->what];
4151 /* Encapsulate RELOADREG so its machine mode matches what
4152 used to be there. */
4153 if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
4154 reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg));
4156 /* If we are putting this into a SUBREG and RELOADREG is a
4157 SUBREG, we would be making nested SUBREGs, so we have to fix
4158 this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */
4160 if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG)
4162 if (GET_MODE (*r->subreg_loc)
4163 == GET_MODE (SUBREG_REG (reloadreg)))
4164 *r->subreg_loc = SUBREG_REG (reloadreg);
4167 *r->where = SUBREG_REG (reloadreg);
4168 SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg);
4172 *r->where = reloadreg;
4174 /* If reload got no reg and isn't optional, something's wrong. */
4175 else if (! reload_optional[r->what])
4180 /* Make a copy of any replacements being done into X and move those copies
4181 to locations in Y, a copy of X. We only look at the highest level of
4185 copy_replacements (x, y)
4190 enum rtx_code code = GET_CODE (x);
4191 char *fmt = GET_RTX_FORMAT (code);
4192 struct replacement *r;
4194 /* We can't support X being a SUBREG because we might then need to know its
4195 location if something inside it was replaced. */
4199 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4201 for (j = 0; j < n_replacements; j++)
4203 if (replacements[j].subreg_loc == &XEXP (x, i))
4205 r = &replacements[n_replacements++];
4206 r->where = replacements[j].where;
4207 r->subreg_loc = &XEXP (y, i);
4208 r->what = replacements[j].what;
4209 r->mode = replacements[j].mode;
4211 else if (replacements[j].where == &XEXP (x, i))
4213 r = &replacements[n_replacements++];
4214 r->where = &XEXP (y, i);
4216 r->what = replacements[j].what;
4217 r->mode = replacements[j].mode;
4222 /* If LOC was scheduled to be replaced by something, return the replacement.
4223 Otherwise, return *LOC. */
4226 find_replacement (loc)
4229 struct replacement *r;
4231 for (r = &replacements[0]; r < &replacements[n_replacements]; r++)
4233 rtx reloadreg = reload_reg_rtx[r->what];
4235 if (reloadreg && r->where == loc)
4237 if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
4238 reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg));
4242 else if (reloadreg && r->subreg_loc == loc)
4244 /* RELOADREG must be either a REG or a SUBREG.
4246 ??? Is it actually still ever a SUBREG? If so, why? */
4248 if (GET_CODE (reloadreg) == REG)
4249 return gen_rtx (REG, GET_MODE (*loc),
4250 REGNO (reloadreg) + SUBREG_WORD (*loc));
4251 else if (GET_MODE (reloadreg) == GET_MODE (*loc))
4254 return gen_rtx (SUBREG, GET_MODE (*loc), SUBREG_REG (reloadreg),
4255 SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc));
4262 /* Return nonzero if register in range [REGNO, ENDREGNO)
4263 appears either explicitly or implicitly in X
4264 other than being stored into.
4266 References contained within the substructure at LOC do not count.
4267 LOC may be zero, meaning don't ignore anything.
4269 This is similar to refers_to_regno_p in rtlanal.c except that we
4270 look at equivalences for pseudos that didn't get hard registers. */
4273 refers_to_regno_for_reload_p (regno, endregno, x, loc)
4274 int regno, endregno;
4279 register RTX_CODE code;
4286 code = GET_CODE (x);
4293 /* If this is a pseudo, a hard register must not have been allocated.
4294 X must therefore either be a constant or be in memory. */
4295 if (i >= FIRST_PSEUDO_REGISTER)
4297 if (reg_equiv_memory_loc[i])
4298 return refers_to_regno_for_reload_p (regno, endregno,
4299 reg_equiv_memory_loc[i],
4302 if (reg_equiv_constant[i])
4308 return (endregno > i
4309 && regno < i + (i < FIRST_PSEUDO_REGISTER
4310 ? HARD_REGNO_NREGS (i, GET_MODE (x))
4314 /* If this is a SUBREG of a hard reg, we can see exactly which
4315 registers are being modified. Otherwise, handle normally. */
4316 if (GET_CODE (SUBREG_REG (x)) == REG
4317 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
4319 int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
4321 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
4322 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
4324 return endregno > inner_regno && regno < inner_endregno;
4330 if (&SET_DEST (x) != loc
4331 /* Note setting a SUBREG counts as referring to the REG it is in for
4332 a pseudo but not for hard registers since we can
4333 treat each word individually. */
4334 && ((GET_CODE (SET_DEST (x)) == SUBREG
4335 && loc != &SUBREG_REG (SET_DEST (x))
4336 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
4337 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
4338 && refers_to_regno_for_reload_p (regno, endregno,
4339 SUBREG_REG (SET_DEST (x)),
4341 || (GET_CODE (SET_DEST (x)) != REG
4342 && refers_to_regno_for_reload_p (regno, endregno,
4343 SET_DEST (x), loc))))
4346 if (code == CLOBBER || loc == &SET_SRC (x))
4352 /* X does not match, so try its subexpressions. */
4354 fmt = GET_RTX_FORMAT (code);
4355 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4357 if (fmt[i] == 'e' && loc != &XEXP (x, i))
4365 if (refers_to_regno_for_reload_p (regno, endregno,
4369 else if (fmt[i] == 'E')
4372 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4373 if (loc != &XVECEXP (x, i, j)
4374 && refers_to_regno_for_reload_p (regno, endregno,
4375 XVECEXP (x, i, j), loc))
4382 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
4383 we check if any register number in X conflicts with the relevant register
4384 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
4385 contains a MEM (we don't bother checking for memory addresses that can't
4386 conflict because we expect this to be a rare case.
4388 This function is similar to reg_overlap_mention_p in rtlanal.c except
4389 that we look at equivalences for pseudos that didn't get hard registers. */
4392 reg_overlap_mentioned_for_reload_p (x, in)
4395 int regno, endregno;
4397 if (GET_CODE (x) == SUBREG)
4399 regno = REGNO (SUBREG_REG (x));
4400 if (regno < FIRST_PSEUDO_REGISTER)
4401 regno += SUBREG_WORD (x);
4403 else if (GET_CODE (x) == REG)
4407 /* If this is a pseudo, it must not have been assigned a hard register.
4408 Therefore, it must either be in memory or be a constant. */
4410 if (regno >= FIRST_PSEUDO_REGISTER)
4412 if (reg_equiv_memory_loc[regno])
4413 return refers_to_mem_for_reload_p (in);
4414 else if (reg_equiv_constant[regno])
4419 else if (CONSTANT_P (x))
4421 else if (GET_CODE (x) == MEM)
4422 return refers_to_mem_for_reload_p (in);
4423 else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC
4424 || GET_CODE (x) == CC0)
4425 return reg_mentioned_p (x, in);
4429 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
4430 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
4432 return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR);
4435 /* Return nonzero if anything in X contains a MEM. Look also for pseudo
4439 refers_to_mem_for_reload_p (x)
4445 if (GET_CODE (x) == MEM)
4448 if (GET_CODE (x) == REG)
4449 return (REGNO (x) >= FIRST_PSEUDO_REGISTER
4450 && reg_equiv_memory_loc[REGNO (x)]);
4452 fmt = GET_RTX_FORMAT (GET_CODE (x));
4453 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4455 && (GET_CODE (XEXP (x, i)) == MEM
4456 || refers_to_mem_for_reload_p (XEXP (x, i))))
4464 /* [[This function is currently obsolete, now that volatility
4465 is represented by a special bit `volatil' so VOLATILE is never used;
4466 and UNCHANGING has never been brought into use.]]
4468 Alter X by eliminating all VOLATILE and UNCHANGING expressions.
4469 Each of them is replaced by its operand.
4470 Thus, (PLUS (VOLATILE (MEM (REG 5))) (CONST_INT 4))
4471 becomes (PLUS (MEM (REG 5)) (CONST_INT 4)).
4473 If X is itself a VOLATILE expression,
4474 we return the expression that should replace it
4475 but we do not modify X. */
4478 forget_volatility (x)
4481 enum rtx_code code = GET_CODE (x);
4484 register rtx value = 0;
4503 fmt = GET_RTX_FORMAT (code);
4504 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4507 XEXP (x, i) = forget_volatility (XEXP (x, i));
4511 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4512 XVECEXP (x, i, j) = forget_volatility (XVECEXP (x, i, j));
4521 /* Check the insns before INSN to see if there is a suitable register
4522 containing the same value as GOAL.
4523 If OTHER is -1, look for a register in class CLASS.
4524 Otherwise, just see if register number OTHER shares GOAL's value.
4526 Return an rtx for the register found, or zero if none is found.
4528 If RELOAD_REG_P is (short *)1,
4529 we reject any hard reg that appears in reload_reg_rtx
4530 because such a hard reg is also needed coming into this insn.
4532 If RELOAD_REG_P is any other nonzero value,
4533 it is a vector indexed by hard reg number
4534 and we reject any hard reg whose element in the vector is nonnegative
4535 as well as any that appears in reload_reg_rtx.
4537 If GOAL is zero, then GOALREG is a register number; we look
4538 for an equivalent for that register.
4540 MODE is the machine mode of the value we want an equivalence for.
4541 If GOAL is nonzero and not VOIDmode, then it must have mode MODE.
4543 This function is used by jump.c as well as in the reload pass.
4545 If GOAL is the sum of the stack pointer and a constant, we treat it
4546 as if it were a constant except that sp is required to be unchanging. */
4549 find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
4552 enum reg_class class;
4554 short *reload_reg_p;
4556 enum machine_mode mode;
4558 register rtx p = insn;
4559 rtx valtry, value, where;
4561 register int regno = -1;
4565 int goal_mem_addr_varies = 0;
4566 int need_stable_sp = 0;
4572 else if (GET_CODE (goal) == REG)
4573 regno = REGNO (goal);
4574 else if (GET_CODE (goal) == MEM)
4576 enum rtx_code code = GET_CODE (XEXP (goal, 0));
4577 if (MEM_VOLATILE_P (goal))
4579 if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT)
4581 /* An address with side effects must be reexecuted. */
4592 else if (CONSTANT_P (goal))
4594 else if (GET_CODE (goal) == PLUS
4595 && XEXP (goal, 0) == stack_pointer_rtx
4596 && CONSTANT_P (XEXP (goal, 1)))
4597 goal_const = need_stable_sp = 1;
4601 /* On some machines, certain regs must always be rejected
4602 because they don't behave the way ordinary registers do. */
4604 #ifdef OVERLAPPING_REGNO_P
4605 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4606 && OVERLAPPING_REGNO_P (regno))
4610 /* Scan insns back from INSN, looking for one that copies
4611 a value into or out of GOAL.
4612 Stop and give up if we reach a label. */
4617 if (p == 0 || GET_CODE (p) == CODE_LABEL)
4619 if (GET_CODE (p) == INSN
4620 /* If we don't want spill regs ... */
4621 && (! (reload_reg_p != 0 && reload_reg_p != (short *)1)
4622 /* ... then ignore insns introduced by reload; they aren't useful
4623 and can cause results in reload_as_needed to be different
4624 from what they were when calculating the need for spills.
4625 If we notice an input-reload insn here, we will reject it below,
4626 but it might hide a usable equivalent. That makes bad code.
4627 It may even abort: perhaps no reg was spilled for this insn
4628 because it was assumed we would find that equivalent. */
4629 || INSN_UID (p) < reload_first_uid))
4632 pat = single_set (p);
4633 /* First check for something that sets some reg equal to GOAL. */
4636 && true_regnum (SET_SRC (pat)) == regno
4637 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4640 && true_regnum (SET_DEST (pat)) == regno
4641 && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0)
4643 (goal_const && rtx_equal_p (SET_SRC (pat), goal)
4644 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4646 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0
4647 && rtx_renumbered_equal_p (goal, SET_SRC (pat)))
4649 && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0
4650 && rtx_renumbered_equal_p (goal, SET_DEST (pat)))
4651 /* If we are looking for a constant,
4652 and something equivalent to that constant was copied
4653 into a reg, we can use that reg. */
4654 || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
4656 && rtx_equal_p (XEXP (tem, 0), goal)
4657 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4658 || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
4660 && GET_CODE (SET_DEST (pat)) == REG
4661 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
4662 && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT
4663 && GET_CODE (goal) == CONST_INT
4664 && INTVAL (goal) == CONST_DOUBLE_LOW (XEXP (tem, 0))
4665 && (valtry = operand_subword (SET_DEST (pat), 0, 0,
4667 && (valueno = true_regnum (valtry)) >= 0)
4668 || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
4670 && GET_CODE (SET_DEST (pat)) == REG
4671 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
4672 && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT
4673 && GET_CODE (goal) == CONST_INT
4674 && INTVAL (goal) == CONST_DOUBLE_HIGH (XEXP (tem, 0))
4676 = operand_subword (SET_DEST (pat), 1, 0, VOIDmode))
4677 && (valueno = true_regnum (valtry)) >= 0)))
4680 : ((unsigned) valueno < FIRST_PSEUDO_REGISTER
4681 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
4691 /* We found a previous insn copying GOAL into a suitable other reg VALUE
4692 (or copying VALUE into GOAL, if GOAL is also a register).
4693 Now verify that VALUE is really valid. */
4695 /* VALUENO is the register number of VALUE; a hard register. */
4697 /* Don't try to re-use something that is killed in this insn. We want
4698 to be able to trust REG_UNUSED notes. */
4699 if (find_reg_note (where, REG_UNUSED, value))
4702 /* If we propose to get the value from the stack pointer or if GOAL is
4703 a MEM based on the stack pointer, we need a stable SP. */
4704 if (valueno == STACK_POINTER_REGNUM
4705 || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx,
4709 /* Reject VALUE if the copy-insn moved the wrong sort of datum. */
4710 if (GET_MODE (value) != mode)
4713 /* Reject VALUE if it was loaded from GOAL
4714 and is also a register that appears in the address of GOAL. */
4716 if (goal_mem && value == SET_DEST (PATTERN (where))
4717 && refers_to_regno_for_reload_p (valueno,
4719 + HARD_REGNO_NREGS (valueno, mode)),
4723 /* Reject registers that overlap GOAL. */
4725 if (!goal_mem && !goal_const
4726 && regno + HARD_REGNO_NREGS (regno, mode) > valueno
4727 && regno < valueno + HARD_REGNO_NREGS (valueno, mode))
4730 /* Reject VALUE if it is one of the regs reserved for reloads.
4731 Reload1 knows how to reuse them anyway, and it would get
4732 confused if we allocated one without its knowledge.
4733 (Now that insns introduced by reload are ignored above,
4734 this case shouldn't happen, but I'm not positive.) */
4736 if (reload_reg_p != 0 && reload_reg_p != (short *)1
4737 && reload_reg_p[valueno] >= 0)
4740 /* On some machines, certain regs must always be rejected
4741 because they don't behave the way ordinary registers do. */
4743 #ifdef OVERLAPPING_REGNO_P
4744 if (OVERLAPPING_REGNO_P (valueno))
4748 nregs = HARD_REGNO_NREGS (regno, mode);
4749 valuenregs = HARD_REGNO_NREGS (valueno, mode);
4751 /* Reject VALUE if it is a register being used for an input reload
4752 even if it is not one of those reserved. */
4754 if (reload_reg_p != 0)
4757 for (i = 0; i < n_reloads; i++)
4758 if (reload_reg_rtx[i] != 0 && reload_in[i])
4760 int regno1 = REGNO (reload_reg_rtx[i]);
4761 int nregs1 = HARD_REGNO_NREGS (regno1,
4762 GET_MODE (reload_reg_rtx[i]));
4763 if (regno1 < valueno + valuenregs
4764 && regno1 + nregs1 > valueno)
4770 goal_mem_addr_varies = rtx_addr_varies_p (goal);
4772 /* Now verify that the values of GOAL and VALUE remain unaltered
4773 until INSN is reached. */
4782 /* Don't trust the conversion past a function call
4783 if either of the two is in a call-clobbered register, or memory. */
4784 if (GET_CODE (p) == CALL_INSN
4785 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4786 && call_used_regs[regno])
4788 (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4789 && call_used_regs[valueno])
4795 #ifdef INSN_CLOBBERS_REGNO_P
4796 if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4797 && INSN_CLOBBERS_REGNO_P (p, valueno))
4798 || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4799 && INSN_CLOBBERS_REGNO_P (p, regno)))
4803 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
4805 /* If this insn P stores in either GOAL or VALUE, return 0.
4806 If GOAL is a memory ref and this insn writes memory, return 0.
4807 If GOAL is a memory ref and its address is not constant,
4808 and this insn P changes a register used in GOAL, return 0. */
4811 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
4813 register rtx dest = SET_DEST (pat);
4814 while (GET_CODE (dest) == SUBREG
4815 || GET_CODE (dest) == ZERO_EXTRACT
4816 || GET_CODE (dest) == SIGN_EXTRACT
4817 || GET_CODE (dest) == STRICT_LOW_PART)
4818 dest = XEXP (dest, 0);
4819 if (GET_CODE (dest) == REG)
4821 register int xregno = REGNO (dest);
4823 if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
4824 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
4827 if (xregno < regno + nregs && xregno + xnregs > regno)
4829 if (xregno < valueno + valuenregs
4830 && xregno + xnregs > valueno)
4832 if (goal_mem_addr_varies
4833 && reg_overlap_mentioned_for_reload_p (dest, goal))
4836 else if (goal_mem && GET_CODE (dest) == MEM
4837 && ! push_operand (dest, GET_MODE (dest)))
4839 else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
4842 else if (GET_CODE (pat) == PARALLEL)
4845 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
4847 register rtx v1 = XVECEXP (pat, 0, i);
4848 if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
4850 register rtx dest = SET_DEST (v1);
4851 while (GET_CODE (dest) == SUBREG
4852 || GET_CODE (dest) == ZERO_EXTRACT
4853 || GET_CODE (dest) == SIGN_EXTRACT
4854 || GET_CODE (dest) == STRICT_LOW_PART)
4855 dest = XEXP (dest, 0);
4856 if (GET_CODE (dest) == REG)
4858 register int xregno = REGNO (dest);
4860 if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
4861 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
4864 if (xregno < regno + nregs
4865 && xregno + xnregs > regno)
4867 if (xregno < valueno + valuenregs
4868 && xregno + xnregs > valueno)
4870 if (goal_mem_addr_varies
4871 && reg_overlap_mentioned_for_reload_p (dest,
4875 else if (goal_mem && GET_CODE (dest) == MEM
4876 && ! push_operand (dest, GET_MODE (dest)))
4878 else if (need_stable_sp
4879 && push_operand (dest, GET_MODE (dest)))
4886 /* If this insn auto-increments or auto-decrements
4887 either regno or valueno, return 0 now.
4888 If GOAL is a memory ref and its address is not constant,
4889 and this insn P increments a register used in GOAL, return 0. */
4893 for (link = REG_NOTES (p); link; link = XEXP (link, 1))
4894 if (REG_NOTE_KIND (link) == REG_INC
4895 && GET_CODE (XEXP (link, 0)) == REG)
4897 register int incno = REGNO (XEXP (link, 0));
4898 if (incno < regno + nregs && incno >= regno)
4900 if (incno < valueno + valuenregs && incno >= valueno)
4902 if (goal_mem_addr_varies
4903 && reg_overlap_mentioned_for_reload_p (XEXP (link, 0),
4913 /* Find a place where INCED appears in an increment or decrement operator
4914 within X, and return the amount INCED is incremented or decremented by.
4915 The value is always positive. */
4918 find_inc_amount (x, inced)
4921 register enum rtx_code code = GET_CODE (x);
4927 register rtx addr = XEXP (x, 0);
4928 if ((GET_CODE (addr) == PRE_DEC
4929 || GET_CODE (addr) == POST_DEC
4930 || GET_CODE (addr) == PRE_INC
4931 || GET_CODE (addr) == POST_INC)
4932 && XEXP (addr, 0) == inced)
4933 return GET_MODE_SIZE (GET_MODE (x));
4936 fmt = GET_RTX_FORMAT (code);
4937 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4941 register int tem = find_inc_amount (XEXP (x, i), inced);
4948 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4950 register int tem = find_inc_amount (XVECEXP (x, i, j), inced);
4960 /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */
4963 regno_clobbered_p (regno, insn)
4967 if (GET_CODE (PATTERN (insn)) == CLOBBER
4968 && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
4969 return REGNO (XEXP (PATTERN (insn), 0)) == regno;
4971 if (GET_CODE (PATTERN (insn)) == PARALLEL)
4973 int i = XVECLEN (PATTERN (insn), 0) - 1;
4977 rtx elt = XVECEXP (PATTERN (insn), 0, i);
4978 if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG
4979 && REGNO (XEXP (elt, 0)) == regno)
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