1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
43 #ifndef REGISTER_MOVE_COST
44 #define REGISTER_MOVE_COST(x, y) 2
47 static void init_reg_sets_1 PROTO((void));
48 static void init_reg_modes PROTO((void));
50 /* If we have auto-increment or auto-decrement and we can have secondary
51 reloads, we are not allowed to use classes requiring secondary
52 reloads for pseudos auto-incremented since reload can't handle it. */
55 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
56 #define FORBIDDEN_INC_DEC_CLASSES
60 /* Register tables used by many passes. */
62 /* Indexed by hard register number, contains 1 for registers
63 that are fixed use (stack pointer, pc, frame pointer, etc.).
64 These are the registers that cannot be used to allocate
65 a pseudo reg for general use. */
67 char fixed_regs[FIRST_PSEUDO_REGISTER];
69 /* Same info as a HARD_REG_SET. */
71 HARD_REG_SET fixed_reg_set;
73 /* Data for initializing the above. */
75 static char initial_fixed_regs[] = FIXED_REGISTERS;
77 /* Indexed by hard register number, contains 1 for registers
78 that are fixed use or are clobbered by function calls.
79 These are the registers that cannot be used to allocate
80 a pseudo reg whose life crosses calls unless we are able
81 to save/restore them across the calls. */
83 char call_used_regs[FIRST_PSEUDO_REGISTER];
85 /* Same info as a HARD_REG_SET. */
87 HARD_REG_SET call_used_reg_set;
89 /* HARD_REG_SET of registers we want to avoid caller saving. */
90 HARD_REG_SET losing_caller_save_reg_set;
92 /* Data for initializing the above. */
94 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
96 /* Indexed by hard register number, contains 1 for registers that are
97 fixed use or call used registers that cannot hold quantities across
98 calls even if we are willing to save and restore them. call fixed
99 registers are a subset of call used registers. */
101 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
103 /* The same info as a HARD_REG_SET. */
105 HARD_REG_SET call_fixed_reg_set;
107 /* Number of non-fixed registers. */
109 int n_non_fixed_regs;
111 /* Indexed by hard register number, contains 1 for registers
112 that are being used for global register decls.
113 These must be exempt from ordinary flow analysis
114 and are also considered fixed. */
116 char global_regs[FIRST_PSEUDO_REGISTER];
118 /* Table of register numbers in the order in which to try to use them. */
119 #ifdef REG_ALLOC_ORDER
120 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
125 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
127 /* The same information, but as an array of unsigned ints. We copy from
128 these unsigned ints to the table above. We do this so the tm.h files
129 do not have to be aware of the wordsize for machines with <= 64 regs. */
132 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
134 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
135 = REG_CLASS_CONTENTS;
137 /* For each reg class, number of regs it contains. */
139 int reg_class_size[N_REG_CLASSES];
141 /* For each reg class, table listing all the containing classes. */
143 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
145 /* For each reg class, table listing all the classes contained in it. */
147 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each pair of reg classes,
150 a largest reg class contained in their union. */
152 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
154 /* For each pair of reg classes,
155 the smallest reg class containing their union. */
157 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
159 /* Array containing all of the register names */
161 const char *reg_names[] = REGISTER_NAMES;
163 /* For each hard register, the widest mode object that it can contain.
164 This will be a MODE_INT mode if the register can hold integers. Otherwise
165 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
168 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
170 /* Maximum cost of moving from a register in one class to a register in
171 another class. Based on REGISTER_MOVE_COST. */
173 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
175 /* Similar, but here we don't have to move if the first index is a subset
176 of the second so in that case the cost is zero. */
178 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
180 /* Similar, but here we don't have to move if the first index is a superset
181 of the second so in that case the cost is zero. */
183 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
185 #ifdef FORBIDDEN_INC_DEC_CLASSES
187 /* These are the classes that regs which are auto-incremented or decremented
190 static int forbidden_inc_dec_class[N_REG_CLASSES];
192 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
195 static char *in_inc_dec;
197 #endif /* FORBIDDEN_INC_DEC_CLASSES */
199 #ifdef HAVE_SECONDARY_RELOADS
201 /* Sample MEM values for use by memory_move_secondary_cost. */
203 static rtx top_of_stack[MAX_MACHINE_MODE];
205 #endif /* HAVE_SECONDARY_RELOADS */
207 /* Linked list of reg_info structures allocated for reg_n_info array.
208 Grouping all of the allocated structures together in one lump
209 means only one call to bzero to clear them, rather than n smaller
211 struct reg_info_data {
212 struct reg_info_data *next; /* next set of reg_info structures */
213 size_t min_index; /* minimum index # */
214 size_t max_index; /* maximum index # */
215 char used_p; /* non-zero if this has been used previously */
216 reg_info data[1]; /* beginning of the reg_info data */
219 static struct reg_info_data *reg_info_head;
222 /* Function called only once to initialize the above data on reg usage.
223 Once this is done, various switches may override. */
230 /* First copy the register information from the initial int form into
233 for (i = 0; i < N_REG_CLASSES; i++)
235 CLEAR_HARD_REG_SET (reg_class_contents[i]);
237 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
238 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
239 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
240 SET_HARD_REG_BIT (reg_class_contents[i], j);
243 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
244 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
245 bzero (global_regs, sizeof global_regs);
247 /* Do any additional initialization regsets may need */
248 INIT_ONCE_REG_SET ();
251 /* After switches have been processed, which perhaps alter
252 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
257 register unsigned int i, j;
259 /* This macro allows the fixed or call-used registers
260 and the register classes to depend on target flags. */
262 #ifdef CONDITIONAL_REGISTER_USAGE
263 CONDITIONAL_REGISTER_USAGE;
266 /* Compute number of hard regs in each class. */
268 bzero ((char *) reg_class_size, sizeof reg_class_size);
269 for (i = 0; i < N_REG_CLASSES; i++)
270 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
271 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
274 /* Initialize the table of subunions.
275 reg_class_subunion[I][J] gets the largest-numbered reg-class
276 that is contained in the union of classes I and J. */
278 for (i = 0; i < N_REG_CLASSES; i++)
280 for (j = 0; j < N_REG_CLASSES; j++)
283 register /* Declare it register if it's a scalar. */
288 COPY_HARD_REG_SET (c, reg_class_contents[i]);
289 IOR_HARD_REG_SET (c, reg_class_contents[j]);
290 for (k = 0; k < N_REG_CLASSES; k++)
292 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
297 /* keep the largest subclass */ /* SPEE 900308 */
298 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
299 reg_class_contents[(int) reg_class_subunion[i][j]],
301 reg_class_subunion[i][j] = (enum reg_class) k;
308 /* Initialize the table of superunions.
309 reg_class_superunion[I][J] gets the smallest-numbered reg-class
310 containing the union of classes I and J. */
312 for (i = 0; i < N_REG_CLASSES; i++)
314 for (j = 0; j < N_REG_CLASSES; j++)
317 register /* Declare it register if it's a scalar. */
322 COPY_HARD_REG_SET (c, reg_class_contents[i]);
323 IOR_HARD_REG_SET (c, reg_class_contents[j]);
324 for (k = 0; k < N_REG_CLASSES; k++)
325 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
328 reg_class_superunion[i][j] = (enum reg_class) k;
332 /* Initialize the tables of subclasses and superclasses of each reg class.
333 First clear the whole table, then add the elements as they are found. */
335 for (i = 0; i < N_REG_CLASSES; i++)
337 for (j = 0; j < N_REG_CLASSES; j++)
339 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
340 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
344 for (i = 0; i < N_REG_CLASSES; i++)
346 if (i == (int) NO_REGS)
349 for (j = i + 1; j < N_REG_CLASSES; j++)
353 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
357 /* Reg class I is a subclass of J.
358 Add J to the table of superclasses of I. */
359 p = ®_class_superclasses[i][0];
360 while (*p != LIM_REG_CLASSES) p++;
361 *p = (enum reg_class) j;
362 /* Add I to the table of superclasses of J. */
363 p = ®_class_subclasses[j][0];
364 while (*p != LIM_REG_CLASSES) p++;
365 *p = (enum reg_class) i;
369 /* Initialize "constant" tables. */
371 CLEAR_HARD_REG_SET (fixed_reg_set);
372 CLEAR_HARD_REG_SET (call_used_reg_set);
373 CLEAR_HARD_REG_SET (call_fixed_reg_set);
375 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
377 n_non_fixed_regs = 0;
379 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
382 SET_HARD_REG_BIT (fixed_reg_set, i);
386 if (call_used_regs[i])
387 SET_HARD_REG_BIT (call_used_reg_set, i);
388 if (call_fixed_regs[i])
389 SET_HARD_REG_BIT (call_fixed_reg_set, i);
390 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
391 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
394 /* Initialize the move cost table. Find every subset of each class
395 and take the maximum cost of moving any subset to any other. */
397 for (i = 0; i < N_REG_CLASSES; i++)
398 for (j = 0; j < N_REG_CLASSES; j++)
400 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
401 enum reg_class *p1, *p2;
403 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
405 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
407 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
410 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
412 for (p2 = ®_class_subclasses[j][0];
413 *p2 != LIM_REG_CLASSES; p2++)
415 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
418 move_cost[i][j] = cost;
420 if (reg_class_subset_p (i, j))
421 may_move_in_cost[i][j] = 0;
423 may_move_in_cost[i][j] = cost;
425 if (reg_class_subset_p (j, i))
426 may_move_out_cost[i][j] = 0;
428 may_move_out_cost[i][j] = cost;
432 /* Compute the table of register modes.
433 These values are used to record death information for individual registers
434 (as opposed to a multi-register mode). */
441 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
443 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
445 /* If we couldn't find a valid mode, just use the previous mode.
446 ??? One situation in which we need to do this is on the mips where
447 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
448 to use DF mode for the even registers and VOIDmode for the odd
449 (for the cpu models where the odd ones are inaccessible). */
450 if (reg_raw_mode[i] == VOIDmode)
451 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
455 /* Finish initializing the register sets and
456 initialize the register modes. */
461 /* This finishes what was started by init_reg_sets, but couldn't be done
462 until after register usage was specified. */
467 #ifdef HAVE_SECONDARY_RELOADS
469 /* Make some fake stack-frame MEM references for use in
470 memory_move_secondary_cost. */
472 for (i = 0; i < MAX_MACHINE_MODE; i++)
473 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
474 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
479 #ifdef HAVE_SECONDARY_RELOADS
481 /* Compute extra cost of moving registers to/from memory due to reloads.
482 Only needed if secondary reloads are required for memory moves. */
485 memory_move_secondary_cost (mode, class, in)
486 enum machine_mode mode;
487 enum reg_class class;
490 enum reg_class altclass;
491 int partial_cost = 0;
492 /* We need a memory reference to feed to SECONDARY... macros. */
493 rtx mem = top_of_stack[(int) mode];
497 #ifdef SECONDARY_INPUT_RELOAD_CLASS
498 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
505 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
506 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
512 if (altclass == NO_REGS)
516 partial_cost = REGISTER_MOVE_COST (altclass, class);
518 partial_cost = REGISTER_MOVE_COST (class, altclass);
520 if (class == altclass)
521 /* This isn't simply a copy-to-temporary situation. Can't guess
522 what it is, so MEMORY_MOVE_COST really ought not to be calling
525 I'm tempted to put in an abort here, but returning this will
526 probably only give poor estimates, which is what we would've
527 had before this code anyways. */
530 /* Check if the secondary reload register will also need a
532 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
536 /* Return a machine mode that is legitimate for hard reg REGNO and large
537 enough to save nregs. If we can't find one, return VOIDmode. */
540 choose_hard_reg_mode (regno, nregs)
544 enum machine_mode found_mode = VOIDmode, mode;
546 /* We first look for the largest integer mode that can be validly
547 held in REGNO. If none, we look for the largest floating-point mode.
548 If we still didn't find a valid mode, try CCmode. */
550 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
552 mode = GET_MODE_WIDER_MODE (mode))
553 if (HARD_REGNO_NREGS (regno, mode) == nregs
554 && HARD_REGNO_MODE_OK (regno, mode))
557 if (found_mode != VOIDmode)
560 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
562 mode = GET_MODE_WIDER_MODE (mode))
563 if (HARD_REGNO_NREGS (regno, mode) == nregs
564 && HARD_REGNO_MODE_OK (regno, mode))
567 if (found_mode != VOIDmode)
570 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
571 && HARD_REGNO_MODE_OK (regno, CCmode))
574 /* We can't find a mode valid for this register. */
578 /* Specify the usage characteristics of the register named NAME.
579 It should be a fixed register if FIXED and a
580 call-used register if CALL_USED. */
583 fix_register (name, fixed, call_used)
585 int fixed, call_used;
589 /* Decode the name and update the primary form of
590 the register info. */
592 if ((i = decode_reg_name (name)) >= 0)
594 if ((i == STACK_POINTER_REGNUM
595 #ifdef HARD_FRAME_POINTER_REGNUM
596 || i == HARD_FRAME_POINTER_REGNUM
598 || i == FRAME_POINTER_REGNUM
601 && (fixed == 0 || call_used == 0))
603 static const char * const what_option[2][2] = {
604 { "call-saved", "call-used" },
605 { "no-such-option", "fixed" }};
607 error ("can't use '%s' as a %s register", name,
608 what_option[fixed][call_used]);
612 fixed_regs[i] = fixed;
613 call_used_regs[i] = call_used;
618 warning ("unknown register name: %s", name);
622 /* Mark register number I as global. */
630 warning ("register used for two global register variables");
634 if (call_used_regs[i] && ! fixed_regs[i])
635 warning ("call-clobbered register used for global register variable");
639 /* If already fixed, nothing else to do. */
643 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
646 SET_HARD_REG_BIT (fixed_reg_set, i);
647 SET_HARD_REG_BIT (call_used_reg_set, i);
648 SET_HARD_REG_BIT (call_fixed_reg_set, i);
651 /* Now the data and code for the `regclass' pass, which happens
652 just before local-alloc. */
654 /* The `costs' struct records the cost of using a hard register of each class
655 and of using memory for each pseudo. We use this data to set up
656 register class preferences. */
660 int cost[N_REG_CLASSES];
664 /* Record the cost of each class for each pseudo. */
666 static struct costs *costs;
668 /* Initialized once, and used to initialize cost values for each insn. */
670 static struct costs init_cost;
672 /* Record the same data by operand number, accumulated for each alternative
673 in an insn. The contribution to a pseudo is that of the minimum-cost
676 static struct costs op_costs[MAX_RECOG_OPERANDS];
678 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
679 This is available after `regclass' is run. */
681 static char *prefclass;
683 /* altclass[R] is a register class that we should use for allocating
684 pseudo number R if no register in the preferred class is available.
685 If no register in this class is available, memory is preferred.
687 It might appear to be more general to have a bitmask of classes here,
688 but since it is recommended that there be a class corresponding to the
689 union of most major pair of classes, that generality is not required.
691 This is available after `regclass' is run. */
693 static char *altclass;
695 /* Allocated buffers for prefclass and altclass. */
696 static char *prefclass_buffer;
697 static char *altclass_buffer;
699 /* Record the depth of loops that we are in. */
701 static int loop_depth;
703 /* Account for the fact that insns within a loop are executed very commonly,
704 but don't keep doing this as loops go too deep. */
706 static int loop_cost;
708 static rtx scan_one_insn PROTO((rtx, int));
709 static void dump_regclass PROTO((FILE *));
710 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
711 char *, const char **, rtx));
712 static int copy_cost PROTO((rtx, enum machine_mode,
713 enum reg_class, int));
714 static void record_address_regs PROTO((rtx, enum reg_class, int));
715 #ifdef FORBIDDEN_INC_DEC_CLASSES
716 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
718 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
720 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
721 This function is sometimes called before the info has been computed.
722 When that happens, just return GENERAL_REGS, which is innocuous. */
725 reg_preferred_class (regno)
730 return (enum reg_class) prefclass[regno];
734 reg_alternate_class (regno)
740 return (enum reg_class) altclass[regno];
743 /* Initialize some global data for this pass. */
750 init_cost.mem_cost = 10000;
751 for (i = 0; i < N_REG_CLASSES; i++)
752 init_cost.cost[i] = 10000;
754 /* This prevents dump_flow_info from losing if called
755 before regclass is run. */
759 /* Dump register costs. */
764 static const char *const reg_class_names[] = REG_CLASS_NAMES;
766 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
768 enum reg_class class;
771 fprintf (dump, ";; Register %i costs:", i);
772 for (class = 0; class < N_REG_CLASSES; class++)
773 fprintf (dump, " %s:%i", reg_class_names[(int) class],
774 costs[i].cost[class]);
775 fprintf (dump, " MEM:%i\n\n", costs[i].mem_cost);
781 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
782 time it would save code to put a certain register in a certain class.
783 PASS, when nonzero, inhibits some optimizations which need only be done
785 Return the last insn processed, so that the scan can be continued from
789 scan_one_insn (insn, pass)
793 enum rtx_code code = GET_CODE (insn);
794 enum rtx_code pat_code;
795 const char *constraints[MAX_RECOG_OPERANDS];
796 enum machine_mode modes[MAX_RECOG_OPERANDS];
797 char subreg_changes_size[MAX_RECOG_OPERANDS];
801 /* Show that an insn inside a loop is likely to be executed three
802 times more than insns outside a loop. This is much more aggressive
803 than the assumptions made elsewhere and is being tried as an
808 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
809 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
810 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
811 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
816 if (GET_RTX_CLASS (code) != 'i')
819 pat_code = GET_CODE (PATTERN (insn));
821 || pat_code == CLOBBER
822 || pat_code == ASM_INPUT
823 || pat_code == ADDR_VEC
824 || pat_code == ADDR_DIFF_VEC)
827 set = single_set (insn);
830 for (i = 0; i < recog_data.n_operands; i++)
832 constraints[i] = recog_data.constraints[i];
833 modes[i] = recog_data.operand_mode[i];
835 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
837 /* If this insn loads a parameter from its stack slot, then
838 it represents a savings, rather than a cost, if the
839 parameter is stored in memory. Record this fact. */
841 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
842 && GET_CODE (SET_SRC (set)) == MEM
843 && (note = find_reg_note (insn, REG_EQUIV,
845 && GET_CODE (XEXP (note, 0)) == MEM)
847 costs[REGNO (SET_DEST (set))].mem_cost
848 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
851 record_address_regs (XEXP (SET_SRC (set), 0),
852 BASE_REG_CLASS, loop_cost * 2);
856 /* Improve handling of two-address insns such as
857 (set X (ashift CONST Y)) where CONST must be made to
858 match X. Change it into two insns: (set X CONST)
859 (set X (ashift X Y)). If we left this for reloading, it
860 would probably get three insns because X and Y might go
861 in the same place. This prevents X and Y from receiving
864 We can only do this if the modes of operands 0 and 1
865 (which might not be the same) are tieable and we only need
866 do this during our first pass. */
868 if (pass == 0 && optimize
869 && recog_data.n_operands >= 3
870 && recog_data.constraints[1][0] == '0'
871 && recog_data.constraints[1][1] == 0
872 && CONSTANT_P (recog_data.operand[1])
873 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
874 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
875 && GET_CODE (recog_data.operand[0]) == REG
876 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
877 recog_data.operand_mode[1]))
879 rtx previnsn = prev_real_insn (insn);
881 = gen_lowpart (recog_data.operand_mode[1],
882 recog_data.operand[0]);
884 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
886 /* If this insn was the start of a basic block,
887 include the new insn in that block.
888 We need not check for code_label here;
889 while a basic block can start with a code_label,
890 INSN could not be at the beginning of that block. */
891 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
894 for (b = 0; b < n_basic_blocks; b++)
895 if (insn == BLOCK_HEAD (b))
896 BLOCK_HEAD (b) = newinsn;
899 /* This makes one more setting of new insns's dest. */
900 REG_N_SETS (REGNO (recog_data.operand[0]))++;
902 *recog_data.operand_loc[1] = recog_data.operand[0];
903 for (i = recog_data.n_dups - 1; i >= 0; i--)
904 if (recog_data.dup_num[i] == 1)
905 *recog_data.dup_loc[i] = recog_data.operand[0];
907 return PREV_INSN (newinsn);
910 /* If we get here, we are set up to record the costs of all the
911 operands for this insn. Start by initializing the costs.
912 Then handle any address registers. Finally record the desired
913 classes for any pseudos, doing it twice if some pair of
914 operands are commutative. */
916 for (i = 0; i < recog_data.n_operands; i++)
918 op_costs[i] = init_cost;
920 if (GET_CODE (recog_data.operand[i]) == SUBREG)
922 rtx inner = SUBREG_REG (recog_data.operand[i]);
923 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
924 subreg_changes_size[i] = 1;
925 recog_data.operand[i] = inner;
928 if (GET_CODE (recog_data.operand[i]) == MEM)
929 record_address_regs (XEXP (recog_data.operand[i], 0),
930 BASE_REG_CLASS, loop_cost * 2);
931 else if (constraints[i][0] == 'p')
932 record_address_regs (recog_data.operand[i],
933 BASE_REG_CLASS, loop_cost * 2);
936 /* Check for commutative in a separate loop so everything will
937 have been initialized. We must do this even if one operand
938 is a constant--see addsi3 in m68k.md. */
940 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
941 if (constraints[i][0] == '%')
943 const char *xconstraints[MAX_RECOG_OPERANDS];
946 /* Handle commutative operands by swapping the constraints.
947 We assume the modes are the same. */
949 for (j = 0; j < recog_data.n_operands; j++)
950 xconstraints[j] = constraints[j];
952 xconstraints[i] = constraints[i+1];
953 xconstraints[i+1] = constraints[i];
954 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
955 recog_data.operand, modes, subreg_changes_size,
959 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
960 recog_data.operand, modes, subreg_changes_size,
963 /* Now add the cost for each operand to the total costs for
966 for (i = 0; i < recog_data.n_operands; i++)
967 if (GET_CODE (recog_data.operand[i]) == REG
968 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
970 int regno = REGNO (recog_data.operand[i]);
971 struct costs *p = &costs[regno], *q = &op_costs[i];
973 p->mem_cost += q->mem_cost * loop_cost;
974 for (j = 0; j < N_REG_CLASSES; j++)
975 p->cost[j] += q->cost[j] * loop_cost;
981 /* This is a pass of the compiler that scans all instructions
982 and calculates the preferred class for each pseudo-register.
983 This information can be accessed later by calling `reg_preferred_class'.
984 This pass comes just before local register allocation. */
987 regclass (f, nregs, dump)
998 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1000 #ifdef FORBIDDEN_INC_DEC_CLASSES
1002 in_inc_dec = (char *) xmalloc (nregs);
1004 /* Initialize information about which register classes can be used for
1005 pseudos that are auto-incremented or auto-decremented. It would
1006 seem better to put this in init_reg_sets, but we need to be able
1007 to allocate rtx, which we can't do that early. */
1009 for (i = 0; i < N_REG_CLASSES; i++)
1011 rtx r = gen_rtx_REG (VOIDmode, 0);
1012 enum machine_mode m;
1015 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1016 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1020 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1021 m = (enum machine_mode) ((int) m + 1))
1022 if (HARD_REGNO_MODE_OK (j, m))
1026 /* If a register is not directly suitable for an
1027 auto-increment or decrement addressing mode and
1028 requires secondary reloads, disallow its class from
1029 being used in such addresses. */
1032 #ifdef SECONDARY_RELOAD_CLASS
1033 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1036 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1037 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1040 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1041 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1046 && ! auto_inc_dec_reg_p (r, m))
1047 forbidden_inc_dec_class[i] = 1;
1051 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1053 /* Normally we scan the insns once and determine the best class to use for
1054 each register. However, if -fexpensive_optimizations are on, we do so
1055 twice, the second time using the tentative best classes to guide the
1058 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1060 /* Zero out our accumulation of the cost of each class for each reg. */
1062 bzero ((char *) costs, nregs * sizeof (struct costs));
1064 #ifdef FORBIDDEN_INC_DEC_CLASSES
1065 bzero (in_inc_dec, nregs);
1068 loop_depth = 0, loop_cost = 1;
1070 /* Scan the instructions and record each time it would
1071 save code to put a certain register in a certain class. */
1073 for (insn = f; insn; insn = NEXT_INSN (insn))
1075 insn = scan_one_insn (insn, pass);
1078 /* Now for each register look at how desirable each class is
1079 and find which class is preferred. Store that in
1080 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1081 class any of whose registers is better than memory. */
1085 prefclass = prefclass_buffer;
1086 altclass = altclass_buffer;
1089 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1091 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1092 enum reg_class best = ALL_REGS, alt = NO_REGS;
1093 /* This is an enum reg_class, but we call it an int
1094 to save lots of casts. */
1096 register struct costs *p = &costs[i];
1098 for (class = (int) ALL_REGS - 1; class > 0; class--)
1100 /* Ignore classes that are too small for this operand or
1101 invalid for a operand that was auto-incremented. */
1102 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1103 > reg_class_size[class]
1104 #ifdef FORBIDDEN_INC_DEC_CLASSES
1105 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1109 else if (p->cost[class] < best_cost)
1111 best_cost = p->cost[class];
1112 best = (enum reg_class) class;
1114 else if (p->cost[class] == best_cost)
1115 best = reg_class_subunion[(int)best][class];
1118 /* Record the alternate register class; i.e., a class for which
1119 every register in it is better than using memory. If adding a
1120 class would make a smaller class (i.e., no union of just those
1121 classes exists), skip that class. The major unions of classes
1122 should be provided as a register class. Don't do this if we
1123 will be doing it again later. */
1125 if (pass == 1 || ! flag_expensive_optimizations)
1126 for (class = 0; class < N_REG_CLASSES; class++)
1127 if (p->cost[class] < p->mem_cost
1128 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1129 > reg_class_size[(int) alt])
1130 #ifdef FORBIDDEN_INC_DEC_CLASSES
1131 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1134 alt = reg_class_subunion[(int) alt][class];
1136 /* If we don't add any classes, nothing to try. */
1140 /* We cast to (int) because (char) hits bugs in some compilers. */
1141 prefclass[i] = (int) best;
1142 altclass[i] = (int) alt;
1147 dump_regclass (dump);
1148 #ifdef FORBIDDEN_INC_DEC_CLASSES
1154 /* Record the cost of using memory or registers of various classes for
1155 the operands in INSN.
1157 N_ALTS is the number of alternatives.
1159 N_OPS is the number of operands.
1161 OPS is an array of the operands.
1163 MODES are the modes of the operands, in case any are VOIDmode.
1165 CONSTRAINTS are the constraints to use for the operands. This array
1166 is modified by this procedure.
1168 This procedure works alternative by alternative. For each alternative
1169 we assume that we will be able to allocate all pseudos to their ideal
1170 register class and calculate the cost of using that alternative. Then
1171 we compute for each operand that is a pseudo-register, the cost of
1172 having the pseudo allocated to each register class and using it in that
1173 alternative. To this cost is added the cost of the alternative.
1175 The cost of each class for this insn is its lowest cost among all the
1179 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1184 enum machine_mode *modes;
1185 char *subreg_changes_size;
1186 const char **constraints;
1193 /* Process each alternative, each time minimizing an operand's cost with
1194 the cost for each operand in that alternative. */
1196 for (alt = 0; alt < n_alts; alt++)
1198 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1201 enum reg_class classes[MAX_RECOG_OPERANDS];
1202 int allows_mem[MAX_RECOG_OPERANDS];
1205 for (i = 0; i < n_ops; i++)
1207 const char *p = constraints[i];
1209 enum machine_mode mode = modes[i];
1210 int allows_addr = 0;
1214 /* Initially show we know nothing about the register class. */
1215 classes[i] = NO_REGS;
1218 /* If this operand has no constraints at all, we can conclude
1219 nothing about it since anything is valid. */
1223 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1224 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1229 /* If this alternative is only relevant when this operand
1230 matches a previous operand, we do different things depending
1231 on whether this operand is a pseudo-reg or not. We must process
1232 any modifiers for the operand before we can make this test. */
1234 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1237 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1239 /* Copy class and whether memory is allowed from the matching
1240 alternative. Then perform any needed cost computations
1241 and/or adjustments. */
1243 classes[i] = classes[j];
1244 allows_mem[i] = allows_mem[j];
1246 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1248 /* If this matches the other operand, we have no added
1250 if (rtx_equal_p (ops[j], op))
1253 /* If we can put the other operand into a register, add to
1254 the cost of this alternative the cost to copy this
1255 operand to the register used for the other operand. */
1257 else if (classes[j] != NO_REGS)
1258 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1260 else if (GET_CODE (ops[j]) != REG
1261 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1263 /* This op is a pseudo but the one it matches is not. */
1265 /* If we can't put the other operand into a register, this
1266 alternative can't be used. */
1268 if (classes[j] == NO_REGS)
1271 /* Otherwise, add to the cost of this alternative the cost
1272 to copy the other operand to the register used for this
1276 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1280 /* The costs of this operand are not the same as the other
1281 operand since move costs are not symmetric. Moreover,
1282 if we cannot tie them, this alternative needs to do a
1283 copy, which is one instruction. */
1285 struct costs *pp = &this_op_costs[i];
1287 for (class = 0; class < N_REG_CLASSES; class++)
1289 = (recog_data.operand_type[i] == OP_IN
1290 ? may_move_in_cost[class][(int) classes[i]]
1291 : may_move_out_cost[(int) classes[i]][class]);
1293 /* If the alternative actually allows memory, make things
1294 a bit cheaper since we won't need an extra insn to
1298 = (MEMORY_MOVE_COST (mode, classes[i],
1299 recog_data.operand_type[i] == OP_IN)
1302 /* If we have assigned a class to this register in our
1303 first pass, add a cost to this alternative corresponding
1304 to what we would add if this register were not in the
1305 appropriate class. */
1309 += (may_move_in_cost[(unsigned char) prefclass[REGNO (op)]]
1310 [(int) classes[i]]);
1312 if (REGNO (ops[i]) != REGNO (ops[j])
1313 && ! find_reg_note (insn, REG_DEAD, op))
1316 /* This is in place of ordinary cost computation
1317 for this operand, so skip to the end of the
1318 alternative (should be just one character). */
1319 while (*p && *p++ != ',')
1327 /* Scan all the constraint letters. See if the operand matches
1328 any of the constraints. Collect the valid register classes
1329 and see if this operand accepts memory. */
1331 while (*p && (c = *p++) != ',')
1335 /* Ignore the next letter for this pass. */
1341 case '!': case '#': case '&':
1342 case '0': case '1': case '2': case '3': case '4':
1343 case '5': case '6': case '7': case '8': case '9':
1348 win = address_operand (op, GET_MODE (op));
1349 /* We know this operand is an address, so we want it to be
1350 allocated to a register that can be the base of an
1351 address, ie BASE_REG_CLASS. */
1353 = reg_class_subunion[(int) classes[i]]
1354 [(int) BASE_REG_CLASS];
1357 case 'm': case 'o': case 'V':
1358 /* It doesn't seem worth distinguishing between offsettable
1359 and non-offsettable addresses here. */
1361 if (GET_CODE (op) == MEM)
1366 if (GET_CODE (op) == MEM
1367 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1368 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1373 if (GET_CODE (op) == MEM
1374 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1375 || GET_CODE (XEXP (op, 0)) == POST_INC))
1380 #ifndef REAL_ARITHMETIC
1381 /* Match any floating double constant, but only if
1382 we can examine the bits of it reliably. */
1383 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1384 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1385 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1388 if (GET_CODE (op) == CONST_DOUBLE)
1393 if (GET_CODE (op) == CONST_DOUBLE)
1399 if (GET_CODE (op) == CONST_DOUBLE
1400 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1405 if (GET_CODE (op) == CONST_INT
1406 || (GET_CODE (op) == CONST_DOUBLE
1407 && GET_MODE (op) == VOIDmode))
1411 #ifdef LEGITIMATE_PIC_OPERAND_P
1412 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1419 if (GET_CODE (op) == CONST_INT
1420 || (GET_CODE (op) == CONST_DOUBLE
1421 && GET_MODE (op) == VOIDmode))
1433 if (GET_CODE (op) == CONST_INT
1434 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1442 #ifdef EXTRA_CONSTRAINT
1448 if (EXTRA_CONSTRAINT (op, c))
1454 if (GET_CODE (op) == MEM
1456 #ifdef LEGITIMATE_PIC_OPERAND_P
1457 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1464 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1469 = reg_class_subunion[(int) classes[i]]
1470 [(int) REG_CLASS_FROM_LETTER (c)];
1475 #ifdef CLASS_CANNOT_CHANGE_SIZE
1476 /* If we noted a subreg earlier, and the selected class is a
1477 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1478 if (subreg_changes_size[i]
1479 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1481 == CLASS_CANNOT_CHANGE_SIZE))
1482 classes[i] = NO_REGS;
1485 /* How we account for this operand now depends on whether it is a
1486 pseudo register or not. If it is, we first check if any
1487 register classes are valid. If not, we ignore this alternative,
1488 since we want to assume that all pseudos get allocated for
1489 register preferencing. If some register class is valid, compute
1490 the costs of moving the pseudo into that class. */
1492 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1494 if (classes[i] == NO_REGS)
1496 /* We must always fail if the operand is a REG, but
1497 we did not find a suitable class.
1499 Otherwise we may perform an uninitialized read
1500 from this_op_costs after the `continue' statement
1506 struct costs *pp = &this_op_costs[i];
1508 for (class = 0; class < N_REG_CLASSES; class++)
1510 = (recog_data.operand_type[i] == OP_IN
1511 ? may_move_in_cost[class][(int) classes[i]]
1512 : may_move_out_cost[(int) classes[i]][class]);
1514 /* If the alternative actually allows memory, make things
1515 a bit cheaper since we won't need an extra insn to
1519 = (MEMORY_MOVE_COST (mode, classes[i],
1520 recog_data.operand_type[i] == OP_IN)
1523 /* If we have assigned a class to this register in our
1524 first pass, add a cost to this alternative corresponding
1525 to what we would add if this register were not in the
1526 appropriate class. */
1530 += (may_move_in_cost[(unsigned char) prefclass[REGNO (op)]]
1531 [(int) classes[i]]);
1535 /* Otherwise, if this alternative wins, either because we
1536 have already determined that or if we have a hard register of
1537 the proper class, there is no cost for this alternative. */
1540 || (GET_CODE (op) == REG
1541 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1544 /* If registers are valid, the cost of this alternative includes
1545 copying the object to and/or from a register. */
1547 else if (classes[i] != NO_REGS)
1549 if (recog_data.operand_type[i] != OP_OUT)
1550 alt_cost += copy_cost (op, mode, classes[i], 1);
1552 if (recog_data.operand_type[i] != OP_IN)
1553 alt_cost += copy_cost (op, mode, classes[i], 0);
1556 /* The only other way this alternative can be used is if this is a
1557 constant that could be placed into memory. */
1559 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1560 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1568 /* Finally, update the costs with the information we've calculated
1569 about this alternative. */
1571 for (i = 0; i < n_ops; i++)
1572 if (GET_CODE (ops[i]) == REG
1573 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1575 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1576 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1578 pp->mem_cost = MIN (pp->mem_cost,
1579 (qq->mem_cost + alt_cost) * scale);
1581 for (class = 0; class < N_REG_CLASSES; class++)
1582 pp->cost[class] = MIN (pp->cost[class],
1583 (qq->cost[class] + alt_cost) * scale);
1587 /* If this insn is a single set copying operand 1 to operand 0
1588 and one is a pseudo with the other a hard reg that is in its
1589 own register class, set the cost of that register class to -1. */
1591 if ((set = single_set (insn)) != 0
1592 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1593 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1594 for (i = 0; i <= 1; i++)
1595 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1597 int regno = REGNO (ops[!i]);
1598 enum machine_mode mode = GET_MODE (ops[!i]);
1602 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1603 && (reg_class_size[(unsigned char) prefclass[regno]]
1604 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1605 op_costs[i].cost[(unsigned char) prefclass[regno]] = -1;
1606 else if (regno < FIRST_PSEUDO_REGISTER)
1607 for (class = 0; class < N_REG_CLASSES; class++)
1608 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1609 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1611 if (reg_class_size[class] == 1)
1612 op_costs[i].cost[class] = -1;
1615 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1617 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1621 if (nr == HARD_REGNO_NREGS(regno,mode))
1622 op_costs[i].cost[class] = -1;
1628 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1629 TO_P is zero) a register of class CLASS in mode MODE.
1631 X must not be a pseudo. */
1634 copy_cost (x, mode, class, to_p)
1636 enum machine_mode mode;
1637 enum reg_class class;
1640 #ifdef HAVE_SECONDARY_RELOADS
1641 enum reg_class secondary_class = NO_REGS;
1644 /* If X is a SCRATCH, there is actually nothing to move since we are
1645 assuming optimal allocation. */
1647 if (GET_CODE (x) == SCRATCH)
1650 /* Get the class we will actually use for a reload. */
1651 class = PREFERRED_RELOAD_CLASS (x, class);
1653 #ifdef HAVE_SECONDARY_RELOADS
1654 /* If we need a secondary reload (we assume here that we are using
1655 the secondary reload as an intermediate, not a scratch register), the
1656 cost is that to load the input into the intermediate register, then
1657 to copy them. We use a special value of TO_P to avoid recursion. */
1659 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1661 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1664 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1666 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1669 if (secondary_class != NO_REGS)
1670 return (move_cost[(int) secondary_class][(int) class]
1671 + copy_cost (x, mode, secondary_class, 2));
1672 #endif /* HAVE_SECONDARY_RELOADS */
1674 /* For memory, use the memory move cost, for (hard) registers, use the
1675 cost to move between the register classes, and use 2 for everything
1676 else (constants). */
1678 if (GET_CODE (x) == MEM || class == NO_REGS)
1679 return MEMORY_MOVE_COST (mode, class, to_p);
1681 else if (GET_CODE (x) == REG)
1682 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1685 /* If this is a constant, we may eventually want to call rtx_cost here. */
1689 /* Record the pseudo registers we must reload into hard registers
1690 in a subexpression of a memory address, X.
1692 CLASS is the class that the register needs to be in and is either
1693 BASE_REG_CLASS or INDEX_REG_CLASS.
1695 SCALE is twice the amount to multiply the cost by (it is twice so we
1696 can represent half-cost adjustments). */
1699 record_address_regs (x, class, scale)
1701 enum reg_class class;
1704 register enum rtx_code code = GET_CODE (x);
1717 /* When we have an address that is a sum,
1718 we must determine whether registers are "base" or "index" regs.
1719 If there is a sum of two registers, we must choose one to be
1720 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1721 to make a good choice most of the time. We only need to do this
1722 on machines that can have two registers in an address and where
1723 the base and index register classes are different.
1725 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1726 that seems bogus since it should only be set when we are sure
1727 the register is being used as a pointer. */
1730 rtx arg0 = XEXP (x, 0);
1731 rtx arg1 = XEXP (x, 1);
1732 register enum rtx_code code0 = GET_CODE (arg0);
1733 register enum rtx_code code1 = GET_CODE (arg1);
1735 /* Look inside subregs. */
1736 if (code0 == SUBREG)
1737 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1738 if (code1 == SUBREG)
1739 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1741 /* If this machine only allows one register per address, it must
1742 be in the first operand. */
1744 if (MAX_REGS_PER_ADDRESS == 1)
1745 record_address_regs (arg0, class, scale);
1747 /* If index and base registers are the same on this machine, just
1748 record registers in any non-constant operands. We assume here,
1749 as well as in the tests below, that all addresses are in
1752 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1754 record_address_regs (arg0, class, scale);
1755 if (! CONSTANT_P (arg1))
1756 record_address_regs (arg1, class, scale);
1759 /* If the second operand is a constant integer, it doesn't change
1760 what class the first operand must be. */
1762 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1763 record_address_regs (arg0, class, scale);
1765 /* If the second operand is a symbolic constant, the first operand
1766 must be an index register. */
1768 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1769 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1771 /* If both operands are registers but one is already a hard register
1772 of index or base class, give the other the class that the hard
1775 #ifdef REG_OK_FOR_BASE_P
1776 else if (code0 == REG && code1 == REG
1777 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1778 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1779 record_address_regs (arg1,
1780 REG_OK_FOR_BASE_P (arg0)
1781 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1783 else if (code0 == REG && code1 == REG
1784 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1785 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1786 record_address_regs (arg0,
1787 REG_OK_FOR_BASE_P (arg1)
1788 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1792 /* If one operand is known to be a pointer, it must be the base
1793 with the other operand the index. Likewise if the other operand
1796 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1799 record_address_regs (arg0, BASE_REG_CLASS, scale);
1800 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1802 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1805 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1806 record_address_regs (arg1, BASE_REG_CLASS, scale);
1809 /* Otherwise, count equal chances that each might be a base
1810 or index register. This case should be rare. */
1814 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1815 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1816 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1817 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1826 /* Double the importance of a pseudo register that is incremented
1827 or decremented, since it would take two extra insns
1828 if it ends up in the wrong place. If the operand is a pseudo,
1829 show it is being used in an INC_DEC context. */
1831 #ifdef FORBIDDEN_INC_DEC_CLASSES
1832 if (GET_CODE (XEXP (x, 0)) == REG
1833 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1834 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1837 record_address_regs (XEXP (x, 0), class, 2 * scale);
1842 register struct costs *pp = &costs[REGNO (x)];
1845 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1847 for (i = 0; i < N_REG_CLASSES; i++)
1848 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1854 register const char *fmt = GET_RTX_FORMAT (code);
1856 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1858 record_address_regs (XEXP (x, i), class, scale);
1863 #ifdef FORBIDDEN_INC_DEC_CLASSES
1865 /* Return 1 if REG is valid as an auto-increment memory reference
1866 to an object of MODE. */
1869 auto_inc_dec_reg_p (reg, mode)
1871 enum machine_mode mode;
1873 if (HAVE_POST_INCREMENT
1874 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1877 if (HAVE_POST_DECREMENT
1878 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1881 if (HAVE_PRE_INCREMENT
1882 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1885 if (HAVE_PRE_DECREMENT
1886 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1893 static short *renumber = (short *)0;
1894 static size_t regno_allocated = 0;
1896 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1897 reg_scan and flow_analysis that are indexed by the register number. If
1898 NEW_P is non zero, initialize all of the registers, otherwise only
1899 initialize the new registers allocated. The same table is kept from
1900 function to function, only reallocating it when we need more room. If
1901 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1904 allocate_reg_info (num_regs, new_p, renumber_p)
1910 size_t size_renumber;
1911 size_t min = (new_p) ? 0 : reg_n_max;
1912 struct reg_info_data *reg_data;
1913 struct reg_info_data *reg_next;
1915 if (num_regs > regno_allocated)
1917 size_t old_allocated = regno_allocated;
1919 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1920 size_renumber = regno_allocated * sizeof (short);
1924 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1925 renumber = (short *) xmalloc (size_renumber);
1926 prefclass_buffer = (char *) xmalloc (regno_allocated);
1927 altclass_buffer = (char *) xmalloc (regno_allocated);
1932 VARRAY_GROW (reg_n_info, regno_allocated);
1934 if (new_p) /* if we're zapping everything, no need to realloc */
1936 free ((char *)renumber);
1937 free ((char *)prefclass_buffer);
1938 free ((char *)altclass_buffer);
1939 renumber = (short *) xmalloc (size_renumber);
1940 prefclass_buffer = (char *) xmalloc (regno_allocated);
1941 altclass_buffer = (char *) xmalloc (regno_allocated);
1946 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1947 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1950 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1955 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1956 + sizeof (struct reg_info_data) - sizeof (reg_info);
1957 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1958 reg_data->min_index = old_allocated;
1959 reg_data->max_index = regno_allocated - 1;
1960 reg_data->next = reg_info_head;
1961 reg_info_head = reg_data;
1964 reg_n_max = num_regs;
1967 /* Loop through each of the segments allocated for the actual
1968 reg_info pages, and set up the pointers, zero the pages, etc. */
1969 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1971 size_t min_index = reg_data->min_index;
1972 size_t max_index = reg_data->max_index;
1974 reg_next = reg_data->next;
1975 if (min <= max_index)
1977 size_t max = max_index;
1978 size_t local_min = min - min_index;
1981 if (min < min_index)
1983 if (!reg_data->used_p) /* page just allocated with calloc */
1984 reg_data->used_p = 1; /* no need to zero */
1986 bzero ((char *) ®_data->data[local_min],
1987 sizeof (reg_info) * (max - min_index - local_min + 1));
1989 for (i = min_index+local_min; i <= max; i++)
1991 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1992 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1994 prefclass_buffer[i] = (char) NO_REGS;
1995 altclass_buffer[i] = (char) NO_REGS;
2001 /* If {pref,alt}class have already been allocated, update the pointers to
2002 the newly realloced ones. */
2005 prefclass = prefclass_buffer;
2006 altclass = altclass_buffer;
2010 reg_renumber = renumber;
2012 /* Tell the regset code about the new number of registers */
2013 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2016 /* Free up the space allocated by allocate_reg_info. */
2022 struct reg_info_data *reg_data;
2023 struct reg_info_data *reg_next;
2025 VARRAY_FREE (reg_n_info);
2026 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2028 reg_next = reg_data->next;
2029 free ((char *)reg_data);
2032 free (prefclass_buffer);
2033 free (altclass_buffer);
2034 prefclass_buffer = (char *)0;
2035 altclass_buffer = (char *)0;
2036 reg_info_head = (struct reg_info_data *)0;
2037 renumber = (short *)0;
2039 regno_allocated = 0;
2043 /* This is the `regscan' pass of the compiler, run just before cse
2044 and again just before loop.
2046 It finds the first and last use of each pseudo-register
2047 and records them in the vectors regno_first_uid, regno_last_uid
2048 and counts the number of sets in the vector reg_n_sets.
2050 REPEAT is nonzero the second time this is called. */
2052 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2053 Always at least 3, since the combiner could put that many together
2054 and we want this to remain correct for all the remaining passes. */
2059 reg_scan (f, nregs, repeat)
2066 allocate_reg_info (nregs, TRUE, FALSE);
2069 for (insn = f; insn; insn = NEXT_INSN (insn))
2070 if (GET_CODE (insn) == INSN
2071 || GET_CODE (insn) == CALL_INSN
2072 || GET_CODE (insn) == JUMP_INSN)
2074 if (GET_CODE (PATTERN (insn)) == PARALLEL
2075 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2076 max_parallel = XVECLEN (PATTERN (insn), 0);
2077 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2079 if (REG_NOTES (insn))
2080 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2084 /* Update 'regscan' information by looking at the insns
2085 from FIRST to LAST. Some new REGs have been created,
2086 and any REG with number greater than OLD_MAX_REGNO is
2087 such a REG. We only update information for those. */
2090 reg_scan_update(first, last, old_max_regno)
2097 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2099 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2100 if (GET_CODE (insn) == INSN
2101 || GET_CODE (insn) == CALL_INSN
2102 || GET_CODE (insn) == JUMP_INSN)
2104 if (GET_CODE (PATTERN (insn)) == PARALLEL
2105 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2106 max_parallel = XVECLEN (PATTERN (insn), 0);
2107 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2109 if (REG_NOTES (insn))
2110 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2114 /* X is the expression to scan. INSN is the insn it appears in.
2115 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2116 We should only record information for REGs with numbers
2117 greater than or equal to MIN_REGNO. */
2120 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2126 register enum rtx_code code;
2130 code = GET_CODE (x);
2146 register int regno = REGNO (x);
2148 if (regno >= min_regno)
2150 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2152 REGNO_LAST_UID (regno) = INSN_UID (insn);
2153 if (REGNO_FIRST_UID (regno) == 0)
2154 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2161 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2163 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2168 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2172 /* Count a set of the destination if it is a register. */
2173 for (dest = SET_DEST (x);
2174 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2175 || GET_CODE (dest) == ZERO_EXTEND;
2176 dest = XEXP (dest, 0))
2179 if (GET_CODE (dest) == REG
2180 && REGNO (dest) >= min_regno)
2181 REG_N_SETS (REGNO (dest))++;
2183 /* If this is setting a pseudo from another pseudo or the sum of a
2184 pseudo and a constant integer and the other pseudo is known to be
2185 a pointer, set the destination to be a pointer as well.
2187 Likewise if it is setting the destination from an address or from a
2188 value equivalent to an address or to the sum of an address and
2191 But don't do any of this if the pseudo corresponds to a user
2192 variable since it should have already been set as a pointer based
2195 if (GET_CODE (SET_DEST (x)) == REG
2196 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2197 && REGNO (SET_DEST (x)) >= min_regno
2198 /* If the destination pseudo is set more than once, then other
2199 sets might not be to a pointer value (consider access to a
2200 union in two threads of control in the presense of global
2201 optimizations). So only set REGNO_POINTER_FLAG on the destination
2202 pseudo if this is the only set of that pseudo. */
2203 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2204 && ! REG_USERVAR_P (SET_DEST (x))
2205 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2206 && ((GET_CODE (SET_SRC (x)) == REG
2207 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2208 || ((GET_CODE (SET_SRC (x)) == PLUS
2209 || GET_CODE (SET_SRC (x)) == LO_SUM)
2210 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2211 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2212 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2213 || GET_CODE (SET_SRC (x)) == CONST
2214 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2215 || GET_CODE (SET_SRC (x)) == LABEL_REF
2216 || (GET_CODE (SET_SRC (x)) == HIGH
2217 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2218 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2219 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2220 || ((GET_CODE (SET_SRC (x)) == PLUS
2221 || GET_CODE (SET_SRC (x)) == LO_SUM)
2222 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2223 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2224 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2225 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2226 && (GET_CODE (XEXP (note, 0)) == CONST
2227 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2228 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2229 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2231 /* ... fall through ... */
2235 register const char *fmt = GET_RTX_FORMAT (code);
2237 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2240 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2241 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2244 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2245 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2252 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2256 reg_class_subset_p (c1, c2)
2257 register enum reg_class c1;
2258 register enum reg_class c2;
2260 if (c1 == c2) return 1;
2265 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2266 reg_class_contents[(int)c2],
2271 /* Return nonzero if there is a register that is in both C1 and C2. */
2274 reg_classes_intersect_p (c1, c2)
2275 register enum reg_class c1;
2276 register enum reg_class c2;
2283 if (c1 == c2) return 1;
2285 if (c1 == ALL_REGS || c2 == ALL_REGS)
2288 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2289 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2291 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2298 /* Release any memory allocated by register sets. */
2301 regset_release_memory ()
2303 bitmap_release_memory ();