1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
43 #ifndef REGISTER_MOVE_COST
44 #define REGISTER_MOVE_COST(x, y) 2
47 static void init_reg_sets_1 PROTO((void));
48 static void init_reg_modes PROTO((void));
50 /* If we have auto-increment or auto-decrement and we can have secondary
51 reloads, we are not allowed to use classes requiring secondary
52 reloads for pseudos auto-incremented since reload can't handle it. */
55 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
56 #define FORBIDDEN_INC_DEC_CLASSES
60 /* Register tables used by many passes. */
62 /* Indexed by hard register number, contains 1 for registers
63 that are fixed use (stack pointer, pc, frame pointer, etc.).
64 These are the registers that cannot be used to allocate
65 a pseudo reg for general use. */
67 char fixed_regs[FIRST_PSEUDO_REGISTER];
69 /* Same info as a HARD_REG_SET. */
71 HARD_REG_SET fixed_reg_set;
73 /* Data for initializing the above. */
75 static char initial_fixed_regs[] = FIXED_REGISTERS;
77 /* Indexed by hard register number, contains 1 for registers
78 that are fixed use or are clobbered by function calls.
79 These are the registers that cannot be used to allocate
80 a pseudo reg whose life crosses calls unless we are able
81 to save/restore them across the calls. */
83 char call_used_regs[FIRST_PSEUDO_REGISTER];
85 /* Same info as a HARD_REG_SET. */
87 HARD_REG_SET call_used_reg_set;
89 /* HARD_REG_SET of registers we want to avoid caller saving. */
90 HARD_REG_SET losing_caller_save_reg_set;
92 /* Data for initializing the above. */
94 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
96 /* Indexed by hard register number, contains 1 for registers that are
97 fixed use or call used registers that cannot hold quantities across
98 calls even if we are willing to save and restore them. call fixed
99 registers are a subset of call used registers. */
101 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
103 /* The same info as a HARD_REG_SET. */
105 HARD_REG_SET call_fixed_reg_set;
107 /* Number of non-fixed registers. */
109 int n_non_fixed_regs;
111 /* Indexed by hard register number, contains 1 for registers
112 that are being used for global register decls.
113 These must be exempt from ordinary flow analysis
114 and are also considered fixed. */
116 char global_regs[FIRST_PSEUDO_REGISTER];
118 /* Table of register numbers in the order in which to try to use them. */
119 #ifdef REG_ALLOC_ORDER
120 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
125 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
127 /* The same information, but as an array of unsigned ints. We copy from
128 these unsigned ints to the table above. We do this so the tm.h files
129 do not have to be aware of the wordsize for machines with <= 64 regs. */
132 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
134 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
135 = REG_CLASS_CONTENTS;
137 /* For each reg class, number of regs it contains. */
139 int reg_class_size[N_REG_CLASSES];
141 /* For each reg class, table listing all the containing classes. */
143 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
145 /* For each reg class, table listing all the classes contained in it. */
147 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each pair of reg classes,
150 a largest reg class contained in their union. */
152 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
154 /* For each pair of reg classes,
155 the smallest reg class containing their union. */
157 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
159 /* Array containing all of the register names */
161 const char *reg_names[] = REGISTER_NAMES;
163 /* For each hard register, the widest mode object that it can contain.
164 This will be a MODE_INT mode if the register can hold integers. Otherwise
165 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
168 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
170 /* Maximum cost of moving from a register in one class to a register in
171 another class. Based on REGISTER_MOVE_COST. */
173 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
175 /* Similar, but here we don't have to move if the first index is a subset
176 of the second so in that case the cost is zero. */
178 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
180 /* Similar, but here we don't have to move if the first index is a superset
181 of the second so in that case the cost is zero. */
183 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
185 #ifdef FORBIDDEN_INC_DEC_CLASSES
187 /* These are the classes that regs which are auto-incremented or decremented
190 static int forbidden_inc_dec_class[N_REG_CLASSES];
192 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
195 static char *in_inc_dec;
197 #endif /* FORBIDDEN_INC_DEC_CLASSES */
199 #ifdef HAVE_SECONDARY_RELOADS
201 /* Sample MEM values for use by memory_move_secondary_cost. */
203 static rtx top_of_stack[MAX_MACHINE_MODE];
205 #endif /* HAVE_SECONDARY_RELOADS */
207 /* Linked list of reg_info structures allocated for reg_n_info array.
208 Grouping all of the allocated structures together in one lump
209 means only one call to bzero to clear them, rather than n smaller
211 struct reg_info_data {
212 struct reg_info_data *next; /* next set of reg_info structures */
213 size_t min_index; /* minimum index # */
214 size_t max_index; /* maximum index # */
215 char used_p; /* non-zero if this has been used previously */
216 reg_info data[1]; /* beginning of the reg_info data */
219 static struct reg_info_data *reg_info_head;
222 /* Function called only once to initialize the above data on reg usage.
223 Once this is done, various switches may override. */
230 /* First copy the register information from the initial int form into
233 for (i = 0; i < N_REG_CLASSES; i++)
235 CLEAR_HARD_REG_SET (reg_class_contents[i]);
237 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
238 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
239 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
240 SET_HARD_REG_BIT (reg_class_contents[i], j);
243 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
244 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
245 bzero (global_regs, sizeof global_regs);
247 /* Do any additional initialization regsets may need */
248 INIT_ONCE_REG_SET ();
251 /* After switches have been processed, which perhaps alter
252 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
257 register unsigned int i, j;
259 /* This macro allows the fixed or call-used registers
260 and the register classes to depend on target flags. */
262 #ifdef CONDITIONAL_REGISTER_USAGE
263 CONDITIONAL_REGISTER_USAGE;
266 /* Compute number of hard regs in each class. */
268 bzero ((char *) reg_class_size, sizeof reg_class_size);
269 for (i = 0; i < N_REG_CLASSES; i++)
270 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
271 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
274 /* Initialize the table of subunions.
275 reg_class_subunion[I][J] gets the largest-numbered reg-class
276 that is contained in the union of classes I and J. */
278 for (i = 0; i < N_REG_CLASSES; i++)
280 for (j = 0; j < N_REG_CLASSES; j++)
283 register /* Declare it register if it's a scalar. */
288 COPY_HARD_REG_SET (c, reg_class_contents[i]);
289 IOR_HARD_REG_SET (c, reg_class_contents[j]);
290 for (k = 0; k < N_REG_CLASSES; k++)
292 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
297 /* keep the largest subclass */ /* SPEE 900308 */
298 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
299 reg_class_contents[(int) reg_class_subunion[i][j]],
301 reg_class_subunion[i][j] = (enum reg_class) k;
308 /* Initialize the table of superunions.
309 reg_class_superunion[I][J] gets the smallest-numbered reg-class
310 containing the union of classes I and J. */
312 for (i = 0; i < N_REG_CLASSES; i++)
314 for (j = 0; j < N_REG_CLASSES; j++)
317 register /* Declare it register if it's a scalar. */
322 COPY_HARD_REG_SET (c, reg_class_contents[i]);
323 IOR_HARD_REG_SET (c, reg_class_contents[j]);
324 for (k = 0; k < N_REG_CLASSES; k++)
325 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
328 reg_class_superunion[i][j] = (enum reg_class) k;
332 /* Initialize the tables of subclasses and superclasses of each reg class.
333 First clear the whole table, then add the elements as they are found. */
335 for (i = 0; i < N_REG_CLASSES; i++)
337 for (j = 0; j < N_REG_CLASSES; j++)
339 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
340 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
344 for (i = 0; i < N_REG_CLASSES; i++)
346 if (i == (int) NO_REGS)
349 for (j = i + 1; j < N_REG_CLASSES; j++)
353 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
357 /* Reg class I is a subclass of J.
358 Add J to the table of superclasses of I. */
359 p = ®_class_superclasses[i][0];
360 while (*p != LIM_REG_CLASSES) p++;
361 *p = (enum reg_class) j;
362 /* Add I to the table of superclasses of J. */
363 p = ®_class_subclasses[j][0];
364 while (*p != LIM_REG_CLASSES) p++;
365 *p = (enum reg_class) i;
369 /* Initialize "constant" tables. */
371 CLEAR_HARD_REG_SET (fixed_reg_set);
372 CLEAR_HARD_REG_SET (call_used_reg_set);
373 CLEAR_HARD_REG_SET (call_fixed_reg_set);
375 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
377 n_non_fixed_regs = 0;
379 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
382 SET_HARD_REG_BIT (fixed_reg_set, i);
386 if (call_used_regs[i])
387 SET_HARD_REG_BIT (call_used_reg_set, i);
388 if (call_fixed_regs[i])
389 SET_HARD_REG_BIT (call_fixed_reg_set, i);
390 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
391 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
394 /* Initialize the move cost table. Find every subset of each class
395 and take the maximum cost of moving any subset to any other. */
397 for (i = 0; i < N_REG_CLASSES; i++)
398 for (j = 0; j < N_REG_CLASSES; j++)
400 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
401 enum reg_class *p1, *p2;
403 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
405 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
407 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
410 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
412 for (p2 = ®_class_subclasses[j][0];
413 *p2 != LIM_REG_CLASSES; p2++)
415 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
418 move_cost[i][j] = cost;
420 if (reg_class_subset_p (i, j))
421 may_move_in_cost[i][j] = 0;
423 may_move_in_cost[i][j] = cost;
425 if (reg_class_subset_p (j, i))
426 may_move_out_cost[i][j] = 0;
428 may_move_out_cost[i][j] = cost;
432 /* Compute the table of register modes.
433 These values are used to record death information for individual registers
434 (as opposed to a multi-register mode). */
441 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
443 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
445 /* If we couldn't find a valid mode, just use the previous mode.
446 ??? One situation in which we need to do this is on the mips where
447 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
448 to use DF mode for the even registers and VOIDmode for the odd
449 (for the cpu models where the odd ones are inaccessible). */
450 if (reg_raw_mode[i] == VOIDmode)
451 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
455 /* Finish initializing the register sets and
456 initialize the register modes. */
461 /* This finishes what was started by init_reg_sets, but couldn't be done
462 until after register usage was specified. */
467 #ifdef HAVE_SECONDARY_RELOADS
469 /* Make some fake stack-frame MEM references for use in
470 memory_move_secondary_cost. */
472 for (i = 0; i < MAX_MACHINE_MODE; i++)
473 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
474 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
479 #ifdef HAVE_SECONDARY_RELOADS
481 /* Compute extra cost of moving registers to/from memory due to reloads.
482 Only needed if secondary reloads are required for memory moves. */
485 memory_move_secondary_cost (mode, class, in)
486 enum machine_mode mode;
487 enum reg_class class;
490 enum reg_class altclass;
491 int partial_cost = 0;
492 /* We need a memory reference to feed to SECONDARY... macros. */
493 rtx mem = top_of_stack[(int) mode];
497 #ifdef SECONDARY_INPUT_RELOAD_CLASS
498 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
505 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
506 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
512 if (altclass == NO_REGS)
516 partial_cost = REGISTER_MOVE_COST (altclass, class);
518 partial_cost = REGISTER_MOVE_COST (class, altclass);
520 if (class == altclass)
521 /* This isn't simply a copy-to-temporary situation. Can't guess
522 what it is, so MEMORY_MOVE_COST really ought not to be calling
525 I'm tempted to put in an abort here, but returning this will
526 probably only give poor estimates, which is what we would've
527 had before this code anyways. */
530 /* Check if the secondary reload register will also need a
532 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
536 /* Return a machine mode that is legitimate for hard reg REGNO and large
537 enough to save nregs. If we can't find one, return VOIDmode. */
540 choose_hard_reg_mode (regno, nregs)
544 enum machine_mode found_mode = VOIDmode, mode;
546 /* We first look for the largest integer mode that can be validly
547 held in REGNO. If none, we look for the largest floating-point mode.
548 If we still didn't find a valid mode, try CCmode. */
550 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
552 mode = GET_MODE_WIDER_MODE (mode))
553 if (HARD_REGNO_NREGS (regno, mode) == nregs
554 && HARD_REGNO_MODE_OK (regno, mode))
557 if (found_mode != VOIDmode)
560 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
562 mode = GET_MODE_WIDER_MODE (mode))
563 if (HARD_REGNO_NREGS (regno, mode) == nregs
564 && HARD_REGNO_MODE_OK (regno, mode))
567 if (found_mode != VOIDmode)
570 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
571 && HARD_REGNO_MODE_OK (regno, CCmode))
574 /* We can't find a mode valid for this register. */
578 /* Specify the usage characteristics of the register named NAME.
579 It should be a fixed register if FIXED and a
580 call-used register if CALL_USED. */
583 fix_register (name, fixed, call_used)
585 int fixed, call_used;
589 /* Decode the name and update the primary form of
590 the register info. */
592 if ((i = decode_reg_name (name)) >= 0)
594 if ((i == STACK_POINTER_REGNUM
595 #ifdef HARD_FRAME_POINTER_REGNUM
596 || i == HARD_FRAME_POINTER_REGNUM
598 || i == FRAME_POINTER_REGNUM
601 && (fixed == 0 || call_used == 0))
603 static const char * const what_option[2][2] = {
604 { "call-saved", "call-used" },
605 { "no-such-option", "fixed" }};
607 error ("can't use '%s' as a %s register", name,
608 what_option[fixed][call_used]);
612 fixed_regs[i] = fixed;
613 call_used_regs[i] = call_used;
618 warning ("unknown register name: %s", name);
622 /* Mark register number I as global. */
630 warning ("register used for two global register variables");
634 if (call_used_regs[i] && ! fixed_regs[i])
635 warning ("call-clobbered register used for global register variable");
639 /* If already fixed, nothing else to do. */
643 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
646 SET_HARD_REG_BIT (fixed_reg_set, i);
647 SET_HARD_REG_BIT (call_used_reg_set, i);
648 SET_HARD_REG_BIT (call_fixed_reg_set, i);
651 /* Now the data and code for the `regclass' pass, which happens
652 just before local-alloc. */
654 /* The `costs' struct records the cost of using a hard register of each class
655 and of using memory for each pseudo. We use this data to set up
656 register class preferences. */
660 int cost[N_REG_CLASSES];
664 /* Structure used to record preferrences of given pseudo. */
667 /* (enum reg_class) prefclass is the preferred class. */
670 /* altclass is a register class that we should use for allocating
671 pseudo if no register in the preferred class is available.
672 If no register in this class is available, memory is preferred.
674 It might appear to be more general to have a bitmask of classes here,
675 but since it is recommended that there be a class corresponding to the
676 union of most major pair of classes, that generality is not required. */
680 /* Record the cost of each class for each pseudo. */
682 static struct costs *costs;
684 /* Initialized once, and used to initialize cost values for each insn. */
686 static struct costs init_cost;
688 /* Record the same data by operand number, accumulated for each alternative
689 in an insn. The contribution to a pseudo is that of the minimum-cost
692 static struct costs op_costs[MAX_RECOG_OPERANDS];
694 /* Record preferrences of each pseudo.
695 This is available after `regclass' is run. */
697 static struct reg_pref *reg_pref;
699 /* Allocated buffers for reg_pref. */
701 static struct reg_pref *reg_pref_buffer;
703 /* Record the depth of loops that we are in. */
705 static int loop_depth;
707 /* Account for the fact that insns within a loop are executed very commonly,
708 but don't keep doing this as loops go too deep. */
710 static int loop_cost;
712 static rtx scan_one_insn PROTO((rtx, int));
713 static void dump_regclass PROTO((FILE *));
714 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
715 char *, const char **, rtx));
716 static int copy_cost PROTO((rtx, enum machine_mode,
717 enum reg_class, int));
718 static void record_address_regs PROTO((rtx, enum reg_class, int));
719 #ifdef FORBIDDEN_INC_DEC_CLASSES
720 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
722 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
724 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
725 This function is sometimes called before the info has been computed.
726 When that happens, just return GENERAL_REGS, which is innocuous. */
729 reg_preferred_class (regno)
734 return (enum reg_class) reg_pref[regno].prefclass;
738 reg_alternate_class (regno)
744 return (enum reg_class) reg_pref[regno].altclass;
747 /* Initialize some global data for this pass. */
754 init_cost.mem_cost = 10000;
755 for (i = 0; i < N_REG_CLASSES; i++)
756 init_cost.cost[i] = 10000;
758 /* This prevents dump_flow_info from losing if called
759 before regclass is run. */
763 /* Dump register costs. */
768 static const char *const reg_class_names[] = REG_CLASS_NAMES;
770 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
772 enum reg_class class;
775 fprintf (dump, ";; Register %i costs:", i);
776 for (class = 0; class < N_REG_CLASSES; class++)
777 fprintf (dump, " %s:%i", reg_class_names[(int) class],
778 costs[i].cost[class]);
779 fprintf (dump, " MEM:%i\n\n", costs[i].mem_cost);
785 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
786 time it would save code to put a certain register in a certain class.
787 PASS, when nonzero, inhibits some optimizations which need only be done
789 Return the last insn processed, so that the scan can be continued from
793 scan_one_insn (insn, pass)
797 enum rtx_code code = GET_CODE (insn);
798 enum rtx_code pat_code;
799 const char *constraints[MAX_RECOG_OPERANDS];
800 enum machine_mode modes[MAX_RECOG_OPERANDS];
801 char subreg_changes_size[MAX_RECOG_OPERANDS];
805 /* Show that an insn inside a loop is likely to be executed three
806 times more than insns outside a loop. This is much more aggressive
807 than the assumptions made elsewhere and is being tried as an
812 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
813 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
814 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
815 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
820 if (GET_RTX_CLASS (code) != 'i')
823 pat_code = GET_CODE (PATTERN (insn));
825 || pat_code == CLOBBER
826 || pat_code == ASM_INPUT
827 || pat_code == ADDR_VEC
828 || pat_code == ADDR_DIFF_VEC)
831 set = single_set (insn);
834 for (i = 0; i < recog_data.n_operands; i++)
836 constraints[i] = recog_data.constraints[i];
837 modes[i] = recog_data.operand_mode[i];
839 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
841 /* If this insn loads a parameter from its stack slot, then
842 it represents a savings, rather than a cost, if the
843 parameter is stored in memory. Record this fact. */
845 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
846 && GET_CODE (SET_SRC (set)) == MEM
847 && (note = find_reg_note (insn, REG_EQUIV,
849 && GET_CODE (XEXP (note, 0)) == MEM)
851 costs[REGNO (SET_DEST (set))].mem_cost
852 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
855 record_address_regs (XEXP (SET_SRC (set), 0),
856 BASE_REG_CLASS, loop_cost * 2);
860 /* Improve handling of two-address insns such as
861 (set X (ashift CONST Y)) where CONST must be made to
862 match X. Change it into two insns: (set X CONST)
863 (set X (ashift X Y)). If we left this for reloading, it
864 would probably get three insns because X and Y might go
865 in the same place. This prevents X and Y from receiving
868 We can only do this if the modes of operands 0 and 1
869 (which might not be the same) are tieable and we only need
870 do this during our first pass. */
872 if (pass == 0 && optimize
873 && recog_data.n_operands >= 3
874 && recog_data.constraints[1][0] == '0'
875 && recog_data.constraints[1][1] == 0
876 && CONSTANT_P (recog_data.operand[1])
877 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
878 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
879 && GET_CODE (recog_data.operand[0]) == REG
880 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
881 recog_data.operand_mode[1]))
883 rtx previnsn = prev_real_insn (insn);
885 = gen_lowpart (recog_data.operand_mode[1],
886 recog_data.operand[0]);
888 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
890 /* If this insn was the start of a basic block,
891 include the new insn in that block.
892 We need not check for code_label here;
893 while a basic block can start with a code_label,
894 INSN could not be at the beginning of that block. */
895 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
898 for (b = 0; b < n_basic_blocks; b++)
899 if (insn == BLOCK_HEAD (b))
900 BLOCK_HEAD (b) = newinsn;
903 /* This makes one more setting of new insns's dest. */
904 REG_N_SETS (REGNO (recog_data.operand[0]))++;
906 *recog_data.operand_loc[1] = recog_data.operand[0];
907 for (i = recog_data.n_dups - 1; i >= 0; i--)
908 if (recog_data.dup_num[i] == 1)
909 *recog_data.dup_loc[i] = recog_data.operand[0];
911 return PREV_INSN (newinsn);
914 /* If we get here, we are set up to record the costs of all the
915 operands for this insn. Start by initializing the costs.
916 Then handle any address registers. Finally record the desired
917 classes for any pseudos, doing it twice if some pair of
918 operands are commutative. */
920 for (i = 0; i < recog_data.n_operands; i++)
922 op_costs[i] = init_cost;
924 if (GET_CODE (recog_data.operand[i]) == SUBREG)
926 rtx inner = SUBREG_REG (recog_data.operand[i]);
927 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
928 subreg_changes_size[i] = 1;
929 recog_data.operand[i] = inner;
932 if (GET_CODE (recog_data.operand[i]) == MEM)
933 record_address_regs (XEXP (recog_data.operand[i], 0),
934 BASE_REG_CLASS, loop_cost * 2);
935 else if (constraints[i][0] == 'p')
936 record_address_regs (recog_data.operand[i],
937 BASE_REG_CLASS, loop_cost * 2);
940 /* Check for commutative in a separate loop so everything will
941 have been initialized. We must do this even if one operand
942 is a constant--see addsi3 in m68k.md. */
944 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
945 if (constraints[i][0] == '%')
947 const char *xconstraints[MAX_RECOG_OPERANDS];
950 /* Handle commutative operands by swapping the constraints.
951 We assume the modes are the same. */
953 for (j = 0; j < recog_data.n_operands; j++)
954 xconstraints[j] = constraints[j];
956 xconstraints[i] = constraints[i+1];
957 xconstraints[i+1] = constraints[i];
958 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
959 recog_data.operand, modes, subreg_changes_size,
963 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
964 recog_data.operand, modes, subreg_changes_size,
967 /* Now add the cost for each operand to the total costs for
970 for (i = 0; i < recog_data.n_operands; i++)
971 if (GET_CODE (recog_data.operand[i]) == REG
972 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
974 int regno = REGNO (recog_data.operand[i]);
975 struct costs *p = &costs[regno], *q = &op_costs[i];
977 p->mem_cost += q->mem_cost * loop_cost;
978 for (j = 0; j < N_REG_CLASSES; j++)
979 p->cost[j] += q->cost[j] * loop_cost;
985 /* This is a pass of the compiler that scans all instructions
986 and calculates the preferred class for each pseudo-register.
987 This information can be accessed later by calling `reg_preferred_class'.
988 This pass comes just before local register allocation. */
991 regclass (f, nregs, dump)
1002 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1004 #ifdef FORBIDDEN_INC_DEC_CLASSES
1006 in_inc_dec = (char *) xmalloc (nregs);
1008 /* Initialize information about which register classes can be used for
1009 pseudos that are auto-incremented or auto-decremented. It would
1010 seem better to put this in init_reg_sets, but we need to be able
1011 to allocate rtx, which we can't do that early. */
1013 for (i = 0; i < N_REG_CLASSES; i++)
1015 rtx r = gen_rtx_REG (VOIDmode, 0);
1016 enum machine_mode m;
1019 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1020 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1024 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1025 m = (enum machine_mode) ((int) m + 1))
1026 if (HARD_REGNO_MODE_OK (j, m))
1030 /* If a register is not directly suitable for an
1031 auto-increment or decrement addressing mode and
1032 requires secondary reloads, disallow its class from
1033 being used in such addresses. */
1036 #ifdef SECONDARY_RELOAD_CLASS
1037 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1040 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1041 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1044 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1045 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1050 && ! auto_inc_dec_reg_p (r, m))
1051 forbidden_inc_dec_class[i] = 1;
1055 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1057 /* Normally we scan the insns once and determine the best class to use for
1058 each register. However, if -fexpensive_optimizations are on, we do so
1059 twice, the second time using the tentative best classes to guide the
1062 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1064 /* Zero out our accumulation of the cost of each class for each reg. */
1066 bzero ((char *) costs, nregs * sizeof (struct costs));
1068 #ifdef FORBIDDEN_INC_DEC_CLASSES
1069 bzero (in_inc_dec, nregs);
1072 loop_depth = 0, loop_cost = 1;
1074 /* Scan the instructions and record each time it would
1075 save code to put a certain register in a certain class. */
1077 for (insn = f; insn; insn = NEXT_INSN (insn))
1079 insn = scan_one_insn (insn, pass);
1082 /* Now for each register look at how desirable each class is
1083 and find which class is preferred. Store that in
1084 `prefclass'. Record in `altclass' the largest register
1085 class any of whose registers is better than memory. */
1088 reg_pref = reg_pref_buffer;
1090 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1092 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1093 enum reg_class best = ALL_REGS, alt = NO_REGS;
1094 /* This is an enum reg_class, but we call it an int
1095 to save lots of casts. */
1097 register struct costs *p = &costs[i];
1099 for (class = (int) ALL_REGS - 1; class > 0; class--)
1101 /* Ignore classes that are too small for this operand or
1102 invalid for a operand that was auto-incremented. */
1103 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1104 > reg_class_size[class]
1105 #ifdef FORBIDDEN_INC_DEC_CLASSES
1106 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1110 else if (p->cost[class] < best_cost)
1112 best_cost = p->cost[class];
1113 best = (enum reg_class) class;
1115 else if (p->cost[class] == best_cost)
1116 best = reg_class_subunion[(int)best][class];
1119 /* Record the alternate register class; i.e., a class for which
1120 every register in it is better than using memory. If adding a
1121 class would make a smaller class (i.e., no union of just those
1122 classes exists), skip that class. The major unions of classes
1123 should be provided as a register class. Don't do this if we
1124 will be doing it again later. */
1126 if (pass == 1 || ! flag_expensive_optimizations)
1127 for (class = 0; class < N_REG_CLASSES; class++)
1128 if (p->cost[class] < p->mem_cost
1129 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1130 > reg_class_size[(int) alt])
1131 #ifdef FORBIDDEN_INC_DEC_CLASSES
1132 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1135 alt = reg_class_subunion[(int) alt][class];
1137 /* If we don't add any classes, nothing to try. */
1141 /* We cast to (int) because (char) hits bugs in some compilers. */
1142 reg_pref[i].prefclass = (int) best;
1143 reg_pref[i].altclass = (int) alt;
1148 dump_regclass (dump);
1149 #ifdef FORBIDDEN_INC_DEC_CLASSES
1155 /* Record the cost of using memory or registers of various classes for
1156 the operands in INSN.
1158 N_ALTS is the number of alternatives.
1160 N_OPS is the number of operands.
1162 OPS is an array of the operands.
1164 MODES are the modes of the operands, in case any are VOIDmode.
1166 CONSTRAINTS are the constraints to use for the operands. This array
1167 is modified by this procedure.
1169 This procedure works alternative by alternative. For each alternative
1170 we assume that we will be able to allocate all pseudos to their ideal
1171 register class and calculate the cost of using that alternative. Then
1172 we compute for each operand that is a pseudo-register, the cost of
1173 having the pseudo allocated to each register class and using it in that
1174 alternative. To this cost is added the cost of the alternative.
1176 The cost of each class for this insn is its lowest cost among all the
1180 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1185 enum machine_mode *modes;
1186 char *subreg_changes_size;
1187 const char **constraints;
1194 /* Process each alternative, each time minimizing an operand's cost with
1195 the cost for each operand in that alternative. */
1197 for (alt = 0; alt < n_alts; alt++)
1199 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1202 enum reg_class classes[MAX_RECOG_OPERANDS];
1203 int allows_mem[MAX_RECOG_OPERANDS];
1206 for (i = 0; i < n_ops; i++)
1208 const char *p = constraints[i];
1210 enum machine_mode mode = modes[i];
1211 int allows_addr = 0;
1215 /* Initially show we know nothing about the register class. */
1216 classes[i] = NO_REGS;
1219 /* If this operand has no constraints at all, we can conclude
1220 nothing about it since anything is valid. */
1224 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1225 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1230 /* If this alternative is only relevant when this operand
1231 matches a previous operand, we do different things depending
1232 on whether this operand is a pseudo-reg or not. We must process
1233 any modifiers for the operand before we can make this test. */
1235 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1238 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1240 /* Copy class and whether memory is allowed from the matching
1241 alternative. Then perform any needed cost computations
1242 and/or adjustments. */
1244 classes[i] = classes[j];
1245 allows_mem[i] = allows_mem[j];
1247 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1249 /* If this matches the other operand, we have no added
1251 if (rtx_equal_p (ops[j], op))
1254 /* If we can put the other operand into a register, add to
1255 the cost of this alternative the cost to copy this
1256 operand to the register used for the other operand. */
1258 else if (classes[j] != NO_REGS)
1259 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1261 else if (GET_CODE (ops[j]) != REG
1262 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1264 /* This op is a pseudo but the one it matches is not. */
1266 /* If we can't put the other operand into a register, this
1267 alternative can't be used. */
1269 if (classes[j] == NO_REGS)
1272 /* Otherwise, add to the cost of this alternative the cost
1273 to copy the other operand to the register used for this
1277 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1281 /* The costs of this operand are not the same as the other
1282 operand since move costs are not symmetric. Moreover,
1283 if we cannot tie them, this alternative needs to do a
1284 copy, which is one instruction. */
1286 struct costs *pp = &this_op_costs[i];
1288 for (class = 0; class < N_REG_CLASSES; class++)
1290 = (recog_data.operand_type[i] == OP_IN
1291 ? may_move_in_cost[class][(int) classes[i]]
1292 : may_move_out_cost[(int) classes[i]][class]);
1294 /* If the alternative actually allows memory, make things
1295 a bit cheaper since we won't need an extra insn to
1299 = (MEMORY_MOVE_COST (mode, classes[i],
1300 recog_data.operand_type[i] == OP_IN)
1303 /* If we have assigned a class to this register in our
1304 first pass, add a cost to this alternative corresponding
1305 to what we would add if this register were not in the
1306 appropriate class. */
1310 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1311 [(int) classes[i]]);
1313 if (REGNO (ops[i]) != REGNO (ops[j])
1314 && ! find_reg_note (insn, REG_DEAD, op))
1317 /* This is in place of ordinary cost computation
1318 for this operand, so skip to the end of the
1319 alternative (should be just one character). */
1320 while (*p && *p++ != ',')
1328 /* Scan all the constraint letters. See if the operand matches
1329 any of the constraints. Collect the valid register classes
1330 and see if this operand accepts memory. */
1332 while (*p && (c = *p++) != ',')
1336 /* Ignore the next letter for this pass. */
1342 case '!': case '#': case '&':
1343 case '0': case '1': case '2': case '3': case '4':
1344 case '5': case '6': case '7': case '8': case '9':
1349 win = address_operand (op, GET_MODE (op));
1350 /* We know this operand is an address, so we want it to be
1351 allocated to a register that can be the base of an
1352 address, ie BASE_REG_CLASS. */
1354 = reg_class_subunion[(int) classes[i]]
1355 [(int) BASE_REG_CLASS];
1358 case 'm': case 'o': case 'V':
1359 /* It doesn't seem worth distinguishing between offsettable
1360 and non-offsettable addresses here. */
1362 if (GET_CODE (op) == MEM)
1367 if (GET_CODE (op) == MEM
1368 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1369 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1374 if (GET_CODE (op) == MEM
1375 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1376 || GET_CODE (XEXP (op, 0)) == POST_INC))
1381 #ifndef REAL_ARITHMETIC
1382 /* Match any floating double constant, but only if
1383 we can examine the bits of it reliably. */
1384 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1385 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1386 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1389 if (GET_CODE (op) == CONST_DOUBLE)
1394 if (GET_CODE (op) == CONST_DOUBLE)
1400 if (GET_CODE (op) == CONST_DOUBLE
1401 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1406 if (GET_CODE (op) == CONST_INT
1407 || (GET_CODE (op) == CONST_DOUBLE
1408 && GET_MODE (op) == VOIDmode))
1412 #ifdef LEGITIMATE_PIC_OPERAND_P
1413 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1420 if (GET_CODE (op) == CONST_INT
1421 || (GET_CODE (op) == CONST_DOUBLE
1422 && GET_MODE (op) == VOIDmode))
1434 if (GET_CODE (op) == CONST_INT
1435 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1443 #ifdef EXTRA_CONSTRAINT
1449 if (EXTRA_CONSTRAINT (op, c))
1455 if (GET_CODE (op) == MEM
1457 #ifdef LEGITIMATE_PIC_OPERAND_P
1458 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1465 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1470 = reg_class_subunion[(int) classes[i]]
1471 [(int) REG_CLASS_FROM_LETTER (c)];
1476 #ifdef CLASS_CANNOT_CHANGE_SIZE
1477 /* If we noted a subreg earlier, and the selected class is a
1478 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1479 if (subreg_changes_size[i]
1480 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1482 == CLASS_CANNOT_CHANGE_SIZE))
1483 classes[i] = NO_REGS;
1486 /* How we account for this operand now depends on whether it is a
1487 pseudo register or not. If it is, we first check if any
1488 register classes are valid. If not, we ignore this alternative,
1489 since we want to assume that all pseudos get allocated for
1490 register preferencing. If some register class is valid, compute
1491 the costs of moving the pseudo into that class. */
1493 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1495 if (classes[i] == NO_REGS)
1497 /* We must always fail if the operand is a REG, but
1498 we did not find a suitable class.
1500 Otherwise we may perform an uninitialized read
1501 from this_op_costs after the `continue' statement
1507 struct costs *pp = &this_op_costs[i];
1509 for (class = 0; class < N_REG_CLASSES; class++)
1511 = (recog_data.operand_type[i] == OP_IN
1512 ? may_move_in_cost[class][(int) classes[i]]
1513 : may_move_out_cost[(int) classes[i]][class]);
1515 /* If the alternative actually allows memory, make things
1516 a bit cheaper since we won't need an extra insn to
1520 = (MEMORY_MOVE_COST (mode, classes[i],
1521 recog_data.operand_type[i] == OP_IN)
1524 /* If we have assigned a class to this register in our
1525 first pass, add a cost to this alternative corresponding
1526 to what we would add if this register were not in the
1527 appropriate class. */
1531 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1532 [(int) classes[i]]);
1536 /* Otherwise, if this alternative wins, either because we
1537 have already determined that or if we have a hard register of
1538 the proper class, there is no cost for this alternative. */
1541 || (GET_CODE (op) == REG
1542 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1545 /* If registers are valid, the cost of this alternative includes
1546 copying the object to and/or from a register. */
1548 else if (classes[i] != NO_REGS)
1550 if (recog_data.operand_type[i] != OP_OUT)
1551 alt_cost += copy_cost (op, mode, classes[i], 1);
1553 if (recog_data.operand_type[i] != OP_IN)
1554 alt_cost += copy_cost (op, mode, classes[i], 0);
1557 /* The only other way this alternative can be used is if this is a
1558 constant that could be placed into memory. */
1560 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1561 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1569 /* Finally, update the costs with the information we've calculated
1570 about this alternative. */
1572 for (i = 0; i < n_ops; i++)
1573 if (GET_CODE (ops[i]) == REG
1574 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1576 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1577 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1579 pp->mem_cost = MIN (pp->mem_cost,
1580 (qq->mem_cost + alt_cost) * scale);
1582 for (class = 0; class < N_REG_CLASSES; class++)
1583 pp->cost[class] = MIN (pp->cost[class],
1584 (qq->cost[class] + alt_cost) * scale);
1588 /* If this insn is a single set copying operand 1 to operand 0
1589 and one is a pseudo with the other a hard reg that is in its
1590 own register class, set the cost of that register class to -1. */
1592 if ((set = single_set (insn)) != 0
1593 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1594 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1595 for (i = 0; i <= 1; i++)
1596 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1598 int regno = REGNO (ops[!i]);
1599 enum machine_mode mode = GET_MODE (ops[!i]);
1603 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0
1604 && (reg_class_size[(unsigned char) reg_pref[regno].prefclass]
1605 == CLASS_MAX_NREGS (reg_pref[regno].prefclass, mode)))
1606 op_costs[i].cost[(unsigned char) reg_pref[regno].prefclass] = -1;
1607 else if (regno < FIRST_PSEUDO_REGISTER)
1608 for (class = 0; class < N_REG_CLASSES; class++)
1609 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1610 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1612 if (reg_class_size[class] == 1)
1613 op_costs[i].cost[class] = -1;
1616 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1618 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1622 if (nr == HARD_REGNO_NREGS(regno,mode))
1623 op_costs[i].cost[class] = -1;
1629 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1630 TO_P is zero) a register of class CLASS in mode MODE.
1632 X must not be a pseudo. */
1635 copy_cost (x, mode, class, to_p)
1637 enum machine_mode mode;
1638 enum reg_class class;
1641 #ifdef HAVE_SECONDARY_RELOADS
1642 enum reg_class secondary_class = NO_REGS;
1645 /* If X is a SCRATCH, there is actually nothing to move since we are
1646 assuming optimal allocation. */
1648 if (GET_CODE (x) == SCRATCH)
1651 /* Get the class we will actually use for a reload. */
1652 class = PREFERRED_RELOAD_CLASS (x, class);
1654 #ifdef HAVE_SECONDARY_RELOADS
1655 /* If we need a secondary reload (we assume here that we are using
1656 the secondary reload as an intermediate, not a scratch register), the
1657 cost is that to load the input into the intermediate register, then
1658 to copy them. We use a special value of TO_P to avoid recursion. */
1660 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1662 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1665 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1667 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1670 if (secondary_class != NO_REGS)
1671 return (move_cost[(int) secondary_class][(int) class]
1672 + copy_cost (x, mode, secondary_class, 2));
1673 #endif /* HAVE_SECONDARY_RELOADS */
1675 /* For memory, use the memory move cost, for (hard) registers, use the
1676 cost to move between the register classes, and use 2 for everything
1677 else (constants). */
1679 if (GET_CODE (x) == MEM || class == NO_REGS)
1680 return MEMORY_MOVE_COST (mode, class, to_p);
1682 else if (GET_CODE (x) == REG)
1683 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1686 /* If this is a constant, we may eventually want to call rtx_cost here. */
1690 /* Record the pseudo registers we must reload into hard registers
1691 in a subexpression of a memory address, X.
1693 CLASS is the class that the register needs to be in and is either
1694 BASE_REG_CLASS or INDEX_REG_CLASS.
1696 SCALE is twice the amount to multiply the cost by (it is twice so we
1697 can represent half-cost adjustments). */
1700 record_address_regs (x, class, scale)
1702 enum reg_class class;
1705 register enum rtx_code code = GET_CODE (x);
1718 /* When we have an address that is a sum,
1719 we must determine whether registers are "base" or "index" regs.
1720 If there is a sum of two registers, we must choose one to be
1721 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1722 to make a good choice most of the time. We only need to do this
1723 on machines that can have two registers in an address and where
1724 the base and index register classes are different.
1726 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1727 that seems bogus since it should only be set when we are sure
1728 the register is being used as a pointer. */
1731 rtx arg0 = XEXP (x, 0);
1732 rtx arg1 = XEXP (x, 1);
1733 register enum rtx_code code0 = GET_CODE (arg0);
1734 register enum rtx_code code1 = GET_CODE (arg1);
1736 /* Look inside subregs. */
1737 if (code0 == SUBREG)
1738 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1739 if (code1 == SUBREG)
1740 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1742 /* If this machine only allows one register per address, it must
1743 be in the first operand. */
1745 if (MAX_REGS_PER_ADDRESS == 1)
1746 record_address_regs (arg0, class, scale);
1748 /* If index and base registers are the same on this machine, just
1749 record registers in any non-constant operands. We assume here,
1750 as well as in the tests below, that all addresses are in
1753 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1755 record_address_regs (arg0, class, scale);
1756 if (! CONSTANT_P (arg1))
1757 record_address_regs (arg1, class, scale);
1760 /* If the second operand is a constant integer, it doesn't change
1761 what class the first operand must be. */
1763 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1764 record_address_regs (arg0, class, scale);
1766 /* If the second operand is a symbolic constant, the first operand
1767 must be an index register. */
1769 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1770 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1772 /* If both operands are registers but one is already a hard register
1773 of index or base class, give the other the class that the hard
1776 #ifdef REG_OK_FOR_BASE_P
1777 else if (code0 == REG && code1 == REG
1778 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1779 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1780 record_address_regs (arg1,
1781 REG_OK_FOR_BASE_P (arg0)
1782 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1784 else if (code0 == REG && code1 == REG
1785 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1786 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1787 record_address_regs (arg0,
1788 REG_OK_FOR_BASE_P (arg1)
1789 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1793 /* If one operand is known to be a pointer, it must be the base
1794 with the other operand the index. Likewise if the other operand
1797 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1800 record_address_regs (arg0, BASE_REG_CLASS, scale);
1801 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1803 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1806 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1807 record_address_regs (arg1, BASE_REG_CLASS, scale);
1810 /* Otherwise, count equal chances that each might be a base
1811 or index register. This case should be rare. */
1815 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1816 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1817 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1818 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1827 /* Double the importance of a pseudo register that is incremented
1828 or decremented, since it would take two extra insns
1829 if it ends up in the wrong place. If the operand is a pseudo,
1830 show it is being used in an INC_DEC context. */
1832 #ifdef FORBIDDEN_INC_DEC_CLASSES
1833 if (GET_CODE (XEXP (x, 0)) == REG
1834 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1835 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1838 record_address_regs (XEXP (x, 0), class, 2 * scale);
1843 register struct costs *pp = &costs[REGNO (x)];
1846 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1848 for (i = 0; i < N_REG_CLASSES; i++)
1849 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1855 register const char *fmt = GET_RTX_FORMAT (code);
1857 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1859 record_address_regs (XEXP (x, i), class, scale);
1864 #ifdef FORBIDDEN_INC_DEC_CLASSES
1866 /* Return 1 if REG is valid as an auto-increment memory reference
1867 to an object of MODE. */
1870 auto_inc_dec_reg_p (reg, mode)
1872 enum machine_mode mode;
1874 if (HAVE_POST_INCREMENT
1875 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1878 if (HAVE_POST_DECREMENT
1879 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1882 if (HAVE_PRE_INCREMENT
1883 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1886 if (HAVE_PRE_DECREMENT
1887 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1894 static short *renumber = (short *)0;
1895 static size_t regno_allocated = 0;
1897 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1898 reg_scan and flow_analysis that are indexed by the register number. If
1899 NEW_P is non zero, initialize all of the registers, otherwise only
1900 initialize the new registers allocated. The same table is kept from
1901 function to function, only reallocating it when we need more room. If
1902 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1905 allocate_reg_info (num_regs, new_p, renumber_p)
1911 size_t size_renumber;
1912 size_t min = (new_p) ? 0 : reg_n_max;
1913 struct reg_info_data *reg_data;
1914 struct reg_info_data *reg_next;
1916 if (num_regs > regno_allocated)
1918 size_t old_allocated = regno_allocated;
1920 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1921 size_renumber = regno_allocated * sizeof (short);
1925 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1926 renumber = (short *) xmalloc (size_renumber);
1927 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
1928 * sizeof (struct reg_pref));
1933 VARRAY_GROW (reg_n_info, regno_allocated);
1935 if (new_p) /* if we're zapping everything, no need to realloc */
1937 free ((char *)renumber);
1938 free ((char *)reg_pref);
1939 renumber = (short *) xmalloc (size_renumber);
1940 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
1941 * sizeof (struct reg_pref));
1946 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1947 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
1949 * sizeof (struct reg_pref));
1953 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1954 + sizeof (struct reg_info_data) - sizeof (reg_info);
1955 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1956 reg_data->min_index = old_allocated;
1957 reg_data->max_index = regno_allocated - 1;
1958 reg_data->next = reg_info_head;
1959 reg_info_head = reg_data;
1962 reg_n_max = num_regs;
1965 /* Loop through each of the segments allocated for the actual
1966 reg_info pages, and set up the pointers, zero the pages, etc. */
1967 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1969 size_t min_index = reg_data->min_index;
1970 size_t max_index = reg_data->max_index;
1972 reg_next = reg_data->next;
1973 if (min <= max_index)
1975 size_t max = max_index;
1976 size_t local_min = min - min_index;
1979 if (min < min_index)
1981 if (!reg_data->used_p) /* page just allocated with calloc */
1982 reg_data->used_p = 1; /* no need to zero */
1984 bzero ((char *) ®_data->data[local_min],
1985 sizeof (reg_info) * (max - min_index - local_min + 1));
1987 for (i = min_index+local_min; i <= max; i++)
1989 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1990 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1992 reg_pref_buffer[i].prefclass = (char) NO_REGS;
1993 reg_pref_buffer[i].altclass = (char) NO_REGS;
1999 /* If {pref,alt}class have already been allocated, update the pointers to
2000 the newly realloced ones. */
2002 reg_pref = reg_pref_buffer;
2005 reg_renumber = renumber;
2007 /* Tell the regset code about the new number of registers */
2008 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2011 /* Free up the space allocated by allocate_reg_info. */
2017 struct reg_info_data *reg_data;
2018 struct reg_info_data *reg_next;
2020 VARRAY_FREE (reg_n_info);
2021 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2023 reg_next = reg_data->next;
2024 free ((char *)reg_data);
2027 free (reg_pref_buffer);
2028 reg_pref_buffer = (struct reg_pref *)0;
2029 reg_info_head = (struct reg_info_data *)0;
2030 renumber = (short *)0;
2032 regno_allocated = 0;
2036 /* This is the `regscan' pass of the compiler, run just before cse
2037 and again just before loop.
2039 It finds the first and last use of each pseudo-register
2040 and records them in the vectors regno_first_uid, regno_last_uid
2041 and counts the number of sets in the vector reg_n_sets.
2043 REPEAT is nonzero the second time this is called. */
2045 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2046 Always at least 3, since the combiner could put that many together
2047 and we want this to remain correct for all the remaining passes. */
2052 reg_scan (f, nregs, repeat)
2059 allocate_reg_info (nregs, TRUE, FALSE);
2062 for (insn = f; insn; insn = NEXT_INSN (insn))
2063 if (GET_CODE (insn) == INSN
2064 || GET_CODE (insn) == CALL_INSN
2065 || GET_CODE (insn) == JUMP_INSN)
2067 if (GET_CODE (PATTERN (insn)) == PARALLEL
2068 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2069 max_parallel = XVECLEN (PATTERN (insn), 0);
2070 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2072 if (REG_NOTES (insn))
2073 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2077 /* Update 'regscan' information by looking at the insns
2078 from FIRST to LAST. Some new REGs have been created,
2079 and any REG with number greater than OLD_MAX_REGNO is
2080 such a REG. We only update information for those. */
2083 reg_scan_update(first, last, old_max_regno)
2090 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2092 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2093 if (GET_CODE (insn) == INSN
2094 || GET_CODE (insn) == CALL_INSN
2095 || GET_CODE (insn) == JUMP_INSN)
2097 if (GET_CODE (PATTERN (insn)) == PARALLEL
2098 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2099 max_parallel = XVECLEN (PATTERN (insn), 0);
2100 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2102 if (REG_NOTES (insn))
2103 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2107 /* X is the expression to scan. INSN is the insn it appears in.
2108 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2109 We should only record information for REGs with numbers
2110 greater than or equal to MIN_REGNO. */
2113 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2119 register enum rtx_code code;
2123 code = GET_CODE (x);
2139 register int regno = REGNO (x);
2141 if (regno >= min_regno)
2143 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2145 REGNO_LAST_UID (regno) = INSN_UID (insn);
2146 if (REGNO_FIRST_UID (regno) == 0)
2147 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2154 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2156 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2161 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2165 /* Count a set of the destination if it is a register. */
2166 for (dest = SET_DEST (x);
2167 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2168 || GET_CODE (dest) == ZERO_EXTEND;
2169 dest = XEXP (dest, 0))
2172 if (GET_CODE (dest) == REG
2173 && REGNO (dest) >= min_regno)
2174 REG_N_SETS (REGNO (dest))++;
2176 /* If this is setting a pseudo from another pseudo or the sum of a
2177 pseudo and a constant integer and the other pseudo is known to be
2178 a pointer, set the destination to be a pointer as well.
2180 Likewise if it is setting the destination from an address or from a
2181 value equivalent to an address or to the sum of an address and
2184 But don't do any of this if the pseudo corresponds to a user
2185 variable since it should have already been set as a pointer based
2188 if (GET_CODE (SET_DEST (x)) == REG
2189 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2190 && REGNO (SET_DEST (x)) >= min_regno
2191 /* If the destination pseudo is set more than once, then other
2192 sets might not be to a pointer value (consider access to a
2193 union in two threads of control in the presense of global
2194 optimizations). So only set REGNO_POINTER_FLAG on the destination
2195 pseudo if this is the only set of that pseudo. */
2196 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2197 && ! REG_USERVAR_P (SET_DEST (x))
2198 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2199 && ((GET_CODE (SET_SRC (x)) == REG
2200 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2201 || ((GET_CODE (SET_SRC (x)) == PLUS
2202 || GET_CODE (SET_SRC (x)) == LO_SUM)
2203 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2204 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2205 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2206 || GET_CODE (SET_SRC (x)) == CONST
2207 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2208 || GET_CODE (SET_SRC (x)) == LABEL_REF
2209 || (GET_CODE (SET_SRC (x)) == HIGH
2210 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2211 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2212 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2213 || ((GET_CODE (SET_SRC (x)) == PLUS
2214 || GET_CODE (SET_SRC (x)) == LO_SUM)
2215 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2216 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2217 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2218 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2219 && (GET_CODE (XEXP (note, 0)) == CONST
2220 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2221 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2222 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2224 /* ... fall through ... */
2228 register const char *fmt = GET_RTX_FORMAT (code);
2230 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2233 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2234 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2237 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2238 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2245 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2249 reg_class_subset_p (c1, c2)
2250 register enum reg_class c1;
2251 register enum reg_class c2;
2253 if (c1 == c2) return 1;
2258 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2259 reg_class_contents[(int)c2],
2264 /* Return nonzero if there is a register that is in both C1 and C2. */
2267 reg_classes_intersect_p (c1, c2)
2268 register enum reg_class c1;
2269 register enum reg_class c2;
2276 if (c1 == c2) return 1;
2278 if (c1 == ALL_REGS || c2 == ALL_REGS)
2281 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2282 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2284 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2291 /* Release any memory allocated by register sets. */
2294 regset_release_memory ()
2296 bitmap_release_memory ();