1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(m, x, y) 2
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* Maximum cost of moving from a register in one class to a register in
178 another class. Based on REGISTER_MOVE_COST. */
180 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
182 /* Similar, but here we don't have to move if the first index is a subset
183 of the second so in that case the cost is zero. */
185 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
187 /* Similar, but here we don't have to move if the first index is a superset
188 of the second so in that case the cost is zero. */
190 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
192 #ifdef FORBIDDEN_INC_DEC_CLASSES
194 /* These are the classes that regs which are auto-incremented or decremented
197 static int forbidden_inc_dec_class[N_REG_CLASSES];
199 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
202 static char *in_inc_dec;
204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
206 #ifdef CLASS_CANNOT_CHANGE_MODE
208 /* These are the classes containing only registers that can be used in
209 a SUBREG expression that changes the mode of the register in some
210 way that is illegal. */
212 static int class_can_change_mode[N_REG_CLASSES];
214 /* Registers, including pseudos, which change modes in some way that
217 static regset reg_changes_mode;
219 #endif /* CLASS_CANNOT_CHANGE_MODE */
221 #ifdef HAVE_SECONDARY_RELOADS
223 /* Sample MEM values for use by memory_move_secondary_cost. */
225 static rtx top_of_stack[MAX_MACHINE_MODE];
227 #endif /* HAVE_SECONDARY_RELOADS */
229 /* Linked list of reg_info structures allocated for reg_n_info array.
230 Grouping all of the allocated structures together in one lump
231 means only one call to bzero to clear them, rather than n smaller
233 struct reg_info_data {
234 struct reg_info_data *next; /* next set of reg_info structures */
235 size_t min_index; /* minimum index # */
236 size_t max_index; /* maximum index # */
237 char used_p; /* non-zero if this has been used previously */
238 reg_info data[1]; /* beginning of the reg_info data */
241 static struct reg_info_data *reg_info_head;
243 /* No more global register variables may be declared; true once
244 regclass has been initialized. */
246 static int no_global_reg_vars = 0;
249 /* Function called only once to initialize the above data on reg usage.
250 Once this is done, various switches may override. */
257 /* First copy the register information from the initial int form into
260 for (i = 0; i < N_REG_CLASSES; i++)
262 CLEAR_HARD_REG_SET (reg_class_contents[i]);
264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
265 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
266 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
267 SET_HARD_REG_BIT (reg_class_contents[i], j);
270 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
271 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
272 memset (global_regs, 0, sizeof global_regs);
274 /* Do any additional initialization regsets may need */
275 INIT_ONCE_REG_SET ();
277 #ifdef REG_ALLOC_ORDER
278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
279 inv_reg_alloc_order[reg_alloc_order[i]] = i;
283 /* After switches have been processed, which perhaps alter
284 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
289 register unsigned int i, j;
290 register unsigned int /* enum machine_mode */ m;
291 char contains_reg_of_mode [LIM_REG_CLASSES] [MAX_MACHINE_MODE];
292 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
294 /* This macro allows the fixed or call-used registers
295 and the register classes to depend on target flags. */
297 #ifdef CONDITIONAL_REGISTER_USAGE
298 CONDITIONAL_REGISTER_USAGE;
301 /* Compute number of hard regs in each class. */
303 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
304 for (i = 0; i < N_REG_CLASSES; i++)
305 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
306 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
309 /* Initialize the table of subunions.
310 reg_class_subunion[I][J] gets the largest-numbered reg-class
311 that is contained in the union of classes I and J. */
313 for (i = 0; i < N_REG_CLASSES; i++)
315 for (j = 0; j < N_REG_CLASSES; j++)
318 register /* Declare it register if it's a scalar. */
323 COPY_HARD_REG_SET (c, reg_class_contents[i]);
324 IOR_HARD_REG_SET (c, reg_class_contents[j]);
325 for (k = 0; k < N_REG_CLASSES; k++)
327 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
332 /* keep the largest subclass */ /* SPEE 900308 */
333 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
334 reg_class_contents[(int) reg_class_subunion[i][j]],
336 reg_class_subunion[i][j] = (enum reg_class) k;
343 /* Initialize the table of superunions.
344 reg_class_superunion[I][J] gets the smallest-numbered reg-class
345 containing the union of classes I and J. */
347 for (i = 0; i < N_REG_CLASSES; i++)
349 for (j = 0; j < N_REG_CLASSES; j++)
352 register /* Declare it register if it's a scalar. */
357 COPY_HARD_REG_SET (c, reg_class_contents[i]);
358 IOR_HARD_REG_SET (c, reg_class_contents[j]);
359 for (k = 0; k < N_REG_CLASSES; k++)
360 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
363 reg_class_superunion[i][j] = (enum reg_class) k;
367 /* Initialize the tables of subclasses and superclasses of each reg class.
368 First clear the whole table, then add the elements as they are found. */
370 for (i = 0; i < N_REG_CLASSES; i++)
372 for (j = 0; j < N_REG_CLASSES; j++)
374 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
375 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
379 for (i = 0; i < N_REG_CLASSES; i++)
381 if (i == (int) NO_REGS)
384 for (j = i + 1; j < N_REG_CLASSES; j++)
388 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
392 /* Reg class I is a subclass of J.
393 Add J to the table of superclasses of I. */
394 p = ®_class_superclasses[i][0];
395 while (*p != LIM_REG_CLASSES) p++;
396 *p = (enum reg_class) j;
397 /* Add I to the table of superclasses of J. */
398 p = ®_class_subclasses[j][0];
399 while (*p != LIM_REG_CLASSES) p++;
400 *p = (enum reg_class) i;
404 /* Initialize "constant" tables. */
406 CLEAR_HARD_REG_SET (fixed_reg_set);
407 CLEAR_HARD_REG_SET (call_used_reg_set);
408 CLEAR_HARD_REG_SET (call_fixed_reg_set);
410 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
412 n_non_fixed_regs = 0;
414 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
417 SET_HARD_REG_BIT (fixed_reg_set, i);
421 if (call_used_regs[i])
422 SET_HARD_REG_BIT (call_used_reg_set, i);
423 if (call_fixed_regs[i])
424 SET_HARD_REG_BIT (call_fixed_reg_set, i);
425 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
426 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
428 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
429 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
430 for (m = 0; m < MAX_MACHINE_MODE; m++)
431 for (i = 0; i < N_REG_CLASSES; i++)
432 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
433 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
434 && HARD_REGNO_MODE_OK (j, m))
436 contains_reg_of_mode [i][m] = 1;
437 allocatable_regs_of_mode [m] = 1;
441 /* Initialize the move cost table. Find every subset of each class
442 and take the maximum cost of moving any subset to any other. */
444 for (m = 0; m < MAX_MACHINE_MODE; m++)
445 if (allocatable_regs_of_mode [m])
446 for (i = 0; i < N_REG_CLASSES; i++)
447 if (contains_reg_of_mode [i][m])
448 for (j = 0; j < N_REG_CLASSES; j++)
451 enum reg_class *p1, *p2;
453 if (!contains_reg_of_mode [j][m])
455 move_cost[m][i][j] = 65536;
456 may_move_in_cost[m][i][j] = 65536;
457 may_move_out_cost[m][i][j] = 65536;
461 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
463 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES;
465 if (*p2 != i && contains_reg_of_mode [*p1][m])
466 cost = MAX (cost, move_cost [m][i][*p2]);
468 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES;
470 if (*p1 != j && contains_reg_of_mode [*p1][m])
471 cost = MAX (cost, move_cost [m][*p1][j]);
473 move_cost[m][i][j] = cost;
475 if (reg_class_subset_p (i, j))
476 may_move_in_cost[m][i][j] = 0;
478 may_move_in_cost[m][i][j] = cost;
480 if (reg_class_subset_p (j, i))
481 may_move_out_cost[m][i][j] = 0;
483 may_move_out_cost[m][i][j] = cost;
487 for (j = 0; j < N_REG_CLASSES; j++)
489 move_cost[m][i][j] = 65536;
490 may_move_in_cost[m][i][j] = 65536;
491 may_move_out_cost[m][i][j] = 65536;
494 #ifdef CLASS_CANNOT_CHANGE_MODE
497 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
499 for (i = 0; i < N_REG_CLASSES; i++)
501 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
502 class_can_change_mode [i] = 0;
505 class_can_change_mode [i] = 1;
508 #endif /* CLASS_CANNOT_CHANGE_MODE */
511 /* Compute the table of register modes.
512 These values are used to record death information for individual registers
513 (as opposed to a multi-register mode). */
520 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
522 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
524 /* If we couldn't find a valid mode, just use the previous mode.
525 ??? One situation in which we need to do this is on the mips where
526 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
527 to use DF mode for the even registers and VOIDmode for the odd
528 (for the cpu models where the odd ones are inaccessible). */
529 if (reg_raw_mode[i] == VOIDmode)
530 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
534 /* Finish initializing the register sets and
535 initialize the register modes. */
540 /* This finishes what was started by init_reg_sets, but couldn't be done
541 until after register usage was specified. */
546 #ifdef HAVE_SECONDARY_RELOADS
548 /* Make some fake stack-frame MEM references for use in
549 memory_move_secondary_cost. */
552 for (i = 0; i < MAX_MACHINE_MODE; i++)
553 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
554 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
559 #ifdef HAVE_SECONDARY_RELOADS
561 /* Compute extra cost of moving registers to/from memory due to reloads.
562 Only needed if secondary reloads are required for memory moves. */
565 memory_move_secondary_cost (mode, class, in)
566 enum machine_mode mode;
567 enum reg_class class;
570 enum reg_class altclass;
571 int partial_cost = 0;
572 /* We need a memory reference to feed to SECONDARY... macros. */
573 /* mem may be unused even if the SECONDARY_ macros are defined. */
574 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
579 #ifdef SECONDARY_INPUT_RELOAD_CLASS
580 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
587 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
588 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
594 if (altclass == NO_REGS)
598 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
600 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
602 if (class == altclass)
603 /* This isn't simply a copy-to-temporary situation. Can't guess
604 what it is, so MEMORY_MOVE_COST really ought not to be calling
607 I'm tempted to put in an abort here, but returning this will
608 probably only give poor estimates, which is what we would've
609 had before this code anyways. */
612 /* Check if the secondary reload register will also need a
614 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
618 /* Return a machine mode that is legitimate for hard reg REGNO and large
619 enough to save nregs. If we can't find one, return VOIDmode. */
622 choose_hard_reg_mode (regno, nregs)
623 unsigned int regno ATTRIBUTE_UNUSED;
626 enum machine_mode found_mode = VOIDmode, mode;
628 /* We first look for the largest integer mode that can be validly
629 held in REGNO. If none, we look for the largest floating-point mode.
630 If we still didn't find a valid mode, try CCmode. */
632 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
634 mode = GET_MODE_WIDER_MODE (mode))
635 if (HARD_REGNO_NREGS (regno, mode) == nregs
636 && HARD_REGNO_MODE_OK (regno, mode))
639 if (found_mode != VOIDmode)
642 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
644 mode = GET_MODE_WIDER_MODE (mode))
645 if (HARD_REGNO_NREGS (regno, mode) == nregs
646 && HARD_REGNO_MODE_OK (regno, mode))
649 if (found_mode != VOIDmode)
652 /* Iterate over all of the CCmodes. */
653 for (mode = CCmode; mode < NUM_MACHINE_MODES; ++mode)
654 if (HARD_REGNO_NREGS (regno, mode) == nregs
655 && HARD_REGNO_MODE_OK (regno, mode))
658 /* We can't find a mode valid for this register. */
662 /* Specify the usage characteristics of the register named NAME.
663 It should be a fixed register if FIXED and a
664 call-used register if CALL_USED. */
667 fix_register (name, fixed, call_used)
669 int fixed, call_used;
673 /* Decode the name and update the primary form of
674 the register info. */
676 if ((i = decode_reg_name (name)) >= 0)
678 if ((i == STACK_POINTER_REGNUM
679 #ifdef HARD_FRAME_POINTER_REGNUM
680 || i == HARD_FRAME_POINTER_REGNUM
682 || i == FRAME_POINTER_REGNUM
685 && (fixed == 0 || call_used == 0))
687 static const char * const what_option[2][2] = {
688 { "call-saved", "call-used" },
689 { "no-such-option", "fixed" }};
691 error ("can't use '%s' as a %s register", name,
692 what_option[fixed][call_used]);
696 fixed_regs[i] = fixed;
697 call_used_regs[i] = call_used;
702 warning ("unknown register name: %s", name);
706 /* Mark register number I as global. */
712 if (fixed_regs[i] == 0 && no_global_reg_vars)
713 error ("global register variable follows a function definition");
717 warning ("register used for two global register variables");
721 if (call_used_regs[i] && ! fixed_regs[i])
722 warning ("call-clobbered register used for global register variable");
726 /* If already fixed, nothing else to do. */
730 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
733 SET_HARD_REG_BIT (fixed_reg_set, i);
734 SET_HARD_REG_BIT (call_used_reg_set, i);
735 SET_HARD_REG_BIT (call_fixed_reg_set, i);
738 /* Now the data and code for the `regclass' pass, which happens
739 just before local-alloc. */
741 /* The `costs' struct records the cost of using a hard register of each class
742 and of using memory for each pseudo. We use this data to set up
743 register class preferences. */
747 int cost[N_REG_CLASSES];
751 /* Structure used to record preferrences of given pseudo. */
754 /* (enum reg_class) prefclass is the preferred class. */
757 /* altclass is a register class that we should use for allocating
758 pseudo if no register in the preferred class is available.
759 If no register in this class is available, memory is preferred.
761 It might appear to be more general to have a bitmask of classes here,
762 but since it is recommended that there be a class corresponding to the
763 union of most major pair of classes, that generality is not required. */
767 /* Record the cost of each class for each pseudo. */
769 static struct costs *costs;
771 /* Initialized once, and used to initialize cost values for each insn. */
773 static struct costs init_cost;
775 /* Record preferrences of each pseudo.
776 This is available after `regclass' is run. */
778 static struct reg_pref *reg_pref;
780 /* Allocated buffers for reg_pref. */
782 static struct reg_pref *reg_pref_buffer;
784 /* Account for the fact that insns within a loop are executed very commonly,
785 but don't keep doing this as loops go too deep. */
787 static int loop_cost;
789 static rtx scan_one_insn PARAMS ((rtx, int));
790 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
791 static void dump_regclass PARAMS ((FILE *));
792 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
794 struct costs *, struct reg_pref *));
795 static int copy_cost PARAMS ((rtx, enum machine_mode,
796 enum reg_class, int));
797 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
798 #ifdef FORBIDDEN_INC_DEC_CLASSES
799 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
801 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
803 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
804 This function is sometimes called before the info has been computed.
805 When that happens, just return GENERAL_REGS, which is innocuous. */
808 reg_preferred_class (regno)
813 return (enum reg_class) reg_pref[regno].prefclass;
817 reg_alternate_class (regno)
823 return (enum reg_class) reg_pref[regno].altclass;
826 /* Initialize some global data for this pass. */
833 init_cost.mem_cost = 10000;
834 for (i = 0; i < N_REG_CLASSES; i++)
835 init_cost.cost[i] = 10000;
837 /* This prevents dump_flow_info from losing if called
838 before regclass is run. */
841 /* No more global register variables may be declared. */
842 no_global_reg_vars = 1;
845 /* Dump register costs. */
850 static const char *const reg_class_names[] = REG_CLASS_NAMES;
852 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
854 enum reg_class class;
857 fprintf (dump, " Register %i costs:", i);
858 for (class = 0; class < N_REG_CLASSES; class++)
859 fprintf (dump, " %s:%i", reg_class_names[(int) class],
860 costs[i].cost[class]);
861 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
867 /* Calculate the costs of insn operands. */
870 record_operand_costs (insn, op_costs, reg_pref)
872 struct costs *op_costs;
873 struct reg_pref *reg_pref;
875 const char *constraints[MAX_RECOG_OPERANDS];
876 enum machine_mode modes[MAX_RECOG_OPERANDS];
879 for (i = 0; i < recog_data.n_operands; i++)
881 constraints[i] = recog_data.constraints[i];
882 modes[i] = recog_data.operand_mode[i];
885 /* If we get here, we are set up to record the costs of all the
886 operands for this insn. Start by initializing the costs.
887 Then handle any address registers. Finally record the desired
888 classes for any pseudos, doing it twice if some pair of
889 operands are commutative. */
891 for (i = 0; i < recog_data.n_operands; i++)
893 op_costs[i] = init_cost;
895 if (GET_CODE (recog_data.operand[i]) == SUBREG)
897 rtx inner = SUBREG_REG (recog_data.operand[i]);
898 #ifdef CLASS_CANNOT_CHANGE_MODE
899 if (GET_CODE (inner) == REG
900 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
901 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
903 recog_data.operand[i] = inner;
906 if (GET_CODE (recog_data.operand[i]) == MEM)
907 record_address_regs (XEXP (recog_data.operand[i], 0),
908 BASE_REG_CLASS, loop_cost * 2);
909 else if (constraints[i][0] == 'p')
910 record_address_regs (recog_data.operand[i],
911 BASE_REG_CLASS, loop_cost * 2);
914 /* Check for commutative in a separate loop so everything will
915 have been initialized. We must do this even if one operand
916 is a constant--see addsi3 in m68k.md. */
918 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
919 if (constraints[i][0] == '%')
921 const char *xconstraints[MAX_RECOG_OPERANDS];
924 /* Handle commutative operands by swapping the constraints.
925 We assume the modes are the same. */
927 for (j = 0; j < recog_data.n_operands; j++)
928 xconstraints[j] = constraints[j];
930 xconstraints[i] = constraints[i+1];
931 xconstraints[i+1] = constraints[i];
932 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
933 recog_data.operand, modes,
934 xconstraints, insn, op_costs, reg_pref);
937 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
938 recog_data.operand, modes,
939 constraints, insn, op_costs, reg_pref);
942 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
943 time it would save code to put a certain register in a certain class.
944 PASS, when nonzero, inhibits some optimizations which need only be done
946 Return the last insn processed, so that the scan can be continued from
950 scan_one_insn (insn, pass)
954 enum rtx_code code = GET_CODE (insn);
955 enum rtx_code pat_code;
958 struct costs op_costs[MAX_RECOG_OPERANDS];
960 if (GET_RTX_CLASS (code) != 'i')
963 pat_code = GET_CODE (PATTERN (insn));
965 || pat_code == CLOBBER
966 || pat_code == ASM_INPUT
967 || pat_code == ADDR_VEC
968 || pat_code == ADDR_DIFF_VEC)
971 set = single_set (insn);
974 /* If this insn loads a parameter from its stack slot, then
975 it represents a savings, rather than a cost, if the
976 parameter is stored in memory. Record this fact. */
978 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
979 && GET_CODE (SET_SRC (set)) == MEM
980 && (note = find_reg_note (insn, REG_EQUIV,
982 && GET_CODE (XEXP (note, 0)) == MEM)
984 costs[REGNO (SET_DEST (set))].mem_cost
985 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
988 record_address_regs (XEXP (SET_SRC (set), 0),
989 BASE_REG_CLASS, loop_cost * 2);
993 /* Improve handling of two-address insns such as
994 (set X (ashift CONST Y)) where CONST must be made to
995 match X. Change it into two insns: (set X CONST)
996 (set X (ashift X Y)). If we left this for reloading, it
997 would probably get three insns because X and Y might go
998 in the same place. This prevents X and Y from receiving
1001 We can only do this if the modes of operands 0 and 1
1002 (which might not be the same) are tieable and we only need
1003 do this during our first pass. */
1005 if (pass == 0 && optimize
1006 && recog_data.n_operands >= 3
1007 && recog_data.constraints[1][0] == '0'
1008 && recog_data.constraints[1][1] == 0
1009 && CONSTANT_P (recog_data.operand[1])
1010 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1011 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1012 && GET_CODE (recog_data.operand[0]) == REG
1013 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1014 recog_data.operand_mode[1]))
1016 rtx previnsn = prev_real_insn (insn);
1018 = gen_lowpart (recog_data.operand_mode[1],
1019 recog_data.operand[0]);
1021 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1023 /* If this insn was the start of a basic block,
1024 include the new insn in that block.
1025 We need not check for code_label here;
1026 while a basic block can start with a code_label,
1027 INSN could not be at the beginning of that block. */
1028 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1031 for (b = 0; b < n_basic_blocks; b++)
1032 if (insn == BLOCK_HEAD (b))
1033 BLOCK_HEAD (b) = newinsn;
1036 /* This makes one more setting of new insns's dest. */
1037 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1039 *recog_data.operand_loc[1] = recog_data.operand[0];
1040 for (i = recog_data.n_dups - 1; i >= 0; i--)
1041 if (recog_data.dup_num[i] == 1)
1042 *recog_data.dup_loc[i] = recog_data.operand[0];
1044 return PREV_INSN (newinsn);
1047 record_operand_costs (insn, op_costs, reg_pref);
1049 /* Now add the cost for each operand to the total costs for
1052 for (i = 0; i < recog_data.n_operands; i++)
1053 if (GET_CODE (recog_data.operand[i]) == REG
1054 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1056 int regno = REGNO (recog_data.operand[i]);
1057 struct costs *p = &costs[regno], *q = &op_costs[i];
1059 p->mem_cost += q->mem_cost * loop_cost;
1060 for (j = 0; j < N_REG_CLASSES; j++)
1061 p->cost[j] += q->cost[j] * loop_cost;
1067 /* This is a pass of the compiler that scans all instructions
1068 and calculates the preferred class for each pseudo-register.
1069 This information can be accessed later by calling `reg_preferred_class'.
1070 This pass comes just before local register allocation. */
1073 regclass (f, nregs, dump)
1084 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1086 #ifdef CLASS_CANNOT_CHANGE_MODE
1087 reg_changes_mode = BITMAP_XMALLOC();
1090 #ifdef FORBIDDEN_INC_DEC_CLASSES
1092 in_inc_dec = (char *) xmalloc (nregs);
1094 /* Initialize information about which register classes can be used for
1095 pseudos that are auto-incremented or auto-decremented. It would
1096 seem better to put this in init_reg_sets, but we need to be able
1097 to allocate rtx, which we can't do that early. */
1099 for (i = 0; i < N_REG_CLASSES; i++)
1101 rtx r = gen_rtx_REG (VOIDmode, 0);
1102 enum machine_mode m;
1105 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1106 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1110 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1111 m = (enum machine_mode) ((int) m + 1))
1112 if (HARD_REGNO_MODE_OK (j, m))
1116 /* If a register is not directly suitable for an
1117 auto-increment or decrement addressing mode and
1118 requires secondary reloads, disallow its class from
1119 being used in such addresses. */
1122 #ifdef SECONDARY_RELOAD_CLASS
1123 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1126 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1127 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1130 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1131 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1136 && ! auto_inc_dec_reg_p (r, m))
1137 forbidden_inc_dec_class[i] = 1;
1141 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1143 /* Normally we scan the insns once and determine the best class to use for
1144 each register. However, if -fexpensive_optimizations are on, we do so
1145 twice, the second time using the tentative best classes to guide the
1148 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1153 fprintf (dump, "\n\nPass %i\n\n",pass);
1154 /* Zero out our accumulation of the cost of each class for each reg. */
1156 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1158 #ifdef FORBIDDEN_INC_DEC_CLASSES
1159 memset (in_inc_dec, 0, nregs);
1162 /* Scan the instructions and record each time it would
1163 save code to put a certain register in a certain class. */
1168 for (insn = f; insn; insn = NEXT_INSN (insn))
1169 insn = scan_one_insn (insn, pass);
1172 for (index = 0; index < n_basic_blocks; index++)
1174 basic_block bb = BASIC_BLOCK (index);
1176 /* Show that an insn inside a loop is likely to be executed three
1177 times more than insns outside a loop. This is much more
1178 aggressive than the assumptions made elsewhere and is being
1179 tried as an experiment. */
1183 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1184 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1186 insn = scan_one_insn (insn, pass);
1187 if (insn == bb->end)
1192 /* Now for each register look at how desirable each class is
1193 and find which class is preferred. Store that in
1194 `prefclass'. Record in `altclass' the largest register
1195 class any of whose registers is better than memory. */
1198 reg_pref = reg_pref_buffer;
1202 dump_regclass (dump);
1203 fprintf (dump,"\n");
1205 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1207 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1208 enum reg_class best = ALL_REGS, alt = NO_REGS;
1209 /* This is an enum reg_class, but we call it an int
1210 to save lots of casts. */
1212 register struct costs *p = &costs[i];
1214 /* In non-optimizing compilation REG_N_REFS is not initialized
1216 if (optimize && !REG_N_REFS (i))
1219 for (class = (int) ALL_REGS - 1; class > 0; class--)
1221 /* Ignore classes that are too small for this operand or
1222 invalid for a operand that was auto-incremented. */
1223 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1224 > reg_class_size[class]
1225 #ifdef FORBIDDEN_INC_DEC_CLASSES
1226 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1228 #ifdef CLASS_CANNOT_CHANGE_MODE
1229 || (REGNO_REG_SET_P (reg_changes_mode, i)
1230 && ! class_can_change_mode [class])
1234 else if (p->cost[class] < best_cost)
1236 best_cost = p->cost[class];
1237 best = (enum reg_class) class;
1239 else if (p->cost[class] == best_cost)
1240 best = reg_class_subunion[(int)best][class];
1243 /* Record the alternate register class; i.e., a class for which
1244 every register in it is better than using memory. If adding a
1245 class would make a smaller class (i.e., no union of just those
1246 classes exists), skip that class. The major unions of classes
1247 should be provided as a register class. Don't do this if we
1248 will be doing it again later. */
1250 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1251 for (class = 0; class < N_REG_CLASSES; class++)
1252 if (p->cost[class] < p->mem_cost
1253 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1254 > reg_class_size[(int) alt])
1255 #ifdef FORBIDDEN_INC_DEC_CLASSES
1256 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1258 #ifdef CLASS_CANNOT_CHANGE_MODE
1259 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1260 && ! class_can_change_mode [class])
1263 alt = reg_class_subunion[(int) alt][class];
1265 /* If we don't add any classes, nothing to try. */
1270 && (reg_pref[i].prefclass != (int) best
1271 || reg_pref[i].altclass != (int) alt))
1273 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1274 fprintf (dump, " Register %i", i);
1275 if (alt == ALL_REGS || best == ALL_REGS)
1276 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1277 else if (alt == NO_REGS)
1278 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1280 fprintf (dump, " pref %s, else %s\n",
1281 reg_class_names[(int) best],
1282 reg_class_names[(int) alt]);
1285 /* We cast to (int) because (char) hits bugs in some compilers. */
1286 reg_pref[i].prefclass = (int) best;
1287 reg_pref[i].altclass = (int) alt;
1291 #ifdef FORBIDDEN_INC_DEC_CLASSES
1294 #ifdef CLASS_CANNOT_CHANGE_MODE
1295 BITMAP_XFREE (reg_changes_mode);
1300 /* Record the cost of using memory or registers of various classes for
1301 the operands in INSN.
1303 N_ALTS is the number of alternatives.
1305 N_OPS is the number of operands.
1307 OPS is an array of the operands.
1309 MODES are the modes of the operands, in case any are VOIDmode.
1311 CONSTRAINTS are the constraints to use for the operands. This array
1312 is modified by this procedure.
1314 This procedure works alternative by alternative. For each alternative
1315 we assume that we will be able to allocate all pseudos to their ideal
1316 register class and calculate the cost of using that alternative. Then
1317 we compute for each operand that is a pseudo-register, the cost of
1318 having the pseudo allocated to each register class and using it in that
1319 alternative. To this cost is added the cost of the alternative.
1321 The cost of each class for this insn is its lowest cost among all the
1325 record_reg_classes (n_alts, n_ops, ops, modes,
1326 constraints, insn, op_costs, reg_pref)
1330 enum machine_mode *modes;
1331 const char **constraints;
1333 struct costs *op_costs;
1334 struct reg_pref *reg_pref;
1340 /* Process each alternative, each time minimizing an operand's cost with
1341 the cost for each operand in that alternative. */
1343 for (alt = 0; alt < n_alts; alt++)
1345 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1348 enum reg_class classes[MAX_RECOG_OPERANDS];
1349 int allows_mem[MAX_RECOG_OPERANDS];
1352 for (i = 0; i < n_ops; i++)
1354 const char *p = constraints[i];
1356 enum machine_mode mode = modes[i];
1357 int allows_addr = 0;
1361 /* Initially show we know nothing about the register class. */
1362 classes[i] = NO_REGS;
1365 /* If this operand has no constraints at all, we can conclude
1366 nothing about it since anything is valid. */
1370 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1371 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1376 /* If this alternative is only relevant when this operand
1377 matches a previous operand, we do different things depending
1378 on whether this operand is a pseudo-reg or not. We must process
1379 any modifiers for the operand before we can make this test. */
1381 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1384 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1386 /* Copy class and whether memory is allowed from the matching
1387 alternative. Then perform any needed cost computations
1388 and/or adjustments. */
1390 classes[i] = classes[j];
1391 allows_mem[i] = allows_mem[j];
1393 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1395 /* If this matches the other operand, we have no added
1397 if (rtx_equal_p (ops[j], op))
1400 /* If we can put the other operand into a register, add to
1401 the cost of this alternative the cost to copy this
1402 operand to the register used for the other operand. */
1404 else if (classes[j] != NO_REGS)
1405 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1407 else if (GET_CODE (ops[j]) != REG
1408 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1410 /* This op is a pseudo but the one it matches is not. */
1412 /* If we can't put the other operand into a register, this
1413 alternative can't be used. */
1415 if (classes[j] == NO_REGS)
1418 /* Otherwise, add to the cost of this alternative the cost
1419 to copy the other operand to the register used for this
1423 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1427 /* The costs of this operand are not the same as the other
1428 operand since move costs are not symmetric. Moreover,
1429 if we cannot tie them, this alternative needs to do a
1430 copy, which is one instruction. */
1432 struct costs *pp = &this_op_costs[i];
1434 for (class = 0; class < N_REG_CLASSES; class++)
1436 = ((recog_data.operand_type[i] != OP_OUT
1437 ? may_move_in_cost[mode][class][(int) classes[i]]
1439 + (recog_data.operand_type[i] != OP_IN
1440 ? may_move_out_cost[mode][(int) classes[i]][class]
1443 /* If the alternative actually allows memory, make things
1444 a bit cheaper since we won't need an extra insn to
1448 = ((recog_data.operand_type[i] != OP_IN
1449 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1451 + (recog_data.operand_type[i] != OP_OUT
1452 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1453 : 0) - allows_mem[i]);
1455 /* If we have assigned a class to this register in our
1456 first pass, add a cost to this alternative corresponding
1457 to what we would add if this register were not in the
1458 appropriate class. */
1462 += (may_move_in_cost[mode]
1463 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1464 [(int) classes[i]]);
1466 if (REGNO (ops[i]) != REGNO (ops[j])
1467 && ! find_reg_note (insn, REG_DEAD, op))
1470 /* This is in place of ordinary cost computation
1471 for this operand, so skip to the end of the
1472 alternative (should be just one character). */
1473 while (*p && *p++ != ',')
1481 /* Scan all the constraint letters. See if the operand matches
1482 any of the constraints. Collect the valid register classes
1483 and see if this operand accepts memory. */
1485 while (*p && (c = *p++) != ',')
1489 /* Ignore the next letter for this pass. */
1495 case '!': case '#': case '&':
1496 case '0': case '1': case '2': case '3': case '4':
1497 case '5': case '6': case '7': case '8': case '9':
1502 win = address_operand (op, GET_MODE (op));
1503 /* We know this operand is an address, so we want it to be
1504 allocated to a register that can be the base of an
1505 address, ie BASE_REG_CLASS. */
1507 = reg_class_subunion[(int) classes[i]]
1508 [(int) BASE_REG_CLASS];
1511 case 'm': case 'o': case 'V':
1512 /* It doesn't seem worth distinguishing between offsettable
1513 and non-offsettable addresses here. */
1515 if (GET_CODE (op) == MEM)
1520 if (GET_CODE (op) == MEM
1521 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1522 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1527 if (GET_CODE (op) == MEM
1528 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1529 || GET_CODE (XEXP (op, 0)) == POST_INC))
1534 #ifndef REAL_ARITHMETIC
1535 /* Match any floating double constant, but only if
1536 we can examine the bits of it reliably. */
1537 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1538 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1539 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1542 if (GET_CODE (op) == CONST_DOUBLE)
1547 if (GET_CODE (op) == CONST_DOUBLE)
1553 if (GET_CODE (op) == CONST_DOUBLE
1554 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1559 if (GET_CODE (op) == CONST_INT
1560 || (GET_CODE (op) == CONST_DOUBLE
1561 && GET_MODE (op) == VOIDmode))
1565 #ifdef LEGITIMATE_PIC_OPERAND_P
1566 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1573 if (GET_CODE (op) == CONST_INT
1574 || (GET_CODE (op) == CONST_DOUBLE
1575 && GET_MODE (op) == VOIDmode))
1587 if (GET_CODE (op) == CONST_INT
1588 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1597 if (GET_CODE (op) == MEM
1599 #ifdef LEGITIMATE_PIC_OPERAND_P
1600 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1607 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1611 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1613 = reg_class_subunion[(int) classes[i]]
1614 [(int) REG_CLASS_FROM_LETTER (c)];
1615 #ifdef EXTRA_CONSTRAINT
1616 else if (EXTRA_CONSTRAINT (op, c))
1624 /* How we account for this operand now depends on whether it is a
1625 pseudo register or not. If it is, we first check if any
1626 register classes are valid. If not, we ignore this alternative,
1627 since we want to assume that all pseudos get allocated for
1628 register preferencing. If some register class is valid, compute
1629 the costs of moving the pseudo into that class. */
1631 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1633 if (classes[i] == NO_REGS)
1635 /* We must always fail if the operand is a REG, but
1636 we did not find a suitable class.
1638 Otherwise we may perform an uninitialized read
1639 from this_op_costs after the `continue' statement
1645 struct costs *pp = &this_op_costs[i];
1647 for (class = 0; class < N_REG_CLASSES; class++)
1649 = ((recog_data.operand_type[i] != OP_OUT
1650 ? may_move_in_cost[mode][class][(int) classes[i]]
1652 + (recog_data.operand_type[i] != OP_IN
1653 ? may_move_out_cost[mode][(int) classes[i]][class]
1656 /* If the alternative actually allows memory, make things
1657 a bit cheaper since we won't need an extra insn to
1661 = ((recog_data.operand_type[i] != OP_IN
1662 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1664 + (recog_data.operand_type[i] != OP_OUT
1665 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1666 : 0) - allows_mem[i]);
1668 /* If we have assigned a class to this register in our
1669 first pass, add a cost to this alternative corresponding
1670 to what we would add if this register were not in the
1671 appropriate class. */
1675 += (may_move_in_cost[mode]
1676 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1677 [(int) classes[i]]);
1681 /* Otherwise, if this alternative wins, either because we
1682 have already determined that or if we have a hard register of
1683 the proper class, there is no cost for this alternative. */
1686 || (GET_CODE (op) == REG
1687 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1690 /* If registers are valid, the cost of this alternative includes
1691 copying the object to and/or from a register. */
1693 else if (classes[i] != NO_REGS)
1695 if (recog_data.operand_type[i] != OP_OUT)
1696 alt_cost += copy_cost (op, mode, classes[i], 1);
1698 if (recog_data.operand_type[i] != OP_IN)
1699 alt_cost += copy_cost (op, mode, classes[i], 0);
1702 /* The only other way this alternative can be used is if this is a
1703 constant that could be placed into memory. */
1705 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1706 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1714 /* Finally, update the costs with the information we've calculated
1715 about this alternative. */
1717 for (i = 0; i < n_ops; i++)
1718 if (GET_CODE (ops[i]) == REG
1719 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1721 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1722 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1724 pp->mem_cost = MIN (pp->mem_cost,
1725 (qq->mem_cost + alt_cost) * scale);
1727 for (class = 0; class < N_REG_CLASSES; class++)
1728 pp->cost[class] = MIN (pp->cost[class],
1729 (qq->cost[class] + alt_cost) * scale);
1733 /* If this insn is a single set copying operand 1 to operand 0
1734 and one operand is a pseudo with the other a hard reg or a pseudo
1735 that prefers a register that is in its own register class then
1736 we may want to adjust the cost of that register class to -1.
1738 Avoid the adjustment if the source does not die to avoid stressing of
1739 register allocator by preferrencing two coliding registers into single
1742 Also avoid the adjustment if a copy between registers of the class
1743 is expensive (ten times the cost of a default copy is considered
1744 arbitrarily expensive). This avoids losing when the preferred class
1745 is very expensive as the source of a copy instruction. */
1747 if ((set = single_set (insn)) != 0
1748 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1749 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1750 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1751 for (i = 0; i <= 1; i++)
1752 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1754 unsigned int regno = REGNO (ops[!i]);
1755 enum machine_mode mode = GET_MODE (ops[!i]);
1759 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1761 enum reg_class pref = reg_pref[regno].prefclass;
1763 if ((reg_class_size[(unsigned char) pref]
1764 == CLASS_MAX_NREGS (pref, mode))
1765 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1766 op_costs[i].cost[(unsigned char) pref] = -1;
1768 else if (regno < FIRST_PSEUDO_REGISTER)
1769 for (class = 0; class < N_REG_CLASSES; class++)
1770 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1771 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1773 if (reg_class_size[class] == 1)
1774 op_costs[i].cost[class] = -1;
1777 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1779 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1784 if (nr == HARD_REGNO_NREGS (regno,mode))
1785 op_costs[i].cost[class] = -1;
1791 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1792 TO_P is zero) a register of class CLASS in mode MODE.
1794 X must not be a pseudo. */
1797 copy_cost (x, mode, class, to_p)
1799 enum machine_mode mode ATTRIBUTE_UNUSED;
1800 enum reg_class class;
1801 int to_p ATTRIBUTE_UNUSED;
1803 #ifdef HAVE_SECONDARY_RELOADS
1804 enum reg_class secondary_class = NO_REGS;
1807 /* If X is a SCRATCH, there is actually nothing to move since we are
1808 assuming optimal allocation. */
1810 if (GET_CODE (x) == SCRATCH)
1813 /* Get the class we will actually use for a reload. */
1814 class = PREFERRED_RELOAD_CLASS (x, class);
1816 #ifdef HAVE_SECONDARY_RELOADS
1817 /* If we need a secondary reload (we assume here that we are using
1818 the secondary reload as an intermediate, not a scratch register), the
1819 cost is that to load the input into the intermediate register, then
1820 to copy them. We use a special value of TO_P to avoid recursion. */
1822 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1824 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1827 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1829 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1832 if (secondary_class != NO_REGS)
1833 return (move_cost[mode][(int) secondary_class][(int) class]
1834 + copy_cost (x, mode, secondary_class, 2));
1835 #endif /* HAVE_SECONDARY_RELOADS */
1837 /* For memory, use the memory move cost, for (hard) registers, use the
1838 cost to move between the register classes, and use 2 for everything
1839 else (constants). */
1841 if (GET_CODE (x) == MEM || class == NO_REGS)
1842 return MEMORY_MOVE_COST (mode, class, to_p);
1844 else if (GET_CODE (x) == REG)
1845 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1848 /* If this is a constant, we may eventually want to call rtx_cost here. */
1849 return COSTS_N_INSNS (1);
1852 /* Record the pseudo registers we must reload into hard registers
1853 in a subexpression of a memory address, X.
1855 CLASS is the class that the register needs to be in and is either
1856 BASE_REG_CLASS or INDEX_REG_CLASS.
1858 SCALE is twice the amount to multiply the cost by (it is twice so we
1859 can represent half-cost adjustments). */
1862 record_address_regs (x, class, scale)
1864 enum reg_class class;
1867 register enum rtx_code code = GET_CODE (x);
1880 /* When we have an address that is a sum,
1881 we must determine whether registers are "base" or "index" regs.
1882 If there is a sum of two registers, we must choose one to be
1883 the "base". Luckily, we can use the REG_POINTER to make a good
1884 choice most of the time. We only need to do this on machines
1885 that can have two registers in an address and where the base
1886 and index register classes are different.
1888 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1889 that seems bogus since it should only be set when we are sure
1890 the register is being used as a pointer. */
1893 rtx arg0 = XEXP (x, 0);
1894 rtx arg1 = XEXP (x, 1);
1895 register enum rtx_code code0 = GET_CODE (arg0);
1896 register enum rtx_code code1 = GET_CODE (arg1);
1898 /* Look inside subregs. */
1899 if (code0 == SUBREG)
1900 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1901 if (code1 == SUBREG)
1902 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1904 /* If this machine only allows one register per address, it must
1905 be in the first operand. */
1907 if (MAX_REGS_PER_ADDRESS == 1)
1908 record_address_regs (arg0, class, scale);
1910 /* If index and base registers are the same on this machine, just
1911 record registers in any non-constant operands. We assume here,
1912 as well as in the tests below, that all addresses are in
1915 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1917 record_address_regs (arg0, class, scale);
1918 if (! CONSTANT_P (arg1))
1919 record_address_regs (arg1, class, scale);
1922 /* If the second operand is a constant integer, it doesn't change
1923 what class the first operand must be. */
1925 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1926 record_address_regs (arg0, class, scale);
1928 /* If the second operand is a symbolic constant, the first operand
1929 must be an index register. */
1931 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1932 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1934 /* If both operands are registers but one is already a hard register
1935 of index or base class, give the other the class that the hard
1938 #ifdef REG_OK_FOR_BASE_P
1939 else if (code0 == REG && code1 == REG
1940 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1941 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1942 record_address_regs (arg1,
1943 REG_OK_FOR_BASE_P (arg0)
1944 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1946 else if (code0 == REG && code1 == REG
1947 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1948 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1949 record_address_regs (arg0,
1950 REG_OK_FOR_BASE_P (arg1)
1951 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1955 /* If one operand is known to be a pointer, it must be the base
1956 with the other operand the index. Likewise if the other operand
1959 else if ((code0 == REG && REG_POINTER (arg0))
1962 record_address_regs (arg0, BASE_REG_CLASS, scale);
1963 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1965 else if ((code1 == REG && REG_POINTER (arg1))
1968 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1969 record_address_regs (arg1, BASE_REG_CLASS, scale);
1972 /* Otherwise, count equal chances that each might be a base
1973 or index register. This case should be rare. */
1977 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1978 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1979 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1980 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1985 /* Double the importance of a pseudo register that is incremented
1986 or decremented, since it would take two extra insns
1987 if it ends up in the wrong place. */
1990 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
1991 if (REG_P (XEXP (XEXP (x, 1), 1)))
1992 record_address_regs (XEXP (XEXP (x, 1), 1),
1993 INDEX_REG_CLASS, 2 * scale);
2000 /* Double the importance of a pseudo register that is incremented
2001 or decremented, since it would take two extra insns
2002 if it ends up in the wrong place. If the operand is a pseudo,
2003 show it is being used in an INC_DEC context. */
2005 #ifdef FORBIDDEN_INC_DEC_CLASSES
2006 if (GET_CODE (XEXP (x, 0)) == REG
2007 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2008 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2011 record_address_regs (XEXP (x, 0), class, 2 * scale);
2016 register struct costs *pp = &costs[REGNO (x)];
2019 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2021 for (i = 0; i < N_REG_CLASSES; i++)
2022 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2028 register const char *fmt = GET_RTX_FORMAT (code);
2030 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2032 record_address_regs (XEXP (x, i), class, scale);
2037 #ifdef FORBIDDEN_INC_DEC_CLASSES
2039 /* Return 1 if REG is valid as an auto-increment memory reference
2040 to an object of MODE. */
2043 auto_inc_dec_reg_p (reg, mode)
2045 enum machine_mode mode;
2047 if (HAVE_POST_INCREMENT
2048 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2051 if (HAVE_POST_DECREMENT
2052 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2055 if (HAVE_PRE_INCREMENT
2056 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2059 if (HAVE_PRE_DECREMENT
2060 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2067 static short *renumber;
2068 static size_t regno_allocated;
2069 static unsigned int reg_n_max;
2071 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2072 reg_scan and flow_analysis that are indexed by the register number. If
2073 NEW_P is non zero, initialize all of the registers, otherwise only
2074 initialize the new registers allocated. The same table is kept from
2075 function to function, only reallocating it when we need more room. If
2076 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2079 allocate_reg_info (num_regs, new_p, renumber_p)
2085 size_t size_renumber;
2086 size_t min = (new_p) ? 0 : reg_n_max;
2087 struct reg_info_data *reg_data;
2089 if (num_regs > regno_allocated)
2091 size_t old_allocated = regno_allocated;
2093 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2094 size_renumber = regno_allocated * sizeof (short);
2098 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2099 renumber = (short *) xmalloc (size_renumber);
2100 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2101 * sizeof (struct reg_pref));
2106 VARRAY_GROW (reg_n_info, regno_allocated);
2108 if (new_p) /* if we're zapping everything, no need to realloc */
2110 free ((char *)renumber);
2111 free ((char *)reg_pref);
2112 renumber = (short *) xmalloc (size_renumber);
2113 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2114 * sizeof (struct reg_pref));
2119 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2120 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2122 * sizeof (struct reg_pref));
2126 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2127 + sizeof (struct reg_info_data) - sizeof (reg_info);
2128 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2129 reg_data->min_index = old_allocated;
2130 reg_data->max_index = regno_allocated - 1;
2131 reg_data->next = reg_info_head;
2132 reg_info_head = reg_data;
2135 reg_n_max = num_regs;
2138 /* Loop through each of the segments allocated for the actual
2139 reg_info pages, and set up the pointers, zero the pages, etc. */
2140 for (reg_data = reg_info_head;
2141 reg_data && reg_data->max_index >= min;
2142 reg_data = reg_data->next)
2144 size_t min_index = reg_data->min_index;
2145 size_t max_index = reg_data->max_index;
2146 size_t max = MIN (max_index, num_regs);
2147 size_t local_min = min - min_index;
2150 if (reg_data->min_index > num_regs)
2153 if (min < min_index)
2155 if (!reg_data->used_p) /* page just allocated with calloc */
2156 reg_data->used_p = 1; /* no need to zero */
2158 memset ((char *) ®_data->data[local_min], 0,
2159 sizeof (reg_info) * (max - min_index - local_min + 1));
2161 for (i = min_index+local_min; i <= max; i++)
2163 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2164 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2166 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2167 reg_pref_buffer[i].altclass = (char) NO_REGS;
2172 /* If {pref,alt}class have already been allocated, update the pointers to
2173 the newly realloced ones. */
2175 reg_pref = reg_pref_buffer;
2178 reg_renumber = renumber;
2180 /* Tell the regset code about the new number of registers */
2181 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2184 /* Free up the space allocated by allocate_reg_info. */
2190 struct reg_info_data *reg_data;
2191 struct reg_info_data *reg_next;
2193 VARRAY_FREE (reg_n_info);
2194 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2196 reg_next = reg_data->next;
2197 free ((char *)reg_data);
2200 free (reg_pref_buffer);
2201 reg_pref_buffer = (struct reg_pref *)0;
2202 reg_info_head = (struct reg_info_data *)0;
2203 renumber = (short *)0;
2205 regno_allocated = 0;
2209 /* This is the `regscan' pass of the compiler, run just before cse
2210 and again just before loop.
2212 It finds the first and last use of each pseudo-register
2213 and records them in the vectors regno_first_uid, regno_last_uid
2214 and counts the number of sets in the vector reg_n_sets.
2216 REPEAT is nonzero the second time this is called. */
2218 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2219 Always at least 3, since the combiner could put that many together
2220 and we want this to remain correct for all the remaining passes.
2221 This corresponds to the maximum number of times note_stores will call
2222 a function for any insn. */
2226 /* Used as a temporary to record the largest number of registers in
2227 PARALLEL in a SET_DEST. This is added to max_parallel. */
2229 static int max_set_parallel;
2232 reg_scan (f, nregs, repeat)
2235 int repeat ATTRIBUTE_UNUSED;
2239 allocate_reg_info (nregs, TRUE, FALSE);
2241 max_set_parallel = 0;
2243 for (insn = f; insn; insn = NEXT_INSN (insn))
2244 if (GET_CODE (insn) == INSN
2245 || GET_CODE (insn) == CALL_INSN
2246 || GET_CODE (insn) == JUMP_INSN)
2248 if (GET_CODE (PATTERN (insn)) == PARALLEL
2249 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2250 max_parallel = XVECLEN (PATTERN (insn), 0);
2251 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2253 if (REG_NOTES (insn))
2254 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2257 max_parallel += max_set_parallel;
2260 /* Update 'regscan' information by looking at the insns
2261 from FIRST to LAST. Some new REGs have been created,
2262 and any REG with number greater than OLD_MAX_REGNO is
2263 such a REG. We only update information for those. */
2266 reg_scan_update (first, last, old_max_regno)
2269 unsigned int old_max_regno;
2273 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2275 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2276 if (GET_CODE (insn) == INSN
2277 || GET_CODE (insn) == CALL_INSN
2278 || GET_CODE (insn) == JUMP_INSN)
2280 if (GET_CODE (PATTERN (insn)) == PARALLEL
2281 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2282 max_parallel = XVECLEN (PATTERN (insn), 0);
2283 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2285 if (REG_NOTES (insn))
2286 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2290 /* X is the expression to scan. INSN is the insn it appears in.
2291 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2292 We should only record information for REGs with numbers
2293 greater than or equal to MIN_REGNO. */
2296 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2300 unsigned int min_regno;
2302 register enum rtx_code code;
2306 code = GET_CODE (x);
2322 unsigned int regno = REGNO (x);
2324 if (regno >= min_regno)
2326 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2328 REGNO_LAST_UID (regno) = INSN_UID (insn);
2329 if (REGNO_FIRST_UID (regno) == 0)
2330 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2337 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2339 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2344 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2348 /* Count a set of the destination if it is a register. */
2349 for (dest = SET_DEST (x);
2350 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2351 || GET_CODE (dest) == ZERO_EXTEND;
2352 dest = XEXP (dest, 0))
2355 /* For a PARALLEL, record the number of things (less the usual one for a
2356 SET) that are set. */
2357 if (GET_CODE (dest) == PARALLEL)
2358 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2360 if (GET_CODE (dest) == REG
2361 && REGNO (dest) >= min_regno)
2362 REG_N_SETS (REGNO (dest))++;
2364 /* If this is setting a pseudo from another pseudo or the sum of a
2365 pseudo and a constant integer and the other pseudo is known to be
2366 a pointer, set the destination to be a pointer as well.
2368 Likewise if it is setting the destination from an address or from a
2369 value equivalent to an address or to the sum of an address and
2372 But don't do any of this if the pseudo corresponds to a user
2373 variable since it should have already been set as a pointer based
2376 if (GET_CODE (SET_DEST (x)) == REG
2377 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2378 && REGNO (SET_DEST (x)) >= min_regno
2379 /* If the destination pseudo is set more than once, then other
2380 sets might not be to a pointer value (consider access to a
2381 union in two threads of control in the presense of global
2382 optimizations). So only set REG_POINTER on the destination
2383 pseudo if this is the only set of that pseudo. */
2384 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2385 && ! REG_USERVAR_P (SET_DEST (x))
2386 && ! REG_POINTER (SET_DEST (x))
2387 && ((GET_CODE (SET_SRC (x)) == REG
2388 && REG_POINTER (SET_SRC (x)))
2389 || ((GET_CODE (SET_SRC (x)) == PLUS
2390 || GET_CODE (SET_SRC (x)) == LO_SUM)
2391 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2392 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2393 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2394 || GET_CODE (SET_SRC (x)) == CONST
2395 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2396 || GET_CODE (SET_SRC (x)) == LABEL_REF
2397 || (GET_CODE (SET_SRC (x)) == HIGH
2398 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2399 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2400 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2401 || ((GET_CODE (SET_SRC (x)) == PLUS
2402 || GET_CODE (SET_SRC (x)) == LO_SUM)
2403 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2404 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2405 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2406 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2407 && (GET_CODE (XEXP (note, 0)) == CONST
2408 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2409 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2410 REG_POINTER (SET_DEST (x)) = 1;
2412 /* ... fall through ... */
2416 register const char *fmt = GET_RTX_FORMAT (code);
2418 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2421 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2422 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2425 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2426 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2433 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2437 reg_class_subset_p (c1, c2)
2438 register enum reg_class c1;
2439 register enum reg_class c2;
2441 if (c1 == c2) return 1;
2446 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2447 reg_class_contents[(int)c2],
2452 /* Return nonzero if there is a register that is in both C1 and C2. */
2455 reg_classes_intersect_p (c1, c2)
2456 register enum reg_class c1;
2457 register enum reg_class c2;
2464 if (c1 == c2) return 1;
2466 if (c1 == ALL_REGS || c2 == ALL_REGS)
2469 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2470 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2472 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2479 /* Release any memory allocated by register sets. */
2482 regset_release_memory ()
2484 bitmap_release_memory ();