1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
32 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1 PARAMS ((void));
50 static void init_reg_modes PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs[FIRST_PSEUDO_REGISTER];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set;
75 /* Data for initializing the above. */
77 static char initial_fixed_regs[] = FIXED_REGISTERS;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs[FIRST_PSEUDO_REGISTER];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set;
94 /* Data for initializing the above. */
96 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
98 /* This is much like call_used_regs, except it doesn't have to
99 be a superset of FIXED_REGISTERS. This vector indicates
100 what is really call clobbered, and is used when defining
101 regs_invalidated_by_call. */
103 char call_really_used_regs[] =
104 #ifdef CALL_REALLY_USED_REGISTERS
105 CALL_REALLY_USED_REGISTERS;
110 /* Indexed by hard register number, contains 1 for registers that are
111 fixed use or call used registers that cannot hold quantities across
112 calls even if we are willing to save and restore them. call fixed
113 registers are a subset of call used registers. */
115 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
117 /* The same info as a HARD_REG_SET. */
119 HARD_REG_SET call_fixed_reg_set;
121 /* Number of non-fixed registers. */
123 int n_non_fixed_regs;
125 /* Indexed by hard register number, contains 1 for registers
126 that are being used for global register decls.
127 These must be exempt from ordinary flow analysis
128 and are also considered fixed. */
130 char global_regs[FIRST_PSEUDO_REGISTER];
132 /* Contains 1 for registers that are set or clobbered by calls. */
133 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
134 for someone's bright idea to have call_used_regs strictly include
135 fixed_regs. Which leaves us guessing as to the set of fixed_regs
136 that are actually preserved. We know for sure that those associated
137 with the local stack frame are safe, but scant others. */
139 HARD_REG_SET regs_invalidated_by_call;
141 /* Table of register numbers in the order in which to try to use them. */
142 #ifdef REG_ALLOC_ORDER
143 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
145 /* The inverse of reg_alloc_order. */
146 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
149 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
151 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
153 /* The same information, but as an array of unsigned ints. We copy from
154 these unsigned ints to the table above. We do this so the tm.h files
155 do not have to be aware of the wordsize for machines with <= 64 regs.
156 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
159 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
161 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
162 = REG_CLASS_CONTENTS;
164 /* For each reg class, number of regs it contains. */
166 unsigned int reg_class_size[N_REG_CLASSES];
168 /* For each reg class, table listing all the containing classes. */
170 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
172 /* For each reg class, table listing all the classes contained in it. */
174 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
176 /* For each pair of reg classes,
177 a largest reg class contained in their union. */
179 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
181 /* For each pair of reg classes,
182 the smallest reg class containing their union. */
184 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
186 /* Array containing all of the register names. Unless
187 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
189 #ifdef DEBUG_REGISTER_NAMES
190 const char * reg_names[] = REGISTER_NAMES;
193 /* For each hard register, the widest mode object that it can contain.
194 This will be a MODE_INT mode if the register can hold integers. Otherwise
195 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
198 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
200 /* 1 if class does contain register of given mode. */
202 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
204 /* Maximum cost of moving from a register in one class to a register in
205 another class. Based on REGISTER_MOVE_COST. */
207 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
209 /* Similar, but here we don't have to move if the first index is a subset
210 of the second so in that case the cost is zero. */
212 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
214 /* Similar, but here we don't have to move if the first index is a superset
215 of the second so in that case the cost is zero. */
217 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
219 #ifdef FORBIDDEN_INC_DEC_CLASSES
221 /* These are the classes that regs which are auto-incremented or decremented
224 static int forbidden_inc_dec_class[N_REG_CLASSES];
226 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
229 static char *in_inc_dec;
231 #endif /* FORBIDDEN_INC_DEC_CLASSES */
233 #ifdef CLASS_CANNOT_CHANGE_MODE
235 /* These are the classes containing only registers that can be used in
236 a SUBREG expression that changes the mode of the register in some
237 way that is illegal. */
239 static int class_can_change_mode[N_REG_CLASSES];
241 /* Registers, including pseudos, which change modes in some way that
244 static regset reg_changes_mode;
246 #endif /* CLASS_CANNOT_CHANGE_MODE */
248 #ifdef HAVE_SECONDARY_RELOADS
250 /* Sample MEM values for use by memory_move_secondary_cost. */
252 static rtx top_of_stack[MAX_MACHINE_MODE];
254 #endif /* HAVE_SECONDARY_RELOADS */
256 /* Linked list of reg_info structures allocated for reg_n_info array.
257 Grouping all of the allocated structures together in one lump
258 means only one call to bzero to clear them, rather than n smaller
260 struct reg_info_data {
261 struct reg_info_data *next; /* next set of reg_info structures */
262 size_t min_index; /* minimum index # */
263 size_t max_index; /* maximum index # */
264 char used_p; /* non-zero if this has been used previously */
265 reg_info data[1]; /* beginning of the reg_info data */
268 static struct reg_info_data *reg_info_head;
270 /* No more global register variables may be declared; true once
271 regclass has been initialized. */
273 static int no_global_reg_vars = 0;
276 /* Function called only once to initialize the above data on reg usage.
277 Once this is done, various switches may override. */
284 /* First copy the register information from the initial int form into
287 for (i = 0; i < N_REG_CLASSES; i++)
289 CLEAR_HARD_REG_SET (reg_class_contents[i]);
291 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
292 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
293 if (int_reg_class_contents[i][j / 32]
294 & ((unsigned) 1 << (j % 32)))
295 SET_HARD_REG_BIT (reg_class_contents[i], j);
298 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
299 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
300 memset (global_regs, 0, sizeof global_regs);
302 /* Do any additional initialization regsets may need */
303 INIT_ONCE_REG_SET ();
305 #ifdef REG_ALLOC_ORDER
306 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
307 inv_reg_alloc_order[reg_alloc_order[i]] = i;
311 /* After switches have been processed, which perhaps alter
312 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
317 register unsigned int i, j;
318 register unsigned int /* enum machine_mode */ m;
319 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
321 /* This macro allows the fixed or call-used registers
322 and the register classes to depend on target flags. */
324 #ifdef CONDITIONAL_REGISTER_USAGE
325 CONDITIONAL_REGISTER_USAGE;
328 /* Compute number of hard regs in each class. */
330 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
331 for (i = 0; i < N_REG_CLASSES; i++)
332 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
333 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
336 /* Initialize the table of subunions.
337 reg_class_subunion[I][J] gets the largest-numbered reg-class
338 that is contained in the union of classes I and J. */
340 for (i = 0; i < N_REG_CLASSES; i++)
342 for (j = 0; j < N_REG_CLASSES; j++)
345 register /* Declare it register if it's a scalar. */
350 COPY_HARD_REG_SET (c, reg_class_contents[i]);
351 IOR_HARD_REG_SET (c, reg_class_contents[j]);
352 for (k = 0; k < N_REG_CLASSES; k++)
354 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
359 /* keep the largest subclass */ /* SPEE 900308 */
360 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
361 reg_class_contents[(int) reg_class_subunion[i][j]],
363 reg_class_subunion[i][j] = (enum reg_class) k;
370 /* Initialize the table of superunions.
371 reg_class_superunion[I][J] gets the smallest-numbered reg-class
372 containing the union of classes I and J. */
374 for (i = 0; i < N_REG_CLASSES; i++)
376 for (j = 0; j < N_REG_CLASSES; j++)
379 register /* Declare it register if it's a scalar. */
384 COPY_HARD_REG_SET (c, reg_class_contents[i]);
385 IOR_HARD_REG_SET (c, reg_class_contents[j]);
386 for (k = 0; k < N_REG_CLASSES; k++)
387 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
390 reg_class_superunion[i][j] = (enum reg_class) k;
394 /* Initialize the tables of subclasses and superclasses of each reg class.
395 First clear the whole table, then add the elements as they are found. */
397 for (i = 0; i < N_REG_CLASSES; i++)
399 for (j = 0; j < N_REG_CLASSES; j++)
401 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
402 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
406 for (i = 0; i < N_REG_CLASSES; i++)
408 if (i == (int) NO_REGS)
411 for (j = i + 1; j < N_REG_CLASSES; j++)
415 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
419 /* Reg class I is a subclass of J.
420 Add J to the table of superclasses of I. */
421 p = ®_class_superclasses[i][0];
422 while (*p != LIM_REG_CLASSES) p++;
423 *p = (enum reg_class) j;
424 /* Add I to the table of superclasses of J. */
425 p = ®_class_subclasses[j][0];
426 while (*p != LIM_REG_CLASSES) p++;
427 *p = (enum reg_class) i;
431 /* Initialize "constant" tables. */
433 CLEAR_HARD_REG_SET (fixed_reg_set);
434 CLEAR_HARD_REG_SET (call_used_reg_set);
435 CLEAR_HARD_REG_SET (call_fixed_reg_set);
436 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
438 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
440 n_non_fixed_regs = 0;
442 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
445 SET_HARD_REG_BIT (fixed_reg_set, i);
449 if (call_used_regs[i])
450 SET_HARD_REG_BIT (call_used_reg_set, i);
451 if (call_fixed_regs[i])
452 SET_HARD_REG_BIT (call_fixed_reg_set, i);
453 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
454 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
456 /* There are a couple of fixed registers that we know are safe to
457 exclude from being clobbered by calls:
459 The frame pointer is always preserved across calls. The arg pointer
460 is if it is fixed. The stack pointer usually is, unless
461 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
462 If we are generating PIC code, the PIC offset table register is
463 preserved across calls, though the target can override that. */
465 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM)
467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
468 else if (i == HARD_FRAME_POINTER_REGNUM)
471 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
472 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
475 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
476 else if (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
479 else if (call_really_used_regs[i] || global_regs[i])
480 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
483 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
484 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
485 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
486 for (i = 0; i < N_REG_CLASSES; i++)
487 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
488 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
489 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
490 && HARD_REGNO_MODE_OK (j, m))
492 contains_reg_of_mode [i][m] = 1;
493 allocatable_regs_of_mode [m] = 1;
497 /* Initialize the move cost table. Find every subset of each class
498 and take the maximum cost of moving any subset to any other. */
500 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
501 if (allocatable_regs_of_mode [m])
503 for (i = 0; i < N_REG_CLASSES; i++)
504 if (contains_reg_of_mode [i][m])
505 for (j = 0; j < N_REG_CLASSES; j++)
508 enum reg_class *p1, *p2;
510 if (!contains_reg_of_mode [j][m])
512 move_cost[m][i][j] = 65536;
513 may_move_in_cost[m][i][j] = 65536;
514 may_move_out_cost[m][i][j] = 65536;
518 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
520 for (p2 = ®_class_subclasses[j][0];
521 *p2 != LIM_REG_CLASSES;
523 if (*p2 != i && contains_reg_of_mode [*p2][m])
524 cost = MAX (cost, move_cost [m][i][*p2]);
526 for (p1 = ®_class_subclasses[i][0];
527 *p1 != LIM_REG_CLASSES;
529 if (*p1 != j && contains_reg_of_mode [*p1][m])
530 cost = MAX (cost, move_cost [m][*p1][j]);
532 move_cost[m][i][j] = cost;
534 if (reg_class_subset_p (i, j))
535 may_move_in_cost[m][i][j] = 0;
537 may_move_in_cost[m][i][j] = cost;
539 if (reg_class_subset_p (j, i))
540 may_move_out_cost[m][i][j] = 0;
542 may_move_out_cost[m][i][j] = cost;
546 for (j = 0; j < N_REG_CLASSES; j++)
548 move_cost[m][i][j] = 65536;
549 may_move_in_cost[m][i][j] = 65536;
550 may_move_out_cost[m][i][j] = 65536;
554 #ifdef CLASS_CANNOT_CHANGE_MODE
557 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
559 for (i = 0; i < N_REG_CLASSES; i++)
561 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
562 class_can_change_mode [i] = 0;
565 class_can_change_mode [i] = 1;
568 #endif /* CLASS_CANNOT_CHANGE_MODE */
571 /* Compute the table of register modes.
572 These values are used to record death information for individual registers
573 (as opposed to a multi-register mode). */
580 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
582 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
584 /* If we couldn't find a valid mode, just use the previous mode.
585 ??? One situation in which we need to do this is on the mips where
586 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
587 to use DF mode for the even registers and VOIDmode for the odd
588 (for the cpu models where the odd ones are inaccessible). */
589 if (reg_raw_mode[i] == VOIDmode)
590 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
594 /* Finish initializing the register sets and
595 initialize the register modes. */
600 /* This finishes what was started by init_reg_sets, but couldn't be done
601 until after register usage was specified. */
606 #ifdef HAVE_SECONDARY_RELOADS
608 /* Make some fake stack-frame MEM references for use in
609 memory_move_secondary_cost. */
612 for (i = 0; i < MAX_MACHINE_MODE; i++)
613 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
614 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
619 #ifdef HAVE_SECONDARY_RELOADS
621 /* Compute extra cost of moving registers to/from memory due to reloads.
622 Only needed if secondary reloads are required for memory moves. */
625 memory_move_secondary_cost (mode, class, in)
626 enum machine_mode mode;
627 enum reg_class class;
630 enum reg_class altclass;
631 int partial_cost = 0;
632 /* We need a memory reference to feed to SECONDARY... macros. */
633 /* mem may be unused even if the SECONDARY_ macros are defined. */
634 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
639 #ifdef SECONDARY_INPUT_RELOAD_CLASS
640 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
647 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
648 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
654 if (altclass == NO_REGS)
658 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
660 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
662 if (class == altclass)
663 /* This isn't simply a copy-to-temporary situation. Can't guess
664 what it is, so MEMORY_MOVE_COST really ought not to be calling
667 I'm tempted to put in an abort here, but returning this will
668 probably only give poor estimates, which is what we would've
669 had before this code anyways. */
672 /* Check if the secondary reload register will also need a
674 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
678 /* Return a machine mode that is legitimate for hard reg REGNO and large
679 enough to save nregs. If we can't find one, return VOIDmode. */
682 choose_hard_reg_mode (regno, nregs)
683 unsigned int regno ATTRIBUTE_UNUSED;
686 unsigned int /* enum machine_mode */ m;
687 enum machine_mode found_mode = VOIDmode, mode;
689 /* We first look for the largest integer mode that can be validly
690 held in REGNO. If none, we look for the largest floating-point mode.
691 If we still didn't find a valid mode, try CCmode. */
693 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
695 mode = GET_MODE_WIDER_MODE (mode))
696 if (HARD_REGNO_NREGS (regno, mode) == nregs
697 && HARD_REGNO_MODE_OK (regno, mode))
700 if (found_mode != VOIDmode)
703 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
705 mode = GET_MODE_WIDER_MODE (mode))
706 if (HARD_REGNO_NREGS (regno, mode) == nregs
707 && HARD_REGNO_MODE_OK (regno, mode))
710 if (found_mode != VOIDmode)
713 /* Iterate over all of the CCmodes. */
714 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
716 mode = (enum machine_mode) m;
717 if (HARD_REGNO_NREGS (regno, mode) == nregs
718 && HARD_REGNO_MODE_OK (regno, mode))
722 /* We can't find a mode valid for this register. */
726 /* Specify the usage characteristics of the register named NAME.
727 It should be a fixed register if FIXED and a
728 call-used register if CALL_USED. */
731 fix_register (name, fixed, call_used)
733 int fixed, call_used;
737 /* Decode the name and update the primary form of
738 the register info. */
740 if ((i = decode_reg_name (name)) >= 0)
742 if ((i == STACK_POINTER_REGNUM
743 #ifdef HARD_FRAME_POINTER_REGNUM
744 || i == HARD_FRAME_POINTER_REGNUM
746 || i == FRAME_POINTER_REGNUM
749 && (fixed == 0 || call_used == 0))
751 static const char * const what_option[2][2] = {
752 { "call-saved", "call-used" },
753 { "no-such-option", "fixed" }};
755 error ("can't use '%s' as a %s register", name,
756 what_option[fixed][call_used]);
760 fixed_regs[i] = fixed;
761 call_used_regs[i] = call_used;
763 call_really_used_regs[i] = call_used;
768 warning ("unknown register name: %s", name);
772 /* Mark register number I as global. */
778 if (fixed_regs[i] == 0 && no_global_reg_vars)
779 error ("global register variable follows a function definition");
783 warning ("register used for two global register variables");
787 if (call_used_regs[i] && ! fixed_regs[i])
788 warning ("call-clobbered register used for global register variable");
792 /* If already fixed, nothing else to do. */
796 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
799 SET_HARD_REG_BIT (fixed_reg_set, i);
800 SET_HARD_REG_BIT (call_used_reg_set, i);
801 SET_HARD_REG_BIT (call_fixed_reg_set, i);
804 /* Now the data and code for the `regclass' pass, which happens
805 just before local-alloc. */
807 /* The `costs' struct records the cost of using a hard register of each class
808 and of using memory for each pseudo. We use this data to set up
809 register class preferences. */
813 int cost[N_REG_CLASSES];
817 /* Structure used to record preferrences of given pseudo. */
820 /* (enum reg_class) prefclass is the preferred class. */
823 /* altclass is a register class that we should use for allocating
824 pseudo if no register in the preferred class is available.
825 If no register in this class is available, memory is preferred.
827 It might appear to be more general to have a bitmask of classes here,
828 but since it is recommended that there be a class corresponding to the
829 union of most major pair of classes, that generality is not required. */
833 /* Record the cost of each class for each pseudo. */
835 static struct costs *costs;
837 /* Initialized once, and used to initialize cost values for each insn. */
839 static struct costs init_cost;
841 /* Record preferrences of each pseudo.
842 This is available after `regclass' is run. */
844 static struct reg_pref *reg_pref;
846 /* Allocated buffers for reg_pref. */
848 static struct reg_pref *reg_pref_buffer;
850 /* Frequency of executions of current insn. */
852 static int frequency;
854 static rtx scan_one_insn PARAMS ((rtx, int));
855 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
856 static void dump_regclass PARAMS ((FILE *));
857 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
859 struct costs *, struct reg_pref *));
860 static int copy_cost PARAMS ((rtx, enum machine_mode,
861 enum reg_class, int));
862 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
863 #ifdef FORBIDDEN_INC_DEC_CLASSES
864 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
866 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
868 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
869 This function is sometimes called before the info has been computed.
870 When that happens, just return GENERAL_REGS, which is innocuous. */
873 reg_preferred_class (regno)
878 return (enum reg_class) reg_pref[regno].prefclass;
882 reg_alternate_class (regno)
888 return (enum reg_class) reg_pref[regno].altclass;
891 /* Initialize some global data for this pass. */
898 init_cost.mem_cost = 10000;
899 for (i = 0; i < N_REG_CLASSES; i++)
900 init_cost.cost[i] = 10000;
902 /* This prevents dump_flow_info from losing if called
903 before regclass is run. */
906 /* No more global register variables may be declared. */
907 no_global_reg_vars = 1;
910 /* Dump register costs. */
915 static const char *const reg_class_names[] = REG_CLASS_NAMES;
917 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
919 int /* enum reg_class */ class;
922 fprintf (dump, " Register %i costs:", i);
923 for (class = 0; class < (int) N_REG_CLASSES; class++)
924 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
925 #ifdef FORBIDDEN_INC_DEC_CLASSES
927 || !forbidden_inc_dec_class[(enum reg_class) class])
929 #ifdef CLASS_CANNOT_CHANGE_MODE
930 && (!REGNO_REG_SET_P (reg_changes_mode, i)
931 || class_can_change_mode [(enum reg_class) class])
934 fprintf (dump, " %s:%i", reg_class_names[class],
935 costs[i].cost[(enum reg_class) class]);
936 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
942 /* Calculate the costs of insn operands. */
945 record_operand_costs (insn, op_costs, reg_pref)
947 struct costs *op_costs;
948 struct reg_pref *reg_pref;
950 const char *constraints[MAX_RECOG_OPERANDS];
951 enum machine_mode modes[MAX_RECOG_OPERANDS];
954 for (i = 0; i < recog_data.n_operands; i++)
956 constraints[i] = recog_data.constraints[i];
957 modes[i] = recog_data.operand_mode[i];
960 /* If we get here, we are set up to record the costs of all the
961 operands for this insn. Start by initializing the costs.
962 Then handle any address registers. Finally record the desired
963 classes for any pseudos, doing it twice if some pair of
964 operands are commutative. */
966 for (i = 0; i < recog_data.n_operands; i++)
968 op_costs[i] = init_cost;
970 if (GET_CODE (recog_data.operand[i]) == SUBREG)
972 rtx inner = SUBREG_REG (recog_data.operand[i]);
973 #ifdef CLASS_CANNOT_CHANGE_MODE
974 if (GET_CODE (inner) == REG
975 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
976 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
978 recog_data.operand[i] = inner;
981 if (GET_CODE (recog_data.operand[i]) == MEM)
982 record_address_regs (XEXP (recog_data.operand[i], 0),
983 BASE_REG_CLASS, frequency * 2);
984 else if (constraints[i][0] == 'p')
985 record_address_regs (recog_data.operand[i],
986 BASE_REG_CLASS, frequency * 2);
989 /* Check for commutative in a separate loop so everything will
990 have been initialized. We must do this even if one operand
991 is a constant--see addsi3 in m68k.md. */
993 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
994 if (constraints[i][0] == '%')
996 const char *xconstraints[MAX_RECOG_OPERANDS];
999 /* Handle commutative operands by swapping the constraints.
1000 We assume the modes are the same. */
1002 for (j = 0; j < recog_data.n_operands; j++)
1003 xconstraints[j] = constraints[j];
1005 xconstraints[i] = constraints[i+1];
1006 xconstraints[i+1] = constraints[i];
1007 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1008 recog_data.operand, modes,
1009 xconstraints, insn, op_costs, reg_pref);
1012 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1013 recog_data.operand, modes,
1014 constraints, insn, op_costs, reg_pref);
1017 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1018 time it would save code to put a certain register in a certain class.
1019 PASS, when nonzero, inhibits some optimizations which need only be done
1021 Return the last insn processed, so that the scan can be continued from
1025 scan_one_insn (insn, pass)
1029 enum rtx_code code = GET_CODE (insn);
1030 enum rtx_code pat_code;
1033 struct costs op_costs[MAX_RECOG_OPERANDS];
1035 if (GET_RTX_CLASS (code) != 'i')
1038 pat_code = GET_CODE (PATTERN (insn));
1040 || pat_code == CLOBBER
1041 || pat_code == ASM_INPUT
1042 || pat_code == ADDR_VEC
1043 || pat_code == ADDR_DIFF_VEC)
1046 set = single_set (insn);
1047 extract_insn (insn);
1049 /* If this insn loads a parameter from its stack slot, then
1050 it represents a savings, rather than a cost, if the
1051 parameter is stored in memory. Record this fact. */
1053 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1054 && GET_CODE (SET_SRC (set)) == MEM
1055 && (note = find_reg_note (insn, REG_EQUIV,
1057 && GET_CODE (XEXP (note, 0)) == MEM)
1059 costs[REGNO (SET_DEST (set))].mem_cost
1060 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1063 record_address_regs (XEXP (SET_SRC (set), 0),
1064 BASE_REG_CLASS, frequency * 2);
1068 /* Improve handling of two-address insns such as
1069 (set X (ashift CONST Y)) where CONST must be made to
1070 match X. Change it into two insns: (set X CONST)
1071 (set X (ashift X Y)). If we left this for reloading, it
1072 would probably get three insns because X and Y might go
1073 in the same place. This prevents X and Y from receiving
1076 We can only do this if the modes of operands 0 and 1
1077 (which might not be the same) are tieable and we only need
1078 do this during our first pass. */
1080 if (pass == 0 && optimize
1081 && recog_data.n_operands >= 3
1082 && recog_data.constraints[1][0] == '0'
1083 && recog_data.constraints[1][1] == 0
1084 && CONSTANT_P (recog_data.operand[1])
1085 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1086 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1087 && GET_CODE (recog_data.operand[0]) == REG
1088 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1089 recog_data.operand_mode[1]))
1091 rtx previnsn = prev_real_insn (insn);
1093 = gen_lowpart (recog_data.operand_mode[1],
1094 recog_data.operand[0]);
1096 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1098 /* If this insn was the start of a basic block,
1099 include the new insn in that block.
1100 We need not check for code_label here;
1101 while a basic block can start with a code_label,
1102 INSN could not be at the beginning of that block. */
1103 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1106 for (b = 0; b < n_basic_blocks; b++)
1107 if (insn == BLOCK_HEAD (b))
1108 BLOCK_HEAD (b) = newinsn;
1111 /* This makes one more setting of new insns's dest. */
1112 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1113 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1114 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1116 *recog_data.operand_loc[1] = recog_data.operand[0];
1117 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1118 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1119 for (i = recog_data.n_dups - 1; i >= 0; i--)
1120 if (recog_data.dup_num[i] == 1)
1122 *recog_data.dup_loc[i] = recog_data.operand[0];
1123 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1124 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1127 return PREV_INSN (newinsn);
1130 record_operand_costs (insn, op_costs, reg_pref);
1132 /* Now add the cost for each operand to the total costs for
1135 for (i = 0; i < recog_data.n_operands; i++)
1136 if (GET_CODE (recog_data.operand[i]) == REG
1137 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1139 int regno = REGNO (recog_data.operand[i]);
1140 struct costs *p = &costs[regno], *q = &op_costs[i];
1142 p->mem_cost += q->mem_cost * frequency;
1143 for (j = 0; j < N_REG_CLASSES; j++)
1144 p->cost[j] += q->cost[j] * frequency;
1150 /* This is a pass of the compiler that scans all instructions
1151 and calculates the preferred class for each pseudo-register.
1152 This information can be accessed later by calling `reg_preferred_class'.
1153 This pass comes just before local register allocation. */
1156 regclass (f, nregs, dump)
1167 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1169 #ifdef CLASS_CANNOT_CHANGE_MODE
1170 reg_changes_mode = BITMAP_XMALLOC();
1173 #ifdef FORBIDDEN_INC_DEC_CLASSES
1175 in_inc_dec = (char *) xmalloc (nregs);
1177 /* Initialize information about which register classes can be used for
1178 pseudos that are auto-incremented or auto-decremented. It would
1179 seem better to put this in init_reg_sets, but we need to be able
1180 to allocate rtx, which we can't do that early. */
1182 for (i = 0; i < N_REG_CLASSES; i++)
1184 rtx r = gen_rtx_REG (VOIDmode, 0);
1185 enum machine_mode m;
1188 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1189 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1193 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1194 m = (enum machine_mode) ((int) m + 1))
1195 if (HARD_REGNO_MODE_OK (j, m))
1199 /* If a register is not directly suitable for an
1200 auto-increment or decrement addressing mode and
1201 requires secondary reloads, disallow its class from
1202 being used in such addresses. */
1205 #ifdef SECONDARY_RELOAD_CLASS
1206 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1209 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1210 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1213 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1214 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1219 && ! auto_inc_dec_reg_p (r, m))
1220 forbidden_inc_dec_class[i] = 1;
1224 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1226 /* Normally we scan the insns once and determine the best class to use for
1227 each register. However, if -fexpensive_optimizations are on, we do so
1228 twice, the second time using the tentative best classes to guide the
1231 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1236 fprintf (dump, "\n\nPass %i\n\n",pass);
1237 /* Zero out our accumulation of the cost of each class for each reg. */
1239 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1241 #ifdef FORBIDDEN_INC_DEC_CLASSES
1242 memset (in_inc_dec, 0, nregs);
1245 /* Scan the instructions and record each time it would
1246 save code to put a certain register in a certain class. */
1250 frequency = REG_FREQ_MAX;
1251 for (insn = f; insn; insn = NEXT_INSN (insn))
1252 insn = scan_one_insn (insn, pass);
1255 for (index = 0; index < n_basic_blocks; index++)
1257 basic_block bb = BASIC_BLOCK (index);
1259 /* Show that an insn inside a loop is likely to be executed three
1260 times more than insns outside a loop. This is much more
1261 aggressive than the assumptions made elsewhere and is being
1262 tried as an experiment. */
1263 frequency = REG_FREQ_FROM_BB (bb);
1264 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1266 insn = scan_one_insn (insn, pass);
1267 if (insn == bb->end)
1272 /* Now for each register look at how desirable each class is
1273 and find which class is preferred. Store that in
1274 `prefclass'. Record in `altclass' the largest register
1275 class any of whose registers is better than memory. */
1278 reg_pref = reg_pref_buffer;
1282 dump_regclass (dump);
1283 fprintf (dump,"\n");
1285 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1287 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1288 enum reg_class best = ALL_REGS, alt = NO_REGS;
1289 /* This is an enum reg_class, but we call it an int
1290 to save lots of casts. */
1292 register struct costs *p = &costs[i];
1294 /* In non-optimizing compilation REG_N_REFS is not initialized
1296 if (optimize && !REG_N_REFS (i))
1299 for (class = (int) ALL_REGS - 1; class > 0; class--)
1301 /* Ignore classes that are too small for this operand or
1302 invalid for a operand that was auto-incremented. */
1303 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1304 #ifdef FORBIDDEN_INC_DEC_CLASSES
1305 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1307 #ifdef CLASS_CANNOT_CHANGE_MODE
1308 || (REGNO_REG_SET_P (reg_changes_mode, i)
1309 && ! class_can_change_mode [class])
1313 else if (p->cost[class] < best_cost)
1315 best_cost = p->cost[class];
1316 best = (enum reg_class) class;
1318 else if (p->cost[class] == best_cost)
1319 best = reg_class_subunion[(int)best][class];
1322 /* Record the alternate register class; i.e., a class for which
1323 every register in it is better than using memory. If adding a
1324 class would make a smaller class (i.e., no union of just those
1325 classes exists), skip that class. The major unions of classes
1326 should be provided as a register class. Don't do this if we
1327 will be doing it again later. */
1329 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1330 for (class = 0; class < N_REG_CLASSES; class++)
1331 if (p->cost[class] < p->mem_cost
1332 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1333 > reg_class_size[(int) alt])
1334 #ifdef FORBIDDEN_INC_DEC_CLASSES
1335 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1337 #ifdef CLASS_CANNOT_CHANGE_MODE
1338 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1339 && ! class_can_change_mode [class])
1342 alt = reg_class_subunion[(int) alt][class];
1344 /* If we don't add any classes, nothing to try. */
1349 && (reg_pref[i].prefclass != (int) best
1350 || reg_pref[i].altclass != (int) alt))
1352 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1353 fprintf (dump, " Register %i", i);
1354 if (alt == ALL_REGS || best == ALL_REGS)
1355 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1356 else if (alt == NO_REGS)
1357 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1359 fprintf (dump, " pref %s, else %s\n",
1360 reg_class_names[(int) best],
1361 reg_class_names[(int) alt]);
1364 /* We cast to (int) because (char) hits bugs in some compilers. */
1365 reg_pref[i].prefclass = (int) best;
1366 reg_pref[i].altclass = (int) alt;
1370 #ifdef FORBIDDEN_INC_DEC_CLASSES
1373 #ifdef CLASS_CANNOT_CHANGE_MODE
1374 BITMAP_XFREE (reg_changes_mode);
1379 /* Record the cost of using memory or registers of various classes for
1380 the operands in INSN.
1382 N_ALTS is the number of alternatives.
1384 N_OPS is the number of operands.
1386 OPS is an array of the operands.
1388 MODES are the modes of the operands, in case any are VOIDmode.
1390 CONSTRAINTS are the constraints to use for the operands. This array
1391 is modified by this procedure.
1393 This procedure works alternative by alternative. For each alternative
1394 we assume that we will be able to allocate all pseudos to their ideal
1395 register class and calculate the cost of using that alternative. Then
1396 we compute for each operand that is a pseudo-register, the cost of
1397 having the pseudo allocated to each register class and using it in that
1398 alternative. To this cost is added the cost of the alternative.
1400 The cost of each class for this insn is its lowest cost among all the
1404 record_reg_classes (n_alts, n_ops, ops, modes,
1405 constraints, insn, op_costs, reg_pref)
1409 enum machine_mode *modes;
1410 const char **constraints;
1412 struct costs *op_costs;
1413 struct reg_pref *reg_pref;
1419 /* Process each alternative, each time minimizing an operand's cost with
1420 the cost for each operand in that alternative. */
1422 for (alt = 0; alt < n_alts; alt++)
1424 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1427 enum reg_class classes[MAX_RECOG_OPERANDS];
1428 int allows_mem[MAX_RECOG_OPERANDS];
1431 for (i = 0; i < n_ops; i++)
1433 const char *p = constraints[i];
1435 enum machine_mode mode = modes[i];
1436 int allows_addr = 0;
1440 /* Initially show we know nothing about the register class. */
1441 classes[i] = NO_REGS;
1444 /* If this operand has no constraints at all, we can conclude
1445 nothing about it since anything is valid. */
1449 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1450 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1455 /* If this alternative is only relevant when this operand
1456 matches a previous operand, we do different things depending
1457 on whether this operand is a pseudo-reg or not. We must process
1458 any modifiers for the operand before we can make this test. */
1460 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1463 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1465 /* Copy class and whether memory is allowed from the matching
1466 alternative. Then perform any needed cost computations
1467 and/or adjustments. */
1469 classes[i] = classes[j];
1470 allows_mem[i] = allows_mem[j];
1472 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1474 /* If this matches the other operand, we have no added
1476 if (rtx_equal_p (ops[j], op))
1479 /* If we can put the other operand into a register, add to
1480 the cost of this alternative the cost to copy this
1481 operand to the register used for the other operand. */
1483 else if (classes[j] != NO_REGS)
1484 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1486 else if (GET_CODE (ops[j]) != REG
1487 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1489 /* This op is a pseudo but the one it matches is not. */
1491 /* If we can't put the other operand into a register, this
1492 alternative can't be used. */
1494 if (classes[j] == NO_REGS)
1497 /* Otherwise, add to the cost of this alternative the cost
1498 to copy the other operand to the register used for this
1502 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1506 /* The costs of this operand are not the same as the other
1507 operand since move costs are not symmetric. Moreover,
1508 if we cannot tie them, this alternative needs to do a
1509 copy, which is one instruction. */
1511 struct costs *pp = &this_op_costs[i];
1513 for (class = 0; class < N_REG_CLASSES; class++)
1515 = ((recog_data.operand_type[i] != OP_OUT
1516 ? may_move_in_cost[mode][class][(int) classes[i]]
1518 + (recog_data.operand_type[i] != OP_IN
1519 ? may_move_out_cost[mode][(int) classes[i]][class]
1522 /* If the alternative actually allows memory, make things
1523 a bit cheaper since we won't need an extra insn to
1527 = ((recog_data.operand_type[i] != OP_IN
1528 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1530 + (recog_data.operand_type[i] != OP_OUT
1531 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1532 : 0) - allows_mem[i]);
1534 /* If we have assigned a class to this register in our
1535 first pass, add a cost to this alternative corresponding
1536 to what we would add if this register were not in the
1537 appropriate class. */
1541 += (may_move_in_cost[mode]
1542 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1543 [(int) classes[i]]);
1545 if (REGNO (ops[i]) != REGNO (ops[j])
1546 && ! find_reg_note (insn, REG_DEAD, op))
1549 /* This is in place of ordinary cost computation
1550 for this operand, so skip to the end of the
1551 alternative (should be just one character). */
1552 while (*p && *p++ != ',')
1560 /* Scan all the constraint letters. See if the operand matches
1561 any of the constraints. Collect the valid register classes
1562 and see if this operand accepts memory. */
1564 while (*p && (c = *p++) != ',')
1568 /* Ignore the next letter for this pass. */
1574 case '!': case '#': case '&':
1575 case '0': case '1': case '2': case '3': case '4':
1576 case '5': case '6': case '7': case '8': case '9':
1581 win = address_operand (op, GET_MODE (op));
1582 /* We know this operand is an address, so we want it to be
1583 allocated to a register that can be the base of an
1584 address, ie BASE_REG_CLASS. */
1586 = reg_class_subunion[(int) classes[i]]
1587 [(int) BASE_REG_CLASS];
1590 case 'm': case 'o': case 'V':
1591 /* It doesn't seem worth distinguishing between offsettable
1592 and non-offsettable addresses here. */
1594 if (GET_CODE (op) == MEM)
1599 if (GET_CODE (op) == MEM
1600 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1601 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1606 if (GET_CODE (op) == MEM
1607 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1608 || GET_CODE (XEXP (op, 0)) == POST_INC))
1613 #ifndef REAL_ARITHMETIC
1614 /* Match any floating double constant, but only if
1615 we can examine the bits of it reliably. */
1616 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1617 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1618 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1621 if (GET_CODE (op) == CONST_DOUBLE)
1626 if (GET_CODE (op) == CONST_DOUBLE)
1632 if (GET_CODE (op) == CONST_DOUBLE
1633 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1638 if (GET_CODE (op) == CONST_INT
1639 || (GET_CODE (op) == CONST_DOUBLE
1640 && GET_MODE (op) == VOIDmode))
1644 #ifdef LEGITIMATE_PIC_OPERAND_P
1645 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1652 if (GET_CODE (op) == CONST_INT
1653 || (GET_CODE (op) == CONST_DOUBLE
1654 && GET_MODE (op) == VOIDmode))
1666 if (GET_CODE (op) == CONST_INT
1667 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1676 if (GET_CODE (op) == MEM
1678 #ifdef LEGITIMATE_PIC_OPERAND_P
1679 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1686 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1690 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1692 = reg_class_subunion[(int) classes[i]]
1693 [(int) REG_CLASS_FROM_LETTER (c)];
1694 #ifdef EXTRA_CONSTRAINT
1695 else if (EXTRA_CONSTRAINT (op, c))
1703 /* How we account for this operand now depends on whether it is a
1704 pseudo register or not. If it is, we first check if any
1705 register classes are valid. If not, we ignore this alternative,
1706 since we want to assume that all pseudos get allocated for
1707 register preferencing. If some register class is valid, compute
1708 the costs of moving the pseudo into that class. */
1710 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1712 if (classes[i] == NO_REGS)
1714 /* We must always fail if the operand is a REG, but
1715 we did not find a suitable class.
1717 Otherwise we may perform an uninitialized read
1718 from this_op_costs after the `continue' statement
1724 struct costs *pp = &this_op_costs[i];
1726 for (class = 0; class < N_REG_CLASSES; class++)
1728 = ((recog_data.operand_type[i] != OP_OUT
1729 ? may_move_in_cost[mode][class][(int) classes[i]]
1731 + (recog_data.operand_type[i] != OP_IN
1732 ? may_move_out_cost[mode][(int) classes[i]][class]
1735 /* If the alternative actually allows memory, make things
1736 a bit cheaper since we won't need an extra insn to
1740 = ((recog_data.operand_type[i] != OP_IN
1741 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1743 + (recog_data.operand_type[i] != OP_OUT
1744 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1745 : 0) - allows_mem[i]);
1747 /* If we have assigned a class to this register in our
1748 first pass, add a cost to this alternative corresponding
1749 to what we would add if this register were not in the
1750 appropriate class. */
1754 += (may_move_in_cost[mode]
1755 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1756 [(int) classes[i]]);
1760 /* Otherwise, if this alternative wins, either because we
1761 have already determined that or if we have a hard register of
1762 the proper class, there is no cost for this alternative. */
1765 || (GET_CODE (op) == REG
1766 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1769 /* If registers are valid, the cost of this alternative includes
1770 copying the object to and/or from a register. */
1772 else if (classes[i] != NO_REGS)
1774 if (recog_data.operand_type[i] != OP_OUT)
1775 alt_cost += copy_cost (op, mode, classes[i], 1);
1777 if (recog_data.operand_type[i] != OP_IN)
1778 alt_cost += copy_cost (op, mode, classes[i], 0);
1781 /* The only other way this alternative can be used is if this is a
1782 constant that could be placed into memory. */
1784 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1785 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1793 /* Finally, update the costs with the information we've calculated
1794 about this alternative. */
1796 for (i = 0; i < n_ops; i++)
1797 if (GET_CODE (ops[i]) == REG
1798 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1800 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1801 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1803 pp->mem_cost = MIN (pp->mem_cost,
1804 (qq->mem_cost + alt_cost) * scale);
1806 for (class = 0; class < N_REG_CLASSES; class++)
1807 pp->cost[class] = MIN (pp->cost[class],
1808 (qq->cost[class] + alt_cost) * scale);
1812 /* If this insn is a single set copying operand 1 to operand 0
1813 and one operand is a pseudo with the other a hard reg or a pseudo
1814 that prefers a register that is in its own register class then
1815 we may want to adjust the cost of that register class to -1.
1817 Avoid the adjustment if the source does not die to avoid stressing of
1818 register allocator by preferrencing two coliding registers into single
1821 Also avoid the adjustment if a copy between registers of the class
1822 is expensive (ten times the cost of a default copy is considered
1823 arbitrarily expensive). This avoids losing when the preferred class
1824 is very expensive as the source of a copy instruction. */
1826 if ((set = single_set (insn)) != 0
1827 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1828 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1829 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1830 for (i = 0; i <= 1; i++)
1831 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1833 unsigned int regno = REGNO (ops[!i]);
1834 enum machine_mode mode = GET_MODE (ops[!i]);
1838 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1840 enum reg_class pref = reg_pref[regno].prefclass;
1842 if ((reg_class_size[(unsigned char) pref]
1843 == CLASS_MAX_NREGS (pref, mode))
1844 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1845 op_costs[i].cost[(unsigned char) pref] = -1;
1847 else if (regno < FIRST_PSEUDO_REGISTER)
1848 for (class = 0; class < N_REG_CLASSES; class++)
1849 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1850 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1852 if (reg_class_size[class] == 1)
1853 op_costs[i].cost[class] = -1;
1856 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1858 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1863 if (nr == HARD_REGNO_NREGS (regno,mode))
1864 op_costs[i].cost[class] = -1;
1870 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1871 TO_P is zero) a register of class CLASS in mode MODE.
1873 X must not be a pseudo. */
1876 copy_cost (x, mode, class, to_p)
1878 enum machine_mode mode ATTRIBUTE_UNUSED;
1879 enum reg_class class;
1880 int to_p ATTRIBUTE_UNUSED;
1882 #ifdef HAVE_SECONDARY_RELOADS
1883 enum reg_class secondary_class = NO_REGS;
1886 /* If X is a SCRATCH, there is actually nothing to move since we are
1887 assuming optimal allocation. */
1889 if (GET_CODE (x) == SCRATCH)
1892 /* Get the class we will actually use for a reload. */
1893 class = PREFERRED_RELOAD_CLASS (x, class);
1895 #ifdef HAVE_SECONDARY_RELOADS
1896 /* If we need a secondary reload (we assume here that we are using
1897 the secondary reload as an intermediate, not a scratch register), the
1898 cost is that to load the input into the intermediate register, then
1899 to copy them. We use a special value of TO_P to avoid recursion. */
1901 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1903 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1906 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1908 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1911 if (secondary_class != NO_REGS)
1912 return (move_cost[mode][(int) secondary_class][(int) class]
1913 + copy_cost (x, mode, secondary_class, 2));
1914 #endif /* HAVE_SECONDARY_RELOADS */
1916 /* For memory, use the memory move cost, for (hard) registers, use the
1917 cost to move between the register classes, and use 2 for everything
1918 else (constants). */
1920 if (GET_CODE (x) == MEM || class == NO_REGS)
1921 return MEMORY_MOVE_COST (mode, class, to_p);
1923 else if (GET_CODE (x) == REG)
1924 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1927 /* If this is a constant, we may eventually want to call rtx_cost here. */
1928 return COSTS_N_INSNS (1);
1931 /* Record the pseudo registers we must reload into hard registers
1932 in a subexpression of a memory address, X.
1934 CLASS is the class that the register needs to be in and is either
1935 BASE_REG_CLASS or INDEX_REG_CLASS.
1937 SCALE is twice the amount to multiply the cost by (it is twice so we
1938 can represent half-cost adjustments). */
1941 record_address_regs (x, class, scale)
1943 enum reg_class class;
1946 register enum rtx_code code = GET_CODE (x);
1959 /* When we have an address that is a sum,
1960 we must determine whether registers are "base" or "index" regs.
1961 If there is a sum of two registers, we must choose one to be
1962 the "base". Luckily, we can use the REG_POINTER to make a good
1963 choice most of the time. We only need to do this on machines
1964 that can have two registers in an address and where the base
1965 and index register classes are different.
1967 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1968 that seems bogus since it should only be set when we are sure
1969 the register is being used as a pointer. */
1972 rtx arg0 = XEXP (x, 0);
1973 rtx arg1 = XEXP (x, 1);
1974 register enum rtx_code code0 = GET_CODE (arg0);
1975 register enum rtx_code code1 = GET_CODE (arg1);
1977 /* Look inside subregs. */
1978 if (code0 == SUBREG)
1979 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1980 if (code1 == SUBREG)
1981 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1983 /* If this machine only allows one register per address, it must
1984 be in the first operand. */
1986 if (MAX_REGS_PER_ADDRESS == 1)
1987 record_address_regs (arg0, class, scale);
1989 /* If index and base registers are the same on this machine, just
1990 record registers in any non-constant operands. We assume here,
1991 as well as in the tests below, that all addresses are in
1994 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1996 record_address_regs (arg0, class, scale);
1997 if (! CONSTANT_P (arg1))
1998 record_address_regs (arg1, class, scale);
2001 /* If the second operand is a constant integer, it doesn't change
2002 what class the first operand must be. */
2004 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
2005 record_address_regs (arg0, class, scale);
2007 /* If the second operand is a symbolic constant, the first operand
2008 must be an index register. */
2010 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
2011 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2013 /* If both operands are registers but one is already a hard register
2014 of index or base class, give the other the class that the hard
2017 #ifdef REG_OK_FOR_BASE_P
2018 else if (code0 == REG && code1 == REG
2019 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2020 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
2021 record_address_regs (arg1,
2022 REG_OK_FOR_BASE_P (arg0)
2023 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2025 else if (code0 == REG && code1 == REG
2026 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2027 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
2028 record_address_regs (arg0,
2029 REG_OK_FOR_BASE_P (arg1)
2030 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2034 /* If one operand is known to be a pointer, it must be the base
2035 with the other operand the index. Likewise if the other operand
2038 else if ((code0 == REG && REG_POINTER (arg0))
2041 record_address_regs (arg0, BASE_REG_CLASS, scale);
2042 record_address_regs (arg1, INDEX_REG_CLASS, scale);
2044 else if ((code1 == REG && REG_POINTER (arg1))
2047 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2048 record_address_regs (arg1, BASE_REG_CLASS, scale);
2051 /* Otherwise, count equal chances that each might be a base
2052 or index register. This case should be rare. */
2056 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
2057 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2058 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
2059 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2064 /* Double the importance of a pseudo register that is incremented
2065 or decremented, since it would take two extra insns
2066 if it ends up in the wrong place. */
2069 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
2070 if (REG_P (XEXP (XEXP (x, 1), 1)))
2071 record_address_regs (XEXP (XEXP (x, 1), 1),
2072 INDEX_REG_CLASS, 2 * scale);
2079 /* Double the importance of a pseudo register that is incremented
2080 or decremented, since it would take two extra insns
2081 if it ends up in the wrong place. If the operand is a pseudo,
2082 show it is being used in an INC_DEC context. */
2084 #ifdef FORBIDDEN_INC_DEC_CLASSES
2085 if (GET_CODE (XEXP (x, 0)) == REG
2086 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2087 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2090 record_address_regs (XEXP (x, 0), class, 2 * scale);
2095 register struct costs *pp = &costs[REGNO (x)];
2098 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2100 for (i = 0; i < N_REG_CLASSES; i++)
2101 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2107 register const char *fmt = GET_RTX_FORMAT (code);
2109 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2111 record_address_regs (XEXP (x, i), class, scale);
2116 #ifdef FORBIDDEN_INC_DEC_CLASSES
2118 /* Return 1 if REG is valid as an auto-increment memory reference
2119 to an object of MODE. */
2122 auto_inc_dec_reg_p (reg, mode)
2124 enum machine_mode mode;
2126 if (HAVE_POST_INCREMENT
2127 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2130 if (HAVE_POST_DECREMENT
2131 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2134 if (HAVE_PRE_INCREMENT
2135 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2138 if (HAVE_PRE_DECREMENT
2139 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2146 static short *renumber;
2147 static size_t regno_allocated;
2148 static unsigned int reg_n_max;
2150 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2151 reg_scan and flow_analysis that are indexed by the register number. If
2152 NEW_P is non zero, initialize all of the registers, otherwise only
2153 initialize the new registers allocated. The same table is kept from
2154 function to function, only reallocating it when we need more room. If
2155 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2158 allocate_reg_info (num_regs, new_p, renumber_p)
2164 size_t size_renumber;
2165 size_t min = (new_p) ? 0 : reg_n_max;
2166 struct reg_info_data *reg_data;
2168 if (num_regs > regno_allocated)
2170 size_t old_allocated = regno_allocated;
2172 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2173 size_renumber = regno_allocated * sizeof (short);
2177 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2178 renumber = (short *) xmalloc (size_renumber);
2179 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2180 * sizeof (struct reg_pref));
2185 VARRAY_GROW (reg_n_info, regno_allocated);
2187 if (new_p) /* if we're zapping everything, no need to realloc */
2189 free ((char *)renumber);
2190 free ((char *)reg_pref);
2191 renumber = (short *) xmalloc (size_renumber);
2192 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2193 * sizeof (struct reg_pref));
2198 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2199 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2201 * sizeof (struct reg_pref));
2205 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2206 + sizeof (struct reg_info_data) - sizeof (reg_info);
2207 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2208 reg_data->min_index = old_allocated;
2209 reg_data->max_index = regno_allocated - 1;
2210 reg_data->next = reg_info_head;
2211 reg_info_head = reg_data;
2214 reg_n_max = num_regs;
2217 /* Loop through each of the segments allocated for the actual
2218 reg_info pages, and set up the pointers, zero the pages, etc. */
2219 for (reg_data = reg_info_head;
2220 reg_data && reg_data->max_index >= min;
2221 reg_data = reg_data->next)
2223 size_t min_index = reg_data->min_index;
2224 size_t max_index = reg_data->max_index;
2225 size_t max = MIN (max_index, num_regs);
2226 size_t local_min = min - min_index;
2229 if (reg_data->min_index > num_regs)
2232 if (min < min_index)
2234 if (!reg_data->used_p) /* page just allocated with calloc */
2235 reg_data->used_p = 1; /* no need to zero */
2237 memset ((char *) ®_data->data[local_min], 0,
2238 sizeof (reg_info) * (max - min_index - local_min + 1));
2240 for (i = min_index+local_min; i <= max; i++)
2242 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2243 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2245 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2246 reg_pref_buffer[i].altclass = (char) NO_REGS;
2251 /* If {pref,alt}class have already been allocated, update the pointers to
2252 the newly realloced ones. */
2254 reg_pref = reg_pref_buffer;
2257 reg_renumber = renumber;
2259 /* Tell the regset code about the new number of registers */
2260 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2263 /* Free up the space allocated by allocate_reg_info. */
2269 struct reg_info_data *reg_data;
2270 struct reg_info_data *reg_next;
2272 VARRAY_FREE (reg_n_info);
2273 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2275 reg_next = reg_data->next;
2276 free ((char *)reg_data);
2279 free (reg_pref_buffer);
2280 reg_pref_buffer = (struct reg_pref *)0;
2281 reg_info_head = (struct reg_info_data *)0;
2282 renumber = (short *)0;
2284 regno_allocated = 0;
2288 /* This is the `regscan' pass of the compiler, run just before cse
2289 and again just before loop.
2291 It finds the first and last use of each pseudo-register
2292 and records them in the vectors regno_first_uid, regno_last_uid
2293 and counts the number of sets in the vector reg_n_sets.
2295 REPEAT is nonzero the second time this is called. */
2297 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2298 Always at least 3, since the combiner could put that many together
2299 and we want this to remain correct for all the remaining passes.
2300 This corresponds to the maximum number of times note_stores will call
2301 a function for any insn. */
2305 /* Used as a temporary to record the largest number of registers in
2306 PARALLEL in a SET_DEST. This is added to max_parallel. */
2308 static int max_set_parallel;
2311 reg_scan (f, nregs, repeat)
2314 int repeat ATTRIBUTE_UNUSED;
2318 allocate_reg_info (nregs, TRUE, FALSE);
2320 max_set_parallel = 0;
2322 for (insn = f; insn; insn = NEXT_INSN (insn))
2323 if (GET_CODE (insn) == INSN
2324 || GET_CODE (insn) == CALL_INSN
2325 || GET_CODE (insn) == JUMP_INSN)
2327 if (GET_CODE (PATTERN (insn)) == PARALLEL
2328 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2329 max_parallel = XVECLEN (PATTERN (insn), 0);
2330 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2332 if (REG_NOTES (insn))
2333 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2336 max_parallel += max_set_parallel;
2339 /* Update 'regscan' information by looking at the insns
2340 from FIRST to LAST. Some new REGs have been created,
2341 and any REG with number greater than OLD_MAX_REGNO is
2342 such a REG. We only update information for those. */
2345 reg_scan_update (first, last, old_max_regno)
2348 unsigned int old_max_regno;
2352 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2354 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2355 if (GET_CODE (insn) == INSN
2356 || GET_CODE (insn) == CALL_INSN
2357 || GET_CODE (insn) == JUMP_INSN)
2359 if (GET_CODE (PATTERN (insn)) == PARALLEL
2360 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2361 max_parallel = XVECLEN (PATTERN (insn), 0);
2362 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2364 if (REG_NOTES (insn))
2365 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2369 /* X is the expression to scan. INSN is the insn it appears in.
2370 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2371 We should only record information for REGs with numbers
2372 greater than or equal to MIN_REGNO. */
2375 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2379 unsigned int min_regno;
2381 register enum rtx_code code;
2385 code = GET_CODE (x);
2401 unsigned int regno = REGNO (x);
2403 if (regno >= min_regno)
2405 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2407 REGNO_LAST_UID (regno) = INSN_UID (insn);
2408 if (REGNO_FIRST_UID (regno) == 0)
2409 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2416 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2418 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2423 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2427 /* Count a set of the destination if it is a register. */
2428 for (dest = SET_DEST (x);
2429 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2430 || GET_CODE (dest) == ZERO_EXTEND;
2431 dest = XEXP (dest, 0))
2434 /* For a PARALLEL, record the number of things (less the usual one for a
2435 SET) that are set. */
2436 if (GET_CODE (dest) == PARALLEL)
2437 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2439 if (GET_CODE (dest) == REG
2440 && REGNO (dest) >= min_regno)
2442 REG_N_SETS (REGNO (dest))++;
2443 REG_N_REFS (REGNO (dest))++;
2446 /* If this is setting a pseudo from another pseudo or the sum of a
2447 pseudo and a constant integer and the other pseudo is known to be
2448 a pointer, set the destination to be a pointer as well.
2450 Likewise if it is setting the destination from an address or from a
2451 value equivalent to an address or to the sum of an address and
2454 But don't do any of this if the pseudo corresponds to a user
2455 variable since it should have already been set as a pointer based
2458 if (GET_CODE (SET_DEST (x)) == REG
2459 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2460 && REGNO (SET_DEST (x)) >= min_regno
2461 /* If the destination pseudo is set more than once, then other
2462 sets might not be to a pointer value (consider access to a
2463 union in two threads of control in the presense of global
2464 optimizations). So only set REG_POINTER on the destination
2465 pseudo if this is the only set of that pseudo. */
2466 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2467 && ! REG_USERVAR_P (SET_DEST (x))
2468 && ! REG_POINTER (SET_DEST (x))
2469 && ((GET_CODE (SET_SRC (x)) == REG
2470 && REG_POINTER (SET_SRC (x)))
2471 || ((GET_CODE (SET_SRC (x)) == PLUS
2472 || GET_CODE (SET_SRC (x)) == LO_SUM)
2473 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2474 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2475 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2476 || GET_CODE (SET_SRC (x)) == CONST
2477 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2478 || GET_CODE (SET_SRC (x)) == LABEL_REF
2479 || (GET_CODE (SET_SRC (x)) == HIGH
2480 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2481 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2482 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2483 || ((GET_CODE (SET_SRC (x)) == PLUS
2484 || GET_CODE (SET_SRC (x)) == LO_SUM)
2485 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2486 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2487 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2488 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2489 && (GET_CODE (XEXP (note, 0)) == CONST
2490 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2491 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2492 REG_POINTER (SET_DEST (x)) = 1;
2494 /* ... fall through ... */
2498 register const char *fmt = GET_RTX_FORMAT (code);
2500 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2503 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2504 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2507 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2508 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2515 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2519 reg_class_subset_p (c1, c2)
2520 register enum reg_class c1;
2521 register enum reg_class c2;
2523 if (c1 == c2) return 1;
2528 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2529 reg_class_contents[(int)c2],
2534 /* Return nonzero if there is a register that is in both C1 and C2. */
2537 reg_classes_intersect_p (c1, c2)
2538 register enum reg_class c1;
2539 register enum reg_class c2;
2546 if (c1 == c2) return 1;
2548 if (c1 == ALL_REGS || c2 == ALL_REGS)
2551 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2552 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2554 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2561 /* Release any memory allocated by register sets. */
2564 regset_release_memory ()
2566 bitmap_release_memory ();