1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
43 #ifndef REGISTER_MOVE_COST
44 #define REGISTER_MOVE_COST(x, y) 2
47 static void init_reg_sets_1 PROTO((void));
48 static void init_reg_modes PROTO((void));
50 /* If we have auto-increment or auto-decrement and we can have secondary
51 reloads, we are not allowed to use classes requiring secondary
52 reloads for pseudos auto-incremented since reload can't handle it. */
55 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
56 #define FORBIDDEN_INC_DEC_CLASSES
60 /* Register tables used by many passes. */
62 /* Indexed by hard register number, contains 1 for registers
63 that are fixed use (stack pointer, pc, frame pointer, etc.).
64 These are the registers that cannot be used to allocate
65 a pseudo reg for general use. */
67 char fixed_regs[FIRST_PSEUDO_REGISTER];
69 /* Same info as a HARD_REG_SET. */
71 HARD_REG_SET fixed_reg_set;
73 /* Data for initializing the above. */
75 static char initial_fixed_regs[] = FIXED_REGISTERS;
77 /* Indexed by hard register number, contains 1 for registers
78 that are fixed use or are clobbered by function calls.
79 These are the registers that cannot be used to allocate
80 a pseudo reg whose life crosses calls unless we are able
81 to save/restore them across the calls. */
83 char call_used_regs[FIRST_PSEUDO_REGISTER];
85 /* Same info as a HARD_REG_SET. */
87 HARD_REG_SET call_used_reg_set;
89 /* HARD_REG_SET of registers we want to avoid caller saving. */
90 HARD_REG_SET losing_caller_save_reg_set;
92 /* Data for initializing the above. */
94 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
96 /* Indexed by hard register number, contains 1 for registers that are
97 fixed use or call used registers that cannot hold quantities across
98 calls even if we are willing to save and restore them. call fixed
99 registers are a subset of call used registers. */
101 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
103 /* The same info as a HARD_REG_SET. */
105 HARD_REG_SET call_fixed_reg_set;
107 /* Number of non-fixed registers. */
109 int n_non_fixed_regs;
111 /* Indexed by hard register number, contains 1 for registers
112 that are being used for global register decls.
113 These must be exempt from ordinary flow analysis
114 and are also considered fixed. */
116 char global_regs[FIRST_PSEUDO_REGISTER];
118 /* Table of register numbers in the order in which to try to use them. */
119 #ifdef REG_ALLOC_ORDER
120 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
122 /* The inverse of reg_alloc_order. */
123 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
126 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
128 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
130 /* The same information, but as an array of unsigned ints. We copy from
131 these unsigned ints to the table above. We do this so the tm.h files
132 do not have to be aware of the wordsize for machines with <= 64 regs. */
135 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
137 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
138 = REG_CLASS_CONTENTS;
140 /* For each reg class, number of regs it contains. */
142 int reg_class_size[N_REG_CLASSES];
144 /* For each reg class, table listing all the containing classes. */
146 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each reg class, table listing all the classes contained in it. */
150 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
152 /* For each pair of reg classes,
153 a largest reg class contained in their union. */
155 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
157 /* For each pair of reg classes,
158 the smallest reg class containing their union. */
160 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
162 /* Array containing all of the register names */
164 const char *reg_names[] = REGISTER_NAMES;
166 /* For each hard register, the widest mode object that it can contain.
167 This will be a MODE_INT mode if the register can hold integers. Otherwise
168 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
171 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
173 /* Maximum cost of moving from a register in one class to a register in
174 another class. Based on REGISTER_MOVE_COST. */
176 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
178 /* Similar, but here we don't have to move if the first index is a subset
179 of the second so in that case the cost is zero. */
181 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
183 /* Similar, but here we don't have to move if the first index is a superset
184 of the second so in that case the cost is zero. */
186 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
188 #ifdef FORBIDDEN_INC_DEC_CLASSES
190 /* These are the classes that regs which are auto-incremented or decremented
193 static int forbidden_inc_dec_class[N_REG_CLASSES];
195 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
198 static char *in_inc_dec;
200 #endif /* FORBIDDEN_INC_DEC_CLASSES */
202 #ifdef HAVE_SECONDARY_RELOADS
204 /* Sample MEM values for use by memory_move_secondary_cost. */
206 static rtx top_of_stack[MAX_MACHINE_MODE];
208 #endif /* HAVE_SECONDARY_RELOADS */
210 /* Linked list of reg_info structures allocated for reg_n_info array.
211 Grouping all of the allocated structures together in one lump
212 means only one call to bzero to clear them, rather than n smaller
214 struct reg_info_data {
215 struct reg_info_data *next; /* next set of reg_info structures */
216 size_t min_index; /* minimum index # */
217 size_t max_index; /* maximum index # */
218 char used_p; /* non-zero if this has been used previously */
219 reg_info data[1]; /* beginning of the reg_info data */
222 static struct reg_info_data *reg_info_head;
224 /* No more global register variables may be declared; true once
225 regclass has been initialized. */
227 static int no_global_reg_vars = 0;
230 /* Function called only once to initialize the above data on reg usage.
231 Once this is done, various switches may override. */
238 /* First copy the register information from the initial int form into
241 for (i = 0; i < N_REG_CLASSES; i++)
243 CLEAR_HARD_REG_SET (reg_class_contents[i]);
245 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
246 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
247 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
248 SET_HARD_REG_BIT (reg_class_contents[i], j);
251 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
252 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
253 bzero (global_regs, sizeof global_regs);
255 /* Do any additional initialization regsets may need */
256 INIT_ONCE_REG_SET ();
258 #ifdef REG_ALLOC_ORDER
259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
260 inv_reg_alloc_order[reg_alloc_order[i]] = i;
264 /* After switches have been processed, which perhaps alter
265 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
270 register unsigned int i, j;
272 /* This macro allows the fixed or call-used registers
273 and the register classes to depend on target flags. */
275 #ifdef CONDITIONAL_REGISTER_USAGE
276 CONDITIONAL_REGISTER_USAGE;
279 /* Compute number of hard regs in each class. */
281 bzero ((char *) reg_class_size, sizeof reg_class_size);
282 for (i = 0; i < N_REG_CLASSES; i++)
283 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
284 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
287 /* Initialize the table of subunions.
288 reg_class_subunion[I][J] gets the largest-numbered reg-class
289 that is contained in the union of classes I and J. */
291 for (i = 0; i < N_REG_CLASSES; i++)
293 for (j = 0; j < N_REG_CLASSES; j++)
296 register /* Declare it register if it's a scalar. */
301 COPY_HARD_REG_SET (c, reg_class_contents[i]);
302 IOR_HARD_REG_SET (c, reg_class_contents[j]);
303 for (k = 0; k < N_REG_CLASSES; k++)
305 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
310 /* keep the largest subclass */ /* SPEE 900308 */
311 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
312 reg_class_contents[(int) reg_class_subunion[i][j]],
314 reg_class_subunion[i][j] = (enum reg_class) k;
321 /* Initialize the table of superunions.
322 reg_class_superunion[I][J] gets the smallest-numbered reg-class
323 containing the union of classes I and J. */
325 for (i = 0; i < N_REG_CLASSES; i++)
327 for (j = 0; j < N_REG_CLASSES; j++)
330 register /* Declare it register if it's a scalar. */
335 COPY_HARD_REG_SET (c, reg_class_contents[i]);
336 IOR_HARD_REG_SET (c, reg_class_contents[j]);
337 for (k = 0; k < N_REG_CLASSES; k++)
338 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
341 reg_class_superunion[i][j] = (enum reg_class) k;
345 /* Initialize the tables of subclasses and superclasses of each reg class.
346 First clear the whole table, then add the elements as they are found. */
348 for (i = 0; i < N_REG_CLASSES; i++)
350 for (j = 0; j < N_REG_CLASSES; j++)
352 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
353 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
357 for (i = 0; i < N_REG_CLASSES; i++)
359 if (i == (int) NO_REGS)
362 for (j = i + 1; j < N_REG_CLASSES; j++)
366 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
370 /* Reg class I is a subclass of J.
371 Add J to the table of superclasses of I. */
372 p = ®_class_superclasses[i][0];
373 while (*p != LIM_REG_CLASSES) p++;
374 *p = (enum reg_class) j;
375 /* Add I to the table of superclasses of J. */
376 p = ®_class_subclasses[j][0];
377 while (*p != LIM_REG_CLASSES) p++;
378 *p = (enum reg_class) i;
382 /* Initialize "constant" tables. */
384 CLEAR_HARD_REG_SET (fixed_reg_set);
385 CLEAR_HARD_REG_SET (call_used_reg_set);
386 CLEAR_HARD_REG_SET (call_fixed_reg_set);
388 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
390 n_non_fixed_regs = 0;
392 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
395 SET_HARD_REG_BIT (fixed_reg_set, i);
399 if (call_used_regs[i])
400 SET_HARD_REG_BIT (call_used_reg_set, i);
401 if (call_fixed_regs[i])
402 SET_HARD_REG_BIT (call_fixed_reg_set, i);
403 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
404 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
407 /* Initialize the move cost table. Find every subset of each class
408 and take the maximum cost of moving any subset to any other. */
410 for (i = 0; i < N_REG_CLASSES; i++)
411 for (j = 0; j < N_REG_CLASSES; j++)
413 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
414 enum reg_class *p1, *p2;
416 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
418 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
420 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
423 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
425 for (p2 = ®_class_subclasses[j][0];
426 *p2 != LIM_REG_CLASSES; p2++)
428 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
431 move_cost[i][j] = cost;
433 if (reg_class_subset_p (i, j))
434 may_move_in_cost[i][j] = 0;
436 may_move_in_cost[i][j] = cost;
438 if (reg_class_subset_p (j, i))
439 may_move_out_cost[i][j] = 0;
441 may_move_out_cost[i][j] = cost;
445 /* Compute the table of register modes.
446 These values are used to record death information for individual registers
447 (as opposed to a multi-register mode). */
454 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
456 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
458 /* If we couldn't find a valid mode, just use the previous mode.
459 ??? One situation in which we need to do this is on the mips where
460 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
461 to use DF mode for the even registers and VOIDmode for the odd
462 (for the cpu models where the odd ones are inaccessible). */
463 if (reg_raw_mode[i] == VOIDmode)
464 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
468 /* Finish initializing the register sets and
469 initialize the register modes. */
474 /* This finishes what was started by init_reg_sets, but couldn't be done
475 until after register usage was specified. */
480 #ifdef HAVE_SECONDARY_RELOADS
482 /* Make some fake stack-frame MEM references for use in
483 memory_move_secondary_cost. */
485 for (i = 0; i < MAX_MACHINE_MODE; i++)
486 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
487 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
492 #ifdef HAVE_SECONDARY_RELOADS
494 /* Compute extra cost of moving registers to/from memory due to reloads.
495 Only needed if secondary reloads are required for memory moves. */
498 memory_move_secondary_cost (mode, class, in)
499 enum machine_mode mode;
500 enum reg_class class;
503 enum reg_class altclass;
504 int partial_cost = 0;
505 /* We need a memory reference to feed to SECONDARY... macros. */
506 rtx mem = top_of_stack[(int) mode];
510 #ifdef SECONDARY_INPUT_RELOAD_CLASS
511 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
518 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
519 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
525 if (altclass == NO_REGS)
529 partial_cost = REGISTER_MOVE_COST (altclass, class);
531 partial_cost = REGISTER_MOVE_COST (class, altclass);
533 if (class == altclass)
534 /* This isn't simply a copy-to-temporary situation. Can't guess
535 what it is, so MEMORY_MOVE_COST really ought not to be calling
538 I'm tempted to put in an abort here, but returning this will
539 probably only give poor estimates, which is what we would've
540 had before this code anyways. */
543 /* Check if the secondary reload register will also need a
545 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
549 /* Return a machine mode that is legitimate for hard reg REGNO and large
550 enough to save nregs. If we can't find one, return VOIDmode. */
553 choose_hard_reg_mode (regno, nregs)
557 enum machine_mode found_mode = VOIDmode, mode;
559 /* We first look for the largest integer mode that can be validly
560 held in REGNO. If none, we look for the largest floating-point mode.
561 If we still didn't find a valid mode, try CCmode. */
563 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
565 mode = GET_MODE_WIDER_MODE (mode))
566 if (HARD_REGNO_NREGS (regno, mode) == nregs
567 && HARD_REGNO_MODE_OK (regno, mode))
570 if (found_mode != VOIDmode)
573 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
575 mode = GET_MODE_WIDER_MODE (mode))
576 if (HARD_REGNO_NREGS (regno, mode) == nregs
577 && HARD_REGNO_MODE_OK (regno, mode))
580 if (found_mode != VOIDmode)
583 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
584 && HARD_REGNO_MODE_OK (regno, CCmode))
587 /* We can't find a mode valid for this register. */
591 /* Specify the usage characteristics of the register named NAME.
592 It should be a fixed register if FIXED and a
593 call-used register if CALL_USED. */
596 fix_register (name, fixed, call_used)
598 int fixed, call_used;
602 /* Decode the name and update the primary form of
603 the register info. */
605 if ((i = decode_reg_name (name)) >= 0)
607 if ((i == STACK_POINTER_REGNUM
608 #ifdef HARD_FRAME_POINTER_REGNUM
609 || i == HARD_FRAME_POINTER_REGNUM
611 || i == FRAME_POINTER_REGNUM
614 && (fixed == 0 || call_used == 0))
616 static const char * const what_option[2][2] = {
617 { "call-saved", "call-used" },
618 { "no-such-option", "fixed" }};
620 error ("can't use '%s' as a %s register", name,
621 what_option[fixed][call_used]);
625 fixed_regs[i] = fixed;
626 call_used_regs[i] = call_used;
631 warning ("unknown register name: %s", name);
635 /* Mark register number I as global. */
641 if (fixed_regs[i] == 0 && no_global_reg_vars)
642 error ("global register variable follows a function definition");
646 warning ("register used for two global register variables");
650 if (call_used_regs[i] && ! fixed_regs[i])
651 warning ("call-clobbered register used for global register variable");
655 /* If already fixed, nothing else to do. */
659 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
662 SET_HARD_REG_BIT (fixed_reg_set, i);
663 SET_HARD_REG_BIT (call_used_reg_set, i);
664 SET_HARD_REG_BIT (call_fixed_reg_set, i);
667 /* Now the data and code for the `regclass' pass, which happens
668 just before local-alloc. */
670 /* The `costs' struct records the cost of using a hard register of each class
671 and of using memory for each pseudo. We use this data to set up
672 register class preferences. */
676 int cost[N_REG_CLASSES];
680 /* Structure used to record preferrences of given pseudo. */
683 /* (enum reg_class) prefclass is the preferred class. */
686 /* altclass is a register class that we should use for allocating
687 pseudo if no register in the preferred class is available.
688 If no register in this class is available, memory is preferred.
690 It might appear to be more general to have a bitmask of classes here,
691 but since it is recommended that there be a class corresponding to the
692 union of most major pair of classes, that generality is not required. */
696 /* Record the cost of each class for each pseudo. */
698 static struct costs *costs;
700 /* Initialized once, and used to initialize cost values for each insn. */
702 static struct costs init_cost;
704 /* Record the same data by operand number, accumulated for each alternative
705 in an insn. The contribution to a pseudo is that of the minimum-cost
708 static struct costs op_costs[MAX_RECOG_OPERANDS];
710 /* Record preferrences of each pseudo.
711 This is available after `regclass' is run. */
713 static struct reg_pref *reg_pref;
715 /* Allocated buffers for reg_pref. */
717 static struct reg_pref *reg_pref_buffer;
719 /* Record the depth of loops that we are in. */
721 static int loop_depth;
723 /* Account for the fact that insns within a loop are executed very commonly,
724 but don't keep doing this as loops go too deep. */
726 static int loop_cost;
728 static rtx scan_one_insn PROTO((rtx, int));
729 static void dump_regclass PROTO((FILE *));
730 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
731 char *, const char **, rtx));
732 static int copy_cost PROTO((rtx, enum machine_mode,
733 enum reg_class, int));
734 static void record_address_regs PROTO((rtx, enum reg_class, int));
735 #ifdef FORBIDDEN_INC_DEC_CLASSES
736 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
738 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
740 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
741 This function is sometimes called before the info has been computed.
742 When that happens, just return GENERAL_REGS, which is innocuous. */
745 reg_preferred_class (regno)
750 return (enum reg_class) reg_pref[regno].prefclass;
754 reg_alternate_class (regno)
760 return (enum reg_class) reg_pref[regno].altclass;
763 /* Initialize some global data for this pass. */
770 init_cost.mem_cost = 10000;
771 for (i = 0; i < N_REG_CLASSES; i++)
772 init_cost.cost[i] = 10000;
774 /* This prevents dump_flow_info from losing if called
775 before regclass is run. */
778 /* No more global register variables may be declared. */
779 no_global_reg_vars = 1;
782 /* Dump register costs. */
787 static const char *const reg_class_names[] = REG_CLASS_NAMES;
789 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
791 enum reg_class class;
794 fprintf (dump, ";; Register %i costs:", i);
795 for (class = 0; class < N_REG_CLASSES; class++)
796 fprintf (dump, " %s:%i", reg_class_names[(int) class],
797 costs[i].cost[class]);
798 fprintf (dump, " MEM:%i\n\n", costs[i].mem_cost);
804 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
805 time it would save code to put a certain register in a certain class.
806 PASS, when nonzero, inhibits some optimizations which need only be done
808 Return the last insn processed, so that the scan can be continued from
812 scan_one_insn (insn, pass)
816 enum rtx_code code = GET_CODE (insn);
817 enum rtx_code pat_code;
818 const char *constraints[MAX_RECOG_OPERANDS];
819 enum machine_mode modes[MAX_RECOG_OPERANDS];
820 char subreg_changes_size[MAX_RECOG_OPERANDS];
824 /* Show that an insn inside a loop is likely to be executed three
825 times more than insns outside a loop. This is much more aggressive
826 than the assumptions made elsewhere and is being tried as an
831 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
833 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
839 loop_cost = 1 << (2 * MIN (loop_depth, 5));
844 if (GET_RTX_CLASS (code) != 'i')
847 pat_code = GET_CODE (PATTERN (insn));
849 || pat_code == CLOBBER
850 || pat_code == ASM_INPUT
851 || pat_code == ADDR_VEC
852 || pat_code == ADDR_DIFF_VEC)
855 set = single_set (insn);
858 for (i = 0; i < recog_data.n_operands; i++)
860 constraints[i] = recog_data.constraints[i];
861 modes[i] = recog_data.operand_mode[i];
863 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
865 /* If this insn loads a parameter from its stack slot, then
866 it represents a savings, rather than a cost, if the
867 parameter is stored in memory. Record this fact. */
869 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
870 && GET_CODE (SET_SRC (set)) == MEM
871 && (note = find_reg_note (insn, REG_EQUIV,
873 && GET_CODE (XEXP (note, 0)) == MEM)
875 costs[REGNO (SET_DEST (set))].mem_cost
876 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
879 record_address_regs (XEXP (SET_SRC (set), 0),
880 BASE_REG_CLASS, loop_cost * 2);
884 /* Improve handling of two-address insns such as
885 (set X (ashift CONST Y)) where CONST must be made to
886 match X. Change it into two insns: (set X CONST)
887 (set X (ashift X Y)). If we left this for reloading, it
888 would probably get three insns because X and Y might go
889 in the same place. This prevents X and Y from receiving
892 We can only do this if the modes of operands 0 and 1
893 (which might not be the same) are tieable and we only need
894 do this during our first pass. */
896 if (pass == 0 && optimize
897 && recog_data.n_operands >= 3
898 && recog_data.constraints[1][0] == '0'
899 && recog_data.constraints[1][1] == 0
900 && CONSTANT_P (recog_data.operand[1])
901 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
902 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
903 && GET_CODE (recog_data.operand[0]) == REG
904 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
905 recog_data.operand_mode[1]))
907 rtx previnsn = prev_real_insn (insn);
909 = gen_lowpart (recog_data.operand_mode[1],
910 recog_data.operand[0]);
912 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
914 /* If this insn was the start of a basic block,
915 include the new insn in that block.
916 We need not check for code_label here;
917 while a basic block can start with a code_label,
918 INSN could not be at the beginning of that block. */
919 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
922 for (b = 0; b < n_basic_blocks; b++)
923 if (insn == BLOCK_HEAD (b))
924 BLOCK_HEAD (b) = newinsn;
927 /* This makes one more setting of new insns's dest. */
928 REG_N_SETS (REGNO (recog_data.operand[0]))++;
930 *recog_data.operand_loc[1] = recog_data.operand[0];
931 for (i = recog_data.n_dups - 1; i >= 0; i--)
932 if (recog_data.dup_num[i] == 1)
933 *recog_data.dup_loc[i] = recog_data.operand[0];
935 return PREV_INSN (newinsn);
938 /* If we get here, we are set up to record the costs of all the
939 operands for this insn. Start by initializing the costs.
940 Then handle any address registers. Finally record the desired
941 classes for any pseudos, doing it twice if some pair of
942 operands are commutative. */
944 for (i = 0; i < recog_data.n_operands; i++)
946 op_costs[i] = init_cost;
948 if (GET_CODE (recog_data.operand[i]) == SUBREG)
950 rtx inner = SUBREG_REG (recog_data.operand[i]);
951 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
952 subreg_changes_size[i] = 1;
953 recog_data.operand[i] = inner;
956 if (GET_CODE (recog_data.operand[i]) == MEM)
957 record_address_regs (XEXP (recog_data.operand[i], 0),
958 BASE_REG_CLASS, loop_cost * 2);
959 else if (constraints[i][0] == 'p')
960 record_address_regs (recog_data.operand[i],
961 BASE_REG_CLASS, loop_cost * 2);
964 /* Check for commutative in a separate loop so everything will
965 have been initialized. We must do this even if one operand
966 is a constant--see addsi3 in m68k.md. */
968 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
969 if (constraints[i][0] == '%')
971 const char *xconstraints[MAX_RECOG_OPERANDS];
974 /* Handle commutative operands by swapping the constraints.
975 We assume the modes are the same. */
977 for (j = 0; j < recog_data.n_operands; j++)
978 xconstraints[j] = constraints[j];
980 xconstraints[i] = constraints[i+1];
981 xconstraints[i+1] = constraints[i];
982 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
983 recog_data.operand, modes, subreg_changes_size,
987 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
988 recog_data.operand, modes, subreg_changes_size,
991 /* Now add the cost for each operand to the total costs for
994 for (i = 0; i < recog_data.n_operands; i++)
995 if (GET_CODE (recog_data.operand[i]) == REG
996 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
998 int regno = REGNO (recog_data.operand[i]);
999 struct costs *p = &costs[regno], *q = &op_costs[i];
1001 p->mem_cost += q->mem_cost * loop_cost;
1002 for (j = 0; j < N_REG_CLASSES; j++)
1003 p->cost[j] += q->cost[j] * loop_cost;
1009 /* This is a pass of the compiler that scans all instructions
1010 and calculates the preferred class for each pseudo-register.
1011 This information can be accessed later by calling `reg_preferred_class'.
1012 This pass comes just before local register allocation. */
1015 regclass (f, nregs, dump)
1026 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1028 #ifdef FORBIDDEN_INC_DEC_CLASSES
1030 in_inc_dec = (char *) xmalloc (nregs);
1032 /* Initialize information about which register classes can be used for
1033 pseudos that are auto-incremented or auto-decremented. It would
1034 seem better to put this in init_reg_sets, but we need to be able
1035 to allocate rtx, which we can't do that early. */
1037 for (i = 0; i < N_REG_CLASSES; i++)
1039 rtx r = gen_rtx_REG (VOIDmode, 0);
1040 enum machine_mode m;
1043 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1044 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1048 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1049 m = (enum machine_mode) ((int) m + 1))
1050 if (HARD_REGNO_MODE_OK (j, m))
1054 /* If a register is not directly suitable for an
1055 auto-increment or decrement addressing mode and
1056 requires secondary reloads, disallow its class from
1057 being used in such addresses. */
1060 #ifdef SECONDARY_RELOAD_CLASS
1061 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1064 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1065 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1068 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1069 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1074 && ! auto_inc_dec_reg_p (r, m))
1075 forbidden_inc_dec_class[i] = 1;
1079 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1081 /* Normally we scan the insns once and determine the best class to use for
1082 each register. However, if -fexpensive_optimizations are on, we do so
1083 twice, the second time using the tentative best classes to guide the
1086 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1088 /* Zero out our accumulation of the cost of each class for each reg. */
1090 bzero ((char *) costs, nregs * sizeof (struct costs));
1092 #ifdef FORBIDDEN_INC_DEC_CLASSES
1093 bzero (in_inc_dec, nregs);
1096 loop_depth = 0, loop_cost = 1;
1098 /* Scan the instructions and record each time it would
1099 save code to put a certain register in a certain class. */
1101 for (insn = f; insn; insn = NEXT_INSN (insn))
1103 insn = scan_one_insn (insn, pass);
1106 /* Now for each register look at how desirable each class is
1107 and find which class is preferred. Store that in
1108 `prefclass'. Record in `altclass' the largest register
1109 class any of whose registers is better than memory. */
1112 reg_pref = reg_pref_buffer;
1114 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1116 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1117 enum reg_class best = ALL_REGS, alt = NO_REGS;
1118 /* This is an enum reg_class, but we call it an int
1119 to save lots of casts. */
1121 register struct costs *p = &costs[i];
1123 for (class = (int) ALL_REGS - 1; class > 0; class--)
1125 /* Ignore classes that are too small for this operand or
1126 invalid for a operand that was auto-incremented. */
1127 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1128 > reg_class_size[class]
1129 #ifdef FORBIDDEN_INC_DEC_CLASSES
1130 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1134 else if (p->cost[class] < best_cost)
1136 best_cost = p->cost[class];
1137 best = (enum reg_class) class;
1139 else if (p->cost[class] == best_cost)
1140 best = reg_class_subunion[(int)best][class];
1143 /* Record the alternate register class; i.e., a class for which
1144 every register in it is better than using memory. If adding a
1145 class would make a smaller class (i.e., no union of just those
1146 classes exists), skip that class. The major unions of classes
1147 should be provided as a register class. Don't do this if we
1148 will be doing it again later. */
1150 if (pass == 1 || ! flag_expensive_optimizations)
1151 for (class = 0; class < N_REG_CLASSES; class++)
1152 if (p->cost[class] < p->mem_cost
1153 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1154 > reg_class_size[(int) alt])
1155 #ifdef FORBIDDEN_INC_DEC_CLASSES
1156 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1159 alt = reg_class_subunion[(int) alt][class];
1161 /* If we don't add any classes, nothing to try. */
1165 /* We cast to (int) because (char) hits bugs in some compilers. */
1166 reg_pref[i].prefclass = (int) best;
1167 reg_pref[i].altclass = (int) alt;
1172 dump_regclass (dump);
1173 #ifdef FORBIDDEN_INC_DEC_CLASSES
1179 /* Record the cost of using memory or registers of various classes for
1180 the operands in INSN.
1182 N_ALTS is the number of alternatives.
1184 N_OPS is the number of operands.
1186 OPS is an array of the operands.
1188 MODES are the modes of the operands, in case any are VOIDmode.
1190 CONSTRAINTS are the constraints to use for the operands. This array
1191 is modified by this procedure.
1193 This procedure works alternative by alternative. For each alternative
1194 we assume that we will be able to allocate all pseudos to their ideal
1195 register class and calculate the cost of using that alternative. Then
1196 we compute for each operand that is a pseudo-register, the cost of
1197 having the pseudo allocated to each register class and using it in that
1198 alternative. To this cost is added the cost of the alternative.
1200 The cost of each class for this insn is its lowest cost among all the
1204 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1209 enum machine_mode *modes;
1210 char *subreg_changes_size;
1211 const char **constraints;
1218 /* Process each alternative, each time minimizing an operand's cost with
1219 the cost for each operand in that alternative. */
1221 for (alt = 0; alt < n_alts; alt++)
1223 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1226 enum reg_class classes[MAX_RECOG_OPERANDS];
1227 int allows_mem[MAX_RECOG_OPERANDS];
1230 for (i = 0; i < n_ops; i++)
1232 const char *p = constraints[i];
1234 enum machine_mode mode = modes[i];
1235 int allows_addr = 0;
1239 /* Initially show we know nothing about the register class. */
1240 classes[i] = NO_REGS;
1243 /* If this operand has no constraints at all, we can conclude
1244 nothing about it since anything is valid. */
1248 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1249 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1254 /* If this alternative is only relevant when this operand
1255 matches a previous operand, we do different things depending
1256 on whether this operand is a pseudo-reg or not. We must process
1257 any modifiers for the operand before we can make this test. */
1259 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1262 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1264 /* Copy class and whether memory is allowed from the matching
1265 alternative. Then perform any needed cost computations
1266 and/or adjustments. */
1268 classes[i] = classes[j];
1269 allows_mem[i] = allows_mem[j];
1271 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1273 /* If this matches the other operand, we have no added
1275 if (rtx_equal_p (ops[j], op))
1278 /* If we can put the other operand into a register, add to
1279 the cost of this alternative the cost to copy this
1280 operand to the register used for the other operand. */
1282 else if (classes[j] != NO_REGS)
1283 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1285 else if (GET_CODE (ops[j]) != REG
1286 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1288 /* This op is a pseudo but the one it matches is not. */
1290 /* If we can't put the other operand into a register, this
1291 alternative can't be used. */
1293 if (classes[j] == NO_REGS)
1296 /* Otherwise, add to the cost of this alternative the cost
1297 to copy the other operand to the register used for this
1301 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1305 /* The costs of this operand are not the same as the other
1306 operand since move costs are not symmetric. Moreover,
1307 if we cannot tie them, this alternative needs to do a
1308 copy, which is one instruction. */
1310 struct costs *pp = &this_op_costs[i];
1312 for (class = 0; class < N_REG_CLASSES; class++)
1314 = ((recog_data.operand_type[i] != OP_OUT
1315 ? may_move_in_cost[class][(int) classes[i]]
1317 + (recog_data.operand_type[i] != OP_IN
1318 ? may_move_out_cost[(int) classes[i]][class]
1321 /* If the alternative actually allows memory, make things
1322 a bit cheaper since we won't need an extra insn to
1326 = ((recog_data.operand_type[i] != OP_IN
1327 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1329 + (recog_data.operand_type[i] != OP_OUT
1330 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1331 : 0) - allows_mem[i]);
1333 /* If we have assigned a class to this register in our
1334 first pass, add a cost to this alternative corresponding
1335 to what we would add if this register were not in the
1336 appropriate class. */
1340 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1341 [(int) classes[i]]);
1343 if (REGNO (ops[i]) != REGNO (ops[j])
1344 && ! find_reg_note (insn, REG_DEAD, op))
1347 /* This is in place of ordinary cost computation
1348 for this operand, so skip to the end of the
1349 alternative (should be just one character). */
1350 while (*p && *p++ != ',')
1358 /* Scan all the constraint letters. See if the operand matches
1359 any of the constraints. Collect the valid register classes
1360 and see if this operand accepts memory. */
1362 while (*p && (c = *p++) != ',')
1366 /* Ignore the next letter for this pass. */
1372 case '!': case '#': case '&':
1373 case '0': case '1': case '2': case '3': case '4':
1374 case '5': case '6': case '7': case '8': case '9':
1379 win = address_operand (op, GET_MODE (op));
1380 /* We know this operand is an address, so we want it to be
1381 allocated to a register that can be the base of an
1382 address, ie BASE_REG_CLASS. */
1384 = reg_class_subunion[(int) classes[i]]
1385 [(int) BASE_REG_CLASS];
1388 case 'm': case 'o': case 'V':
1389 /* It doesn't seem worth distinguishing between offsettable
1390 and non-offsettable addresses here. */
1392 if (GET_CODE (op) == MEM)
1397 if (GET_CODE (op) == MEM
1398 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1399 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1404 if (GET_CODE (op) == MEM
1405 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1406 || GET_CODE (XEXP (op, 0)) == POST_INC))
1411 #ifndef REAL_ARITHMETIC
1412 /* Match any floating double constant, but only if
1413 we can examine the bits of it reliably. */
1414 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1415 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1416 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1419 if (GET_CODE (op) == CONST_DOUBLE)
1424 if (GET_CODE (op) == CONST_DOUBLE)
1430 if (GET_CODE (op) == CONST_DOUBLE
1431 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1436 if (GET_CODE (op) == CONST_INT
1437 || (GET_CODE (op) == CONST_DOUBLE
1438 && GET_MODE (op) == VOIDmode))
1442 #ifdef LEGITIMATE_PIC_OPERAND_P
1443 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1450 if (GET_CODE (op) == CONST_INT
1451 || (GET_CODE (op) == CONST_DOUBLE
1452 && GET_MODE (op) == VOIDmode))
1464 if (GET_CODE (op) == CONST_INT
1465 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1473 #ifdef EXTRA_CONSTRAINT
1479 if (EXTRA_CONSTRAINT (op, c))
1485 if (GET_CODE (op) == MEM
1487 #ifdef LEGITIMATE_PIC_OPERAND_P
1488 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1495 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1500 = reg_class_subunion[(int) classes[i]]
1501 [(int) REG_CLASS_FROM_LETTER (c)];
1506 #ifdef CLASS_CANNOT_CHANGE_SIZE
1507 /* If we noted a subreg earlier, and the selected class is a
1508 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1509 if (subreg_changes_size[i]
1510 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1512 == CLASS_CANNOT_CHANGE_SIZE))
1513 classes[i] = NO_REGS;
1516 /* How we account for this operand now depends on whether it is a
1517 pseudo register or not. If it is, we first check if any
1518 register classes are valid. If not, we ignore this alternative,
1519 since we want to assume that all pseudos get allocated for
1520 register preferencing. If some register class is valid, compute
1521 the costs of moving the pseudo into that class. */
1523 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1525 if (classes[i] == NO_REGS)
1527 /* We must always fail if the operand is a REG, but
1528 we did not find a suitable class.
1530 Otherwise we may perform an uninitialized read
1531 from this_op_costs after the `continue' statement
1537 struct costs *pp = &this_op_costs[i];
1539 for (class = 0; class < N_REG_CLASSES; class++)
1541 = ((recog_data.operand_type[i] != OP_OUT
1542 ? may_move_in_cost[class][(int) classes[i]]
1544 + (recog_data.operand_type[i] != OP_IN
1545 ? may_move_out_cost[(int) classes[i]][class]
1548 /* If the alternative actually allows memory, make things
1549 a bit cheaper since we won't need an extra insn to
1553 = ((recog_data.operand_type[i] != OP_IN
1554 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1556 + (recog_data.operand_type[i] != OP_OUT
1557 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1558 : 0) - allows_mem[i]);
1560 /* If we have assigned a class to this register in our
1561 first pass, add a cost to this alternative corresponding
1562 to what we would add if this register were not in the
1563 appropriate class. */
1567 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1568 [(int) classes[i]]);
1572 /* Otherwise, if this alternative wins, either because we
1573 have already determined that or if we have a hard register of
1574 the proper class, there is no cost for this alternative. */
1577 || (GET_CODE (op) == REG
1578 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1581 /* If registers are valid, the cost of this alternative includes
1582 copying the object to and/or from a register. */
1584 else if (classes[i] != NO_REGS)
1586 if (recog_data.operand_type[i] != OP_OUT)
1587 alt_cost += copy_cost (op, mode, classes[i], 1);
1589 if (recog_data.operand_type[i] != OP_IN)
1590 alt_cost += copy_cost (op, mode, classes[i], 0);
1593 /* The only other way this alternative can be used is if this is a
1594 constant that could be placed into memory. */
1596 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1597 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1605 /* Finally, update the costs with the information we've calculated
1606 about this alternative. */
1608 for (i = 0; i < n_ops; i++)
1609 if (GET_CODE (ops[i]) == REG
1610 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1612 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1613 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1615 pp->mem_cost = MIN (pp->mem_cost,
1616 (qq->mem_cost + alt_cost) * scale);
1618 for (class = 0; class < N_REG_CLASSES; class++)
1619 pp->cost[class] = MIN (pp->cost[class],
1620 (qq->cost[class] + alt_cost) * scale);
1624 /* If this insn is a single set copying operand 1 to operand 0
1625 and one is a pseudo with the other a hard reg that is in its
1626 own register class, set the cost of that register class to -1.
1627 Do this only when source dies to avoid stressing of register
1628 allocator by preferrencing two coliding registers into single
1631 if ((set = single_set (insn)) != 0
1632 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1633 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1634 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1635 for (i = 0; i <= 1; i++)
1636 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1638 int regno = REGNO (ops[!i]);
1639 enum machine_mode mode = GET_MODE (ops[!i]);
1643 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0
1644 && (reg_class_size[(unsigned char) reg_pref[regno].prefclass]
1645 == CLASS_MAX_NREGS (reg_pref[regno].prefclass, mode)))
1646 op_costs[i].cost[(unsigned char) reg_pref[regno].prefclass] = -1;
1647 else if (regno < FIRST_PSEUDO_REGISTER)
1648 for (class = 0; class < N_REG_CLASSES; class++)
1649 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1650 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1652 if (reg_class_size[class] == 1)
1653 op_costs[i].cost[class] = -1;
1656 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1658 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1662 if (nr == HARD_REGNO_NREGS(regno,mode))
1663 op_costs[i].cost[class] = -1;
1669 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1670 TO_P is zero) a register of class CLASS in mode MODE.
1672 X must not be a pseudo. */
1675 copy_cost (x, mode, class, to_p)
1677 enum machine_mode mode;
1678 enum reg_class class;
1681 #ifdef HAVE_SECONDARY_RELOADS
1682 enum reg_class secondary_class = NO_REGS;
1685 /* If X is a SCRATCH, there is actually nothing to move since we are
1686 assuming optimal allocation. */
1688 if (GET_CODE (x) == SCRATCH)
1691 /* Get the class we will actually use for a reload. */
1692 class = PREFERRED_RELOAD_CLASS (x, class);
1694 #ifdef HAVE_SECONDARY_RELOADS
1695 /* If we need a secondary reload (we assume here that we are using
1696 the secondary reload as an intermediate, not a scratch register), the
1697 cost is that to load the input into the intermediate register, then
1698 to copy them. We use a special value of TO_P to avoid recursion. */
1700 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1702 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1705 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1707 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1710 if (secondary_class != NO_REGS)
1711 return (move_cost[(int) secondary_class][(int) class]
1712 + copy_cost (x, mode, secondary_class, 2));
1713 #endif /* HAVE_SECONDARY_RELOADS */
1715 /* For memory, use the memory move cost, for (hard) registers, use the
1716 cost to move between the register classes, and use 2 for everything
1717 else (constants). */
1719 if (GET_CODE (x) == MEM || class == NO_REGS)
1720 return MEMORY_MOVE_COST (mode, class, to_p);
1722 else if (GET_CODE (x) == REG)
1723 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1726 /* If this is a constant, we may eventually want to call rtx_cost here. */
1730 /* Record the pseudo registers we must reload into hard registers
1731 in a subexpression of a memory address, X.
1733 CLASS is the class that the register needs to be in and is either
1734 BASE_REG_CLASS or INDEX_REG_CLASS.
1736 SCALE is twice the amount to multiply the cost by (it is twice so we
1737 can represent half-cost adjustments). */
1740 record_address_regs (x, class, scale)
1742 enum reg_class class;
1745 register enum rtx_code code = GET_CODE (x);
1758 /* When we have an address that is a sum,
1759 we must determine whether registers are "base" or "index" regs.
1760 If there is a sum of two registers, we must choose one to be
1761 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1762 to make a good choice most of the time. We only need to do this
1763 on machines that can have two registers in an address and where
1764 the base and index register classes are different.
1766 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1767 that seems bogus since it should only be set when we are sure
1768 the register is being used as a pointer. */
1771 rtx arg0 = XEXP (x, 0);
1772 rtx arg1 = XEXP (x, 1);
1773 register enum rtx_code code0 = GET_CODE (arg0);
1774 register enum rtx_code code1 = GET_CODE (arg1);
1776 /* Look inside subregs. */
1777 if (code0 == SUBREG)
1778 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1779 if (code1 == SUBREG)
1780 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1782 /* If this machine only allows one register per address, it must
1783 be in the first operand. */
1785 if (MAX_REGS_PER_ADDRESS == 1)
1786 record_address_regs (arg0, class, scale);
1788 /* If index and base registers are the same on this machine, just
1789 record registers in any non-constant operands. We assume here,
1790 as well as in the tests below, that all addresses are in
1793 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1795 record_address_regs (arg0, class, scale);
1796 if (! CONSTANT_P (arg1))
1797 record_address_regs (arg1, class, scale);
1800 /* If the second operand is a constant integer, it doesn't change
1801 what class the first operand must be. */
1803 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1804 record_address_regs (arg0, class, scale);
1806 /* If the second operand is a symbolic constant, the first operand
1807 must be an index register. */
1809 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1810 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1812 /* If both operands are registers but one is already a hard register
1813 of index or base class, give the other the class that the hard
1816 #ifdef REG_OK_FOR_BASE_P
1817 else if (code0 == REG && code1 == REG
1818 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1819 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1820 record_address_regs (arg1,
1821 REG_OK_FOR_BASE_P (arg0)
1822 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1824 else if (code0 == REG && code1 == REG
1825 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1826 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1827 record_address_regs (arg0,
1828 REG_OK_FOR_BASE_P (arg1)
1829 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1833 /* If one operand is known to be a pointer, it must be the base
1834 with the other operand the index. Likewise if the other operand
1837 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1840 record_address_regs (arg0, BASE_REG_CLASS, scale);
1841 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1843 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1846 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1847 record_address_regs (arg1, BASE_REG_CLASS, scale);
1850 /* Otherwise, count equal chances that each might be a base
1851 or index register. This case should be rare. */
1855 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1856 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1857 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1858 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1867 /* Double the importance of a pseudo register that is incremented
1868 or decremented, since it would take two extra insns
1869 if it ends up in the wrong place. If the operand is a pseudo,
1870 show it is being used in an INC_DEC context. */
1872 #ifdef FORBIDDEN_INC_DEC_CLASSES
1873 if (GET_CODE (XEXP (x, 0)) == REG
1874 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1875 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1878 record_address_regs (XEXP (x, 0), class, 2 * scale);
1883 register struct costs *pp = &costs[REGNO (x)];
1886 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1888 for (i = 0; i < N_REG_CLASSES; i++)
1889 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1895 register const char *fmt = GET_RTX_FORMAT (code);
1897 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1899 record_address_regs (XEXP (x, i), class, scale);
1904 #ifdef FORBIDDEN_INC_DEC_CLASSES
1906 /* Return 1 if REG is valid as an auto-increment memory reference
1907 to an object of MODE. */
1910 auto_inc_dec_reg_p (reg, mode)
1912 enum machine_mode mode;
1914 if (HAVE_POST_INCREMENT
1915 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1918 if (HAVE_POST_DECREMENT
1919 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1922 if (HAVE_PRE_INCREMENT
1923 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1926 if (HAVE_PRE_DECREMENT
1927 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1934 static short *renumber = (short *)0;
1935 static size_t regno_allocated = 0;
1937 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1938 reg_scan and flow_analysis that are indexed by the register number. If
1939 NEW_P is non zero, initialize all of the registers, otherwise only
1940 initialize the new registers allocated. The same table is kept from
1941 function to function, only reallocating it when we need more room. If
1942 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1945 allocate_reg_info (num_regs, new_p, renumber_p)
1951 size_t size_renumber;
1952 size_t min = (new_p) ? 0 : reg_n_max;
1953 struct reg_info_data *reg_data;
1954 struct reg_info_data *reg_next;
1956 if (num_regs > regno_allocated)
1958 size_t old_allocated = regno_allocated;
1960 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1961 size_renumber = regno_allocated * sizeof (short);
1965 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1966 renumber = (short *) xmalloc (size_renumber);
1967 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
1968 * sizeof (struct reg_pref));
1973 VARRAY_GROW (reg_n_info, regno_allocated);
1975 if (new_p) /* if we're zapping everything, no need to realloc */
1977 free ((char *)renumber);
1978 free ((char *)reg_pref);
1979 renumber = (short *) xmalloc (size_renumber);
1980 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
1981 * sizeof (struct reg_pref));
1986 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1987 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
1989 * sizeof (struct reg_pref));
1993 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1994 + sizeof (struct reg_info_data) - sizeof (reg_info);
1995 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1996 reg_data->min_index = old_allocated;
1997 reg_data->max_index = regno_allocated - 1;
1998 reg_data->next = reg_info_head;
1999 reg_info_head = reg_data;
2002 reg_n_max = num_regs;
2005 /* Loop through each of the segments allocated for the actual
2006 reg_info pages, and set up the pointers, zero the pages, etc. */
2007 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2009 size_t min_index = reg_data->min_index;
2010 size_t max_index = reg_data->max_index;
2012 reg_next = reg_data->next;
2013 if (min <= max_index)
2015 size_t max = max_index;
2016 size_t local_min = min - min_index;
2019 if (min < min_index)
2021 if (!reg_data->used_p) /* page just allocated with calloc */
2022 reg_data->used_p = 1; /* no need to zero */
2024 bzero ((char *) ®_data->data[local_min],
2025 sizeof (reg_info) * (max - min_index - local_min + 1));
2027 for (i = min_index+local_min; i <= max; i++)
2029 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2030 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2032 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2033 reg_pref_buffer[i].altclass = (char) NO_REGS;
2039 /* If {pref,alt}class have already been allocated, update the pointers to
2040 the newly realloced ones. */
2042 reg_pref = reg_pref_buffer;
2045 reg_renumber = renumber;
2047 /* Tell the regset code about the new number of registers */
2048 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2051 /* Free up the space allocated by allocate_reg_info. */
2057 struct reg_info_data *reg_data;
2058 struct reg_info_data *reg_next;
2060 VARRAY_FREE (reg_n_info);
2061 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2063 reg_next = reg_data->next;
2064 free ((char *)reg_data);
2067 free (reg_pref_buffer);
2068 reg_pref_buffer = (struct reg_pref *)0;
2069 reg_info_head = (struct reg_info_data *)0;
2070 renumber = (short *)0;
2072 regno_allocated = 0;
2076 /* This is the `regscan' pass of the compiler, run just before cse
2077 and again just before loop.
2079 It finds the first and last use of each pseudo-register
2080 and records them in the vectors regno_first_uid, regno_last_uid
2081 and counts the number of sets in the vector reg_n_sets.
2083 REPEAT is nonzero the second time this is called. */
2085 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2086 Always at least 3, since the combiner could put that many together
2087 and we want this to remain correct for all the remaining passes. */
2092 reg_scan (f, nregs, repeat)
2099 allocate_reg_info (nregs, TRUE, FALSE);
2102 for (insn = f; insn; insn = NEXT_INSN (insn))
2103 if (GET_CODE (insn) == INSN
2104 || GET_CODE (insn) == CALL_INSN
2105 || GET_CODE (insn) == JUMP_INSN)
2107 if (GET_CODE (PATTERN (insn)) == PARALLEL
2108 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2109 max_parallel = XVECLEN (PATTERN (insn), 0);
2110 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2112 if (REG_NOTES (insn))
2113 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2117 /* Update 'regscan' information by looking at the insns
2118 from FIRST to LAST. Some new REGs have been created,
2119 and any REG with number greater than OLD_MAX_REGNO is
2120 such a REG. We only update information for those. */
2123 reg_scan_update(first, last, old_max_regno)
2130 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2132 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2133 if (GET_CODE (insn) == INSN
2134 || GET_CODE (insn) == CALL_INSN
2135 || GET_CODE (insn) == JUMP_INSN)
2137 if (GET_CODE (PATTERN (insn)) == PARALLEL
2138 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2139 max_parallel = XVECLEN (PATTERN (insn), 0);
2140 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2142 if (REG_NOTES (insn))
2143 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2147 /* X is the expression to scan. INSN is the insn it appears in.
2148 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2149 We should only record information for REGs with numbers
2150 greater than or equal to MIN_REGNO. */
2153 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2159 register enum rtx_code code;
2163 code = GET_CODE (x);
2179 register int regno = REGNO (x);
2181 if (regno >= min_regno)
2183 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2185 REGNO_LAST_UID (regno) = INSN_UID (insn);
2186 if (REGNO_FIRST_UID (regno) == 0)
2187 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2194 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2196 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2201 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2205 /* Count a set of the destination if it is a register. */
2206 for (dest = SET_DEST (x);
2207 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2208 || GET_CODE (dest) == ZERO_EXTEND;
2209 dest = XEXP (dest, 0))
2212 if (GET_CODE (dest) == REG
2213 && REGNO (dest) >= min_regno)
2214 REG_N_SETS (REGNO (dest))++;
2216 /* If this is setting a pseudo from another pseudo or the sum of a
2217 pseudo and a constant integer and the other pseudo is known to be
2218 a pointer, set the destination to be a pointer as well.
2220 Likewise if it is setting the destination from an address or from a
2221 value equivalent to an address or to the sum of an address and
2224 But don't do any of this if the pseudo corresponds to a user
2225 variable since it should have already been set as a pointer based
2228 if (GET_CODE (SET_DEST (x)) == REG
2229 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2230 && REGNO (SET_DEST (x)) >= min_regno
2231 /* If the destination pseudo is set more than once, then other
2232 sets might not be to a pointer value (consider access to a
2233 union in two threads of control in the presense of global
2234 optimizations). So only set REGNO_POINTER_FLAG on the destination
2235 pseudo if this is the only set of that pseudo. */
2236 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2237 && ! REG_USERVAR_P (SET_DEST (x))
2238 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2239 && ((GET_CODE (SET_SRC (x)) == REG
2240 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2241 || ((GET_CODE (SET_SRC (x)) == PLUS
2242 || GET_CODE (SET_SRC (x)) == LO_SUM)
2243 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2244 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2245 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2246 || GET_CODE (SET_SRC (x)) == CONST
2247 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2248 || GET_CODE (SET_SRC (x)) == LABEL_REF
2249 || (GET_CODE (SET_SRC (x)) == HIGH
2250 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2251 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2252 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2253 || ((GET_CODE (SET_SRC (x)) == PLUS
2254 || GET_CODE (SET_SRC (x)) == LO_SUM)
2255 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2256 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2257 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2258 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2259 && (GET_CODE (XEXP (note, 0)) == CONST
2260 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2261 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2262 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2264 /* ... fall through ... */
2268 register const char *fmt = GET_RTX_FORMAT (code);
2270 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2273 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2274 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2277 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2278 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2285 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2289 reg_class_subset_p (c1, c2)
2290 register enum reg_class c1;
2291 register enum reg_class c2;
2293 if (c1 == c2) return 1;
2298 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2299 reg_class_contents[(int)c2],
2304 /* Return nonzero if there is a register that is in both C1 and C2. */
2307 reg_classes_intersect_p (c1, c2)
2308 register enum reg_class c1;
2309 register enum reg_class c2;
2316 if (c1 == c2) return 1;
2318 if (c1 == ALL_REGS || c2 == ALL_REGS)
2321 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2322 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2324 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2331 /* Release any memory allocated by register sets. */
2334 regset_release_memory ()
2336 bitmap_release_memory ();