1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(m, x, y) 2
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* Maximum cost of moving from a register in one class to a register in
178 another class. Based on REGISTER_MOVE_COST. */
180 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
182 /* Similar, but here we don't have to move if the first index is a subset
183 of the second so in that case the cost is zero. */
185 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
187 /* Similar, but here we don't have to move if the first index is a superset
188 of the second so in that case the cost is zero. */
190 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
192 #ifdef FORBIDDEN_INC_DEC_CLASSES
194 /* These are the classes that regs which are auto-incremented or decremented
197 static int forbidden_inc_dec_class[N_REG_CLASSES];
199 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
202 static char *in_inc_dec;
204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
206 #ifdef CLASS_CANNOT_CHANGE_MODE
208 /* These are the classes containing only registers that can be used in
209 a SUBREG expression that changes the mode of the register in some
210 way that is illegal. */
212 static int class_can_change_mode[N_REG_CLASSES];
214 /* Registers, including pseudos, which change modes in some way that
217 static regset reg_changes_mode;
219 #endif /* CLASS_CANNOT_CHANGE_MODE */
221 #ifdef HAVE_SECONDARY_RELOADS
223 /* Sample MEM values for use by memory_move_secondary_cost. */
225 static rtx top_of_stack[MAX_MACHINE_MODE];
227 #endif /* HAVE_SECONDARY_RELOADS */
229 /* Linked list of reg_info structures allocated for reg_n_info array.
230 Grouping all of the allocated structures together in one lump
231 means only one call to bzero to clear them, rather than n smaller
233 struct reg_info_data {
234 struct reg_info_data *next; /* next set of reg_info structures */
235 size_t min_index; /* minimum index # */
236 size_t max_index; /* maximum index # */
237 char used_p; /* non-zero if this has been used previously */
238 reg_info data[1]; /* beginning of the reg_info data */
241 static struct reg_info_data *reg_info_head;
243 /* No more global register variables may be declared; true once
244 regclass has been initialized. */
246 static int no_global_reg_vars = 0;
249 /* Function called only once to initialize the above data on reg usage.
250 Once this is done, various switches may override. */
257 /* First copy the register information from the initial int form into
260 for (i = 0; i < N_REG_CLASSES; i++)
262 CLEAR_HARD_REG_SET (reg_class_contents[i]);
264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
265 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
266 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
267 SET_HARD_REG_BIT (reg_class_contents[i], j);
270 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
271 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
272 memset (global_regs, 0, sizeof global_regs);
274 /* Do any additional initialization regsets may need */
275 INIT_ONCE_REG_SET ();
277 #ifdef REG_ALLOC_ORDER
278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
279 inv_reg_alloc_order[reg_alloc_order[i]] = i;
283 /* After switches have been processed, which perhaps alter
284 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
289 register unsigned int i, j;
290 register unsigned int /* enum machine_mode */ m;
291 char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
292 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
294 /* This macro allows the fixed or call-used registers
295 and the register classes to depend on target flags. */
297 #ifdef CONDITIONAL_REGISTER_USAGE
298 CONDITIONAL_REGISTER_USAGE;
301 /* Compute number of hard regs in each class. */
303 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
304 for (i = 0; i < N_REG_CLASSES; i++)
305 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
306 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
309 /* Initialize the table of subunions.
310 reg_class_subunion[I][J] gets the largest-numbered reg-class
311 that is contained in the union of classes I and J. */
313 for (i = 0; i < N_REG_CLASSES; i++)
315 for (j = 0; j < N_REG_CLASSES; j++)
318 register /* Declare it register if it's a scalar. */
323 COPY_HARD_REG_SET (c, reg_class_contents[i]);
324 IOR_HARD_REG_SET (c, reg_class_contents[j]);
325 for (k = 0; k < N_REG_CLASSES; k++)
327 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
332 /* keep the largest subclass */ /* SPEE 900308 */
333 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
334 reg_class_contents[(int) reg_class_subunion[i][j]],
336 reg_class_subunion[i][j] = (enum reg_class) k;
343 /* Initialize the table of superunions.
344 reg_class_superunion[I][J] gets the smallest-numbered reg-class
345 containing the union of classes I and J. */
347 for (i = 0; i < N_REG_CLASSES; i++)
349 for (j = 0; j < N_REG_CLASSES; j++)
352 register /* Declare it register if it's a scalar. */
357 COPY_HARD_REG_SET (c, reg_class_contents[i]);
358 IOR_HARD_REG_SET (c, reg_class_contents[j]);
359 for (k = 0; k < N_REG_CLASSES; k++)
360 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
363 reg_class_superunion[i][j] = (enum reg_class) k;
367 /* Initialize the tables of subclasses and superclasses of each reg class.
368 First clear the whole table, then add the elements as they are found. */
370 for (i = 0; i < N_REG_CLASSES; i++)
372 for (j = 0; j < N_REG_CLASSES; j++)
374 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
375 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
379 for (i = 0; i < N_REG_CLASSES; i++)
381 if (i == (int) NO_REGS)
384 for (j = i + 1; j < N_REG_CLASSES; j++)
388 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
392 /* Reg class I is a subclass of J.
393 Add J to the table of superclasses of I. */
394 p = ®_class_superclasses[i][0];
395 while (*p != LIM_REG_CLASSES) p++;
396 *p = (enum reg_class) j;
397 /* Add I to the table of superclasses of J. */
398 p = ®_class_subclasses[j][0];
399 while (*p != LIM_REG_CLASSES) p++;
400 *p = (enum reg_class) i;
404 /* Initialize "constant" tables. */
406 CLEAR_HARD_REG_SET (fixed_reg_set);
407 CLEAR_HARD_REG_SET (call_used_reg_set);
408 CLEAR_HARD_REG_SET (call_fixed_reg_set);
410 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
412 n_non_fixed_regs = 0;
414 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
417 SET_HARD_REG_BIT (fixed_reg_set, i);
421 if (call_used_regs[i])
422 SET_HARD_REG_BIT (call_used_reg_set, i);
423 if (call_fixed_regs[i])
424 SET_HARD_REG_BIT (call_fixed_reg_set, i);
425 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
426 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
428 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
429 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
430 for (m = 0; m < MAX_MACHINE_MODE; m++)
431 for (i = 0; i < N_REG_CLASSES; i++)
432 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
433 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
434 && HARD_REGNO_MODE_OK (j, m))
436 contains_reg_of_mode [i][m] = 1;
437 allocatable_regs_of_mode [m] = 1;
441 /* Initialize the move cost table. Find every subset of each class
442 and take the maximum cost of moving any subset to any other. */
444 for (m = 0; m < MAX_MACHINE_MODE; m++)
445 if (allocatable_regs_of_mode [m])
447 for (i = 0; i < N_REG_CLASSES; i++)
448 if (contains_reg_of_mode [i][m])
449 for (j = 0; j < N_REG_CLASSES; j++)
452 enum reg_class *p1, *p2;
454 if (!contains_reg_of_mode [j][m])
456 move_cost[m][i][j] = 65536;
457 may_move_in_cost[m][i][j] = 65536;
458 may_move_out_cost[m][i][j] = 65536;
462 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
464 for (p2 = ®_class_subclasses[j][0];
465 *p2 != LIM_REG_CLASSES;
467 if (*p2 != i && contains_reg_of_mode [*p1][m])
468 cost = MAX (cost, move_cost [m][i][*p2]);
470 for (p1 = ®_class_subclasses[i][0];
471 *p1 != LIM_REG_CLASSES;
473 if (*p1 != j && contains_reg_of_mode [*p1][m])
474 cost = MAX (cost, move_cost [m][*p1][j]);
476 move_cost[m][i][j] = cost;
478 if (reg_class_subset_p (i, j))
479 may_move_in_cost[m][i][j] = 0;
481 may_move_in_cost[m][i][j] = cost;
483 if (reg_class_subset_p (j, i))
484 may_move_out_cost[m][i][j] = 0;
486 may_move_out_cost[m][i][j] = cost;
490 for (j = 0; j < N_REG_CLASSES; j++)
492 move_cost[m][i][j] = 65536;
493 may_move_in_cost[m][i][j] = 65536;
494 may_move_out_cost[m][i][j] = 65536;
498 #ifdef CLASS_CANNOT_CHANGE_MODE
501 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
503 for (i = 0; i < N_REG_CLASSES; i++)
505 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
506 class_can_change_mode [i] = 0;
509 class_can_change_mode [i] = 1;
512 #endif /* CLASS_CANNOT_CHANGE_MODE */
515 /* Compute the table of register modes.
516 These values are used to record death information for individual registers
517 (as opposed to a multi-register mode). */
524 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
526 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
528 /* If we couldn't find a valid mode, just use the previous mode.
529 ??? One situation in which we need to do this is on the mips where
530 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
531 to use DF mode for the even registers and VOIDmode for the odd
532 (for the cpu models where the odd ones are inaccessible). */
533 if (reg_raw_mode[i] == VOIDmode)
534 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
538 /* Finish initializing the register sets and
539 initialize the register modes. */
544 /* This finishes what was started by init_reg_sets, but couldn't be done
545 until after register usage was specified. */
550 #ifdef HAVE_SECONDARY_RELOADS
552 /* Make some fake stack-frame MEM references for use in
553 memory_move_secondary_cost. */
556 for (i = 0; i < MAX_MACHINE_MODE; i++)
557 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
558 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
563 #ifdef HAVE_SECONDARY_RELOADS
565 /* Compute extra cost of moving registers to/from memory due to reloads.
566 Only needed if secondary reloads are required for memory moves. */
569 memory_move_secondary_cost (mode, class, in)
570 enum machine_mode mode;
571 enum reg_class class;
574 enum reg_class altclass;
575 int partial_cost = 0;
576 /* We need a memory reference to feed to SECONDARY... macros. */
577 /* mem may be unused even if the SECONDARY_ macros are defined. */
578 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
583 #ifdef SECONDARY_INPUT_RELOAD_CLASS
584 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
591 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
592 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
598 if (altclass == NO_REGS)
602 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
604 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
606 if (class == altclass)
607 /* This isn't simply a copy-to-temporary situation. Can't guess
608 what it is, so MEMORY_MOVE_COST really ought not to be calling
611 I'm tempted to put in an abort here, but returning this will
612 probably only give poor estimates, which is what we would've
613 had before this code anyways. */
616 /* Check if the secondary reload register will also need a
618 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
622 /* Return a machine mode that is legitimate for hard reg REGNO and large
623 enough to save nregs. If we can't find one, return VOIDmode. */
626 choose_hard_reg_mode (regno, nregs)
627 unsigned int regno ATTRIBUTE_UNUSED;
630 enum machine_mode found_mode = VOIDmode, mode;
632 /* We first look for the largest integer mode that can be validly
633 held in REGNO. If none, we look for the largest floating-point mode.
634 If we still didn't find a valid mode, try CCmode. */
636 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
638 mode = GET_MODE_WIDER_MODE (mode))
639 if (HARD_REGNO_NREGS (regno, mode) == nregs
640 && HARD_REGNO_MODE_OK (regno, mode))
643 if (found_mode != VOIDmode)
646 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
648 mode = GET_MODE_WIDER_MODE (mode))
649 if (HARD_REGNO_NREGS (regno, mode) == nregs
650 && HARD_REGNO_MODE_OK (regno, mode))
653 if (found_mode != VOIDmode)
656 /* Iterate over all of the CCmodes. */
657 for (mode = CCmode; mode < NUM_MACHINE_MODES; ++mode)
658 if (HARD_REGNO_NREGS (regno, mode) == nregs
659 && HARD_REGNO_MODE_OK (regno, mode))
662 /* We can't find a mode valid for this register. */
666 /* Specify the usage characteristics of the register named NAME.
667 It should be a fixed register if FIXED and a
668 call-used register if CALL_USED. */
671 fix_register (name, fixed, call_used)
673 int fixed, call_used;
677 /* Decode the name and update the primary form of
678 the register info. */
680 if ((i = decode_reg_name (name)) >= 0)
682 if ((i == STACK_POINTER_REGNUM
683 #ifdef HARD_FRAME_POINTER_REGNUM
684 || i == HARD_FRAME_POINTER_REGNUM
686 || i == FRAME_POINTER_REGNUM
689 && (fixed == 0 || call_used == 0))
691 static const char * const what_option[2][2] = {
692 { "call-saved", "call-used" },
693 { "no-such-option", "fixed" }};
695 error ("can't use '%s' as a %s register", name,
696 what_option[fixed][call_used]);
700 fixed_regs[i] = fixed;
701 call_used_regs[i] = call_used;
706 warning ("unknown register name: %s", name);
710 /* Mark register number I as global. */
716 if (fixed_regs[i] == 0 && no_global_reg_vars)
717 error ("global register variable follows a function definition");
721 warning ("register used for two global register variables");
725 if (call_used_regs[i] && ! fixed_regs[i])
726 warning ("call-clobbered register used for global register variable");
730 /* If already fixed, nothing else to do. */
734 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
737 SET_HARD_REG_BIT (fixed_reg_set, i);
738 SET_HARD_REG_BIT (call_used_reg_set, i);
739 SET_HARD_REG_BIT (call_fixed_reg_set, i);
742 /* Now the data and code for the `regclass' pass, which happens
743 just before local-alloc. */
745 /* The `costs' struct records the cost of using a hard register of each class
746 and of using memory for each pseudo. We use this data to set up
747 register class preferences. */
751 int cost[N_REG_CLASSES];
755 /* Structure used to record preferrences of given pseudo. */
758 /* (enum reg_class) prefclass is the preferred class. */
761 /* altclass is a register class that we should use for allocating
762 pseudo if no register in the preferred class is available.
763 If no register in this class is available, memory is preferred.
765 It might appear to be more general to have a bitmask of classes here,
766 but since it is recommended that there be a class corresponding to the
767 union of most major pair of classes, that generality is not required. */
771 /* Record the cost of each class for each pseudo. */
773 static struct costs *costs;
775 /* Initialized once, and used to initialize cost values for each insn. */
777 static struct costs init_cost;
779 /* Record preferrences of each pseudo.
780 This is available after `regclass' is run. */
782 static struct reg_pref *reg_pref;
784 /* Allocated buffers for reg_pref. */
786 static struct reg_pref *reg_pref_buffer;
788 /* Account for the fact that insns within a loop are executed very commonly,
789 but don't keep doing this as loops go too deep. */
791 static int loop_cost;
793 static rtx scan_one_insn PARAMS ((rtx, int));
794 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
795 static void dump_regclass PARAMS ((FILE *));
796 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
798 struct costs *, struct reg_pref *));
799 static int copy_cost PARAMS ((rtx, enum machine_mode,
800 enum reg_class, int));
801 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
802 #ifdef FORBIDDEN_INC_DEC_CLASSES
803 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
805 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
807 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
808 This function is sometimes called before the info has been computed.
809 When that happens, just return GENERAL_REGS, which is innocuous. */
812 reg_preferred_class (regno)
817 return (enum reg_class) reg_pref[regno].prefclass;
821 reg_alternate_class (regno)
827 return (enum reg_class) reg_pref[regno].altclass;
830 /* Initialize some global data for this pass. */
837 init_cost.mem_cost = 10000;
838 for (i = 0; i < N_REG_CLASSES; i++)
839 init_cost.cost[i] = 10000;
841 /* This prevents dump_flow_info from losing if called
842 before regclass is run. */
845 /* No more global register variables may be declared. */
846 no_global_reg_vars = 1;
849 /* Dump register costs. */
854 static const char *const reg_class_names[] = REG_CLASS_NAMES;
856 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
858 enum reg_class class;
861 fprintf (dump, " Register %i costs:", i);
862 for (class = 0; class < N_REG_CLASSES; class++)
863 fprintf (dump, " %s:%i", reg_class_names[(int) class],
864 costs[i].cost[class]);
865 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
871 /* Calculate the costs of insn operands. */
874 record_operand_costs (insn, op_costs, reg_pref)
876 struct costs *op_costs;
877 struct reg_pref *reg_pref;
879 const char *constraints[MAX_RECOG_OPERANDS];
880 enum machine_mode modes[MAX_RECOG_OPERANDS];
883 for (i = 0; i < recog_data.n_operands; i++)
885 constraints[i] = recog_data.constraints[i];
886 modes[i] = recog_data.operand_mode[i];
889 /* If we get here, we are set up to record the costs of all the
890 operands for this insn. Start by initializing the costs.
891 Then handle any address registers. Finally record the desired
892 classes for any pseudos, doing it twice if some pair of
893 operands are commutative. */
895 for (i = 0; i < recog_data.n_operands; i++)
897 op_costs[i] = init_cost;
899 if (GET_CODE (recog_data.operand[i]) == SUBREG)
901 rtx inner = SUBREG_REG (recog_data.operand[i]);
902 #ifdef CLASS_CANNOT_CHANGE_MODE
903 if (GET_CODE (inner) == REG
904 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
905 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
907 recog_data.operand[i] = inner;
910 if (GET_CODE (recog_data.operand[i]) == MEM)
911 record_address_regs (XEXP (recog_data.operand[i], 0),
912 BASE_REG_CLASS, loop_cost * 2);
913 else if (constraints[i][0] == 'p')
914 record_address_regs (recog_data.operand[i],
915 BASE_REG_CLASS, loop_cost * 2);
918 /* Check for commutative in a separate loop so everything will
919 have been initialized. We must do this even if one operand
920 is a constant--see addsi3 in m68k.md. */
922 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
923 if (constraints[i][0] == '%')
925 const char *xconstraints[MAX_RECOG_OPERANDS];
928 /* Handle commutative operands by swapping the constraints.
929 We assume the modes are the same. */
931 for (j = 0; j < recog_data.n_operands; j++)
932 xconstraints[j] = constraints[j];
934 xconstraints[i] = constraints[i+1];
935 xconstraints[i+1] = constraints[i];
936 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
937 recog_data.operand, modes,
938 xconstraints, insn, op_costs, reg_pref);
941 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
942 recog_data.operand, modes,
943 constraints, insn, op_costs, reg_pref);
946 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
947 time it would save code to put a certain register in a certain class.
948 PASS, when nonzero, inhibits some optimizations which need only be done
950 Return the last insn processed, so that the scan can be continued from
954 scan_one_insn (insn, pass)
958 enum rtx_code code = GET_CODE (insn);
959 enum rtx_code pat_code;
962 struct costs op_costs[MAX_RECOG_OPERANDS];
964 if (GET_RTX_CLASS (code) != 'i')
967 pat_code = GET_CODE (PATTERN (insn));
969 || pat_code == CLOBBER
970 || pat_code == ASM_INPUT
971 || pat_code == ADDR_VEC
972 || pat_code == ADDR_DIFF_VEC)
975 set = single_set (insn);
978 /* If this insn loads a parameter from its stack slot, then
979 it represents a savings, rather than a cost, if the
980 parameter is stored in memory. Record this fact. */
982 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
983 && GET_CODE (SET_SRC (set)) == MEM
984 && (note = find_reg_note (insn, REG_EQUIV,
986 && GET_CODE (XEXP (note, 0)) == MEM)
988 costs[REGNO (SET_DEST (set))].mem_cost
989 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
992 record_address_regs (XEXP (SET_SRC (set), 0),
993 BASE_REG_CLASS, loop_cost * 2);
997 /* Improve handling of two-address insns such as
998 (set X (ashift CONST Y)) where CONST must be made to
999 match X. Change it into two insns: (set X CONST)
1000 (set X (ashift X Y)). If we left this for reloading, it
1001 would probably get three insns because X and Y might go
1002 in the same place. This prevents X and Y from receiving
1005 We can only do this if the modes of operands 0 and 1
1006 (which might not be the same) are tieable and we only need
1007 do this during our first pass. */
1009 if (pass == 0 && optimize
1010 && recog_data.n_operands >= 3
1011 && recog_data.constraints[1][0] == '0'
1012 && recog_data.constraints[1][1] == 0
1013 && CONSTANT_P (recog_data.operand[1])
1014 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1015 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1016 && GET_CODE (recog_data.operand[0]) == REG
1017 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1018 recog_data.operand_mode[1]))
1020 rtx previnsn = prev_real_insn (insn);
1022 = gen_lowpart (recog_data.operand_mode[1],
1023 recog_data.operand[0]);
1025 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1027 /* If this insn was the start of a basic block,
1028 include the new insn in that block.
1029 We need not check for code_label here;
1030 while a basic block can start with a code_label,
1031 INSN could not be at the beginning of that block. */
1032 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1035 for (b = 0; b < n_basic_blocks; b++)
1036 if (insn == BLOCK_HEAD (b))
1037 BLOCK_HEAD (b) = newinsn;
1040 /* This makes one more setting of new insns's dest. */
1041 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1043 *recog_data.operand_loc[1] = recog_data.operand[0];
1044 for (i = recog_data.n_dups - 1; i >= 0; i--)
1045 if (recog_data.dup_num[i] == 1)
1046 *recog_data.dup_loc[i] = recog_data.operand[0];
1048 return PREV_INSN (newinsn);
1051 record_operand_costs (insn, op_costs, reg_pref);
1053 /* Now add the cost for each operand to the total costs for
1056 for (i = 0; i < recog_data.n_operands; i++)
1057 if (GET_CODE (recog_data.operand[i]) == REG
1058 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1060 int regno = REGNO (recog_data.operand[i]);
1061 struct costs *p = &costs[regno], *q = &op_costs[i];
1063 p->mem_cost += q->mem_cost * loop_cost;
1064 for (j = 0; j < N_REG_CLASSES; j++)
1065 p->cost[j] += q->cost[j] * loop_cost;
1071 /* This is a pass of the compiler that scans all instructions
1072 and calculates the preferred class for each pseudo-register.
1073 This information can be accessed later by calling `reg_preferred_class'.
1074 This pass comes just before local register allocation. */
1077 regclass (f, nregs, dump)
1088 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1090 #ifdef CLASS_CANNOT_CHANGE_MODE
1091 reg_changes_mode = BITMAP_XMALLOC();
1094 #ifdef FORBIDDEN_INC_DEC_CLASSES
1096 in_inc_dec = (char *) xmalloc (nregs);
1098 /* Initialize information about which register classes can be used for
1099 pseudos that are auto-incremented or auto-decremented. It would
1100 seem better to put this in init_reg_sets, but we need to be able
1101 to allocate rtx, which we can't do that early. */
1103 for (i = 0; i < N_REG_CLASSES; i++)
1105 rtx r = gen_rtx_REG (VOIDmode, 0);
1106 enum machine_mode m;
1109 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1110 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1114 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1115 m = (enum machine_mode) ((int) m + 1))
1116 if (HARD_REGNO_MODE_OK (j, m))
1120 /* If a register is not directly suitable for an
1121 auto-increment or decrement addressing mode and
1122 requires secondary reloads, disallow its class from
1123 being used in such addresses. */
1126 #ifdef SECONDARY_RELOAD_CLASS
1127 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1130 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1131 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1134 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1135 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1140 && ! auto_inc_dec_reg_p (r, m))
1141 forbidden_inc_dec_class[i] = 1;
1145 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1147 /* Normally we scan the insns once and determine the best class to use for
1148 each register. However, if -fexpensive_optimizations are on, we do so
1149 twice, the second time using the tentative best classes to guide the
1152 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1157 fprintf (dump, "\n\nPass %i\n\n",pass);
1158 /* Zero out our accumulation of the cost of each class for each reg. */
1160 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1162 #ifdef FORBIDDEN_INC_DEC_CLASSES
1163 memset (in_inc_dec, 0, nregs);
1166 /* Scan the instructions and record each time it would
1167 save code to put a certain register in a certain class. */
1172 for (insn = f; insn; insn = NEXT_INSN (insn))
1173 insn = scan_one_insn (insn, pass);
1176 for (index = 0; index < n_basic_blocks; index++)
1178 basic_block bb = BASIC_BLOCK (index);
1180 /* Show that an insn inside a loop is likely to be executed three
1181 times more than insns outside a loop. This is much more
1182 aggressive than the assumptions made elsewhere and is being
1183 tried as an experiment. */
1187 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1188 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1190 insn = scan_one_insn (insn, pass);
1191 if (insn == bb->end)
1196 /* Now for each register look at how desirable each class is
1197 and find which class is preferred. Store that in
1198 `prefclass'. Record in `altclass' the largest register
1199 class any of whose registers is better than memory. */
1202 reg_pref = reg_pref_buffer;
1206 dump_regclass (dump);
1207 fprintf (dump,"\n");
1209 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1211 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1212 enum reg_class best = ALL_REGS, alt = NO_REGS;
1213 /* This is an enum reg_class, but we call it an int
1214 to save lots of casts. */
1216 register struct costs *p = &costs[i];
1218 /* In non-optimizing compilation REG_N_REFS is not initialized
1220 if (optimize && !REG_N_REFS (i))
1223 for (class = (int) ALL_REGS - 1; class > 0; class--)
1225 /* Ignore classes that are too small for this operand or
1226 invalid for a operand that was auto-incremented. */
1227 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1228 > reg_class_size[class]
1229 #ifdef FORBIDDEN_INC_DEC_CLASSES
1230 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1232 #ifdef CLASS_CANNOT_CHANGE_MODE
1233 || (REGNO_REG_SET_P (reg_changes_mode, i)
1234 && ! class_can_change_mode [class])
1238 else if (p->cost[class] < best_cost)
1240 best_cost = p->cost[class];
1241 best = (enum reg_class) class;
1243 else if (p->cost[class] == best_cost)
1244 best = reg_class_subunion[(int)best][class];
1247 /* Record the alternate register class; i.e., a class for which
1248 every register in it is better than using memory. If adding a
1249 class would make a smaller class (i.e., no union of just those
1250 classes exists), skip that class. The major unions of classes
1251 should be provided as a register class. Don't do this if we
1252 will be doing it again later. */
1254 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1255 for (class = 0; class < N_REG_CLASSES; class++)
1256 if (p->cost[class] < p->mem_cost
1257 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1258 > reg_class_size[(int) alt])
1259 #ifdef FORBIDDEN_INC_DEC_CLASSES
1260 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1262 #ifdef CLASS_CANNOT_CHANGE_MODE
1263 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1264 && ! class_can_change_mode [class])
1267 alt = reg_class_subunion[(int) alt][class];
1269 /* If we don't add any classes, nothing to try. */
1274 && (reg_pref[i].prefclass != (int) best
1275 || reg_pref[i].altclass != (int) alt))
1277 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1278 fprintf (dump, " Register %i", i);
1279 if (alt == ALL_REGS || best == ALL_REGS)
1280 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1281 else if (alt == NO_REGS)
1282 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1284 fprintf (dump, " pref %s, else %s\n",
1285 reg_class_names[(int) best],
1286 reg_class_names[(int) alt]);
1289 /* We cast to (int) because (char) hits bugs in some compilers. */
1290 reg_pref[i].prefclass = (int) best;
1291 reg_pref[i].altclass = (int) alt;
1295 #ifdef FORBIDDEN_INC_DEC_CLASSES
1298 #ifdef CLASS_CANNOT_CHANGE_MODE
1299 BITMAP_XFREE (reg_changes_mode);
1304 /* Record the cost of using memory or registers of various classes for
1305 the operands in INSN.
1307 N_ALTS is the number of alternatives.
1309 N_OPS is the number of operands.
1311 OPS is an array of the operands.
1313 MODES are the modes of the operands, in case any are VOIDmode.
1315 CONSTRAINTS are the constraints to use for the operands. This array
1316 is modified by this procedure.
1318 This procedure works alternative by alternative. For each alternative
1319 we assume that we will be able to allocate all pseudos to their ideal
1320 register class and calculate the cost of using that alternative. Then
1321 we compute for each operand that is a pseudo-register, the cost of
1322 having the pseudo allocated to each register class and using it in that
1323 alternative. To this cost is added the cost of the alternative.
1325 The cost of each class for this insn is its lowest cost among all the
1329 record_reg_classes (n_alts, n_ops, ops, modes,
1330 constraints, insn, op_costs, reg_pref)
1334 enum machine_mode *modes;
1335 const char **constraints;
1337 struct costs *op_costs;
1338 struct reg_pref *reg_pref;
1344 /* Process each alternative, each time minimizing an operand's cost with
1345 the cost for each operand in that alternative. */
1347 for (alt = 0; alt < n_alts; alt++)
1349 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1352 enum reg_class classes[MAX_RECOG_OPERANDS];
1353 int allows_mem[MAX_RECOG_OPERANDS];
1356 for (i = 0; i < n_ops; i++)
1358 const char *p = constraints[i];
1360 enum machine_mode mode = modes[i];
1361 int allows_addr = 0;
1365 /* Initially show we know nothing about the register class. */
1366 classes[i] = NO_REGS;
1369 /* If this operand has no constraints at all, we can conclude
1370 nothing about it since anything is valid. */
1374 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1375 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1380 /* If this alternative is only relevant when this operand
1381 matches a previous operand, we do different things depending
1382 on whether this operand is a pseudo-reg or not. We must process
1383 any modifiers for the operand before we can make this test. */
1385 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1388 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1390 /* Copy class and whether memory is allowed from the matching
1391 alternative. Then perform any needed cost computations
1392 and/or adjustments. */
1394 classes[i] = classes[j];
1395 allows_mem[i] = allows_mem[j];
1397 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1399 /* If this matches the other operand, we have no added
1401 if (rtx_equal_p (ops[j], op))
1404 /* If we can put the other operand into a register, add to
1405 the cost of this alternative the cost to copy this
1406 operand to the register used for the other operand. */
1408 else if (classes[j] != NO_REGS)
1409 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1411 else if (GET_CODE (ops[j]) != REG
1412 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1414 /* This op is a pseudo but the one it matches is not. */
1416 /* If we can't put the other operand into a register, this
1417 alternative can't be used. */
1419 if (classes[j] == NO_REGS)
1422 /* Otherwise, add to the cost of this alternative the cost
1423 to copy the other operand to the register used for this
1427 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1431 /* The costs of this operand are not the same as the other
1432 operand since move costs are not symmetric. Moreover,
1433 if we cannot tie them, this alternative needs to do a
1434 copy, which is one instruction. */
1436 struct costs *pp = &this_op_costs[i];
1438 for (class = 0; class < N_REG_CLASSES; class++)
1440 = ((recog_data.operand_type[i] != OP_OUT
1441 ? may_move_in_cost[mode][class][(int) classes[i]]
1443 + (recog_data.operand_type[i] != OP_IN
1444 ? may_move_out_cost[mode][(int) classes[i]][class]
1447 /* If the alternative actually allows memory, make things
1448 a bit cheaper since we won't need an extra insn to
1452 = ((recog_data.operand_type[i] != OP_IN
1453 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1455 + (recog_data.operand_type[i] != OP_OUT
1456 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1457 : 0) - allows_mem[i]);
1459 /* If we have assigned a class to this register in our
1460 first pass, add a cost to this alternative corresponding
1461 to what we would add if this register were not in the
1462 appropriate class. */
1466 += (may_move_in_cost[mode]
1467 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1468 [(int) classes[i]]);
1470 if (REGNO (ops[i]) != REGNO (ops[j])
1471 && ! find_reg_note (insn, REG_DEAD, op))
1474 /* This is in place of ordinary cost computation
1475 for this operand, so skip to the end of the
1476 alternative (should be just one character). */
1477 while (*p && *p++ != ',')
1485 /* Scan all the constraint letters. See if the operand matches
1486 any of the constraints. Collect the valid register classes
1487 and see if this operand accepts memory. */
1489 while (*p && (c = *p++) != ',')
1493 /* Ignore the next letter for this pass. */
1499 case '!': case '#': case '&':
1500 case '0': case '1': case '2': case '3': case '4':
1501 case '5': case '6': case '7': case '8': case '9':
1506 win = address_operand (op, GET_MODE (op));
1507 /* We know this operand is an address, so we want it to be
1508 allocated to a register that can be the base of an
1509 address, ie BASE_REG_CLASS. */
1511 = reg_class_subunion[(int) classes[i]]
1512 [(int) BASE_REG_CLASS];
1515 case 'm': case 'o': case 'V':
1516 /* It doesn't seem worth distinguishing between offsettable
1517 and non-offsettable addresses here. */
1519 if (GET_CODE (op) == MEM)
1524 if (GET_CODE (op) == MEM
1525 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1526 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1531 if (GET_CODE (op) == MEM
1532 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1533 || GET_CODE (XEXP (op, 0)) == POST_INC))
1538 #ifndef REAL_ARITHMETIC
1539 /* Match any floating double constant, but only if
1540 we can examine the bits of it reliably. */
1541 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1542 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1543 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1546 if (GET_CODE (op) == CONST_DOUBLE)
1551 if (GET_CODE (op) == CONST_DOUBLE)
1557 if (GET_CODE (op) == CONST_DOUBLE
1558 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1563 if (GET_CODE (op) == CONST_INT
1564 || (GET_CODE (op) == CONST_DOUBLE
1565 && GET_MODE (op) == VOIDmode))
1569 #ifdef LEGITIMATE_PIC_OPERAND_P
1570 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1577 if (GET_CODE (op) == CONST_INT
1578 || (GET_CODE (op) == CONST_DOUBLE
1579 && GET_MODE (op) == VOIDmode))
1591 if (GET_CODE (op) == CONST_INT
1592 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1601 if (GET_CODE (op) == MEM
1603 #ifdef LEGITIMATE_PIC_OPERAND_P
1604 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1611 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1615 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1617 = reg_class_subunion[(int) classes[i]]
1618 [(int) REG_CLASS_FROM_LETTER (c)];
1619 #ifdef EXTRA_CONSTRAINT
1620 else if (EXTRA_CONSTRAINT (op, c))
1628 /* How we account for this operand now depends on whether it is a
1629 pseudo register or not. If it is, we first check if any
1630 register classes are valid. If not, we ignore this alternative,
1631 since we want to assume that all pseudos get allocated for
1632 register preferencing. If some register class is valid, compute
1633 the costs of moving the pseudo into that class. */
1635 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1637 if (classes[i] == NO_REGS)
1639 /* We must always fail if the operand is a REG, but
1640 we did not find a suitable class.
1642 Otherwise we may perform an uninitialized read
1643 from this_op_costs after the `continue' statement
1649 struct costs *pp = &this_op_costs[i];
1651 for (class = 0; class < N_REG_CLASSES; class++)
1653 = ((recog_data.operand_type[i] != OP_OUT
1654 ? may_move_in_cost[mode][class][(int) classes[i]]
1656 + (recog_data.operand_type[i] != OP_IN
1657 ? may_move_out_cost[mode][(int) classes[i]][class]
1660 /* If the alternative actually allows memory, make things
1661 a bit cheaper since we won't need an extra insn to
1665 = ((recog_data.operand_type[i] != OP_IN
1666 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1668 + (recog_data.operand_type[i] != OP_OUT
1669 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1670 : 0) - allows_mem[i]);
1672 /* If we have assigned a class to this register in our
1673 first pass, add a cost to this alternative corresponding
1674 to what we would add if this register were not in the
1675 appropriate class. */
1679 += (may_move_in_cost[mode]
1680 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1681 [(int) classes[i]]);
1685 /* Otherwise, if this alternative wins, either because we
1686 have already determined that or if we have a hard register of
1687 the proper class, there is no cost for this alternative. */
1690 || (GET_CODE (op) == REG
1691 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1694 /* If registers are valid, the cost of this alternative includes
1695 copying the object to and/or from a register. */
1697 else if (classes[i] != NO_REGS)
1699 if (recog_data.operand_type[i] != OP_OUT)
1700 alt_cost += copy_cost (op, mode, classes[i], 1);
1702 if (recog_data.operand_type[i] != OP_IN)
1703 alt_cost += copy_cost (op, mode, classes[i], 0);
1706 /* The only other way this alternative can be used is if this is a
1707 constant that could be placed into memory. */
1709 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1710 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1718 /* Finally, update the costs with the information we've calculated
1719 about this alternative. */
1721 for (i = 0; i < n_ops; i++)
1722 if (GET_CODE (ops[i]) == REG
1723 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1725 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1726 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1728 pp->mem_cost = MIN (pp->mem_cost,
1729 (qq->mem_cost + alt_cost) * scale);
1731 for (class = 0; class < N_REG_CLASSES; class++)
1732 pp->cost[class] = MIN (pp->cost[class],
1733 (qq->cost[class] + alt_cost) * scale);
1737 /* If this insn is a single set copying operand 1 to operand 0
1738 and one operand is a pseudo with the other a hard reg or a pseudo
1739 that prefers a register that is in its own register class then
1740 we may want to adjust the cost of that register class to -1.
1742 Avoid the adjustment if the source does not die to avoid stressing of
1743 register allocator by preferrencing two coliding registers into single
1746 Also avoid the adjustment if a copy between registers of the class
1747 is expensive (ten times the cost of a default copy is considered
1748 arbitrarily expensive). This avoids losing when the preferred class
1749 is very expensive as the source of a copy instruction. */
1751 if ((set = single_set (insn)) != 0
1752 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1753 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1754 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1755 for (i = 0; i <= 1; i++)
1756 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1758 unsigned int regno = REGNO (ops[!i]);
1759 enum machine_mode mode = GET_MODE (ops[!i]);
1763 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1765 enum reg_class pref = reg_pref[regno].prefclass;
1767 if ((reg_class_size[(unsigned char) pref]
1768 == CLASS_MAX_NREGS (pref, mode))
1769 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1770 op_costs[i].cost[(unsigned char) pref] = -1;
1772 else if (regno < FIRST_PSEUDO_REGISTER)
1773 for (class = 0; class < N_REG_CLASSES; class++)
1774 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1775 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1777 if (reg_class_size[class] == 1)
1778 op_costs[i].cost[class] = -1;
1781 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1783 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1788 if (nr == HARD_REGNO_NREGS (regno,mode))
1789 op_costs[i].cost[class] = -1;
1795 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1796 TO_P is zero) a register of class CLASS in mode MODE.
1798 X must not be a pseudo. */
1801 copy_cost (x, mode, class, to_p)
1803 enum machine_mode mode ATTRIBUTE_UNUSED;
1804 enum reg_class class;
1805 int to_p ATTRIBUTE_UNUSED;
1807 #ifdef HAVE_SECONDARY_RELOADS
1808 enum reg_class secondary_class = NO_REGS;
1811 /* If X is a SCRATCH, there is actually nothing to move since we are
1812 assuming optimal allocation. */
1814 if (GET_CODE (x) == SCRATCH)
1817 /* Get the class we will actually use for a reload. */
1818 class = PREFERRED_RELOAD_CLASS (x, class);
1820 #ifdef HAVE_SECONDARY_RELOADS
1821 /* If we need a secondary reload (we assume here that we are using
1822 the secondary reload as an intermediate, not a scratch register), the
1823 cost is that to load the input into the intermediate register, then
1824 to copy them. We use a special value of TO_P to avoid recursion. */
1826 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1828 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1831 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1833 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1836 if (secondary_class != NO_REGS)
1837 return (move_cost[mode][(int) secondary_class][(int) class]
1838 + copy_cost (x, mode, secondary_class, 2));
1839 #endif /* HAVE_SECONDARY_RELOADS */
1841 /* For memory, use the memory move cost, for (hard) registers, use the
1842 cost to move between the register classes, and use 2 for everything
1843 else (constants). */
1845 if (GET_CODE (x) == MEM || class == NO_REGS)
1846 return MEMORY_MOVE_COST (mode, class, to_p);
1848 else if (GET_CODE (x) == REG)
1849 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1852 /* If this is a constant, we may eventually want to call rtx_cost here. */
1853 return COSTS_N_INSNS (1);
1856 /* Record the pseudo registers we must reload into hard registers
1857 in a subexpression of a memory address, X.
1859 CLASS is the class that the register needs to be in and is either
1860 BASE_REG_CLASS or INDEX_REG_CLASS.
1862 SCALE is twice the amount to multiply the cost by (it is twice so we
1863 can represent half-cost adjustments). */
1866 record_address_regs (x, class, scale)
1868 enum reg_class class;
1871 register enum rtx_code code = GET_CODE (x);
1884 /* When we have an address that is a sum,
1885 we must determine whether registers are "base" or "index" regs.
1886 If there is a sum of two registers, we must choose one to be
1887 the "base". Luckily, we can use the REG_POINTER to make a good
1888 choice most of the time. We only need to do this on machines
1889 that can have two registers in an address and where the base
1890 and index register classes are different.
1892 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1893 that seems bogus since it should only be set when we are sure
1894 the register is being used as a pointer. */
1897 rtx arg0 = XEXP (x, 0);
1898 rtx arg1 = XEXP (x, 1);
1899 register enum rtx_code code0 = GET_CODE (arg0);
1900 register enum rtx_code code1 = GET_CODE (arg1);
1902 /* Look inside subregs. */
1903 if (code0 == SUBREG)
1904 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1905 if (code1 == SUBREG)
1906 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1908 /* If this machine only allows one register per address, it must
1909 be in the first operand. */
1911 if (MAX_REGS_PER_ADDRESS == 1)
1912 record_address_regs (arg0, class, scale);
1914 /* If index and base registers are the same on this machine, just
1915 record registers in any non-constant operands. We assume here,
1916 as well as in the tests below, that all addresses are in
1919 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1921 record_address_regs (arg0, class, scale);
1922 if (! CONSTANT_P (arg1))
1923 record_address_regs (arg1, class, scale);
1926 /* If the second operand is a constant integer, it doesn't change
1927 what class the first operand must be. */
1929 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1930 record_address_regs (arg0, class, scale);
1932 /* If the second operand is a symbolic constant, the first operand
1933 must be an index register. */
1935 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1936 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1938 /* If both operands are registers but one is already a hard register
1939 of index or base class, give the other the class that the hard
1942 #ifdef REG_OK_FOR_BASE_P
1943 else if (code0 == REG && code1 == REG
1944 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1945 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1946 record_address_regs (arg1,
1947 REG_OK_FOR_BASE_P (arg0)
1948 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1950 else if (code0 == REG && code1 == REG
1951 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1952 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1953 record_address_regs (arg0,
1954 REG_OK_FOR_BASE_P (arg1)
1955 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1959 /* If one operand is known to be a pointer, it must be the base
1960 with the other operand the index. Likewise if the other operand
1963 else if ((code0 == REG && REG_POINTER (arg0))
1966 record_address_regs (arg0, BASE_REG_CLASS, scale);
1967 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1969 else if ((code1 == REG && REG_POINTER (arg1))
1972 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1973 record_address_regs (arg1, BASE_REG_CLASS, scale);
1976 /* Otherwise, count equal chances that each might be a base
1977 or index register. This case should be rare. */
1981 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1982 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1983 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1984 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1989 /* Double the importance of a pseudo register that is incremented
1990 or decremented, since it would take two extra insns
1991 if it ends up in the wrong place. */
1994 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
1995 if (REG_P (XEXP (XEXP (x, 1), 1)))
1996 record_address_regs (XEXP (XEXP (x, 1), 1),
1997 INDEX_REG_CLASS, 2 * scale);
2004 /* Double the importance of a pseudo register that is incremented
2005 or decremented, since it would take two extra insns
2006 if it ends up in the wrong place. If the operand is a pseudo,
2007 show it is being used in an INC_DEC context. */
2009 #ifdef FORBIDDEN_INC_DEC_CLASSES
2010 if (GET_CODE (XEXP (x, 0)) == REG
2011 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2012 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2015 record_address_regs (XEXP (x, 0), class, 2 * scale);
2020 register struct costs *pp = &costs[REGNO (x)];
2023 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2025 for (i = 0; i < N_REG_CLASSES; i++)
2026 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2032 register const char *fmt = GET_RTX_FORMAT (code);
2034 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2036 record_address_regs (XEXP (x, i), class, scale);
2041 #ifdef FORBIDDEN_INC_DEC_CLASSES
2043 /* Return 1 if REG is valid as an auto-increment memory reference
2044 to an object of MODE. */
2047 auto_inc_dec_reg_p (reg, mode)
2049 enum machine_mode mode;
2051 if (HAVE_POST_INCREMENT
2052 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2055 if (HAVE_POST_DECREMENT
2056 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2059 if (HAVE_PRE_INCREMENT
2060 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2063 if (HAVE_PRE_DECREMENT
2064 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2071 static short *renumber;
2072 static size_t regno_allocated;
2073 static unsigned int reg_n_max;
2075 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2076 reg_scan and flow_analysis that are indexed by the register number. If
2077 NEW_P is non zero, initialize all of the registers, otherwise only
2078 initialize the new registers allocated. The same table is kept from
2079 function to function, only reallocating it when we need more room. If
2080 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2083 allocate_reg_info (num_regs, new_p, renumber_p)
2089 size_t size_renumber;
2090 size_t min = (new_p) ? 0 : reg_n_max;
2091 struct reg_info_data *reg_data;
2093 if (num_regs > regno_allocated)
2095 size_t old_allocated = regno_allocated;
2097 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2098 size_renumber = regno_allocated * sizeof (short);
2102 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2103 renumber = (short *) xmalloc (size_renumber);
2104 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2105 * sizeof (struct reg_pref));
2110 VARRAY_GROW (reg_n_info, regno_allocated);
2112 if (new_p) /* if we're zapping everything, no need to realloc */
2114 free ((char *)renumber);
2115 free ((char *)reg_pref);
2116 renumber = (short *) xmalloc (size_renumber);
2117 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2118 * sizeof (struct reg_pref));
2123 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2124 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2126 * sizeof (struct reg_pref));
2130 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2131 + sizeof (struct reg_info_data) - sizeof (reg_info);
2132 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2133 reg_data->min_index = old_allocated;
2134 reg_data->max_index = regno_allocated - 1;
2135 reg_data->next = reg_info_head;
2136 reg_info_head = reg_data;
2139 reg_n_max = num_regs;
2142 /* Loop through each of the segments allocated for the actual
2143 reg_info pages, and set up the pointers, zero the pages, etc. */
2144 for (reg_data = reg_info_head;
2145 reg_data && reg_data->max_index >= min;
2146 reg_data = reg_data->next)
2148 size_t min_index = reg_data->min_index;
2149 size_t max_index = reg_data->max_index;
2150 size_t max = MIN (max_index, num_regs);
2151 size_t local_min = min - min_index;
2154 if (reg_data->min_index > num_regs)
2157 if (min < min_index)
2159 if (!reg_data->used_p) /* page just allocated with calloc */
2160 reg_data->used_p = 1; /* no need to zero */
2162 memset ((char *) ®_data->data[local_min], 0,
2163 sizeof (reg_info) * (max - min_index - local_min + 1));
2165 for (i = min_index+local_min; i <= max; i++)
2167 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2168 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2170 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2171 reg_pref_buffer[i].altclass = (char) NO_REGS;
2176 /* If {pref,alt}class have already been allocated, update the pointers to
2177 the newly realloced ones. */
2179 reg_pref = reg_pref_buffer;
2182 reg_renumber = renumber;
2184 /* Tell the regset code about the new number of registers */
2185 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2188 /* Free up the space allocated by allocate_reg_info. */
2194 struct reg_info_data *reg_data;
2195 struct reg_info_data *reg_next;
2197 VARRAY_FREE (reg_n_info);
2198 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2200 reg_next = reg_data->next;
2201 free ((char *)reg_data);
2204 free (reg_pref_buffer);
2205 reg_pref_buffer = (struct reg_pref *)0;
2206 reg_info_head = (struct reg_info_data *)0;
2207 renumber = (short *)0;
2209 regno_allocated = 0;
2213 /* This is the `regscan' pass of the compiler, run just before cse
2214 and again just before loop.
2216 It finds the first and last use of each pseudo-register
2217 and records them in the vectors regno_first_uid, regno_last_uid
2218 and counts the number of sets in the vector reg_n_sets.
2220 REPEAT is nonzero the second time this is called. */
2222 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2223 Always at least 3, since the combiner could put that many together
2224 and we want this to remain correct for all the remaining passes.
2225 This corresponds to the maximum number of times note_stores will call
2226 a function for any insn. */
2230 /* Used as a temporary to record the largest number of registers in
2231 PARALLEL in a SET_DEST. This is added to max_parallel. */
2233 static int max_set_parallel;
2236 reg_scan (f, nregs, repeat)
2239 int repeat ATTRIBUTE_UNUSED;
2243 allocate_reg_info (nregs, TRUE, FALSE);
2245 max_set_parallel = 0;
2247 for (insn = f; insn; insn = NEXT_INSN (insn))
2248 if (GET_CODE (insn) == INSN
2249 || GET_CODE (insn) == CALL_INSN
2250 || GET_CODE (insn) == JUMP_INSN)
2252 if (GET_CODE (PATTERN (insn)) == PARALLEL
2253 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2254 max_parallel = XVECLEN (PATTERN (insn), 0);
2255 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2257 if (REG_NOTES (insn))
2258 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2261 max_parallel += max_set_parallel;
2264 /* Update 'regscan' information by looking at the insns
2265 from FIRST to LAST. Some new REGs have been created,
2266 and any REG with number greater than OLD_MAX_REGNO is
2267 such a REG. We only update information for those. */
2270 reg_scan_update (first, last, old_max_regno)
2273 unsigned int old_max_regno;
2277 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2279 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2280 if (GET_CODE (insn) == INSN
2281 || GET_CODE (insn) == CALL_INSN
2282 || GET_CODE (insn) == JUMP_INSN)
2284 if (GET_CODE (PATTERN (insn)) == PARALLEL
2285 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2286 max_parallel = XVECLEN (PATTERN (insn), 0);
2287 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2289 if (REG_NOTES (insn))
2290 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2294 /* X is the expression to scan. INSN is the insn it appears in.
2295 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2296 We should only record information for REGs with numbers
2297 greater than or equal to MIN_REGNO. */
2300 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2304 unsigned int min_regno;
2306 register enum rtx_code code;
2310 code = GET_CODE (x);
2326 unsigned int regno = REGNO (x);
2328 if (regno >= min_regno)
2330 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2332 REGNO_LAST_UID (regno) = INSN_UID (insn);
2333 if (REGNO_FIRST_UID (regno) == 0)
2334 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2341 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2343 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2348 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2352 /* Count a set of the destination if it is a register. */
2353 for (dest = SET_DEST (x);
2354 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2355 || GET_CODE (dest) == ZERO_EXTEND;
2356 dest = XEXP (dest, 0))
2359 /* For a PARALLEL, record the number of things (less the usual one for a
2360 SET) that are set. */
2361 if (GET_CODE (dest) == PARALLEL)
2362 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2364 if (GET_CODE (dest) == REG
2365 && REGNO (dest) >= min_regno)
2366 REG_N_SETS (REGNO (dest))++;
2368 /* If this is setting a pseudo from another pseudo or the sum of a
2369 pseudo and a constant integer and the other pseudo is known to be
2370 a pointer, set the destination to be a pointer as well.
2372 Likewise if it is setting the destination from an address or from a
2373 value equivalent to an address or to the sum of an address and
2376 But don't do any of this if the pseudo corresponds to a user
2377 variable since it should have already been set as a pointer based
2380 if (GET_CODE (SET_DEST (x)) == REG
2381 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2382 && REGNO (SET_DEST (x)) >= min_regno
2383 /* If the destination pseudo is set more than once, then other
2384 sets might not be to a pointer value (consider access to a
2385 union in two threads of control in the presense of global
2386 optimizations). So only set REG_POINTER on the destination
2387 pseudo if this is the only set of that pseudo. */
2388 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2389 && ! REG_USERVAR_P (SET_DEST (x))
2390 && ! REG_POINTER (SET_DEST (x))
2391 && ((GET_CODE (SET_SRC (x)) == REG
2392 && REG_POINTER (SET_SRC (x)))
2393 || ((GET_CODE (SET_SRC (x)) == PLUS
2394 || GET_CODE (SET_SRC (x)) == LO_SUM)
2395 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2396 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2397 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2398 || GET_CODE (SET_SRC (x)) == CONST
2399 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2400 || GET_CODE (SET_SRC (x)) == LABEL_REF
2401 || (GET_CODE (SET_SRC (x)) == HIGH
2402 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2403 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2404 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2405 || ((GET_CODE (SET_SRC (x)) == PLUS
2406 || GET_CODE (SET_SRC (x)) == LO_SUM)
2407 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2408 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2409 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2410 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2411 && (GET_CODE (XEXP (note, 0)) == CONST
2412 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2413 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2414 REG_POINTER (SET_DEST (x)) = 1;
2416 /* ... fall through ... */
2420 register const char *fmt = GET_RTX_FORMAT (code);
2422 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2425 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2426 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2429 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2430 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2437 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2441 reg_class_subset_p (c1, c2)
2442 register enum reg_class c1;
2443 register enum reg_class c2;
2445 if (c1 == c2) return 1;
2450 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2451 reg_class_contents[(int)c2],
2456 /* Return nonzero if there is a register that is in both C1 and C2. */
2459 reg_classes_intersect_p (c1, c2)
2460 register enum reg_class c1;
2461 register enum reg_class c2;
2468 if (c1 == c2) return 1;
2470 if (c1 == ALL_REGS || c2 == ALL_REGS)
2473 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2474 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2476 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2483 /* Release any memory allocated by register sets. */
2486 regset_release_memory ()
2488 bitmap_release_memory ();