1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 /* This file contains two passes of the compiler: reg_scan and reg_class.
25 It also defines some tables of information about the hardware registers
26 and a function init_reg_sets to initialize the tables. */
30 #include "coretypes.h"
32 #include "hard-reg-set.h"
37 #include "basic-block.h"
39 #include "addresses.h"
41 #include "insn-config.h"
52 static void init_reg_sets_1 (void);
53 static void init_reg_autoinc (void);
55 /* If we have auto-increment or auto-decrement and we can have secondary
56 reloads, we are not allowed to use classes requiring secondary
57 reloads for pseudos auto-incremented since reload can't handle it. */
58 /* We leave it to target hooks to decide if we have secondary reloads, so
59 assume that we might have them. */
60 #if defined(AUTO_INC_DEC) /* */
61 #define FORBIDDEN_INC_DEC_CLASSES
64 /* Register tables used by many passes. */
66 /* Indexed by hard register number, contains 1 for registers
67 that are fixed use (stack pointer, pc, frame pointer, etc.).
68 These are the registers that cannot be used to allocate
69 a pseudo reg for general use. */
71 char fixed_regs[FIRST_PSEUDO_REGISTER];
73 /* Same info as a HARD_REG_SET. */
75 HARD_REG_SET fixed_reg_set;
77 /* Data for initializing the above. */
79 static const char initial_fixed_regs[] = FIXED_REGISTERS;
81 /* Indexed by hard register number, contains 1 for registers
82 that are fixed use or are clobbered by function calls.
83 These are the registers that cannot be used to allocate
84 a pseudo reg whose life crosses calls unless we are able
85 to save/restore them across the calls. */
87 char call_used_regs[FIRST_PSEUDO_REGISTER];
89 /* Same info as a HARD_REG_SET. */
91 HARD_REG_SET call_used_reg_set;
93 /* HARD_REG_SET of registers we want to avoid caller saving. */
94 HARD_REG_SET losing_caller_save_reg_set;
96 /* Data for initializing the above. */
98 static const char initial_call_used_regs[] = CALL_USED_REGISTERS;
100 /* This is much like call_used_regs, except it doesn't have to
101 be a superset of FIXED_REGISTERS. This vector indicates
102 what is really call clobbered, and is used when defining
103 regs_invalidated_by_call. */
105 #ifdef CALL_REALLY_USED_REGISTERS
106 char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS;
109 #ifdef CALL_REALLY_USED_REGISTERS
110 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
112 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
116 /* Indexed by hard register number, contains 1 for registers that are
117 fixed use or call used registers that cannot hold quantities across
118 calls even if we are willing to save and restore them. call fixed
119 registers are a subset of call used registers. */
121 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
123 /* The same info as a HARD_REG_SET. */
125 HARD_REG_SET call_fixed_reg_set;
127 /* Indexed by hard register number, contains 1 for registers
128 that are being used for global register decls.
129 These must be exempt from ordinary flow analysis
130 and are also considered fixed. */
132 char global_regs[FIRST_PSEUDO_REGISTER];
134 /* Contains 1 for registers that are set or clobbered by calls. */
135 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
136 for someone's bright idea to have call_used_regs strictly include
137 fixed_regs. Which leaves us guessing as to the set of fixed_regs
138 that are actually preserved. We know for sure that those associated
139 with the local stack frame are safe, but scant others. */
141 HARD_REG_SET regs_invalidated_by_call;
143 /* Table of register numbers in the order in which to try to use them. */
144 #ifdef REG_ALLOC_ORDER
145 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
147 /* The inverse of reg_alloc_order. */
148 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
151 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
153 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
155 /* The same information, but as an array of unsigned ints. We copy from
156 these unsigned ints to the table above. We do this so the tm.h files
157 do not have to be aware of the wordsize for machines with <= 64 regs.
158 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
161 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
163 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
164 = REG_CLASS_CONTENTS;
166 /* For each reg class, number of regs it contains. */
168 unsigned int reg_class_size[N_REG_CLASSES];
170 /* For each reg class, table listing all the containing classes. */
172 static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
174 /* For each reg class, table listing all the classes contained in it. */
176 static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
178 /* For each pair of reg classes,
179 a largest reg class contained in their union. */
181 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
183 /* For each pair of reg classes,
184 the smallest reg class containing their union. */
186 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
188 /* Array containing all of the register names. */
190 const char * reg_names[] = REGISTER_NAMES;
192 /* Array containing all of the register class names. */
194 const char * reg_class_names[] = REG_CLASS_NAMES;
196 /* For each hard register, the widest mode object that it can contain.
197 This will be a MODE_INT mode if the register can hold integers. Otherwise
198 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
201 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
203 /* 1 if there is a register of given mode. */
205 bool have_regs_of_mode [MAX_MACHINE_MODE];
207 /* 1 if class does contain register of given mode. */
209 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
211 /* Maximum cost of moving from a register in one class to a register in
212 another class. Based on REGISTER_MOVE_COST. */
214 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
216 /* Similar, but here we don't have to move if the first index is a subset
217 of the second so in that case the cost is zero. */
219 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
221 /* Similar, but here we don't have to move if the first index is a superset
222 of the second so in that case the cost is zero. */
224 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
226 #ifdef FORBIDDEN_INC_DEC_CLASSES
228 /* These are the classes that regs which are auto-incremented or decremented
231 static int forbidden_inc_dec_class[N_REG_CLASSES];
233 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
236 static char *in_inc_dec;
238 #endif /* FORBIDDEN_INC_DEC_CLASSES */
240 /* Sample MEM values for use by memory_move_secondary_cost. */
242 static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE];
244 /* Linked list of reg_info structures allocated for reg_n_info array.
245 Grouping all of the allocated structures together in one lump
246 means only one call to bzero to clear them, rather than n smaller
248 struct reg_info_data {
249 struct reg_info_data *next; /* next set of reg_info structures */
250 size_t min_index; /* minimum index # */
251 size_t max_index; /* maximum index # */
252 char used_p; /* nonzero if this has been used previously */
253 reg_info data[1]; /* beginning of the reg_info data */
256 static struct reg_info_data *reg_info_head;
258 /* No more global register variables may be declared; true once
259 regclass has been initialized. */
261 static int no_global_reg_vars = 0;
263 /* Specify number of hard registers given machine mode occupy. */
264 unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
266 /* Function called only once to initialize the above data on reg usage.
267 Once this is done, various switches may override. */
274 /* First copy the register information from the initial int form into
277 for (i = 0; i < N_REG_CLASSES; i++)
279 CLEAR_HARD_REG_SET (reg_class_contents[i]);
281 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
282 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
283 if (int_reg_class_contents[i][j / 32]
284 & ((unsigned) 1 << (j % 32)))
285 SET_HARD_REG_BIT (reg_class_contents[i], j);
288 /* Sanity check: make sure the target macros FIXED_REGISTERS and
289 CALL_USED_REGISTERS had the right number of initializers. */
290 gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs);
291 gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs);
293 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
294 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
295 memset (global_regs, 0, sizeof global_regs);
297 #ifdef REG_ALLOC_ORDER
298 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
299 inv_reg_alloc_order[reg_alloc_order[i]] = i;
303 /* After switches have been processed, which perhaps alter
304 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
307 init_reg_sets_1 (void)
310 unsigned int /* enum machine_mode */ m;
312 /* This macro allows the fixed or call-used registers
313 and the register classes to depend on target flags. */
315 #ifdef CONDITIONAL_REGISTER_USAGE
316 CONDITIONAL_REGISTER_USAGE;
319 /* Compute number of hard regs in each class. */
321 memset (reg_class_size, 0, sizeof reg_class_size);
322 for (i = 0; i < N_REG_CLASSES; i++)
323 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
324 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
327 /* Initialize the table of subunions.
328 reg_class_subunion[I][J] gets the largest-numbered reg-class
329 that is contained in the union of classes I and J. */
331 for (i = 0; i < N_REG_CLASSES; i++)
333 for (j = 0; j < N_REG_CLASSES; j++)
338 COPY_HARD_REG_SET (c, reg_class_contents[i]);
339 IOR_HARD_REG_SET (c, reg_class_contents[j]);
340 for (k = 0; k < N_REG_CLASSES; k++)
341 if (hard_reg_set_subset_p (reg_class_contents[k], c)
342 && !hard_reg_set_subset_p (reg_class_contents[k],
344 [(int) reg_class_subunion[i][j]]))
345 reg_class_subunion[i][j] = (enum reg_class) k;
349 /* Initialize the table of superunions.
350 reg_class_superunion[I][J] gets the smallest-numbered reg-class
351 containing the union of classes I and J. */
353 for (i = 0; i < N_REG_CLASSES; i++)
355 for (j = 0; j < N_REG_CLASSES; j++)
360 COPY_HARD_REG_SET (c, reg_class_contents[i]);
361 IOR_HARD_REG_SET (c, reg_class_contents[j]);
362 for (k = 0; k < N_REG_CLASSES; k++)
363 if (hard_reg_set_subset_p (c, reg_class_contents[k]))
366 reg_class_superunion[i][j] = (enum reg_class) k;
370 /* Initialize the tables of subclasses and superclasses of each reg class.
371 First clear the whole table, then add the elements as they are found. */
373 for (i = 0; i < N_REG_CLASSES; i++)
375 for (j = 0; j < N_REG_CLASSES; j++)
377 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
378 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
382 for (i = 0; i < N_REG_CLASSES; i++)
384 if (i == (int) NO_REGS)
387 for (j = i + 1; j < N_REG_CLASSES; j++)
388 if (hard_reg_set_subset_p (reg_class_contents[i],
389 reg_class_contents[j]))
391 /* Reg class I is a subclass of J.
392 Add J to the table of superclasses of I. */
395 p = ®_class_superclasses[i][0];
396 while (*p != LIM_REG_CLASSES) p++;
397 *p = (enum reg_class) j;
398 /* Add I to the table of superclasses of J. */
399 p = ®_class_subclasses[j][0];
400 while (*p != LIM_REG_CLASSES) p++;
401 *p = (enum reg_class) i;
405 /* Initialize "constant" tables. */
407 CLEAR_HARD_REG_SET (fixed_reg_set);
408 CLEAR_HARD_REG_SET (call_used_reg_set);
409 CLEAR_HARD_REG_SET (call_fixed_reg_set);
410 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
412 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
414 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
416 /* call_used_regs must include fixed_regs. */
417 gcc_assert (!fixed_regs[i] || call_used_regs[i]);
418 #ifdef CALL_REALLY_USED_REGISTERS
419 /* call_used_regs must include call_really_used_regs. */
420 gcc_assert (!call_really_used_regs[i] || call_used_regs[i]);
424 SET_HARD_REG_BIT (fixed_reg_set, i);
426 if (call_used_regs[i])
427 SET_HARD_REG_BIT (call_used_reg_set, i);
428 if (call_fixed_regs[i])
429 SET_HARD_REG_BIT (call_fixed_reg_set, i);
430 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
431 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
433 /* There are a couple of fixed registers that we know are safe to
434 exclude from being clobbered by calls:
436 The frame pointer is always preserved across calls. The arg pointer
437 is if it is fixed. The stack pointer usually is, unless
438 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
439 If we are generating PIC code, the PIC offset table register is
440 preserved across calls, though the target can override that. */
442 if (i == STACK_POINTER_REGNUM)
444 else if (global_regs[i])
445 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
446 else if (i == FRAME_POINTER_REGNUM)
448 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
449 else if (i == HARD_FRAME_POINTER_REGNUM)
452 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
453 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
456 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
457 else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i])
460 else if (CALL_REALLY_USED_REGNO_P (i))
461 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
464 memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode));
465 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
466 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
467 for (i = 0; i < N_REG_CLASSES; i++)
468 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
469 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
470 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
471 && HARD_REGNO_MODE_OK (j, m))
473 contains_reg_of_mode [i][m] = 1;
474 have_regs_of_mode [m] = 1;
478 /* Initialize the move cost table. Find every subset of each class
479 and take the maximum cost of moving any subset to any other. */
481 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
482 if (have_regs_of_mode [m])
484 for (i = 0; i < N_REG_CLASSES; i++)
485 if (contains_reg_of_mode [i][m])
486 for (j = 0; j < N_REG_CLASSES; j++)
489 enum reg_class *p1, *p2;
491 if (!contains_reg_of_mode [j][m])
493 move_cost[m][i][j] = 65536;
494 may_move_in_cost[m][i][j] = 65536;
495 may_move_out_cost[m][i][j] = 65536;
499 cost = REGISTER_MOVE_COST (m, i, j);
501 for (p2 = ®_class_subclasses[j][0];
502 *p2 != LIM_REG_CLASSES;
504 if (*p2 != i && contains_reg_of_mode [*p2][m])
505 cost = MAX (cost, move_cost [m][i][*p2]);
507 for (p1 = ®_class_subclasses[i][0];
508 *p1 != LIM_REG_CLASSES;
510 if (*p1 != j && contains_reg_of_mode [*p1][m])
511 cost = MAX (cost, move_cost [m][*p1][j]);
513 move_cost[m][i][j] = cost;
515 if (reg_class_subset_p (i, j))
516 may_move_in_cost[m][i][j] = 0;
518 may_move_in_cost[m][i][j] = cost;
520 if (reg_class_subset_p (j, i))
521 may_move_out_cost[m][i][j] = 0;
523 may_move_out_cost[m][i][j] = cost;
527 for (j = 0; j < N_REG_CLASSES; j++)
529 move_cost[m][i][j] = 65536;
530 may_move_in_cost[m][i][j] = 65536;
531 may_move_out_cost[m][i][j] = 65536;
536 /* Compute the table of register modes.
537 These values are used to record death information for individual registers
538 (as opposed to a multi-register mode). */
541 init_reg_modes_once (void)
545 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
546 for (j = 0; j < MAX_MACHINE_MODE; j++)
547 hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j);
549 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
551 reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false);
553 /* If we couldn't find a valid mode, just use the previous mode.
554 ??? One situation in which we need to do this is on the mips where
555 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
556 to use DF mode for the even registers and VOIDmode for the odd
557 (for the cpu models where the odd ones are inaccessible). */
558 if (reg_raw_mode[i] == VOIDmode)
559 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
563 /* Finish initializing the register sets and
564 initialize the register modes. */
569 /* This finishes what was started by init_reg_sets, but couldn't be done
570 until after register usage was specified. */
576 /* Initialize some fake stack-frame MEM references for use in
577 memory_move_secondary_cost. */
580 init_fake_stack_mems (void)
585 for (i = 0; i < MAX_MACHINE_MODE; i++)
586 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
591 /* Compute extra cost of moving registers to/from memory due to reloads.
592 Only needed if secondary reloads are required for memory moves. */
595 memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in)
597 enum reg_class altclass;
598 int partial_cost = 0;
599 /* We need a memory reference to feed to SECONDARY... macros. */
600 /* mem may be unused even if the SECONDARY_ macros are defined. */
601 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
604 altclass = secondary_reload_class (in ? 1 : 0, class, mode, mem);
606 if (altclass == NO_REGS)
610 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
612 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
614 if (class == altclass)
615 /* This isn't simply a copy-to-temporary situation. Can't guess
616 what it is, so MEMORY_MOVE_COST really ought not to be calling
619 I'm tempted to put in an assert here, but returning this will
620 probably only give poor estimates, which is what we would've
621 had before this code anyways. */
624 /* Check if the secondary reload register will also need a
626 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
629 /* Return a machine mode that is legitimate for hard reg REGNO and large
630 enough to save nregs. If we can't find one, return VOIDmode.
631 If CALL_SAVED is true, only consider modes that are call saved. */
634 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED,
635 unsigned int nregs, bool call_saved)
637 unsigned int /* enum machine_mode */ m;
638 enum machine_mode found_mode = VOIDmode, mode;
640 /* We first look for the largest integer mode that can be validly
641 held in REGNO. If none, we look for the largest floating-point mode.
642 If we still didn't find a valid mode, try CCmode. */
644 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
646 mode = GET_MODE_WIDER_MODE (mode))
647 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
648 && HARD_REGNO_MODE_OK (regno, mode)
649 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
652 if (found_mode != VOIDmode)
655 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
657 mode = GET_MODE_WIDER_MODE (mode))
658 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
659 && HARD_REGNO_MODE_OK (regno, mode)
660 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
663 if (found_mode != VOIDmode)
666 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
668 mode = GET_MODE_WIDER_MODE (mode))
669 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
670 && HARD_REGNO_MODE_OK (regno, mode)
671 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
674 if (found_mode != VOIDmode)
677 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
679 mode = GET_MODE_WIDER_MODE (mode))
680 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
681 && HARD_REGNO_MODE_OK (regno, mode)
682 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
685 if (found_mode != VOIDmode)
688 /* Iterate over all of the CCmodes. */
689 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
691 mode = (enum machine_mode) m;
692 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
693 && HARD_REGNO_MODE_OK (regno, mode)
694 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
698 /* We can't find a mode valid for this register. */
702 /* Specify the usage characteristics of the register named NAME.
703 It should be a fixed register if FIXED and a
704 call-used register if CALL_USED. */
707 fix_register (const char *name, int fixed, int call_used)
711 /* Decode the name and update the primary form of
712 the register info. */
714 if ((i = decode_reg_name (name)) >= 0)
716 if ((i == STACK_POINTER_REGNUM
717 #ifdef HARD_FRAME_POINTER_REGNUM
718 || i == HARD_FRAME_POINTER_REGNUM
720 || i == FRAME_POINTER_REGNUM
723 && (fixed == 0 || call_used == 0))
725 static const char * const what_option[2][2] = {
726 { "call-saved", "call-used" },
727 { "no-such-option", "fixed" }};
729 error ("can't use '%s' as a %s register", name,
730 what_option[fixed][call_used]);
734 fixed_regs[i] = fixed;
735 call_used_regs[i] = call_used;
736 #ifdef CALL_REALLY_USED_REGISTERS
738 call_really_used_regs[i] = call_used;
744 warning (0, "unknown register name: %s", name);
748 /* Mark register number I as global. */
751 globalize_reg (int i)
753 if (fixed_regs[i] == 0 && no_global_reg_vars)
754 error ("global register variable follows a function definition");
758 warning (0, "register used for two global register variables");
762 if (call_used_regs[i] && ! fixed_regs[i])
763 warning (0, "call-clobbered register used for global register variable");
767 /* If we're globalizing the frame pointer, we need to set the
768 appropriate regs_invalidated_by_call bit, even if it's already
769 set in fixed_regs. */
770 if (i != STACK_POINTER_REGNUM)
771 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
773 /* If already fixed, nothing else to do. */
777 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
778 #ifdef CALL_REALLY_USED_REGISTERS
779 call_really_used_regs[i] = 1;
782 SET_HARD_REG_BIT (fixed_reg_set, i);
783 SET_HARD_REG_BIT (call_used_reg_set, i);
784 SET_HARD_REG_BIT (call_fixed_reg_set, i);
787 /* Now the data and code for the `regclass' pass, which happens
788 just before local-alloc. */
790 /* The `costs' struct records the cost of using a hard register of each class
791 and of using memory for each pseudo. We use this data to set up
792 register class preferences. */
796 int cost[N_REG_CLASSES];
800 /* Structure used to record preferences of given pseudo. */
803 /* (enum reg_class) prefclass is the preferred class. May be
804 NO_REGS if no class is better than memory. */
807 /* altclass is a register class that we should use for allocating
808 pseudo if no register in the preferred class is available.
809 If no register in this class is available, memory is preferred.
811 It might appear to be more general to have a bitmask of classes here,
812 but since it is recommended that there be a class corresponding to the
813 union of most major pair of classes, that generality is not required. */
817 /* Record the cost of each class for each pseudo. */
819 static struct costs *costs;
821 /* Initialized once, and used to initialize cost values for each insn. */
823 static struct costs init_cost;
825 /* Record preferences of each pseudo.
826 This is available after `regclass' is run. */
828 static struct reg_pref *reg_pref;
830 /* Allocated buffers for reg_pref. */
832 static struct reg_pref *reg_pref_buffer;
834 /* Frequency of executions of current insn. */
836 static int frequency;
838 static rtx scan_one_insn (rtx, int);
839 static void record_operand_costs (rtx, struct costs *, struct reg_pref *);
840 static void dump_regclass (FILE *);
841 static void record_reg_classes (int, int, rtx *, enum machine_mode *,
842 const char **, rtx, struct costs *,
844 static int copy_cost (rtx, enum machine_mode, enum reg_class, int,
845 secondary_reload_info *);
846 static void record_address_regs (enum machine_mode, rtx, int, enum rtx_code,
848 #ifdef FORBIDDEN_INC_DEC_CLASSES
849 static int auto_inc_dec_reg_p (rtx, enum machine_mode);
851 static void reg_scan_mark_refs (rtx, rtx, int, unsigned int);
853 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
856 ok_for_index_p_nonstrict (rtx reg)
858 unsigned regno = REGNO (reg);
859 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
862 /* A version of regno_ok_for_base_p for use during regclass, when all pseudos
863 should count as OK. Arguments as for regno_ok_for_base_p. */
866 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode,
867 enum rtx_code outer_code, enum rtx_code index_code)
869 unsigned regno = REGNO (reg);
870 if (regno >= FIRST_PSEUDO_REGISTER)
873 return ok_for_base_p_1 (regno, mode, outer_code, index_code);
876 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
877 This function is sometimes called before the info has been computed.
878 When that happens, just return GENERAL_REGS, which is innocuous. */
881 reg_preferred_class (int regno)
885 return (enum reg_class) reg_pref[regno].prefclass;
889 reg_alternate_class (int regno)
894 return (enum reg_class) reg_pref[regno].altclass;
897 /* Initialize some global data for this pass. */
904 init_cost.mem_cost = 10000;
905 for (i = 0; i < N_REG_CLASSES; i++)
906 init_cost.cost[i] = 10000;
908 /* This prevents dump_flow_info from losing if called
909 before regclass is run. */
912 /* No more global register variables may be declared. */
913 no_global_reg_vars = 1;
916 /* Dump register costs. */
918 dump_regclass (FILE *dump)
921 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 int /* enum reg_class */ class;
926 fprintf (dump, " Register %i costs:", i);
927 for (class = 0; class < (int) N_REG_CLASSES; class++)
928 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
929 #ifdef FORBIDDEN_INC_DEC_CLASSES
931 || !forbidden_inc_dec_class[(enum reg_class) class])
933 #ifdef CANNOT_CHANGE_MODE_CLASS
934 && ! invalid_mode_change_p (i, (enum reg_class) class,
935 PSEUDO_REGNO_MODE (i))
938 fprintf (dump, " %s:%i", reg_class_names[class],
939 costs[i].cost[(enum reg_class) class]);
940 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
946 /* Calculate the costs of insn operands. */
949 record_operand_costs (rtx insn, struct costs *op_costs,
950 struct reg_pref *reg_pref)
952 const char *constraints[MAX_RECOG_OPERANDS];
953 enum machine_mode modes[MAX_RECOG_OPERANDS];
956 for (i = 0; i < recog_data.n_operands; i++)
958 constraints[i] = recog_data.constraints[i];
959 modes[i] = recog_data.operand_mode[i];
962 /* If we get here, we are set up to record the costs of all the
963 operands for this insn. Start by initializing the costs.
964 Then handle any address registers. Finally record the desired
965 classes for any pseudos, doing it twice if some pair of
966 operands are commutative. */
968 for (i = 0; i < recog_data.n_operands; i++)
970 op_costs[i] = init_cost;
972 if (GET_CODE (recog_data.operand[i]) == SUBREG)
973 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
975 if (MEM_P (recog_data.operand[i]))
976 record_address_regs (GET_MODE (recog_data.operand[i]),
977 XEXP (recog_data.operand[i], 0),
978 0, MEM, SCRATCH, frequency * 2);
979 else if (constraints[i][0] == 'p'
980 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i]))
981 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS,
982 SCRATCH, frequency * 2);
985 /* Check for commutative in a separate loop so everything will
986 have been initialized. We must do this even if one operand
987 is a constant--see addsi3 in m68k.md. */
989 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
990 if (constraints[i][0] == '%')
992 const char *xconstraints[MAX_RECOG_OPERANDS];
995 /* Handle commutative operands by swapping the constraints.
996 We assume the modes are the same. */
998 for (j = 0; j < recog_data.n_operands; j++)
999 xconstraints[j] = constraints[j];
1001 xconstraints[i] = constraints[i+1];
1002 xconstraints[i+1] = constraints[i];
1003 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1004 recog_data.operand, modes,
1005 xconstraints, insn, op_costs, reg_pref);
1008 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1009 recog_data.operand, modes,
1010 constraints, insn, op_costs, reg_pref);
1013 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1014 time it would save code to put a certain register in a certain class.
1015 PASS, when nonzero, inhibits some optimizations which need only be done
1017 Return the last insn processed, so that the scan can be continued from
1021 scan_one_insn (rtx insn, int pass ATTRIBUTE_UNUSED)
1023 enum rtx_code pat_code;
1026 struct costs op_costs[MAX_RECOG_OPERANDS];
1031 pat_code = GET_CODE (PATTERN (insn));
1033 || pat_code == CLOBBER
1034 || pat_code == ASM_INPUT
1035 || pat_code == ADDR_VEC
1036 || pat_code == ADDR_DIFF_VEC)
1039 set = single_set (insn);
1040 extract_insn (insn);
1042 /* If this insn loads a parameter from its stack slot, then
1043 it represents a savings, rather than a cost, if the
1044 parameter is stored in memory. Record this fact. */
1046 if (set != 0 && REG_P (SET_DEST (set))
1047 && MEM_P (SET_SRC (set))
1048 && (note = find_reg_note (insn, REG_EQUIV,
1050 && MEM_P (XEXP (note, 0)))
1052 costs[REGNO (SET_DEST (set))].mem_cost
1053 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1056 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0),
1057 0, MEM, SCRATCH, frequency * 2);
1061 record_operand_costs (insn, op_costs, reg_pref);
1063 /* Now add the cost for each operand to the total costs for
1066 for (i = 0; i < recog_data.n_operands; i++)
1067 if (REG_P (recog_data.operand[i])
1068 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1070 int regno = REGNO (recog_data.operand[i]);
1071 struct costs *p = &costs[regno], *q = &op_costs[i];
1073 p->mem_cost += q->mem_cost * frequency;
1074 for (j = 0; j < N_REG_CLASSES; j++)
1075 p->cost[j] += q->cost[j] * frequency;
1081 /* Initialize information about which register classes can be used for
1082 pseudos that are auto-incremented or auto-decremented. */
1085 init_reg_autoinc (void)
1087 #ifdef FORBIDDEN_INC_DEC_CLASSES
1090 for (i = 0; i < N_REG_CLASSES; i++)
1092 rtx r = gen_rtx_raw_REG (VOIDmode, 0);
1093 enum machine_mode m;
1096 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1097 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1101 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1102 m = (enum machine_mode) ((int) m + 1))
1103 if (HARD_REGNO_MODE_OK (j, m))
1105 /* ??? There are two assumptions here; that the base class does not
1106 depend on the exact outer code (POST_INC vs. PRE_INC etc.), and
1107 that it does not depend on the machine mode of the memory
1109 enum reg_class base_class
1110 = base_reg_class (VOIDmode, POST_INC, SCRATCH);
1114 /* If a register is not directly suitable for an
1115 auto-increment or decrement addressing mode and
1116 requires secondary reloads, disallow its class from
1117 being used in such addresses. */
1119 if ((secondary_reload_class (1, base_class, m, r)
1120 || secondary_reload_class (1, base_class, m, r))
1121 && ! auto_inc_dec_reg_p (r, m))
1122 forbidden_inc_dec_class[i] = 1;
1126 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1129 /* This is a pass of the compiler that scans all instructions
1130 and calculates the preferred class for each pseudo-register.
1131 This information can be accessed later by calling `reg_preferred_class'.
1132 This pass comes just before local register allocation. */
1135 regclass (rtx f, int nregs)
1143 costs = XNEWVEC (struct costs, nregs);
1145 #ifdef FORBIDDEN_INC_DEC_CLASSES
1147 in_inc_dec = XNEWVEC (char, nregs);
1149 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1151 /* Normally we scan the insns once and determine the best class to use for
1152 each register. However, if -fexpensive_optimizations are on, we do so
1153 twice, the second time using the tentative best classes to guide the
1156 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1161 fprintf (dump_file, "\n\nPass %i\n\n",pass);
1162 /* Zero out our accumulation of the cost of each class for each reg. */
1164 memset (costs, 0, nregs * sizeof (struct costs));
1166 #ifdef FORBIDDEN_INC_DEC_CLASSES
1167 memset (in_inc_dec, 0, nregs);
1170 /* Scan the instructions and record each time it would
1171 save code to put a certain register in a certain class. */
1175 frequency = REG_FREQ_MAX;
1176 for (insn = f; insn; insn = NEXT_INSN (insn))
1177 insn = scan_one_insn (insn, pass);
1182 /* Show that an insn inside a loop is likely to be executed three
1183 times more than insns outside a loop. This is much more
1184 aggressive than the assumptions made elsewhere and is being
1185 tried as an experiment. */
1186 frequency = REG_FREQ_FROM_BB (bb);
1187 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
1189 insn = scan_one_insn (insn, pass);
1190 if (insn == BB_END (bb))
1195 /* Now for each register look at how desirable each class is
1196 and find which class is preferred. Store that in
1197 `prefclass'. Record in `altclass' the largest register
1198 class any of whose registers is better than memory. */
1201 reg_pref = reg_pref_buffer;
1205 dump_regclass (dump_file);
1206 fprintf (dump_file,"\n");
1208 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1210 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1211 enum reg_class best = ALL_REGS, alt = NO_REGS;
1212 /* This is an enum reg_class, but we call it an int
1213 to save lots of casts. */
1215 struct costs *p = &costs[i];
1217 /* In non-optimizing compilation REG_N_REFS is not initialized
1219 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i))
1222 for (class = (int) ALL_REGS - 1; class > 0; class--)
1224 /* Ignore classes that are too small for this operand or
1225 invalid for an operand that was auto-incremented. */
1226 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1227 #ifdef FORBIDDEN_INC_DEC_CLASSES
1228 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1230 #ifdef CANNOT_CHANGE_MODE_CLASS
1231 || invalid_mode_change_p (i, (enum reg_class) class,
1232 PSEUDO_REGNO_MODE (i))
1236 else if (p->cost[class] < best_cost)
1238 best_cost = p->cost[class];
1239 best = (enum reg_class) class;
1241 else if (p->cost[class] == best_cost)
1242 best = reg_class_subunion[(int) best][class];
1245 /* If no register class is better than memory, use memory. */
1246 if (p->mem_cost < best_cost)
1249 /* Record the alternate register class; i.e., a class for which
1250 every register in it is better than using memory. If adding a
1251 class would make a smaller class (i.e., no union of just those
1252 classes exists), skip that class. The major unions of classes
1253 should be provided as a register class. Don't do this if we
1254 will be doing it again later. */
1256 if ((pass == 1 || dump_file) || ! flag_expensive_optimizations)
1257 for (class = 0; class < N_REG_CLASSES; class++)
1258 if (p->cost[class] < p->mem_cost
1259 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1260 > reg_class_size[(int) alt])
1261 #ifdef FORBIDDEN_INC_DEC_CLASSES
1262 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1264 #ifdef CANNOT_CHANGE_MODE_CLASS
1265 && ! invalid_mode_change_p (i, (enum reg_class) class,
1266 PSEUDO_REGNO_MODE (i))
1269 alt = reg_class_subunion[(int) alt][class];
1271 /* If we don't add any classes, nothing to try. */
1276 && (reg_pref[i].prefclass != (int) best
1277 || reg_pref[i].altclass != (int) alt))
1279 fprintf (dump_file, " Register %i", i);
1280 if (alt == ALL_REGS || best == ALL_REGS)
1281 fprintf (dump_file, " pref %s\n", reg_class_names[(int) best]);
1282 else if (alt == NO_REGS)
1283 fprintf (dump_file, " pref %s or none\n", reg_class_names[(int) best]);
1285 fprintf (dump_file, " pref %s, else %s\n",
1286 reg_class_names[(int) best],
1287 reg_class_names[(int) alt]);
1290 /* We cast to (int) because (char) hits bugs in some compilers. */
1291 reg_pref[i].prefclass = (int) best;
1292 reg_pref[i].altclass = (int) alt;
1296 #ifdef FORBIDDEN_INC_DEC_CLASSES
1302 /* Record the cost of using memory or registers of various classes for
1303 the operands in INSN.
1305 N_ALTS is the number of alternatives.
1307 N_OPS is the number of operands.
1309 OPS is an array of the operands.
1311 MODES are the modes of the operands, in case any are VOIDmode.
1313 CONSTRAINTS are the constraints to use for the operands. This array
1314 is modified by this procedure.
1316 This procedure works alternative by alternative. For each alternative
1317 we assume that we will be able to allocate all pseudos to their ideal
1318 register class and calculate the cost of using that alternative. Then
1319 we compute for each operand that is a pseudo-register, the cost of
1320 having the pseudo allocated to each register class and using it in that
1321 alternative. To this cost is added the cost of the alternative.
1323 The cost of each class for this insn is its lowest cost among all the
1327 record_reg_classes (int n_alts, int n_ops, rtx *ops,
1328 enum machine_mode *modes, const char **constraints,
1329 rtx insn, struct costs *op_costs,
1330 struct reg_pref *reg_pref)
1336 /* Process each alternative, each time minimizing an operand's cost with
1337 the cost for each operand in that alternative. */
1339 for (alt = 0; alt < n_alts; alt++)
1341 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1344 enum reg_class classes[MAX_RECOG_OPERANDS];
1345 int allows_mem[MAX_RECOG_OPERANDS];
1348 for (i = 0; i < n_ops; i++)
1350 const char *p = constraints[i];
1352 enum machine_mode mode = modes[i];
1353 int allows_addr = 0;
1357 /* Initially show we know nothing about the register class. */
1358 classes[i] = NO_REGS;
1361 /* If this operand has no constraints at all, we can conclude
1362 nothing about it since anything is valid. */
1366 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1367 memset (&this_op_costs[i], 0, sizeof this_op_costs[i]);
1372 /* If this alternative is only relevant when this operand
1373 matches a previous operand, we do different things depending
1374 on whether this operand is a pseudo-reg or not. We must process
1375 any modifiers for the operand before we can make this test. */
1377 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1380 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1382 /* Copy class and whether memory is allowed from the matching
1383 alternative. Then perform any needed cost computations
1384 and/or adjustments. */
1386 classes[i] = classes[j];
1387 allows_mem[i] = allows_mem[j];
1389 if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
1391 /* If this matches the other operand, we have no added
1393 if (rtx_equal_p (ops[j], op))
1396 /* If we can put the other operand into a register, add to
1397 the cost of this alternative the cost to copy this
1398 operand to the register used for the other operand. */
1400 else if (classes[j] != NO_REGS)
1402 alt_cost += copy_cost (op, mode, classes[j], 1, NULL);
1406 else if (!REG_P (ops[j])
1407 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1409 /* This op is a pseudo but the one it matches is not. */
1411 /* If we can't put the other operand into a register, this
1412 alternative can't be used. */
1414 if (classes[j] == NO_REGS)
1417 /* Otherwise, add to the cost of this alternative the cost
1418 to copy the other operand to the register used for this
1422 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
1426 /* The costs of this operand are not the same as the other
1427 operand since move costs are not symmetric. Moreover,
1428 if we cannot tie them, this alternative needs to do a
1429 copy, which is one instruction. */
1431 struct costs *pp = &this_op_costs[i];
1433 for (class = 0; class < N_REG_CLASSES; class++)
1435 = ((recog_data.operand_type[i] != OP_OUT
1436 ? may_move_in_cost[mode][class][(int) classes[i]]
1438 + (recog_data.operand_type[i] != OP_IN
1439 ? may_move_out_cost[mode][(int) classes[i]][class]
1442 /* If the alternative actually allows memory, make things
1443 a bit cheaper since we won't need an extra insn to
1447 = ((recog_data.operand_type[i] != OP_IN
1448 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1450 + (recog_data.operand_type[i] != OP_OUT
1451 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1452 : 0) - allows_mem[i]);
1454 /* If we have assigned a class to this register in our
1455 first pass, add a cost to this alternative corresponding
1456 to what we would add if this register were not in the
1457 appropriate class. */
1459 if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS)
1461 += (may_move_in_cost[mode]
1462 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1463 [(int) classes[i]]);
1465 if (REGNO (ops[i]) != REGNO (ops[j])
1466 && ! find_reg_note (insn, REG_DEAD, op))
1469 /* This is in place of ordinary cost computation
1470 for this operand, so skip to the end of the
1471 alternative (should be just one character). */
1472 while (*p && *p++ != ',')
1480 /* Scan all the constraint letters. See if the operand matches
1481 any of the constraints. Collect the valid register classes
1482 and see if this operand accepts memory. */
1491 /* Ignore the next letter for this pass. */
1497 case '!': case '#': case '&':
1498 case '0': case '1': case '2': case '3': case '4':
1499 case '5': case '6': case '7': case '8': case '9':
1504 win = address_operand (op, GET_MODE (op));
1505 /* We know this operand is an address, so we want it to be
1506 allocated to a register that can be the base of an
1507 address, i.e. BASE_REG_CLASS. */
1509 = reg_class_subunion[(int) classes[i]]
1510 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1513 case 'm': case 'o': case 'V':
1514 /* It doesn't seem worth distinguishing between offsettable
1515 and non-offsettable addresses here. */
1523 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1524 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1530 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1531 || GET_CODE (XEXP (op, 0)) == POST_INC))
1537 if (GET_CODE (op) == CONST_DOUBLE
1538 || (GET_CODE (op) == CONST_VECTOR
1539 && (GET_MODE_CLASS (GET_MODE (op))
1540 == MODE_VECTOR_FLOAT)))
1546 if (GET_CODE (op) == CONST_DOUBLE
1547 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
1552 if (GET_CODE (op) == CONST_INT
1553 || (GET_CODE (op) == CONST_DOUBLE
1554 && GET_MODE (op) == VOIDmode))
1558 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
1563 if (GET_CODE (op) == CONST_INT
1564 || (GET_CODE (op) == CONST_DOUBLE
1565 && GET_MODE (op) == VOIDmode))
1577 if (GET_CODE (op) == CONST_INT
1578 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
1589 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
1594 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1598 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS)
1600 = reg_class_subunion[(int) classes[i]]
1601 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1602 #ifdef EXTRA_CONSTRAINT_STR
1603 else if (EXTRA_CONSTRAINT_STR (op, c, p))
1606 if (EXTRA_MEMORY_CONSTRAINT (c, p))
1608 /* Every MEM can be reloaded to fit. */
1613 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1615 /* Every address can be reloaded to fit. */
1617 if (address_operand (op, GET_MODE (op)))
1619 /* We know this operand is an address, so we want it to
1620 be allocated to a register that can be the base of an
1621 address, i.e. BASE_REG_CLASS. */
1623 = reg_class_subunion[(int) classes[i]]
1624 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1629 p += CONSTRAINT_LEN (c, p);
1636 /* How we account for this operand now depends on whether it is a
1637 pseudo register or not. If it is, we first check if any
1638 register classes are valid. If not, we ignore this alternative,
1639 since we want to assume that all pseudos get allocated for
1640 register preferencing. If some register class is valid, compute
1641 the costs of moving the pseudo into that class. */
1643 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1645 if (classes[i] == NO_REGS)
1647 /* We must always fail if the operand is a REG, but
1648 we did not find a suitable class.
1650 Otherwise we may perform an uninitialized read
1651 from this_op_costs after the `continue' statement
1657 struct costs *pp = &this_op_costs[i];
1659 for (class = 0; class < N_REG_CLASSES; class++)
1661 = ((recog_data.operand_type[i] != OP_OUT
1662 ? may_move_in_cost[mode][class][(int) classes[i]]
1664 + (recog_data.operand_type[i] != OP_IN
1665 ? may_move_out_cost[mode][(int) classes[i]][class]
1668 /* If the alternative actually allows memory, make things
1669 a bit cheaper since we won't need an extra insn to
1673 = ((recog_data.operand_type[i] != OP_IN
1674 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1676 + (recog_data.operand_type[i] != OP_OUT
1677 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1678 : 0) - allows_mem[i]);
1680 /* If we have assigned a class to this register in our
1681 first pass, add a cost to this alternative corresponding
1682 to what we would add if this register were not in the
1683 appropriate class. */
1685 if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS)
1687 += (may_move_in_cost[mode]
1688 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1689 [(int) classes[i]]);
1693 /* Otherwise, if this alternative wins, either because we
1694 have already determined that or if we have a hard register of
1695 the proper class, there is no cost for this alternative. */
1699 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1702 /* If registers are valid, the cost of this alternative includes
1703 copying the object to and/or from a register. */
1705 else if (classes[i] != NO_REGS)
1707 if (recog_data.operand_type[i] != OP_OUT)
1708 alt_cost += copy_cost (op, mode, classes[i], 1, NULL);
1710 if (recog_data.operand_type[i] != OP_IN)
1711 alt_cost += copy_cost (op, mode, classes[i], 0, NULL);
1714 /* The only other way this alternative can be used is if this is a
1715 constant that could be placed into memory. */
1717 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1718 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1726 /* Finally, update the costs with the information we've calculated
1727 about this alternative. */
1729 for (i = 0; i < n_ops; i++)
1731 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1733 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1734 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1736 pp->mem_cost = MIN (pp->mem_cost,
1737 (qq->mem_cost + alt_cost) * scale);
1739 for (class = 0; class < N_REG_CLASSES; class++)
1740 pp->cost[class] = MIN (pp->cost[class],
1741 (qq->cost[class] + alt_cost) * scale);
1745 /* If this insn is a single set copying operand 1 to operand 0
1746 and one operand is a pseudo with the other a hard reg or a pseudo
1747 that prefers a register that is in its own register class then
1748 we may want to adjust the cost of that register class to -1.
1750 Avoid the adjustment if the source does not die to avoid stressing of
1751 register allocator by preferrencing two colliding registers into single
1754 Also avoid the adjustment if a copy between registers of the class
1755 is expensive (ten times the cost of a default copy is considered
1756 arbitrarily expensive). This avoids losing when the preferred class
1757 is very expensive as the source of a copy instruction. */
1759 if ((set = single_set (insn)) != 0
1760 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1761 && REG_P (ops[0]) && REG_P (ops[1])
1762 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1763 for (i = 0; i <= 1; i++)
1764 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1766 unsigned int regno = REGNO (ops[!i]);
1767 enum machine_mode mode = GET_MODE (ops[!i]);
1770 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0
1771 && reg_pref[regno].prefclass != NO_REGS)
1773 enum reg_class pref = reg_pref[regno].prefclass;
1775 if ((reg_class_size[(unsigned char) pref]
1776 == (unsigned) CLASS_MAX_NREGS (pref, mode))
1777 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1778 op_costs[i].cost[(unsigned char) pref] = -1;
1780 else if (regno < FIRST_PSEUDO_REGISTER)
1781 for (class = 0; class < N_REG_CLASSES; class++)
1782 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1783 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode))
1785 if (reg_class_size[class] == 1)
1786 op_costs[i].cost[class] = -1;
1787 else if (in_hard_reg_set_p (reg_class_contents[class],
1789 op_costs[i].cost[class] = -1;
1794 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1795 TO_P is zero) a register of class CLASS in mode MODE.
1797 X must not be a pseudo. */
1800 copy_cost (rtx x, enum machine_mode mode, enum reg_class class, int to_p,
1801 secondary_reload_info *prev_sri)
1803 enum reg_class secondary_class = NO_REGS;
1804 secondary_reload_info sri;
1806 /* If X is a SCRATCH, there is actually nothing to move since we are
1807 assuming optimal allocation. */
1809 if (GET_CODE (x) == SCRATCH)
1812 /* Get the class we will actually use for a reload. */
1813 class = PREFERRED_RELOAD_CLASS (x, class);
1815 /* If we need a secondary reload for an intermediate, the
1816 cost is that to load the input into the intermediate register, then
1819 sri.prev_sri = prev_sri;
1821 secondary_class = targetm.secondary_reload (to_p, x, class, mode, &sri);
1823 if (secondary_class != NO_REGS)
1824 return (move_cost[mode][(int) secondary_class][(int) class]
1826 + copy_cost (x, mode, secondary_class, to_p, &sri));
1828 /* For memory, use the memory move cost, for (hard) registers, use the
1829 cost to move between the register classes, and use 2 for everything
1830 else (constants). */
1832 if (MEM_P (x) || class == NO_REGS)
1833 return sri.extra_cost + MEMORY_MOVE_COST (mode, class, to_p);
1836 return (sri.extra_cost
1837 + move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]);
1840 /* If this is a constant, we may eventually want to call rtx_cost here. */
1841 return sri.extra_cost + COSTS_N_INSNS (1);
1844 /* Record the pseudo registers we must reload into hard registers
1845 in a subexpression of a memory address, X.
1847 If CONTEXT is 0, we are looking at the base part of an address, otherwise we
1848 are looking at the index part.
1850 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
1851 give the context that the rtx appears in. These three arguments are
1852 passed down to base_reg_class.
1854 SCALE is twice the amount to multiply the cost by (it is twice so we
1855 can represent half-cost adjustments). */
1858 record_address_regs (enum machine_mode mode, rtx x, int context,
1859 enum rtx_code outer_code, enum rtx_code index_code,
1862 enum rtx_code code = GET_CODE (x);
1863 enum reg_class class;
1866 class = INDEX_REG_CLASS;
1868 class = base_reg_class (mode, outer_code, index_code);
1881 /* When we have an address that is a sum,
1882 we must determine whether registers are "base" or "index" regs.
1883 If there is a sum of two registers, we must choose one to be
1884 the "base". Luckily, we can use the REG_POINTER to make a good
1885 choice most of the time. We only need to do this on machines
1886 that can have two registers in an address and where the base
1887 and index register classes are different.
1889 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1890 that seems bogus since it should only be set when we are sure
1891 the register is being used as a pointer. */
1894 rtx arg0 = XEXP (x, 0);
1895 rtx arg1 = XEXP (x, 1);
1896 enum rtx_code code0 = GET_CODE (arg0);
1897 enum rtx_code code1 = GET_CODE (arg1);
1899 /* Look inside subregs. */
1900 if (code0 == SUBREG)
1901 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1902 if (code1 == SUBREG)
1903 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1905 /* If this machine only allows one register per address, it must
1906 be in the first operand. */
1908 if (MAX_REGS_PER_ADDRESS == 1)
1909 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
1911 /* If index and base registers are the same on this machine, just
1912 record registers in any non-constant operands. We assume here,
1913 as well as in the tests below, that all addresses are in
1916 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH))
1918 record_address_regs (mode, arg0, context, PLUS, code1, scale);
1919 if (! CONSTANT_P (arg1))
1920 record_address_regs (mode, arg1, context, PLUS, code0, scale);
1923 /* If the second operand is a constant integer, it doesn't change
1924 what class the first operand must be. */
1926 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1927 record_address_regs (mode, arg0, context, PLUS, code1, scale);
1929 /* If the second operand is a symbolic constant, the first operand
1930 must be an index register. */
1932 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1933 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
1935 /* If both operands are registers but one is already a hard register
1936 of index or reg-base class, give the other the class that the
1937 hard register is not. */
1939 else if (code0 == REG && code1 == REG
1940 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1941 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
1942 || ok_for_index_p_nonstrict (arg0)))
1943 record_address_regs (mode, arg1,
1944 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
1947 else if (code0 == REG && code1 == REG
1948 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1949 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
1950 || ok_for_index_p_nonstrict (arg1)))
1951 record_address_regs (mode, arg0,
1952 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
1956 /* If one operand is known to be a pointer, it must be the base
1957 with the other operand the index. Likewise if the other operand
1960 else if ((code0 == REG && REG_POINTER (arg0))
1963 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
1964 record_address_regs (mode, arg1, 1, PLUS, code0, scale);
1966 else if ((code1 == REG && REG_POINTER (arg1))
1969 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
1970 record_address_regs (mode, arg1, 0, PLUS, code0, scale);
1973 /* Otherwise, count equal chances that each might be a base
1974 or index register. This case should be rare. */
1978 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2);
1979 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2);
1980 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2);
1981 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2);
1986 /* Double the importance of a pseudo register that is incremented
1987 or decremented, since it would take two extra insns
1988 if it ends up in the wrong place. */
1991 record_address_regs (mode, XEXP (x, 0), 0, code,
1992 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale);
1993 if (REG_P (XEXP (XEXP (x, 1), 1)))
1994 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG,
2002 /* Double the importance of a pseudo register that is incremented
2003 or decremented, since it would take two extra insns
2004 if it ends up in the wrong place. If the operand is a pseudo,
2005 show it is being used in an INC_DEC context. */
2007 #ifdef FORBIDDEN_INC_DEC_CLASSES
2008 if (REG_P (XEXP (x, 0))
2009 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2010 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2013 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale);
2018 struct costs *pp = &costs[REGNO (x)];
2021 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2023 for (i = 0; i < N_REG_CLASSES; i++)
2024 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2030 const char *fmt = GET_RTX_FORMAT (code);
2032 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2034 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH,
2040 #ifdef FORBIDDEN_INC_DEC_CLASSES
2042 /* Return 1 if REG is valid as an auto-increment memory reference
2043 to an object of MODE. */
2046 auto_inc_dec_reg_p (rtx reg, enum machine_mode mode)
2048 if (HAVE_POST_INCREMENT
2049 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2052 if (HAVE_POST_DECREMENT
2053 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2056 if (HAVE_PRE_INCREMENT
2057 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2060 if (HAVE_PRE_DECREMENT
2061 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2068 static short *renumber;
2069 static size_t regno_allocated;
2070 static unsigned int reg_n_max;
2072 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2073 reg_scan and flow_analysis that are indexed by the register number. If
2074 NEW_P is nonzero, initialize all of the registers, otherwise only
2075 initialize the new registers allocated. The same table is kept from
2076 function to function, only reallocating it when we need more room. If
2077 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2080 allocate_reg_info (size_t num_regs, int new_p, int renumber_p)
2083 size_t size_renumber;
2084 size_t min = (new_p) ? 0 : reg_n_max;
2085 struct reg_info_data *reg_data;
2087 if (num_regs > regno_allocated)
2089 size_t old_allocated = regno_allocated;
2091 regno_allocated = num_regs + (num_regs / 20); /* Add some slop space. */
2092 size_renumber = regno_allocated * sizeof (short);
2096 reg_n_info = VEC_alloc (reg_info_p, heap, regno_allocated);
2097 VEC_safe_grow_cleared (reg_info_p, heap, reg_n_info,
2099 renumber = xmalloc (size_renumber);
2100 reg_pref_buffer = XNEWVEC (struct reg_pref, regno_allocated);
2104 size_t old_length = VEC_length (reg_info_p, reg_n_info);
2105 if (old_length < regno_allocated)
2107 VEC_safe_grow_cleared (reg_info_p, heap, reg_n_info,
2110 else if (regno_allocated < old_length)
2112 VEC_truncate (reg_info_p, reg_n_info, regno_allocated);
2115 if (new_p) /* If we're zapping everything, no need to realloc. */
2117 free ((char *) renumber);
2118 free ((char *) reg_pref);
2119 renumber = xmalloc (size_renumber);
2120 reg_pref_buffer = XNEWVEC (struct reg_pref, regno_allocated);
2125 renumber = xrealloc (renumber, size_renumber);
2126 reg_pref_buffer = (struct reg_pref *) xrealloc (reg_pref_buffer,
2128 * sizeof (struct reg_pref));
2132 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2133 + sizeof (struct reg_info_data) - sizeof (reg_info);
2134 reg_data = xcalloc (size_info, 1);
2135 reg_data->min_index = old_allocated;
2136 reg_data->max_index = regno_allocated - 1;
2137 reg_data->next = reg_info_head;
2138 reg_info_head = reg_data;
2141 reg_n_max = num_regs;
2144 /* Loop through each of the segments allocated for the actual
2145 reg_info pages, and set up the pointers, zero the pages, etc. */
2146 for (reg_data = reg_info_head;
2147 reg_data && reg_data->max_index >= min;
2148 reg_data = reg_data->next)
2150 size_t min_index = reg_data->min_index;
2151 size_t max_index = reg_data->max_index;
2152 size_t max = MIN (max_index, num_regs);
2153 size_t local_min = min - min_index;
2156 if (reg_data->min_index > num_regs)
2159 if (min < min_index)
2161 if (!reg_data->used_p) /* page just allocated with calloc */
2162 reg_data->used_p = 1; /* no need to zero */
2164 memset (®_data->data[local_min], 0,
2165 sizeof (reg_info) * (max - min_index - local_min + 1));
2167 for (i = min_index+local_min; i <= max; i++)
2169 VEC_replace (reg_info_p, reg_n_info, i,
2170 ®_data->data[i-min_index]);
2171 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2173 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2174 reg_pref_buffer[i].altclass = (char) NO_REGS;
2179 /* If {pref,alt}class have already been allocated, update the pointers to
2180 the newly realloced ones. */
2182 reg_pref = reg_pref_buffer;
2185 reg_renumber = renumber;
2188 /* Free up the space allocated by allocate_reg_info. */
2190 free_reg_info (void)
2194 struct reg_info_data *reg_data;
2195 struct reg_info_data *reg_next;
2197 VEC_free (reg_info_p, heap, reg_n_info);
2198 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2200 reg_next = reg_data->next;
2201 free ((char *) reg_data);
2204 free (reg_pref_buffer);
2205 reg_pref_buffer = (struct reg_pref *) 0;
2206 reg_info_head = (struct reg_info_data *) 0;
2207 renumber = (short *) 0;
2209 regno_allocated = 0;
2213 /* Clear the information stored for REGNO. */
2215 clear_reg_info_regno (unsigned int regno)
2217 if (regno < regno_allocated)
2218 memset (VEC_index (reg_info_p, reg_n_info, regno), 0, sizeof (reg_info));
2221 /* This is the `regscan' pass of the compiler, run just before cse
2222 and again just before loop.
2224 It finds the first and last use of each pseudo-register
2225 and records them in the vectors regno_first_uid, regno_last_uid
2226 and counts the number of sets in the vector reg_n_sets.
2228 REPEAT is nonzero the second time this is called. */
2230 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2231 Always at least 3, since the combiner could put that many together
2232 and we want this to remain correct for all the remaining passes.
2233 This corresponds to the maximum number of times note_stores will call
2234 a function for any insn. */
2238 /* Used as a temporary to record the largest number of registers in
2239 PARALLEL in a SET_DEST. This is added to max_parallel. */
2241 static int max_set_parallel;
2244 reg_scan (rtx f, unsigned int nregs)
2248 timevar_push (TV_REG_SCAN);
2250 allocate_reg_info (nregs, TRUE, FALSE);
2252 max_set_parallel = 0;
2254 for (insn = f; insn; insn = NEXT_INSN (insn))
2257 rtx pat = PATTERN (insn);
2258 if (GET_CODE (pat) == PARALLEL
2259 && XVECLEN (pat, 0) > max_parallel)
2260 max_parallel = XVECLEN (pat, 0);
2261 reg_scan_mark_refs (pat, insn, 0, 0);
2263 if (REG_NOTES (insn))
2264 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2267 max_parallel += max_set_parallel;
2269 timevar_pop (TV_REG_SCAN);
2272 /* Update 'regscan' information by looking at the insns
2273 from FIRST to LAST. Some new REGs have been created,
2274 and any REG with number greater than OLD_MAX_REGNO is
2275 such a REG. We only update information for those. */
2278 reg_scan_update (rtx first, rtx last, unsigned int old_max_regno)
2282 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2284 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2287 rtx pat = PATTERN (insn);
2288 if (GET_CODE (pat) == PARALLEL
2289 && XVECLEN (pat, 0) > max_parallel)
2290 max_parallel = XVECLEN (pat, 0);
2291 reg_scan_mark_refs (pat, insn, 0, old_max_regno);
2293 if (REG_NOTES (insn))
2294 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2298 /* X is the expression to scan. INSN is the insn it appears in.
2299 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2300 We should only record information for REGs with numbers
2301 greater than or equal to MIN_REGNO. */
2304 reg_scan_mark_refs (rtx x, rtx insn, int note_flag, unsigned int min_regno)
2312 code = GET_CODE (x);
2329 unsigned int regno = REGNO (x);
2331 if (regno >= min_regno)
2334 REGNO_LAST_UID (regno) = INSN_UID (insn);
2335 if (REGNO_FIRST_UID (regno) == 0)
2336 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2337 /* If we are called by reg_scan_update() (indicated by min_regno
2338 being set), we also need to update the reference count. */
2340 REG_N_REFS (regno)++;
2347 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2349 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2354 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2359 rtx reg = XEXP (x, 0);
2361 && REGNO (reg) >= min_regno)
2363 REG_N_SETS (REGNO (reg))++;
2364 REG_N_REFS (REGNO (reg))++;
2366 else if (MEM_P (reg))
2367 reg_scan_mark_refs (XEXP (reg, 0), insn, note_flag, min_regno);
2372 /* Count a set of the destination if it is a register. */
2373 for (dest = SET_DEST (x);
2374 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2375 || GET_CODE (dest) == ZERO_EXTEND;
2376 dest = XEXP (dest, 0))
2379 /* For a PARALLEL, record the number of things (less the usual one for a
2380 SET) that are set. */
2381 if (GET_CODE (dest) == PARALLEL)
2382 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2385 && REGNO (dest) >= min_regno)
2387 REG_N_SETS (REGNO (dest))++;
2388 REG_N_REFS (REGNO (dest))++;
2391 /* If this is setting a pseudo from another pseudo or the sum of a
2392 pseudo and a constant integer and the other pseudo is known to be
2393 a pointer, set the destination to be a pointer as well.
2395 Likewise if it is setting the destination from an address or from a
2396 value equivalent to an address or to the sum of an address and
2399 But don't do any of this if the pseudo corresponds to a user
2400 variable since it should have already been set as a pointer based
2403 if (REG_P (SET_DEST (x))
2404 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2405 && REGNO (SET_DEST (x)) >= min_regno
2406 /* If the destination pseudo is set more than once, then other
2407 sets might not be to a pointer value (consider access to a
2408 union in two threads of control in the presence of global
2409 optimizations). So only set REG_POINTER on the destination
2410 pseudo if this is the only set of that pseudo. */
2411 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2412 && ! REG_USERVAR_P (SET_DEST (x))
2413 && ! REG_POINTER (SET_DEST (x))
2414 && ((REG_P (SET_SRC (x))
2415 && REG_POINTER (SET_SRC (x)))
2416 || ((GET_CODE (SET_SRC (x)) == PLUS
2417 || GET_CODE (SET_SRC (x)) == LO_SUM)
2418 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2419 && REG_P (XEXP (SET_SRC (x), 0))
2420 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2421 || GET_CODE (SET_SRC (x)) == CONST
2422 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2423 || GET_CODE (SET_SRC (x)) == LABEL_REF
2424 || (GET_CODE (SET_SRC (x)) == HIGH
2425 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2426 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2427 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2428 || ((GET_CODE (SET_SRC (x)) == PLUS
2429 || GET_CODE (SET_SRC (x)) == LO_SUM)
2430 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2431 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2432 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2433 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2434 && (GET_CODE (XEXP (note, 0)) == CONST
2435 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2436 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2437 REG_POINTER (SET_DEST (x)) = 1;
2439 /* If this is setting a register from a register or from a simple
2440 conversion of a register, propagate REG_EXPR. */
2443 rtx src = SET_SRC (x);
2445 while (GET_CODE (src) == SIGN_EXTEND
2446 || GET_CODE (src) == ZERO_EXTEND
2447 || GET_CODE (src) == TRUNCATE
2448 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)))
2449 src = XEXP (src, 0);
2451 if (!REG_ATTRS (dest) && REG_P (src))
2452 REG_ATTRS (dest) = REG_ATTRS (src);
2453 if (!REG_ATTRS (dest) && MEM_P (src))
2454 set_reg_attrs_from_mem (dest, src);
2457 /* ... fall through ... */
2461 const char *fmt = GET_RTX_FORMAT (code);
2463 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2466 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2467 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2470 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2471 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2478 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2482 reg_class_subset_p (enum reg_class c1, enum reg_class c2)
2486 || hard_reg_set_subset_p (reg_class_contents[(int) c1],
2487 reg_class_contents[(int) c2]));
2490 /* Return nonzero if there is a register that is in both C1 and C2. */
2493 reg_classes_intersect_p (enum reg_class c1, enum reg_class c2)
2498 || hard_reg_set_intersect_p (reg_class_contents[(int) c1],
2499 reg_class_contents[(int) c2]));
2502 #ifdef CANNOT_CHANGE_MODE_CLASS
2504 struct subregs_of_mode_node
2507 unsigned char modes[MAX_MACHINE_MODE];
2510 static htab_t subregs_of_mode;
2513 som_hash (const void *x)
2515 const struct subregs_of_mode_node *a = x;
2520 som_eq (const void *x, const void *y)
2522 const struct subregs_of_mode_node *a = x;
2523 const struct subregs_of_mode_node *b = y;
2524 return a->block == b->block;
2528 init_subregs_of_mode (void)
2530 if (subregs_of_mode)
2531 htab_empty (subregs_of_mode);
2533 subregs_of_mode = htab_create (100, som_hash, som_eq, free);
2537 record_subregs_of_mode (rtx subreg)
2539 struct subregs_of_mode_node dummy, *node;
2540 enum machine_mode mode;
2544 if (!REG_P (SUBREG_REG (subreg)))
2547 regno = REGNO (SUBREG_REG (subreg));
2548 mode = GET_MODE (subreg);
2550 if (regno < FIRST_PSEUDO_REGISTER)
2553 dummy.block = regno & -8;
2554 slot = htab_find_slot_with_hash (subregs_of_mode, &dummy,
2555 dummy.block, INSERT);
2559 node = XCNEW (struct subregs_of_mode_node);
2560 node->block = regno & -8;
2564 node->modes[mode] |= 1 << (regno & 7);
2567 /* Set bits in *USED which correspond to registers which can't change
2568 their mode from FROM to any mode in which REGNO was encountered. */
2571 cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from,
2574 struct subregs_of_mode_node dummy, *node;
2575 enum machine_mode to;
2579 dummy.block = regno & -8;
2580 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block);
2584 mask = 1 << (regno & 7);
2585 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
2586 if (node->modes[to] & mask)
2587 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2588 if (!TEST_HARD_REG_BIT (*used, i)
2589 && REG_CANNOT_CHANGE_MODE_P (i, from, to))
2590 SET_HARD_REG_BIT (*used, i);
2593 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2597 invalid_mode_change_p (unsigned int regno, enum reg_class class,
2598 enum machine_mode from)
2600 struct subregs_of_mode_node dummy, *node;
2601 enum machine_mode to;
2604 dummy.block = regno & -8;
2605 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block);
2609 mask = 1 << (regno & 7);
2610 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
2611 if (node->modes[to] & mask)
2612 if (CANNOT_CHANGE_MODE_CLASS (from, to, class))
2617 #endif /* CANNOT_CHANGE_MODE_CLASS */
2619 #include "gt-regclass.h"