1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
43 #ifndef REGISTER_MOVE_COST
44 #define REGISTER_MOVE_COST(x, y) 2
47 static void init_reg_sets_1 PROTO((void));
48 static void init_reg_modes PROTO((void));
50 /* If we have auto-increment or auto-decrement and we can have secondary
51 reloads, we are not allowed to use classes requiring secondary
52 reloads for pseudos auto-incremented since reload can't handle it. */
55 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
56 #define FORBIDDEN_INC_DEC_CLASSES
60 /* Register tables used by many passes. */
62 /* Indexed by hard register number, contains 1 for registers
63 that are fixed use (stack pointer, pc, frame pointer, etc.).
64 These are the registers that cannot be used to allocate
65 a pseudo reg for general use. */
67 char fixed_regs[FIRST_PSEUDO_REGISTER];
69 /* Same info as a HARD_REG_SET. */
71 HARD_REG_SET fixed_reg_set;
73 /* Data for initializing the above. */
75 static char initial_fixed_regs[] = FIXED_REGISTERS;
77 /* Indexed by hard register number, contains 1 for registers
78 that are fixed use or are clobbered by function calls.
79 These are the registers that cannot be used to allocate
80 a pseudo reg whose life crosses calls unless we are able
81 to save/restore them across the calls. */
83 char call_used_regs[FIRST_PSEUDO_REGISTER];
85 /* Same info as a HARD_REG_SET. */
87 HARD_REG_SET call_used_reg_set;
89 /* HARD_REG_SET of registers we want to avoid caller saving. */
90 HARD_REG_SET losing_caller_save_reg_set;
92 /* Data for initializing the above. */
94 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
96 /* Indexed by hard register number, contains 1 for registers that are
97 fixed use or call used registers that cannot hold quantities across
98 calls even if we are willing to save and restore them. call fixed
99 registers are a subset of call used registers. */
101 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
103 /* The same info as a HARD_REG_SET. */
105 HARD_REG_SET call_fixed_reg_set;
107 /* Number of non-fixed registers. */
109 int n_non_fixed_regs;
111 /* Indexed by hard register number, contains 1 for registers
112 that are being used for global register decls.
113 These must be exempt from ordinary flow analysis
114 and are also considered fixed. */
116 char global_regs[FIRST_PSEUDO_REGISTER];
118 /* Table of register numbers in the order in which to try to use them. */
119 #ifdef REG_ALLOC_ORDER
120 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
125 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
127 /* The same information, but as an array of unsigned ints. We copy from
128 these unsigned ints to the table above. We do this so the tm.h files
129 do not have to be aware of the wordsize for machines with <= 64 regs. */
132 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
134 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
135 = REG_CLASS_CONTENTS;
137 /* For each reg class, number of regs it contains. */
139 int reg_class_size[N_REG_CLASSES];
141 /* For each reg class, table listing all the containing classes. */
143 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
145 /* For each reg class, table listing all the classes contained in it. */
147 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each pair of reg classes,
150 a largest reg class contained in their union. */
152 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
154 /* For each pair of reg classes,
155 the smallest reg class containing their union. */
157 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
159 /* Array containing all of the register names */
161 const char *reg_names[] = REGISTER_NAMES;
163 /* For each hard register, the widest mode object that it can contain.
164 This will be a MODE_INT mode if the register can hold integers. Otherwise
165 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
168 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
170 /* Maximum cost of moving from a register in one class to a register in
171 another class. Based on REGISTER_MOVE_COST. */
173 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
175 /* Similar, but here we don't have to move if the first index is a subset
176 of the second so in that case the cost is zero. */
178 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
180 /* Similar, but here we don't have to move if the first index is a superset
181 of the second so in that case the cost is zero. */
183 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
185 #ifdef FORBIDDEN_INC_DEC_CLASSES
187 /* These are the classes that regs which are auto-incremented or decremented
190 static int forbidden_inc_dec_class[N_REG_CLASSES];
192 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
195 static char *in_inc_dec;
197 #endif /* FORBIDDEN_INC_DEC_CLASSES */
199 #ifdef HAVE_SECONDARY_RELOADS
201 /* Sample MEM values for use by memory_move_secondary_cost. */
203 static rtx top_of_stack[MAX_MACHINE_MODE];
205 #endif /* HAVE_SECONDARY_RELOADS */
207 /* Linked list of reg_info structures allocated for reg_n_info array.
208 Grouping all of the allocated structures together in one lump
209 means only one call to bzero to clear them, rather than n smaller
211 struct reg_info_data {
212 struct reg_info_data *next; /* next set of reg_info structures */
213 size_t min_index; /* minimum index # */
214 size_t max_index; /* maximum index # */
215 char used_p; /* non-zero if this has been used previously */
216 reg_info data[1]; /* beginning of the reg_info data */
219 static struct reg_info_data *reg_info_head;
221 /* No more global register variables may be declared; true once
222 regclass has been initialized. */
224 static int no_global_reg_vars = 0;
227 /* Function called only once to initialize the above data on reg usage.
228 Once this is done, various switches may override. */
235 /* First copy the register information from the initial int form into
238 for (i = 0; i < N_REG_CLASSES; i++)
240 CLEAR_HARD_REG_SET (reg_class_contents[i]);
242 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
243 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
244 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
245 SET_HARD_REG_BIT (reg_class_contents[i], j);
248 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
249 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
250 bzero (global_regs, sizeof global_regs);
252 /* Do any additional initialization regsets may need */
253 INIT_ONCE_REG_SET ();
256 /* After switches have been processed, which perhaps alter
257 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
262 register unsigned int i, j;
264 /* This macro allows the fixed or call-used registers
265 and the register classes to depend on target flags. */
267 #ifdef CONDITIONAL_REGISTER_USAGE
268 CONDITIONAL_REGISTER_USAGE;
271 /* Compute number of hard regs in each class. */
273 bzero ((char *) reg_class_size, sizeof reg_class_size);
274 for (i = 0; i < N_REG_CLASSES; i++)
275 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
276 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
279 /* Initialize the table of subunions.
280 reg_class_subunion[I][J] gets the largest-numbered reg-class
281 that is contained in the union of classes I and J. */
283 for (i = 0; i < N_REG_CLASSES; i++)
285 for (j = 0; j < N_REG_CLASSES; j++)
288 register /* Declare it register if it's a scalar. */
293 COPY_HARD_REG_SET (c, reg_class_contents[i]);
294 IOR_HARD_REG_SET (c, reg_class_contents[j]);
295 for (k = 0; k < N_REG_CLASSES; k++)
297 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
302 /* keep the largest subclass */ /* SPEE 900308 */
303 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
304 reg_class_contents[(int) reg_class_subunion[i][j]],
306 reg_class_subunion[i][j] = (enum reg_class) k;
313 /* Initialize the table of superunions.
314 reg_class_superunion[I][J] gets the smallest-numbered reg-class
315 containing the union of classes I and J. */
317 for (i = 0; i < N_REG_CLASSES; i++)
319 for (j = 0; j < N_REG_CLASSES; j++)
322 register /* Declare it register if it's a scalar. */
327 COPY_HARD_REG_SET (c, reg_class_contents[i]);
328 IOR_HARD_REG_SET (c, reg_class_contents[j]);
329 for (k = 0; k < N_REG_CLASSES; k++)
330 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
333 reg_class_superunion[i][j] = (enum reg_class) k;
337 /* Initialize the tables of subclasses and superclasses of each reg class.
338 First clear the whole table, then add the elements as they are found. */
340 for (i = 0; i < N_REG_CLASSES; i++)
342 for (j = 0; j < N_REG_CLASSES; j++)
344 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
345 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
349 for (i = 0; i < N_REG_CLASSES; i++)
351 if (i == (int) NO_REGS)
354 for (j = i + 1; j < N_REG_CLASSES; j++)
358 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
362 /* Reg class I is a subclass of J.
363 Add J to the table of superclasses of I. */
364 p = ®_class_superclasses[i][0];
365 while (*p != LIM_REG_CLASSES) p++;
366 *p = (enum reg_class) j;
367 /* Add I to the table of superclasses of J. */
368 p = ®_class_subclasses[j][0];
369 while (*p != LIM_REG_CLASSES) p++;
370 *p = (enum reg_class) i;
374 /* Initialize "constant" tables. */
376 CLEAR_HARD_REG_SET (fixed_reg_set);
377 CLEAR_HARD_REG_SET (call_used_reg_set);
378 CLEAR_HARD_REG_SET (call_fixed_reg_set);
380 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
382 n_non_fixed_regs = 0;
384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
387 SET_HARD_REG_BIT (fixed_reg_set, i);
391 if (call_used_regs[i])
392 SET_HARD_REG_BIT (call_used_reg_set, i);
393 if (call_fixed_regs[i])
394 SET_HARD_REG_BIT (call_fixed_reg_set, i);
395 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
396 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
399 /* Initialize the move cost table. Find every subset of each class
400 and take the maximum cost of moving any subset to any other. */
402 for (i = 0; i < N_REG_CLASSES; i++)
403 for (j = 0; j < N_REG_CLASSES; j++)
405 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
406 enum reg_class *p1, *p2;
408 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
410 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
412 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
415 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
417 for (p2 = ®_class_subclasses[j][0];
418 *p2 != LIM_REG_CLASSES; p2++)
420 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
423 move_cost[i][j] = cost;
425 if (reg_class_subset_p (i, j))
426 may_move_in_cost[i][j] = 0;
428 may_move_in_cost[i][j] = cost;
430 if (reg_class_subset_p (j, i))
431 may_move_out_cost[i][j] = 0;
433 may_move_out_cost[i][j] = cost;
437 /* Compute the table of register modes.
438 These values are used to record death information for individual registers
439 (as opposed to a multi-register mode). */
446 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
448 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
450 /* If we couldn't find a valid mode, just use the previous mode.
451 ??? One situation in which we need to do this is on the mips where
452 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
453 to use DF mode for the even registers and VOIDmode for the odd
454 (for the cpu models where the odd ones are inaccessible). */
455 if (reg_raw_mode[i] == VOIDmode)
456 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
460 /* Finish initializing the register sets and
461 initialize the register modes. */
466 /* This finishes what was started by init_reg_sets, but couldn't be done
467 until after register usage was specified. */
472 #ifdef HAVE_SECONDARY_RELOADS
474 /* Make some fake stack-frame MEM references for use in
475 memory_move_secondary_cost. */
477 for (i = 0; i < MAX_MACHINE_MODE; i++)
478 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
479 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
484 #ifdef HAVE_SECONDARY_RELOADS
486 /* Compute extra cost of moving registers to/from memory due to reloads.
487 Only needed if secondary reloads are required for memory moves. */
490 memory_move_secondary_cost (mode, class, in)
491 enum machine_mode mode;
492 enum reg_class class;
495 enum reg_class altclass;
496 int partial_cost = 0;
497 /* We need a memory reference to feed to SECONDARY... macros. */
498 rtx mem = top_of_stack[(int) mode];
502 #ifdef SECONDARY_INPUT_RELOAD_CLASS
503 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
510 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
511 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
517 if (altclass == NO_REGS)
521 partial_cost = REGISTER_MOVE_COST (altclass, class);
523 partial_cost = REGISTER_MOVE_COST (class, altclass);
525 if (class == altclass)
526 /* This isn't simply a copy-to-temporary situation. Can't guess
527 what it is, so MEMORY_MOVE_COST really ought not to be calling
530 I'm tempted to put in an abort here, but returning this will
531 probably only give poor estimates, which is what we would've
532 had before this code anyways. */
535 /* Check if the secondary reload register will also need a
537 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
541 /* Return a machine mode that is legitimate for hard reg REGNO and large
542 enough to save nregs. If we can't find one, return VOIDmode. */
545 choose_hard_reg_mode (regno, nregs)
549 enum machine_mode found_mode = VOIDmode, mode;
551 /* We first look for the largest integer mode that can be validly
552 held in REGNO. If none, we look for the largest floating-point mode.
553 If we still didn't find a valid mode, try CCmode. */
555 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
557 mode = GET_MODE_WIDER_MODE (mode))
558 if (HARD_REGNO_NREGS (regno, mode) == nregs
559 && HARD_REGNO_MODE_OK (regno, mode))
562 if (found_mode != VOIDmode)
565 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
567 mode = GET_MODE_WIDER_MODE (mode))
568 if (HARD_REGNO_NREGS (regno, mode) == nregs
569 && HARD_REGNO_MODE_OK (regno, mode))
572 if (found_mode != VOIDmode)
575 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
576 && HARD_REGNO_MODE_OK (regno, CCmode))
579 /* We can't find a mode valid for this register. */
583 /* Specify the usage characteristics of the register named NAME.
584 It should be a fixed register if FIXED and a
585 call-used register if CALL_USED. */
588 fix_register (name, fixed, call_used)
590 int fixed, call_used;
594 /* Decode the name and update the primary form of
595 the register info. */
597 if ((i = decode_reg_name (name)) >= 0)
599 if ((i == STACK_POINTER_REGNUM
600 #ifdef HARD_FRAME_POINTER_REGNUM
601 || i == HARD_FRAME_POINTER_REGNUM
603 || i == FRAME_POINTER_REGNUM
606 && (fixed == 0 || call_used == 0))
608 static const char * const what_option[2][2] = {
609 { "call-saved", "call-used" },
610 { "no-such-option", "fixed" }};
612 error ("can't use '%s' as a %s register", name,
613 what_option[fixed][call_used]);
617 fixed_regs[i] = fixed;
618 call_used_regs[i] = call_used;
623 warning ("unknown register name: %s", name);
627 /* Mark register number I as global. */
633 if (fixed_regs[i] == 0 && no_global_reg_vars)
634 error ("global register variable follows a function definition");
638 warning ("register used for two global register variables");
642 if (call_used_regs[i] && ! fixed_regs[i])
643 warning ("call-clobbered register used for global register variable");
647 /* If already fixed, nothing else to do. */
651 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
654 SET_HARD_REG_BIT (fixed_reg_set, i);
655 SET_HARD_REG_BIT (call_used_reg_set, i);
656 SET_HARD_REG_BIT (call_fixed_reg_set, i);
659 /* Now the data and code for the `regclass' pass, which happens
660 just before local-alloc. */
662 /* The `costs' struct records the cost of using a hard register of each class
663 and of using memory for each pseudo. We use this data to set up
664 register class preferences. */
668 int cost[N_REG_CLASSES];
672 /* Structure used to record preferrences of given pseudo. */
675 /* (enum reg_class) prefclass is the preferred class. */
678 /* altclass is a register class that we should use for allocating
679 pseudo if no register in the preferred class is available.
680 If no register in this class is available, memory is preferred.
682 It might appear to be more general to have a bitmask of classes here,
683 but since it is recommended that there be a class corresponding to the
684 union of most major pair of classes, that generality is not required. */
688 /* Record the cost of each class for each pseudo. */
690 static struct costs *costs;
692 /* Initialized once, and used to initialize cost values for each insn. */
694 static struct costs init_cost;
696 /* Record the same data by operand number, accumulated for each alternative
697 in an insn. The contribution to a pseudo is that of the minimum-cost
700 static struct costs op_costs[MAX_RECOG_OPERANDS];
702 /* Record preferrences of each pseudo.
703 This is available after `regclass' is run. */
705 static struct reg_pref *reg_pref;
707 /* Allocated buffers for reg_pref. */
709 static struct reg_pref *reg_pref_buffer;
711 /* Record the depth of loops that we are in. */
713 static int loop_depth;
715 /* Account for the fact that insns within a loop are executed very commonly,
716 but don't keep doing this as loops go too deep. */
718 static int loop_cost;
720 static rtx scan_one_insn PROTO((rtx, int));
721 static void dump_regclass PROTO((FILE *));
722 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
723 char *, const char **, rtx));
724 static int copy_cost PROTO((rtx, enum machine_mode,
725 enum reg_class, int));
726 static void record_address_regs PROTO((rtx, enum reg_class, int));
727 #ifdef FORBIDDEN_INC_DEC_CLASSES
728 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
730 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
732 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
733 This function is sometimes called before the info has been computed.
734 When that happens, just return GENERAL_REGS, which is innocuous. */
737 reg_preferred_class (regno)
742 return (enum reg_class) reg_pref[regno].prefclass;
746 reg_alternate_class (regno)
752 return (enum reg_class) reg_pref[regno].altclass;
755 /* Initialize some global data for this pass. */
762 init_cost.mem_cost = 10000;
763 for (i = 0; i < N_REG_CLASSES; i++)
764 init_cost.cost[i] = 10000;
766 /* This prevents dump_flow_info from losing if called
767 before regclass is run. */
770 /* No more global register variables may be declared. */
771 no_global_reg_vars = 1;
774 /* Dump register costs. */
779 static const char *const reg_class_names[] = REG_CLASS_NAMES;
781 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
783 enum reg_class class;
786 fprintf (dump, ";; Register %i costs:", i);
787 for (class = 0; class < N_REG_CLASSES; class++)
788 fprintf (dump, " %s:%i", reg_class_names[(int) class],
789 costs[i].cost[class]);
790 fprintf (dump, " MEM:%i\n\n", costs[i].mem_cost);
796 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
797 time it would save code to put a certain register in a certain class.
798 PASS, when nonzero, inhibits some optimizations which need only be done
800 Return the last insn processed, so that the scan can be continued from
804 scan_one_insn (insn, pass)
808 enum rtx_code code = GET_CODE (insn);
809 enum rtx_code pat_code;
810 const char *constraints[MAX_RECOG_OPERANDS];
811 enum machine_mode modes[MAX_RECOG_OPERANDS];
812 char subreg_changes_size[MAX_RECOG_OPERANDS];
816 /* Show that an insn inside a loop is likely to be executed three
817 times more than insns outside a loop. This is much more aggressive
818 than the assumptions made elsewhere and is being tried as an
823 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
824 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
825 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
826 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
831 if (GET_RTX_CLASS (code) != 'i')
834 pat_code = GET_CODE (PATTERN (insn));
836 || pat_code == CLOBBER
837 || pat_code == ASM_INPUT
838 || pat_code == ADDR_VEC
839 || pat_code == ADDR_DIFF_VEC)
842 set = single_set (insn);
845 for (i = 0; i < recog_data.n_operands; i++)
847 constraints[i] = recog_data.constraints[i];
848 modes[i] = recog_data.operand_mode[i];
850 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
852 /* If this insn loads a parameter from its stack slot, then
853 it represents a savings, rather than a cost, if the
854 parameter is stored in memory. Record this fact. */
856 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
857 && GET_CODE (SET_SRC (set)) == MEM
858 && (note = find_reg_note (insn, REG_EQUIV,
860 && GET_CODE (XEXP (note, 0)) == MEM)
862 costs[REGNO (SET_DEST (set))].mem_cost
863 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
866 record_address_regs (XEXP (SET_SRC (set), 0),
867 BASE_REG_CLASS, loop_cost * 2);
871 /* Improve handling of two-address insns such as
872 (set X (ashift CONST Y)) where CONST must be made to
873 match X. Change it into two insns: (set X CONST)
874 (set X (ashift X Y)). If we left this for reloading, it
875 would probably get three insns because X and Y might go
876 in the same place. This prevents X and Y from receiving
879 We can only do this if the modes of operands 0 and 1
880 (which might not be the same) are tieable and we only need
881 do this during our first pass. */
883 if (pass == 0 && optimize
884 && recog_data.n_operands >= 3
885 && recog_data.constraints[1][0] == '0'
886 && recog_data.constraints[1][1] == 0
887 && CONSTANT_P (recog_data.operand[1])
888 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
889 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
890 && GET_CODE (recog_data.operand[0]) == REG
891 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
892 recog_data.operand_mode[1]))
894 rtx previnsn = prev_real_insn (insn);
896 = gen_lowpart (recog_data.operand_mode[1],
897 recog_data.operand[0]);
899 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
901 /* If this insn was the start of a basic block,
902 include the new insn in that block.
903 We need not check for code_label here;
904 while a basic block can start with a code_label,
905 INSN could not be at the beginning of that block. */
906 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
909 for (b = 0; b < n_basic_blocks; b++)
910 if (insn == BLOCK_HEAD (b))
911 BLOCK_HEAD (b) = newinsn;
914 /* This makes one more setting of new insns's dest. */
915 REG_N_SETS (REGNO (recog_data.operand[0]))++;
917 *recog_data.operand_loc[1] = recog_data.operand[0];
918 for (i = recog_data.n_dups - 1; i >= 0; i--)
919 if (recog_data.dup_num[i] == 1)
920 *recog_data.dup_loc[i] = recog_data.operand[0];
922 return PREV_INSN (newinsn);
925 /* If we get here, we are set up to record the costs of all the
926 operands for this insn. Start by initializing the costs.
927 Then handle any address registers. Finally record the desired
928 classes for any pseudos, doing it twice if some pair of
929 operands are commutative. */
931 for (i = 0; i < recog_data.n_operands; i++)
933 op_costs[i] = init_cost;
935 if (GET_CODE (recog_data.operand[i]) == SUBREG)
937 rtx inner = SUBREG_REG (recog_data.operand[i]);
938 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
939 subreg_changes_size[i] = 1;
940 recog_data.operand[i] = inner;
943 if (GET_CODE (recog_data.operand[i]) == MEM)
944 record_address_regs (XEXP (recog_data.operand[i], 0),
945 BASE_REG_CLASS, loop_cost * 2);
946 else if (constraints[i][0] == 'p')
947 record_address_regs (recog_data.operand[i],
948 BASE_REG_CLASS, loop_cost * 2);
951 /* Check for commutative in a separate loop so everything will
952 have been initialized. We must do this even if one operand
953 is a constant--see addsi3 in m68k.md. */
955 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
956 if (constraints[i][0] == '%')
958 const char *xconstraints[MAX_RECOG_OPERANDS];
961 /* Handle commutative operands by swapping the constraints.
962 We assume the modes are the same. */
964 for (j = 0; j < recog_data.n_operands; j++)
965 xconstraints[j] = constraints[j];
967 xconstraints[i] = constraints[i+1];
968 xconstraints[i+1] = constraints[i];
969 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
970 recog_data.operand, modes, subreg_changes_size,
974 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
975 recog_data.operand, modes, subreg_changes_size,
978 /* Now add the cost for each operand to the total costs for
981 for (i = 0; i < recog_data.n_operands; i++)
982 if (GET_CODE (recog_data.operand[i]) == REG
983 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
985 int regno = REGNO (recog_data.operand[i]);
986 struct costs *p = &costs[regno], *q = &op_costs[i];
988 p->mem_cost += q->mem_cost * loop_cost;
989 for (j = 0; j < N_REG_CLASSES; j++)
990 p->cost[j] += q->cost[j] * loop_cost;
996 /* This is a pass of the compiler that scans all instructions
997 and calculates the preferred class for each pseudo-register.
998 This information can be accessed later by calling `reg_preferred_class'.
999 This pass comes just before local register allocation. */
1002 regclass (f, nregs, dump)
1013 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1015 #ifdef FORBIDDEN_INC_DEC_CLASSES
1017 in_inc_dec = (char *) xmalloc (nregs);
1019 /* Initialize information about which register classes can be used for
1020 pseudos that are auto-incremented or auto-decremented. It would
1021 seem better to put this in init_reg_sets, but we need to be able
1022 to allocate rtx, which we can't do that early. */
1024 for (i = 0; i < N_REG_CLASSES; i++)
1026 rtx r = gen_rtx_REG (VOIDmode, 0);
1027 enum machine_mode m;
1030 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1031 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1035 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1036 m = (enum machine_mode) ((int) m + 1))
1037 if (HARD_REGNO_MODE_OK (j, m))
1041 /* If a register is not directly suitable for an
1042 auto-increment or decrement addressing mode and
1043 requires secondary reloads, disallow its class from
1044 being used in such addresses. */
1047 #ifdef SECONDARY_RELOAD_CLASS
1048 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1051 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1052 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1055 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1056 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1061 && ! auto_inc_dec_reg_p (r, m))
1062 forbidden_inc_dec_class[i] = 1;
1066 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1068 /* Normally we scan the insns once and determine the best class to use for
1069 each register. However, if -fexpensive_optimizations are on, we do so
1070 twice, the second time using the tentative best classes to guide the
1073 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1075 /* Zero out our accumulation of the cost of each class for each reg. */
1077 bzero ((char *) costs, nregs * sizeof (struct costs));
1079 #ifdef FORBIDDEN_INC_DEC_CLASSES
1080 bzero (in_inc_dec, nregs);
1083 loop_depth = 0, loop_cost = 1;
1085 /* Scan the instructions and record each time it would
1086 save code to put a certain register in a certain class. */
1088 for (insn = f; insn; insn = NEXT_INSN (insn))
1090 insn = scan_one_insn (insn, pass);
1093 /* Now for each register look at how desirable each class is
1094 and find which class is preferred. Store that in
1095 `prefclass'. Record in `altclass' the largest register
1096 class any of whose registers is better than memory. */
1099 reg_pref = reg_pref_buffer;
1101 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1103 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1104 enum reg_class best = ALL_REGS, alt = NO_REGS;
1105 /* This is an enum reg_class, but we call it an int
1106 to save lots of casts. */
1108 register struct costs *p = &costs[i];
1110 for (class = (int) ALL_REGS - 1; class > 0; class--)
1112 /* Ignore classes that are too small for this operand or
1113 invalid for a operand that was auto-incremented. */
1114 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1115 > reg_class_size[class]
1116 #ifdef FORBIDDEN_INC_DEC_CLASSES
1117 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1121 else if (p->cost[class] < best_cost)
1123 best_cost = p->cost[class];
1124 best = (enum reg_class) class;
1126 else if (p->cost[class] == best_cost)
1127 best = reg_class_subunion[(int)best][class];
1130 /* Record the alternate register class; i.e., a class for which
1131 every register in it is better than using memory. If adding a
1132 class would make a smaller class (i.e., no union of just those
1133 classes exists), skip that class. The major unions of classes
1134 should be provided as a register class. Don't do this if we
1135 will be doing it again later. */
1137 if (pass == 1 || ! flag_expensive_optimizations)
1138 for (class = 0; class < N_REG_CLASSES; class++)
1139 if (p->cost[class] < p->mem_cost
1140 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1141 > reg_class_size[(int) alt])
1142 #ifdef FORBIDDEN_INC_DEC_CLASSES
1143 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1146 alt = reg_class_subunion[(int) alt][class];
1148 /* If we don't add any classes, nothing to try. */
1152 /* We cast to (int) because (char) hits bugs in some compilers. */
1153 reg_pref[i].prefclass = (int) best;
1154 reg_pref[i].altclass = (int) alt;
1159 dump_regclass (dump);
1160 #ifdef FORBIDDEN_INC_DEC_CLASSES
1166 /* Record the cost of using memory or registers of various classes for
1167 the operands in INSN.
1169 N_ALTS is the number of alternatives.
1171 N_OPS is the number of operands.
1173 OPS is an array of the operands.
1175 MODES are the modes of the operands, in case any are VOIDmode.
1177 CONSTRAINTS are the constraints to use for the operands. This array
1178 is modified by this procedure.
1180 This procedure works alternative by alternative. For each alternative
1181 we assume that we will be able to allocate all pseudos to their ideal
1182 register class and calculate the cost of using that alternative. Then
1183 we compute for each operand that is a pseudo-register, the cost of
1184 having the pseudo allocated to each register class and using it in that
1185 alternative. To this cost is added the cost of the alternative.
1187 The cost of each class for this insn is its lowest cost among all the
1191 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1196 enum machine_mode *modes;
1197 char *subreg_changes_size;
1198 const char **constraints;
1205 /* Process each alternative, each time minimizing an operand's cost with
1206 the cost for each operand in that alternative. */
1208 for (alt = 0; alt < n_alts; alt++)
1210 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1213 enum reg_class classes[MAX_RECOG_OPERANDS];
1214 int allows_mem[MAX_RECOG_OPERANDS];
1217 for (i = 0; i < n_ops; i++)
1219 const char *p = constraints[i];
1221 enum machine_mode mode = modes[i];
1222 int allows_addr = 0;
1226 /* Initially show we know nothing about the register class. */
1227 classes[i] = NO_REGS;
1230 /* If this operand has no constraints at all, we can conclude
1231 nothing about it since anything is valid. */
1235 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1236 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1241 /* If this alternative is only relevant when this operand
1242 matches a previous operand, we do different things depending
1243 on whether this operand is a pseudo-reg or not. We must process
1244 any modifiers for the operand before we can make this test. */
1246 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1249 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1251 /* Copy class and whether memory is allowed from the matching
1252 alternative. Then perform any needed cost computations
1253 and/or adjustments. */
1255 classes[i] = classes[j];
1256 allows_mem[i] = allows_mem[j];
1258 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1260 /* If this matches the other operand, we have no added
1262 if (rtx_equal_p (ops[j], op))
1265 /* If we can put the other operand into a register, add to
1266 the cost of this alternative the cost to copy this
1267 operand to the register used for the other operand. */
1269 else if (classes[j] != NO_REGS)
1270 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1272 else if (GET_CODE (ops[j]) != REG
1273 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1275 /* This op is a pseudo but the one it matches is not. */
1277 /* If we can't put the other operand into a register, this
1278 alternative can't be used. */
1280 if (classes[j] == NO_REGS)
1283 /* Otherwise, add to the cost of this alternative the cost
1284 to copy the other operand to the register used for this
1288 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1292 /* The costs of this operand are not the same as the other
1293 operand since move costs are not symmetric. Moreover,
1294 if we cannot tie them, this alternative needs to do a
1295 copy, which is one instruction. */
1297 struct costs *pp = &this_op_costs[i];
1299 for (class = 0; class < N_REG_CLASSES; class++)
1301 = (recog_data.operand_type[i] == OP_IN
1302 ? may_move_in_cost[class][(int) classes[i]]
1303 : may_move_out_cost[(int) classes[i]][class]);
1305 /* If the alternative actually allows memory, make things
1306 a bit cheaper since we won't need an extra insn to
1310 = (MEMORY_MOVE_COST (mode, classes[i],
1311 recog_data.operand_type[i] == OP_IN)
1314 /* If we have assigned a class to this register in our
1315 first pass, add a cost to this alternative corresponding
1316 to what we would add if this register were not in the
1317 appropriate class. */
1321 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1322 [(int) classes[i]]);
1324 if (REGNO (ops[i]) != REGNO (ops[j])
1325 && ! find_reg_note (insn, REG_DEAD, op))
1328 /* This is in place of ordinary cost computation
1329 for this operand, so skip to the end of the
1330 alternative (should be just one character). */
1331 while (*p && *p++ != ',')
1339 /* Scan all the constraint letters. See if the operand matches
1340 any of the constraints. Collect the valid register classes
1341 and see if this operand accepts memory. */
1343 while (*p && (c = *p++) != ',')
1347 /* Ignore the next letter for this pass. */
1353 case '!': case '#': case '&':
1354 case '0': case '1': case '2': case '3': case '4':
1355 case '5': case '6': case '7': case '8': case '9':
1360 win = address_operand (op, GET_MODE (op));
1361 /* We know this operand is an address, so we want it to be
1362 allocated to a register that can be the base of an
1363 address, ie BASE_REG_CLASS. */
1365 = reg_class_subunion[(int) classes[i]]
1366 [(int) BASE_REG_CLASS];
1369 case 'm': case 'o': case 'V':
1370 /* It doesn't seem worth distinguishing between offsettable
1371 and non-offsettable addresses here. */
1373 if (GET_CODE (op) == MEM)
1378 if (GET_CODE (op) == MEM
1379 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1380 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1385 if (GET_CODE (op) == MEM
1386 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1387 || GET_CODE (XEXP (op, 0)) == POST_INC))
1392 #ifndef REAL_ARITHMETIC
1393 /* Match any floating double constant, but only if
1394 we can examine the bits of it reliably. */
1395 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1396 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1397 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1400 if (GET_CODE (op) == CONST_DOUBLE)
1405 if (GET_CODE (op) == CONST_DOUBLE)
1411 if (GET_CODE (op) == CONST_DOUBLE
1412 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1417 if (GET_CODE (op) == CONST_INT
1418 || (GET_CODE (op) == CONST_DOUBLE
1419 && GET_MODE (op) == VOIDmode))
1423 #ifdef LEGITIMATE_PIC_OPERAND_P
1424 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1431 if (GET_CODE (op) == CONST_INT
1432 || (GET_CODE (op) == CONST_DOUBLE
1433 && GET_MODE (op) == VOIDmode))
1445 if (GET_CODE (op) == CONST_INT
1446 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1454 #ifdef EXTRA_CONSTRAINT
1460 if (EXTRA_CONSTRAINT (op, c))
1466 if (GET_CODE (op) == MEM
1468 #ifdef LEGITIMATE_PIC_OPERAND_P
1469 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1476 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1481 = reg_class_subunion[(int) classes[i]]
1482 [(int) REG_CLASS_FROM_LETTER (c)];
1487 #ifdef CLASS_CANNOT_CHANGE_SIZE
1488 /* If we noted a subreg earlier, and the selected class is a
1489 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1490 if (subreg_changes_size[i]
1491 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1493 == CLASS_CANNOT_CHANGE_SIZE))
1494 classes[i] = NO_REGS;
1497 /* How we account for this operand now depends on whether it is a
1498 pseudo register or not. If it is, we first check if any
1499 register classes are valid. If not, we ignore this alternative,
1500 since we want to assume that all pseudos get allocated for
1501 register preferencing. If some register class is valid, compute
1502 the costs of moving the pseudo into that class. */
1504 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1506 if (classes[i] == NO_REGS)
1508 /* We must always fail if the operand is a REG, but
1509 we did not find a suitable class.
1511 Otherwise we may perform an uninitialized read
1512 from this_op_costs after the `continue' statement
1518 struct costs *pp = &this_op_costs[i];
1520 for (class = 0; class < N_REG_CLASSES; class++)
1522 = (recog_data.operand_type[i] == OP_IN
1523 ? may_move_in_cost[class][(int) classes[i]]
1524 : may_move_out_cost[(int) classes[i]][class]);
1526 /* If the alternative actually allows memory, make things
1527 a bit cheaper since we won't need an extra insn to
1531 = (MEMORY_MOVE_COST (mode, classes[i],
1532 recog_data.operand_type[i] == OP_IN)
1535 /* If we have assigned a class to this register in our
1536 first pass, add a cost to this alternative corresponding
1537 to what we would add if this register were not in the
1538 appropriate class. */
1542 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1543 [(int) classes[i]]);
1547 /* Otherwise, if this alternative wins, either because we
1548 have already determined that or if we have a hard register of
1549 the proper class, there is no cost for this alternative. */
1552 || (GET_CODE (op) == REG
1553 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1556 /* If registers are valid, the cost of this alternative includes
1557 copying the object to and/or from a register. */
1559 else if (classes[i] != NO_REGS)
1561 if (recog_data.operand_type[i] != OP_OUT)
1562 alt_cost += copy_cost (op, mode, classes[i], 1);
1564 if (recog_data.operand_type[i] != OP_IN)
1565 alt_cost += copy_cost (op, mode, classes[i], 0);
1568 /* The only other way this alternative can be used is if this is a
1569 constant that could be placed into memory. */
1571 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1572 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1580 /* Finally, update the costs with the information we've calculated
1581 about this alternative. */
1583 for (i = 0; i < n_ops; i++)
1584 if (GET_CODE (ops[i]) == REG
1585 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1587 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1588 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1590 pp->mem_cost = MIN (pp->mem_cost,
1591 (qq->mem_cost + alt_cost) * scale);
1593 for (class = 0; class < N_REG_CLASSES; class++)
1594 pp->cost[class] = MIN (pp->cost[class],
1595 (qq->cost[class] + alt_cost) * scale);
1599 /* If this insn is a single set copying operand 1 to operand 0
1600 and one is a pseudo with the other a hard reg that is in its
1601 own register class, set the cost of that register class to -1. */
1603 if ((set = single_set (insn)) != 0
1604 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1605 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1606 for (i = 0; i <= 1; i++)
1607 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1609 int regno = REGNO (ops[!i]);
1610 enum machine_mode mode = GET_MODE (ops[!i]);
1614 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0
1615 && (reg_class_size[(unsigned char) reg_pref[regno].prefclass]
1616 == CLASS_MAX_NREGS (reg_pref[regno].prefclass, mode)))
1617 op_costs[i].cost[(unsigned char) reg_pref[regno].prefclass] = -1;
1618 else if (regno < FIRST_PSEUDO_REGISTER)
1619 for (class = 0; class < N_REG_CLASSES; class++)
1620 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1621 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1623 if (reg_class_size[class] == 1)
1624 op_costs[i].cost[class] = -1;
1627 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1629 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1633 if (nr == HARD_REGNO_NREGS(regno,mode))
1634 op_costs[i].cost[class] = -1;
1640 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1641 TO_P is zero) a register of class CLASS in mode MODE.
1643 X must not be a pseudo. */
1646 copy_cost (x, mode, class, to_p)
1648 enum machine_mode mode;
1649 enum reg_class class;
1652 #ifdef HAVE_SECONDARY_RELOADS
1653 enum reg_class secondary_class = NO_REGS;
1656 /* If X is a SCRATCH, there is actually nothing to move since we are
1657 assuming optimal allocation. */
1659 if (GET_CODE (x) == SCRATCH)
1662 /* Get the class we will actually use for a reload. */
1663 class = PREFERRED_RELOAD_CLASS (x, class);
1665 #ifdef HAVE_SECONDARY_RELOADS
1666 /* If we need a secondary reload (we assume here that we are using
1667 the secondary reload as an intermediate, not a scratch register), the
1668 cost is that to load the input into the intermediate register, then
1669 to copy them. We use a special value of TO_P to avoid recursion. */
1671 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1673 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1676 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1678 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1681 if (secondary_class != NO_REGS)
1682 return (move_cost[(int) secondary_class][(int) class]
1683 + copy_cost (x, mode, secondary_class, 2));
1684 #endif /* HAVE_SECONDARY_RELOADS */
1686 /* For memory, use the memory move cost, for (hard) registers, use the
1687 cost to move between the register classes, and use 2 for everything
1688 else (constants). */
1690 if (GET_CODE (x) == MEM || class == NO_REGS)
1691 return MEMORY_MOVE_COST (mode, class, to_p);
1693 else if (GET_CODE (x) == REG)
1694 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1697 /* If this is a constant, we may eventually want to call rtx_cost here. */
1701 /* Record the pseudo registers we must reload into hard registers
1702 in a subexpression of a memory address, X.
1704 CLASS is the class that the register needs to be in and is either
1705 BASE_REG_CLASS or INDEX_REG_CLASS.
1707 SCALE is twice the amount to multiply the cost by (it is twice so we
1708 can represent half-cost adjustments). */
1711 record_address_regs (x, class, scale)
1713 enum reg_class class;
1716 register enum rtx_code code = GET_CODE (x);
1729 /* When we have an address that is a sum,
1730 we must determine whether registers are "base" or "index" regs.
1731 If there is a sum of two registers, we must choose one to be
1732 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1733 to make a good choice most of the time. We only need to do this
1734 on machines that can have two registers in an address and where
1735 the base and index register classes are different.
1737 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1738 that seems bogus since it should only be set when we are sure
1739 the register is being used as a pointer. */
1742 rtx arg0 = XEXP (x, 0);
1743 rtx arg1 = XEXP (x, 1);
1744 register enum rtx_code code0 = GET_CODE (arg0);
1745 register enum rtx_code code1 = GET_CODE (arg1);
1747 /* Look inside subregs. */
1748 if (code0 == SUBREG)
1749 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1750 if (code1 == SUBREG)
1751 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1753 /* If this machine only allows one register per address, it must
1754 be in the first operand. */
1756 if (MAX_REGS_PER_ADDRESS == 1)
1757 record_address_regs (arg0, class, scale);
1759 /* If index and base registers are the same on this machine, just
1760 record registers in any non-constant operands. We assume here,
1761 as well as in the tests below, that all addresses are in
1764 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1766 record_address_regs (arg0, class, scale);
1767 if (! CONSTANT_P (arg1))
1768 record_address_regs (arg1, class, scale);
1771 /* If the second operand is a constant integer, it doesn't change
1772 what class the first operand must be. */
1774 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1775 record_address_regs (arg0, class, scale);
1777 /* If the second operand is a symbolic constant, the first operand
1778 must be an index register. */
1780 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1781 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1783 /* If both operands are registers but one is already a hard register
1784 of index or base class, give the other the class that the hard
1787 #ifdef REG_OK_FOR_BASE_P
1788 else if (code0 == REG && code1 == REG
1789 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1790 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1791 record_address_regs (arg1,
1792 REG_OK_FOR_BASE_P (arg0)
1793 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1795 else if (code0 == REG && code1 == REG
1796 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1797 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1798 record_address_regs (arg0,
1799 REG_OK_FOR_BASE_P (arg1)
1800 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1804 /* If one operand is known to be a pointer, it must be the base
1805 with the other operand the index. Likewise if the other operand
1808 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1811 record_address_regs (arg0, BASE_REG_CLASS, scale);
1812 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1814 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1817 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1818 record_address_regs (arg1, BASE_REG_CLASS, scale);
1821 /* Otherwise, count equal chances that each might be a base
1822 or index register. This case should be rare. */
1826 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1827 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1828 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1829 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1838 /* Double the importance of a pseudo register that is incremented
1839 or decremented, since it would take two extra insns
1840 if it ends up in the wrong place. If the operand is a pseudo,
1841 show it is being used in an INC_DEC context. */
1843 #ifdef FORBIDDEN_INC_DEC_CLASSES
1844 if (GET_CODE (XEXP (x, 0)) == REG
1845 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1846 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1849 record_address_regs (XEXP (x, 0), class, 2 * scale);
1854 register struct costs *pp = &costs[REGNO (x)];
1857 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1859 for (i = 0; i < N_REG_CLASSES; i++)
1860 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1866 register const char *fmt = GET_RTX_FORMAT (code);
1868 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1870 record_address_regs (XEXP (x, i), class, scale);
1875 #ifdef FORBIDDEN_INC_DEC_CLASSES
1877 /* Return 1 if REG is valid as an auto-increment memory reference
1878 to an object of MODE. */
1881 auto_inc_dec_reg_p (reg, mode)
1883 enum machine_mode mode;
1885 if (HAVE_POST_INCREMENT
1886 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1889 if (HAVE_POST_DECREMENT
1890 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1893 if (HAVE_PRE_INCREMENT
1894 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1897 if (HAVE_PRE_DECREMENT
1898 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1905 static short *renumber = (short *)0;
1906 static size_t regno_allocated = 0;
1908 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1909 reg_scan and flow_analysis that are indexed by the register number. If
1910 NEW_P is non zero, initialize all of the registers, otherwise only
1911 initialize the new registers allocated. The same table is kept from
1912 function to function, only reallocating it when we need more room. If
1913 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1916 allocate_reg_info (num_regs, new_p, renumber_p)
1922 size_t size_renumber;
1923 size_t min = (new_p) ? 0 : reg_n_max;
1924 struct reg_info_data *reg_data;
1925 struct reg_info_data *reg_next;
1927 if (num_regs > regno_allocated)
1929 size_t old_allocated = regno_allocated;
1931 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1932 size_renumber = regno_allocated * sizeof (short);
1936 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1937 renumber = (short *) xmalloc (size_renumber);
1938 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
1939 * sizeof (struct reg_pref));
1944 VARRAY_GROW (reg_n_info, regno_allocated);
1946 if (new_p) /* if we're zapping everything, no need to realloc */
1948 free ((char *)renumber);
1949 free ((char *)reg_pref);
1950 renumber = (short *) xmalloc (size_renumber);
1951 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
1952 * sizeof (struct reg_pref));
1957 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1958 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
1960 * sizeof (struct reg_pref));
1964 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1965 + sizeof (struct reg_info_data) - sizeof (reg_info);
1966 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1967 reg_data->min_index = old_allocated;
1968 reg_data->max_index = regno_allocated - 1;
1969 reg_data->next = reg_info_head;
1970 reg_info_head = reg_data;
1973 reg_n_max = num_regs;
1976 /* Loop through each of the segments allocated for the actual
1977 reg_info pages, and set up the pointers, zero the pages, etc. */
1978 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1980 size_t min_index = reg_data->min_index;
1981 size_t max_index = reg_data->max_index;
1983 reg_next = reg_data->next;
1984 if (min <= max_index)
1986 size_t max = max_index;
1987 size_t local_min = min - min_index;
1990 if (min < min_index)
1992 if (!reg_data->used_p) /* page just allocated with calloc */
1993 reg_data->used_p = 1; /* no need to zero */
1995 bzero ((char *) ®_data->data[local_min],
1996 sizeof (reg_info) * (max - min_index - local_min + 1));
1998 for (i = min_index+local_min; i <= max; i++)
2000 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2001 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2003 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2004 reg_pref_buffer[i].altclass = (char) NO_REGS;
2010 /* If {pref,alt}class have already been allocated, update the pointers to
2011 the newly realloced ones. */
2013 reg_pref = reg_pref_buffer;
2016 reg_renumber = renumber;
2018 /* Tell the regset code about the new number of registers */
2019 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2022 /* Free up the space allocated by allocate_reg_info. */
2028 struct reg_info_data *reg_data;
2029 struct reg_info_data *reg_next;
2031 VARRAY_FREE (reg_n_info);
2032 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2034 reg_next = reg_data->next;
2035 free ((char *)reg_data);
2038 free (reg_pref_buffer);
2039 reg_pref_buffer = (struct reg_pref *)0;
2040 reg_info_head = (struct reg_info_data *)0;
2041 renumber = (short *)0;
2043 regno_allocated = 0;
2047 /* This is the `regscan' pass of the compiler, run just before cse
2048 and again just before loop.
2050 It finds the first and last use of each pseudo-register
2051 and records them in the vectors regno_first_uid, regno_last_uid
2052 and counts the number of sets in the vector reg_n_sets.
2054 REPEAT is nonzero the second time this is called. */
2056 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2057 Always at least 3, since the combiner could put that many together
2058 and we want this to remain correct for all the remaining passes. */
2063 reg_scan (f, nregs, repeat)
2070 allocate_reg_info (nregs, TRUE, FALSE);
2073 for (insn = f; insn; insn = NEXT_INSN (insn))
2074 if (GET_CODE (insn) == INSN
2075 || GET_CODE (insn) == CALL_INSN
2076 || GET_CODE (insn) == JUMP_INSN)
2078 if (GET_CODE (PATTERN (insn)) == PARALLEL
2079 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2080 max_parallel = XVECLEN (PATTERN (insn), 0);
2081 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2083 if (REG_NOTES (insn))
2084 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2088 /* Update 'regscan' information by looking at the insns
2089 from FIRST to LAST. Some new REGs have been created,
2090 and any REG with number greater than OLD_MAX_REGNO is
2091 such a REG. We only update information for those. */
2094 reg_scan_update(first, last, old_max_regno)
2101 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2103 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2104 if (GET_CODE (insn) == INSN
2105 || GET_CODE (insn) == CALL_INSN
2106 || GET_CODE (insn) == JUMP_INSN)
2108 if (GET_CODE (PATTERN (insn)) == PARALLEL
2109 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2110 max_parallel = XVECLEN (PATTERN (insn), 0);
2111 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2113 if (REG_NOTES (insn))
2114 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2118 /* X is the expression to scan. INSN is the insn it appears in.
2119 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2120 We should only record information for REGs with numbers
2121 greater than or equal to MIN_REGNO. */
2124 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2130 register enum rtx_code code;
2134 code = GET_CODE (x);
2150 register int regno = REGNO (x);
2152 if (regno >= min_regno)
2154 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2156 REGNO_LAST_UID (regno) = INSN_UID (insn);
2157 if (REGNO_FIRST_UID (regno) == 0)
2158 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2165 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2167 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2172 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2176 /* Count a set of the destination if it is a register. */
2177 for (dest = SET_DEST (x);
2178 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2179 || GET_CODE (dest) == ZERO_EXTEND;
2180 dest = XEXP (dest, 0))
2183 if (GET_CODE (dest) == REG
2184 && REGNO (dest) >= min_regno)
2185 REG_N_SETS (REGNO (dest))++;
2187 /* If this is setting a pseudo from another pseudo or the sum of a
2188 pseudo and a constant integer and the other pseudo is known to be
2189 a pointer, set the destination to be a pointer as well.
2191 Likewise if it is setting the destination from an address or from a
2192 value equivalent to an address or to the sum of an address and
2195 But don't do any of this if the pseudo corresponds to a user
2196 variable since it should have already been set as a pointer based
2199 if (GET_CODE (SET_DEST (x)) == REG
2200 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2201 && REGNO (SET_DEST (x)) >= min_regno
2202 /* If the destination pseudo is set more than once, then other
2203 sets might not be to a pointer value (consider access to a
2204 union in two threads of control in the presense of global
2205 optimizations). So only set REGNO_POINTER_FLAG on the destination
2206 pseudo if this is the only set of that pseudo. */
2207 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2208 && ! REG_USERVAR_P (SET_DEST (x))
2209 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2210 && ((GET_CODE (SET_SRC (x)) == REG
2211 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2212 || ((GET_CODE (SET_SRC (x)) == PLUS
2213 || GET_CODE (SET_SRC (x)) == LO_SUM)
2214 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2215 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2216 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2217 || GET_CODE (SET_SRC (x)) == CONST
2218 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2219 || GET_CODE (SET_SRC (x)) == LABEL_REF
2220 || (GET_CODE (SET_SRC (x)) == HIGH
2221 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2222 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2223 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2224 || ((GET_CODE (SET_SRC (x)) == PLUS
2225 || GET_CODE (SET_SRC (x)) == LO_SUM)
2226 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2227 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2228 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2229 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2230 && (GET_CODE (XEXP (note, 0)) == CONST
2231 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2232 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2233 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2235 /* ... fall through ... */
2239 register const char *fmt = GET_RTX_FORMAT (code);
2241 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2244 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2245 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2248 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2249 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2256 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2260 reg_class_subset_p (c1, c2)
2261 register enum reg_class c1;
2262 register enum reg_class c2;
2264 if (c1 == c2) return 1;
2269 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2270 reg_class_contents[(int)c2],
2275 /* Return nonzero if there is a register that is in both C1 and C2. */
2278 reg_classes_intersect_p (c1, c2)
2279 register enum reg_class c1;
2280 register enum reg_class c2;
2287 if (c1 == c2) return 1;
2289 if (c1 == ALL_REGS || c2 == ALL_REGS)
2292 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2293 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2295 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2302 /* Release any memory allocated by register sets. */
2305 regset_release_memory ()
2307 bitmap_release_memory ();