1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
42 #ifndef REGISTER_MOVE_COST
43 #define REGISTER_MOVE_COST(x, y) 2
46 static void init_reg_sets_1 PROTO((void));
47 static void init_reg_modes PROTO((void));
49 /* If we have auto-increment or auto-decrement and we can have secondary
50 reloads, we are not allowed to use classes requiring secondary
51 reloads for pseudos auto-incremented since reload can't handle it. */
54 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
55 #define FORBIDDEN_INC_DEC_CLASSES
59 /* Register tables used by many passes. */
61 /* Indexed by hard register number, contains 1 for registers
62 that are fixed use (stack pointer, pc, frame pointer, etc.).
63 These are the registers that cannot be used to allocate
64 a pseudo reg for general use. */
66 char fixed_regs[FIRST_PSEUDO_REGISTER];
68 /* Same info as a HARD_REG_SET. */
70 HARD_REG_SET fixed_reg_set;
72 /* Data for initializing the above. */
74 static char initial_fixed_regs[] = FIXED_REGISTERS;
76 /* Indexed by hard register number, contains 1 for registers
77 that are fixed use or are clobbered by function calls.
78 These are the registers that cannot be used to allocate
79 a pseudo reg whose life crosses calls unless we are able
80 to save/restore them across the calls. */
82 char call_used_regs[FIRST_PSEUDO_REGISTER];
84 /* Same info as a HARD_REG_SET. */
86 HARD_REG_SET call_used_reg_set;
88 /* HARD_REG_SET of registers we want to avoid caller saving. */
89 HARD_REG_SET losing_caller_save_reg_set;
91 /* Data for initializing the above. */
93 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
95 /* Indexed by hard register number, contains 1 for registers that are
96 fixed use or call used registers that cannot hold quantities across
97 calls even if we are willing to save and restore them. call fixed
98 registers are a subset of call used registers. */
100 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
102 /* The same info as a HARD_REG_SET. */
104 HARD_REG_SET call_fixed_reg_set;
106 /* Number of non-fixed registers. */
108 int n_non_fixed_regs;
110 /* Indexed by hard register number, contains 1 for registers
111 that are being used for global register decls.
112 These must be exempt from ordinary flow analysis
113 and are also considered fixed. */
115 char global_regs[FIRST_PSEUDO_REGISTER];
117 /* Table of register numbers in the order in which to try to use them. */
118 #ifdef REG_ALLOC_ORDER
119 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
122 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
124 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
126 /* The same information, but as an array of unsigned ints. We copy from
127 these unsigned ints to the table above. We do this so the tm.h files
128 do not have to be aware of the wordsize for machines with <= 64 regs. */
131 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
133 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
134 = REG_CLASS_CONTENTS;
136 /* For each reg class, number of regs it contains. */
138 int reg_class_size[N_REG_CLASSES];
140 /* For each reg class, table listing all the containing classes. */
142 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
144 /* For each reg class, table listing all the classes contained in it. */
146 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each pair of reg classes,
149 a largest reg class contained in their union. */
151 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 the smallest reg class containing their union. */
156 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* Array containing all of the register names */
160 char *reg_names[] = REGISTER_NAMES;
162 /* For each hard register, the widest mode object that it can contain.
163 This will be a MODE_INT mode if the register can hold integers. Otherwise
164 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
167 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
169 /* Maximum cost of moving from a register in one class to a register in
170 another class. Based on REGISTER_MOVE_COST. */
172 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
174 /* Similar, but here we don't have to move if the first index is a subset
175 of the second so in that case the cost is zero. */
177 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
179 #ifdef FORBIDDEN_INC_DEC_CLASSES
181 /* These are the classes that regs which are auto-incremented or decremented
184 static int forbidden_inc_dec_class[N_REG_CLASSES];
186 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
189 static char *in_inc_dec;
191 #endif /* FORBIDDEN_INC_DEC_CLASSES */
193 #ifdef HAVE_SECONDARY_RELOADS
195 /* Sample MEM values for use by memory_move_secondary_cost. */
197 static rtx top_of_stack[MAX_MACHINE_MODE];
199 #endif /* HAVE_SECONDARY_RELOADS */
201 /* Linked list of reg_info structures allocated for reg_n_info array.
202 Grouping all of the allocated structures together in one lump
203 means only one call to bzero to clear them, rather than n smaller
205 struct reg_info_data {
206 struct reg_info_data *next; /* next set of reg_info structures */
207 size_t min_index; /* minimum index # */
208 size_t max_index; /* maximum index # */
209 char used_p; /* non-zero if this has been used previously */
210 reg_info data[1]; /* beginning of the reg_info data */
213 static struct reg_info_data *reg_info_head;
216 /* Function called only once to initialize the above data on reg usage.
217 Once this is done, various switches may override. */
224 /* First copy the register information from the initial int form into
227 for (i = 0; i < N_REG_CLASSES; i++)
229 CLEAR_HARD_REG_SET (reg_class_contents[i]);
231 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
232 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
233 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
234 SET_HARD_REG_BIT (reg_class_contents[i], j);
237 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
238 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
239 bzero (global_regs, sizeof global_regs);
241 /* Do any additional initialization regsets may need */
242 INIT_ONCE_REG_SET ();
245 /* After switches have been processed, which perhaps alter
246 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
251 register unsigned int i, j;
253 /* This macro allows the fixed or call-used registers
254 and the register classes to depend on target flags. */
256 #ifdef CONDITIONAL_REGISTER_USAGE
257 CONDITIONAL_REGISTER_USAGE;
260 /* Compute number of hard regs in each class. */
262 bzero ((char *) reg_class_size, sizeof reg_class_size);
263 for (i = 0; i < N_REG_CLASSES; i++)
264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
265 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
268 /* Initialize the table of subunions.
269 reg_class_subunion[I][J] gets the largest-numbered reg-class
270 that is contained in the union of classes I and J. */
272 for (i = 0; i < N_REG_CLASSES; i++)
274 for (j = 0; j < N_REG_CLASSES; j++)
277 register /* Declare it register if it's a scalar. */
282 COPY_HARD_REG_SET (c, reg_class_contents[i]);
283 IOR_HARD_REG_SET (c, reg_class_contents[j]);
284 for (k = 0; k < N_REG_CLASSES; k++)
286 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
291 /* keep the largest subclass */ /* SPEE 900308 */
292 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
293 reg_class_contents[(int) reg_class_subunion[i][j]],
295 reg_class_subunion[i][j] = (enum reg_class) k;
302 /* Initialize the table of superunions.
303 reg_class_superunion[I][J] gets the smallest-numbered reg-class
304 containing the union of classes I and J. */
306 for (i = 0; i < N_REG_CLASSES; i++)
308 for (j = 0; j < N_REG_CLASSES; j++)
311 register /* Declare it register if it's a scalar. */
316 COPY_HARD_REG_SET (c, reg_class_contents[i]);
317 IOR_HARD_REG_SET (c, reg_class_contents[j]);
318 for (k = 0; k < N_REG_CLASSES; k++)
319 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
322 reg_class_superunion[i][j] = (enum reg_class) k;
326 /* Initialize the tables of subclasses and superclasses of each reg class.
327 First clear the whole table, then add the elements as they are found. */
329 for (i = 0; i < N_REG_CLASSES; i++)
331 for (j = 0; j < N_REG_CLASSES; j++)
333 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
334 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
338 for (i = 0; i < N_REG_CLASSES; i++)
340 if (i == (int) NO_REGS)
343 for (j = i + 1; j < N_REG_CLASSES; j++)
347 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
351 /* Reg class I is a subclass of J.
352 Add J to the table of superclasses of I. */
353 p = ®_class_superclasses[i][0];
354 while (*p != LIM_REG_CLASSES) p++;
355 *p = (enum reg_class) j;
356 /* Add I to the table of superclasses of J. */
357 p = ®_class_subclasses[j][0];
358 while (*p != LIM_REG_CLASSES) p++;
359 *p = (enum reg_class) i;
363 /* Initialize "constant" tables. */
365 CLEAR_HARD_REG_SET (fixed_reg_set);
366 CLEAR_HARD_REG_SET (call_used_reg_set);
367 CLEAR_HARD_REG_SET (call_fixed_reg_set);
369 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
371 n_non_fixed_regs = 0;
373 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
376 SET_HARD_REG_BIT (fixed_reg_set, i);
380 if (call_used_regs[i])
381 SET_HARD_REG_BIT (call_used_reg_set, i);
382 if (call_fixed_regs[i])
383 SET_HARD_REG_BIT (call_fixed_reg_set, i);
384 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
385 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
388 /* Initialize the move cost table. Find every subset of each class
389 and take the maximum cost of moving any subset to any other. */
391 for (i = 0; i < N_REG_CLASSES; i++)
392 for (j = 0; j < N_REG_CLASSES; j++)
394 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
395 enum reg_class *p1, *p2;
397 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
399 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
401 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
404 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
406 for (p2 = ®_class_subclasses[j][0];
407 *p2 != LIM_REG_CLASSES; p2++)
409 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
412 move_cost[i][j] = cost;
414 if (reg_class_subset_p (i, j))
417 may_move_cost[i][j] = cost;
421 /* Compute the table of register modes.
422 These values are used to record death information for individual registers
423 (as opposed to a multi-register mode). */
430 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
432 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
434 /* If we couldn't find a valid mode, just use the previous mode.
435 ??? One situation in which we need to do this is on the mips where
436 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
437 to use DF mode for the even registers and VOIDmode for the odd
438 (for the cpu models where the odd ones are inaccessible). */
439 if (reg_raw_mode[i] == VOIDmode)
440 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
444 /* Finish initializing the register sets and
445 initialize the register modes. */
450 /* This finishes what was started by init_reg_sets, but couldn't be done
451 until after register usage was specified. */
456 #ifdef HAVE_SECONDARY_RELOADS
458 /* Make some fake stack-frame MEM references for use in
459 memory_move_secondary_cost. */
461 for (i = 0; i < MAX_MACHINE_MODE; i++)
462 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
467 #ifdef HAVE_SECONDARY_RELOADS
469 /* Compute extra cost of moving registers to/from memory due to reloads.
470 Only needed if secondary reloads are required for memory moves. */
473 memory_move_secondary_cost (mode, class, in)
474 enum machine_mode mode;
475 enum reg_class class;
478 enum reg_class altclass;
479 int partial_cost = 0;
480 /* We need a memory reference to feed to SECONDARY... macros. */
481 rtx mem = top_of_stack[(int) mode];
485 #ifdef SECONDARY_INPUT_RELOAD_CLASS
486 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
493 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
494 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
500 if (altclass == NO_REGS)
504 partial_cost = REGISTER_MOVE_COST (altclass, class);
506 partial_cost = REGISTER_MOVE_COST (class, altclass);
508 if (class == altclass)
509 /* This isn't simply a copy-to-temporary situation. Can't guess
510 what it is, so MEMORY_MOVE_COST really ought not to be calling
513 I'm tempted to put in an abort here, but returning this will
514 probably only give poor estimates, which is what we would've
515 had before this code anyways. */
518 /* Check if the secondary reload register will also need a
520 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
524 /* Return a machine mode that is legitimate for hard reg REGNO and large
525 enough to save nregs. If we can't find one, return VOIDmode. */
528 choose_hard_reg_mode (regno, nregs)
532 enum machine_mode found_mode = VOIDmode, mode;
534 /* We first look for the largest integer mode that can be validly
535 held in REGNO. If none, we look for the largest floating-point mode.
536 If we still didn't find a valid mode, try CCmode. */
538 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
540 mode = GET_MODE_WIDER_MODE (mode))
541 if (HARD_REGNO_NREGS (regno, mode) == nregs
542 && HARD_REGNO_MODE_OK (regno, mode))
545 if (found_mode != VOIDmode)
548 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
550 mode = GET_MODE_WIDER_MODE (mode))
551 if (HARD_REGNO_NREGS (regno, mode) == nregs
552 && HARD_REGNO_MODE_OK (regno, mode))
555 if (found_mode != VOIDmode)
558 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
559 && HARD_REGNO_MODE_OK (regno, CCmode))
562 /* We can't find a mode valid for this register. */
566 /* Specify the usage characteristics of the register named NAME.
567 It should be a fixed register if FIXED and a
568 call-used register if CALL_USED. */
571 fix_register (name, fixed, call_used)
573 int fixed, call_used;
577 /* Decode the name and update the primary form of
578 the register info. */
580 if ((i = decode_reg_name (name)) >= 0)
582 if ((i == STACK_POINTER_REGNUM
583 #ifdef HARD_FRAME_POINTER_REGNUM
584 || i == HARD_FRAME_POINTER_REGNUM
586 || i == FRAME_POINTER_REGNUM
589 && (fixed == 0 || call_used == 0))
591 static const char * const what_option[2][2] = {
592 { "call-saved", "call-used" },
593 { "no-such-option", "fixed" }};
595 error ("can't use '%s' as a %s register", name,
596 what_option[fixed][call_used]);
600 fixed_regs[i] = fixed;
601 call_used_regs[i] = call_used;
606 warning ("unknown register name: %s", name);
610 /* Mark register number I as global. */
618 warning ("register used for two global register variables");
622 if (call_used_regs[i] && ! fixed_regs[i])
623 warning ("call-clobbered register used for global register variable");
627 /* If already fixed, nothing else to do. */
631 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
634 SET_HARD_REG_BIT (fixed_reg_set, i);
635 SET_HARD_REG_BIT (call_used_reg_set, i);
636 SET_HARD_REG_BIT (call_fixed_reg_set, i);
639 /* Now the data and code for the `regclass' pass, which happens
640 just before local-alloc. */
642 /* The `costs' struct records the cost of using a hard register of each class
643 and of using memory for each pseudo. We use this data to set up
644 register class preferences. */
648 int cost[N_REG_CLASSES];
652 /* Record the cost of each class for each pseudo. */
654 static struct costs *costs;
656 /* Initialized once, and used to initialize cost values for each insn. */
658 static struct costs init_cost;
660 /* Record the same data by operand number, accumulated for each alternative
661 in an insn. The contribution to a pseudo is that of the minimum-cost
664 static struct costs op_costs[MAX_RECOG_OPERANDS];
666 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
667 This is available after `regclass' is run. */
669 static char *prefclass;
671 /* altclass[R] is a register class that we should use for allocating
672 pseudo number R if no register in the preferred class is available.
673 If no register in this class is available, memory is preferred.
675 It might appear to be more general to have a bitmask of classes here,
676 but since it is recommended that there be a class corresponding to the
677 union of most major pair of classes, that generality is not required.
679 This is available after `regclass' is run. */
681 static char *altclass;
683 /* Allocated buffers for prefclass and altclass. */
684 static char *prefclass_buffer;
685 static char *altclass_buffer;
687 /* Record the depth of loops that we are in. */
689 static int loop_depth;
691 /* Account for the fact that insns within a loop are executed very commonly,
692 but don't keep doing this as loops go too deep. */
694 static int loop_cost;
696 static rtx scan_one_insn PROTO((rtx, int));
697 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
698 char *, const char **, rtx));
699 static int copy_cost PROTO((rtx, enum machine_mode,
700 enum reg_class, int));
701 static void record_address_regs PROTO((rtx, enum reg_class, int));
702 #ifdef FORBIDDEN_INC_DEC_CLASSES
703 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
705 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
707 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
708 This function is sometimes called before the info has been computed.
709 When that happens, just return GENERAL_REGS, which is innocuous. */
712 reg_preferred_class (regno)
717 return (enum reg_class) prefclass[regno];
721 reg_alternate_class (regno)
727 return (enum reg_class) altclass[regno];
730 /* Initialize some global data for this pass. */
737 init_cost.mem_cost = 10000;
738 for (i = 0; i < N_REG_CLASSES; i++)
739 init_cost.cost[i] = 10000;
741 /* This prevents dump_flow_info from losing if called
742 before regclass is run. */
746 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
747 time it would save code to put a certain register in a certain class.
748 PASS, when nonzero, inhibits some optimizations which need only be done
750 Return the last insn processed, so that the scan can be continued from
754 scan_one_insn (insn, pass)
758 enum rtx_code code = GET_CODE (insn);
759 enum rtx_code pat_code;
760 const char *constraints[MAX_RECOG_OPERANDS];
761 enum machine_mode modes[MAX_RECOG_OPERANDS];
762 char subreg_changes_size[MAX_RECOG_OPERANDS];
766 /* Show that an insn inside a loop is likely to be executed three
767 times more than insns outside a loop. This is much more aggressive
768 than the assumptions made elsewhere and is being tried as an
773 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
774 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
775 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
776 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
781 if (GET_RTX_CLASS (code) != 'i')
784 pat_code = GET_CODE (PATTERN (insn));
786 || pat_code == CLOBBER
787 || pat_code == ASM_INPUT
788 || pat_code == ADDR_VEC
789 || pat_code == ADDR_DIFF_VEC)
792 set = single_set (insn);
795 for (i = 0; i < recog_data.n_operands; i++)
797 constraints[i] = recog_data.constraints[i];
798 modes[i] = recog_data.operand_mode[i];
800 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
802 /* If this insn loads a parameter from its stack slot, then
803 it represents a savings, rather than a cost, if the
804 parameter is stored in memory. Record this fact. */
806 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
807 && GET_CODE (SET_SRC (set)) == MEM
808 && (note = find_reg_note (insn, REG_EQUIV,
810 && GET_CODE (XEXP (note, 0)) == MEM)
812 costs[REGNO (SET_DEST (set))].mem_cost
813 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
816 record_address_regs (XEXP (SET_SRC (set), 0),
817 BASE_REG_CLASS, loop_cost * 2);
821 /* Improve handling of two-address insns such as
822 (set X (ashift CONST Y)) where CONST must be made to
823 match X. Change it into two insns: (set X CONST)
824 (set X (ashift X Y)). If we left this for reloading, it
825 would probably get three insns because X and Y might go
826 in the same place. This prevents X and Y from receiving
829 We can only do this if the modes of operands 0 and 1
830 (which might not be the same) are tieable and we only need
831 do this during our first pass. */
833 if (pass == 0 && optimize
834 && recog_data.n_operands >= 3
835 && recog_data.constraints[1][0] == '0'
836 && recog_data.constraints[1][1] == 0
837 && CONSTANT_P (recog_data.operand[1])
838 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
839 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
840 && GET_CODE (recog_data.operand[0]) == REG
841 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
842 recog_data.operand_mode[1]))
844 rtx previnsn = prev_real_insn (insn);
846 = gen_lowpart (recog_data.operand_mode[1],
847 recog_data.operand[0]);
849 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
851 /* If this insn was the start of a basic block,
852 include the new insn in that block.
853 We need not check for code_label here;
854 while a basic block can start with a code_label,
855 INSN could not be at the beginning of that block. */
856 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
859 for (b = 0; b < n_basic_blocks; b++)
860 if (insn == BLOCK_HEAD (b))
861 BLOCK_HEAD (b) = newinsn;
864 /* This makes one more setting of new insns's dest. */
865 REG_N_SETS (REGNO (recog_data.operand[0]))++;
867 *recog_data.operand_loc[1] = recog_data.operand[0];
868 for (i = recog_data.n_dups - 1; i >= 0; i--)
869 if (recog_data.dup_num[i] == 1)
870 *recog_data.dup_loc[i] = recog_data.operand[0];
872 return PREV_INSN (newinsn);
875 /* If we get here, we are set up to record the costs of all the
876 operands for this insn. Start by initializing the costs.
877 Then handle any address registers. Finally record the desired
878 classes for any pseudos, doing it twice if some pair of
879 operands are commutative. */
881 for (i = 0; i < recog_data.n_operands; i++)
883 op_costs[i] = init_cost;
885 if (GET_CODE (recog_data.operand[i]) == SUBREG)
887 rtx inner = SUBREG_REG (recog_data.operand[i]);
888 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
889 subreg_changes_size[i] = 1;
890 recog_data.operand[i] = inner;
893 if (GET_CODE (recog_data.operand[i]) == MEM)
894 record_address_regs (XEXP (recog_data.operand[i], 0),
895 BASE_REG_CLASS, loop_cost * 2);
896 else if (constraints[i][0] == 'p')
897 record_address_regs (recog_data.operand[i],
898 BASE_REG_CLASS, loop_cost * 2);
901 /* Check for commutative in a separate loop so everything will
902 have been initialized. We must do this even if one operand
903 is a constant--see addsi3 in m68k.md. */
905 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
906 if (constraints[i][0] == '%')
908 const char *xconstraints[MAX_RECOG_OPERANDS];
911 /* Handle commutative operands by swapping the constraints.
912 We assume the modes are the same. */
914 for (j = 0; j < recog_data.n_operands; j++)
915 xconstraints[j] = constraints[j];
917 xconstraints[i] = constraints[i+1];
918 xconstraints[i+1] = constraints[i];
919 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
920 recog_data.operand, modes, subreg_changes_size,
924 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
925 recog_data.operand, modes, subreg_changes_size,
928 /* Now add the cost for each operand to the total costs for
931 for (i = 0; i < recog_data.n_operands; i++)
932 if (GET_CODE (recog_data.operand[i]) == REG
933 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
935 int regno = REGNO (recog_data.operand[i]);
936 struct costs *p = &costs[regno], *q = &op_costs[i];
938 p->mem_cost += q->mem_cost * loop_cost;
939 for (j = 0; j < N_REG_CLASSES; j++)
940 p->cost[j] += q->cost[j] * loop_cost;
946 /* This is a pass of the compiler that scans all instructions
947 and calculates the preferred class for each pseudo-register.
948 This information can be accessed later by calling `reg_preferred_class'.
949 This pass comes just before local register allocation. */
956 #ifdef REGISTER_CONSTRAINTS
963 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
965 #ifdef FORBIDDEN_INC_DEC_CLASSES
967 in_inc_dec = (char *) alloca (nregs);
969 /* Initialize information about which register classes can be used for
970 pseudos that are auto-incremented or auto-decremented. It would
971 seem better to put this in init_reg_sets, but we need to be able
972 to allocate rtx, which we can't do that early. */
974 for (i = 0; i < N_REG_CLASSES; i++)
976 rtx r = gen_rtx_REG (VOIDmode, 0);
980 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
981 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
985 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
986 m = (enum machine_mode) ((int) m + 1))
987 if (HARD_REGNO_MODE_OK (j, m))
991 /* If a register is not directly suitable for an
992 auto-increment or decrement addressing mode and
993 requires secondary reloads, disallow its class from
994 being used in such addresses. */
997 #ifdef SECONDARY_RELOAD_CLASS
998 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1001 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1002 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1005 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1006 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1011 && ! auto_inc_dec_reg_p (r, m))
1012 forbidden_inc_dec_class[i] = 1;
1016 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1018 /* Normally we scan the insns once and determine the best class to use for
1019 each register. However, if -fexpensive_optimizations are on, we do so
1020 twice, the second time using the tentative best classes to guide the
1023 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1025 /* Zero out our accumulation of the cost of each class for each reg. */
1027 bzero ((char *) costs, nregs * sizeof (struct costs));
1029 #ifdef FORBIDDEN_INC_DEC_CLASSES
1030 bzero (in_inc_dec, nregs);
1033 loop_depth = 0, loop_cost = 1;
1035 /* Scan the instructions and record each time it would
1036 save code to put a certain register in a certain class. */
1038 for (insn = f; insn; insn = NEXT_INSN (insn))
1040 insn = scan_one_insn (insn, pass);
1043 /* Now for each register look at how desirable each class is
1044 and find which class is preferred. Store that in
1045 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1046 class any of whose registers is better than memory. */
1050 prefclass = prefclass_buffer;
1051 altclass = altclass_buffer;
1054 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1056 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1057 enum reg_class best = ALL_REGS, alt = NO_REGS;
1058 /* This is an enum reg_class, but we call it an int
1059 to save lots of casts. */
1061 register struct costs *p = &costs[i];
1063 for (class = (int) ALL_REGS - 1; class > 0; class--)
1065 /* Ignore classes that are too small for this operand or
1066 invalid for a operand that was auto-incremented. */
1067 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1068 > reg_class_size[class]
1069 #ifdef FORBIDDEN_INC_DEC_CLASSES
1070 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1074 else if (p->cost[class] < best_cost)
1076 best_cost = p->cost[class];
1077 best = (enum reg_class) class;
1079 else if (p->cost[class] == best_cost)
1080 best = reg_class_subunion[(int)best][class];
1083 /* Record the alternate register class; i.e., a class for which
1084 every register in it is better than using memory. If adding a
1085 class would make a smaller class (i.e., no union of just those
1086 classes exists), skip that class. The major unions of classes
1087 should be provided as a register class. Don't do this if we
1088 will be doing it again later. */
1090 if (pass == 1 || ! flag_expensive_optimizations)
1091 for (class = 0; class < N_REG_CLASSES; class++)
1092 if (p->cost[class] < p->mem_cost
1093 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1094 > reg_class_size[(int) alt])
1095 #ifdef FORBIDDEN_INC_DEC_CLASSES
1096 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1099 alt = reg_class_subunion[(int) alt][class];
1101 /* If we don't add any classes, nothing to try. */
1105 /* We cast to (int) because (char) hits bugs in some compilers. */
1106 prefclass[i] = (int) best;
1107 altclass[i] = (int) alt;
1110 #endif /* REGISTER_CONSTRAINTS */
1115 #ifdef REGISTER_CONSTRAINTS
1117 /* Record the cost of using memory or registers of various classes for
1118 the operands in INSN.
1120 N_ALTS is the number of alternatives.
1122 N_OPS is the number of operands.
1124 OPS is an array of the operands.
1126 MODES are the modes of the operands, in case any are VOIDmode.
1128 CONSTRAINTS are the constraints to use for the operands. This array
1129 is modified by this procedure.
1131 This procedure works alternative by alternative. For each alternative
1132 we assume that we will be able to allocate all pseudos to their ideal
1133 register class and calculate the cost of using that alternative. Then
1134 we compute for each operand that is a pseudo-register, the cost of
1135 having the pseudo allocated to each register class and using it in that
1136 alternative. To this cost is added the cost of the alternative.
1138 The cost of each class for this insn is its lowest cost among all the
1142 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1147 enum machine_mode *modes;
1148 char *subreg_changes_size;
1149 const char **constraints;
1156 /* Process each alternative, each time minimizing an operand's cost with
1157 the cost for each operand in that alternative. */
1159 for (alt = 0; alt < n_alts; alt++)
1161 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1164 enum reg_class classes[MAX_RECOG_OPERANDS];
1167 for (i = 0; i < n_ops; i++)
1169 const char *p = constraints[i];
1171 enum machine_mode mode = modes[i];
1172 int allows_addr = 0;
1177 /* Initially show we know nothing about the register class. */
1178 classes[i] = NO_REGS;
1180 /* If this operand has no constraints at all, we can conclude
1181 nothing about it since anything is valid. */
1185 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1186 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1191 /* If this alternative is only relevant when this operand
1192 matches a previous operand, we do different things depending
1193 on whether this operand is a pseudo-reg or not. We must process
1194 any modifiers for the operand before we can make this test. */
1196 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1199 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1202 classes[i] = classes[j];
1204 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1206 /* If this matches the other operand, we have no added
1208 if (rtx_equal_p (ops[j], op))
1211 /* If we can put the other operand into a register, add to
1212 the cost of this alternative the cost to copy this
1213 operand to the register used for the other operand. */
1215 else if (classes[j] != NO_REGS)
1216 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1218 else if (GET_CODE (ops[j]) != REG
1219 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1221 /* This op is a pseudo but the one it matches is not. */
1223 /* If we can't put the other operand into a register, this
1224 alternative can't be used. */
1226 if (classes[j] == NO_REGS)
1229 /* Otherwise, add to the cost of this alternative the cost
1230 to copy the other operand to the register used for this
1234 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1238 /* The costs of this operand are the same as that of the
1239 other operand. However, if we cannot tie them, this
1240 alternative needs to do a copy, which is one
1243 this_op_costs[i] = this_op_costs[j];
1244 if (REGNO (ops[i]) != REGNO (ops[j])
1245 && ! find_reg_note (insn, REG_DEAD, op))
1248 /* This is in place of ordinary cost computation
1249 for this operand, so skip to the end of the
1250 alternative (should be just one character). */
1251 while (*p && *p++ != ',')
1259 /* Scan all the constraint letters. See if the operand matches
1260 any of the constraints. Collect the valid register classes
1261 and see if this operand accepts memory. */
1263 while (*p && (c = *p++) != ',')
1267 /* Ignore the next letter for this pass. */
1273 case '!': case '#': case '&':
1274 case '0': case '1': case '2': case '3': case '4':
1275 case '5': case '6': case '7': case '8': case '9':
1280 win = address_operand (op, GET_MODE (op));
1281 /* We know this operand is an address, so we want it to be
1282 allocated to a register that can be the base of an
1283 address, ie BASE_REG_CLASS. */
1285 = reg_class_subunion[(int) classes[i]]
1286 [(int) BASE_REG_CLASS];
1289 case 'm': case 'o': case 'V':
1290 /* It doesn't seem worth distinguishing between offsettable
1291 and non-offsettable addresses here. */
1293 if (GET_CODE (op) == MEM)
1298 if (GET_CODE (op) == MEM
1299 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1300 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1305 if (GET_CODE (op) == MEM
1306 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1307 || GET_CODE (XEXP (op, 0)) == POST_INC))
1312 #ifndef REAL_ARITHMETIC
1313 /* Match any floating double constant, but only if
1314 we can examine the bits of it reliably. */
1315 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1316 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1317 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1320 if (GET_CODE (op) == CONST_DOUBLE)
1325 if (GET_CODE (op) == CONST_DOUBLE)
1331 if (GET_CODE (op) == CONST_DOUBLE
1332 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1337 if (GET_CODE (op) == CONST_INT
1338 || (GET_CODE (op) == CONST_DOUBLE
1339 && GET_MODE (op) == VOIDmode))
1343 #ifdef LEGITIMATE_PIC_OPERAND_P
1344 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1351 if (GET_CODE (op) == CONST_INT
1352 || (GET_CODE (op) == CONST_DOUBLE
1353 && GET_MODE (op) == VOIDmode))
1365 if (GET_CODE (op) == CONST_INT
1366 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1374 #ifdef EXTRA_CONSTRAINT
1380 if (EXTRA_CONSTRAINT (op, c))
1386 if (GET_CODE (op) == MEM
1388 #ifdef LEGITIMATE_PIC_OPERAND_P
1389 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1396 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1401 = reg_class_subunion[(int) classes[i]]
1402 [(int) REG_CLASS_FROM_LETTER (c)];
1407 #ifdef CLASS_CANNOT_CHANGE_SIZE
1408 /* If we noted a subreg earlier, and the selected class is a
1409 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1410 if (subreg_changes_size[i]
1411 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1413 == CLASS_CANNOT_CHANGE_SIZE))
1414 classes[i] = NO_REGS;
1417 /* How we account for this operand now depends on whether it is a
1418 pseudo register or not. If it is, we first check if any
1419 register classes are valid. If not, we ignore this alternative,
1420 since we want to assume that all pseudos get allocated for
1421 register preferencing. If some register class is valid, compute
1422 the costs of moving the pseudo into that class. */
1424 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1426 if (classes[i] == NO_REGS)
1428 /* We must always fail if the operand is a REG, but
1429 we did not find a suitable class.
1431 Otherwise we may perform an uninitialized read
1432 from this_op_costs after the `continue' statement
1438 struct costs *pp = &this_op_costs[i];
1440 for (class = 0; class < N_REG_CLASSES; class++)
1441 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1443 /* If the alternative actually allows memory, make things
1444 a bit cheaper since we won't need an extra insn to
1447 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1450 /* If we have assigned a class to this register in our
1451 first pass, add a cost to this alternative corresponding
1452 to what we would add if this register were not in the
1453 appropriate class. */
1457 += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]];
1461 /* Otherwise, if this alternative wins, either because we
1462 have already determined that or if we have a hard register of
1463 the proper class, there is no cost for this alternative. */
1466 || (GET_CODE (op) == REG
1467 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1470 /* If registers are valid, the cost of this alternative includes
1471 copying the object to and/or from a register. */
1473 else if (classes[i] != NO_REGS)
1475 if (recog_data.operand_type[i] != OP_OUT)
1476 alt_cost += copy_cost (op, mode, classes[i], 1);
1478 if (recog_data.operand_type[i] != OP_IN)
1479 alt_cost += copy_cost (op, mode, classes[i], 0);
1482 /* The only other way this alternative can be used is if this is a
1483 constant that could be placed into memory. */
1485 else if (CONSTANT_P (op) && (allows_addr || allows_mem))
1486 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1494 /* Finally, update the costs with the information we've calculated
1495 about this alternative. */
1497 for (i = 0; i < n_ops; i++)
1498 if (GET_CODE (ops[i]) == REG
1499 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1501 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1502 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1504 pp->mem_cost = MIN (pp->mem_cost,
1505 (qq->mem_cost + alt_cost) * scale);
1507 for (class = 0; class < N_REG_CLASSES; class++)
1508 pp->cost[class] = MIN (pp->cost[class],
1509 (qq->cost[class] + alt_cost) * scale);
1513 /* If this insn is a single set copying operand 1 to operand 0
1514 and one is a pseudo with the other a hard reg that is in its
1515 own register class, set the cost of that register class to -1. */
1517 if ((set = single_set (insn)) != 0
1518 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1519 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1520 for (i = 0; i <= 1; i++)
1521 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1523 int regno = REGNO (ops[!i]);
1524 enum machine_mode mode = GET_MODE (ops[!i]);
1528 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1529 && (reg_class_size[(unsigned char)prefclass[regno]]
1530 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1531 op_costs[i].cost[(unsigned char)prefclass[regno]] = -1;
1532 else if (regno < FIRST_PSEUDO_REGISTER)
1533 for (class = 0; class < N_REG_CLASSES; class++)
1534 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1535 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1537 if (reg_class_size[class] == 1)
1538 op_costs[i].cost[class] = -1;
1541 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1543 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1547 if (nr == HARD_REGNO_NREGS(regno,mode))
1548 op_costs[i].cost[class] = -1;
1554 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1555 TO_P is zero) a register of class CLASS in mode MODE.
1557 X must not be a pseudo. */
1560 copy_cost (x, mode, class, to_p)
1562 enum machine_mode mode;
1563 enum reg_class class;
1566 #ifdef HAVE_SECONDARY_RELOADS
1567 enum reg_class secondary_class = NO_REGS;
1570 /* If X is a SCRATCH, there is actually nothing to move since we are
1571 assuming optimal allocation. */
1573 if (GET_CODE (x) == SCRATCH)
1576 /* Get the class we will actually use for a reload. */
1577 class = PREFERRED_RELOAD_CLASS (x, class);
1579 #ifdef HAVE_SECONDARY_RELOADS
1580 /* If we need a secondary reload (we assume here that we are using
1581 the secondary reload as an intermediate, not a scratch register), the
1582 cost is that to load the input into the intermediate register, then
1583 to copy them. We use a special value of TO_P to avoid recursion. */
1585 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1587 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1590 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1592 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1595 if (secondary_class != NO_REGS)
1596 return (move_cost[(int) secondary_class][(int) class]
1597 + copy_cost (x, mode, secondary_class, 2));
1598 #endif /* HAVE_SECONDARY_RELOADS */
1600 /* For memory, use the memory move cost, for (hard) registers, use the
1601 cost to move between the register classes, and use 2 for everything
1602 else (constants). */
1604 if (GET_CODE (x) == MEM || class == NO_REGS)
1605 return MEMORY_MOVE_COST (mode, class, to_p);
1607 else if (GET_CODE (x) == REG)
1608 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1611 /* If this is a constant, we may eventually want to call rtx_cost here. */
1615 /* Record the pseudo registers we must reload into hard registers
1616 in a subexpression of a memory address, X.
1618 CLASS is the class that the register needs to be in and is either
1619 BASE_REG_CLASS or INDEX_REG_CLASS.
1621 SCALE is twice the amount to multiply the cost by (it is twice so we
1622 can represent half-cost adjustments). */
1625 record_address_regs (x, class, scale)
1627 enum reg_class class;
1630 register enum rtx_code code = GET_CODE (x);
1643 /* When we have an address that is a sum,
1644 we must determine whether registers are "base" or "index" regs.
1645 If there is a sum of two registers, we must choose one to be
1646 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1647 to make a good choice most of the time. We only need to do this
1648 on machines that can have two registers in an address and where
1649 the base and index register classes are different.
1651 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1652 that seems bogus since it should only be set when we are sure
1653 the register is being used as a pointer. */
1656 rtx arg0 = XEXP (x, 0);
1657 rtx arg1 = XEXP (x, 1);
1658 register enum rtx_code code0 = GET_CODE (arg0);
1659 register enum rtx_code code1 = GET_CODE (arg1);
1661 /* Look inside subregs. */
1662 if (code0 == SUBREG)
1663 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1664 if (code1 == SUBREG)
1665 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1667 /* If this machine only allows one register per address, it must
1668 be in the first operand. */
1670 if (MAX_REGS_PER_ADDRESS == 1)
1671 record_address_regs (arg0, class, scale);
1673 /* If index and base registers are the same on this machine, just
1674 record registers in any non-constant operands. We assume here,
1675 as well as in the tests below, that all addresses are in
1678 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1680 record_address_regs (arg0, class, scale);
1681 if (! CONSTANT_P (arg1))
1682 record_address_regs (arg1, class, scale);
1685 /* If the second operand is a constant integer, it doesn't change
1686 what class the first operand must be. */
1688 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1689 record_address_regs (arg0, class, scale);
1691 /* If the second operand is a symbolic constant, the first operand
1692 must be an index register. */
1694 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1695 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1697 /* If both operands are registers but one is already a hard register
1698 of index or base class, give the other the class that the hard
1701 #ifdef REG_OK_FOR_BASE_P
1702 else if (code0 == REG && code1 == REG
1703 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1704 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1705 record_address_regs (arg1,
1706 REG_OK_FOR_BASE_P (arg0)
1707 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1709 else if (code0 == REG && code1 == REG
1710 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1711 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1712 record_address_regs (arg0,
1713 REG_OK_FOR_BASE_P (arg1)
1714 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1718 /* If one operand is known to be a pointer, it must be the base
1719 with the other operand the index. Likewise if the other operand
1722 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1725 record_address_regs (arg0, BASE_REG_CLASS, scale);
1726 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1728 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1731 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1732 record_address_regs (arg1, BASE_REG_CLASS, scale);
1735 /* Otherwise, count equal chances that each might be a base
1736 or index register. This case should be rare. */
1740 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1741 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1742 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1743 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1752 /* Double the importance of a pseudo register that is incremented
1753 or decremented, since it would take two extra insns
1754 if it ends up in the wrong place. If the operand is a pseudo,
1755 show it is being used in an INC_DEC context. */
1757 #ifdef FORBIDDEN_INC_DEC_CLASSES
1758 if (GET_CODE (XEXP (x, 0)) == REG
1759 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1760 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1763 record_address_regs (XEXP (x, 0), class, 2 * scale);
1768 register struct costs *pp = &costs[REGNO (x)];
1771 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1773 for (i = 0; i < N_REG_CLASSES; i++)
1774 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1780 register const char *fmt = GET_RTX_FORMAT (code);
1782 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1784 record_address_regs (XEXP (x, i), class, scale);
1789 #ifdef FORBIDDEN_INC_DEC_CLASSES
1791 /* Return 1 if REG is valid as an auto-increment memory reference
1792 to an object of MODE. */
1795 auto_inc_dec_reg_p (reg, mode)
1797 enum machine_mode mode;
1799 if (HAVE_POST_INCREMENT
1800 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1803 if (HAVE_POST_DECREMENT
1804 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1807 if (HAVE_PRE_INCREMENT
1808 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1811 if (HAVE_PRE_DECREMENT
1812 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1819 #endif /* REGISTER_CONSTRAINTS */
1821 static short *renumber = (short *)0;
1822 static size_t regno_allocated = 0;
1824 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1825 reg_scan and flow_analysis that are indexed by the register number. If
1826 NEW_P is non zero, initialize all of the registers, otherwise only
1827 initialize the new registers allocated. The same table is kept from
1828 function to function, only reallocating it when we need more room. If
1829 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1832 allocate_reg_info (num_regs, new_p, renumber_p)
1838 size_t size_renumber;
1839 size_t min = (new_p) ? 0 : reg_n_max;
1840 struct reg_info_data *reg_data;
1841 struct reg_info_data *reg_next;
1843 if (num_regs > regno_allocated)
1845 size_t old_allocated = regno_allocated;
1847 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1848 size_renumber = regno_allocated * sizeof (short);
1852 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1853 renumber = (short *) xmalloc (size_renumber);
1854 prefclass_buffer = (char *) xmalloc (regno_allocated);
1855 altclass_buffer = (char *) xmalloc (regno_allocated);
1860 VARRAY_GROW (reg_n_info, regno_allocated);
1862 if (new_p) /* if we're zapping everything, no need to realloc */
1864 free ((char *)renumber);
1865 free ((char *)prefclass_buffer);
1866 free ((char *)altclass_buffer);
1867 renumber = (short *) xmalloc (size_renumber);
1868 prefclass_buffer = (char *) xmalloc (regno_allocated);
1869 altclass_buffer = (char *) xmalloc (regno_allocated);
1874 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1875 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1878 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1883 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1884 + sizeof (struct reg_info_data) - sizeof (reg_info);
1885 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1886 reg_data->min_index = old_allocated;
1887 reg_data->max_index = regno_allocated - 1;
1888 reg_data->next = reg_info_head;
1889 reg_info_head = reg_data;
1892 reg_n_max = num_regs;
1895 /* Loop through each of the segments allocated for the actual
1896 reg_info pages, and set up the pointers, zero the pages, etc. */
1897 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1899 size_t min_index = reg_data->min_index;
1900 size_t max_index = reg_data->max_index;
1902 reg_next = reg_data->next;
1903 if (min <= max_index)
1905 size_t max = max_index;
1906 size_t local_min = min - min_index;
1909 if (min < min_index)
1911 if (!reg_data->used_p) /* page just allocated with calloc */
1912 reg_data->used_p = 1; /* no need to zero */
1914 bzero ((char *) ®_data->data[local_min],
1915 sizeof (reg_info) * (max - min_index - local_min + 1));
1917 for (i = min_index+local_min; i <= max; i++)
1919 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1920 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1922 prefclass_buffer[i] = (char) NO_REGS;
1923 altclass_buffer[i] = (char) NO_REGS;
1929 /* If {pref,alt}class have already been allocated, update the pointers to
1930 the newly realloced ones. */
1933 prefclass = prefclass_buffer;
1934 altclass = altclass_buffer;
1938 reg_renumber = renumber;
1940 /* Tell the regset code about the new number of registers */
1941 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1944 /* Free up the space allocated by allocate_reg_info. */
1950 struct reg_info_data *reg_data;
1951 struct reg_info_data *reg_next;
1953 VARRAY_FREE (reg_n_info);
1954 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1956 reg_next = reg_data->next;
1957 free ((char *)reg_data);
1960 free (prefclass_buffer);
1961 free (altclass_buffer);
1962 prefclass_buffer = (char *)0;
1963 altclass_buffer = (char *)0;
1964 reg_info_head = (struct reg_info_data *)0;
1965 renumber = (short *)0;
1967 regno_allocated = 0;
1971 /* This is the `regscan' pass of the compiler, run just before cse
1972 and again just before loop.
1974 It finds the first and last use of each pseudo-register
1975 and records them in the vectors regno_first_uid, regno_last_uid
1976 and counts the number of sets in the vector reg_n_sets.
1978 REPEAT is nonzero the second time this is called. */
1980 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1981 Always at least 3, since the combiner could put that many together
1982 and we want this to remain correct for all the remaining passes. */
1987 reg_scan (f, nregs, repeat)
1994 allocate_reg_info (nregs, TRUE, FALSE);
1997 for (insn = f; insn; insn = NEXT_INSN (insn))
1998 if (GET_CODE (insn) == INSN
1999 || GET_CODE (insn) == CALL_INSN
2000 || GET_CODE (insn) == JUMP_INSN)
2002 if (GET_CODE (PATTERN (insn)) == PARALLEL
2003 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2004 max_parallel = XVECLEN (PATTERN (insn), 0);
2005 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2007 if (REG_NOTES (insn))
2008 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2012 /* Update 'regscan' information by looking at the insns
2013 from FIRST to LAST. Some new REGs have been created,
2014 and any REG with number greater than OLD_MAX_REGNO is
2015 such a REG. We only update information for those. */
2018 reg_scan_update(first, last, old_max_regno)
2025 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2027 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2028 if (GET_CODE (insn) == INSN
2029 || GET_CODE (insn) == CALL_INSN
2030 || GET_CODE (insn) == JUMP_INSN)
2032 if (GET_CODE (PATTERN (insn)) == PARALLEL
2033 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2034 max_parallel = XVECLEN (PATTERN (insn), 0);
2035 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2037 if (REG_NOTES (insn))
2038 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2042 /* X is the expression to scan. INSN is the insn it appears in.
2043 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2044 We should only record information for REGs with numbers
2045 greater than or equal to MIN_REGNO. */
2048 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2054 register enum rtx_code code;
2058 code = GET_CODE (x);
2074 register int regno = REGNO (x);
2076 if (regno >= min_regno)
2078 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2080 REGNO_LAST_UID (regno) = INSN_UID (insn);
2081 if (REGNO_FIRST_UID (regno) == 0)
2082 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2089 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2091 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2096 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2100 /* Count a set of the destination if it is a register. */
2101 for (dest = SET_DEST (x);
2102 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2103 || GET_CODE (dest) == ZERO_EXTEND;
2104 dest = XEXP (dest, 0))
2107 if (GET_CODE (dest) == REG
2108 && REGNO (dest) >= min_regno)
2109 REG_N_SETS (REGNO (dest))++;
2111 /* If this is setting a pseudo from another pseudo or the sum of a
2112 pseudo and a constant integer and the other pseudo is known to be
2113 a pointer, set the destination to be a pointer as well.
2115 Likewise if it is setting the destination from an address or from a
2116 value equivalent to an address or to the sum of an address and
2119 But don't do any of this if the pseudo corresponds to a user
2120 variable since it should have already been set as a pointer based
2123 if (GET_CODE (SET_DEST (x)) == REG
2124 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2125 && REGNO (SET_DEST (x)) >= min_regno
2126 /* If the destination pseudo is set more than once, then other
2127 sets might not be to a pointer value (consider access to a
2128 union in two threads of control in the presense of global
2129 optimizations). So only set REGNO_POINTER_FLAG on the destination
2130 pseudo if this is the only set of that pseudo. */
2131 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2132 && ! REG_USERVAR_P (SET_DEST (x))
2133 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2134 && ((GET_CODE (SET_SRC (x)) == REG
2135 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2136 || ((GET_CODE (SET_SRC (x)) == PLUS
2137 || GET_CODE (SET_SRC (x)) == LO_SUM)
2138 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2139 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2140 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2141 || GET_CODE (SET_SRC (x)) == CONST
2142 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2143 || GET_CODE (SET_SRC (x)) == LABEL_REF
2144 || (GET_CODE (SET_SRC (x)) == HIGH
2145 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2146 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2147 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2148 || ((GET_CODE (SET_SRC (x)) == PLUS
2149 || GET_CODE (SET_SRC (x)) == LO_SUM)
2150 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2151 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2152 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2153 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2154 && (GET_CODE (XEXP (note, 0)) == CONST
2155 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2156 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2157 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2159 /* ... fall through ... */
2163 register const char *fmt = GET_RTX_FORMAT (code);
2165 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2168 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2169 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2172 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2173 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2180 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2184 reg_class_subset_p (c1, c2)
2185 register enum reg_class c1;
2186 register enum reg_class c2;
2188 if (c1 == c2) return 1;
2193 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2194 reg_class_contents[(int)c2],
2199 /* Return nonzero if there is a register that is in both C1 and C2. */
2202 reg_classes_intersect_p (c1, c2)
2203 register enum reg_class c1;
2204 register enum reg_class c2;
2211 if (c1 == c2) return 1;
2213 if (c1 == ALL_REGS || c2 == ALL_REGS)
2216 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2217 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2219 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2226 /* Release any memory allocated by register sets. */
2229 regset_release_memory ()
2231 bitmap_release_memory ();