1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
38 #ifndef REGISTER_MOVE_COST
39 #define REGISTER_MOVE_COST(x, y) 2
42 /* If we have auto-increment or auto-decrement and we can have secondary
43 reloads, we are not allowed to use classes requiring secondary
44 reloads for pseudos auto-incremented since reload can't handle it. */
47 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
48 #define FORBIDDEN_INC_DEC_CLASSES
52 /* Register tables used by many passes. */
54 /* Indexed by hard register number, contains 1 for registers
55 that are fixed use (stack pointer, pc, frame pointer, etc.).
56 These are the registers that cannot be used to allocate
57 a pseudo reg whose life does not cross calls. */
59 char fixed_regs[FIRST_PSEUDO_REGISTER];
61 /* Same info as a HARD_REG_SET. */
63 HARD_REG_SET fixed_reg_set;
65 /* Data for initializing the above. */
67 static char initial_fixed_regs[] = FIXED_REGISTERS;
69 /* Indexed by hard register number, contains 1 for registers
70 that are fixed use or are clobbered by function calls.
71 These are the registers that cannot be used to allocate
72 a pseudo reg whose life crosses calls. */
74 char call_used_regs[FIRST_PSEUDO_REGISTER];
76 /* Same info as a HARD_REG_SET. */
78 HARD_REG_SET call_used_reg_set;
80 /* HARD_REG_SET of registers we want to avoid caller saving. */
81 HARD_REG_SET losing_caller_save_reg_set;
83 /* Data for initializing the above. */
85 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
87 /* Indexed by hard register number, contains 1 for registers that are
88 fixed use -- i.e. in fixed_regs -- or a function value return register
89 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
90 registers that cannot hold quantities across calls even if we are
91 willing to save and restore them. */
93 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
95 /* The same info as a HARD_REG_SET. */
97 HARD_REG_SET call_fixed_reg_set;
99 /* Number of non-fixed registers. */
101 int n_non_fixed_regs;
103 /* Indexed by hard register number, contains 1 for registers
104 that are being used for global register decls.
105 These must be exempt from ordinary flow analysis
106 and are also considered fixed. */
108 char global_regs[FIRST_PSEUDO_REGISTER];
110 /* Table of register numbers in the order in which to try to use them. */
111 #ifdef REG_ALLOC_ORDER
112 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
115 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
117 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
119 /* The same information, but as an array of unsigned ints. We copy from
120 these unsigned ints to the table above. We do this so the tm.h files
121 do not have to be aware of the wordsize for machines with <= 64 regs. */
124 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
126 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
127 = REG_CLASS_CONTENTS;
129 /* For each reg class, number of regs it contains. */
131 int reg_class_size[N_REG_CLASSES];
133 /* For each reg class, table listing all the containing classes. */
135 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
137 /* For each reg class, table listing all the classes contained in it. */
139 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
141 /* For each pair of reg classes,
142 a largest reg class contained in their union. */
144 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
146 /* For each pair of reg classes,
147 the smallest reg class containing their union. */
149 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
151 /* Array containing all of the register names */
153 char *reg_names[] = REGISTER_NAMES;
155 /* For each hard register, the widest mode object that it can contain.
156 This will be a MODE_INT mode if the register can hold integers. Otherwise
157 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
160 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
162 /* Maximum cost of moving from a register in one class to a register in
163 another class. Based on REGISTER_MOVE_COST. */
165 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
167 /* Similar, but here we don't have to move if the first index is a subset
168 of the second so in that case the cost is zero. */
170 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
172 #ifdef FORBIDDEN_INC_DEC_CLASSES
174 /* These are the classes that regs which are auto-incremented or decremented
177 static int forbidden_inc_dec_class[N_REG_CLASSES];
179 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
182 static char *in_inc_dec;
184 #endif /* FORBIDDEN_INC_DEC_CLASSES */
186 /* Function called only once to initialize the above data on reg usage.
187 Once this is done, various switches may override. */
194 /* First copy the register information from the initial int form into
197 for (i = 0; i < N_REG_CLASSES; i++)
199 CLEAR_HARD_REG_SET (reg_class_contents[i]);
201 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
202 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
203 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
204 SET_HARD_REG_BIT (reg_class_contents[i], j);
207 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
208 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
209 bzero (global_regs, sizeof global_regs);
211 /* Compute number of hard regs in each class. */
213 bzero ((char *) reg_class_size, sizeof reg_class_size);
214 for (i = 0; i < N_REG_CLASSES; i++)
215 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
216 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
219 /* Initialize the table of subunions.
220 reg_class_subunion[I][J] gets the largest-numbered reg-class
221 that is contained in the union of classes I and J. */
223 for (i = 0; i < N_REG_CLASSES; i++)
225 for (j = 0; j < N_REG_CLASSES; j++)
228 register /* Declare it register if it's a scalar. */
233 COPY_HARD_REG_SET (c, reg_class_contents[i]);
234 IOR_HARD_REG_SET (c, reg_class_contents[j]);
235 for (k = 0; k < N_REG_CLASSES; k++)
237 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
242 /* keep the largest subclass */ /* SPEE 900308 */
243 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
244 reg_class_contents[(int) reg_class_subunion[i][j]],
246 reg_class_subunion[i][j] = (enum reg_class) k;
253 /* Initialize the table of superunions.
254 reg_class_superunion[I][J] gets the smallest-numbered reg-class
255 containing the union of classes I and J. */
257 for (i = 0; i < N_REG_CLASSES; i++)
259 for (j = 0; j < N_REG_CLASSES; j++)
262 register /* Declare it register if it's a scalar. */
267 COPY_HARD_REG_SET (c, reg_class_contents[i]);
268 IOR_HARD_REG_SET (c, reg_class_contents[j]);
269 for (k = 0; k < N_REG_CLASSES; k++)
270 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
273 reg_class_superunion[i][j] = (enum reg_class) k;
277 /* Initialize the tables of subclasses and superclasses of each reg class.
278 First clear the whole table, then add the elements as they are found. */
280 for (i = 0; i < N_REG_CLASSES; i++)
282 for (j = 0; j < N_REG_CLASSES; j++)
284 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
285 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
289 for (i = 0; i < N_REG_CLASSES; i++)
291 if (i == (int) NO_REGS)
294 for (j = i + 1; j < N_REG_CLASSES; j++)
298 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
302 /* Reg class I is a subclass of J.
303 Add J to the table of superclasses of I. */
304 p = ®_class_superclasses[i][0];
305 while (*p != LIM_REG_CLASSES) p++;
306 *p = (enum reg_class) j;
307 /* Add I to the table of superclasses of J. */
308 p = ®_class_subclasses[j][0];
309 while (*p != LIM_REG_CLASSES) p++;
310 *p = (enum reg_class) i;
314 /* Do any additional initialization regsets may need */
315 INIT_ONCE_REG_SET ();
318 /* After switches have been processed, which perhaps alter
319 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
324 register unsigned int i, j;
326 /* This macro allows the fixed or call-used registers
327 to depend on target flags. */
329 #ifdef CONDITIONAL_REGISTER_USAGE
330 CONDITIONAL_REGISTER_USAGE;
333 /* Initialize "constant" tables. */
335 CLEAR_HARD_REG_SET (fixed_reg_set);
336 CLEAR_HARD_REG_SET (call_used_reg_set);
337 CLEAR_HARD_REG_SET (call_fixed_reg_set);
339 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
341 n_non_fixed_regs = 0;
343 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
346 SET_HARD_REG_BIT (fixed_reg_set, i);
350 if (call_used_regs[i])
351 SET_HARD_REG_BIT (call_used_reg_set, i);
352 if (call_fixed_regs[i])
353 SET_HARD_REG_BIT (call_fixed_reg_set, i);
354 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
355 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
358 /* Initialize the move cost table. Find every subset of each class
359 and take the maximum cost of moving any subset to any other. */
361 for (i = 0; i < N_REG_CLASSES; i++)
362 for (j = 0; j < N_REG_CLASSES; j++)
364 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
365 enum reg_class *p1, *p2;
367 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
369 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
371 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
374 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
376 for (p2 = ®_class_subclasses[j][0];
377 *p2 != LIM_REG_CLASSES; p2++)
379 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
382 move_cost[i][j] = cost;
384 if (reg_class_subset_p (i, j))
387 may_move_cost[i][j] = cost;
391 /* Compute the table of register modes.
392 These values are used to record death information for individual registers
393 (as opposed to a multi-register mode). */
400 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
402 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
404 /* If we couldn't find a valid mode, just use the previous mode.
405 ??? One situation in which we need to do this is on the mips where
406 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
407 to use DF mode for the even registers and VOIDmode for the odd
408 (for the cpu models where the odd ones are inaccessible). */
409 if (reg_raw_mode[i] == VOIDmode)
410 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
414 /* Finish initializing the register sets and
415 initialize the register modes. */
420 /* This finishes what was started by init_reg_sets, but couldn't be done
421 until after register usage was specified. */
427 #ifdef HAVE_SECONDARY_RELOADS
428 /* Compute extra cost of moving registers to/from memory due to reloads.
429 Only needed if secondary reloads are required for memory moves. */
431 memory_move_secondary_cost (mode, class, in)
432 enum machine_mode mode;
433 enum reg_class class;
436 enum reg_class altclass;
437 int partial_cost = 0;
440 /* We need a memory reference to feed to SECONDARY... macros. */
441 mem = gen_rtx (MEM, mode, stack_pointer_rtx);
444 #ifdef SECONDARY_INPUT_RELOAD_CLASS
445 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
450 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
451 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
455 if (altclass == NO_REGS)
459 partial_cost = REGISTER_MOVE_COST (altclass, class);
461 partial_cost = REGISTER_MOVE_COST (class, altclass);
463 if (class == altclass)
464 /* This isn't simply a copy-to-temporary situation. Can't guess
465 what it is, so MEMORY_MOVE_COST really ought not to be calling
468 I'm tempted to put in an abort here, but returning this will
469 probably only give poor estimates, which is what we would've
470 had before this code anyways. */
473 /* Check if the secondary reload register will also need a
475 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
479 /* Return a machine mode that is legitimate for hard reg REGNO and large
480 enough to save nregs. If we can't find one, return VOIDmode. */
483 choose_hard_reg_mode (regno, nregs)
487 enum machine_mode found_mode = VOIDmode, mode;
489 /* We first look for the largest integer mode that can be validly
490 held in REGNO. If none, we look for the largest floating-point mode.
491 If we still didn't find a valid mode, try CCmode. */
493 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
495 mode = GET_MODE_WIDER_MODE (mode))
496 if (HARD_REGNO_NREGS (regno, mode) == nregs
497 && HARD_REGNO_MODE_OK (regno, mode))
500 if (found_mode != VOIDmode)
503 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
505 mode = GET_MODE_WIDER_MODE (mode))
506 if (HARD_REGNO_NREGS (regno, mode) == nregs
507 && HARD_REGNO_MODE_OK (regno, mode))
510 if (found_mode != VOIDmode)
513 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
514 && HARD_REGNO_MODE_OK (regno, CCmode))
517 /* We can't find a mode valid for this register. */
521 /* Specify the usage characteristics of the register named NAME.
522 It should be a fixed register if FIXED and a
523 call-used register if CALL_USED. */
526 fix_register (name, fixed, call_used)
528 int fixed, call_used;
532 /* Decode the name and update the primary form of
533 the register info. */
535 if ((i = decode_reg_name (name)) >= 0)
537 fixed_regs[i] = fixed;
538 call_used_regs[i] = call_used;
542 warning ("unknown register name: %s", name);
546 /* Mark register number I as global. */
554 warning ("register used for two global register variables");
558 if (call_used_regs[i] && ! fixed_regs[i])
559 warning ("call-clobbered register used for global register variable");
563 /* If already fixed, nothing else to do. */
567 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
570 SET_HARD_REG_BIT (fixed_reg_set, i);
571 SET_HARD_REG_BIT (call_used_reg_set, i);
572 SET_HARD_REG_BIT (call_fixed_reg_set, i);
575 /* Now the data and code for the `regclass' pass, which happens
576 just before local-alloc. */
578 /* The `costs' struct records the cost of using a hard register of each class
579 and of using memory for each pseudo. We use this data to set up
580 register class preferences. */
584 int cost[N_REG_CLASSES];
588 /* Record the cost of each class for each pseudo. */
590 static struct costs *costs;
592 /* Record the same data by operand number, accumulated for each alternative
593 in an insn. The contribution to a pseudo is that of the minimum-cost
596 static struct costs op_costs[MAX_RECOG_OPERANDS];
598 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
599 This is available after `regclass' is run. */
601 static char *prefclass;
603 /* altclass[R] is a register class that we should use for allocating
604 pseudo number R if no register in the preferred class is available.
605 If no register in this class is available, memory is preferred.
607 It might appear to be more general to have a bitmask of classes here,
608 but since it is recommended that there be a class corresponding to the
609 union of most major pair of classes, that generality is not required.
611 This is available after `regclass' is run. */
613 static char *altclass;
615 /* Record the depth of loops that we are in. */
617 static int loop_depth;
619 /* Account for the fact that insns within a loop are executed very commonly,
620 but don't keep doing this as loops go too deep. */
622 static int loop_cost;
624 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
626 static int copy_cost PROTO((rtx, enum machine_mode,
627 enum reg_class, int));
628 static void record_address_regs PROTO((rtx, enum reg_class, int));
629 #ifdef FORBIDDEN_INC_DEC_CLASSES
630 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
632 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
634 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
635 This function is sometimes called before the info has been computed.
636 When that happens, just return GENERAL_REGS, which is innocuous. */
639 reg_preferred_class (regno)
644 return (enum reg_class) prefclass[regno];
648 reg_alternate_class (regno)
654 return (enum reg_class) altclass[regno];
657 /* This prevents dump_flow_info from losing if called
658 before regclass is run. */
666 /* This is a pass of the compiler that scans all instructions
667 and calculates the preferred class for each pseudo-register.
668 This information can be accessed later by calling `reg_preferred_class'.
669 This pass comes just before local register allocation. */
676 #ifdef REGISTER_CONSTRAINTS
679 struct costs init_cost;
685 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
687 #ifdef FORBIDDEN_INC_DEC_CLASSES
689 in_inc_dec = (char *) alloca (nregs);
691 /* Initialize information about which register classes can be used for
692 pseudos that are auto-incremented or auto-decremented. It would
693 seem better to put this in init_reg_sets, but we need to be able
694 to allocate rtx, which we can't do that early. */
696 for (i = 0; i < N_REG_CLASSES; i++)
698 rtx r = gen_rtx_REG (VOIDmode, 0);
701 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
702 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
706 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
707 m = (enum machine_mode) ((int) m + 1))
708 if (HARD_REGNO_MODE_OK (j, m))
712 /* If a register is not directly suitable for an
713 auto-increment or decrement addressing mode and
714 requires secondary reloads, disallow its class from
715 being used in such addresses. */
718 #ifdef SECONDARY_RELOAD_CLASS
719 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
722 #ifdef SECONDARY_INPUT_RELOAD_CLASS
723 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
726 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
727 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
732 && ! auto_inc_dec_reg_p (r, m))
733 forbidden_inc_dec_class[i] = 1;
737 #endif /* FORBIDDEN_INC_DEC_CLASSES */
739 init_cost.mem_cost = 10000;
740 for (i = 0; i < N_REG_CLASSES; i++)
741 init_cost.cost[i] = 10000;
743 /* Normally we scan the insns once and determine the best class to use for
744 each register. However, if -fexpensive_optimizations are on, we do so
745 twice, the second time using the tentative best classes to guide the
748 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
750 /* Zero out our accumulation of the cost of each class for each reg. */
752 bzero ((char *) costs, nregs * sizeof (struct costs));
754 #ifdef FORBIDDEN_INC_DEC_CLASSES
755 bzero (in_inc_dec, nregs);
758 loop_depth = 0, loop_cost = 1;
760 /* Scan the instructions and record each time it would
761 save code to put a certain register in a certain class. */
763 for (insn = f; insn; insn = NEXT_INSN (insn))
765 char *constraints[MAX_RECOG_OPERANDS];
766 enum machine_mode modes[MAX_RECOG_OPERANDS];
770 /* Show that an insn inside a loop is likely to be executed three
771 times more than insns outside a loop. This is much more aggressive
772 than the assumptions made elsewhere and is being tried as an
775 if (GET_CODE (insn) == NOTE
776 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
777 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
778 else if (GET_CODE (insn) == NOTE
779 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
780 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
782 else if ((GET_CODE (insn) == INSN
783 && GET_CODE (PATTERN (insn)) != USE
784 && GET_CODE (PATTERN (insn)) != CLOBBER
785 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
786 || (GET_CODE (insn) == JUMP_INSN
787 && GET_CODE (PATTERN (insn)) != ADDR_VEC
788 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
789 || GET_CODE (insn) == CALL_INSN)
791 if (GET_CODE (insn) == INSN
792 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
794 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
796 nalternatives = (noperands == 0 ? 0
797 : n_occurrences (',', constraints[0]) + 1);
801 int insn_code_number = recog_memoized (insn);
804 set = single_set (insn);
807 nalternatives = insn_n_alternatives[insn_code_number];
808 noperands = insn_n_operands[insn_code_number];
810 /* If this insn loads a parameter from its stack slot, then
811 it represents a savings, rather than a cost, if the
812 parameter is stored in memory. Record this fact. */
814 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
815 && GET_CODE (SET_SRC (set)) == MEM
816 && (note = find_reg_note (insn, REG_EQUIV,
818 && GET_CODE (XEXP (note, 0)) == MEM)
820 costs[REGNO (SET_DEST (set))].mem_cost
821 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
824 record_address_regs (XEXP (SET_SRC (set), 0),
825 BASE_REG_CLASS, loop_cost * 2);
829 /* Improve handling of two-address insns such as
830 (set X (ashift CONST Y)) where CONST must be made to
831 match X. Change it into two insns: (set X CONST)
832 (set X (ashift X Y)). If we left this for reloading, it
833 would probably get three insns because X and Y might go
834 in the same place. This prevents X and Y from receiving
837 We can only do this if the modes of operands 0 and 1
838 (which might not be the same) are tieable and we only need
839 do this during our first pass. */
841 if (pass == 0 && optimize
843 && insn_operand_constraint[insn_code_number][1][0] == '0'
844 && insn_operand_constraint[insn_code_number][1][1] == 0
845 && CONSTANT_P (recog_operand[1])
846 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
847 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
848 && GET_CODE (recog_operand[0]) == REG
849 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
850 insn_operand_mode[insn_code_number][1]))
852 rtx previnsn = prev_real_insn (insn);
854 = gen_lowpart (insn_operand_mode[insn_code_number][1],
857 = emit_insn_before (gen_move_insn (dest,
861 /* If this insn was the start of a basic block,
862 include the new insn in that block.
863 We need not check for code_label here;
864 while a basic block can start with a code_label,
865 INSN could not be at the beginning of that block. */
866 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
869 for (b = 0; b < n_basic_blocks; b++)
870 if (insn == basic_block_head[b])
871 basic_block_head[b] = newinsn;
874 /* This makes one more setting of new insns's dest. */
875 REG_N_SETS (REGNO (recog_operand[0]))++;
877 *recog_operand_loc[1] = recog_operand[0];
878 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
879 if (recog_dup_num[i] == 1)
880 *recog_dup_loc[i] = recog_operand[0];
882 insn = PREV_INSN (newinsn);
886 for (i = 0; i < noperands; i++)
889 = insn_operand_constraint[insn_code_number][i];
890 modes[i] = insn_operand_mode[insn_code_number][i];
894 /* If we get here, we are set up to record the costs of all the
895 operands for this insn. Start by initializing the costs.
896 Then handle any address registers. Finally record the desired
897 classes for any pseudos, doing it twice if some pair of
898 operands are commutative. */
900 for (i = 0; i < noperands; i++)
902 op_costs[i] = init_cost;
904 if (GET_CODE (recog_operand[i]) == SUBREG)
905 recog_operand[i] = SUBREG_REG (recog_operand[i]);
907 if (GET_CODE (recog_operand[i]) == MEM)
908 record_address_regs (XEXP (recog_operand[i], 0),
909 BASE_REG_CLASS, loop_cost * 2);
910 else if (constraints[i][0] == 'p')
911 record_address_regs (recog_operand[i],
912 BASE_REG_CLASS, loop_cost * 2);
915 /* Check for commutative in a separate loop so everything will
916 have been initialized. We must do this even if one operand
917 is a constant--see addsi3 in m68k.md. */
919 for (i = 0; i < noperands - 1; i++)
920 if (constraints[i][0] == '%')
922 char *xconstraints[MAX_RECOG_OPERANDS];
925 /* Handle commutative operands by swapping the constraints.
926 We assume the modes are the same. */
928 for (j = 0; j < noperands; j++)
929 xconstraints[j] = constraints[j];
931 xconstraints[i] = constraints[i+1];
932 xconstraints[i+1] = constraints[i];
933 record_reg_classes (nalternatives, noperands,
934 recog_operand, modes, xconstraints,
938 record_reg_classes (nalternatives, noperands, recog_operand,
939 modes, constraints, insn);
941 /* Now add the cost for each operand to the total costs for
944 for (i = 0; i < noperands; i++)
945 if (GET_CODE (recog_operand[i]) == REG
946 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
948 int regno = REGNO (recog_operand[i]);
949 struct costs *p = &costs[regno], *q = &op_costs[i];
951 p->mem_cost += q->mem_cost * loop_cost;
952 for (j = 0; j < N_REG_CLASSES; j++)
953 p->cost[j] += q->cost[j] * loop_cost;
958 /* Now for each register look at how desirable each class is
959 and find which class is preferred. Store that in
960 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
961 class any of whose registers is better than memory. */
965 prefclass = (char *) oballoc (nregs);
966 altclass = (char *) oballoc (nregs);
969 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
971 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
972 enum reg_class best = ALL_REGS, alt = NO_REGS;
973 /* This is an enum reg_class, but we call it an int
974 to save lots of casts. */
976 register struct costs *p = &costs[i];
978 for (class = (int) ALL_REGS - 1; class > 0; class--)
980 /* Ignore classes that are too small for this operand or
981 invalid for a operand that was auto-incremented. */
982 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
983 > reg_class_size[class]
984 #ifdef FORBIDDEN_INC_DEC_CLASSES
985 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
989 else if (p->cost[class] < best_cost)
991 best_cost = p->cost[class];
992 best = (enum reg_class) class;
994 else if (p->cost[class] == best_cost)
995 best = reg_class_subunion[(int)best][class];
998 /* Record the alternate register class; i.e., a class for which
999 every register in it is better than using memory. If adding a
1000 class would make a smaller class (i.e., no union of just those
1001 classes exists), skip that class. The major unions of classes
1002 should be provided as a register class. Don't do this if we
1003 will be doing it again later. */
1005 if (pass == 1 || ! flag_expensive_optimizations)
1006 for (class = 0; class < N_REG_CLASSES; class++)
1007 if (p->cost[class] < p->mem_cost
1008 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1009 > reg_class_size[(int) alt])
1010 #ifdef FORBIDDEN_INC_DEC_CLASSES
1011 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1014 alt = reg_class_subunion[(int) alt][class];
1016 /* If we don't add any classes, nothing to try. */
1020 /* We cast to (int) because (char) hits bugs in some compilers. */
1021 prefclass[i] = (int) best;
1022 altclass[i] = (int) alt;
1025 #endif /* REGISTER_CONSTRAINTS */
1028 #ifdef REGISTER_CONSTRAINTS
1030 /* Record the cost of using memory or registers of various classes for
1031 the operands in INSN.
1033 N_ALTS is the number of alternatives.
1035 N_OPS is the number of operands.
1037 OPS is an array of the operands.
1039 MODES are the modes of the operands, in case any are VOIDmode.
1041 CONSTRAINTS are the constraints to use for the operands. This array
1042 is modified by this procedure.
1044 This procedure works alternative by alternative. For each alternative
1045 we assume that we will be able to allocate all pseudos to their ideal
1046 register class and calculate the cost of using that alternative. Then
1047 we compute for each operand that is a pseudo-register, the cost of
1048 having the pseudo allocated to each register class and using it in that
1049 alternative. To this cost is added the cost of the alternative.
1051 The cost of each class for this insn is its lowest cost among all the
1055 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1059 enum machine_mode *modes;
1064 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1068 /* By default, each operand is an input operand. */
1070 for (i = 0; i < n_ops; i++)
1071 op_types[i] = OP_READ;
1073 /* Process each alternative, each time minimizing an operand's cost with
1074 the cost for each operand in that alternative. */
1076 for (alt = 0; alt < n_alts; alt++)
1078 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1081 enum reg_class classes[MAX_RECOG_OPERANDS];
1084 for (i = 0; i < n_ops; i++)
1086 char *p = constraints[i];
1088 enum machine_mode mode = modes[i];
1093 /* If this operand has no constraints at all, we can conclude
1094 nothing about it since anything is valid. */
1098 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1099 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1107 /* If this alternative is only relevant when this operand
1108 matches a previous operand, we do different things depending
1109 on whether this operand is a pseudo-reg or not. */
1111 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1114 classes[i] = classes[j];
1116 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1118 /* If this matches the other operand, we have no added
1120 if (rtx_equal_p (ops[j], op))
1123 /* If we can put the other operand into a register, add to
1124 the cost of this alternative the cost to copy this
1125 operand to the register used for the other operand. */
1127 else if (classes[j] != NO_REGS)
1128 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1130 else if (GET_CODE (ops[j]) != REG
1131 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1133 /* This op is a pseudo but the one it matches is not. */
1135 /* If we can't put the other operand into a register, this
1136 alternative can't be used. */
1138 if (classes[j] == NO_REGS)
1141 /* Otherwise, add to the cost of this alternative the cost
1142 to copy the other operand to the register used for this
1146 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1150 /* The costs of this operand are the same as that of the
1151 other operand. However, if we cannot tie them, this
1152 alternative needs to do a copy, which is one
1155 this_op_costs[i] = this_op_costs[j];
1156 if (REGNO (ops[i]) != REGNO (ops[j])
1157 && ! find_reg_note (insn, REG_DEAD, op))
1160 /* This is in place of ordinary cost computation
1161 for this operand, so skip to the end of the
1162 alternative (should be just one character). */
1163 while (*p && *p++ != ',')
1171 /* Scan all the constraint letters. See if the operand matches
1172 any of the constraints. Collect the valid register classes
1173 and see if this operand accepts memory. */
1175 classes[i] = NO_REGS;
1176 while (*p && (c = *p++) != ',')
1180 op_types[i] = OP_WRITE;
1184 op_types[i] = OP_READ_WRITE;
1188 /* Ignore the next letter for this pass. */
1193 case '?': case '!': case '#':
1195 case '0': case '1': case '2': case '3': case '4':
1199 case 'm': case 'o': case 'V':
1200 /* It doesn't seem worth distinguishing between offsettable
1201 and non-offsettable addresses here. */
1203 if (GET_CODE (op) == MEM)
1208 if (GET_CODE (op) == MEM
1209 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1210 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1215 if (GET_CODE (op) == MEM
1216 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1217 || GET_CODE (XEXP (op, 0)) == POST_INC))
1222 #ifndef REAL_ARITHMETIC
1223 /* Match any floating double constant, but only if
1224 we can examine the bits of it reliably. */
1225 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1226 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1227 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1230 if (GET_CODE (op) == CONST_DOUBLE)
1235 if (GET_CODE (op) == CONST_DOUBLE)
1241 if (GET_CODE (op) == CONST_DOUBLE
1242 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1247 if (GET_CODE (op) == CONST_INT
1248 || (GET_CODE (op) == CONST_DOUBLE
1249 && GET_MODE (op) == VOIDmode))
1253 #ifdef LEGITIMATE_PIC_OPERAND_P
1254 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1261 if (GET_CODE (op) == CONST_INT
1262 || (GET_CODE (op) == CONST_DOUBLE
1263 && GET_MODE (op) == VOIDmode))
1275 if (GET_CODE (op) == CONST_INT
1276 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1284 #ifdef EXTRA_CONSTRAINT
1290 if (EXTRA_CONSTRAINT (op, c))
1296 if (GET_CODE (op) == MEM
1298 #ifdef LEGITIMATE_PIC_OPERAND_P
1299 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1306 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1311 = reg_class_subunion[(int) classes[i]]
1312 [(int) REG_CLASS_FROM_LETTER (c)];
1317 /* How we account for this operand now depends on whether it is a
1318 pseudo register or not. If it is, we first check if any
1319 register classes are valid. If not, we ignore this alternative,
1320 since we want to assume that all pseudos get allocated for
1321 register preferencing. If some register class is valid, compute
1322 the costs of moving the pseudo into that class. */
1324 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1326 if (classes[i] == NO_REGS)
1330 struct costs *pp = &this_op_costs[i];
1332 for (class = 0; class < N_REG_CLASSES; class++)
1333 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1335 /* If the alternative actually allows memory, make things
1336 a bit cheaper since we won't need an extra insn to
1339 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1342 /* If we have assigned a class to this register in our
1343 first pass, add a cost to this alternative corresponding
1344 to what we would add if this register were not in the
1345 appropriate class. */
1349 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1353 /* Otherwise, if this alternative wins, either because we
1354 have already determined that or if we have a hard register of
1355 the proper class, there is no cost for this alternative. */
1358 || (GET_CODE (op) == REG
1359 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1362 /* If registers are valid, the cost of this alternative includes
1363 copying the object to and/or from a register. */
1365 else if (classes[i] != NO_REGS)
1367 if (op_types[i] != OP_WRITE)
1368 alt_cost += copy_cost (op, mode, classes[i], 1);
1370 if (op_types[i] != OP_READ)
1371 alt_cost += copy_cost (op, mode, classes[i], 0);
1374 /* The only other way this alternative can be used is if this is a
1375 constant that could be placed into memory. */
1377 else if (CONSTANT_P (op) && allows_mem)
1378 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1386 /* Finally, update the costs with the information we've calculated
1387 about this alternative. */
1389 for (i = 0; i < n_ops; i++)
1390 if (GET_CODE (ops[i]) == REG
1391 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1393 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1394 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1396 pp->mem_cost = MIN (pp->mem_cost,
1397 (qq->mem_cost + alt_cost) * scale);
1399 for (class = 0; class < N_REG_CLASSES; class++)
1400 pp->cost[class] = MIN (pp->cost[class],
1401 (qq->cost[class] + alt_cost) * scale);
1405 /* If this insn is a single set copying operand 1 to operand 0
1406 and one is a pseudo with the other a hard reg that is in its
1407 own register class, set the cost of that register class to -1. */
1409 if ((set = single_set (insn)) != 0
1410 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1411 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1412 for (i = 0; i <= 1; i++)
1413 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1415 int regno = REGNO (ops[!i]);
1416 enum machine_mode mode = GET_MODE (ops[!i]);
1420 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1421 && (reg_class_size[prefclass[regno]]
1422 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1423 op_costs[i].cost[prefclass[regno]] = -1;
1424 else if (regno < FIRST_PSEUDO_REGISTER)
1425 for (class = 0; class < N_REG_CLASSES; class++)
1426 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1427 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1429 if (reg_class_size[class] == 1)
1430 op_costs[i].cost[class] = -1;
1433 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1435 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1439 if (nr == HARD_REGNO_NREGS(regno,mode))
1440 op_costs[i].cost[class] = -1;
1446 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1447 TO_P is zero) a register of class CLASS in mode MODE.
1449 X must not be a pseudo. */
1452 copy_cost (x, mode, class, to_p)
1454 enum machine_mode mode;
1455 enum reg_class class;
1458 #ifdef HAVE_SECONDARY_RELOADS
1459 enum reg_class secondary_class = NO_REGS;
1462 /* If X is a SCRATCH, there is actually nothing to move since we are
1463 assuming optimal allocation. */
1465 if (GET_CODE (x) == SCRATCH)
1468 /* Get the class we will actually use for a reload. */
1469 class = PREFERRED_RELOAD_CLASS (x, class);
1471 #ifdef HAVE_SECONDARY_RELOADS
1472 /* If we need a secondary reload (we assume here that we are using
1473 the secondary reload as an intermediate, not a scratch register), the
1474 cost is that to load the input into the intermediate register, then
1475 to copy them. We use a special value of TO_P to avoid recursion. */
1477 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1479 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1482 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1484 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1487 if (secondary_class != NO_REGS)
1488 return (move_cost[(int) secondary_class][(int) class]
1489 + copy_cost (x, mode, secondary_class, 2));
1490 #endif /* HAVE_SECONDARY_RELOADS */
1492 /* For memory, use the memory move cost, for (hard) registers, use the
1493 cost to move between the register classes, and use 2 for everything
1494 else (constants). */
1496 if (GET_CODE (x) == MEM || class == NO_REGS)
1497 return MEMORY_MOVE_COST (mode, class, to_p);
1499 else if (GET_CODE (x) == REG)
1500 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1503 /* If this is a constant, we may eventually want to call rtx_cost here. */
1507 /* Record the pseudo registers we must reload into hard registers
1508 in a subexpression of a memory address, X.
1510 CLASS is the class that the register needs to be in and is either
1511 BASE_REG_CLASS or INDEX_REG_CLASS.
1513 SCALE is twice the amount to multiply the cost by (it is twice so we
1514 can represent half-cost adjustments). */
1517 record_address_regs (x, class, scale)
1519 enum reg_class class;
1522 register enum rtx_code code = GET_CODE (x);
1535 /* When we have an address that is a sum,
1536 we must determine whether registers are "base" or "index" regs.
1537 If there is a sum of two registers, we must choose one to be
1538 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1539 to make a good choice most of the time. We only need to do this
1540 on machines that can have two registers in an address and where
1541 the base and index register classes are different.
1543 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1544 that seems bogus since it should only be set when we are sure
1545 the register is being used as a pointer. */
1548 rtx arg0 = XEXP (x, 0);
1549 rtx arg1 = XEXP (x, 1);
1550 register enum rtx_code code0 = GET_CODE (arg0);
1551 register enum rtx_code code1 = GET_CODE (arg1);
1553 /* Look inside subregs. */
1554 if (code0 == SUBREG)
1555 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1556 if (code1 == SUBREG)
1557 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1559 /* If this machine only allows one register per address, it must
1560 be in the first operand. */
1562 if (MAX_REGS_PER_ADDRESS == 1)
1563 record_address_regs (arg0, class, scale);
1565 /* If index and base registers are the same on this machine, just
1566 record registers in any non-constant operands. We assume here,
1567 as well as in the tests below, that all addresses are in
1570 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1572 record_address_regs (arg0, class, scale);
1573 if (! CONSTANT_P (arg1))
1574 record_address_regs (arg1, class, scale);
1577 /* If the second operand is a constant integer, it doesn't change
1578 what class the first operand must be. */
1580 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1581 record_address_regs (arg0, class, scale);
1583 /* If the second operand is a symbolic constant, the first operand
1584 must be an index register. */
1586 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1587 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1589 /* If both operands are registers but one is already a hard register
1590 of index or base class, give the other the class that the hard
1593 #ifdef REG_OK_FOR_BASE_P
1594 else if (code0 == REG && code1 == REG
1595 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1596 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1597 record_address_regs (arg1,
1598 REG_OK_FOR_BASE_P (arg0)
1599 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1601 else if (code0 == REG && code1 == REG
1602 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1603 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1604 record_address_regs (arg0,
1605 REG_OK_FOR_BASE_P (arg1)
1606 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1610 /* If one operand is known to be a pointer, it must be the base
1611 with the other operand the index. Likewise if the other operand
1614 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1617 record_address_regs (arg0, BASE_REG_CLASS, scale);
1618 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1620 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1623 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1624 record_address_regs (arg1, BASE_REG_CLASS, scale);
1627 /* Otherwise, count equal chances that each might be a base
1628 or index register. This case should be rare. */
1632 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1633 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1634 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1635 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1644 /* Double the importance of a pseudo register that is incremented
1645 or decremented, since it would take two extra insns
1646 if it ends up in the wrong place. If the operand is a pseudo,
1647 show it is being used in an INC_DEC context. */
1649 #ifdef FORBIDDEN_INC_DEC_CLASSES
1650 if (GET_CODE (XEXP (x, 0)) == REG
1651 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1652 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1655 record_address_regs (XEXP (x, 0), class, 2 * scale);
1660 register struct costs *pp = &costs[REGNO (x)];
1663 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1665 for (i = 0; i < N_REG_CLASSES; i++)
1666 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1672 register char *fmt = GET_RTX_FORMAT (code);
1674 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1676 record_address_regs (XEXP (x, i), class, scale);
1681 #ifdef FORBIDDEN_INC_DEC_CLASSES
1683 /* Return 1 if REG is valid as an auto-increment memory reference
1684 to an object of MODE. */
1687 auto_inc_dec_reg_p (reg, mode)
1689 enum machine_mode mode;
1691 #ifdef HAVE_POST_INCREMENT
1692 if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1696 #ifdef HAVE_POST_DECREMENT
1697 if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1701 #ifdef HAVE_PRE_INCREMENT
1702 if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1706 #ifdef HAVE_PRE_DECREMENT
1707 if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1715 #endif /* REGISTER_CONSTRAINTS */
1717 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1718 reg_scan and flow_analysis that are indexed by the register number. If
1719 NEW_P is non zero, initialize all of the registers, otherwise only
1720 initialize the new registers allocated. The same table is kept from
1721 function to function, only reallocating it when we need more room. If
1722 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1725 allocate_reg_info (num_regs, new_p, renumber_p)
1730 static int regno_allocated = 0;
1731 static int regno_max = 0;
1732 static short *renumber = (short *)0;
1736 int min = (new_p) ? 0 : regno_max;
1738 /* If this message come up, and you want to fix it, then all of the tables
1739 like reg_renumber, etc. that use short will have to be found and lengthed
1740 to int or HOST_WIDE_INT. */
1742 /* Free up all storage allocated */
1747 free ((char *)reg_n_info);
1748 free ((char *)renumber);
1749 reg_n_info = (reg_info *)0;
1750 renumber = (short *)0;
1752 regno_allocated = 0;
1757 if (num_regs > regno_allocated)
1759 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1760 size_info = regno_allocated * sizeof (reg_info);
1761 size_renumber = regno_allocated * sizeof (short);
1765 reg_n_info = (reg_info *) xmalloc (size_info);
1766 renumber = (short *) xmalloc (size_renumber);
1769 else if (new_p) /* if we're zapping everything, no need to realloc */
1771 free ((char *)reg_n_info);
1772 free ((char *)renumber);
1773 reg_n_info = (reg_info *) xmalloc (size_info);
1774 renumber = (short *) xmalloc (size_renumber);
1779 reg_n_info = (reg_info *) xrealloc ((char *)reg_n_info, size_info);
1780 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1786 bzero ((char *) ®_n_info[min], (num_regs - min) * sizeof (reg_info));
1787 for (i = min; i < num_regs; i++)
1789 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1795 reg_renumber = renumber;
1797 /* Tell the regset code about the new number of registers */
1798 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1800 regno_max = num_regs;
1804 /* This is the `regscan' pass of the compiler, run just before cse
1805 and again just before loop.
1807 It finds the first and last use of each pseudo-register
1808 and records them in the vectors regno_first_uid, regno_last_uid
1809 and counts the number of sets in the vector reg_n_sets.
1811 REPEAT is nonzero the second time this is called. */
1813 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1814 Always at least 3, since the combiner could put that many together
1815 and we want this to remain correct for all the remaining passes. */
1820 reg_scan (f, nregs, repeat)
1827 allocate_reg_info (nregs, TRUE, FALSE);
1830 for (insn = f; insn; insn = NEXT_INSN (insn))
1831 if (GET_CODE (insn) == INSN
1832 || GET_CODE (insn) == CALL_INSN
1833 || GET_CODE (insn) == JUMP_INSN)
1835 if (GET_CODE (PATTERN (insn)) == PARALLEL
1836 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1837 max_parallel = XVECLEN (PATTERN (insn), 0);
1838 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1840 if (REG_NOTES (insn))
1841 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1845 /* X is the expression to scan. INSN is the insn it appears in.
1846 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1849 reg_scan_mark_refs (x, insn, note_flag)
1854 register enum rtx_code code = GET_CODE (x);
1873 register int regno = REGNO (x);
1875 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
1877 REGNO_LAST_UID (regno) = INSN_UID (insn);
1878 if (REGNO_FIRST_UID (regno) == 0)
1879 REGNO_FIRST_UID (regno) = INSN_UID (insn);
1885 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1887 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1892 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1896 /* Count a set of the destination if it is a register. */
1897 for (dest = SET_DEST (x);
1898 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1899 || GET_CODE (dest) == ZERO_EXTEND;
1900 dest = XEXP (dest, 0))
1903 if (GET_CODE (dest) == REG)
1904 REG_N_SETS (REGNO (dest))++;
1906 /* If this is setting a pseudo from another pseudo or the sum of a
1907 pseudo and a constant integer and the other pseudo is known to be
1908 a pointer, set the destination to be a pointer as well.
1910 Likewise if it is setting the destination from an address or from a
1911 value equivalent to an address or to the sum of an address and
1914 But don't do any of this if the pseudo corresponds to a user
1915 variable since it should have already been set as a pointer based
1918 if (GET_CODE (SET_DEST (x)) == REG
1919 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
1920 && ! REG_USERVAR_P (SET_DEST (x))
1921 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
1922 && ((GET_CODE (SET_SRC (x)) == REG
1923 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
1924 || ((GET_CODE (SET_SRC (x)) == PLUS
1925 || GET_CODE (SET_SRC (x)) == LO_SUM)
1926 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1927 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
1928 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
1929 || GET_CODE (SET_SRC (x)) == CONST
1930 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
1931 || GET_CODE (SET_SRC (x)) == LABEL_REF
1932 || (GET_CODE (SET_SRC (x)) == HIGH
1933 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
1934 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
1935 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
1936 || ((GET_CODE (SET_SRC (x)) == PLUS
1937 || GET_CODE (SET_SRC (x)) == LO_SUM)
1938 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
1939 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
1940 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
1941 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
1942 && (GET_CODE (XEXP (note, 0)) == CONST
1943 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
1944 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
1945 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
1947 /* ... fall through ... */
1951 register char *fmt = GET_RTX_FORMAT (code);
1953 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1956 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
1957 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1960 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1961 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
1968 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1972 reg_class_subset_p (c1, c2)
1973 register enum reg_class c1;
1974 register enum reg_class c2;
1976 if (c1 == c2) return 1;
1981 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1982 reg_class_contents[(int)c2],
1987 /* Return nonzero if there is a register that is in both C1 and C2. */
1990 reg_classes_intersect_p (c1, c2)
1991 register enum reg_class c1;
1992 register enum reg_class c2;
1999 if (c1 == c2) return 1;
2001 if (c1 == ALL_REGS || c2 == ALL_REGS)
2004 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2005 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2007 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2014 /* Release any memory allocated by register sets. */
2017 regset_release_memory ()
2019 if (basic_block_live_at_start)
2021 free_regset_vector (basic_block_live_at_start, n_basic_blocks);
2022 basic_block_live_at_start = 0;
2025 FREE_REG_SET (regs_live_at_setjmp);
2026 bitmap_release_memory ();