1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
28 #include "hard-reg-set.h"
30 #include "basic-block.h"
32 #include "insn-config.h"
38 #ifndef REGISTER_MOVE_COST
39 #define REGISTER_MOVE_COST(x, y) 2
42 #ifndef MEMORY_MOVE_COST
43 #define MEMORY_MOVE_COST(x) 4
46 /* If we have auto-increment or auto-decrement and we can have secondary
47 reloads, we are not allowed to use classes requiring secondary
48 reloads for pseudos auto-incremented since reload can't handle it. */
51 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
52 #define FORBIDDEN_INC_DEC_CLASSES
56 /* Register tables used by many passes. */
58 /* Indexed by hard register number, contains 1 for registers
59 that are fixed use (stack pointer, pc, frame pointer, etc.).
60 These are the registers that cannot be used to allocate
61 a pseudo reg whose life does not cross calls. */
63 char fixed_regs[FIRST_PSEUDO_REGISTER];
65 /* Same info as a HARD_REG_SET. */
67 HARD_REG_SET fixed_reg_set;
69 /* Data for initializing the above. */
71 static char initial_fixed_regs[] = FIXED_REGISTERS;
73 /* Indexed by hard register number, contains 1 for registers
74 that are fixed use or are clobbered by function calls.
75 These are the registers that cannot be used to allocate
76 a pseudo reg whose life crosses calls. */
78 char call_used_regs[FIRST_PSEUDO_REGISTER];
80 /* Same info as a HARD_REG_SET. */
82 HARD_REG_SET call_used_reg_set;
84 /* Data for initializing the above. */
86 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
88 /* Indexed by hard register number, contains 1 for registers that are
89 fixed use -- i.e. in fixed_regs -- or a function value return register
90 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
91 registers that cannot hold quantities across calls even if we are
92 willing to save and restore them. */
94 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
96 /* The same info as a HARD_REG_SET. */
98 HARD_REG_SET call_fixed_reg_set;
100 /* Number of non-fixed registers. */
102 int n_non_fixed_regs;
104 /* Indexed by hard register number, contains 1 for registers
105 that are being used for global register decls.
106 These must be exempt from ordinary flow analysis
107 and are also considered fixed. */
109 char global_regs[FIRST_PSEUDO_REGISTER];
111 /* Table of register numbers in the order in which to try to use them. */
112 #ifdef REG_ALLOC_ORDER
113 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
116 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
118 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
120 /* The same information, but as an array of unsigned ints. We copy from
121 these unsigned ints to the table above. We do this so the tm.h files
122 do not have to be aware of the wordsize for machines with <= 64 regs. */
125 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
127 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
128 = REG_CLASS_CONTENTS;
130 /* For each reg class, number of regs it contains. */
132 int reg_class_size[N_REG_CLASSES];
134 /* For each reg class, table listing all the containing classes. */
136 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
138 /* For each reg class, table listing all the classes contained in it. */
140 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
142 /* For each pair of reg classes,
143 a largest reg class contained in their union. */
145 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
147 /* For each pair of reg classes,
148 the smallest reg class containing their union. */
150 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
152 /* Array containing all of the register names */
154 char *reg_names[] = REGISTER_NAMES;
156 /* For each hard register, the widest mode object that it can contain.
157 This will be a MODE_INT mode if the register can hold integers. Otherwise
158 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
161 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
163 /* Indexed by n, gives number of times (REG n) is set or clobbered.
164 This information remains valid for the rest of the compilation
165 of the current function; it is used to control register allocation.
167 This information applies to both hard registers and pseudo registers,
168 unlike much of the information above. */
172 /* Maximum cost of moving from a register in one class to a register in
173 another class. Based on REGISTER_MOVE_COST. */
175 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
177 /* Similar, but here we don't have to move if the first index is a subset
178 of the second so in that case the cost is zero. */
180 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
182 #ifdef FORBIDDEN_INC_DEC_CLASSES
184 /* These are the classes that regs which are auto-incremented or decremented
187 static int forbidden_inc_dec_class[N_REG_CLASSES];
189 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
192 static char *in_inc_dec;
194 #endif /* FORBIDDEN_INC_DEC_CLASSES */
196 /* Function called only once to initialize the above data on reg usage.
197 Once this is done, various switches may override. */
204 /* First copy the register information from the initial int form into
207 for (i = 0; i < N_REG_CLASSES; i++)
209 CLEAR_HARD_REG_SET (reg_class_contents[i]);
211 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
212 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
213 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
214 SET_HARD_REG_BIT (reg_class_contents[i], j);
217 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
218 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
219 bzero (global_regs, sizeof global_regs);
221 /* Compute number of hard regs in each class. */
223 bzero ((char *) reg_class_size, sizeof reg_class_size);
224 for (i = 0; i < N_REG_CLASSES; i++)
225 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
226 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
229 /* Initialize the table of subunions.
230 reg_class_subunion[I][J] gets the largest-numbered reg-class
231 that is contained in the union of classes I and J. */
233 for (i = 0; i < N_REG_CLASSES; i++)
235 for (j = 0; j < N_REG_CLASSES; j++)
238 register /* Declare it register if it's a scalar. */
243 COPY_HARD_REG_SET (c, reg_class_contents[i]);
244 IOR_HARD_REG_SET (c, reg_class_contents[j]);
245 for (k = 0; k < N_REG_CLASSES; k++)
247 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
252 /* keep the largest subclass */ /* SPEE 900308 */
253 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
254 reg_class_contents[(int) reg_class_subunion[i][j]],
256 reg_class_subunion[i][j] = (enum reg_class) k;
263 /* Initialize the table of superunions.
264 reg_class_superunion[I][J] gets the smallest-numbered reg-class
265 containing the union of classes I and J. */
267 for (i = 0; i < N_REG_CLASSES; i++)
269 for (j = 0; j < N_REG_CLASSES; j++)
272 register /* Declare it register if it's a scalar. */
277 COPY_HARD_REG_SET (c, reg_class_contents[i]);
278 IOR_HARD_REG_SET (c, reg_class_contents[j]);
279 for (k = 0; k < N_REG_CLASSES; k++)
280 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
283 reg_class_superunion[i][j] = (enum reg_class) k;
287 /* Initialize the tables of subclasses and superclasses of each reg class.
288 First clear the whole table, then add the elements as they are found. */
290 for (i = 0; i < N_REG_CLASSES; i++)
292 for (j = 0; j < N_REG_CLASSES; j++)
294 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
295 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
299 for (i = 0; i < N_REG_CLASSES; i++)
301 if (i == (int) NO_REGS)
304 for (j = i + 1; j < N_REG_CLASSES; j++)
308 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
312 /* Reg class I is a subclass of J.
313 Add J to the table of superclasses of I. */
314 p = ®_class_superclasses[i][0];
315 while (*p != LIM_REG_CLASSES) p++;
316 *p = (enum reg_class) j;
317 /* Add I to the table of superclasses of J. */
318 p = ®_class_subclasses[j][0];
319 while (*p != LIM_REG_CLASSES) p++;
320 *p = (enum reg_class) i;
324 /* Initialize the move cost table. Find every subset of each class
325 and take the maximum cost of moving any subset to any other. */
327 for (i = 0; i < N_REG_CLASSES; i++)
328 for (j = 0; j < N_REG_CLASSES; j++)
330 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
331 enum reg_class *p1, *p2;
333 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
335 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
337 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
340 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
342 for (p2 = ®_class_subclasses[j][0];
343 *p2 != LIM_REG_CLASSES; p2++)
345 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
348 move_cost[i][j] = cost;
350 if (reg_class_subset_p (i, j))
353 may_move_cost[i][j] = cost;
357 /* After switches have been processed, which perhaps alter
358 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
365 /* This macro allows the fixed or call-used registers
366 to depend on target flags. */
368 #ifdef CONDITIONAL_REGISTER_USAGE
369 CONDITIONAL_REGISTER_USAGE;
372 /* Initialize "constant" tables. */
374 CLEAR_HARD_REG_SET (fixed_reg_set);
375 CLEAR_HARD_REG_SET (call_used_reg_set);
376 CLEAR_HARD_REG_SET (call_fixed_reg_set);
378 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
380 n_non_fixed_regs = 0;
382 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
385 SET_HARD_REG_BIT (fixed_reg_set, i);
389 if (call_used_regs[i])
390 SET_HARD_REG_BIT (call_used_reg_set, i);
391 if (call_fixed_regs[i])
392 SET_HARD_REG_BIT (call_fixed_reg_set, i);
396 /* Compute the table of register modes.
397 These values are used to record death information for individual registers
398 (as opposed to a multi-register mode). */
405 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
407 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
409 /* If we couldn't find a valid mode, fall back to `word_mode'.
410 ??? We assume `word_mode' has already been initialized.
411 ??? One situation in which we need to do this is on the mips where
412 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
413 to use DF mode for the even registers and VOIDmode for the odd
414 (for the cpu models where the odd ones are inaccessible). */
415 if (reg_raw_mode[i] == VOIDmode)
416 reg_raw_mode[i] = word_mode;
420 /* Finish initializing the register sets and
421 initialize the register modes. */
426 /* This finishes what was started by init_reg_sets, but couldn't be done
427 until after register usage was specified. */
428 if (!output_bytecode)
434 /* Return a machine mode that is legitimate for hard reg REGNO and large
435 enough to save nregs. If we can't find one, return VOIDmode. */
438 choose_hard_reg_mode (regno, nregs)
442 enum machine_mode found_mode = VOIDmode, mode;
444 /* We first look for the largest integer mode that can be validly
445 held in REGNO. If none, we look for the largest floating-point mode.
446 If we still didn't find a valid mode, try CCmode. */
448 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
450 mode = GET_MODE_WIDER_MODE (mode))
451 if (HARD_REGNO_NREGS (regno, mode) == nregs
452 && HARD_REGNO_MODE_OK (regno, mode))
455 if (found_mode != VOIDmode)
458 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
460 mode = GET_MODE_WIDER_MODE (mode))
461 if (HARD_REGNO_NREGS (regno, mode) == nregs
462 && HARD_REGNO_MODE_OK (regno, mode))
465 if (found_mode != VOIDmode)
468 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
469 && HARD_REGNO_MODE_OK (regno, CCmode))
472 /* We can't find a mode valid for this register. */
476 /* Specify the usage characteristics of the register named NAME.
477 It should be a fixed register if FIXED and a
478 call-used register if CALL_USED. */
481 fix_register (name, fixed, call_used)
483 int fixed, call_used;
489 warning ("request to mark `%s' as %s ignored by bytecode compiler",
490 name, call_used ? "call-used" : "fixed");
494 /* Decode the name and update the primary form of
495 the register info. */
497 if ((i = decode_reg_name (name)) >= 0)
499 fixed_regs[i] = fixed;
500 call_used_regs[i] = call_used;
504 warning ("unknown register name: %s", name);
508 /* Mark register number I as global. */
516 warning ("register used for two global register variables");
520 if (call_used_regs[i] && ! fixed_regs[i])
521 warning ("call-clobbered register used for global register variable");
525 /* If already fixed, nothing else to do. */
529 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
532 SET_HARD_REG_BIT (fixed_reg_set, i);
533 SET_HARD_REG_BIT (call_used_reg_set, i);
534 SET_HARD_REG_BIT (call_fixed_reg_set, i);
537 /* Now the data and code for the `regclass' pass, which happens
538 just before local-alloc. */
540 /* The `costs' struct records the cost of using a hard register of each class
541 and of using memory for each pseudo. We use this data to set up
542 register class preferences. */
546 int cost[N_REG_CLASSES];
550 /* Record the cost of each class for each pseudo. */
552 static struct costs *costs;
554 /* Record the same data by operand number, accumulated for each alternative
555 in an insn. The contribution to a pseudo is that of the minimum-cost
558 static struct costs op_costs[MAX_RECOG_OPERANDS];
560 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
561 This is available after `regclass' is run. */
563 static char *prefclass;
565 /* altclass[R] is a register class that we should use for allocating
566 pseudo number R if no register in the preferred class is available.
567 If no register in this class is available, memory is preferred.
569 It might appear to be more general to have a bitmask of classes here,
570 but since it is recommended that there be a class corresponding to the
571 union of most major pair of classes, that generality is not required.
573 This is available after `regclass' is run. */
575 static char *altclass;
577 /* Record the depth of loops that we are in. */
579 static int loop_depth;
581 /* Account for the fact that insns within a loop are executed very commonly,
582 but don't keep doing this as loops go too deep. */
584 static int loop_cost;
586 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
588 static int copy_cost PROTO((rtx, enum machine_mode,
589 enum reg_class, int));
590 static void record_address_regs PROTO((rtx, enum reg_class, int));
591 static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
592 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
594 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
595 This function is sometimes called before the info has been computed.
596 When that happens, just return GENERAL_REGS, which is innocuous. */
599 reg_preferred_class (regno)
604 return (enum reg_class) prefclass[regno];
608 reg_alternate_class (regno)
613 return (enum reg_class) altclass[regno];
616 /* This prevents dump_flow_info from losing if called
617 before regclass is run. */
625 /* This is a pass of the compiler that scans all instructions
626 and calculates the preferred class for each pseudo-register.
627 This information can be accessed later by calling `reg_preferred_class'.
628 This pass comes just before local register allocation. */
635 #ifdef REGISTER_CONSTRAINTS
638 struct costs init_cost;
644 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
646 #ifdef FORBIDDEN_INC_DEC_CLASSES
648 in_inc_dec = (char *) alloca (nregs);
650 /* Initialize information about which register classes can be used for
651 pseudos that are auto-incremented or auto-decremented. It would
652 seem better to put this in init_reg_sets, but we need to be able
653 to allocate rtx, which we can't do that early. */
655 for (i = 0; i < N_REG_CLASSES; i++)
657 rtx r = gen_rtx (REG, VOIDmode, 0);
660 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
661 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
665 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
666 m = (enum machine_mode) ((int) m + 1))
667 if (HARD_REGNO_MODE_OK (j, m))
671 /* If a register is not directly suitable for an
672 auto-increment or decrement addressing mode and
673 requires secondary reloads, disallow its class from
674 being used in such addresses. */
677 #ifdef SECONDARY_INPUT_RELOAD_CLASS
678 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
681 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
682 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
686 && ! auto_inc_dec_reg_p (r, m))
687 forbidden_inc_dec_class[i] = 1;
691 #endif /* FORBIDDEN_INC_DEC_CLASSES */
693 init_cost.mem_cost = 10000;
694 for (i = 0; i < N_REG_CLASSES; i++)
695 init_cost.cost[i] = 10000;
697 /* Normally we scan the insns once and determine the best class to use for
698 each register. However, if -fexpensive_optimizations are on, we do so
699 twice, the second time using the tentative best classes to guide the
702 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
704 /* Zero out our accumulation of the cost of each class for each reg. */
706 bzero ((char *) costs, nregs * sizeof (struct costs));
708 #ifdef FORBIDDEN_INC_DEC_CLASSES
709 bzero (in_inc_dec, nregs);
712 loop_depth = 0, loop_cost = 1;
714 /* Scan the instructions and record each time it would
715 save code to put a certain register in a certain class. */
717 for (insn = f; insn; insn = NEXT_INSN (insn))
719 char *constraints[MAX_RECOG_OPERANDS];
720 enum machine_mode modes[MAX_RECOG_OPERANDS];
724 /* Show that an insn inside a loop is likely to be executed three
725 times more than insns outside a loop. This is much more aggressive
726 than the assumptions made elsewhere and is being tried as an
729 if (GET_CODE (insn) == NOTE
730 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
731 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
732 else if (GET_CODE (insn) == NOTE
733 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
734 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
736 else if ((GET_CODE (insn) == INSN
737 && GET_CODE (PATTERN (insn)) != USE
738 && GET_CODE (PATTERN (insn)) != CLOBBER
739 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
740 || (GET_CODE (insn) == JUMP_INSN
741 && GET_CODE (PATTERN (insn)) != ADDR_VEC
742 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
743 || GET_CODE (insn) == CALL_INSN)
745 if (GET_CODE (insn) == INSN
746 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
748 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
750 nalternatives = (noperands == 0 ? 0
751 : n_occurrences (',', constraints[0]) + 1);
755 int insn_code_number = recog_memoized (insn);
758 set = single_set (insn);
761 nalternatives = insn_n_alternatives[insn_code_number];
762 noperands = insn_n_operands[insn_code_number];
764 /* If this insn loads a parameter from its stack slot, then
765 it represents a savings, rather than a cost, if the
766 parameter is stored in memory. Record this fact. */
768 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
769 && GET_CODE (SET_SRC (set)) == MEM
770 && (note = find_reg_note (insn, REG_EQUIV,
772 && GET_CODE (XEXP (note, 0)) == MEM)
774 costs[REGNO (SET_DEST (set))].mem_cost
775 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
777 record_address_regs (XEXP (SET_SRC (set), 0),
778 BASE_REG_CLASS, loop_cost * 2);
782 /* Improve handling of two-address insns such as
783 (set X (ashift CONST Y)) where CONST must be made to
784 match X. Change it into two insns: (set X CONST)
785 (set X (ashift X Y)). If we left this for reloading, it
786 would probably get three insns because X and Y might go
787 in the same place. This prevents X and Y from receiving
790 We can only do this if the modes of operands 0 and 1
791 (which might not be the same) are tieable and we only need
792 do this during our first pass. */
794 if (pass == 0 && optimize
796 && insn_operand_constraint[insn_code_number][1][0] == '0'
797 && insn_operand_constraint[insn_code_number][1][1] == 0
798 && CONSTANT_P (recog_operand[1])
799 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
800 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
801 && GET_CODE (recog_operand[0]) == REG
802 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
803 insn_operand_mode[insn_code_number][1]))
805 rtx previnsn = prev_real_insn (insn);
807 = gen_lowpart (insn_operand_mode[insn_code_number][1],
810 = emit_insn_before (gen_move_insn (dest,
814 /* If this insn was the start of a basic block,
815 include the new insn in that block.
816 We need not check for code_label here;
817 while a basic block can start with a code_label,
818 INSN could not be at the beginning of that block. */
819 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
822 for (b = 0; b < n_basic_blocks; b++)
823 if (insn == basic_block_head[b])
824 basic_block_head[b] = newinsn;
827 /* This makes one more setting of new insns's dest. */
828 reg_n_sets[REGNO (recog_operand[0])]++;
830 *recog_operand_loc[1] = recog_operand[0];
831 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
832 if (recog_dup_num[i] == 1)
833 *recog_dup_loc[i] = recog_operand[0];
835 insn = PREV_INSN (newinsn);
839 for (i = 0; i < noperands; i++)
842 = insn_operand_constraint[insn_code_number][i];
843 modes[i] = insn_operand_mode[insn_code_number][i];
847 /* If we get here, we are set up to record the costs of all the
848 operands for this insn. Start by initializing the costs.
849 Then handle any address registers. Finally record the desired
850 classes for any pseudos, doing it twice if some pair of
851 operands are commutative. */
853 for (i = 0; i < noperands; i++)
855 op_costs[i] = init_cost;
857 if (GET_CODE (recog_operand[i]) == SUBREG)
858 recog_operand[i] = SUBREG_REG (recog_operand[i]);
860 if (GET_CODE (recog_operand[i]) == MEM)
861 record_address_regs (XEXP (recog_operand[i], 0),
862 BASE_REG_CLASS, loop_cost * 2);
863 else if (constraints[i][0] == 'p')
864 record_address_regs (recog_operand[i],
865 BASE_REG_CLASS, loop_cost * 2);
868 /* Check for commutative in a separate loop so everything will
869 have been initialized. We must do this even if one operand
870 is a constant--see addsi3 in m68k.md. */
872 for (i = 0; i < noperands - 1; i++)
873 if (constraints[i][0] == '%')
875 char *xconstraints[MAX_RECOG_OPERANDS];
878 /* Handle commutative operands by swapping the constraints.
879 We assume the modes are the same. */
881 for (j = 0; j < noperands; j++)
882 xconstraints[j] = constraints[j];
884 xconstraints[i] = constraints[i+1];
885 xconstraints[i+1] = constraints[i];
886 record_reg_classes (nalternatives, noperands,
887 recog_operand, modes, xconstraints,
891 record_reg_classes (nalternatives, noperands, recog_operand,
892 modes, constraints, insn);
894 /* Now add the cost for each operand to the total costs for
897 for (i = 0; i < noperands; i++)
898 if (GET_CODE (recog_operand[i]) == REG
899 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
901 int regno = REGNO (recog_operand[i]);
902 struct costs *p = &costs[regno], *q = &op_costs[i];
904 p->mem_cost += q->mem_cost * loop_cost;
905 for (j = 0; j < N_REG_CLASSES; j++)
906 p->cost[j] += q->cost[j] * loop_cost;
911 /* Now for each register look at how desirable each class is
912 and find which class is preferred. Store that in
913 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
914 class any of whose registers is better than memory. */
918 prefclass = (char *) oballoc (nregs);
919 altclass = (char *) oballoc (nregs);
922 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
924 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
925 enum reg_class best = ALL_REGS, alt = NO_REGS;
926 /* This is an enum reg_class, but we call it an int
927 to save lots of casts. */
929 register struct costs *p = &costs[i];
931 for (class = (int) ALL_REGS - 1; class > 0; class--)
933 /* Ignore classes that are too small for this operand or
934 invalid for a operand that was auto-incremented. */
935 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
936 > reg_class_size[class]
937 #ifdef FORBIDDEN_INC_DEC_CLASSES
938 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
942 else if (p->cost[class] < best_cost)
944 best_cost = p->cost[class];
945 best = (enum reg_class) class;
947 else if (p->cost[class] == best_cost)
948 best = reg_class_subunion[(int)best][class];
951 /* Record the alternate register class; i.e., a class for which
952 every register in it is better than using memory. If adding a
953 class would make a smaller class (i.e., no union of just those
954 classes exists), skip that class. The major unions of classes
955 should be provided as a register class. Don't do this if we
956 will be doing it again later. */
958 if (pass == 1 || ! flag_expensive_optimizations)
959 for (class = 0; class < N_REG_CLASSES; class++)
960 if (p->cost[class] < p->mem_cost
961 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
962 > reg_class_size[(int) alt])
963 #ifdef FORBIDDEN_INC_DEC_CLASSES
964 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
967 alt = reg_class_subunion[(int) alt][class];
969 /* If we don't add any classes, nothing to try. */
973 /* We cast to (int) because (char) hits bugs in some compilers. */
974 prefclass[i] = (int) best;
975 altclass[i] = (int) alt;
978 #endif /* REGISTER_CONSTRAINTS */
981 #ifdef REGISTER_CONSTRAINTS
983 /* Record the cost of using memory or registers of various classes for
984 the operands in INSN.
986 N_ALTS is the number of alternatives.
988 N_OPS is the number of operands.
990 OPS is an array of the operands.
992 MODES are the modes of the operands, in case any are VOIDmode.
994 CONSTRAINTS are the constraints to use for the operands. This array
995 is modified by this procedure.
997 This procedure works alternative by alternative. For each alternative
998 we assume that we will be able to allocate all pseudos to their ideal
999 register class and calculate the cost of using that alternative. Then
1000 we compute for each operand that is a pseudo-register, the cost of
1001 having the pseudo allocated to each register class and using it in that
1002 alternative. To this cost is added the cost of the alternative.
1004 The cost of each class for this insn is its lowest cost among all the
1008 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1012 enum machine_mode *modes;
1017 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1021 /* By default, each operand is an input operand. */
1023 for (i = 0; i < n_ops; i++)
1024 op_types[i] = OP_READ;
1026 /* Process each alternative, each time minimizing an operand's cost with
1027 the cost for each operand in that alternative. */
1029 for (alt = 0; alt < n_alts; alt++)
1031 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1034 enum reg_class classes[MAX_RECOG_OPERANDS];
1037 for (i = 0; i < n_ops; i++)
1039 char *p = constraints[i];
1041 enum machine_mode mode = modes[i];
1046 /* If this operand has no constraints at all, we can conclude
1047 nothing about it since anything is valid. */
1051 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1052 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1060 /* If this alternative is only relevant when this operand
1061 matches a previous operand, we do different things depending
1062 on whether this operand is a pseudo-reg or not. */
1064 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1067 classes[i] = classes[j];
1069 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1071 /* If this matches the other operand, we have no added
1073 if (rtx_equal_p (ops[j], op))
1076 /* If we can put the other operand into a register, add to
1077 the cost of this alternative the cost to copy this
1078 operand to the register used for the other operand. */
1080 else if (classes[j] != NO_REGS)
1081 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1083 else if (GET_CODE (ops[j]) != REG
1084 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1086 /* This op is a pseudo but the one it matches is not. */
1088 /* If we can't put the other operand into a register, this
1089 alternative can't be used. */
1091 if (classes[j] == NO_REGS)
1094 /* Otherwise, add to the cost of this alternative the cost
1095 to copy the other operand to the register used for this
1099 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1103 /* The costs of this operand are the same as that of the
1104 other operand. However, if we cannot tie them, this
1105 alternative needs to do a copy, which is one
1108 this_op_costs[i] = this_op_costs[j];
1109 if (REGNO (ops[i]) != REGNO (ops[j])
1110 && ! find_reg_note (insn, REG_DEAD, op))
1113 /* This is in place of ordinary cost computation
1114 for this operand, so skip to the end of the
1115 alternative (should be just one character). */
1116 while (*p && *p++ != ',')
1124 /* Scan all the constraint letters. See if the operand matches
1125 any of the constraints. Collect the valid register classes
1126 and see if this operand accepts memory. */
1128 classes[i] = NO_REGS;
1129 while (*p && (c = *p++) != ',')
1133 op_types[i] = OP_WRITE;
1137 op_types[i] = OP_READ_WRITE;
1141 /* Ignore the next letter for this pass. */
1146 case '?': case '!': case '#':
1148 case '0': case '1': case '2': case '3': case '4':
1152 case 'm': case 'o': case 'V':
1153 /* It doesn't seem worth distinguishing between offsettable
1154 and non-offsettable addresses here. */
1156 if (GET_CODE (op) == MEM)
1161 if (GET_CODE (op) == MEM
1162 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1163 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1168 if (GET_CODE (op) == MEM
1169 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1170 || GET_CODE (XEXP (op, 0)) == POST_INC))
1175 #ifndef REAL_ARITHMETIC
1176 /* Match any floating double constant, but only if
1177 we can examine the bits of it reliably. */
1178 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1179 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1180 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1183 if (GET_CODE (op) == CONST_DOUBLE)
1188 if (GET_CODE (op) == CONST_DOUBLE)
1194 if (GET_CODE (op) == CONST_DOUBLE
1195 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1200 if (GET_CODE (op) == CONST_INT
1201 || (GET_CODE (op) == CONST_DOUBLE
1202 && GET_MODE (op) == VOIDmode))
1206 #ifdef LEGITIMATE_PIC_OPERAND_P
1207 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1214 if (GET_CODE (op) == CONST_INT
1215 || (GET_CODE (op) == CONST_DOUBLE
1216 && GET_MODE (op) == VOIDmode))
1228 if (GET_CODE (op) == CONST_INT
1229 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1237 #ifdef EXTRA_CONSTRAINT
1243 if (EXTRA_CONSTRAINT (op, c))
1249 if (GET_CODE (op) == MEM
1251 #ifdef LEGITIMATE_PIC_OPERAND_P
1252 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1259 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1264 = reg_class_subunion[(int) classes[i]]
1265 [(int) REG_CLASS_FROM_LETTER (c)];
1270 /* How we account for this operand now depends on whether it is a
1271 pseudo register or not. If it is, we first check if any
1272 register classes are valid. If not, we ignore this alternative,
1273 since we want to assume that all pseudos get allocated for
1274 register preferencing. If some register class is valid, compute
1275 the costs of moving the pseudo into that class. */
1277 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1279 if (classes[i] == NO_REGS)
1283 struct costs *pp = &this_op_costs[i];
1285 for (class = 0; class < N_REG_CLASSES; class++)
1286 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1288 /* If the alternative actually allows memory, make things
1289 a bit cheaper since we won't need an extra insn to
1292 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1294 /* If we have assigned a class to this register in our
1295 first pass, add a cost to this alternative corresponding
1296 to what we would add if this register were not in the
1297 appropriate class. */
1301 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1305 /* Otherwise, if this alternative wins, either because we
1306 have already determined that or if we have a hard register of
1307 the proper class, there is no cost for this alternative. */
1310 || (GET_CODE (op) == REG
1311 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1314 /* If registers are valid, the cost of this alternative includes
1315 copying the object to and/or from a register. */
1317 else if (classes[i] != NO_REGS)
1319 if (op_types[i] != OP_WRITE)
1320 alt_cost += copy_cost (op, mode, classes[i], 1);
1322 if (op_types[i] != OP_READ)
1323 alt_cost += copy_cost (op, mode, classes[i], 0);
1326 /* The only other way this alternative can be used is if this is a
1327 constant that could be placed into memory. */
1329 else if (CONSTANT_P (op) && allows_mem)
1330 alt_cost += MEMORY_MOVE_COST (mode);
1338 /* Finally, update the costs with the information we've calculated
1339 about this alternative. */
1341 for (i = 0; i < n_ops; i++)
1342 if (GET_CODE (ops[i]) == REG
1343 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1345 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1346 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1348 pp->mem_cost = MIN (pp->mem_cost,
1349 (qq->mem_cost + alt_cost) * scale);
1351 for (class = 0; class < N_REG_CLASSES; class++)
1352 pp->cost[class] = MIN (pp->cost[class],
1353 (qq->cost[class] + alt_cost) * scale);
1357 /* If this insn is a single set copying operand 1 to operand 0
1358 and one is a pseudo with the other a hard reg that is in its
1359 own register class, set the cost of that register class to -1. */
1361 if ((set = single_set (insn)) != 0
1362 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1363 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1364 for (i = 0; i <= 1; i++)
1365 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1367 int regno = REGNO (ops[!i]);
1368 enum machine_mode mode = GET_MODE (ops[!i]);
1372 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1373 && (reg_class_size[prefclass[regno]]
1374 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1375 op_costs[i].cost[prefclass[regno]] = -1;
1376 else if (regno < FIRST_PSEUDO_REGISTER)
1377 for (class = 0; class < N_REG_CLASSES; class++)
1378 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1379 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1381 if (reg_class_size[class] == 1)
1382 op_costs[i].cost[class] = -1;
1385 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1387 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1391 if (nr == HARD_REGNO_NREGS(regno,mode))
1392 op_costs[i].cost[class] = -1;
1398 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1399 TO_P is zero) a register of class CLASS in mode MODE.
1401 X must not be a pseudo. */
1404 copy_cost (x, mode, class, to_p)
1406 enum machine_mode mode;
1407 enum reg_class class;
1410 enum reg_class secondary_class = NO_REGS;
1412 /* If X is a SCRATCH, there is actually nothing to move since we are
1413 assuming optimal allocation. */
1415 if (GET_CODE (x) == SCRATCH)
1418 /* Get the class we will actually use for a reload. */
1419 class = PREFERRED_RELOAD_CLASS (x, class);
1421 #ifdef HAVE_SECONDARY_RELOADS
1422 /* If we need a secondary reload (we assume here that we are using
1423 the secondary reload as an intermediate, not a scratch register), the
1424 cost is that to load the input into the intermediate register, then
1425 to copy them. We use a special value of TO_P to avoid recursion. */
1427 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1429 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1432 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1434 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1437 if (secondary_class != NO_REGS)
1438 return (move_cost[(int) secondary_class][(int) class]
1439 + copy_cost (x, mode, secondary_class, 2));
1440 #endif /* HAVE_SECONDARY_RELOADS */
1442 /* For memory, use the memory move cost, for (hard) registers, use the
1443 cost to move between the register classes, and use 2 for everything
1444 else (constants). */
1446 if (GET_CODE (x) == MEM || class == NO_REGS)
1447 return MEMORY_MOVE_COST (mode);
1449 else if (GET_CODE (x) == REG)
1450 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1453 /* If this is a constant, we may eventually want to call rtx_cost here. */
1457 /* Record the pseudo registers we must reload into hard registers
1458 in a subexpression of a memory address, X.
1460 CLASS is the class that the register needs to be in and is either
1461 BASE_REG_CLASS or INDEX_REG_CLASS.
1463 SCALE is twice the amount to multiply the cost by (it is twice so we
1464 can represent half-cost adjustments). */
1467 record_address_regs (x, class, scale)
1469 enum reg_class class;
1472 register enum rtx_code code = GET_CODE (x);
1485 /* When we have an address that is a sum,
1486 we must determine whether registers are "base" or "index" regs.
1487 If there is a sum of two registers, we must choose one to be
1488 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1489 to make a good choice most of the time. We only need to do this
1490 on machines that can have two registers in an address and where
1491 the base and index register classes are different.
1493 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1494 that seems bogus since it should only be set when we are sure
1495 the register is being used as a pointer. */
1498 rtx arg0 = XEXP (x, 0);
1499 rtx arg1 = XEXP (x, 1);
1500 register enum rtx_code code0 = GET_CODE (arg0);
1501 register enum rtx_code code1 = GET_CODE (arg1);
1503 /* Look inside subregs. */
1504 if (code0 == SUBREG)
1505 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1506 if (code1 == SUBREG)
1507 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1509 /* If this machine only allows one register per address, it must
1510 be in the first operand. */
1512 if (MAX_REGS_PER_ADDRESS == 1)
1513 record_address_regs (arg0, class, scale);
1515 /* If index and base registers are the same on this machine, just
1516 record registers in any non-constant operands. We assume here,
1517 as well as in the tests below, that all addresses are in
1520 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1522 record_address_regs (arg0, class, scale);
1523 if (! CONSTANT_P (arg1))
1524 record_address_regs (arg1, class, scale);
1527 /* If the second operand is a constant integer, it doesn't change
1528 what class the first operand must be. */
1530 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1531 record_address_regs (arg0, class, scale);
1533 /* If the second operand is a symbolic constant, the first operand
1534 must be an index register. */
1536 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1537 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1539 /* If this the sum of two registers where the first is known to be a
1540 pointer, it must be a base register with the second an index. */
1542 else if (code0 == REG && code1 == REG
1543 && REGNO_POINTER_FLAG (REGNO (arg0)))
1545 record_address_regs (arg0, BASE_REG_CLASS, scale);
1546 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1549 /* If this is the sum of two registers and neither is known to
1550 be a pointer, count equal chances that each might be a base
1551 or index register. This case should be rare. */
1553 else if (code0 == REG && code1 == REG
1554 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1555 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1557 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1558 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1559 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1560 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1563 /* In all other cases, the first operand is an index and the
1564 second is the base. */
1568 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1569 record_address_regs (arg1, BASE_REG_CLASS, scale);
1578 /* Double the importance of a pseudo register that is incremented
1579 or decremented, since it would take two extra insns
1580 if it ends up in the wrong place. If the operand is a pseudo,
1581 show it is being used in an INC_DEC context. */
1583 #ifdef FORBIDDEN_INC_DEC_CLASSES
1584 if (GET_CODE (XEXP (x, 0)) == REG
1585 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1586 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1589 record_address_regs (XEXP (x, 0), class, 2 * scale);
1594 register struct costs *pp = &costs[REGNO (x)];
1597 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1599 for (i = 0; i < N_REG_CLASSES; i++)
1600 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1606 register char *fmt = GET_RTX_FORMAT (code);
1608 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1610 record_address_regs (XEXP (x, i), class, scale);
1615 #ifdef FORBIDDEN_INC_DEC_CLASSES
1617 /* Return 1 if REG is valid as an auto-increment memory reference
1618 to an object of MODE. */
1621 auto_inc_dec_reg_p (reg, mode)
1623 enum machine_mode mode;
1625 #ifdef HAVE_POST_INCREMENT
1626 if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg)))
1630 #ifdef HAVE_POST_DECREMENT
1631 if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg)))
1635 #ifdef HAVE_PRE_INCREMENT
1636 if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg)))
1640 #ifdef HAVE_PRE_DECREMENT
1641 if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg)))
1649 #endif /* REGISTER_CONSTRAINTS */
1651 /* This is the `regscan' pass of the compiler, run just before cse
1652 and again just before loop.
1654 It finds the first and last use of each pseudo-register
1655 and records them in the vectors regno_first_uid, regno_last_uid
1656 and counts the number of sets in the vector reg_n_sets.
1658 REPEAT is nonzero the second time this is called. */
1660 /* Indexed by pseudo register number, gives uid of first insn using the reg
1661 (as of the time reg_scan is called). */
1663 int *regno_first_uid;
1665 /* Indexed by pseudo register number, gives uid of last insn using the reg
1666 (as of the time reg_scan is called). */
1668 int *regno_last_uid;
1670 /* Indexed by pseudo register number, gives uid of last insn using the reg
1671 or mentioning it in a note (as of the time reg_scan is called). */
1673 int *regno_last_note_uid;
1675 /* Record the number of registers we used when we allocated the above two
1676 tables. If we are called again with more than this, we must re-allocate
1679 static int highest_regno_in_uid_map;
1681 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1682 Always at least 3, since the combiner could put that many together
1683 and we want this to remain correct for all the remaining passes. */
1688 reg_scan (f, nregs, repeat)
1695 if (!repeat || nregs > highest_regno_in_uid_map)
1697 /* Leave some spare space in case more regs are allocated. */
1698 highest_regno_in_uid_map = nregs + nregs / 20;
1700 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1702 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1704 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1706 = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1709 bzero ((char *) regno_first_uid, highest_regno_in_uid_map * sizeof (int));
1710 bzero ((char *) regno_last_uid, highest_regno_in_uid_map * sizeof (int));
1711 bzero ((char *) regno_last_note_uid,
1712 highest_regno_in_uid_map * sizeof (int));
1713 bzero ((char *) reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1717 for (insn = f; insn; insn = NEXT_INSN (insn))
1718 if (GET_CODE (insn) == INSN
1719 || GET_CODE (insn) == CALL_INSN
1720 || GET_CODE (insn) == JUMP_INSN)
1722 if (GET_CODE (PATTERN (insn)) == PARALLEL
1723 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1724 max_parallel = XVECLEN (PATTERN (insn), 0);
1725 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1727 if (REG_NOTES (insn))
1728 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1732 /* X is the expression to scan. INSN is the insn it appears in.
1733 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1736 reg_scan_mark_refs (x, insn, note_flag)
1741 register enum rtx_code code = GET_CODE (x);
1760 register int regno = REGNO (x);
1762 regno_last_note_uid[regno] = INSN_UID (insn);
1764 regno_last_uid[regno] = INSN_UID (insn);
1765 if (regno_first_uid[regno] == 0)
1766 regno_first_uid[regno] = INSN_UID (insn);
1772 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1774 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1779 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1783 /* Count a set of the destination if it is a register. */
1784 for (dest = SET_DEST (x);
1785 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1786 || GET_CODE (dest) == ZERO_EXTEND;
1787 dest = XEXP (dest, 0))
1790 if (GET_CODE (dest) == REG)
1791 reg_n_sets[REGNO (dest)]++;
1793 /* If this is setting a pseudo from another pseudo or the sum of a
1794 pseudo and a constant integer and the other pseudo is known to be
1795 a pointer, set the destination to be a pointer as well.
1797 Likewise if it is setting the destination from an address or from a
1798 value equivalent to an address or to the sum of an address and
1801 But don't do any of this if the pseudo corresponds to a user
1802 variable since it should have already been set as a pointer based
1805 if (GET_CODE (SET_DEST (x)) == REG
1806 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
1807 && ! REG_USERVAR_P (SET_DEST (x))
1808 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
1809 && ((GET_CODE (SET_SRC (x)) == REG
1810 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
1811 || ((GET_CODE (SET_SRC (x)) == PLUS
1812 || GET_CODE (SET_SRC (x)) == LO_SUM)
1813 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1814 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
1815 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
1816 || GET_CODE (SET_SRC (x)) == CONST
1817 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
1818 || GET_CODE (SET_SRC (x)) == LABEL_REF
1819 || (GET_CODE (SET_SRC (x)) == HIGH
1820 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
1821 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
1822 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
1823 || ((GET_CODE (SET_SRC (x)) == PLUS
1824 || GET_CODE (SET_SRC (x)) == LO_SUM)
1825 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
1826 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
1827 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
1828 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
1829 && (GET_CODE (XEXP (note, 0)) == CONST
1830 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
1831 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
1832 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
1834 /* ... fall through ... */
1838 register char *fmt = GET_RTX_FORMAT (code);
1840 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1843 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
1844 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1847 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1848 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
1855 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1859 reg_class_subset_p (c1, c2)
1860 register enum reg_class c1;
1861 register enum reg_class c2;
1863 if (c1 == c2) return 1;
1868 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1869 reg_class_contents[(int)c2],
1874 /* Return nonzero if there is a register that is in both C1 and C2. */
1877 reg_classes_intersect_p (c1, c2)
1878 register enum reg_class c1;
1879 register enum reg_class c2;
1886 if (c1 == c2) return 1;
1888 if (c1 == ALL_REGS || c2 == ALL_REGS)
1891 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1892 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1894 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);