1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
28 #include "hard-reg-set.h"
30 #include "basic-block.h"
32 #include "insn-config.h"
38 #ifndef REGISTER_MOVE_COST
39 #define REGISTER_MOVE_COST(x, y) 2
42 #ifndef MEMORY_MOVE_COST
43 #define MEMORY_MOVE_COST(x) 4
46 /* If we have auto-increment or auto-decrement and we can have secondary
47 reloads, we are not allowed to use classes requiring secondary
48 reloads for pseudos auto-incremented since reload can't handle it. */
51 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
52 #define FORBIDDEN_INC_DEC_CLASSES
56 /* Register tables used by many passes. */
58 /* Indexed by hard register number, contains 1 for registers
59 that are fixed use (stack pointer, pc, frame pointer, etc.).
60 These are the registers that cannot be used to allocate
61 a pseudo reg whose life does not cross calls. */
63 char fixed_regs[FIRST_PSEUDO_REGISTER];
65 /* Same info as a HARD_REG_SET. */
67 HARD_REG_SET fixed_reg_set;
69 /* Data for initializing the above. */
71 static char initial_fixed_regs[] = FIXED_REGISTERS;
73 /* Indexed by hard register number, contains 1 for registers
74 that are fixed use or are clobbered by function calls.
75 These are the registers that cannot be used to allocate
76 a pseudo reg whose life crosses calls. */
78 char call_used_regs[FIRST_PSEUDO_REGISTER];
80 /* Same info as a HARD_REG_SET. */
82 HARD_REG_SET call_used_reg_set;
84 /* HARD_REG_SET of registers we want to avoid caller saving. */
85 HARD_REG_SET losing_caller_save_reg_set;
87 /* Data for initializing the above. */
89 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
91 /* Indexed by hard register number, contains 1 for registers that are
92 fixed use -- i.e. in fixed_regs -- or a function value return register
93 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
94 registers that cannot hold quantities across calls even if we are
95 willing to save and restore them. */
97 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
99 /* The same info as a HARD_REG_SET. */
101 HARD_REG_SET call_fixed_reg_set;
103 /* Number of non-fixed registers. */
105 int n_non_fixed_regs;
107 /* Indexed by hard register number, contains 1 for registers
108 that are being used for global register decls.
109 These must be exempt from ordinary flow analysis
110 and are also considered fixed. */
112 char global_regs[FIRST_PSEUDO_REGISTER];
114 /* Table of register numbers in the order in which to try to use them. */
115 #ifdef REG_ALLOC_ORDER
116 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
119 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
121 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
123 /* The same information, but as an array of unsigned ints. We copy from
124 these unsigned ints to the table above. We do this so the tm.h files
125 do not have to be aware of the wordsize for machines with <= 64 regs. */
128 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
130 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
131 = REG_CLASS_CONTENTS;
133 /* For each reg class, number of regs it contains. */
135 int reg_class_size[N_REG_CLASSES];
137 /* For each reg class, table listing all the containing classes. */
139 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
141 /* For each reg class, table listing all the classes contained in it. */
143 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
145 /* For each pair of reg classes,
146 a largest reg class contained in their union. */
148 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
150 /* For each pair of reg classes,
151 the smallest reg class containing their union. */
153 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
155 /* Array containing all of the register names */
157 char *reg_names[] = REGISTER_NAMES;
159 /* For each hard register, the widest mode object that it can contain.
160 This will be a MODE_INT mode if the register can hold integers. Otherwise
161 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
164 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
166 /* Maximum cost of moving from a register in one class to a register in
167 another class. Based on REGISTER_MOVE_COST. */
169 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
171 /* Similar, but here we don't have to move if the first index is a subset
172 of the second so in that case the cost is zero. */
174 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
176 #ifdef FORBIDDEN_INC_DEC_CLASSES
178 /* These are the classes that regs which are auto-incremented or decremented
181 static int forbidden_inc_dec_class[N_REG_CLASSES];
183 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
186 static char *in_inc_dec;
188 #endif /* FORBIDDEN_INC_DEC_CLASSES */
190 /* Function called only once to initialize the above data on reg usage.
191 Once this is done, various switches may override. */
198 /* First copy the register information from the initial int form into
201 for (i = 0; i < N_REG_CLASSES; i++)
203 CLEAR_HARD_REG_SET (reg_class_contents[i]);
205 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
206 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
207 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
208 SET_HARD_REG_BIT (reg_class_contents[i], j);
211 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
212 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
213 bzero (global_regs, sizeof global_regs);
215 /* Compute number of hard regs in each class. */
217 bzero ((char *) reg_class_size, sizeof reg_class_size);
218 for (i = 0; i < N_REG_CLASSES; i++)
219 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
220 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
223 /* Initialize the table of subunions.
224 reg_class_subunion[I][J] gets the largest-numbered reg-class
225 that is contained in the union of classes I and J. */
227 for (i = 0; i < N_REG_CLASSES; i++)
229 for (j = 0; j < N_REG_CLASSES; j++)
232 register /* Declare it register if it's a scalar. */
237 COPY_HARD_REG_SET (c, reg_class_contents[i]);
238 IOR_HARD_REG_SET (c, reg_class_contents[j]);
239 for (k = 0; k < N_REG_CLASSES; k++)
241 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
246 /* keep the largest subclass */ /* SPEE 900308 */
247 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
248 reg_class_contents[(int) reg_class_subunion[i][j]],
250 reg_class_subunion[i][j] = (enum reg_class) k;
257 /* Initialize the table of superunions.
258 reg_class_superunion[I][J] gets the smallest-numbered reg-class
259 containing the union of classes I and J. */
261 for (i = 0; i < N_REG_CLASSES; i++)
263 for (j = 0; j < N_REG_CLASSES; j++)
266 register /* Declare it register if it's a scalar. */
271 COPY_HARD_REG_SET (c, reg_class_contents[i]);
272 IOR_HARD_REG_SET (c, reg_class_contents[j]);
273 for (k = 0; k < N_REG_CLASSES; k++)
274 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
277 reg_class_superunion[i][j] = (enum reg_class) k;
281 /* Initialize the tables of subclasses and superclasses of each reg class.
282 First clear the whole table, then add the elements as they are found. */
284 for (i = 0; i < N_REG_CLASSES; i++)
286 for (j = 0; j < N_REG_CLASSES; j++)
288 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
289 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
293 for (i = 0; i < N_REG_CLASSES; i++)
295 if (i == (int) NO_REGS)
298 for (j = i + 1; j < N_REG_CLASSES; j++)
302 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
306 /* Reg class I is a subclass of J.
307 Add J to the table of superclasses of I. */
308 p = ®_class_superclasses[i][0];
309 while (*p != LIM_REG_CLASSES) p++;
310 *p = (enum reg_class) j;
311 /* Add I to the table of superclasses of J. */
312 p = ®_class_subclasses[j][0];
313 while (*p != LIM_REG_CLASSES) p++;
314 *p = (enum reg_class) i;
318 /* Initialize the move cost table. Find every subset of each class
319 and take the maximum cost of moving any subset to any other. */
321 for (i = 0; i < N_REG_CLASSES; i++)
322 for (j = 0; j < N_REG_CLASSES; j++)
324 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
325 enum reg_class *p1, *p2;
327 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
329 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
331 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
334 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
336 for (p2 = ®_class_subclasses[j][0];
337 *p2 != LIM_REG_CLASSES; p2++)
339 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
342 move_cost[i][j] = cost;
344 if (reg_class_subset_p (i, j))
347 may_move_cost[i][j] = cost;
350 /* Do any additional initialization regsets may need */
351 INIT_ONCE_REG_SET ();
354 /* After switches have been processed, which perhaps alter
355 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
362 /* This macro allows the fixed or call-used registers
363 to depend on target flags. */
365 #ifdef CONDITIONAL_REGISTER_USAGE
366 CONDITIONAL_REGISTER_USAGE;
369 /* Initialize "constant" tables. */
371 CLEAR_HARD_REG_SET (fixed_reg_set);
372 CLEAR_HARD_REG_SET (call_used_reg_set);
373 CLEAR_HARD_REG_SET (call_fixed_reg_set);
375 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
377 n_non_fixed_regs = 0;
379 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
382 SET_HARD_REG_BIT (fixed_reg_set, i);
386 if (call_used_regs[i])
387 SET_HARD_REG_BIT (call_used_reg_set, i);
388 if (call_fixed_regs[i])
389 SET_HARD_REG_BIT (call_fixed_reg_set, i);
390 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
391 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
395 /* Compute the table of register modes.
396 These values are used to record death information for individual registers
397 (as opposed to a multi-register mode). */
404 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
406 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
408 /* If we couldn't find a valid mode, just use the previous mode.
409 ??? One situation in which we need to do this is on the mips where
410 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
411 to use DF mode for the even registers and VOIDmode for the odd
412 (for the cpu models where the odd ones are inaccessible). */
413 if (reg_raw_mode[i] == VOIDmode)
414 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
418 /* Finish initializing the register sets and
419 initialize the register modes. */
424 /* This finishes what was started by init_reg_sets, but couldn't be done
425 until after register usage was specified. */
426 if (!output_bytecode)
432 /* Return a machine mode that is legitimate for hard reg REGNO and large
433 enough to save nregs. If we can't find one, return VOIDmode. */
436 choose_hard_reg_mode (regno, nregs)
440 enum machine_mode found_mode = VOIDmode, mode;
442 /* We first look for the largest integer mode that can be validly
443 held in REGNO. If none, we look for the largest floating-point mode.
444 If we still didn't find a valid mode, try CCmode. */
446 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
448 mode = GET_MODE_WIDER_MODE (mode))
449 if (HARD_REGNO_NREGS (regno, mode) == nregs
450 && HARD_REGNO_MODE_OK (regno, mode))
453 if (found_mode != VOIDmode)
456 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
458 mode = GET_MODE_WIDER_MODE (mode))
459 if (HARD_REGNO_NREGS (regno, mode) == nregs
460 && HARD_REGNO_MODE_OK (regno, mode))
463 if (found_mode != VOIDmode)
466 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
467 && HARD_REGNO_MODE_OK (regno, CCmode))
470 /* We can't find a mode valid for this register. */
474 /* Specify the usage characteristics of the register named NAME.
475 It should be a fixed register if FIXED and a
476 call-used register if CALL_USED. */
479 fix_register (name, fixed, call_used)
481 int fixed, call_used;
487 warning ("request to mark `%s' as %s ignored by bytecode compiler",
488 name, call_used ? "call-used" : "fixed");
492 /* Decode the name and update the primary form of
493 the register info. */
495 if ((i = decode_reg_name (name)) >= 0)
497 fixed_regs[i] = fixed;
498 call_used_regs[i] = call_used;
502 warning ("unknown register name: %s", name);
506 /* Mark register number I as global. */
514 warning ("register used for two global register variables");
518 if (call_used_regs[i] && ! fixed_regs[i])
519 warning ("call-clobbered register used for global register variable");
523 /* If already fixed, nothing else to do. */
527 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
530 SET_HARD_REG_BIT (fixed_reg_set, i);
531 SET_HARD_REG_BIT (call_used_reg_set, i);
532 SET_HARD_REG_BIT (call_fixed_reg_set, i);
535 /* Now the data and code for the `regclass' pass, which happens
536 just before local-alloc. */
538 /* The `costs' struct records the cost of using a hard register of each class
539 and of using memory for each pseudo. We use this data to set up
540 register class preferences. */
544 int cost[N_REG_CLASSES];
548 /* Record the cost of each class for each pseudo. */
550 static struct costs *costs;
552 /* Record the same data by operand number, accumulated for each alternative
553 in an insn. The contribution to a pseudo is that of the minimum-cost
556 static struct costs op_costs[MAX_RECOG_OPERANDS];
558 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
559 This is available after `regclass' is run. */
561 static char *prefclass;
563 /* altclass[R] is a register class that we should use for allocating
564 pseudo number R if no register in the preferred class is available.
565 If no register in this class is available, memory is preferred.
567 It might appear to be more general to have a bitmask of classes here,
568 but since it is recommended that there be a class corresponding to the
569 union of most major pair of classes, that generality is not required.
571 This is available after `regclass' is run. */
573 static char *altclass;
575 /* Record the depth of loops that we are in. */
577 static int loop_depth;
579 /* Account for the fact that insns within a loop are executed very commonly,
580 but don't keep doing this as loops go too deep. */
582 static int loop_cost;
584 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
586 static int copy_cost PROTO((rtx, enum machine_mode,
587 enum reg_class, int));
588 static void record_address_regs PROTO((rtx, enum reg_class, int));
589 static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
590 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
592 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
593 This function is sometimes called before the info has been computed.
594 When that happens, just return GENERAL_REGS, which is innocuous. */
597 reg_preferred_class (regno)
602 return (enum reg_class) prefclass[regno];
606 reg_alternate_class (regno)
611 return (enum reg_class) altclass[regno];
614 /* This prevents dump_flow_info from losing if called
615 before regclass is run. */
623 /* This is a pass of the compiler that scans all instructions
624 and calculates the preferred class for each pseudo-register.
625 This information can be accessed later by calling `reg_preferred_class'.
626 This pass comes just before local register allocation. */
633 #ifdef REGISTER_CONSTRAINTS
636 struct costs init_cost;
642 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
644 #ifdef FORBIDDEN_INC_DEC_CLASSES
646 in_inc_dec = (char *) alloca (nregs);
648 /* Initialize information about which register classes can be used for
649 pseudos that are auto-incremented or auto-decremented. It would
650 seem better to put this in init_reg_sets, but we need to be able
651 to allocate rtx, which we can't do that early. */
653 for (i = 0; i < N_REG_CLASSES; i++)
655 rtx r = gen_rtx (REG, VOIDmode, 0);
658 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
659 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
663 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
664 m = (enum machine_mode) ((int) m + 1))
665 if (HARD_REGNO_MODE_OK (j, m))
669 /* If a register is not directly suitable for an
670 auto-increment or decrement addressing mode and
671 requires secondary reloads, disallow its class from
672 being used in such addresses. */
675 #ifdef SECONDARY_RELOAD_CLASS
676 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
679 #ifdef SECONDARY_INPUT_RELOAD_CLASS
680 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
683 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
684 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
689 && ! auto_inc_dec_reg_p (r, m))
690 forbidden_inc_dec_class[i] = 1;
694 #endif /* FORBIDDEN_INC_DEC_CLASSES */
696 init_cost.mem_cost = 10000;
697 for (i = 0; i < N_REG_CLASSES; i++)
698 init_cost.cost[i] = 10000;
700 /* Normally we scan the insns once and determine the best class to use for
701 each register. However, if -fexpensive_optimizations are on, we do so
702 twice, the second time using the tentative best classes to guide the
705 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
707 /* Zero out our accumulation of the cost of each class for each reg. */
709 bzero ((char *) costs, nregs * sizeof (struct costs));
711 #ifdef FORBIDDEN_INC_DEC_CLASSES
712 bzero (in_inc_dec, nregs);
715 loop_depth = 0, loop_cost = 1;
717 /* Scan the instructions and record each time it would
718 save code to put a certain register in a certain class. */
720 for (insn = f; insn; insn = NEXT_INSN (insn))
722 char *constraints[MAX_RECOG_OPERANDS];
723 enum machine_mode modes[MAX_RECOG_OPERANDS];
727 /* Show that an insn inside a loop is likely to be executed three
728 times more than insns outside a loop. This is much more aggressive
729 than the assumptions made elsewhere and is being tried as an
732 if (GET_CODE (insn) == NOTE
733 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
734 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
735 else if (GET_CODE (insn) == NOTE
736 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
737 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
739 else if ((GET_CODE (insn) == INSN
740 && GET_CODE (PATTERN (insn)) != USE
741 && GET_CODE (PATTERN (insn)) != CLOBBER
742 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
743 || (GET_CODE (insn) == JUMP_INSN
744 && GET_CODE (PATTERN (insn)) != ADDR_VEC
745 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
746 || GET_CODE (insn) == CALL_INSN)
748 if (GET_CODE (insn) == INSN
749 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
751 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
753 nalternatives = (noperands == 0 ? 0
754 : n_occurrences (',', constraints[0]) + 1);
758 int insn_code_number = recog_memoized (insn);
761 set = single_set (insn);
764 nalternatives = insn_n_alternatives[insn_code_number];
765 noperands = insn_n_operands[insn_code_number];
767 /* If this insn loads a parameter from its stack slot, then
768 it represents a savings, rather than a cost, if the
769 parameter is stored in memory. Record this fact. */
771 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
772 && GET_CODE (SET_SRC (set)) == MEM
773 && (note = find_reg_note (insn, REG_EQUIV,
775 && GET_CODE (XEXP (note, 0)) == MEM)
777 costs[REGNO (SET_DEST (set))].mem_cost
778 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
780 record_address_regs (XEXP (SET_SRC (set), 0),
781 BASE_REG_CLASS, loop_cost * 2);
785 /* Improve handling of two-address insns such as
786 (set X (ashift CONST Y)) where CONST must be made to
787 match X. Change it into two insns: (set X CONST)
788 (set X (ashift X Y)). If we left this for reloading, it
789 would probably get three insns because X and Y might go
790 in the same place. This prevents X and Y from receiving
793 We can only do this if the modes of operands 0 and 1
794 (which might not be the same) are tieable and we only need
795 do this during our first pass. */
797 if (pass == 0 && optimize
799 && insn_operand_constraint[insn_code_number][1][0] == '0'
800 && insn_operand_constraint[insn_code_number][1][1] == 0
801 && CONSTANT_P (recog_operand[1])
802 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
803 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
804 && GET_CODE (recog_operand[0]) == REG
805 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
806 insn_operand_mode[insn_code_number][1]))
808 rtx previnsn = prev_real_insn (insn);
810 = gen_lowpart (insn_operand_mode[insn_code_number][1],
813 = emit_insn_before (gen_move_insn (dest,
817 /* If this insn was the start of a basic block,
818 include the new insn in that block.
819 We need not check for code_label here;
820 while a basic block can start with a code_label,
821 INSN could not be at the beginning of that block. */
822 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
825 for (b = 0; b < n_basic_blocks; b++)
826 if (insn == basic_block_head[b])
827 basic_block_head[b] = newinsn;
830 /* This makes one more setting of new insns's dest. */
831 REG_N_SETS (REGNO (recog_operand[0]))++;
833 *recog_operand_loc[1] = recog_operand[0];
834 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
835 if (recog_dup_num[i] == 1)
836 *recog_dup_loc[i] = recog_operand[0];
838 insn = PREV_INSN (newinsn);
842 for (i = 0; i < noperands; i++)
845 = insn_operand_constraint[insn_code_number][i];
846 modes[i] = insn_operand_mode[insn_code_number][i];
850 /* If we get here, we are set up to record the costs of all the
851 operands for this insn. Start by initializing the costs.
852 Then handle any address registers. Finally record the desired
853 classes for any pseudos, doing it twice if some pair of
854 operands are commutative. */
856 for (i = 0; i < noperands; i++)
858 op_costs[i] = init_cost;
860 if (GET_CODE (recog_operand[i]) == SUBREG)
861 recog_operand[i] = SUBREG_REG (recog_operand[i]);
863 if (GET_CODE (recog_operand[i]) == MEM)
864 record_address_regs (XEXP (recog_operand[i], 0),
865 BASE_REG_CLASS, loop_cost * 2);
866 else if (constraints[i][0] == 'p')
867 record_address_regs (recog_operand[i],
868 BASE_REG_CLASS, loop_cost * 2);
871 /* Check for commutative in a separate loop so everything will
872 have been initialized. We must do this even if one operand
873 is a constant--see addsi3 in m68k.md. */
875 for (i = 0; i < noperands - 1; i++)
876 if (constraints[i][0] == '%')
878 char *xconstraints[MAX_RECOG_OPERANDS];
881 /* Handle commutative operands by swapping the constraints.
882 We assume the modes are the same. */
884 for (j = 0; j < noperands; j++)
885 xconstraints[j] = constraints[j];
887 xconstraints[i] = constraints[i+1];
888 xconstraints[i+1] = constraints[i];
889 record_reg_classes (nalternatives, noperands,
890 recog_operand, modes, xconstraints,
894 record_reg_classes (nalternatives, noperands, recog_operand,
895 modes, constraints, insn);
897 /* Now add the cost for each operand to the total costs for
900 for (i = 0; i < noperands; i++)
901 if (GET_CODE (recog_operand[i]) == REG
902 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
904 int regno = REGNO (recog_operand[i]);
905 struct costs *p = &costs[regno], *q = &op_costs[i];
907 p->mem_cost += q->mem_cost * loop_cost;
908 for (j = 0; j < N_REG_CLASSES; j++)
909 p->cost[j] += q->cost[j] * loop_cost;
914 /* Now for each register look at how desirable each class is
915 and find which class is preferred. Store that in
916 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
917 class any of whose registers is better than memory. */
921 prefclass = (char *) oballoc (nregs);
922 altclass = (char *) oballoc (nregs);
925 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
927 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
928 enum reg_class best = ALL_REGS, alt = NO_REGS;
929 /* This is an enum reg_class, but we call it an int
930 to save lots of casts. */
932 register struct costs *p = &costs[i];
934 for (class = (int) ALL_REGS - 1; class > 0; class--)
936 /* Ignore classes that are too small for this operand or
937 invalid for a operand that was auto-incremented. */
938 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
939 > reg_class_size[class]
940 #ifdef FORBIDDEN_INC_DEC_CLASSES
941 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
945 else if (p->cost[class] < best_cost)
947 best_cost = p->cost[class];
948 best = (enum reg_class) class;
950 else if (p->cost[class] == best_cost)
951 best = reg_class_subunion[(int)best][class];
954 /* Record the alternate register class; i.e., a class for which
955 every register in it is better than using memory. If adding a
956 class would make a smaller class (i.e., no union of just those
957 classes exists), skip that class. The major unions of classes
958 should be provided as a register class. Don't do this if we
959 will be doing it again later. */
961 if (pass == 1 || ! flag_expensive_optimizations)
962 for (class = 0; class < N_REG_CLASSES; class++)
963 if (p->cost[class] < p->mem_cost
964 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
965 > reg_class_size[(int) alt])
966 #ifdef FORBIDDEN_INC_DEC_CLASSES
967 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
970 alt = reg_class_subunion[(int) alt][class];
972 /* If we don't add any classes, nothing to try. */
976 /* We cast to (int) because (char) hits bugs in some compilers. */
977 prefclass[i] = (int) best;
978 altclass[i] = (int) alt;
981 #endif /* REGISTER_CONSTRAINTS */
984 #ifdef REGISTER_CONSTRAINTS
986 /* Record the cost of using memory or registers of various classes for
987 the operands in INSN.
989 N_ALTS is the number of alternatives.
991 N_OPS is the number of operands.
993 OPS is an array of the operands.
995 MODES are the modes of the operands, in case any are VOIDmode.
997 CONSTRAINTS are the constraints to use for the operands. This array
998 is modified by this procedure.
1000 This procedure works alternative by alternative. For each alternative
1001 we assume that we will be able to allocate all pseudos to their ideal
1002 register class and calculate the cost of using that alternative. Then
1003 we compute for each operand that is a pseudo-register, the cost of
1004 having the pseudo allocated to each register class and using it in that
1005 alternative. To this cost is added the cost of the alternative.
1007 The cost of each class for this insn is its lowest cost among all the
1011 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1015 enum machine_mode *modes;
1020 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1024 /* By default, each operand is an input operand. */
1026 for (i = 0; i < n_ops; i++)
1027 op_types[i] = OP_READ;
1029 /* Process each alternative, each time minimizing an operand's cost with
1030 the cost for each operand in that alternative. */
1032 for (alt = 0; alt < n_alts; alt++)
1034 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1037 enum reg_class classes[MAX_RECOG_OPERANDS];
1040 for (i = 0; i < n_ops; i++)
1042 char *p = constraints[i];
1044 enum machine_mode mode = modes[i];
1049 /* If this operand has no constraints at all, we can conclude
1050 nothing about it since anything is valid. */
1054 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1055 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1063 /* If this alternative is only relevant when this operand
1064 matches a previous operand, we do different things depending
1065 on whether this operand is a pseudo-reg or not. */
1067 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1070 classes[i] = classes[j];
1072 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1074 /* If this matches the other operand, we have no added
1076 if (rtx_equal_p (ops[j], op))
1079 /* If we can put the other operand into a register, add to
1080 the cost of this alternative the cost to copy this
1081 operand to the register used for the other operand. */
1083 else if (classes[j] != NO_REGS)
1084 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1086 else if (GET_CODE (ops[j]) != REG
1087 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1089 /* This op is a pseudo but the one it matches is not. */
1091 /* If we can't put the other operand into a register, this
1092 alternative can't be used. */
1094 if (classes[j] == NO_REGS)
1097 /* Otherwise, add to the cost of this alternative the cost
1098 to copy the other operand to the register used for this
1102 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1106 /* The costs of this operand are the same as that of the
1107 other operand. However, if we cannot tie them, this
1108 alternative needs to do a copy, which is one
1111 this_op_costs[i] = this_op_costs[j];
1112 if (REGNO (ops[i]) != REGNO (ops[j])
1113 && ! find_reg_note (insn, REG_DEAD, op))
1116 /* This is in place of ordinary cost computation
1117 for this operand, so skip to the end of the
1118 alternative (should be just one character). */
1119 while (*p && *p++ != ',')
1127 /* Scan all the constraint letters. See if the operand matches
1128 any of the constraints. Collect the valid register classes
1129 and see if this operand accepts memory. */
1131 classes[i] = NO_REGS;
1132 while (*p && (c = *p++) != ',')
1136 op_types[i] = OP_WRITE;
1140 op_types[i] = OP_READ_WRITE;
1144 /* Ignore the next letter for this pass. */
1149 case '?': case '!': case '#':
1151 case '0': case '1': case '2': case '3': case '4':
1155 case 'm': case 'o': case 'V':
1156 /* It doesn't seem worth distinguishing between offsettable
1157 and non-offsettable addresses here. */
1159 if (GET_CODE (op) == MEM)
1164 if (GET_CODE (op) == MEM
1165 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1166 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1171 if (GET_CODE (op) == MEM
1172 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1173 || GET_CODE (XEXP (op, 0)) == POST_INC))
1178 #ifndef REAL_ARITHMETIC
1179 /* Match any floating double constant, but only if
1180 we can examine the bits of it reliably. */
1181 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1182 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1183 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1186 if (GET_CODE (op) == CONST_DOUBLE)
1191 if (GET_CODE (op) == CONST_DOUBLE)
1197 if (GET_CODE (op) == CONST_DOUBLE
1198 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1203 if (GET_CODE (op) == CONST_INT
1204 || (GET_CODE (op) == CONST_DOUBLE
1205 && GET_MODE (op) == VOIDmode))
1209 #ifdef LEGITIMATE_PIC_OPERAND_P
1210 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1217 if (GET_CODE (op) == CONST_INT
1218 || (GET_CODE (op) == CONST_DOUBLE
1219 && GET_MODE (op) == VOIDmode))
1231 if (GET_CODE (op) == CONST_INT
1232 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1240 #ifdef EXTRA_CONSTRAINT
1246 if (EXTRA_CONSTRAINT (op, c))
1252 if (GET_CODE (op) == MEM
1254 #ifdef LEGITIMATE_PIC_OPERAND_P
1255 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1262 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1267 = reg_class_subunion[(int) classes[i]]
1268 [(int) REG_CLASS_FROM_LETTER (c)];
1273 /* How we account for this operand now depends on whether it is a
1274 pseudo register or not. If it is, we first check if any
1275 register classes are valid. If not, we ignore this alternative,
1276 since we want to assume that all pseudos get allocated for
1277 register preferencing. If some register class is valid, compute
1278 the costs of moving the pseudo into that class. */
1280 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1282 if (classes[i] == NO_REGS)
1286 struct costs *pp = &this_op_costs[i];
1288 for (class = 0; class < N_REG_CLASSES; class++)
1289 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1291 /* If the alternative actually allows memory, make things
1292 a bit cheaper since we won't need an extra insn to
1295 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1297 /* If we have assigned a class to this register in our
1298 first pass, add a cost to this alternative corresponding
1299 to what we would add if this register were not in the
1300 appropriate class. */
1304 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1308 /* Otherwise, if this alternative wins, either because we
1309 have already determined that or if we have a hard register of
1310 the proper class, there is no cost for this alternative. */
1313 || (GET_CODE (op) == REG
1314 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1317 /* If registers are valid, the cost of this alternative includes
1318 copying the object to and/or from a register. */
1320 else if (classes[i] != NO_REGS)
1322 if (op_types[i] != OP_WRITE)
1323 alt_cost += copy_cost (op, mode, classes[i], 1);
1325 if (op_types[i] != OP_READ)
1326 alt_cost += copy_cost (op, mode, classes[i], 0);
1329 /* The only other way this alternative can be used is if this is a
1330 constant that could be placed into memory. */
1332 else if (CONSTANT_P (op) && allows_mem)
1333 alt_cost += MEMORY_MOVE_COST (mode);
1341 /* Finally, update the costs with the information we've calculated
1342 about this alternative. */
1344 for (i = 0; i < n_ops; i++)
1345 if (GET_CODE (ops[i]) == REG
1346 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1348 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1349 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1351 pp->mem_cost = MIN (pp->mem_cost,
1352 (qq->mem_cost + alt_cost) * scale);
1354 for (class = 0; class < N_REG_CLASSES; class++)
1355 pp->cost[class] = MIN (pp->cost[class],
1356 (qq->cost[class] + alt_cost) * scale);
1360 /* If this insn is a single set copying operand 1 to operand 0
1361 and one is a pseudo with the other a hard reg that is in its
1362 own register class, set the cost of that register class to -1. */
1364 if ((set = single_set (insn)) != 0
1365 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1366 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1367 for (i = 0; i <= 1; i++)
1368 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1370 int regno = REGNO (ops[!i]);
1371 enum machine_mode mode = GET_MODE (ops[!i]);
1375 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1376 && (reg_class_size[prefclass[regno]]
1377 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1378 op_costs[i].cost[prefclass[regno]] = -1;
1379 else if (regno < FIRST_PSEUDO_REGISTER)
1380 for (class = 0; class < N_REG_CLASSES; class++)
1381 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1382 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1384 if (reg_class_size[class] == 1)
1385 op_costs[i].cost[class] = -1;
1388 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1390 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1394 if (nr == HARD_REGNO_NREGS(regno,mode))
1395 op_costs[i].cost[class] = -1;
1401 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1402 TO_P is zero) a register of class CLASS in mode MODE.
1404 X must not be a pseudo. */
1407 copy_cost (x, mode, class, to_p)
1409 enum machine_mode mode;
1410 enum reg_class class;
1413 enum reg_class secondary_class = NO_REGS;
1415 /* If X is a SCRATCH, there is actually nothing to move since we are
1416 assuming optimal allocation. */
1418 if (GET_CODE (x) == SCRATCH)
1421 /* Get the class we will actually use for a reload. */
1422 class = PREFERRED_RELOAD_CLASS (x, class);
1424 #ifdef HAVE_SECONDARY_RELOADS
1425 /* If we need a secondary reload (we assume here that we are using
1426 the secondary reload as an intermediate, not a scratch register), the
1427 cost is that to load the input into the intermediate register, then
1428 to copy them. We use a special value of TO_P to avoid recursion. */
1430 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1432 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1435 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1437 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1440 if (secondary_class != NO_REGS)
1441 return (move_cost[(int) secondary_class][(int) class]
1442 + copy_cost (x, mode, secondary_class, 2));
1443 #endif /* HAVE_SECONDARY_RELOADS */
1445 /* For memory, use the memory move cost, for (hard) registers, use the
1446 cost to move between the register classes, and use 2 for everything
1447 else (constants). */
1449 if (GET_CODE (x) == MEM || class == NO_REGS)
1450 return MEMORY_MOVE_COST (mode);
1452 else if (GET_CODE (x) == REG)
1453 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1456 /* If this is a constant, we may eventually want to call rtx_cost here. */
1460 /* Record the pseudo registers we must reload into hard registers
1461 in a subexpression of a memory address, X.
1463 CLASS is the class that the register needs to be in and is either
1464 BASE_REG_CLASS or INDEX_REG_CLASS.
1466 SCALE is twice the amount to multiply the cost by (it is twice so we
1467 can represent half-cost adjustments). */
1470 record_address_regs (x, class, scale)
1472 enum reg_class class;
1475 register enum rtx_code code = GET_CODE (x);
1488 /* When we have an address that is a sum,
1489 we must determine whether registers are "base" or "index" regs.
1490 If there is a sum of two registers, we must choose one to be
1491 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1492 to make a good choice most of the time. We only need to do this
1493 on machines that can have two registers in an address and where
1494 the base and index register classes are different.
1496 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1497 that seems bogus since it should only be set when we are sure
1498 the register is being used as a pointer. */
1501 rtx arg0 = XEXP (x, 0);
1502 rtx arg1 = XEXP (x, 1);
1503 register enum rtx_code code0 = GET_CODE (arg0);
1504 register enum rtx_code code1 = GET_CODE (arg1);
1506 /* Look inside subregs. */
1507 if (code0 == SUBREG)
1508 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1509 if (code1 == SUBREG)
1510 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1512 /* If this machine only allows one register per address, it must
1513 be in the first operand. */
1515 if (MAX_REGS_PER_ADDRESS == 1)
1516 record_address_regs (arg0, class, scale);
1518 /* If index and base registers are the same on this machine, just
1519 record registers in any non-constant operands. We assume here,
1520 as well as in the tests below, that all addresses are in
1523 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1525 record_address_regs (arg0, class, scale);
1526 if (! CONSTANT_P (arg1))
1527 record_address_regs (arg1, class, scale);
1530 /* If the second operand is a constant integer, it doesn't change
1531 what class the first operand must be. */
1533 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1534 record_address_regs (arg0, class, scale);
1536 /* If the second operand is a symbolic constant, the first operand
1537 must be an index register. */
1539 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1540 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1542 /* If this the sum of two registers where the first is known to be a
1543 pointer, it must be a base register with the second an index. */
1545 else if (code0 == REG && code1 == REG
1546 && REGNO_POINTER_FLAG (REGNO (arg0)))
1548 record_address_regs (arg0, BASE_REG_CLASS, scale);
1549 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1552 /* If this is the sum of two registers and neither is known to
1553 be a pointer, count equal chances that each might be a base
1554 or index register. This case should be rare. */
1556 else if (code0 == REG && code1 == REG
1557 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1558 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1560 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1561 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1562 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1563 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1566 /* In all other cases, the first operand is an index and the
1567 second is the base. */
1571 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1572 record_address_regs (arg1, BASE_REG_CLASS, scale);
1581 /* Double the importance of a pseudo register that is incremented
1582 or decremented, since it would take two extra insns
1583 if it ends up in the wrong place. If the operand is a pseudo,
1584 show it is being used in an INC_DEC context. */
1586 #ifdef FORBIDDEN_INC_DEC_CLASSES
1587 if (GET_CODE (XEXP (x, 0)) == REG
1588 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1589 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1592 record_address_regs (XEXP (x, 0), class, 2 * scale);
1597 register struct costs *pp = &costs[REGNO (x)];
1600 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1602 for (i = 0; i < N_REG_CLASSES; i++)
1603 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1609 register char *fmt = GET_RTX_FORMAT (code);
1611 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1613 record_address_regs (XEXP (x, i), class, scale);
1618 #ifdef FORBIDDEN_INC_DEC_CLASSES
1620 /* Return 1 if REG is valid as an auto-increment memory reference
1621 to an object of MODE. */
1624 auto_inc_dec_reg_p (reg, mode)
1626 enum machine_mode mode;
1628 #ifdef HAVE_POST_INCREMENT
1629 if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg)))
1633 #ifdef HAVE_POST_DECREMENT
1634 if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg)))
1638 #ifdef HAVE_PRE_INCREMENT
1639 if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg)))
1643 #ifdef HAVE_PRE_DECREMENT
1644 if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg)))
1652 #endif /* REGISTER_CONSTRAINTS */
1654 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1655 reg_scan and flow_analysis that are indexed by the register number. If
1656 NEW_P is non zero, initialize all of the registers, otherwise only
1657 initialize the new registers allocated. The same table is kept from
1658 function to function, only reallocating it when we need more room. If
1659 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1662 allocate_reg_info (num_regs, new_p, renumber_p)
1667 static int regno_allocated = 0;
1668 static int regno_max = 0;
1669 static short *renumber = (short *)0;
1673 int min = (new_p) ? 0 : regno_max;
1675 /* If this message come up, and you want to fix it, then all of the tables
1676 like reg_renumber, etc. that use short will have to be found and lengthed
1677 to int or HOST_WIDE_INT. */
1679 /* Free up all storage allocated */
1684 free ((char *)reg_n_info);
1685 free ((char *)renumber);
1686 reg_n_info = (reg_info *)0;
1687 renumber = (short *)0;
1689 regno_allocated = 0;
1694 if (num_regs > regno_allocated)
1696 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1697 size_info = regno_allocated * sizeof (reg_info);
1698 size_renumber = regno_allocated * sizeof (short);
1702 reg_n_info = (reg_info *) xmalloc (size_info);
1703 renumber = (short *) xmalloc (size_renumber);
1706 else if (new_p) /* if we're zapping everything, no need to realloc */
1708 free ((char *)reg_n_info);
1709 free ((char *)renumber);
1710 reg_n_info = (reg_info *) xmalloc (size_info);
1711 renumber = (short *) xmalloc (size_renumber);
1716 reg_n_info = (reg_info *) xrealloc ((char *)reg_n_info, size_info);
1717 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1723 bzero ((char *) ®_n_info[min], (num_regs - min) * sizeof (reg_info));
1724 for (i = min; i < num_regs; i++)
1726 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1732 reg_renumber = renumber;
1734 /* Tell the regset code about the new number of registers */
1735 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1737 regno_max = num_regs;
1741 /* This is the `regscan' pass of the compiler, run just before cse
1742 and again just before loop.
1744 It finds the first and last use of each pseudo-register
1745 and records them in the vectors regno_first_uid, regno_last_uid
1746 and counts the number of sets in the vector reg_n_sets.
1748 REPEAT is nonzero the second time this is called. */
1750 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1751 Always at least 3, since the combiner could put that many together
1752 and we want this to remain correct for all the remaining passes. */
1757 reg_scan (f, nregs, repeat)
1764 allocate_reg_info (nregs, TRUE, FALSE);
1767 for (insn = f; insn; insn = NEXT_INSN (insn))
1768 if (GET_CODE (insn) == INSN
1769 || GET_CODE (insn) == CALL_INSN
1770 || GET_CODE (insn) == JUMP_INSN)
1772 if (GET_CODE (PATTERN (insn)) == PARALLEL
1773 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1774 max_parallel = XVECLEN (PATTERN (insn), 0);
1775 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1777 if (REG_NOTES (insn))
1778 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1782 /* X is the expression to scan. INSN is the insn it appears in.
1783 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1786 reg_scan_mark_refs (x, insn, note_flag)
1791 register enum rtx_code code = GET_CODE (x);
1810 register int regno = REGNO (x);
1812 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
1814 REGNO_LAST_UID (regno) = INSN_UID (insn);
1815 if (REGNO_FIRST_UID (regno) == 0)
1816 REGNO_FIRST_UID (regno) = INSN_UID (insn);
1822 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1824 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1829 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1833 /* Count a set of the destination if it is a register. */
1834 for (dest = SET_DEST (x);
1835 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1836 || GET_CODE (dest) == ZERO_EXTEND;
1837 dest = XEXP (dest, 0))
1840 if (GET_CODE (dest) == REG)
1841 REG_N_SETS (REGNO (dest))++;
1843 /* If this is setting a pseudo from another pseudo or the sum of a
1844 pseudo and a constant integer and the other pseudo is known to be
1845 a pointer, set the destination to be a pointer as well.
1847 Likewise if it is setting the destination from an address or from a
1848 value equivalent to an address or to the sum of an address and
1851 But don't do any of this if the pseudo corresponds to a user
1852 variable since it should have already been set as a pointer based
1855 if (GET_CODE (SET_DEST (x)) == REG
1856 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
1857 && ! REG_USERVAR_P (SET_DEST (x))
1858 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
1859 && ((GET_CODE (SET_SRC (x)) == REG
1860 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
1861 || ((GET_CODE (SET_SRC (x)) == PLUS
1862 || GET_CODE (SET_SRC (x)) == LO_SUM)
1863 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1864 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
1865 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
1866 || GET_CODE (SET_SRC (x)) == CONST
1867 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
1868 || GET_CODE (SET_SRC (x)) == LABEL_REF
1869 || (GET_CODE (SET_SRC (x)) == HIGH
1870 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
1871 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
1872 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
1873 || ((GET_CODE (SET_SRC (x)) == PLUS
1874 || GET_CODE (SET_SRC (x)) == LO_SUM)
1875 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
1876 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
1877 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
1878 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
1879 && (GET_CODE (XEXP (note, 0)) == CONST
1880 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
1881 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
1882 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
1884 /* ... fall through ... */
1888 register char *fmt = GET_RTX_FORMAT (code);
1890 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1893 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
1894 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1897 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1898 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
1905 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1909 reg_class_subset_p (c1, c2)
1910 register enum reg_class c1;
1911 register enum reg_class c2;
1913 if (c1 == c2) return 1;
1918 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1919 reg_class_contents[(int)c2],
1924 /* Return nonzero if there is a register that is in both C1 and C2. */
1927 reg_classes_intersect_p (c1, c2)
1928 register enum reg_class c1;
1929 register enum reg_class c2;
1936 if (c1 == c2) return 1;
1938 if (c1 == ALL_REGS || c2 == ALL_REGS)
1941 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1942 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1944 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
1951 /* Release any memory allocated by register sets. */
1954 regset_release_memory ()
1956 if (basic_block_live_at_start)
1958 free_regset_vector (basic_block_live_at_start, n_basic_blocks);
1959 basic_block_live_at_start = 0;
1962 FREE_REG_SET (regs_live_at_setjmp);
1963 bitmap_release_memory ();