1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "coretypes.h"
31 #include "hard-reg-set.h"
36 #include "basic-block.h"
39 #include "insn-config.h"
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
50 static void init_reg_autoinc PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs[FIRST_PSEUDO_REGISTER];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set;
75 /* Data for initializing the above. */
77 static const char initial_fixed_regs[] = FIXED_REGISTERS;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs[FIRST_PSEUDO_REGISTER];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set;
94 /* Data for initializing the above. */
96 static const char initial_call_used_regs[] = CALL_USED_REGISTERS;
98 /* This is much like call_used_regs, except it doesn't have to
99 be a superset of FIXED_REGISTERS. This vector indicates
100 what is really call clobbered, and is used when defining
101 regs_invalidated_by_call. */
103 #ifdef CALL_REALLY_USED_REGISTERS
104 char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS;
107 /* Indexed by hard register number, contains 1 for registers that are
108 fixed use or call used registers that cannot hold quantities across
109 calls even if we are willing to save and restore them. call fixed
110 registers are a subset of call used registers. */
112 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
114 /* The same info as a HARD_REG_SET. */
116 HARD_REG_SET call_fixed_reg_set;
118 /* Number of non-fixed registers. */
120 int n_non_fixed_regs;
122 /* Indexed by hard register number, contains 1 for registers
123 that are being used for global register decls.
124 These must be exempt from ordinary flow analysis
125 and are also considered fixed. */
127 char global_regs[FIRST_PSEUDO_REGISTER];
129 /* Contains 1 for registers that are set or clobbered by calls. */
130 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
131 for someone's bright idea to have call_used_regs strictly include
132 fixed_regs. Which leaves us guessing as to the set of fixed_regs
133 that are actually preserved. We know for sure that those associated
134 with the local stack frame are safe, but scant others. */
136 HARD_REG_SET regs_invalidated_by_call;
138 /* Table of register numbers in the order in which to try to use them. */
139 #ifdef REG_ALLOC_ORDER
140 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
142 /* The inverse of reg_alloc_order. */
143 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
146 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
148 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
150 /* The same information, but as an array of unsigned ints. We copy from
151 these unsigned ints to the table above. We do this so the tm.h files
152 do not have to be aware of the wordsize for machines with <= 64 regs.
153 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
156 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
158 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
159 = REG_CLASS_CONTENTS;
161 /* For each reg class, number of regs it contains. */
163 unsigned int reg_class_size[N_REG_CLASSES];
165 /* For each reg class, table listing all the containing classes. */
167 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
169 /* For each reg class, table listing all the classes contained in it. */
171 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
173 /* For each pair of reg classes,
174 a largest reg class contained in their union. */
176 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
178 /* For each pair of reg classes,
179 the smallest reg class containing their union. */
181 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
183 /* Array containing all of the register names. Unless
184 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
186 #ifdef DEBUG_REGISTER_NAMES
187 const char * reg_names[] = REGISTER_NAMES;
190 /* For each hard register, the widest mode object that it can contain.
191 This will be a MODE_INT mode if the register can hold integers. Otherwise
192 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
195 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
197 /* 1 if class does contain register of given mode. */
199 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
201 /* Maximum cost of moving from a register in one class to a register in
202 another class. Based on REGISTER_MOVE_COST. */
204 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
206 /* Similar, but here we don't have to move if the first index is a subset
207 of the second so in that case the cost is zero. */
209 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
211 /* Similar, but here we don't have to move if the first index is a superset
212 of the second so in that case the cost is zero. */
214 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
216 #ifdef FORBIDDEN_INC_DEC_CLASSES
218 /* These are the classes that regs which are auto-incremented or decremented
221 static int forbidden_inc_dec_class[N_REG_CLASSES];
223 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
226 static char *in_inc_dec;
228 #endif /* FORBIDDEN_INC_DEC_CLASSES */
230 #ifdef CANNOT_CHANGE_MODE_CLASS
231 /* All registers that have been subreged. Indexed by regno * MAX_MACHINE_MODE
233 bitmap_head subregs_of_mode;
236 /* Sample MEM values for use by memory_move_secondary_cost. */
238 static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE];
240 /* Linked list of reg_info structures allocated for reg_n_info array.
241 Grouping all of the allocated structures together in one lump
242 means only one call to bzero to clear them, rather than n smaller
244 struct reg_info_data {
245 struct reg_info_data *next; /* next set of reg_info structures */
246 size_t min_index; /* minimum index # */
247 size_t max_index; /* maximum index # */
248 char used_p; /* nonzero if this has been used previously */
249 reg_info data[1]; /* beginning of the reg_info data */
252 static struct reg_info_data *reg_info_head;
254 /* No more global register variables may be declared; true once
255 regclass has been initialized. */
257 static int no_global_reg_vars = 0;
260 /* Function called only once to initialize the above data on reg usage.
261 Once this is done, various switches may override. */
268 /* First copy the register information from the initial int form into
271 for (i = 0; i < N_REG_CLASSES; i++)
273 CLEAR_HARD_REG_SET (reg_class_contents[i]);
275 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
276 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
277 if (int_reg_class_contents[i][j / 32]
278 & ((unsigned) 1 << (j % 32)))
279 SET_HARD_REG_BIT (reg_class_contents[i], j);
282 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
283 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
284 memset (global_regs, 0, sizeof global_regs);
286 /* Do any additional initialization regsets may need. */
287 INIT_ONCE_REG_SET ();
289 #ifdef REG_ALLOC_ORDER
290 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
291 inv_reg_alloc_order[reg_alloc_order[i]] = i;
295 /* After switches have been processed, which perhaps alter
296 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
302 unsigned int /* enum machine_mode */ m;
303 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
305 /* This macro allows the fixed or call-used registers
306 and the register classes to depend on target flags. */
308 #ifdef CONDITIONAL_REGISTER_USAGE
309 CONDITIONAL_REGISTER_USAGE;
312 /* Compute number of hard regs in each class. */
314 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
315 for (i = 0; i < N_REG_CLASSES; i++)
316 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
317 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
320 /* Initialize the table of subunions.
321 reg_class_subunion[I][J] gets the largest-numbered reg-class
322 that is contained in the union of classes I and J. */
324 for (i = 0; i < N_REG_CLASSES; i++)
326 for (j = 0; j < N_REG_CLASSES; j++)
329 register /* Declare it register if it's a scalar. */
334 COPY_HARD_REG_SET (c, reg_class_contents[i]);
335 IOR_HARD_REG_SET (c, reg_class_contents[j]);
336 for (k = 0; k < N_REG_CLASSES; k++)
338 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
343 /* keep the largest subclass */ /* SPEE 900308 */
344 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
345 reg_class_contents[(int) reg_class_subunion[i][j]],
347 reg_class_subunion[i][j] = (enum reg_class) k;
354 /* Initialize the table of superunions.
355 reg_class_superunion[I][J] gets the smallest-numbered reg-class
356 containing the union of classes I and J. */
358 for (i = 0; i < N_REG_CLASSES; i++)
360 for (j = 0; j < N_REG_CLASSES; j++)
363 register /* Declare it register if it's a scalar. */
368 COPY_HARD_REG_SET (c, reg_class_contents[i]);
369 IOR_HARD_REG_SET (c, reg_class_contents[j]);
370 for (k = 0; k < N_REG_CLASSES; k++)
371 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
374 reg_class_superunion[i][j] = (enum reg_class) k;
378 /* Initialize the tables of subclasses and superclasses of each reg class.
379 First clear the whole table, then add the elements as they are found. */
381 for (i = 0; i < N_REG_CLASSES; i++)
383 for (j = 0; j < N_REG_CLASSES; j++)
385 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
386 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
390 for (i = 0; i < N_REG_CLASSES; i++)
392 if (i == (int) NO_REGS)
395 for (j = i + 1; j < N_REG_CLASSES; j++)
399 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
403 /* Reg class I is a subclass of J.
404 Add J to the table of superclasses of I. */
405 p = ®_class_superclasses[i][0];
406 while (*p != LIM_REG_CLASSES) p++;
407 *p = (enum reg_class) j;
408 /* Add I to the table of superclasses of J. */
409 p = ®_class_subclasses[j][0];
410 while (*p != LIM_REG_CLASSES) p++;
411 *p = (enum reg_class) i;
415 /* Initialize "constant" tables. */
417 CLEAR_HARD_REG_SET (fixed_reg_set);
418 CLEAR_HARD_REG_SET (call_used_reg_set);
419 CLEAR_HARD_REG_SET (call_fixed_reg_set);
420 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
422 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
424 n_non_fixed_regs = 0;
426 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
429 SET_HARD_REG_BIT (fixed_reg_set, i);
433 if (call_used_regs[i])
434 SET_HARD_REG_BIT (call_used_reg_set, i);
435 if (call_fixed_regs[i])
436 SET_HARD_REG_BIT (call_fixed_reg_set, i);
437 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
438 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
440 /* There are a couple of fixed registers that we know are safe to
441 exclude from being clobbered by calls:
443 The frame pointer is always preserved across calls. The arg pointer
444 is if it is fixed. The stack pointer usually is, unless
445 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
446 If we are generating PIC code, the PIC offset table register is
447 preserved across calls, though the target can override that. */
449 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM)
451 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
452 else if (i == HARD_FRAME_POINTER_REGNUM)
455 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
456 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
459 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
460 else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i])
464 #ifdef CALL_REALLY_USED_REGISTERS
465 || call_really_used_regs[i]
470 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
473 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
474 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
475 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
476 for (i = 0; i < N_REG_CLASSES; i++)
477 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
478 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
479 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
480 && HARD_REGNO_MODE_OK (j, m))
482 contains_reg_of_mode [i][m] = 1;
483 allocatable_regs_of_mode [m] = 1;
487 /* Initialize the move cost table. Find every subset of each class
488 and take the maximum cost of moving any subset to any other. */
490 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
491 if (allocatable_regs_of_mode [m])
493 for (i = 0; i < N_REG_CLASSES; i++)
494 if (contains_reg_of_mode [i][m])
495 for (j = 0; j < N_REG_CLASSES; j++)
498 enum reg_class *p1, *p2;
500 if (!contains_reg_of_mode [j][m])
502 move_cost[m][i][j] = 65536;
503 may_move_in_cost[m][i][j] = 65536;
504 may_move_out_cost[m][i][j] = 65536;
508 cost = REGISTER_MOVE_COST (m, i, j);
510 for (p2 = ®_class_subclasses[j][0];
511 *p2 != LIM_REG_CLASSES;
513 if (*p2 != i && contains_reg_of_mode [*p2][m])
514 cost = MAX (cost, move_cost [m][i][*p2]);
516 for (p1 = ®_class_subclasses[i][0];
517 *p1 != LIM_REG_CLASSES;
519 if (*p1 != j && contains_reg_of_mode [*p1][m])
520 cost = MAX (cost, move_cost [m][*p1][j]);
522 move_cost[m][i][j] = cost;
524 if (reg_class_subset_p (i, j))
525 may_move_in_cost[m][i][j] = 0;
527 may_move_in_cost[m][i][j] = cost;
529 if (reg_class_subset_p (j, i))
530 may_move_out_cost[m][i][j] = 0;
532 may_move_out_cost[m][i][j] = cost;
536 for (j = 0; j < N_REG_CLASSES; j++)
538 move_cost[m][i][j] = 65536;
539 may_move_in_cost[m][i][j] = 65536;
540 may_move_out_cost[m][i][j] = 65536;
545 /* Compute the table of register modes.
546 These values are used to record death information for individual registers
547 (as opposed to a multi-register mode). */
554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
556 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
558 /* If we couldn't find a valid mode, just use the previous mode.
559 ??? One situation in which we need to do this is on the mips where
560 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
561 to use DF mode for the even registers and VOIDmode for the odd
562 (for the cpu models where the odd ones are inaccessible). */
563 if (reg_raw_mode[i] == VOIDmode)
564 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
568 /* Finish initializing the register sets and
569 initialize the register modes. */
574 /* This finishes what was started by init_reg_sets, but couldn't be done
575 until after register usage was specified. */
583 /* Initialize some fake stack-frame MEM references for use in
584 memory_move_secondary_cost. */
587 init_fake_stack_mems ()
589 #ifdef HAVE_SECONDARY_RELOADS
593 for (i = 0; i < MAX_MACHINE_MODE; i++)
594 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
599 #ifdef HAVE_SECONDARY_RELOADS
601 /* Compute extra cost of moving registers to/from memory due to reloads.
602 Only needed if secondary reloads are required for memory moves. */
605 memory_move_secondary_cost (mode, class, in)
606 enum machine_mode mode;
607 enum reg_class class;
610 enum reg_class altclass;
611 int partial_cost = 0;
612 /* We need a memory reference to feed to SECONDARY... macros. */
613 /* mem may be unused even if the SECONDARY_ macros are defined. */
614 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
619 #ifdef SECONDARY_INPUT_RELOAD_CLASS
620 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
627 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
628 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
634 if (altclass == NO_REGS)
638 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
640 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
642 if (class == altclass)
643 /* This isn't simply a copy-to-temporary situation. Can't guess
644 what it is, so MEMORY_MOVE_COST really ought not to be calling
647 I'm tempted to put in an abort here, but returning this will
648 probably only give poor estimates, which is what we would've
649 had before this code anyways. */
652 /* Check if the secondary reload register will also need a
654 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
658 /* Return a machine mode that is legitimate for hard reg REGNO and large
659 enough to save nregs. If we can't find one, return VOIDmode. */
662 choose_hard_reg_mode (regno, nregs)
663 unsigned int regno ATTRIBUTE_UNUSED;
666 unsigned int /* enum machine_mode */ m;
667 enum machine_mode found_mode = VOIDmode, mode;
669 /* We first look for the largest integer mode that can be validly
670 held in REGNO. If none, we look for the largest floating-point mode.
671 If we still didn't find a valid mode, try CCmode. */
673 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
675 mode = GET_MODE_WIDER_MODE (mode))
676 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
677 && HARD_REGNO_MODE_OK (regno, mode))
680 if (found_mode != VOIDmode)
683 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
685 mode = GET_MODE_WIDER_MODE (mode))
686 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
687 && HARD_REGNO_MODE_OK (regno, mode))
690 if (found_mode != VOIDmode)
693 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
695 mode = GET_MODE_WIDER_MODE (mode))
696 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
697 && HARD_REGNO_MODE_OK (regno, mode))
700 if (found_mode != VOIDmode)
703 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
705 mode = GET_MODE_WIDER_MODE (mode))
706 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
707 && HARD_REGNO_MODE_OK (regno, mode))
710 if (found_mode != VOIDmode)
713 /* Iterate over all of the CCmodes. */
714 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
716 mode = (enum machine_mode) m;
717 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs
718 && HARD_REGNO_MODE_OK (regno, mode))
722 /* We can't find a mode valid for this register. */
726 /* Specify the usage characteristics of the register named NAME.
727 It should be a fixed register if FIXED and a
728 call-used register if CALL_USED. */
731 fix_register (name, fixed, call_used)
733 int fixed, call_used;
737 /* Decode the name and update the primary form of
738 the register info. */
740 if ((i = decode_reg_name (name)) >= 0)
742 if ((i == STACK_POINTER_REGNUM
743 #ifdef HARD_FRAME_POINTER_REGNUM
744 || i == HARD_FRAME_POINTER_REGNUM
746 || i == FRAME_POINTER_REGNUM
749 && (fixed == 0 || call_used == 0))
751 static const char * const what_option[2][2] = {
752 { "call-saved", "call-used" },
753 { "no-such-option", "fixed" }};
755 error ("can't use '%s' as a %s register", name,
756 what_option[fixed][call_used]);
760 fixed_regs[i] = fixed;
761 call_used_regs[i] = call_used;
762 #ifdef CALL_REALLY_USED_REGISTERS
764 call_really_used_regs[i] = call_used;
770 warning ("unknown register name: %s", name);
774 /* Mark register number I as global. */
780 if (fixed_regs[i] == 0 && no_global_reg_vars)
781 error ("global register variable follows a function definition");
785 warning ("register used for two global register variables");
789 if (call_used_regs[i] && ! fixed_regs[i])
790 warning ("call-clobbered register used for global register variable");
794 /* If already fixed, nothing else to do. */
798 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
801 SET_HARD_REG_BIT (fixed_reg_set, i);
802 SET_HARD_REG_BIT (call_used_reg_set, i);
803 SET_HARD_REG_BIT (call_fixed_reg_set, i);
804 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
807 /* Now the data and code for the `regclass' pass, which happens
808 just before local-alloc. */
810 /* The `costs' struct records the cost of using a hard register of each class
811 and of using memory for each pseudo. We use this data to set up
812 register class preferences. */
816 int cost[N_REG_CLASSES];
820 /* Structure used to record preferences of given pseudo. */
823 /* (enum reg_class) prefclass is the preferred class. */
826 /* altclass is a register class that we should use for allocating
827 pseudo if no register in the preferred class is available.
828 If no register in this class is available, memory is preferred.
830 It might appear to be more general to have a bitmask of classes here,
831 but since it is recommended that there be a class corresponding to the
832 union of most major pair of classes, that generality is not required. */
836 /* Record the cost of each class for each pseudo. */
838 static struct costs *costs;
840 /* Initialized once, and used to initialize cost values for each insn. */
842 static struct costs init_cost;
844 /* Record preferences of each pseudo.
845 This is available after `regclass' is run. */
847 static struct reg_pref *reg_pref;
849 /* Allocated buffers for reg_pref. */
851 static struct reg_pref *reg_pref_buffer;
853 /* Frequency of executions of current insn. */
855 static int frequency;
857 static rtx scan_one_insn PARAMS ((rtx, int));
858 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
859 static void dump_regclass PARAMS ((FILE *));
860 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
862 struct costs *, struct reg_pref *));
863 static int copy_cost PARAMS ((rtx, enum machine_mode,
864 enum reg_class, int));
865 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
866 #ifdef FORBIDDEN_INC_DEC_CLASSES
867 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
869 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
871 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
872 This function is sometimes called before the info has been computed.
873 When that happens, just return GENERAL_REGS, which is innocuous. */
876 reg_preferred_class (regno)
881 return (enum reg_class) reg_pref[regno].prefclass;
885 reg_alternate_class (regno)
891 return (enum reg_class) reg_pref[regno].altclass;
894 /* Initialize some global data for this pass. */
901 init_cost.mem_cost = 10000;
902 for (i = 0; i < N_REG_CLASSES; i++)
903 init_cost.cost[i] = 10000;
905 /* This prevents dump_flow_info from losing if called
906 before regclass is run. */
909 /* No more global register variables may be declared. */
910 no_global_reg_vars = 1;
913 /* Dump register costs. */
918 static const char *const reg_class_names[] = REG_CLASS_NAMES;
920 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
922 int /* enum reg_class */ class;
925 fprintf (dump, " Register %i costs:", i);
926 for (class = 0; class < (int) N_REG_CLASSES; class++)
927 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
928 #ifdef FORBIDDEN_INC_DEC_CLASSES
930 || !forbidden_inc_dec_class[(enum reg_class) class])
932 #ifdef CANNOT_CHANGE_MODE_CLASS
933 && ! invalid_mode_change_p (i, (enum reg_class) class,
934 PSEUDO_REGNO_MODE (i))
937 fprintf (dump, " %s:%i", reg_class_names[class],
938 costs[i].cost[(enum reg_class) class]);
939 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
945 /* Calculate the costs of insn operands. */
948 record_operand_costs (insn, op_costs, reg_pref)
950 struct costs *op_costs;
951 struct reg_pref *reg_pref;
953 const char *constraints[MAX_RECOG_OPERANDS];
954 enum machine_mode modes[MAX_RECOG_OPERANDS];
957 for (i = 0; i < recog_data.n_operands; i++)
959 constraints[i] = recog_data.constraints[i];
960 modes[i] = recog_data.operand_mode[i];
963 /* If we get here, we are set up to record the costs of all the
964 operands for this insn. Start by initializing the costs.
965 Then handle any address registers. Finally record the desired
966 classes for any pseudos, doing it twice if some pair of
967 operands are commutative. */
969 for (i = 0; i < recog_data.n_operands; i++)
971 op_costs[i] = init_cost;
973 if (GET_CODE (recog_data.operand[i]) == SUBREG)
974 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
976 if (GET_CODE (recog_data.operand[i]) == MEM)
977 record_address_regs (XEXP (recog_data.operand[i], 0),
978 MODE_BASE_REG_CLASS (modes[i]), frequency * 2);
979 else if (constraints[i][0] == 'p'
980 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i]))
981 record_address_regs (recog_data.operand[i],
982 MODE_BASE_REG_CLASS (modes[i]), frequency * 2);
985 /* Check for commutative in a separate loop so everything will
986 have been initialized. We must do this even if one operand
987 is a constant--see addsi3 in m68k.md. */
989 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
990 if (constraints[i][0] == '%')
992 const char *xconstraints[MAX_RECOG_OPERANDS];
995 /* Handle commutative operands by swapping the constraints.
996 We assume the modes are the same. */
998 for (j = 0; j < recog_data.n_operands; j++)
999 xconstraints[j] = constraints[j];
1001 xconstraints[i] = constraints[i+1];
1002 xconstraints[i+1] = constraints[i];
1003 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1004 recog_data.operand, modes,
1005 xconstraints, insn, op_costs, reg_pref);
1008 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1009 recog_data.operand, modes,
1010 constraints, insn, op_costs, reg_pref);
1013 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1014 time it would save code to put a certain register in a certain class.
1015 PASS, when nonzero, inhibits some optimizations which need only be done
1017 Return the last insn processed, so that the scan can be continued from
1021 scan_one_insn (insn, pass)
1025 enum rtx_code code = GET_CODE (insn);
1026 enum rtx_code pat_code;
1029 struct costs op_costs[MAX_RECOG_OPERANDS];
1031 if (GET_RTX_CLASS (code) != 'i')
1034 pat_code = GET_CODE (PATTERN (insn));
1036 || pat_code == CLOBBER
1037 || pat_code == ASM_INPUT
1038 || pat_code == ADDR_VEC
1039 || pat_code == ADDR_DIFF_VEC)
1042 set = single_set (insn);
1043 extract_insn (insn);
1045 /* If this insn loads a parameter from its stack slot, then
1046 it represents a savings, rather than a cost, if the
1047 parameter is stored in memory. Record this fact. */
1049 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1050 && GET_CODE (SET_SRC (set)) == MEM
1051 && (note = find_reg_note (insn, REG_EQUIV,
1053 && GET_CODE (XEXP (note, 0)) == MEM)
1055 costs[REGNO (SET_DEST (set))].mem_cost
1056 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1059 record_address_regs (XEXP (SET_SRC (set), 0),
1060 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2);
1064 /* Improve handling of two-address insns such as
1065 (set X (ashift CONST Y)) where CONST must be made to
1066 match X. Change it into two insns: (set X CONST)
1067 (set X (ashift X Y)). If we left this for reloading, it
1068 would probably get three insns because X and Y might go
1069 in the same place. This prevents X and Y from receiving
1072 We can only do this if the modes of operands 0 and 1
1073 (which might not be the same) are tieable and we only need
1074 do this during our first pass. */
1076 if (pass == 0 && optimize
1077 && recog_data.n_operands >= 3
1078 && recog_data.constraints[1][0] == '0'
1079 && recog_data.constraints[1][1] == 0
1080 && CONSTANT_P (recog_data.operand[1])
1081 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1082 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1083 && GET_CODE (recog_data.operand[0]) == REG
1084 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1085 recog_data.operand_mode[1]))
1087 rtx previnsn = prev_real_insn (insn);
1089 = gen_lowpart (recog_data.operand_mode[1],
1090 recog_data.operand[0]);
1092 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1094 /* If this insn was the start of a basic block,
1095 include the new insn in that block.
1096 We need not check for code_label here;
1097 while a basic block can start with a code_label,
1098 INSN could not be at the beginning of that block. */
1099 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1103 if (insn == b->head)
1107 /* This makes one more setting of new insns's dest. */
1108 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1109 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1110 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1112 *recog_data.operand_loc[1] = recog_data.operand[0];
1113 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1114 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1115 for (i = recog_data.n_dups - 1; i >= 0; i--)
1116 if (recog_data.dup_num[i] == 1)
1118 *recog_data.dup_loc[i] = recog_data.operand[0];
1119 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1120 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1123 return PREV_INSN (newinsn);
1126 record_operand_costs (insn, op_costs, reg_pref);
1128 /* Now add the cost for each operand to the total costs for
1131 for (i = 0; i < recog_data.n_operands; i++)
1132 if (GET_CODE (recog_data.operand[i]) == REG
1133 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1135 int regno = REGNO (recog_data.operand[i]);
1136 struct costs *p = &costs[regno], *q = &op_costs[i];
1138 p->mem_cost += q->mem_cost * frequency;
1139 for (j = 0; j < N_REG_CLASSES; j++)
1140 p->cost[j] += q->cost[j] * frequency;
1146 /* Initialize information about which register classes can be used for
1147 pseudos that are auto-incremented or auto-decremented. */
1152 #ifdef FORBIDDEN_INC_DEC_CLASSES
1155 for (i = 0; i < N_REG_CLASSES; i++)
1157 rtx r = gen_rtx_raw_REG (VOIDmode, 0);
1158 enum machine_mode m;
1161 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1162 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1166 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1167 m = (enum machine_mode) ((int) m + 1))
1168 if (HARD_REGNO_MODE_OK (j, m))
1172 /* If a register is not directly suitable for an
1173 auto-increment or decrement addressing mode and
1174 requires secondary reloads, disallow its class from
1175 being used in such addresses. */
1178 #ifdef SECONDARY_RELOAD_CLASS
1179 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r)
1182 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1183 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r)
1186 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1187 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r)
1192 && ! auto_inc_dec_reg_p (r, m))
1193 forbidden_inc_dec_class[i] = 1;
1197 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1200 /* This is a pass of the compiler that scans all instructions
1201 and calculates the preferred class for each pseudo-register.
1202 This information can be accessed later by calling `reg_preferred_class'.
1203 This pass comes just before local register allocation. */
1206 regclass (f, nregs, dump)
1217 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1219 #ifdef FORBIDDEN_INC_DEC_CLASSES
1221 in_inc_dec = (char *) xmalloc (nregs);
1223 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1225 /* Normally we scan the insns once and determine the best class to use for
1226 each register. However, if -fexpensive_optimizations are on, we do so
1227 twice, the second time using the tentative best classes to guide the
1230 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1235 fprintf (dump, "\n\nPass %i\n\n",pass);
1236 /* Zero out our accumulation of the cost of each class for each reg. */
1238 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1240 #ifdef FORBIDDEN_INC_DEC_CLASSES
1241 memset (in_inc_dec, 0, nregs);
1244 /* Scan the instructions and record each time it would
1245 save code to put a certain register in a certain class. */
1249 frequency = REG_FREQ_MAX;
1250 for (insn = f; insn; insn = NEXT_INSN (insn))
1251 insn = scan_one_insn (insn, pass);
1256 /* Show that an insn inside a loop is likely to be executed three
1257 times more than insns outside a loop. This is much more
1258 aggressive than the assumptions made elsewhere and is being
1259 tried as an experiment. */
1260 frequency = REG_FREQ_FROM_BB (bb);
1261 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1263 insn = scan_one_insn (insn, pass);
1264 if (insn == bb->end)
1269 /* Now for each register look at how desirable each class is
1270 and find which class is preferred. Store that in
1271 `prefclass'. Record in `altclass' the largest register
1272 class any of whose registers is better than memory. */
1275 reg_pref = reg_pref_buffer;
1279 dump_regclass (dump);
1280 fprintf (dump,"\n");
1282 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1284 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1285 enum reg_class best = ALL_REGS, alt = NO_REGS;
1286 /* This is an enum reg_class, but we call it an int
1287 to save lots of casts. */
1289 struct costs *p = &costs[i];
1291 /* In non-optimizing compilation REG_N_REFS is not initialized
1293 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i))
1296 for (class = (int) ALL_REGS - 1; class > 0; class--)
1298 /* Ignore classes that are too small for this operand or
1299 invalid for an operand that was auto-incremented. */
1300 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1301 #ifdef FORBIDDEN_INC_DEC_CLASSES
1302 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1304 #ifdef CANNOT_CHANGE_MODE_CLASS
1305 || invalid_mode_change_p (i, (enum reg_class) class,
1306 PSEUDO_REGNO_MODE (i))
1310 else if (p->cost[class] < best_cost)
1312 best_cost = p->cost[class];
1313 best = (enum reg_class) class;
1315 else if (p->cost[class] == best_cost)
1316 best = reg_class_subunion[(int) best][class];
1319 /* Record the alternate register class; i.e., a class for which
1320 every register in it is better than using memory. If adding a
1321 class would make a smaller class (i.e., no union of just those
1322 classes exists), skip that class. The major unions of classes
1323 should be provided as a register class. Don't do this if we
1324 will be doing it again later. */
1326 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1327 for (class = 0; class < N_REG_CLASSES; class++)
1328 if (p->cost[class] < p->mem_cost
1329 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1330 > reg_class_size[(int) alt])
1331 #ifdef FORBIDDEN_INC_DEC_CLASSES
1332 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1334 #ifdef CANNOT_CHANGE_MODE_CLASS
1335 && ! invalid_mode_change_p (i, (enum reg_class) class,
1336 PSEUDO_REGNO_MODE (i))
1339 alt = reg_class_subunion[(int) alt][class];
1341 /* If we don't add any classes, nothing to try. */
1346 && (reg_pref[i].prefclass != (int) best
1347 || reg_pref[i].altclass != (int) alt))
1349 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1350 fprintf (dump, " Register %i", i);
1351 if (alt == ALL_REGS || best == ALL_REGS)
1352 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1353 else if (alt == NO_REGS)
1354 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1356 fprintf (dump, " pref %s, else %s\n",
1357 reg_class_names[(int) best],
1358 reg_class_names[(int) alt]);
1361 /* We cast to (int) because (char) hits bugs in some compilers. */
1362 reg_pref[i].prefclass = (int) best;
1363 reg_pref[i].altclass = (int) alt;
1367 #ifdef FORBIDDEN_INC_DEC_CLASSES
1373 /* Record the cost of using memory or registers of various classes for
1374 the operands in INSN.
1376 N_ALTS is the number of alternatives.
1378 N_OPS is the number of operands.
1380 OPS is an array of the operands.
1382 MODES are the modes of the operands, in case any are VOIDmode.
1384 CONSTRAINTS are the constraints to use for the operands. This array
1385 is modified by this procedure.
1387 This procedure works alternative by alternative. For each alternative
1388 we assume that we will be able to allocate all pseudos to their ideal
1389 register class and calculate the cost of using that alternative. Then
1390 we compute for each operand that is a pseudo-register, the cost of
1391 having the pseudo allocated to each register class and using it in that
1392 alternative. To this cost is added the cost of the alternative.
1394 The cost of each class for this insn is its lowest cost among all the
1398 record_reg_classes (n_alts, n_ops, ops, modes,
1399 constraints, insn, op_costs, reg_pref)
1403 enum machine_mode *modes;
1404 const char **constraints;
1406 struct costs *op_costs;
1407 struct reg_pref *reg_pref;
1413 /* Process each alternative, each time minimizing an operand's cost with
1414 the cost for each operand in that alternative. */
1416 for (alt = 0; alt < n_alts; alt++)
1418 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1421 enum reg_class classes[MAX_RECOG_OPERANDS];
1422 int allows_mem[MAX_RECOG_OPERANDS];
1425 for (i = 0; i < n_ops; i++)
1427 const char *p = constraints[i];
1429 enum machine_mode mode = modes[i];
1430 int allows_addr = 0;
1434 /* Initially show we know nothing about the register class. */
1435 classes[i] = NO_REGS;
1438 /* If this operand has no constraints at all, we can conclude
1439 nothing about it since anything is valid. */
1443 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1444 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1449 /* If this alternative is only relevant when this operand
1450 matches a previous operand, we do different things depending
1451 on whether this operand is a pseudo-reg or not. We must process
1452 any modifiers for the operand before we can make this test. */
1454 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1457 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1459 /* Copy class and whether memory is allowed from the matching
1460 alternative. Then perform any needed cost computations
1461 and/or adjustments. */
1463 classes[i] = classes[j];
1464 allows_mem[i] = allows_mem[j];
1466 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1468 /* If this matches the other operand, we have no added
1470 if (rtx_equal_p (ops[j], op))
1473 /* If we can put the other operand into a register, add to
1474 the cost of this alternative the cost to copy this
1475 operand to the register used for the other operand. */
1477 else if (classes[j] != NO_REGS)
1478 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1480 else if (GET_CODE (ops[j]) != REG
1481 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1483 /* This op is a pseudo but the one it matches is not. */
1485 /* If we can't put the other operand into a register, this
1486 alternative can't be used. */
1488 if (classes[j] == NO_REGS)
1491 /* Otherwise, add to the cost of this alternative the cost
1492 to copy the other operand to the register used for this
1496 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1500 /* The costs of this operand are not the same as the other
1501 operand since move costs are not symmetric. Moreover,
1502 if we cannot tie them, this alternative needs to do a
1503 copy, which is one instruction. */
1505 struct costs *pp = &this_op_costs[i];
1507 for (class = 0; class < N_REG_CLASSES; class++)
1509 = ((recog_data.operand_type[i] != OP_OUT
1510 ? may_move_in_cost[mode][class][(int) classes[i]]
1512 + (recog_data.operand_type[i] != OP_IN
1513 ? may_move_out_cost[mode][(int) classes[i]][class]
1516 /* If the alternative actually allows memory, make things
1517 a bit cheaper since we won't need an extra insn to
1521 = ((recog_data.operand_type[i] != OP_IN
1522 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1524 + (recog_data.operand_type[i] != OP_OUT
1525 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1526 : 0) - allows_mem[i]);
1528 /* If we have assigned a class to this register in our
1529 first pass, add a cost to this alternative corresponding
1530 to what we would add if this register were not in the
1531 appropriate class. */
1535 += (may_move_in_cost[mode]
1536 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1537 [(int) classes[i]]);
1539 if (REGNO (ops[i]) != REGNO (ops[j])
1540 && ! find_reg_note (insn, REG_DEAD, op))
1543 /* This is in place of ordinary cost computation
1544 for this operand, so skip to the end of the
1545 alternative (should be just one character). */
1546 while (*p && *p++ != ',')
1554 /* Scan all the constraint letters. See if the operand matches
1555 any of the constraints. Collect the valid register classes
1556 and see if this operand accepts memory. */
1565 /* Ignore the next letter for this pass. */
1571 case '!': case '#': case '&':
1572 case '0': case '1': case '2': case '3': case '4':
1573 case '5': case '6': case '7': case '8': case '9':
1578 win = address_operand (op, GET_MODE (op));
1579 /* We know this operand is an address, so we want it to be
1580 allocated to a register that can be the base of an
1581 address, ie BASE_REG_CLASS. */
1583 = reg_class_subunion[(int) classes[i]]
1584 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1587 case 'm': case 'o': case 'V':
1588 /* It doesn't seem worth distinguishing between offsettable
1589 and non-offsettable addresses here. */
1591 if (GET_CODE (op) == MEM)
1596 if (GET_CODE (op) == MEM
1597 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1598 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1603 if (GET_CODE (op) == MEM
1604 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1605 || GET_CODE (XEXP (op, 0)) == POST_INC))
1611 if (GET_CODE (op) == CONST_DOUBLE
1612 || (GET_CODE (op) == CONST_VECTOR
1613 && (GET_MODE_CLASS (GET_MODE (op))
1614 == MODE_VECTOR_FLOAT)))
1620 if (GET_CODE (op) == CONST_DOUBLE
1621 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
1626 if (GET_CODE (op) == CONST_INT
1627 || (GET_CODE (op) == CONST_DOUBLE
1628 && GET_MODE (op) == VOIDmode))
1632 #ifdef LEGITIMATE_PIC_OPERAND_P
1633 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1640 if (GET_CODE (op) == CONST_INT
1641 || (GET_CODE (op) == CONST_DOUBLE
1642 && GET_MODE (op) == VOIDmode))
1654 if (GET_CODE (op) == CONST_INT
1655 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
1664 if (GET_CODE (op) == MEM
1666 #ifdef LEGITIMATE_PIC_OPERAND_P
1667 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1674 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1678 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS)
1680 = reg_class_subunion[(int) classes[i]]
1681 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1682 #ifdef EXTRA_CONSTRAINT_STR
1683 else if (EXTRA_CONSTRAINT_STR (op, c, p))
1686 if (EXTRA_MEMORY_CONSTRAINT (c, p))
1688 /* Every MEM can be reloaded to fit. */
1690 if (GET_CODE (op) == MEM)
1693 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1695 /* Every address can be reloaded to fit. */
1697 if (address_operand (op, GET_MODE (op)))
1699 /* We know this operand is an address, so we want it to
1700 be allocated to a register that can be the base of an
1701 address, ie BASE_REG_CLASS. */
1703 = reg_class_subunion[(int) classes[i]]
1704 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1709 p += CONSTRAINT_LEN (c, p);
1716 /* How we account for this operand now depends on whether it is a
1717 pseudo register or not. If it is, we first check if any
1718 register classes are valid. If not, we ignore this alternative,
1719 since we want to assume that all pseudos get allocated for
1720 register preferencing. If some register class is valid, compute
1721 the costs of moving the pseudo into that class. */
1723 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1725 if (classes[i] == NO_REGS)
1727 /* We must always fail if the operand is a REG, but
1728 we did not find a suitable class.
1730 Otherwise we may perform an uninitialized read
1731 from this_op_costs after the `continue' statement
1737 struct costs *pp = &this_op_costs[i];
1739 for (class = 0; class < N_REG_CLASSES; class++)
1741 = ((recog_data.operand_type[i] != OP_OUT
1742 ? may_move_in_cost[mode][class][(int) classes[i]]
1744 + (recog_data.operand_type[i] != OP_IN
1745 ? may_move_out_cost[mode][(int) classes[i]][class]
1748 /* If the alternative actually allows memory, make things
1749 a bit cheaper since we won't need an extra insn to
1753 = ((recog_data.operand_type[i] != OP_IN
1754 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1756 + (recog_data.operand_type[i] != OP_OUT
1757 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1758 : 0) - allows_mem[i]);
1760 /* If we have assigned a class to this register in our
1761 first pass, add a cost to this alternative corresponding
1762 to what we would add if this register were not in the
1763 appropriate class. */
1767 += (may_move_in_cost[mode]
1768 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1769 [(int) classes[i]]);
1773 /* Otherwise, if this alternative wins, either because we
1774 have already determined that or if we have a hard register of
1775 the proper class, there is no cost for this alternative. */
1778 || (GET_CODE (op) == REG
1779 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1782 /* If registers are valid, the cost of this alternative includes
1783 copying the object to and/or from a register. */
1785 else if (classes[i] != NO_REGS)
1787 if (recog_data.operand_type[i] != OP_OUT)
1788 alt_cost += copy_cost (op, mode, classes[i], 1);
1790 if (recog_data.operand_type[i] != OP_IN)
1791 alt_cost += copy_cost (op, mode, classes[i], 0);
1794 /* The only other way this alternative can be used is if this is a
1795 constant that could be placed into memory. */
1797 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1798 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1806 /* Finally, update the costs with the information we've calculated
1807 about this alternative. */
1809 for (i = 0; i < n_ops; i++)
1810 if (GET_CODE (ops[i]) == REG
1811 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1813 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1814 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1816 pp->mem_cost = MIN (pp->mem_cost,
1817 (qq->mem_cost + alt_cost) * scale);
1819 for (class = 0; class < N_REG_CLASSES; class++)
1820 pp->cost[class] = MIN (pp->cost[class],
1821 (qq->cost[class] + alt_cost) * scale);
1825 /* If this insn is a single set copying operand 1 to operand 0
1826 and one operand is a pseudo with the other a hard reg or a pseudo
1827 that prefers a register that is in its own register class then
1828 we may want to adjust the cost of that register class to -1.
1830 Avoid the adjustment if the source does not die to avoid stressing of
1831 register allocator by preferrencing two coliding registers into single
1834 Also avoid the adjustment if a copy between registers of the class
1835 is expensive (ten times the cost of a default copy is considered
1836 arbitrarily expensive). This avoids losing when the preferred class
1837 is very expensive as the source of a copy instruction. */
1839 if ((set = single_set (insn)) != 0
1840 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1841 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1842 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1843 for (i = 0; i <= 1; i++)
1844 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1846 unsigned int regno = REGNO (ops[!i]);
1847 enum machine_mode mode = GET_MODE (ops[!i]);
1851 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1853 enum reg_class pref = reg_pref[regno].prefclass;
1855 if ((reg_class_size[(unsigned char) pref]
1856 == (unsigned) CLASS_MAX_NREGS (pref, mode))
1857 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1858 op_costs[i].cost[(unsigned char) pref] = -1;
1860 else if (regno < FIRST_PSEUDO_REGISTER)
1861 for (class = 0; class < N_REG_CLASSES; class++)
1862 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1863 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode))
1865 if (reg_class_size[class] == 1)
1866 op_costs[i].cost[class] = -1;
1869 for (nr = 0; nr < (unsigned) HARD_REGNO_NREGS (regno, mode); nr++)
1871 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1876 if (nr == (unsigned) HARD_REGNO_NREGS (regno,mode))
1877 op_costs[i].cost[class] = -1;
1883 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1884 TO_P is zero) a register of class CLASS in mode MODE.
1886 X must not be a pseudo. */
1889 copy_cost (x, mode, class, to_p)
1891 enum machine_mode mode ATTRIBUTE_UNUSED;
1892 enum reg_class class;
1893 int to_p ATTRIBUTE_UNUSED;
1895 #ifdef HAVE_SECONDARY_RELOADS
1896 enum reg_class secondary_class = NO_REGS;
1899 /* If X is a SCRATCH, there is actually nothing to move since we are
1900 assuming optimal allocation. */
1902 if (GET_CODE (x) == SCRATCH)
1905 /* Get the class we will actually use for a reload. */
1906 class = PREFERRED_RELOAD_CLASS (x, class);
1908 #ifdef HAVE_SECONDARY_RELOADS
1909 /* If we need a secondary reload (we assume here that we are using
1910 the secondary reload as an intermediate, not a scratch register), the
1911 cost is that to load the input into the intermediate register, then
1912 to copy them. We use a special value of TO_P to avoid recursion. */
1914 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1916 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1919 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1921 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1924 if (secondary_class != NO_REGS)
1925 return (move_cost[mode][(int) secondary_class][(int) class]
1926 + copy_cost (x, mode, secondary_class, 2));
1927 #endif /* HAVE_SECONDARY_RELOADS */
1929 /* For memory, use the memory move cost, for (hard) registers, use the
1930 cost to move between the register classes, and use 2 for everything
1931 else (constants). */
1933 if (GET_CODE (x) == MEM || class == NO_REGS)
1934 return MEMORY_MOVE_COST (mode, class, to_p);
1936 else if (GET_CODE (x) == REG)
1937 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1940 /* If this is a constant, we may eventually want to call rtx_cost here. */
1941 return COSTS_N_INSNS (1);
1944 /* Record the pseudo registers we must reload into hard registers
1945 in a subexpression of a memory address, X.
1947 CLASS is the class that the register needs to be in and is either
1948 BASE_REG_CLASS or INDEX_REG_CLASS.
1950 SCALE is twice the amount to multiply the cost by (it is twice so we
1951 can represent half-cost adjustments). */
1954 record_address_regs (x, class, scale)
1956 enum reg_class class;
1959 enum rtx_code code = GET_CODE (x);
1972 /* When we have an address that is a sum,
1973 we must determine whether registers are "base" or "index" regs.
1974 If there is a sum of two registers, we must choose one to be
1975 the "base". Luckily, we can use the REG_POINTER to make a good
1976 choice most of the time. We only need to do this on machines
1977 that can have two registers in an address and where the base
1978 and index register classes are different.
1980 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1981 that seems bogus since it should only be set when we are sure
1982 the register is being used as a pointer. */
1985 rtx arg0 = XEXP (x, 0);
1986 rtx arg1 = XEXP (x, 1);
1987 enum rtx_code code0 = GET_CODE (arg0);
1988 enum rtx_code code1 = GET_CODE (arg1);
1990 /* Look inside subregs. */
1991 if (code0 == SUBREG)
1992 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1993 if (code1 == SUBREG)
1994 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1996 /* If this machine only allows one register per address, it must
1997 be in the first operand. */
1999 if (MAX_REGS_PER_ADDRESS == 1)
2000 record_address_regs (arg0, class, scale);
2002 /* If index and base registers are the same on this machine, just
2003 record registers in any non-constant operands. We assume here,
2004 as well as in the tests below, that all addresses are in
2007 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode))
2009 record_address_regs (arg0, class, scale);
2010 if (! CONSTANT_P (arg1))
2011 record_address_regs (arg1, class, scale);
2014 /* If the second operand is a constant integer, it doesn't change
2015 what class the first operand must be. */
2017 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
2018 record_address_regs (arg0, class, scale);
2020 /* If the second operand is a symbolic constant, the first operand
2021 must be an index register. */
2023 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
2024 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2026 /* If both operands are registers but one is already a hard register
2027 of index or base class, give the other the class that the hard
2030 #ifdef REG_OK_FOR_BASE_P
2031 else if (code0 == REG && code1 == REG
2032 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2033 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
2034 record_address_regs (arg1,
2035 REG_OK_FOR_BASE_P (arg0)
2036 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode),
2038 else if (code0 == REG && code1 == REG
2039 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2040 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
2041 record_address_regs (arg0,
2042 REG_OK_FOR_BASE_P (arg1)
2043 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode),
2047 /* If one operand is known to be a pointer, it must be the base
2048 with the other operand the index. Likewise if the other operand
2051 else if ((code0 == REG && REG_POINTER (arg0))
2054 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale);
2055 record_address_regs (arg1, INDEX_REG_CLASS, scale);
2057 else if ((code1 == REG && REG_POINTER (arg1))
2060 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2061 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale);
2064 /* Otherwise, count equal chances that each might be a base
2065 or index register. This case should be rare. */
2069 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode),
2071 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2072 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode),
2074 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2079 /* Double the importance of a pseudo register that is incremented
2080 or decremented, since it would take two extra insns
2081 if it ends up in the wrong place. */
2084 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode),
2086 if (REG_P (XEXP (XEXP (x, 1), 1)))
2087 record_address_regs (XEXP (XEXP (x, 1), 1),
2088 INDEX_REG_CLASS, 2 * scale);
2095 /* Double the importance of a pseudo register that is incremented
2096 or decremented, since it would take two extra insns
2097 if it ends up in the wrong place. If the operand is a pseudo,
2098 show it is being used in an INC_DEC context. */
2100 #ifdef FORBIDDEN_INC_DEC_CLASSES
2101 if (GET_CODE (XEXP (x, 0)) == REG
2102 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2103 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2106 record_address_regs (XEXP (x, 0), class, 2 * scale);
2111 struct costs *pp = &costs[REGNO (x)];
2114 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2116 for (i = 0; i < N_REG_CLASSES; i++)
2117 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2123 const char *fmt = GET_RTX_FORMAT (code);
2125 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2127 record_address_regs (XEXP (x, i), class, scale);
2132 #ifdef FORBIDDEN_INC_DEC_CLASSES
2134 /* Return 1 if REG is valid as an auto-increment memory reference
2135 to an object of MODE. */
2138 auto_inc_dec_reg_p (reg, mode)
2140 enum machine_mode mode;
2142 if (HAVE_POST_INCREMENT
2143 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2146 if (HAVE_POST_DECREMENT
2147 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2150 if (HAVE_PRE_INCREMENT
2151 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2154 if (HAVE_PRE_DECREMENT
2155 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2162 static short *renumber;
2163 static size_t regno_allocated;
2164 static unsigned int reg_n_max;
2166 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2167 reg_scan and flow_analysis that are indexed by the register number. If
2168 NEW_P is nonzero, initialize all of the registers, otherwise only
2169 initialize the new registers allocated. The same table is kept from
2170 function to function, only reallocating it when we need more room. If
2171 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2174 allocate_reg_info (num_regs, new_p, renumber_p)
2180 size_t size_renumber;
2181 size_t min = (new_p) ? 0 : reg_n_max;
2182 struct reg_info_data *reg_data;
2184 if (num_regs > regno_allocated)
2186 size_t old_allocated = regno_allocated;
2188 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2189 size_renumber = regno_allocated * sizeof (short);
2193 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2194 renumber = (short *) xmalloc (size_renumber);
2195 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2196 * sizeof (struct reg_pref));
2201 VARRAY_GROW (reg_n_info, regno_allocated);
2203 if (new_p) /* if we're zapping everything, no need to realloc */
2205 free ((char *) renumber);
2206 free ((char *) reg_pref);
2207 renumber = (short *) xmalloc (size_renumber);
2208 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2209 * sizeof (struct reg_pref));
2214 renumber = (short *) xrealloc ((char *) renumber, size_renumber);
2215 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer,
2217 * sizeof (struct reg_pref));
2221 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2222 + sizeof (struct reg_info_data) - sizeof (reg_info);
2223 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2224 reg_data->min_index = old_allocated;
2225 reg_data->max_index = regno_allocated - 1;
2226 reg_data->next = reg_info_head;
2227 reg_info_head = reg_data;
2230 reg_n_max = num_regs;
2233 /* Loop through each of the segments allocated for the actual
2234 reg_info pages, and set up the pointers, zero the pages, etc. */
2235 for (reg_data = reg_info_head;
2236 reg_data && reg_data->max_index >= min;
2237 reg_data = reg_data->next)
2239 size_t min_index = reg_data->min_index;
2240 size_t max_index = reg_data->max_index;
2241 size_t max = MIN (max_index, num_regs);
2242 size_t local_min = min - min_index;
2245 if (reg_data->min_index > num_regs)
2248 if (min < min_index)
2250 if (!reg_data->used_p) /* page just allocated with calloc */
2251 reg_data->used_p = 1; /* no need to zero */
2253 memset ((char *) ®_data->data[local_min], 0,
2254 sizeof (reg_info) * (max - min_index - local_min + 1));
2256 for (i = min_index+local_min; i <= max; i++)
2258 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2259 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2261 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2262 reg_pref_buffer[i].altclass = (char) NO_REGS;
2267 /* If {pref,alt}class have already been allocated, update the pointers to
2268 the newly realloced ones. */
2270 reg_pref = reg_pref_buffer;
2273 reg_renumber = renumber;
2275 /* Tell the regset code about the new number of registers. */
2276 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2279 /* Free up the space allocated by allocate_reg_info. */
2285 struct reg_info_data *reg_data;
2286 struct reg_info_data *reg_next;
2288 VARRAY_FREE (reg_n_info);
2289 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2291 reg_next = reg_data->next;
2292 free ((char *) reg_data);
2295 free (reg_pref_buffer);
2296 reg_pref_buffer = (struct reg_pref *) 0;
2297 reg_info_head = (struct reg_info_data *) 0;
2298 renumber = (short *) 0;
2300 regno_allocated = 0;
2304 /* This is the `regscan' pass of the compiler, run just before cse
2305 and again just before loop.
2307 It finds the first and last use of each pseudo-register
2308 and records them in the vectors regno_first_uid, regno_last_uid
2309 and counts the number of sets in the vector reg_n_sets.
2311 REPEAT is nonzero the second time this is called. */
2313 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2314 Always at least 3, since the combiner could put that many together
2315 and we want this to remain correct for all the remaining passes.
2316 This corresponds to the maximum number of times note_stores will call
2317 a function for any insn. */
2321 /* Used as a temporary to record the largest number of registers in
2322 PARALLEL in a SET_DEST. This is added to max_parallel. */
2324 static int max_set_parallel;
2327 reg_scan (f, nregs, repeat)
2330 int repeat ATTRIBUTE_UNUSED;
2334 allocate_reg_info (nregs, TRUE, FALSE);
2336 max_set_parallel = 0;
2338 timevar_push (TV_REG_SCAN);
2340 for (insn = f; insn; insn = NEXT_INSN (insn))
2341 if (GET_CODE (insn) == INSN
2342 || GET_CODE (insn) == CALL_INSN
2343 || GET_CODE (insn) == JUMP_INSN)
2345 if (GET_CODE (PATTERN (insn)) == PARALLEL
2346 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2347 max_parallel = XVECLEN (PATTERN (insn), 0);
2348 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2350 if (REG_NOTES (insn))
2351 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2354 max_parallel += max_set_parallel;
2356 timevar_pop (TV_REG_SCAN);
2359 /* Update 'regscan' information by looking at the insns
2360 from FIRST to LAST. Some new REGs have been created,
2361 and any REG with number greater than OLD_MAX_REGNO is
2362 such a REG. We only update information for those. */
2365 reg_scan_update (first, last, old_max_regno)
2368 unsigned int old_max_regno;
2372 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2374 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2375 if (GET_CODE (insn) == INSN
2376 || GET_CODE (insn) == CALL_INSN
2377 || GET_CODE (insn) == JUMP_INSN)
2379 if (GET_CODE (PATTERN (insn)) == PARALLEL
2380 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2381 max_parallel = XVECLEN (PATTERN (insn), 0);
2382 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2384 if (REG_NOTES (insn))
2385 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2389 /* X is the expression to scan. INSN is the insn it appears in.
2390 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2391 We should only record information for REGs with numbers
2392 greater than or equal to MIN_REGNO. */
2395 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2399 unsigned int min_regno;
2407 code = GET_CODE (x);
2424 unsigned int regno = REGNO (x);
2426 if (regno >= min_regno)
2428 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2430 REGNO_LAST_UID (regno) = INSN_UID (insn);
2431 if (REGNO_FIRST_UID (regno) == 0)
2432 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2433 /* If we are called by reg_scan_update() (indicated by min_regno
2434 being set), we also need to update the reference count. */
2436 REG_N_REFS (regno)++;
2443 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2445 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2450 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2455 rtx reg = XEXP (x, 0);
2457 && REGNO (reg) >= min_regno)
2459 REG_N_SETS (REGNO (reg))++;
2460 REG_N_REFS (REGNO (reg))++;
2466 /* Count a set of the destination if it is a register. */
2467 for (dest = SET_DEST (x);
2468 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2469 || GET_CODE (dest) == ZERO_EXTEND;
2470 dest = XEXP (dest, 0))
2473 /* For a PARALLEL, record the number of things (less the usual one for a
2474 SET) that are set. */
2475 if (GET_CODE (dest) == PARALLEL)
2476 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2478 if (GET_CODE (dest) == REG
2479 && REGNO (dest) >= min_regno)
2481 REG_N_SETS (REGNO (dest))++;
2482 REG_N_REFS (REGNO (dest))++;
2485 /* If this is setting a pseudo from another pseudo or the sum of a
2486 pseudo and a constant integer and the other pseudo is known to be
2487 a pointer, set the destination to be a pointer as well.
2489 Likewise if it is setting the destination from an address or from a
2490 value equivalent to an address or to the sum of an address and
2493 But don't do any of this if the pseudo corresponds to a user
2494 variable since it should have already been set as a pointer based
2497 if (GET_CODE (SET_DEST (x)) == REG
2498 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2499 && REGNO (SET_DEST (x)) >= min_regno
2500 /* If the destination pseudo is set more than once, then other
2501 sets might not be to a pointer value (consider access to a
2502 union in two threads of control in the presence of global
2503 optimizations). So only set REG_POINTER on the destination
2504 pseudo if this is the only set of that pseudo. */
2505 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2506 && ! REG_USERVAR_P (SET_DEST (x))
2507 && ! REG_POINTER (SET_DEST (x))
2508 && ((GET_CODE (SET_SRC (x)) == REG
2509 && REG_POINTER (SET_SRC (x)))
2510 || ((GET_CODE (SET_SRC (x)) == PLUS
2511 || GET_CODE (SET_SRC (x)) == LO_SUM)
2512 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2513 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2514 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2515 || GET_CODE (SET_SRC (x)) == CONST
2516 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2517 || GET_CODE (SET_SRC (x)) == LABEL_REF
2518 || (GET_CODE (SET_SRC (x)) == HIGH
2519 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2520 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2521 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2522 || ((GET_CODE (SET_SRC (x)) == PLUS
2523 || GET_CODE (SET_SRC (x)) == LO_SUM)
2524 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2525 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2526 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2527 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2528 && (GET_CODE (XEXP (note, 0)) == CONST
2529 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2530 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2531 REG_POINTER (SET_DEST (x)) = 1;
2533 /* If this is setting a register from a register or from a simple
2534 conversion of a register, propagate REG_EXPR. */
2535 if (GET_CODE (dest) == REG)
2537 rtx src = SET_SRC (x);
2539 while (GET_CODE (src) == SIGN_EXTEND
2540 || GET_CODE (src) == ZERO_EXTEND
2541 || GET_CODE (src) == TRUNCATE
2542 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)))
2543 src = XEXP (src, 0);
2545 if (!REG_ATTRS (dest) && REG_P (src))
2546 REG_ATTRS (dest) = REG_ATTRS (src);
2547 if (!REG_ATTRS (dest) && GET_CODE (src) == MEM)
2548 set_reg_attrs_from_mem (dest, src);
2551 /* ... fall through ... */
2555 const char *fmt = GET_RTX_FORMAT (code);
2557 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2560 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2561 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2564 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2565 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2572 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2576 reg_class_subset_p (c1, c2)
2580 if (c1 == c2) return 1;
2585 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1],
2586 reg_class_contents[(int) c2],
2591 /* Return nonzero if there is a register that is in both C1 and C2. */
2594 reg_classes_intersect_p (c1, c2)
2603 if (c1 == c2) return 1;
2605 if (c1 == ALL_REGS || c2 == ALL_REGS)
2608 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2609 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2611 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2618 /* Release any memory allocated by register sets. */
2621 regset_release_memory ()
2623 bitmap_release_memory ();
2626 #ifdef CANNOT_CHANGE_MODE_CLASS
2627 /* Set bits in *USED which correspond to registers which can't change
2628 their mode from FROM to any mode in which REGNO was encountered. */
2631 cannot_change_mode_set_regs (used, from, regno)
2633 enum machine_mode from;
2636 enum machine_mode to;
2638 int start = regno * MAX_MACHINE_MODE;
2640 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n,
2641 if (n >= MAX_MACHINE_MODE + start)
2644 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2645 if (! TEST_HARD_REG_BIT (*used, i)
2646 && REG_CANNOT_CHANGE_MODE_P (i, from, to))
2647 SET_HARD_REG_BIT (*used, i);
2651 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2655 invalid_mode_change_p (regno, class, from_mode)
2657 enum reg_class class;
2658 enum machine_mode from_mode;
2660 enum machine_mode to_mode;
2662 int start = regno * MAX_MACHINE_MODE;
2664 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n,
2665 if (n >= MAX_MACHINE_MODE + start)
2667 to_mode = n - start;
2668 if (CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode, class))
2673 #endif /* CANNOT_CHANGE_MODE_CLASS */
2675 #include "gt-regclass.h"