1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This file contains two passes of the compiler: reg_scan and reg_class.
22 It also defines some tables of information about the hardware registers
23 and a function init_reg_sets to initialize the tables. */
27 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
36 #ifndef REGISTER_MOVE_COST
37 #define REGISTER_MOVE_COST(x, y) 2
40 #ifndef MEMORY_MOVE_COST
41 #define MEMORY_MOVE_COST(x) 4
44 /* Register tables used by many passes. */
46 /* Indexed by hard register number, contains 1 for registers
47 that are fixed use (stack pointer, pc, frame pointer, etc.).
48 These are the registers that cannot be used to allocate
49 a pseudo reg whose life does not cross calls. */
51 char fixed_regs[FIRST_PSEUDO_REGISTER];
53 /* Same info as a HARD_REG_SET. */
55 HARD_REG_SET fixed_reg_set;
57 /* Data for initializing the above. */
59 static char initial_fixed_regs[] = FIXED_REGISTERS;
61 /* Indexed by hard register number, contains 1 for registers
62 that are fixed use or are clobbered by function calls.
63 These are the registers that cannot be used to allocate
64 a pseudo reg whose life crosses calls. */
66 char call_used_regs[FIRST_PSEUDO_REGISTER];
68 /* Same info as a HARD_REG_SET. */
70 HARD_REG_SET call_used_reg_set;
72 /* Data for initializing the above. */
74 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
76 /* Indexed by hard register number, contains 1 for registers that are
77 fixed use -- i.e. in fixed_regs -- or a function value return register
78 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
79 registers that cannot hold quantities across calls even if we are
80 willing to save and restore them. */
82 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
84 /* The same info as a HARD_REG_SET. */
86 HARD_REG_SET call_fixed_reg_set;
88 /* Number of non-fixed registers. */
92 /* Indexed by hard register number, contains 1 for registers
93 that are being used for global register decls.
94 These must be exempt from ordinary flow analysis
95 and are also considered fixed. */
97 char global_regs[FIRST_PSEUDO_REGISTER];
99 /* Table of register numbers in the order in which to try to use them. */
100 #ifdef REG_ALLOC_ORDER
101 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
104 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
106 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
108 /* The same information, but as an array of ints. We copy from these
109 ints to the table above. This is done so that the tm.h files do
110 not have to be aware of the wordsize for machines with <= 64 regs. */
113 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
115 static int int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
116 = REG_CLASS_CONTENTS;
118 /* For each reg class, number of regs it contains. */
120 int reg_class_size[N_REG_CLASSES];
122 /* For each reg class, table listing all the containing classes. */
124 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
126 /* For each reg class, table listing all the classes contained in it. */
128 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
130 /* For each pair of reg classes,
131 a largest reg class contained in their union. */
133 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
135 /* For each pair of reg classes,
136 the smallest reg class containing their union. */
138 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
140 /* Array containing all of the register names */
142 char *reg_names[] = REGISTER_NAMES;
144 /* Indexed by n, gives number of times (REG n) is set or clobbered.
145 This information remains valid for the rest of the compilation
146 of the current function; it is used to control register allocation.
148 This information applies to both hard registers and pseudo registers,
149 unlike much of the information above. */
153 /* Maximum cost of moving from a register in one class to a register in
154 another class. Based on REGISTER_MOVE_COST. */
156 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
158 /* Similar, but here we don't have to move if the first index is a subset
159 of the second so in that case the cost is zero. */
161 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
163 /* Function called only once to initialize the above data on reg usage.
164 Once this is done, various switches may override. */
171 /* First copy the register information from the initial int form into
174 for (i = 0; i < N_REG_CLASSES; i++)
176 CLEAR_HARD_REG_SET (reg_class_contents[i]);
178 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
179 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
180 & (1 << (j % HOST_BITS_PER_INT)))
181 SET_HARD_REG_BIT (reg_class_contents[i], j);
184 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
185 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
186 bzero (global_regs, sizeof global_regs);
188 /* Compute number of hard regs in each class. */
190 bzero (reg_class_size, sizeof reg_class_size);
191 for (i = 0; i < N_REG_CLASSES; i++)
192 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
193 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
196 /* Initialize the table of subunions.
197 reg_class_subunion[I][J] gets the largest-numbered reg-class
198 that is contained in the union of classes I and J. */
200 for (i = 0; i < N_REG_CLASSES; i++)
202 for (j = 0; j < N_REG_CLASSES; j++)
205 register /* Declare it register if it's a scalar. */
210 COPY_HARD_REG_SET (c, reg_class_contents[i]);
211 IOR_HARD_REG_SET (c, reg_class_contents[j]);
212 for (k = 0; k < N_REG_CLASSES; k++)
214 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
219 /* keep the largest subclass */ /* SPEE 900308 */
220 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
221 reg_class_contents[(int) reg_class_subunion[i][j]],
223 reg_class_subunion[i][j] = (enum reg_class) k;
230 /* Initialize the table of superunions.
231 reg_class_superunion[I][J] gets the smallest-numbered reg-class
232 containing the union of classes I and J. */
234 for (i = 0; i < N_REG_CLASSES; i++)
236 for (j = 0; j < N_REG_CLASSES; j++)
239 register /* Declare it register if it's a scalar. */
244 COPY_HARD_REG_SET (c, reg_class_contents[i]);
245 IOR_HARD_REG_SET (c, reg_class_contents[j]);
246 for (k = 0; k < N_REG_CLASSES; k++)
247 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
250 reg_class_superunion[i][j] = (enum reg_class) k;
254 /* Initialize the tables of subclasses and superclasses of each reg class.
255 First clear the whole table, then add the elements as they are found. */
257 for (i = 0; i < N_REG_CLASSES; i++)
259 for (j = 0; j < N_REG_CLASSES; j++)
261 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
262 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
266 for (i = 0; i < N_REG_CLASSES; i++)
268 if (i == (int) NO_REGS)
271 for (j = i + 1; j < N_REG_CLASSES; j++)
275 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
279 /* Reg class I is a subclass of J.
280 Add J to the table of superclasses of I. */
281 p = ®_class_superclasses[i][0];
282 while (*p != LIM_REG_CLASSES) p++;
283 *p = (enum reg_class) j;
284 /* Add I to the table of superclasses of J. */
285 p = ®_class_subclasses[j][0];
286 while (*p != LIM_REG_CLASSES) p++;
287 *p = (enum reg_class) i;
291 /* Initialize the move cost table. Find every subset of each class
292 and take the maximum cost of moving any subset to any other. */
294 for (i = 0; i < N_REG_CLASSES; i++)
295 for (j = 0; j < N_REG_CLASSES; j++)
297 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
298 enum reg_class *p1, *p2;
300 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
302 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
304 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
307 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
309 for (p2 = ®_class_subclasses[j][0];
310 *p2 != LIM_REG_CLASSES; p2++)
312 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
315 move_cost[i][j] = cost;
317 if (reg_class_subset_p (i, j))
320 may_move_cost[i][j] = cost;
324 /* After switches have been processed, which perhaps alter
325 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
332 /* This macro allows the fixed or call-used registers
333 to depend on target flags. */
335 #ifdef CONDITIONAL_REGISTER_USAGE
336 CONDITIONAL_REGISTER_USAGE;
339 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
342 if (call_used_regs[i] && ! fixed_regs[i])
343 warning ("call-clobbered register used for global register variable");
345 /* Prevent saving/restoring of this reg. */
346 call_used_regs[i] = 1;
349 /* Initialize "constant" tables. */
351 CLEAR_HARD_REG_SET (fixed_reg_set);
352 CLEAR_HARD_REG_SET (call_used_reg_set);
353 CLEAR_HARD_REG_SET (call_fixed_reg_set);
355 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
356 #ifdef STRUCT_VALUE_REGNUM
357 call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
359 #ifdef STATIC_CHAIN_REGNUM
360 call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
363 n_non_fixed_regs = 0;
365 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
367 if (FUNCTION_VALUE_REGNO_P (i))
368 call_fixed_regs[i] = 1;
370 SET_HARD_REG_BIT (fixed_reg_set, i);
374 if (call_used_regs[i])
375 SET_HARD_REG_BIT (call_used_reg_set, i);
376 if (call_fixed_regs[i])
377 SET_HARD_REG_BIT (call_fixed_reg_set, i);
381 /* Specify the usage characteristics of the register named NAME.
382 It should be a fixed register if FIXED and a
383 call-used register if CALL_USED. */
386 fix_register (name, fixed, call_used)
388 int fixed, call_used;
392 /* Decode the name and update the primary form of
393 the register info. */
395 if ((i = decode_reg_name (name)) >= 0)
397 fixed_regs[i] = fixed;
398 call_used_regs[i] = call_used;
402 warning ("unknown register name: %s", name);
406 /* Now the data and code for the `regclass' pass, which happens
407 just before local-alloc. */
409 /* The `costs' struct records the cost of using a hard register of each class
410 and of using memory for each pseudo. We use this data to set up
411 register class preferences. */
415 int cost[N_REG_CLASSES];
419 /* Record the cost of each class for each pseudo. */
421 static struct costs *costs;
423 /* Record the same data by operand number, accumulated for each alternative
424 in an insn. The contribution to a pseudo is that of the minimum-cost
427 static struct costs op_costs[MAX_RECOG_OPERANDS];
429 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
430 This is available after `regclass' is run. */
432 static char *prefclass;
434 /* altclass[R] is a register class that we should use for allocating
435 pseudo number R if no register in the preferred class is available.
436 If no register in this class is available, memory is preferred.
438 It might appear to be more general to have a bitmask of classes here,
439 but since it is recommended that there be a class corresponding to the
440 union of most major pair of classes, that generality is not required.
442 This is available after `regclass' is run. */
444 static char *altclass;
446 /* Record the depth of loops that we are in. */
448 static int loop_depth;
450 /* Account for the fact that insns within a loop are executed very commonly,
451 but don't keep doing this as loops go too deep. */
453 static int loop_cost;
455 static int copy_cost ();
456 static void record_reg_classes ();
457 static void record_address_regs ();
460 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
461 This function is sometimes called before the info has been computed.
462 When that happens, just return GENERAL_REGS, which is innocuous. */
465 reg_preferred_class (regno)
470 return (enum reg_class) prefclass[regno];
474 reg_alternate_class (regno)
479 return (enum reg_class) altclass[regno];
482 /* This prevents dump_flow_info from losing if called
483 before regclass is run. */
491 /* This is a pass of the compiler that scans all instructions
492 and calculates the preferred class for each pseudo-register.
493 This information can be accessed later by calling `reg_preferred_class'.
494 This pass comes just before local register allocation. */
501 #ifdef REGISTER_CONSTRAINTS
504 struct costs init_cost;
510 init_cost.mem_cost = 10000;
511 for (i = 0; i < N_REG_CLASSES; i++)
512 init_cost.cost[i] = 10000;
514 /* Normally we scan the insns once and determine the best class to use for
515 each register. However, if -fexpensive_optimizations are on, we do so
516 twice, the second time using the tentative best classes to guide the
519 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
521 /* Zero out our accumulation of the cost of each class for each reg. */
523 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
524 bzero (costs, nregs * sizeof (struct costs));
526 loop_depth = 0, loop_cost = 1;
528 /* Scan the instructions and record each time it would
529 save code to put a certain register in a certain class. */
531 for (insn = f; insn; insn = NEXT_INSN (insn))
533 char *constraints[MAX_RECOG_OPERANDS];
534 enum machine_mode modes[MAX_RECOG_OPERANDS];
538 /* Show that an insn inside a loop is likely to be executed three
539 times more than insns outside a loop. This is much more agressive
540 than the assumptions made elsewhere and is being tried as an
543 if (GET_CODE (insn) == NOTE
544 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
545 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
546 else if (GET_CODE (insn) == NOTE
547 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
548 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
550 else if ((GET_CODE (insn) == INSN
551 && GET_CODE (PATTERN (insn)) != USE
552 && GET_CODE (PATTERN (insn)) != CLOBBER
553 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
554 || (GET_CODE (insn) == JUMP_INSN
555 && GET_CODE (PATTERN (insn)) != ADDR_VEC
556 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
557 || GET_CODE (insn) == CALL_INSN)
559 if (GET_CODE (insn) == INSN
560 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
562 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
564 nalternatives = n_occurrences (',', constraints[0]) + 1;
568 int insn_code_number = recog_memoized (insn);
571 set = single_set (insn);
574 nalternatives = insn_n_alternatives[insn_code_number];
575 noperands = insn_n_operands[insn_code_number];
577 /* If this insn loads a parameter from its stack slot, then
578 it represents a savings, rather than a cost, if the
579 parameter is stored in memory. Record this fact. */
581 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
582 && GET_CODE (SET_SRC (set)) == MEM
583 && (note = find_reg_note (insn, REG_EQUIV,
585 && GET_CODE (XEXP (note, 0)) == MEM)
587 costs[REGNO (SET_DEST (set))].mem_cost
588 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
590 record_address_regs (XEXP (SET_SRC (set), 0),
591 BASE_REG_CLASS, loop_cost * 2);
595 /* Improve handling of two-address insns such as
596 (set X (ashift CONST Y)) where CONST must be made to
597 match X. Change it into two insns: (set X CONST)
598 (set X (ashift X Y)). If we left this for reloading, it
599 would probably get three insns because X and Y might go
600 in the same place. This prevents X and Y from receiving
603 We can only do this if the modes of operands 0 and 1
604 (which might not be the same) are tieable and we only need
605 do this during our first pass. */
607 if (pass == 0 && optimize
609 && insn_operand_constraint[insn_code_number][1][0] == '0'
610 && insn_operand_constraint[insn_code_number][1][1] == 0
611 && CONSTANT_P (recog_operand[1])
612 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
613 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
614 && GET_CODE (recog_operand[0]) == REG
615 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
616 insn_operand_mode[insn_code_number][1]))
618 rtx previnsn = prev_real_insn (insn);
620 = gen_lowpart (insn_operand_mode[insn_code_number][1],
623 = emit_insn_before (gen_move_insn (dest,
627 /* If this insn was the start of a basic block,
628 include the new insn in that block.
629 We need not check for code_label here;
630 while a basic block can start with a code_label,
631 INSN could not be at the beginning of that block. */
632 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
635 for (b = 0; b < n_basic_blocks; b++)
636 if (insn == basic_block_head[b])
637 basic_block_head[b] = newinsn;
640 /* This makes one more setting of new insns's dest. */
641 reg_n_sets[REGNO (recog_operand[0])]++;
643 *recog_operand_loc[1] = recog_operand[0];
644 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
645 if (recog_dup_num[i] == 1)
646 *recog_dup_loc[i] = recog_operand[0];
648 insn = PREV_INSN (newinsn);
652 /* If this is setting a pseudo from another pseudo or the
653 sum of a pseudo and a constant integer and the other
654 pseudo is known to be a pointer, set the destination to
655 be a pointer as well.
657 Likewise if it is setting the destination from an address
658 or from a value equivalent to an address or to the sum of
659 an address and something else.
661 But don't do any of this if the pseudo corresponds to
662 a user variable since it should have already been set
663 as a pointer based on the type.
665 There is no point in doing this during our second
666 pass since not enough should have changed. */
668 if (pass == 0 && set != 0 && GET_CODE (SET_DEST (set)) == REG
669 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
670 && ! REG_USERVAR_P (SET_DEST (set))
671 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (set)))
672 && ((GET_CODE (SET_SRC (set)) == REG
673 && REGNO_POINTER_FLAG (REGNO (SET_SRC (set))))
674 || ((GET_CODE (SET_SRC (set)) == PLUS
675 || GET_CODE (SET_SRC (set)) == LO_SUM)
676 && (GET_CODE (XEXP (SET_SRC (set), 1))
678 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
679 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (set), 0))))
680 || GET_CODE (SET_SRC (set)) == CONST
681 || GET_CODE (SET_SRC (set)) == SYMBOL_REF
682 || GET_CODE (SET_SRC (set)) == LABEL_REF
683 || (GET_CODE (SET_SRC (set)) == HIGH
684 && (GET_CODE (XEXP (SET_SRC (set), 0)) == CONST
685 || (GET_CODE (XEXP (SET_SRC (set), 0))
687 || (GET_CODE (XEXP (SET_SRC (set), 0))
689 || ((GET_CODE (SET_SRC (set)) == PLUS
690 || GET_CODE (SET_SRC (set)) == LO_SUM)
691 && (GET_CODE (XEXP (SET_SRC (set), 1)) == CONST
692 || (GET_CODE (XEXP (SET_SRC (set), 1))
694 || (GET_CODE (XEXP (SET_SRC (set), 1))
696 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
697 && (GET_CODE (XEXP (note, 0)) == CONST
698 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
699 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
700 REGNO_POINTER_FLAG (REGNO (SET_DEST (set))) = 1;
702 for (i = 0; i < noperands; i++)
705 = insn_operand_constraint[insn_code_number][i];
706 modes[i] = insn_operand_mode[insn_code_number][i];
710 /* If we get here, we are set up to record the costs of all the
711 operands for this insn. Start by initializing the costs.
712 Then handle any address registers. Finally record the desired
713 classes for any pseudos, doing it twice if some pair of
714 operands are commutative. */
716 for (i = 0; i < noperands; i++)
718 op_costs[i] = init_cost;
720 if (GET_CODE (recog_operand[i]) == SUBREG)
721 recog_operand[i] = SUBREG_REG (recog_operand[i]);
723 if (GET_CODE (recog_operand[i]) == MEM)
724 record_address_regs (XEXP (recog_operand[i], 0),
725 BASE_REG_CLASS, loop_cost * 2);
726 else if (constraints[i][0] == 'p')
727 record_address_regs (recog_operand[i],
728 BASE_REG_CLASS, loop_cost * 2);
731 /* Check for commutative in a separate loop so everything will
732 have been initialized. Don't bother doing anything if the
733 second operand is a constant since that is the case
734 for which the constraints should have been written. */
736 for (i = 0; i < noperands; i++)
737 if (constraints[i][0] == '%'
738 && ! CONSTANT_P (recog_operand[i+1]))
740 char *xconstraints[MAX_RECOG_OPERANDS];
743 /* Handle commutative operands by swapping the constraints.
744 We assume the modes are the same. */
746 for (j = 0; j < noperands; j++)
747 xconstraints[j] = constraints[j];
749 xconstraints[i] = constraints[i+1];
750 xconstraints[i+1] = constraints[i];
751 record_reg_classes (nalternatives, noperands,
752 recog_operand, modes, xconstraints,
756 record_reg_classes (nalternatives, noperands, recog_operand,
757 modes, constraints, insn);
759 /* Now add the cost for each operand to the total costs for
762 for (i = 0; i < noperands; i++)
763 if (GET_CODE (recog_operand[i]) == REG
764 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
766 int regno = REGNO (recog_operand[i]);
767 struct costs *p = &costs[regno], *q = &op_costs[i];
769 p->mem_cost += q->mem_cost * loop_cost;
770 for (j = 0; j < N_REG_CLASSES; j++)
771 p->cost[j] += q->cost[j] * loop_cost;
776 /* Now for each register look at how desirable each class is
777 and find which class is preferred. Store that in
778 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
779 class any of whose registers is better than memory. */
783 prefclass = (char *) oballoc (nregs);
784 altclass = (char *) oballoc (nregs);
787 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
789 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
790 enum reg_class best = ALL_REGS, alt = NO_REGS;
791 /* This is an enum reg_class, but we call it an int
792 to save lots of casts. */
794 register struct costs *p = &costs[i];
796 for (class = (int) ALL_REGS - 1; class > 0; class--)
798 /* Ignore classes that are too small for this operand. */
799 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
800 > reg_class_size[class])
802 else if (p->cost[class] < best_cost)
804 best_cost = p->cost[class];
805 best = (enum reg_class) class;
807 else if (p->cost[class] == best_cost)
808 best = reg_class_subunion[(int)best][class];
811 /* Record the alternate register class; i.e., a class for which
812 every register in it is better than using memory. If adding a
813 class would make a smaller class (i.e., no union of just those
814 classes exists), skip that class. The major unions of classes
815 should be provided as a register class. Don't do this if we
816 will be doing it again later. */
818 if (pass == 1 || ! flag_expensive_optimizations)
819 for (class = 0; class < N_REG_CLASSES; class++)
820 if (p->cost[class] < p->mem_cost
821 && (reg_class_size[reg_class_subunion[(int) alt][class]]
822 > reg_class_size[(int) alt]))
823 alt = reg_class_subunion[(int) alt][class];
825 /* If we don't add any classes, nothing to try. */
829 /* We cast to (int) because (char) hits bugs in some compilers. */
830 prefclass[i] = (int) best;
831 altclass[i] = (int) alt;
834 #endif /* REGISTER_CONSTRAINTS */
837 #ifdef REGISTER_CONSTRAINTS
839 /* Record the cost of using memory or registers of various classes for
840 the operands in INSN.
842 N_ALTS is the number of alternatives.
844 N_OPS is the number of operands.
846 OPS is an array of the operands.
848 MODES are the modes of the operands, in case any are VOIDmode.
850 CONSTRAINTS are the constraints to use for the operands. This array
851 is modified by this procedure.
853 This procedure works alternative by alternative. For each alternative
854 we assume that we will be able to allocate all pseudos to their ideal
855 register class and calculate the cost of using that alternative. Then
856 we compute for each operand that is a pseudo-register, the cost of
857 having the pseudo allocated to each register class and using it in that
858 alternative. To this cost is added the cost of the alternative.
860 The cost of each class for this insn is its lowest cost among all the
864 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
868 enum machine_mode *modes;
873 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
876 /* By default, each operand is an input operand. */
878 for (i = 0; i < n_ops; i++)
879 op_types[i] = OP_READ;
881 /* Process each alternative, each time minimizing an operand's cost with
882 the cost for each operand in that alternative. */
884 for (alt = 0; alt < n_alts; alt++)
886 struct costs this_op_costs[MAX_RECOG_OPERANDS];
889 enum reg_class classes[MAX_RECOG_OPERANDS];
892 for (i = 0; i < n_ops; i++)
894 char *p = constraints[i];
896 enum machine_mode mode = modes[i];
901 /* If this operand has no constraints at all, we can conclude
902 nothing about it since anything is valid. */
906 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
907 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
912 /* If this alternative is only relevant when this operand
913 matches a previous operand, we do different things depending
914 on whether this operand is a pseudo-reg or not. */
916 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
919 classes[i] = classes[j];
921 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
923 /* If this matches the other operand, we have no added
925 if (rtx_equal_p (ops[j], op))
928 /* If we can't put the other operand into a register, this
929 alternative can't be used. */
931 else if (classes[j] == NO_REGS)
934 /* Otherwise, add to the cost of this alternative the cost
935 to copy this operand to the register used for the other
939 alt_cost += copy_cost (op, mode, classes[j], 1);
944 /* The costs of this operand are the same as that of the
945 other operand. However, if we cannot tie them, this
946 alternative needs to do a copy, which is one
949 this_op_costs[i] = this_op_costs[j];
950 if (! find_reg_note (insn, REG_DEAD, op))
957 /* Scan all the constraint letters. See if the operand matches
958 any of the constraints. Collect the valid register classes
959 and see if this operand accepts memory. */
961 classes[i] = NO_REGS;
962 while (*p && (c = *p++) != ',')
966 op_types[i] = OP_WRITE;
970 op_types[i] = OP_READ_WRITE;
974 /* Ignore the next letter for this pass. */
979 case '?': case '!': case '#':
981 case '0': case '1': case '2': case '3': case '4':
985 case 'm': case 'o': case 'V':
986 /* It doesn't seem worth distingishing between offsettable
987 and non-offsettable addresses here. */
989 if (GET_CODE (op) == MEM)
994 if (GET_CODE (op) == MEM
995 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
996 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1001 if (GET_CODE (op) == MEM
1002 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1003 || GET_CODE (XEXP (op, 0)) == POST_INC))
1008 /* Match any floating double constant, but only if
1009 we can examine the bits of it reliably. */
1010 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1011 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1012 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1014 if (GET_CODE (op) == CONST_DOUBLE)
1019 if (GET_CODE (op) == CONST_DOUBLE)
1025 if (GET_CODE (op) == CONST_DOUBLE
1026 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1031 if (GET_CODE (op) == CONST_INT
1032 || (GET_CODE (op) == CONST_DOUBLE
1033 && GET_MODE (op) == VOIDmode))
1037 #ifdef LEGITIMATE_PIC_OPERAND_P
1038 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1045 if (GET_CODE (op) == CONST_INT
1046 || (GET_CODE (op) == CONST_DOUBLE
1047 && GET_MODE (op) == VOIDmode))
1059 if (GET_CODE (op) == CONST_INT
1060 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1068 #ifdef EXTRA_CONSTRAINT
1074 if (EXTRA_CONSTRAINT (op, c))
1080 if (GET_CODE (op) == MEM
1082 #ifdef LEGITIMATE_PIC_OPERAND_P
1083 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1090 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1095 = reg_class_subunion[(int) classes[i]]
1096 [(int) REG_CLASS_FROM_LETTER (c)];
1101 /* How we account for this operand now depends on whether it is a
1102 pseudo register or not. If it is, we first check if any
1103 register classes are valid. If not, we ignore this alternative,
1104 since we want to assume that all pseudos get allocated for
1105 register preferencing. If some register class is valid, compute
1106 the costs of moving the pseudo into that class. */
1108 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1110 if (classes[i] == NO_REGS)
1114 struct costs *pp = &this_op_costs[i];
1116 for (class = 0; class < N_REG_CLASSES; class++)
1117 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1119 /* If the alternative actually allows memory, make things
1120 a bit cheaper since we won't need an extra insn to
1123 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1125 /* If we have assigned a class to this register in our
1126 first pass, add a cost to this alternative corresponding
1127 to what we would add if this register were not in the
1128 appropriate class. */
1132 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1136 /* Otherwise, if this alternative wins, either because we
1137 have already determined that or if we have a hard register of
1138 the proper class, there is no cost for this alternative. */
1141 || (GET_CODE (op) == REG
1142 && reg_fits_class_p (op, classes[i], 0, mode)))
1145 /* If registers are valid, the cost of this alternative includes
1146 copying the object to and/or from a register. */
1148 else if (classes[i] != NO_REGS)
1150 if (op_types[i] != OP_WRITE)
1151 alt_cost += copy_cost (op, mode, classes[i], 1);
1153 if (op_types[i] != OP_READ)
1154 alt_cost += copy_cost (op, mode, classes[i], 0);
1157 /* The only other way this alternative can be used is if this is a
1158 constant that could be placed into memory. */
1160 else if (CONSTANT_P (op) && allows_mem)
1161 alt_cost += MEMORY_MOVE_COST (mode);
1169 /* Finally, update the costs with the information we've calculated
1170 about this alternative. */
1172 for (i = 0; i < n_ops; i++)
1173 if (GET_CODE (ops[i]) == REG
1174 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1176 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1177 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1179 pp->mem_cost = MIN (pp->mem_cost,
1180 (qq->mem_cost + alt_cost) * scale);
1182 for (class = 0; class < N_REG_CLASSES; class++)
1183 pp->cost[class] = MIN (pp->cost[class],
1184 (qq->cost[class] + alt_cost) * scale);
1189 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1190 TO_P is zero) a register of class CLASS in mode MODE.
1192 X must not be a pseudo. */
1195 copy_cost (x, mode, class, to_p)
1197 enum machine_mode mode;
1198 enum reg_class class;
1201 enum reg_class secondary_class = NO_REGS;
1203 /* If X is a SCRATCH, there is actually nothing to move since we are
1204 assuming optimal allocation. */
1206 if (GET_CODE (x) == SCRATCH)
1209 /* Get the class we will actually use for a reload. */
1210 class = PREFERRED_RELOAD_CLASS (x, class);
1212 #ifdef HAVE_SECONDARY_RELOADS
1213 /* If we need a secondary reload (we assume here that we are using
1214 the secondary reload as an intermediate, not a scratch register), the
1215 cost is that to load the input into the intermediate register, then
1216 to copy them. We use a special value of TO_P to avoid recursion. */
1218 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1220 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1223 #ifdef SECONARY_OUTPUT_RELOAD_CLASS
1225 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1228 if (secondary_class != NO_REGS)
1229 return (move_cost[(int) secondary_class][(int) class]
1230 + copy_cost (x, mode, secondary_class, 2));
1231 #endif /* HAVE_SECONARY_RELOADS */
1233 /* For memory, use the memory move cost, for (hard) registers, use the
1234 cost to move between the register classes, and use 2 for everything
1235 else (constants). */
1237 if (GET_CODE (x) == MEM || class == NO_REGS)
1238 return MEMORY_MOVE_COST (mode);
1240 else if (GET_CODE (x) == REG)
1241 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1244 /* If this is a constant, we may eventually want to call rtx_cost here. */
1248 /* Record the pseudo registers we must reload into hard registers
1249 in a subexpression of a memory address, X.
1251 CLASS is the class that the register needs to be in and is either
1252 BASE_REG_CLASS or INDEX_REG_CLASS.
1254 SCALE is twice the amount to multiply the cost by (it is twice so we
1255 can represent half-cost adjustments). */
1258 record_address_regs (x, class, scale)
1260 enum reg_class class;
1263 register enum rtx_code code = GET_CODE (x);
1276 /* When we have an address that is a sum,
1277 we must determine whether registers are "base" or "index" regs.
1278 If there is a sum of two registers, we must choose one to be
1279 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1280 to make a good choice most of the time. We only need to do this
1281 on machines that can have two registers in an address and where
1282 the base and index register classes are different.
1284 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1285 that seems bogus since it should only be set when we are sure
1286 the register is being used as a pointer. */
1289 rtx arg0 = XEXP (x, 0);
1290 rtx arg1 = XEXP (x, 1);
1291 register enum rtx_code code0 = GET_CODE (arg0);
1292 register enum rtx_code code1 = GET_CODE (arg1);
1294 /* Look inside subregs. */
1295 if (code0 == SUBREG)
1296 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1297 if (code1 == SUBREG)
1298 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1300 /* If this machine only allows one register per address, it must
1301 be in the first operand. */
1303 if (MAX_REGS_PER_ADDRESS == 1)
1304 record_address_regs (arg0, class, scale);
1306 /* If index and base registers are the same on this machine, just
1307 record registers in any non-constant operands. We assume here,
1308 as well as in the tests below, that all addresses are in
1311 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1313 record_address_regs (arg0, class, scale);
1314 if (! CONSTANT_P (arg1))
1315 record_address_regs (arg1, class, scale);
1318 /* If the second operand is a constant integer, it doesn't change
1319 what class the first operand must be. */
1321 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1322 record_address_regs (arg0, class, scale);
1324 /* If the second operand is a symbolic constant, the first operand
1325 must be an index register. */
1327 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1328 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1330 /* If this the sum of two registers where the first is known to be a
1331 pointer, it must be a base register with the second an index. */
1333 else if (code0 == REG && code1 == REG
1334 && REGNO_POINTER_FLAG (REGNO (arg0)))
1336 record_address_regs (arg0, BASE_REG_CLASS, scale);
1337 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1340 /* If this is the sum of two registers and neither is known to
1341 be a pointer, count equal chances that each might be a base
1342 or index register. This case should be rare. */
1344 else if (code0 == REG && code1 == REG
1345 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1346 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1348 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1349 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1350 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1351 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1354 /* In all other cases, the first operand is an index and the
1355 second is the base. */
1359 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1360 record_address_regs (arg1, BASE_REG_CLASS, scale);
1369 /* Double the importance of a pseudo register that is incremented
1370 or decremented, since it would take two extra insns
1371 if it ends up in the wrong place. */
1373 record_address_regs (XEXP (x, 0), class, 2 * scale);
1378 register struct costs *pp = &costs[REGNO (x)];
1381 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1383 for (i = 0; i < N_REG_CLASSES; i++)
1384 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1390 register char *fmt = GET_RTX_FORMAT (code);
1392 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1394 record_address_regs (XEXP (x, i), class, scale);
1398 #endif /* REGISTER_CONSTRAINTS */
1400 /* This is the `regscan' pass of the compiler, run just before cse
1401 and again just before loop.
1403 It finds the first and last use of each pseudo-register
1404 and records them in the vectors regno_first_uid, regno_last_uid
1405 and counts the number of sets in the vector reg_n_sets.
1407 REPEAT is nonzero the second time this is called. */
1409 /* Indexed by pseudo register number, gives uid of first insn using the reg
1410 (as of the time reg_scan is called). */
1412 int *regno_first_uid;
1414 /* Indexed by pseudo register number, gives uid of last insn using the reg
1415 (as of the time reg_scan is called). */
1417 int *regno_last_uid;
1419 /* Record the number of registers we used when we allocated the above two
1420 tables. If we are called again with more than this, we must re-allocate
1423 static int highest_regno_in_uid_map;
1425 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1426 Always at least 3, since the combiner could put that many togetherm
1427 and we want this to remain correct for all the remaining passes. */
1431 void reg_scan_mark_refs ();
1434 reg_scan (f, nregs, repeat)
1441 if (!repeat || nregs > highest_regno_in_uid_map)
1443 /* Leave some spare space in case more regs are allocated. */
1444 highest_regno_in_uid_map = nregs + nregs / 20;
1446 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1448 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1450 = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1453 bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int));
1454 bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int));
1455 bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1459 for (insn = f; insn; insn = NEXT_INSN (insn))
1460 if (GET_CODE (insn) == INSN
1461 || GET_CODE (insn) == CALL_INSN
1462 || GET_CODE (insn) == JUMP_INSN)
1464 if (GET_CODE (PATTERN (insn)) == PARALLEL
1465 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1466 max_parallel = XVECLEN (PATTERN (insn), 0);
1467 reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn));
1472 reg_scan_mark_refs (x, uid)
1476 register enum rtx_code code = GET_CODE (x);
1494 register int regno = REGNO (x);
1496 regno_last_uid[regno] = uid;
1497 if (regno_first_uid[regno] == 0)
1498 regno_first_uid[regno] = uid;
1503 /* Count a set of the destination if it is a register. */
1504 for (dest = SET_DEST (x);
1505 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1506 || GET_CODE (dest) == ZERO_EXTEND;
1507 dest = XEXP (dest, 0))
1510 if (GET_CODE (dest) == REG)
1511 reg_n_sets[REGNO (dest)]++;
1513 /* ... fall through ... */
1517 register char *fmt = GET_RTX_FORMAT (code);
1519 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1522 reg_scan_mark_refs (XEXP (x, i), uid);
1523 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1526 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1527 reg_scan_mark_refs (XVECEXP (x, i, j), uid);
1534 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1538 reg_class_subset_p (c1, c2)
1539 register enum reg_class c1;
1540 register enum reg_class c2;
1542 if (c1 == c2) return 1;
1547 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1548 reg_class_contents[(int)c2],
1553 /* Return nonzero if there is a register that is in both C1 and C2. */
1556 reg_classes_intersect_p (c1, c2)
1557 register enum reg_class c1;
1558 register enum reg_class c2;
1565 if (c1 == c2) return 1;
1567 if (c1 == ALL_REGS || c2 == ALL_REGS)
1570 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1571 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1573 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);