1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
32 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1 PARAMS ((void));
50 static void init_reg_modes PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs[FIRST_PSEUDO_REGISTER];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set;
75 /* Data for initializing the above. */
77 static char initial_fixed_regs[] = FIXED_REGISTERS;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs[FIRST_PSEUDO_REGISTER];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set;
94 /* Data for initializing the above. */
96 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
98 /* Indexed by hard register number, contains 1 for registers that are
99 fixed use or call used registers that cannot hold quantities across
100 calls even if we are willing to save and restore them. call fixed
101 registers are a subset of call used registers. */
103 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
105 /* The same info as a HARD_REG_SET. */
107 HARD_REG_SET call_fixed_reg_set;
109 /* Number of non-fixed registers. */
111 int n_non_fixed_regs;
113 /* Indexed by hard register number, contains 1 for registers
114 that are being used for global register decls.
115 These must be exempt from ordinary flow analysis
116 and are also considered fixed. */
118 char global_regs[FIRST_PSEUDO_REGISTER];
120 /* Contains 1 for registers that are set or clobbered by calls. */
121 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
122 for someone's bright idea to have call_used_regs strictly include
123 fixed_regs. Which leaves us guessing as to the set of fixed_regs
124 that are actually preserved. We know for sure that those associated
125 with the local stack frame are safe, but scant others. */
127 HARD_REG_SET regs_invalidated_by_call;
129 /* Table of register numbers in the order in which to try to use them. */
130 #ifdef REG_ALLOC_ORDER
131 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
133 /* The inverse of reg_alloc_order. */
134 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
137 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
139 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
141 /* The same information, but as an array of unsigned ints. We copy from
142 these unsigned ints to the table above. We do this so the tm.h files
143 do not have to be aware of the wordsize for machines with <= 64 regs.
144 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
147 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
149 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
150 = REG_CLASS_CONTENTS;
152 /* For each reg class, number of regs it contains. */
154 unsigned int reg_class_size[N_REG_CLASSES];
156 /* For each reg class, table listing all the containing classes. */
158 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
160 /* For each reg class, table listing all the classes contained in it. */
162 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
164 /* For each pair of reg classes,
165 a largest reg class contained in their union. */
167 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
169 /* For each pair of reg classes,
170 the smallest reg class containing their union. */
172 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
174 /* Array containing all of the register names. Unless
175 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
177 #ifdef DEBUG_REGISTER_NAMES
178 const char * reg_names[] = REGISTER_NAMES;
181 /* For each hard register, the widest mode object that it can contain.
182 This will be a MODE_INT mode if the register can hold integers. Otherwise
183 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
186 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
188 /* 1 if class does contain register of given mode. */
190 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
192 /* Maximum cost of moving from a register in one class to a register in
193 another class. Based on REGISTER_MOVE_COST. */
195 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
197 /* Similar, but here we don't have to move if the first index is a subset
198 of the second so in that case the cost is zero. */
200 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
202 /* Similar, but here we don't have to move if the first index is a superset
203 of the second so in that case the cost is zero. */
205 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
207 #ifdef FORBIDDEN_INC_DEC_CLASSES
209 /* These are the classes that regs which are auto-incremented or decremented
212 static int forbidden_inc_dec_class[N_REG_CLASSES];
214 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
217 static char *in_inc_dec;
219 #endif /* FORBIDDEN_INC_DEC_CLASSES */
221 #ifdef CLASS_CANNOT_CHANGE_MODE
223 /* These are the classes containing only registers that can be used in
224 a SUBREG expression that changes the mode of the register in some
225 way that is illegal. */
227 static int class_can_change_mode[N_REG_CLASSES];
229 /* Registers, including pseudos, which change modes in some way that
232 static regset reg_changes_mode;
234 #endif /* CLASS_CANNOT_CHANGE_MODE */
236 #ifdef HAVE_SECONDARY_RELOADS
238 /* Sample MEM values for use by memory_move_secondary_cost. */
240 static rtx top_of_stack[MAX_MACHINE_MODE];
242 #endif /* HAVE_SECONDARY_RELOADS */
244 /* Linked list of reg_info structures allocated for reg_n_info array.
245 Grouping all of the allocated structures together in one lump
246 means only one call to bzero to clear them, rather than n smaller
248 struct reg_info_data {
249 struct reg_info_data *next; /* next set of reg_info structures */
250 size_t min_index; /* minimum index # */
251 size_t max_index; /* maximum index # */
252 char used_p; /* non-zero if this has been used previously */
253 reg_info data[1]; /* beginning of the reg_info data */
256 static struct reg_info_data *reg_info_head;
258 /* No more global register variables may be declared; true once
259 regclass has been initialized. */
261 static int no_global_reg_vars = 0;
264 /* Function called only once to initialize the above data on reg usage.
265 Once this is done, various switches may override. */
272 /* First copy the register information from the initial int form into
275 for (i = 0; i < N_REG_CLASSES; i++)
277 CLEAR_HARD_REG_SET (reg_class_contents[i]);
279 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
280 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
281 if (int_reg_class_contents[i][j / 32]
282 & ((unsigned) 1 << (j % 32)))
283 SET_HARD_REG_BIT (reg_class_contents[i], j);
286 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
287 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
288 memset (global_regs, 0, sizeof global_regs);
290 /* Do any additional initialization regsets may need */
291 INIT_ONCE_REG_SET ();
293 #ifdef REG_ALLOC_ORDER
294 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
295 inv_reg_alloc_order[reg_alloc_order[i]] = i;
299 /* After switches have been processed, which perhaps alter
300 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
305 register unsigned int i, j;
306 register unsigned int /* enum machine_mode */ m;
307 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
309 /* This macro allows the fixed or call-used registers
310 and the register classes to depend on target flags. */
312 #ifdef CONDITIONAL_REGISTER_USAGE
313 CONDITIONAL_REGISTER_USAGE;
316 /* Compute number of hard regs in each class. */
318 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
319 for (i = 0; i < N_REG_CLASSES; i++)
320 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
321 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
324 /* Initialize the table of subunions.
325 reg_class_subunion[I][J] gets the largest-numbered reg-class
326 that is contained in the union of classes I and J. */
328 for (i = 0; i < N_REG_CLASSES; i++)
330 for (j = 0; j < N_REG_CLASSES; j++)
333 register /* Declare it register if it's a scalar. */
338 COPY_HARD_REG_SET (c, reg_class_contents[i]);
339 IOR_HARD_REG_SET (c, reg_class_contents[j]);
340 for (k = 0; k < N_REG_CLASSES; k++)
342 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
347 /* keep the largest subclass */ /* SPEE 900308 */
348 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
349 reg_class_contents[(int) reg_class_subunion[i][j]],
351 reg_class_subunion[i][j] = (enum reg_class) k;
358 /* Initialize the table of superunions.
359 reg_class_superunion[I][J] gets the smallest-numbered reg-class
360 containing the union of classes I and J. */
362 for (i = 0; i < N_REG_CLASSES; i++)
364 for (j = 0; j < N_REG_CLASSES; j++)
367 register /* Declare it register if it's a scalar. */
372 COPY_HARD_REG_SET (c, reg_class_contents[i]);
373 IOR_HARD_REG_SET (c, reg_class_contents[j]);
374 for (k = 0; k < N_REG_CLASSES; k++)
375 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
378 reg_class_superunion[i][j] = (enum reg_class) k;
382 /* Initialize the tables of subclasses and superclasses of each reg class.
383 First clear the whole table, then add the elements as they are found. */
385 for (i = 0; i < N_REG_CLASSES; i++)
387 for (j = 0; j < N_REG_CLASSES; j++)
389 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
390 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
394 for (i = 0; i < N_REG_CLASSES; i++)
396 if (i == (int) NO_REGS)
399 for (j = i + 1; j < N_REG_CLASSES; j++)
403 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
407 /* Reg class I is a subclass of J.
408 Add J to the table of superclasses of I. */
409 p = ®_class_superclasses[i][0];
410 while (*p != LIM_REG_CLASSES) p++;
411 *p = (enum reg_class) j;
412 /* Add I to the table of superclasses of J. */
413 p = ®_class_subclasses[j][0];
414 while (*p != LIM_REG_CLASSES) p++;
415 *p = (enum reg_class) i;
419 /* Initialize "constant" tables. */
421 CLEAR_HARD_REG_SET (fixed_reg_set);
422 CLEAR_HARD_REG_SET (call_used_reg_set);
423 CLEAR_HARD_REG_SET (call_fixed_reg_set);
424 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
426 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
428 n_non_fixed_regs = 0;
430 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
433 SET_HARD_REG_BIT (fixed_reg_set, i);
437 if (call_used_regs[i])
438 SET_HARD_REG_BIT (call_used_reg_set, i);
439 if (call_fixed_regs[i])
440 SET_HARD_REG_BIT (call_fixed_reg_set, i);
441 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
442 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
444 /* There are a couple of fixed registers that we know are safe to
445 exclude from being clobbered by calls:
447 The frame pointer is always preserved across calls. The arg pointer
448 is if it is fixed. The stack pointer usually is, unless
449 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
450 If we are generating PIC code, the PIC offset table register is
451 preserved across calls, though the target can override that. */
453 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM)
455 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
456 else if (i == HARD_FRAME_POINTER_REGNUM)
459 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
460 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
463 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
464 else if (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
467 else if (call_used_regs[i] || global_regs[i])
468 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
471 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
472 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
473 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
474 for (i = 0; i < N_REG_CLASSES; i++)
475 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
476 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
477 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
478 && HARD_REGNO_MODE_OK (j, m))
480 contains_reg_of_mode [i][m] = 1;
481 allocatable_regs_of_mode [m] = 1;
485 /* Initialize the move cost table. Find every subset of each class
486 and take the maximum cost of moving any subset to any other. */
488 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
489 if (allocatable_regs_of_mode [m])
491 for (i = 0; i < N_REG_CLASSES; i++)
492 if (contains_reg_of_mode [i][m])
493 for (j = 0; j < N_REG_CLASSES; j++)
496 enum reg_class *p1, *p2;
498 if (!contains_reg_of_mode [j][m])
500 move_cost[m][i][j] = 65536;
501 may_move_in_cost[m][i][j] = 65536;
502 may_move_out_cost[m][i][j] = 65536;
506 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
508 for (p2 = ®_class_subclasses[j][0];
509 *p2 != LIM_REG_CLASSES;
511 if (*p2 != i && contains_reg_of_mode [*p2][m])
512 cost = MAX (cost, move_cost [m][i][*p2]);
514 for (p1 = ®_class_subclasses[i][0];
515 *p1 != LIM_REG_CLASSES;
517 if (*p1 != j && contains_reg_of_mode [*p1][m])
518 cost = MAX (cost, move_cost [m][*p1][j]);
520 move_cost[m][i][j] = cost;
522 if (reg_class_subset_p (i, j))
523 may_move_in_cost[m][i][j] = 0;
525 may_move_in_cost[m][i][j] = cost;
527 if (reg_class_subset_p (j, i))
528 may_move_out_cost[m][i][j] = 0;
530 may_move_out_cost[m][i][j] = cost;
534 for (j = 0; j < N_REG_CLASSES; j++)
536 move_cost[m][i][j] = 65536;
537 may_move_in_cost[m][i][j] = 65536;
538 may_move_out_cost[m][i][j] = 65536;
542 #ifdef CLASS_CANNOT_CHANGE_MODE
545 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
547 for (i = 0; i < N_REG_CLASSES; i++)
549 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
550 class_can_change_mode [i] = 0;
553 class_can_change_mode [i] = 1;
556 #endif /* CLASS_CANNOT_CHANGE_MODE */
559 /* Compute the table of register modes.
560 These values are used to record death information for individual registers
561 (as opposed to a multi-register mode). */
568 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
570 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
572 /* If we couldn't find a valid mode, just use the previous mode.
573 ??? One situation in which we need to do this is on the mips where
574 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
575 to use DF mode for the even registers and VOIDmode for the odd
576 (for the cpu models where the odd ones are inaccessible). */
577 if (reg_raw_mode[i] == VOIDmode)
578 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
582 /* Finish initializing the register sets and
583 initialize the register modes. */
588 /* This finishes what was started by init_reg_sets, but couldn't be done
589 until after register usage was specified. */
594 #ifdef HAVE_SECONDARY_RELOADS
596 /* Make some fake stack-frame MEM references for use in
597 memory_move_secondary_cost. */
600 for (i = 0; i < MAX_MACHINE_MODE; i++)
601 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
602 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
607 #ifdef HAVE_SECONDARY_RELOADS
609 /* Compute extra cost of moving registers to/from memory due to reloads.
610 Only needed if secondary reloads are required for memory moves. */
613 memory_move_secondary_cost (mode, class, in)
614 enum machine_mode mode;
615 enum reg_class class;
618 enum reg_class altclass;
619 int partial_cost = 0;
620 /* We need a memory reference to feed to SECONDARY... macros. */
621 /* mem may be unused even if the SECONDARY_ macros are defined. */
622 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
627 #ifdef SECONDARY_INPUT_RELOAD_CLASS
628 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
635 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
636 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
642 if (altclass == NO_REGS)
646 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
648 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
650 if (class == altclass)
651 /* This isn't simply a copy-to-temporary situation. Can't guess
652 what it is, so MEMORY_MOVE_COST really ought not to be calling
655 I'm tempted to put in an abort here, but returning this will
656 probably only give poor estimates, which is what we would've
657 had before this code anyways. */
660 /* Check if the secondary reload register will also need a
662 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
666 /* Return a machine mode that is legitimate for hard reg REGNO and large
667 enough to save nregs. If we can't find one, return VOIDmode. */
670 choose_hard_reg_mode (regno, nregs)
671 unsigned int regno ATTRIBUTE_UNUSED;
674 unsigned int /* enum machine_mode */ m;
675 enum machine_mode found_mode = VOIDmode, mode;
677 /* We first look for the largest integer mode that can be validly
678 held in REGNO. If none, we look for the largest floating-point mode.
679 If we still didn't find a valid mode, try CCmode. */
681 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
683 mode = GET_MODE_WIDER_MODE (mode))
684 if (HARD_REGNO_NREGS (regno, mode) == nregs
685 && HARD_REGNO_MODE_OK (regno, mode))
688 if (found_mode != VOIDmode)
691 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
693 mode = GET_MODE_WIDER_MODE (mode))
694 if (HARD_REGNO_NREGS (regno, mode) == nregs
695 && HARD_REGNO_MODE_OK (regno, mode))
698 if (found_mode != VOIDmode)
701 /* Iterate over all of the CCmodes. */
702 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
704 mode = (enum machine_mode) m;
705 if (HARD_REGNO_NREGS (regno, mode) == nregs
706 && HARD_REGNO_MODE_OK (regno, mode))
710 /* We can't find a mode valid for this register. */
714 /* Specify the usage characteristics of the register named NAME.
715 It should be a fixed register if FIXED and a
716 call-used register if CALL_USED. */
719 fix_register (name, fixed, call_used)
721 int fixed, call_used;
725 /* Decode the name and update the primary form of
726 the register info. */
728 if ((i = decode_reg_name (name)) >= 0)
730 if ((i == STACK_POINTER_REGNUM
731 #ifdef HARD_FRAME_POINTER_REGNUM
732 || i == HARD_FRAME_POINTER_REGNUM
734 || i == FRAME_POINTER_REGNUM
737 && (fixed == 0 || call_used == 0))
739 static const char * const what_option[2][2] = {
740 { "call-saved", "call-used" },
741 { "no-such-option", "fixed" }};
743 error ("can't use '%s' as a %s register", name,
744 what_option[fixed][call_used]);
748 fixed_regs[i] = fixed;
749 call_used_regs[i] = call_used;
754 warning ("unknown register name: %s", name);
758 /* Mark register number I as global. */
764 if (fixed_regs[i] == 0 && no_global_reg_vars)
765 error ("global register variable follows a function definition");
769 warning ("register used for two global register variables");
773 if (call_used_regs[i] && ! fixed_regs[i])
774 warning ("call-clobbered register used for global register variable");
778 /* If already fixed, nothing else to do. */
782 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
785 SET_HARD_REG_BIT (fixed_reg_set, i);
786 SET_HARD_REG_BIT (call_used_reg_set, i);
787 SET_HARD_REG_BIT (call_fixed_reg_set, i);
790 /* Now the data and code for the `regclass' pass, which happens
791 just before local-alloc. */
793 /* The `costs' struct records the cost of using a hard register of each class
794 and of using memory for each pseudo. We use this data to set up
795 register class preferences. */
799 int cost[N_REG_CLASSES];
803 /* Structure used to record preferrences of given pseudo. */
806 /* (enum reg_class) prefclass is the preferred class. */
809 /* altclass is a register class that we should use for allocating
810 pseudo if no register in the preferred class is available.
811 If no register in this class is available, memory is preferred.
813 It might appear to be more general to have a bitmask of classes here,
814 but since it is recommended that there be a class corresponding to the
815 union of most major pair of classes, that generality is not required. */
819 /* Record the cost of each class for each pseudo. */
821 static struct costs *costs;
823 /* Initialized once, and used to initialize cost values for each insn. */
825 static struct costs init_cost;
827 /* Record preferrences of each pseudo.
828 This is available after `regclass' is run. */
830 static struct reg_pref *reg_pref;
832 /* Allocated buffers for reg_pref. */
834 static struct reg_pref *reg_pref_buffer;
836 /* Frequency of executions of current insn. */
838 static int frequency;
840 static rtx scan_one_insn PARAMS ((rtx, int));
841 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
842 static void dump_regclass PARAMS ((FILE *));
843 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
845 struct costs *, struct reg_pref *));
846 static int copy_cost PARAMS ((rtx, enum machine_mode,
847 enum reg_class, int));
848 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
849 #ifdef FORBIDDEN_INC_DEC_CLASSES
850 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
852 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
854 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
855 This function is sometimes called before the info has been computed.
856 When that happens, just return GENERAL_REGS, which is innocuous. */
859 reg_preferred_class (regno)
864 return (enum reg_class) reg_pref[regno].prefclass;
868 reg_alternate_class (regno)
874 return (enum reg_class) reg_pref[regno].altclass;
877 /* Initialize some global data for this pass. */
884 init_cost.mem_cost = 10000;
885 for (i = 0; i < N_REG_CLASSES; i++)
886 init_cost.cost[i] = 10000;
888 /* This prevents dump_flow_info from losing if called
889 before regclass is run. */
892 /* No more global register variables may be declared. */
893 no_global_reg_vars = 1;
896 /* Dump register costs. */
901 static const char *const reg_class_names[] = REG_CLASS_NAMES;
903 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
905 int /* enum reg_class */ class;
908 fprintf (dump, " Register %i costs:", i);
909 for (class = 0; class < (int) N_REG_CLASSES; class++)
910 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
911 #ifdef FORBIDDEN_INC_DEC_CLASSES
913 || !forbidden_inc_dec_class[(enum reg_class) class])
915 #ifdef CLASS_CANNOT_CHANGE_MODE
916 && (!REGNO_REG_SET_P (reg_changes_mode, i)
917 || class_can_change_mode [(enum reg_class) class])
920 fprintf (dump, " %s:%i", reg_class_names[class],
921 costs[i].cost[(enum reg_class) class]);
922 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
928 /* Calculate the costs of insn operands. */
931 record_operand_costs (insn, op_costs, reg_pref)
933 struct costs *op_costs;
934 struct reg_pref *reg_pref;
936 const char *constraints[MAX_RECOG_OPERANDS];
937 enum machine_mode modes[MAX_RECOG_OPERANDS];
940 for (i = 0; i < recog_data.n_operands; i++)
942 constraints[i] = recog_data.constraints[i];
943 modes[i] = recog_data.operand_mode[i];
946 /* If we get here, we are set up to record the costs of all the
947 operands for this insn. Start by initializing the costs.
948 Then handle any address registers. Finally record the desired
949 classes for any pseudos, doing it twice if some pair of
950 operands are commutative. */
952 for (i = 0; i < recog_data.n_operands; i++)
954 op_costs[i] = init_cost;
956 if (GET_CODE (recog_data.operand[i]) == SUBREG)
958 rtx inner = SUBREG_REG (recog_data.operand[i]);
959 #ifdef CLASS_CANNOT_CHANGE_MODE
960 if (GET_CODE (inner) == REG
961 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
962 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
964 recog_data.operand[i] = inner;
967 if (GET_CODE (recog_data.operand[i]) == MEM)
968 record_address_regs (XEXP (recog_data.operand[i], 0),
969 BASE_REG_CLASS, frequency * 2);
970 else if (constraints[i][0] == 'p')
971 record_address_regs (recog_data.operand[i],
972 BASE_REG_CLASS, frequency * 2);
975 /* Check for commutative in a separate loop so everything will
976 have been initialized. We must do this even if one operand
977 is a constant--see addsi3 in m68k.md. */
979 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
980 if (constraints[i][0] == '%')
982 const char *xconstraints[MAX_RECOG_OPERANDS];
985 /* Handle commutative operands by swapping the constraints.
986 We assume the modes are the same. */
988 for (j = 0; j < recog_data.n_operands; j++)
989 xconstraints[j] = constraints[j];
991 xconstraints[i] = constraints[i+1];
992 xconstraints[i+1] = constraints[i];
993 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
994 recog_data.operand, modes,
995 xconstraints, insn, op_costs, reg_pref);
998 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
999 recog_data.operand, modes,
1000 constraints, insn, op_costs, reg_pref);
1003 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1004 time it would save code to put a certain register in a certain class.
1005 PASS, when nonzero, inhibits some optimizations which need only be done
1007 Return the last insn processed, so that the scan can be continued from
1011 scan_one_insn (insn, pass)
1015 enum rtx_code code = GET_CODE (insn);
1016 enum rtx_code pat_code;
1019 struct costs op_costs[MAX_RECOG_OPERANDS];
1021 if (GET_RTX_CLASS (code) != 'i')
1024 pat_code = GET_CODE (PATTERN (insn));
1026 || pat_code == CLOBBER
1027 || pat_code == ASM_INPUT
1028 || pat_code == ADDR_VEC
1029 || pat_code == ADDR_DIFF_VEC)
1032 set = single_set (insn);
1033 extract_insn (insn);
1035 /* If this insn loads a parameter from its stack slot, then
1036 it represents a savings, rather than a cost, if the
1037 parameter is stored in memory. Record this fact. */
1039 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1040 && GET_CODE (SET_SRC (set)) == MEM
1041 && (note = find_reg_note (insn, REG_EQUIV,
1043 && GET_CODE (XEXP (note, 0)) == MEM)
1045 costs[REGNO (SET_DEST (set))].mem_cost
1046 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1049 record_address_regs (XEXP (SET_SRC (set), 0),
1050 BASE_REG_CLASS, frequency * 2);
1054 /* Improve handling of two-address insns such as
1055 (set X (ashift CONST Y)) where CONST must be made to
1056 match X. Change it into two insns: (set X CONST)
1057 (set X (ashift X Y)). If we left this for reloading, it
1058 would probably get three insns because X and Y might go
1059 in the same place. This prevents X and Y from receiving
1062 We can only do this if the modes of operands 0 and 1
1063 (which might not be the same) are tieable and we only need
1064 do this during our first pass. */
1066 if (pass == 0 && optimize
1067 && recog_data.n_operands >= 3
1068 && recog_data.constraints[1][0] == '0'
1069 && recog_data.constraints[1][1] == 0
1070 && CONSTANT_P (recog_data.operand[1])
1071 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1072 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1073 && GET_CODE (recog_data.operand[0]) == REG
1074 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1075 recog_data.operand_mode[1]))
1077 rtx previnsn = prev_real_insn (insn);
1079 = gen_lowpart (recog_data.operand_mode[1],
1080 recog_data.operand[0]);
1082 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1084 /* If this insn was the start of a basic block,
1085 include the new insn in that block.
1086 We need not check for code_label here;
1087 while a basic block can start with a code_label,
1088 INSN could not be at the beginning of that block. */
1089 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1092 for (b = 0; b < n_basic_blocks; b++)
1093 if (insn == BLOCK_HEAD (b))
1094 BLOCK_HEAD (b) = newinsn;
1097 /* This makes one more setting of new insns's dest. */
1098 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1099 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1100 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1102 *recog_data.operand_loc[1] = recog_data.operand[0];
1103 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1104 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1105 for (i = recog_data.n_dups - 1; i >= 0; i--)
1106 if (recog_data.dup_num[i] == 1)
1108 *recog_data.dup_loc[i] = recog_data.operand[0];
1109 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1110 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1113 return PREV_INSN (newinsn);
1116 record_operand_costs (insn, op_costs, reg_pref);
1118 /* Now add the cost for each operand to the total costs for
1121 for (i = 0; i < recog_data.n_operands; i++)
1122 if (GET_CODE (recog_data.operand[i]) == REG
1123 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1125 int regno = REGNO (recog_data.operand[i]);
1126 struct costs *p = &costs[regno], *q = &op_costs[i];
1128 p->mem_cost += q->mem_cost * frequency;
1129 for (j = 0; j < N_REG_CLASSES; j++)
1130 p->cost[j] += q->cost[j] * frequency;
1136 /* This is a pass of the compiler that scans all instructions
1137 and calculates the preferred class for each pseudo-register.
1138 This information can be accessed later by calling `reg_preferred_class'.
1139 This pass comes just before local register allocation. */
1142 regclass (f, nregs, dump)
1153 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1155 #ifdef CLASS_CANNOT_CHANGE_MODE
1156 reg_changes_mode = BITMAP_XMALLOC();
1159 #ifdef FORBIDDEN_INC_DEC_CLASSES
1161 in_inc_dec = (char *) xmalloc (nregs);
1163 /* Initialize information about which register classes can be used for
1164 pseudos that are auto-incremented or auto-decremented. It would
1165 seem better to put this in init_reg_sets, but we need to be able
1166 to allocate rtx, which we can't do that early. */
1168 for (i = 0; i < N_REG_CLASSES; i++)
1170 rtx r = gen_rtx_REG (VOIDmode, 0);
1171 enum machine_mode m;
1174 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1175 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1179 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1180 m = (enum machine_mode) ((int) m + 1))
1181 if (HARD_REGNO_MODE_OK (j, m))
1185 /* If a register is not directly suitable for an
1186 auto-increment or decrement addressing mode and
1187 requires secondary reloads, disallow its class from
1188 being used in such addresses. */
1191 #ifdef SECONDARY_RELOAD_CLASS
1192 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1195 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1196 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1199 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1200 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1205 && ! auto_inc_dec_reg_p (r, m))
1206 forbidden_inc_dec_class[i] = 1;
1210 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1212 /* Normally we scan the insns once and determine the best class to use for
1213 each register. However, if -fexpensive_optimizations are on, we do so
1214 twice, the second time using the tentative best classes to guide the
1217 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1222 fprintf (dump, "\n\nPass %i\n\n",pass);
1223 /* Zero out our accumulation of the cost of each class for each reg. */
1225 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1227 #ifdef FORBIDDEN_INC_DEC_CLASSES
1228 memset (in_inc_dec, 0, nregs);
1231 /* Scan the instructions and record each time it would
1232 save code to put a certain register in a certain class. */
1236 frequency = REG_FREQ_MAX;
1237 for (insn = f; insn; insn = NEXT_INSN (insn))
1238 insn = scan_one_insn (insn, pass);
1241 for (index = 0; index < n_basic_blocks; index++)
1243 basic_block bb = BASIC_BLOCK (index);
1245 /* Show that an insn inside a loop is likely to be executed three
1246 times more than insns outside a loop. This is much more
1247 aggressive than the assumptions made elsewhere and is being
1248 tried as an experiment. */
1249 frequency = REG_FREQ_FROM_BB (bb);
1250 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1252 insn = scan_one_insn (insn, pass);
1253 if (insn == bb->end)
1258 /* Now for each register look at how desirable each class is
1259 and find which class is preferred. Store that in
1260 `prefclass'. Record in `altclass' the largest register
1261 class any of whose registers is better than memory. */
1264 reg_pref = reg_pref_buffer;
1268 dump_regclass (dump);
1269 fprintf (dump,"\n");
1271 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1273 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1274 enum reg_class best = ALL_REGS, alt = NO_REGS;
1275 /* This is an enum reg_class, but we call it an int
1276 to save lots of casts. */
1278 register struct costs *p = &costs[i];
1280 /* In non-optimizing compilation REG_N_REFS is not initialized
1282 if (optimize && !REG_N_REFS (i))
1285 for (class = (int) ALL_REGS - 1; class > 0; class--)
1287 /* Ignore classes that are too small for this operand or
1288 invalid for a operand that was auto-incremented. */
1289 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1290 #ifdef FORBIDDEN_INC_DEC_CLASSES
1291 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1293 #ifdef CLASS_CANNOT_CHANGE_MODE
1294 || (REGNO_REG_SET_P (reg_changes_mode, i)
1295 && ! class_can_change_mode [class])
1299 else if (p->cost[class] < best_cost)
1301 best_cost = p->cost[class];
1302 best = (enum reg_class) class;
1304 else if (p->cost[class] == best_cost)
1305 best = reg_class_subunion[(int)best][class];
1308 /* Record the alternate register class; i.e., a class for which
1309 every register in it is better than using memory. If adding a
1310 class would make a smaller class (i.e., no union of just those
1311 classes exists), skip that class. The major unions of classes
1312 should be provided as a register class. Don't do this if we
1313 will be doing it again later. */
1315 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1316 for (class = 0; class < N_REG_CLASSES; class++)
1317 if (p->cost[class] < p->mem_cost
1318 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1319 > reg_class_size[(int) alt])
1320 #ifdef FORBIDDEN_INC_DEC_CLASSES
1321 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1323 #ifdef CLASS_CANNOT_CHANGE_MODE
1324 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1325 && ! class_can_change_mode [class])
1328 alt = reg_class_subunion[(int) alt][class];
1330 /* If we don't add any classes, nothing to try. */
1335 && (reg_pref[i].prefclass != (int) best
1336 || reg_pref[i].altclass != (int) alt))
1338 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1339 fprintf (dump, " Register %i", i);
1340 if (alt == ALL_REGS || best == ALL_REGS)
1341 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1342 else if (alt == NO_REGS)
1343 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1345 fprintf (dump, " pref %s, else %s\n",
1346 reg_class_names[(int) best],
1347 reg_class_names[(int) alt]);
1350 /* We cast to (int) because (char) hits bugs in some compilers. */
1351 reg_pref[i].prefclass = (int) best;
1352 reg_pref[i].altclass = (int) alt;
1356 #ifdef FORBIDDEN_INC_DEC_CLASSES
1359 #ifdef CLASS_CANNOT_CHANGE_MODE
1360 BITMAP_XFREE (reg_changes_mode);
1365 /* Record the cost of using memory or registers of various classes for
1366 the operands in INSN.
1368 N_ALTS is the number of alternatives.
1370 N_OPS is the number of operands.
1372 OPS is an array of the operands.
1374 MODES are the modes of the operands, in case any are VOIDmode.
1376 CONSTRAINTS are the constraints to use for the operands. This array
1377 is modified by this procedure.
1379 This procedure works alternative by alternative. For each alternative
1380 we assume that we will be able to allocate all pseudos to their ideal
1381 register class and calculate the cost of using that alternative. Then
1382 we compute for each operand that is a pseudo-register, the cost of
1383 having the pseudo allocated to each register class and using it in that
1384 alternative. To this cost is added the cost of the alternative.
1386 The cost of each class for this insn is its lowest cost among all the
1390 record_reg_classes (n_alts, n_ops, ops, modes,
1391 constraints, insn, op_costs, reg_pref)
1395 enum machine_mode *modes;
1396 const char **constraints;
1398 struct costs *op_costs;
1399 struct reg_pref *reg_pref;
1405 /* Process each alternative, each time minimizing an operand's cost with
1406 the cost for each operand in that alternative. */
1408 for (alt = 0; alt < n_alts; alt++)
1410 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1413 enum reg_class classes[MAX_RECOG_OPERANDS];
1414 int allows_mem[MAX_RECOG_OPERANDS];
1417 for (i = 0; i < n_ops; i++)
1419 const char *p = constraints[i];
1421 enum machine_mode mode = modes[i];
1422 int allows_addr = 0;
1426 /* Initially show we know nothing about the register class. */
1427 classes[i] = NO_REGS;
1430 /* If this operand has no constraints at all, we can conclude
1431 nothing about it since anything is valid. */
1435 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1436 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1441 /* If this alternative is only relevant when this operand
1442 matches a previous operand, we do different things depending
1443 on whether this operand is a pseudo-reg or not. We must process
1444 any modifiers for the operand before we can make this test. */
1446 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1449 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1451 /* Copy class and whether memory is allowed from the matching
1452 alternative. Then perform any needed cost computations
1453 and/or adjustments. */
1455 classes[i] = classes[j];
1456 allows_mem[i] = allows_mem[j];
1458 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1460 /* If this matches the other operand, we have no added
1462 if (rtx_equal_p (ops[j], op))
1465 /* If we can put the other operand into a register, add to
1466 the cost of this alternative the cost to copy this
1467 operand to the register used for the other operand. */
1469 else if (classes[j] != NO_REGS)
1470 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1472 else if (GET_CODE (ops[j]) != REG
1473 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1475 /* This op is a pseudo but the one it matches is not. */
1477 /* If we can't put the other operand into a register, this
1478 alternative can't be used. */
1480 if (classes[j] == NO_REGS)
1483 /* Otherwise, add to the cost of this alternative the cost
1484 to copy the other operand to the register used for this
1488 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1492 /* The costs of this operand are not the same as the other
1493 operand since move costs are not symmetric. Moreover,
1494 if we cannot tie them, this alternative needs to do a
1495 copy, which is one instruction. */
1497 struct costs *pp = &this_op_costs[i];
1499 for (class = 0; class < N_REG_CLASSES; class++)
1501 = ((recog_data.operand_type[i] != OP_OUT
1502 ? may_move_in_cost[mode][class][(int) classes[i]]
1504 + (recog_data.operand_type[i] != OP_IN
1505 ? may_move_out_cost[mode][(int) classes[i]][class]
1508 /* If the alternative actually allows memory, make things
1509 a bit cheaper since we won't need an extra insn to
1513 = ((recog_data.operand_type[i] != OP_IN
1514 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1516 + (recog_data.operand_type[i] != OP_OUT
1517 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1518 : 0) - allows_mem[i]);
1520 /* If we have assigned a class to this register in our
1521 first pass, add a cost to this alternative corresponding
1522 to what we would add if this register were not in the
1523 appropriate class. */
1527 += (may_move_in_cost[mode]
1528 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1529 [(int) classes[i]]);
1531 if (REGNO (ops[i]) != REGNO (ops[j])
1532 && ! find_reg_note (insn, REG_DEAD, op))
1535 /* This is in place of ordinary cost computation
1536 for this operand, so skip to the end of the
1537 alternative (should be just one character). */
1538 while (*p && *p++ != ',')
1546 /* Scan all the constraint letters. See if the operand matches
1547 any of the constraints. Collect the valid register classes
1548 and see if this operand accepts memory. */
1550 while (*p && (c = *p++) != ',')
1554 /* Ignore the next letter for this pass. */
1560 case '!': case '#': case '&':
1561 case '0': case '1': case '2': case '3': case '4':
1562 case '5': case '6': case '7': case '8': case '9':
1567 win = address_operand (op, GET_MODE (op));
1568 /* We know this operand is an address, so we want it to be
1569 allocated to a register that can be the base of an
1570 address, ie BASE_REG_CLASS. */
1572 = reg_class_subunion[(int) classes[i]]
1573 [(int) BASE_REG_CLASS];
1576 case 'm': case 'o': case 'V':
1577 /* It doesn't seem worth distinguishing between offsettable
1578 and non-offsettable addresses here. */
1580 if (GET_CODE (op) == MEM)
1585 if (GET_CODE (op) == MEM
1586 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1587 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1592 if (GET_CODE (op) == MEM
1593 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1594 || GET_CODE (XEXP (op, 0)) == POST_INC))
1599 #ifndef REAL_ARITHMETIC
1600 /* Match any floating double constant, but only if
1601 we can examine the bits of it reliably. */
1602 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1603 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1604 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1607 if (GET_CODE (op) == CONST_DOUBLE)
1612 if (GET_CODE (op) == CONST_DOUBLE)
1618 if (GET_CODE (op) == CONST_DOUBLE
1619 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1624 if (GET_CODE (op) == CONST_INT
1625 || (GET_CODE (op) == CONST_DOUBLE
1626 && GET_MODE (op) == VOIDmode))
1630 #ifdef LEGITIMATE_PIC_OPERAND_P
1631 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1638 if (GET_CODE (op) == CONST_INT
1639 || (GET_CODE (op) == CONST_DOUBLE
1640 && GET_MODE (op) == VOIDmode))
1652 if (GET_CODE (op) == CONST_INT
1653 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1662 if (GET_CODE (op) == MEM
1664 #ifdef LEGITIMATE_PIC_OPERAND_P
1665 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1672 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1676 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1678 = reg_class_subunion[(int) classes[i]]
1679 [(int) REG_CLASS_FROM_LETTER (c)];
1680 #ifdef EXTRA_CONSTRAINT
1681 else if (EXTRA_CONSTRAINT (op, c))
1689 /* How we account for this operand now depends on whether it is a
1690 pseudo register or not. If it is, we first check if any
1691 register classes are valid. If not, we ignore this alternative,
1692 since we want to assume that all pseudos get allocated for
1693 register preferencing. If some register class is valid, compute
1694 the costs of moving the pseudo into that class. */
1696 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1698 if (classes[i] == NO_REGS)
1700 /* We must always fail if the operand is a REG, but
1701 we did not find a suitable class.
1703 Otherwise we may perform an uninitialized read
1704 from this_op_costs after the `continue' statement
1710 struct costs *pp = &this_op_costs[i];
1712 for (class = 0; class < N_REG_CLASSES; class++)
1714 = ((recog_data.operand_type[i] != OP_OUT
1715 ? may_move_in_cost[mode][class][(int) classes[i]]
1717 + (recog_data.operand_type[i] != OP_IN
1718 ? may_move_out_cost[mode][(int) classes[i]][class]
1721 /* If the alternative actually allows memory, make things
1722 a bit cheaper since we won't need an extra insn to
1726 = ((recog_data.operand_type[i] != OP_IN
1727 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1729 + (recog_data.operand_type[i] != OP_OUT
1730 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1731 : 0) - allows_mem[i]);
1733 /* If we have assigned a class to this register in our
1734 first pass, add a cost to this alternative corresponding
1735 to what we would add if this register were not in the
1736 appropriate class. */
1740 += (may_move_in_cost[mode]
1741 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1742 [(int) classes[i]]);
1746 /* Otherwise, if this alternative wins, either because we
1747 have already determined that or if we have a hard register of
1748 the proper class, there is no cost for this alternative. */
1751 || (GET_CODE (op) == REG
1752 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1755 /* If registers are valid, the cost of this alternative includes
1756 copying the object to and/or from a register. */
1758 else if (classes[i] != NO_REGS)
1760 if (recog_data.operand_type[i] != OP_OUT)
1761 alt_cost += copy_cost (op, mode, classes[i], 1);
1763 if (recog_data.operand_type[i] != OP_IN)
1764 alt_cost += copy_cost (op, mode, classes[i], 0);
1767 /* The only other way this alternative can be used is if this is a
1768 constant that could be placed into memory. */
1770 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1771 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1779 /* Finally, update the costs with the information we've calculated
1780 about this alternative. */
1782 for (i = 0; i < n_ops; i++)
1783 if (GET_CODE (ops[i]) == REG
1784 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1786 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1787 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1789 pp->mem_cost = MIN (pp->mem_cost,
1790 (qq->mem_cost + alt_cost) * scale);
1792 for (class = 0; class < N_REG_CLASSES; class++)
1793 pp->cost[class] = MIN (pp->cost[class],
1794 (qq->cost[class] + alt_cost) * scale);
1798 /* If this insn is a single set copying operand 1 to operand 0
1799 and one operand is a pseudo with the other a hard reg or a pseudo
1800 that prefers a register that is in its own register class then
1801 we may want to adjust the cost of that register class to -1.
1803 Avoid the adjustment if the source does not die to avoid stressing of
1804 register allocator by preferrencing two coliding registers into single
1807 Also avoid the adjustment if a copy between registers of the class
1808 is expensive (ten times the cost of a default copy is considered
1809 arbitrarily expensive). This avoids losing when the preferred class
1810 is very expensive as the source of a copy instruction. */
1812 if ((set = single_set (insn)) != 0
1813 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1814 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1815 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1816 for (i = 0; i <= 1; i++)
1817 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1819 unsigned int regno = REGNO (ops[!i]);
1820 enum machine_mode mode = GET_MODE (ops[!i]);
1824 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1826 enum reg_class pref = reg_pref[regno].prefclass;
1828 if ((reg_class_size[(unsigned char) pref]
1829 == CLASS_MAX_NREGS (pref, mode))
1830 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1831 op_costs[i].cost[(unsigned char) pref] = -1;
1833 else if (regno < FIRST_PSEUDO_REGISTER)
1834 for (class = 0; class < N_REG_CLASSES; class++)
1835 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1836 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1838 if (reg_class_size[class] == 1)
1839 op_costs[i].cost[class] = -1;
1842 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1844 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1849 if (nr == HARD_REGNO_NREGS (regno,mode))
1850 op_costs[i].cost[class] = -1;
1856 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1857 TO_P is zero) a register of class CLASS in mode MODE.
1859 X must not be a pseudo. */
1862 copy_cost (x, mode, class, to_p)
1864 enum machine_mode mode ATTRIBUTE_UNUSED;
1865 enum reg_class class;
1866 int to_p ATTRIBUTE_UNUSED;
1868 #ifdef HAVE_SECONDARY_RELOADS
1869 enum reg_class secondary_class = NO_REGS;
1872 /* If X is a SCRATCH, there is actually nothing to move since we are
1873 assuming optimal allocation. */
1875 if (GET_CODE (x) == SCRATCH)
1878 /* Get the class we will actually use for a reload. */
1879 class = PREFERRED_RELOAD_CLASS (x, class);
1881 #ifdef HAVE_SECONDARY_RELOADS
1882 /* If we need a secondary reload (we assume here that we are using
1883 the secondary reload as an intermediate, not a scratch register), the
1884 cost is that to load the input into the intermediate register, then
1885 to copy them. We use a special value of TO_P to avoid recursion. */
1887 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1889 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1892 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1894 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1897 if (secondary_class != NO_REGS)
1898 return (move_cost[mode][(int) secondary_class][(int) class]
1899 + copy_cost (x, mode, secondary_class, 2));
1900 #endif /* HAVE_SECONDARY_RELOADS */
1902 /* For memory, use the memory move cost, for (hard) registers, use the
1903 cost to move between the register classes, and use 2 for everything
1904 else (constants). */
1906 if (GET_CODE (x) == MEM || class == NO_REGS)
1907 return MEMORY_MOVE_COST (mode, class, to_p);
1909 else if (GET_CODE (x) == REG)
1910 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1913 /* If this is a constant, we may eventually want to call rtx_cost here. */
1914 return COSTS_N_INSNS (1);
1917 /* Record the pseudo registers we must reload into hard registers
1918 in a subexpression of a memory address, X.
1920 CLASS is the class that the register needs to be in and is either
1921 BASE_REG_CLASS or INDEX_REG_CLASS.
1923 SCALE is twice the amount to multiply the cost by (it is twice so we
1924 can represent half-cost adjustments). */
1927 record_address_regs (x, class, scale)
1929 enum reg_class class;
1932 register enum rtx_code code = GET_CODE (x);
1945 /* When we have an address that is a sum,
1946 we must determine whether registers are "base" or "index" regs.
1947 If there is a sum of two registers, we must choose one to be
1948 the "base". Luckily, we can use the REG_POINTER to make a good
1949 choice most of the time. We only need to do this on machines
1950 that can have two registers in an address and where the base
1951 and index register classes are different.
1953 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1954 that seems bogus since it should only be set when we are sure
1955 the register is being used as a pointer. */
1958 rtx arg0 = XEXP (x, 0);
1959 rtx arg1 = XEXP (x, 1);
1960 register enum rtx_code code0 = GET_CODE (arg0);
1961 register enum rtx_code code1 = GET_CODE (arg1);
1963 /* Look inside subregs. */
1964 if (code0 == SUBREG)
1965 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1966 if (code1 == SUBREG)
1967 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1969 /* If this machine only allows one register per address, it must
1970 be in the first operand. */
1972 if (MAX_REGS_PER_ADDRESS == 1)
1973 record_address_regs (arg0, class, scale);
1975 /* If index and base registers are the same on this machine, just
1976 record registers in any non-constant operands. We assume here,
1977 as well as in the tests below, that all addresses are in
1980 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1982 record_address_regs (arg0, class, scale);
1983 if (! CONSTANT_P (arg1))
1984 record_address_regs (arg1, class, scale);
1987 /* If the second operand is a constant integer, it doesn't change
1988 what class the first operand must be. */
1990 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1991 record_address_regs (arg0, class, scale);
1993 /* If the second operand is a symbolic constant, the first operand
1994 must be an index register. */
1996 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1997 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1999 /* If both operands are registers but one is already a hard register
2000 of index or base class, give the other the class that the hard
2003 #ifdef REG_OK_FOR_BASE_P
2004 else if (code0 == REG && code1 == REG
2005 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2006 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
2007 record_address_regs (arg1,
2008 REG_OK_FOR_BASE_P (arg0)
2009 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2011 else if (code0 == REG && code1 == REG
2012 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2013 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
2014 record_address_regs (arg0,
2015 REG_OK_FOR_BASE_P (arg1)
2016 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2020 /* If one operand is known to be a pointer, it must be the base
2021 with the other operand the index. Likewise if the other operand
2024 else if ((code0 == REG && REG_POINTER (arg0))
2027 record_address_regs (arg0, BASE_REG_CLASS, scale);
2028 record_address_regs (arg1, INDEX_REG_CLASS, scale);
2030 else if ((code1 == REG && REG_POINTER (arg1))
2033 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2034 record_address_regs (arg1, BASE_REG_CLASS, scale);
2037 /* Otherwise, count equal chances that each might be a base
2038 or index register. This case should be rare. */
2042 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
2043 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2044 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
2045 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2050 /* Double the importance of a pseudo register that is incremented
2051 or decremented, since it would take two extra insns
2052 if it ends up in the wrong place. */
2055 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
2056 if (REG_P (XEXP (XEXP (x, 1), 1)))
2057 record_address_regs (XEXP (XEXP (x, 1), 1),
2058 INDEX_REG_CLASS, 2 * scale);
2065 /* Double the importance of a pseudo register that is incremented
2066 or decremented, since it would take two extra insns
2067 if it ends up in the wrong place. If the operand is a pseudo,
2068 show it is being used in an INC_DEC context. */
2070 #ifdef FORBIDDEN_INC_DEC_CLASSES
2071 if (GET_CODE (XEXP (x, 0)) == REG
2072 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2073 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2076 record_address_regs (XEXP (x, 0), class, 2 * scale);
2081 register struct costs *pp = &costs[REGNO (x)];
2084 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2086 for (i = 0; i < N_REG_CLASSES; i++)
2087 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2093 register const char *fmt = GET_RTX_FORMAT (code);
2095 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2097 record_address_regs (XEXP (x, i), class, scale);
2102 #ifdef FORBIDDEN_INC_DEC_CLASSES
2104 /* Return 1 if REG is valid as an auto-increment memory reference
2105 to an object of MODE. */
2108 auto_inc_dec_reg_p (reg, mode)
2110 enum machine_mode mode;
2112 if (HAVE_POST_INCREMENT
2113 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2116 if (HAVE_POST_DECREMENT
2117 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2120 if (HAVE_PRE_INCREMENT
2121 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2124 if (HAVE_PRE_DECREMENT
2125 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2132 static short *renumber;
2133 static size_t regno_allocated;
2134 static unsigned int reg_n_max;
2136 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2137 reg_scan and flow_analysis that are indexed by the register number. If
2138 NEW_P is non zero, initialize all of the registers, otherwise only
2139 initialize the new registers allocated. The same table is kept from
2140 function to function, only reallocating it when we need more room. If
2141 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2144 allocate_reg_info (num_regs, new_p, renumber_p)
2150 size_t size_renumber;
2151 size_t min = (new_p) ? 0 : reg_n_max;
2152 struct reg_info_data *reg_data;
2154 if (num_regs > regno_allocated)
2156 size_t old_allocated = regno_allocated;
2158 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2159 size_renumber = regno_allocated * sizeof (short);
2163 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2164 renumber = (short *) xmalloc (size_renumber);
2165 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2166 * sizeof (struct reg_pref));
2171 VARRAY_GROW (reg_n_info, regno_allocated);
2173 if (new_p) /* if we're zapping everything, no need to realloc */
2175 free ((char *)renumber);
2176 free ((char *)reg_pref);
2177 renumber = (short *) xmalloc (size_renumber);
2178 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2179 * sizeof (struct reg_pref));
2184 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2185 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2187 * sizeof (struct reg_pref));
2191 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2192 + sizeof (struct reg_info_data) - sizeof (reg_info);
2193 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2194 reg_data->min_index = old_allocated;
2195 reg_data->max_index = regno_allocated - 1;
2196 reg_data->next = reg_info_head;
2197 reg_info_head = reg_data;
2200 reg_n_max = num_regs;
2203 /* Loop through each of the segments allocated for the actual
2204 reg_info pages, and set up the pointers, zero the pages, etc. */
2205 for (reg_data = reg_info_head;
2206 reg_data && reg_data->max_index >= min;
2207 reg_data = reg_data->next)
2209 size_t min_index = reg_data->min_index;
2210 size_t max_index = reg_data->max_index;
2211 size_t max = MIN (max_index, num_regs);
2212 size_t local_min = min - min_index;
2215 if (reg_data->min_index > num_regs)
2218 if (min < min_index)
2220 if (!reg_data->used_p) /* page just allocated with calloc */
2221 reg_data->used_p = 1; /* no need to zero */
2223 memset ((char *) ®_data->data[local_min], 0,
2224 sizeof (reg_info) * (max - min_index - local_min + 1));
2226 for (i = min_index+local_min; i <= max; i++)
2228 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2229 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2231 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2232 reg_pref_buffer[i].altclass = (char) NO_REGS;
2237 /* If {pref,alt}class have already been allocated, update the pointers to
2238 the newly realloced ones. */
2240 reg_pref = reg_pref_buffer;
2243 reg_renumber = renumber;
2245 /* Tell the regset code about the new number of registers */
2246 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2249 /* Free up the space allocated by allocate_reg_info. */
2255 struct reg_info_data *reg_data;
2256 struct reg_info_data *reg_next;
2258 VARRAY_FREE (reg_n_info);
2259 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2261 reg_next = reg_data->next;
2262 free ((char *)reg_data);
2265 free (reg_pref_buffer);
2266 reg_pref_buffer = (struct reg_pref *)0;
2267 reg_info_head = (struct reg_info_data *)0;
2268 renumber = (short *)0;
2270 regno_allocated = 0;
2274 /* This is the `regscan' pass of the compiler, run just before cse
2275 and again just before loop.
2277 It finds the first and last use of each pseudo-register
2278 and records them in the vectors regno_first_uid, regno_last_uid
2279 and counts the number of sets in the vector reg_n_sets.
2281 REPEAT is nonzero the second time this is called. */
2283 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2284 Always at least 3, since the combiner could put that many together
2285 and we want this to remain correct for all the remaining passes.
2286 This corresponds to the maximum number of times note_stores will call
2287 a function for any insn. */
2291 /* Used as a temporary to record the largest number of registers in
2292 PARALLEL in a SET_DEST. This is added to max_parallel. */
2294 static int max_set_parallel;
2297 reg_scan (f, nregs, repeat)
2300 int repeat ATTRIBUTE_UNUSED;
2304 allocate_reg_info (nregs, TRUE, FALSE);
2306 max_set_parallel = 0;
2308 for (insn = f; insn; insn = NEXT_INSN (insn))
2309 if (GET_CODE (insn) == INSN
2310 || GET_CODE (insn) == CALL_INSN
2311 || GET_CODE (insn) == JUMP_INSN)
2313 if (GET_CODE (PATTERN (insn)) == PARALLEL
2314 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2315 max_parallel = XVECLEN (PATTERN (insn), 0);
2316 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2318 if (REG_NOTES (insn))
2319 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2322 max_parallel += max_set_parallel;
2325 /* Update 'regscan' information by looking at the insns
2326 from FIRST to LAST. Some new REGs have been created,
2327 and any REG with number greater than OLD_MAX_REGNO is
2328 such a REG. We only update information for those. */
2331 reg_scan_update (first, last, old_max_regno)
2334 unsigned int old_max_regno;
2338 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2340 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2341 if (GET_CODE (insn) == INSN
2342 || GET_CODE (insn) == CALL_INSN
2343 || GET_CODE (insn) == JUMP_INSN)
2345 if (GET_CODE (PATTERN (insn)) == PARALLEL
2346 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2347 max_parallel = XVECLEN (PATTERN (insn), 0);
2348 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2350 if (REG_NOTES (insn))
2351 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2355 /* X is the expression to scan. INSN is the insn it appears in.
2356 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2357 We should only record information for REGs with numbers
2358 greater than or equal to MIN_REGNO. */
2361 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2365 unsigned int min_regno;
2367 register enum rtx_code code;
2371 code = GET_CODE (x);
2387 unsigned int regno = REGNO (x);
2389 if (regno >= min_regno)
2391 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2393 REGNO_LAST_UID (regno) = INSN_UID (insn);
2394 if (REGNO_FIRST_UID (regno) == 0)
2395 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2402 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2404 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2409 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2413 /* Count a set of the destination if it is a register. */
2414 for (dest = SET_DEST (x);
2415 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2416 || GET_CODE (dest) == ZERO_EXTEND;
2417 dest = XEXP (dest, 0))
2420 /* For a PARALLEL, record the number of things (less the usual one for a
2421 SET) that are set. */
2422 if (GET_CODE (dest) == PARALLEL)
2423 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2425 if (GET_CODE (dest) == REG
2426 && REGNO (dest) >= min_regno)
2428 REG_N_SETS (REGNO (dest))++;
2429 REG_N_REFS (REGNO (dest))++;
2432 /* If this is setting a pseudo from another pseudo or the sum of a
2433 pseudo and a constant integer and the other pseudo is known to be
2434 a pointer, set the destination to be a pointer as well.
2436 Likewise if it is setting the destination from an address or from a
2437 value equivalent to an address or to the sum of an address and
2440 But don't do any of this if the pseudo corresponds to a user
2441 variable since it should have already been set as a pointer based
2444 if (GET_CODE (SET_DEST (x)) == REG
2445 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2446 && REGNO (SET_DEST (x)) >= min_regno
2447 /* If the destination pseudo is set more than once, then other
2448 sets might not be to a pointer value (consider access to a
2449 union in two threads of control in the presense of global
2450 optimizations). So only set REG_POINTER on the destination
2451 pseudo if this is the only set of that pseudo. */
2452 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2453 && ! REG_USERVAR_P (SET_DEST (x))
2454 && ! REG_POINTER (SET_DEST (x))
2455 && ((GET_CODE (SET_SRC (x)) == REG
2456 && REG_POINTER (SET_SRC (x)))
2457 || ((GET_CODE (SET_SRC (x)) == PLUS
2458 || GET_CODE (SET_SRC (x)) == LO_SUM)
2459 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2460 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2461 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2462 || GET_CODE (SET_SRC (x)) == CONST
2463 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2464 || GET_CODE (SET_SRC (x)) == LABEL_REF
2465 || (GET_CODE (SET_SRC (x)) == HIGH
2466 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2467 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2468 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2469 || ((GET_CODE (SET_SRC (x)) == PLUS
2470 || GET_CODE (SET_SRC (x)) == LO_SUM)
2471 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2472 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2473 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2474 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2475 && (GET_CODE (XEXP (note, 0)) == CONST
2476 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2477 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2478 REG_POINTER (SET_DEST (x)) = 1;
2480 /* ... fall through ... */
2484 register const char *fmt = GET_RTX_FORMAT (code);
2486 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2489 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2490 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2493 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2494 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2501 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2505 reg_class_subset_p (c1, c2)
2506 register enum reg_class c1;
2507 register enum reg_class c2;
2509 if (c1 == c2) return 1;
2514 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2515 reg_class_contents[(int)c2],
2520 /* Return nonzero if there is a register that is in both C1 and C2. */
2523 reg_classes_intersect_p (c1, c2)
2524 register enum reg_class c1;
2525 register enum reg_class c2;
2532 if (c1 == c2) return 1;
2534 if (c1 == ALL_REGS || c2 == ALL_REGS)
2537 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2538 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2540 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2547 /* Release any memory allocated by register sets. */
2550 regset_release_memory ()
2552 bitmap_release_memory ();