1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(m, x, y) 2
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* 1 if class does contain register of given mode. */
179 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
181 /* Maximum cost of moving from a register in one class to a register in
182 another class. Based on REGISTER_MOVE_COST. */
184 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
186 /* Similar, but here we don't have to move if the first index is a subset
187 of the second so in that case the cost is zero. */
189 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
191 /* Similar, but here we don't have to move if the first index is a superset
192 of the second so in that case the cost is zero. */
194 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
196 #ifdef FORBIDDEN_INC_DEC_CLASSES
198 /* These are the classes that regs which are auto-incremented or decremented
201 static int forbidden_inc_dec_class[N_REG_CLASSES];
203 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
206 static char *in_inc_dec;
208 #endif /* FORBIDDEN_INC_DEC_CLASSES */
210 #ifdef CLASS_CANNOT_CHANGE_MODE
212 /* These are the classes containing only registers that can be used in
213 a SUBREG expression that changes the mode of the register in some
214 way that is illegal. */
216 static int class_can_change_mode[N_REG_CLASSES];
218 /* Registers, including pseudos, which change modes in some way that
221 static regset reg_changes_mode;
223 #endif /* CLASS_CANNOT_CHANGE_MODE */
225 #ifdef HAVE_SECONDARY_RELOADS
227 /* Sample MEM values for use by memory_move_secondary_cost. */
229 static rtx top_of_stack[MAX_MACHINE_MODE];
231 #endif /* HAVE_SECONDARY_RELOADS */
233 /* Linked list of reg_info structures allocated for reg_n_info array.
234 Grouping all of the allocated structures together in one lump
235 means only one call to bzero to clear them, rather than n smaller
237 struct reg_info_data {
238 struct reg_info_data *next; /* next set of reg_info structures */
239 size_t min_index; /* minimum index # */
240 size_t max_index; /* maximum index # */
241 char used_p; /* non-zero if this has been used previously */
242 reg_info data[1]; /* beginning of the reg_info data */
245 static struct reg_info_data *reg_info_head;
247 /* No more global register variables may be declared; true once
248 regclass has been initialized. */
250 static int no_global_reg_vars = 0;
253 /* Function called only once to initialize the above data on reg usage.
254 Once this is done, various switches may override. */
261 /* First copy the register information from the initial int form into
264 for (i = 0; i < N_REG_CLASSES; i++)
266 CLEAR_HARD_REG_SET (reg_class_contents[i]);
268 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
269 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
270 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
271 SET_HARD_REG_BIT (reg_class_contents[i], j);
274 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
275 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
276 memset (global_regs, 0, sizeof global_regs);
278 /* Do any additional initialization regsets may need */
279 INIT_ONCE_REG_SET ();
281 #ifdef REG_ALLOC_ORDER
282 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
283 inv_reg_alloc_order[reg_alloc_order[i]] = i;
287 /* After switches have been processed, which perhaps alter
288 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
293 register unsigned int i, j;
294 register unsigned int /* enum machine_mode */ m;
295 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
297 /* This macro allows the fixed or call-used registers
298 and the register classes to depend on target flags. */
300 #ifdef CONDITIONAL_REGISTER_USAGE
301 CONDITIONAL_REGISTER_USAGE;
304 /* Compute number of hard regs in each class. */
306 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
307 for (i = 0; i < N_REG_CLASSES; i++)
308 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
309 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
312 /* Initialize the table of subunions.
313 reg_class_subunion[I][J] gets the largest-numbered reg-class
314 that is contained in the union of classes I and J. */
316 for (i = 0; i < N_REG_CLASSES; i++)
318 for (j = 0; j < N_REG_CLASSES; j++)
321 register /* Declare it register if it's a scalar. */
326 COPY_HARD_REG_SET (c, reg_class_contents[i]);
327 IOR_HARD_REG_SET (c, reg_class_contents[j]);
328 for (k = 0; k < N_REG_CLASSES; k++)
330 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
335 /* keep the largest subclass */ /* SPEE 900308 */
336 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
337 reg_class_contents[(int) reg_class_subunion[i][j]],
339 reg_class_subunion[i][j] = (enum reg_class) k;
346 /* Initialize the table of superunions.
347 reg_class_superunion[I][J] gets the smallest-numbered reg-class
348 containing the union of classes I and J. */
350 for (i = 0; i < N_REG_CLASSES; i++)
352 for (j = 0; j < N_REG_CLASSES; j++)
355 register /* Declare it register if it's a scalar. */
360 COPY_HARD_REG_SET (c, reg_class_contents[i]);
361 IOR_HARD_REG_SET (c, reg_class_contents[j]);
362 for (k = 0; k < N_REG_CLASSES; k++)
363 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
366 reg_class_superunion[i][j] = (enum reg_class) k;
370 /* Initialize the tables of subclasses and superclasses of each reg class.
371 First clear the whole table, then add the elements as they are found. */
373 for (i = 0; i < N_REG_CLASSES; i++)
375 for (j = 0; j < N_REG_CLASSES; j++)
377 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
378 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
382 for (i = 0; i < N_REG_CLASSES; i++)
384 if (i == (int) NO_REGS)
387 for (j = i + 1; j < N_REG_CLASSES; j++)
391 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
395 /* Reg class I is a subclass of J.
396 Add J to the table of superclasses of I. */
397 p = ®_class_superclasses[i][0];
398 while (*p != LIM_REG_CLASSES) p++;
399 *p = (enum reg_class) j;
400 /* Add I to the table of superclasses of J. */
401 p = ®_class_subclasses[j][0];
402 while (*p != LIM_REG_CLASSES) p++;
403 *p = (enum reg_class) i;
407 /* Initialize "constant" tables. */
409 CLEAR_HARD_REG_SET (fixed_reg_set);
410 CLEAR_HARD_REG_SET (call_used_reg_set);
411 CLEAR_HARD_REG_SET (call_fixed_reg_set);
413 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
415 n_non_fixed_regs = 0;
417 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
420 SET_HARD_REG_BIT (fixed_reg_set, i);
424 if (call_used_regs[i])
425 SET_HARD_REG_BIT (call_used_reg_set, i);
426 if (call_fixed_regs[i])
427 SET_HARD_REG_BIT (call_fixed_reg_set, i);
428 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
429 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
431 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
432 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
433 for (m = 0; m < MAX_MACHINE_MODE; m++)
434 for (i = 0; i < N_REG_CLASSES; i++)
435 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
436 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
437 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
438 && HARD_REGNO_MODE_OK (j, m))
440 contains_reg_of_mode [i][m] = 1;
441 allocatable_regs_of_mode [m] = 1;
445 /* Initialize the move cost table. Find every subset of each class
446 and take the maximum cost of moving any subset to any other. */
448 for (m = 0; m < MAX_MACHINE_MODE; m++)
449 if (allocatable_regs_of_mode [m])
451 for (i = 0; i < N_REG_CLASSES; i++)
452 if (contains_reg_of_mode [i][m])
453 for (j = 0; j < N_REG_CLASSES; j++)
456 enum reg_class *p1, *p2;
458 if (!contains_reg_of_mode [j][m])
460 move_cost[m][i][j] = 65536;
461 may_move_in_cost[m][i][j] = 65536;
462 may_move_out_cost[m][i][j] = 65536;
466 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
468 for (p2 = ®_class_subclasses[j][0];
469 *p2 != LIM_REG_CLASSES;
471 if (*p2 != i && contains_reg_of_mode [*p2][m])
472 cost = MAX (cost, move_cost [m][i][*p2]);
474 for (p1 = ®_class_subclasses[i][0];
475 *p1 != LIM_REG_CLASSES;
477 if (*p1 != j && contains_reg_of_mode [*p1][m])
478 cost = MAX (cost, move_cost [m][*p1][j]);
480 move_cost[m][i][j] = cost;
482 if (reg_class_subset_p (i, j))
483 may_move_in_cost[m][i][j] = 0;
485 may_move_in_cost[m][i][j] = cost;
487 if (reg_class_subset_p (j, i))
488 may_move_out_cost[m][i][j] = 0;
490 may_move_out_cost[m][i][j] = cost;
494 for (j = 0; j < N_REG_CLASSES; j++)
496 move_cost[m][i][j] = 65536;
497 may_move_in_cost[m][i][j] = 65536;
498 may_move_out_cost[m][i][j] = 65536;
502 #ifdef CLASS_CANNOT_CHANGE_MODE
505 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
507 for (i = 0; i < N_REG_CLASSES; i++)
509 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
510 class_can_change_mode [i] = 0;
513 class_can_change_mode [i] = 1;
516 #endif /* CLASS_CANNOT_CHANGE_MODE */
519 /* Compute the table of register modes.
520 These values are used to record death information for individual registers
521 (as opposed to a multi-register mode). */
528 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
530 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
532 /* If we couldn't find a valid mode, just use the previous mode.
533 ??? One situation in which we need to do this is on the mips where
534 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
535 to use DF mode for the even registers and VOIDmode for the odd
536 (for the cpu models where the odd ones are inaccessible). */
537 if (reg_raw_mode[i] == VOIDmode)
538 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
542 /* Finish initializing the register sets and
543 initialize the register modes. */
548 /* This finishes what was started by init_reg_sets, but couldn't be done
549 until after register usage was specified. */
554 #ifdef HAVE_SECONDARY_RELOADS
556 /* Make some fake stack-frame MEM references for use in
557 memory_move_secondary_cost. */
560 for (i = 0; i < MAX_MACHINE_MODE; i++)
561 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
562 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
567 #ifdef HAVE_SECONDARY_RELOADS
569 /* Compute extra cost of moving registers to/from memory due to reloads.
570 Only needed if secondary reloads are required for memory moves. */
573 memory_move_secondary_cost (mode, class, in)
574 enum machine_mode mode;
575 enum reg_class class;
578 enum reg_class altclass;
579 int partial_cost = 0;
580 /* We need a memory reference to feed to SECONDARY... macros. */
581 /* mem may be unused even if the SECONDARY_ macros are defined. */
582 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
587 #ifdef SECONDARY_INPUT_RELOAD_CLASS
588 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
595 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
596 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
602 if (altclass == NO_REGS)
606 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
608 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
610 if (class == altclass)
611 /* This isn't simply a copy-to-temporary situation. Can't guess
612 what it is, so MEMORY_MOVE_COST really ought not to be calling
615 I'm tempted to put in an abort here, but returning this will
616 probably only give poor estimates, which is what we would've
617 had before this code anyways. */
620 /* Check if the secondary reload register will also need a
622 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
626 /* Return a machine mode that is legitimate for hard reg REGNO and large
627 enough to save nregs. If we can't find one, return VOIDmode. */
630 choose_hard_reg_mode (regno, nregs)
631 unsigned int regno ATTRIBUTE_UNUSED;
634 enum machine_mode found_mode = VOIDmode, mode;
636 /* We first look for the largest integer mode that can be validly
637 held in REGNO. If none, we look for the largest floating-point mode.
638 If we still didn't find a valid mode, try CCmode. */
640 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
642 mode = GET_MODE_WIDER_MODE (mode))
643 if (HARD_REGNO_NREGS (regno, mode) == nregs
644 && HARD_REGNO_MODE_OK (regno, mode))
647 if (found_mode != VOIDmode)
650 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
652 mode = GET_MODE_WIDER_MODE (mode))
653 if (HARD_REGNO_NREGS (regno, mode) == nregs
654 && HARD_REGNO_MODE_OK (regno, mode))
657 if (found_mode != VOIDmode)
660 /* Iterate over all of the CCmodes. */
661 for (mode = CCmode; mode < NUM_MACHINE_MODES; ++mode)
662 if (HARD_REGNO_NREGS (regno, mode) == nregs
663 && HARD_REGNO_MODE_OK (regno, mode))
666 /* We can't find a mode valid for this register. */
670 /* Specify the usage characteristics of the register named NAME.
671 It should be a fixed register if FIXED and a
672 call-used register if CALL_USED. */
675 fix_register (name, fixed, call_used)
677 int fixed, call_used;
681 /* Decode the name and update the primary form of
682 the register info. */
684 if ((i = decode_reg_name (name)) >= 0)
686 if ((i == STACK_POINTER_REGNUM
687 #ifdef HARD_FRAME_POINTER_REGNUM
688 || i == HARD_FRAME_POINTER_REGNUM
690 || i == FRAME_POINTER_REGNUM
693 && (fixed == 0 || call_used == 0))
695 static const char * const what_option[2][2] = {
696 { "call-saved", "call-used" },
697 { "no-such-option", "fixed" }};
699 error ("can't use '%s' as a %s register", name,
700 what_option[fixed][call_used]);
704 fixed_regs[i] = fixed;
705 call_used_regs[i] = call_used;
710 warning ("unknown register name: %s", name);
714 /* Mark register number I as global. */
720 if (fixed_regs[i] == 0 && no_global_reg_vars)
721 error ("global register variable follows a function definition");
725 warning ("register used for two global register variables");
729 if (call_used_regs[i] && ! fixed_regs[i])
730 warning ("call-clobbered register used for global register variable");
734 /* If already fixed, nothing else to do. */
738 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
741 SET_HARD_REG_BIT (fixed_reg_set, i);
742 SET_HARD_REG_BIT (call_used_reg_set, i);
743 SET_HARD_REG_BIT (call_fixed_reg_set, i);
746 /* Now the data and code for the `regclass' pass, which happens
747 just before local-alloc. */
749 /* The `costs' struct records the cost of using a hard register of each class
750 and of using memory for each pseudo. We use this data to set up
751 register class preferences. */
755 int cost[N_REG_CLASSES];
759 /* Structure used to record preferrences of given pseudo. */
762 /* (enum reg_class) prefclass is the preferred class. */
765 /* altclass is a register class that we should use for allocating
766 pseudo if no register in the preferred class is available.
767 If no register in this class is available, memory is preferred.
769 It might appear to be more general to have a bitmask of classes here,
770 but since it is recommended that there be a class corresponding to the
771 union of most major pair of classes, that generality is not required. */
775 /* Record the cost of each class for each pseudo. */
777 static struct costs *costs;
779 /* Initialized once, and used to initialize cost values for each insn. */
781 static struct costs init_cost;
783 /* Record preferrences of each pseudo.
784 This is available after `regclass' is run. */
786 static struct reg_pref *reg_pref;
788 /* Allocated buffers for reg_pref. */
790 static struct reg_pref *reg_pref_buffer;
792 /* Account for the fact that insns within a loop are executed very commonly,
793 but don't keep doing this as loops go too deep. */
795 static int loop_cost;
797 static rtx scan_one_insn PARAMS ((rtx, int));
798 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
799 static void dump_regclass PARAMS ((FILE *));
800 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
802 struct costs *, struct reg_pref *));
803 static int copy_cost PARAMS ((rtx, enum machine_mode,
804 enum reg_class, int));
805 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
806 #ifdef FORBIDDEN_INC_DEC_CLASSES
807 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
809 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
811 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
812 This function is sometimes called before the info has been computed.
813 When that happens, just return GENERAL_REGS, which is innocuous. */
816 reg_preferred_class (regno)
821 return (enum reg_class) reg_pref[regno].prefclass;
825 reg_alternate_class (regno)
831 return (enum reg_class) reg_pref[regno].altclass;
834 /* Initialize some global data for this pass. */
841 init_cost.mem_cost = 10000;
842 for (i = 0; i < N_REG_CLASSES; i++)
843 init_cost.cost[i] = 10000;
845 /* This prevents dump_flow_info from losing if called
846 before regclass is run. */
849 /* No more global register variables may be declared. */
850 no_global_reg_vars = 1;
853 /* Dump register costs. */
858 static const char *const reg_class_names[] = REG_CLASS_NAMES;
860 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
862 enum reg_class class;
865 fprintf (dump, " Register %i costs:", i);
866 for (class = 0; class < N_REG_CLASSES; class++)
867 if (contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
868 #ifdef FORBIDDEN_INC_DEC_CLASSES
869 && (!in_inc_dec[i] || !forbidden_inc_dec_class[class])
871 #ifdef CLASS_CANNOT_CHANGE_MODE
872 && (!REGNO_REG_SET_P (reg_changes_mode, i)
873 || class_can_change_mode [class])
876 fprintf (dump, " %s:%i", reg_class_names[(int) class],
877 costs[i].cost[class]);
878 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
884 /* Calculate the costs of insn operands. */
887 record_operand_costs (insn, op_costs, reg_pref)
889 struct costs *op_costs;
890 struct reg_pref *reg_pref;
892 const char *constraints[MAX_RECOG_OPERANDS];
893 enum machine_mode modes[MAX_RECOG_OPERANDS];
896 for (i = 0; i < recog_data.n_operands; i++)
898 constraints[i] = recog_data.constraints[i];
899 modes[i] = recog_data.operand_mode[i];
902 /* If we get here, we are set up to record the costs of all the
903 operands for this insn. Start by initializing the costs.
904 Then handle any address registers. Finally record the desired
905 classes for any pseudos, doing it twice if some pair of
906 operands are commutative. */
908 for (i = 0; i < recog_data.n_operands; i++)
910 op_costs[i] = init_cost;
912 if (GET_CODE (recog_data.operand[i]) == SUBREG)
914 rtx inner = SUBREG_REG (recog_data.operand[i]);
915 #ifdef CLASS_CANNOT_CHANGE_MODE
916 if (GET_CODE (inner) == REG
917 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
918 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
920 recog_data.operand[i] = inner;
923 if (GET_CODE (recog_data.operand[i]) == MEM)
924 record_address_regs (XEXP (recog_data.operand[i], 0),
925 BASE_REG_CLASS, loop_cost * 2);
926 else if (constraints[i][0] == 'p')
927 record_address_regs (recog_data.operand[i],
928 BASE_REG_CLASS, loop_cost * 2);
931 /* Check for commutative in a separate loop so everything will
932 have been initialized. We must do this even if one operand
933 is a constant--see addsi3 in m68k.md. */
935 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
936 if (constraints[i][0] == '%')
938 const char *xconstraints[MAX_RECOG_OPERANDS];
941 /* Handle commutative operands by swapping the constraints.
942 We assume the modes are the same. */
944 for (j = 0; j < recog_data.n_operands; j++)
945 xconstraints[j] = constraints[j];
947 xconstraints[i] = constraints[i+1];
948 xconstraints[i+1] = constraints[i];
949 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
950 recog_data.operand, modes,
951 xconstraints, insn, op_costs, reg_pref);
954 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
955 recog_data.operand, modes,
956 constraints, insn, op_costs, reg_pref);
959 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
960 time it would save code to put a certain register in a certain class.
961 PASS, when nonzero, inhibits some optimizations which need only be done
963 Return the last insn processed, so that the scan can be continued from
967 scan_one_insn (insn, pass)
971 enum rtx_code code = GET_CODE (insn);
972 enum rtx_code pat_code;
975 struct costs op_costs[MAX_RECOG_OPERANDS];
977 if (GET_RTX_CLASS (code) != 'i')
980 pat_code = GET_CODE (PATTERN (insn));
982 || pat_code == CLOBBER
983 || pat_code == ASM_INPUT
984 || pat_code == ADDR_VEC
985 || pat_code == ADDR_DIFF_VEC)
988 set = single_set (insn);
991 /* If this insn loads a parameter from its stack slot, then
992 it represents a savings, rather than a cost, if the
993 parameter is stored in memory. Record this fact. */
995 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
996 && GET_CODE (SET_SRC (set)) == MEM
997 && (note = find_reg_note (insn, REG_EQUIV,
999 && GET_CODE (XEXP (note, 0)) == MEM)
1001 costs[REGNO (SET_DEST (set))].mem_cost
1002 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1005 record_address_regs (XEXP (SET_SRC (set), 0),
1006 BASE_REG_CLASS, loop_cost * 2);
1010 /* Improve handling of two-address insns such as
1011 (set X (ashift CONST Y)) where CONST must be made to
1012 match X. Change it into two insns: (set X CONST)
1013 (set X (ashift X Y)). If we left this for reloading, it
1014 would probably get three insns because X and Y might go
1015 in the same place. This prevents X and Y from receiving
1018 We can only do this if the modes of operands 0 and 1
1019 (which might not be the same) are tieable and we only need
1020 do this during our first pass. */
1022 if (pass == 0 && optimize
1023 && recog_data.n_operands >= 3
1024 && recog_data.constraints[1][0] == '0'
1025 && recog_data.constraints[1][1] == 0
1026 && CONSTANT_P (recog_data.operand[1])
1027 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1028 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1029 && GET_CODE (recog_data.operand[0]) == REG
1030 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1031 recog_data.operand_mode[1]))
1033 rtx previnsn = prev_real_insn (insn);
1035 = gen_lowpart (recog_data.operand_mode[1],
1036 recog_data.operand[0]);
1038 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1040 /* If this insn was the start of a basic block,
1041 include the new insn in that block.
1042 We need not check for code_label here;
1043 while a basic block can start with a code_label,
1044 INSN could not be at the beginning of that block. */
1045 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1048 for (b = 0; b < n_basic_blocks; b++)
1049 if (insn == BLOCK_HEAD (b))
1050 BLOCK_HEAD (b) = newinsn;
1053 /* This makes one more setting of new insns's dest. */
1054 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1056 *recog_data.operand_loc[1] = recog_data.operand[0];
1057 for (i = recog_data.n_dups - 1; i >= 0; i--)
1058 if (recog_data.dup_num[i] == 1)
1059 *recog_data.dup_loc[i] = recog_data.operand[0];
1061 return PREV_INSN (newinsn);
1064 record_operand_costs (insn, op_costs, reg_pref);
1066 /* Now add the cost for each operand to the total costs for
1069 for (i = 0; i < recog_data.n_operands; i++)
1070 if (GET_CODE (recog_data.operand[i]) == REG
1071 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1073 int regno = REGNO (recog_data.operand[i]);
1074 struct costs *p = &costs[regno], *q = &op_costs[i];
1076 p->mem_cost += q->mem_cost * loop_cost;
1077 for (j = 0; j < N_REG_CLASSES; j++)
1078 p->cost[j] += q->cost[j] * loop_cost;
1084 /* This is a pass of the compiler that scans all instructions
1085 and calculates the preferred class for each pseudo-register.
1086 This information can be accessed later by calling `reg_preferred_class'.
1087 This pass comes just before local register allocation. */
1090 regclass (f, nregs, dump)
1101 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1103 #ifdef CLASS_CANNOT_CHANGE_MODE
1104 reg_changes_mode = BITMAP_XMALLOC();
1107 #ifdef FORBIDDEN_INC_DEC_CLASSES
1109 in_inc_dec = (char *) xmalloc (nregs);
1111 /* Initialize information about which register classes can be used for
1112 pseudos that are auto-incremented or auto-decremented. It would
1113 seem better to put this in init_reg_sets, but we need to be able
1114 to allocate rtx, which we can't do that early. */
1116 for (i = 0; i < N_REG_CLASSES; i++)
1118 rtx r = gen_rtx_REG (VOIDmode, 0);
1119 enum machine_mode m;
1122 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1123 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1127 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1128 m = (enum machine_mode) ((int) m + 1))
1129 if (HARD_REGNO_MODE_OK (j, m))
1133 /* If a register is not directly suitable for an
1134 auto-increment or decrement addressing mode and
1135 requires secondary reloads, disallow its class from
1136 being used in such addresses. */
1139 #ifdef SECONDARY_RELOAD_CLASS
1140 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1143 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1144 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1147 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1148 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1153 && ! auto_inc_dec_reg_p (r, m))
1154 forbidden_inc_dec_class[i] = 1;
1158 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1160 /* Normally we scan the insns once and determine the best class to use for
1161 each register. However, if -fexpensive_optimizations are on, we do so
1162 twice, the second time using the tentative best classes to guide the
1165 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1170 fprintf (dump, "\n\nPass %i\n\n",pass);
1171 /* Zero out our accumulation of the cost of each class for each reg. */
1173 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1175 #ifdef FORBIDDEN_INC_DEC_CLASSES
1176 memset (in_inc_dec, 0, nregs);
1179 /* Scan the instructions and record each time it would
1180 save code to put a certain register in a certain class. */
1185 for (insn = f; insn; insn = NEXT_INSN (insn))
1186 insn = scan_one_insn (insn, pass);
1189 for (index = 0; index < n_basic_blocks; index++)
1191 basic_block bb = BASIC_BLOCK (index);
1193 /* Show that an insn inside a loop is likely to be executed three
1194 times more than insns outside a loop. This is much more
1195 aggressive than the assumptions made elsewhere and is being
1196 tried as an experiment. */
1200 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1201 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1203 insn = scan_one_insn (insn, pass);
1204 if (insn == bb->end)
1209 /* Now for each register look at how desirable each class is
1210 and find which class is preferred. Store that in
1211 `prefclass'. Record in `altclass' the largest register
1212 class any of whose registers is better than memory. */
1215 reg_pref = reg_pref_buffer;
1219 dump_regclass (dump);
1220 fprintf (dump,"\n");
1222 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1224 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1225 enum reg_class best = ALL_REGS, alt = NO_REGS;
1226 /* This is an enum reg_class, but we call it an int
1227 to save lots of casts. */
1229 register struct costs *p = &costs[i];
1231 /* In non-optimizing compilation REG_N_REFS is not initialized
1233 if (optimize && !REG_N_REFS (i))
1236 for (class = (int) ALL_REGS - 1; class > 0; class--)
1238 /* Ignore classes that are too small for this operand or
1239 invalid for a operand that was auto-incremented. */
1240 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1241 #ifdef FORBIDDEN_INC_DEC_CLASSES
1242 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1244 #ifdef CLASS_CANNOT_CHANGE_MODE
1245 || (REGNO_REG_SET_P (reg_changes_mode, i)
1246 && ! class_can_change_mode [class])
1250 else if (p->cost[class] < best_cost)
1252 best_cost = p->cost[class];
1253 best = (enum reg_class) class;
1255 else if (p->cost[class] == best_cost)
1256 best = reg_class_subunion[(int)best][class];
1259 /* Record the alternate register class; i.e., a class for which
1260 every register in it is better than using memory. If adding a
1261 class would make a smaller class (i.e., no union of just those
1262 classes exists), skip that class. The major unions of classes
1263 should be provided as a register class. Don't do this if we
1264 will be doing it again later. */
1266 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1267 for (class = 0; class < N_REG_CLASSES; class++)
1268 if (p->cost[class] < p->mem_cost
1269 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1270 > reg_class_size[(int) alt])
1271 #ifdef FORBIDDEN_INC_DEC_CLASSES
1272 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1274 #ifdef CLASS_CANNOT_CHANGE_MODE
1275 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1276 && ! class_can_change_mode [class])
1279 alt = reg_class_subunion[(int) alt][class];
1281 /* If we don't add any classes, nothing to try. */
1286 && (reg_pref[i].prefclass != (int) best
1287 || reg_pref[i].altclass != (int) alt))
1289 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1290 fprintf (dump, " Register %i", i);
1291 if (alt == ALL_REGS || best == ALL_REGS)
1292 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1293 else if (alt == NO_REGS)
1294 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1296 fprintf (dump, " pref %s, else %s\n",
1297 reg_class_names[(int) best],
1298 reg_class_names[(int) alt]);
1301 /* We cast to (int) because (char) hits bugs in some compilers. */
1302 reg_pref[i].prefclass = (int) best;
1303 reg_pref[i].altclass = (int) alt;
1307 #ifdef FORBIDDEN_INC_DEC_CLASSES
1310 #ifdef CLASS_CANNOT_CHANGE_MODE
1311 BITMAP_XFREE (reg_changes_mode);
1316 /* Record the cost of using memory or registers of various classes for
1317 the operands in INSN.
1319 N_ALTS is the number of alternatives.
1321 N_OPS is the number of operands.
1323 OPS is an array of the operands.
1325 MODES are the modes of the operands, in case any are VOIDmode.
1327 CONSTRAINTS are the constraints to use for the operands. This array
1328 is modified by this procedure.
1330 This procedure works alternative by alternative. For each alternative
1331 we assume that we will be able to allocate all pseudos to their ideal
1332 register class and calculate the cost of using that alternative. Then
1333 we compute for each operand that is a pseudo-register, the cost of
1334 having the pseudo allocated to each register class and using it in that
1335 alternative. To this cost is added the cost of the alternative.
1337 The cost of each class for this insn is its lowest cost among all the
1341 record_reg_classes (n_alts, n_ops, ops, modes,
1342 constraints, insn, op_costs, reg_pref)
1346 enum machine_mode *modes;
1347 const char **constraints;
1349 struct costs *op_costs;
1350 struct reg_pref *reg_pref;
1356 /* Process each alternative, each time minimizing an operand's cost with
1357 the cost for each operand in that alternative. */
1359 for (alt = 0; alt < n_alts; alt++)
1361 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1364 enum reg_class classes[MAX_RECOG_OPERANDS];
1365 int allows_mem[MAX_RECOG_OPERANDS];
1368 for (i = 0; i < n_ops; i++)
1370 const char *p = constraints[i];
1372 enum machine_mode mode = modes[i];
1373 int allows_addr = 0;
1377 /* Initially show we know nothing about the register class. */
1378 classes[i] = NO_REGS;
1381 /* If this operand has no constraints at all, we can conclude
1382 nothing about it since anything is valid. */
1386 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1387 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1392 /* If this alternative is only relevant when this operand
1393 matches a previous operand, we do different things depending
1394 on whether this operand is a pseudo-reg or not. We must process
1395 any modifiers for the operand before we can make this test. */
1397 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1400 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1402 /* Copy class and whether memory is allowed from the matching
1403 alternative. Then perform any needed cost computations
1404 and/or adjustments. */
1406 classes[i] = classes[j];
1407 allows_mem[i] = allows_mem[j];
1409 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1411 /* If this matches the other operand, we have no added
1413 if (rtx_equal_p (ops[j], op))
1416 /* If we can put the other operand into a register, add to
1417 the cost of this alternative the cost to copy this
1418 operand to the register used for the other operand. */
1420 else if (classes[j] != NO_REGS)
1421 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1423 else if (GET_CODE (ops[j]) != REG
1424 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1426 /* This op is a pseudo but the one it matches is not. */
1428 /* If we can't put the other operand into a register, this
1429 alternative can't be used. */
1431 if (classes[j] == NO_REGS)
1434 /* Otherwise, add to the cost of this alternative the cost
1435 to copy the other operand to the register used for this
1439 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1443 /* The costs of this operand are not the same as the other
1444 operand since move costs are not symmetric. Moreover,
1445 if we cannot tie them, this alternative needs to do a
1446 copy, which is one instruction. */
1448 struct costs *pp = &this_op_costs[i];
1450 for (class = 0; class < N_REG_CLASSES; class++)
1452 = ((recog_data.operand_type[i] != OP_OUT
1453 ? may_move_in_cost[mode][class][(int) classes[i]]
1455 + (recog_data.operand_type[i] != OP_IN
1456 ? may_move_out_cost[mode][(int) classes[i]][class]
1459 /* If the alternative actually allows memory, make things
1460 a bit cheaper since we won't need an extra insn to
1464 = ((recog_data.operand_type[i] != OP_IN
1465 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1467 + (recog_data.operand_type[i] != OP_OUT
1468 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1469 : 0) - allows_mem[i]);
1471 /* If we have assigned a class to this register in our
1472 first pass, add a cost to this alternative corresponding
1473 to what we would add if this register were not in the
1474 appropriate class. */
1478 += (may_move_in_cost[mode]
1479 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1480 [(int) classes[i]]);
1482 if (REGNO (ops[i]) != REGNO (ops[j])
1483 && ! find_reg_note (insn, REG_DEAD, op))
1486 /* This is in place of ordinary cost computation
1487 for this operand, so skip to the end of the
1488 alternative (should be just one character). */
1489 while (*p && *p++ != ',')
1497 /* Scan all the constraint letters. See if the operand matches
1498 any of the constraints. Collect the valid register classes
1499 and see if this operand accepts memory. */
1501 while (*p && (c = *p++) != ',')
1505 /* Ignore the next letter for this pass. */
1511 case '!': case '#': case '&':
1512 case '0': case '1': case '2': case '3': case '4':
1513 case '5': case '6': case '7': case '8': case '9':
1518 win = address_operand (op, GET_MODE (op));
1519 /* We know this operand is an address, so we want it to be
1520 allocated to a register that can be the base of an
1521 address, ie BASE_REG_CLASS. */
1523 = reg_class_subunion[(int) classes[i]]
1524 [(int) BASE_REG_CLASS];
1527 case 'm': case 'o': case 'V':
1528 /* It doesn't seem worth distinguishing between offsettable
1529 and non-offsettable addresses here. */
1531 if (GET_CODE (op) == MEM)
1536 if (GET_CODE (op) == MEM
1537 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1538 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1543 if (GET_CODE (op) == MEM
1544 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1545 || GET_CODE (XEXP (op, 0)) == POST_INC))
1550 #ifndef REAL_ARITHMETIC
1551 /* Match any floating double constant, but only if
1552 we can examine the bits of it reliably. */
1553 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1554 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1555 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1558 if (GET_CODE (op) == CONST_DOUBLE)
1563 if (GET_CODE (op) == CONST_DOUBLE)
1569 if (GET_CODE (op) == CONST_DOUBLE
1570 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1575 if (GET_CODE (op) == CONST_INT
1576 || (GET_CODE (op) == CONST_DOUBLE
1577 && GET_MODE (op) == VOIDmode))
1581 #ifdef LEGITIMATE_PIC_OPERAND_P
1582 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1589 if (GET_CODE (op) == CONST_INT
1590 || (GET_CODE (op) == CONST_DOUBLE
1591 && GET_MODE (op) == VOIDmode))
1603 if (GET_CODE (op) == CONST_INT
1604 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1613 if (GET_CODE (op) == MEM
1615 #ifdef LEGITIMATE_PIC_OPERAND_P
1616 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1623 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1627 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1629 = reg_class_subunion[(int) classes[i]]
1630 [(int) REG_CLASS_FROM_LETTER (c)];
1631 #ifdef EXTRA_CONSTRAINT
1632 else if (EXTRA_CONSTRAINT (op, c))
1640 /* How we account for this operand now depends on whether it is a
1641 pseudo register or not. If it is, we first check if any
1642 register classes are valid. If not, we ignore this alternative,
1643 since we want to assume that all pseudos get allocated for
1644 register preferencing. If some register class is valid, compute
1645 the costs of moving the pseudo into that class. */
1647 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1649 if (classes[i] == NO_REGS)
1651 /* We must always fail if the operand is a REG, but
1652 we did not find a suitable class.
1654 Otherwise we may perform an uninitialized read
1655 from this_op_costs after the `continue' statement
1661 struct costs *pp = &this_op_costs[i];
1663 for (class = 0; class < N_REG_CLASSES; class++)
1665 = ((recog_data.operand_type[i] != OP_OUT
1666 ? may_move_in_cost[mode][class][(int) classes[i]]
1668 + (recog_data.operand_type[i] != OP_IN
1669 ? may_move_out_cost[mode][(int) classes[i]][class]
1672 /* If the alternative actually allows memory, make things
1673 a bit cheaper since we won't need an extra insn to
1677 = ((recog_data.operand_type[i] != OP_IN
1678 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1680 + (recog_data.operand_type[i] != OP_OUT
1681 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1682 : 0) - allows_mem[i]);
1684 /* If we have assigned a class to this register in our
1685 first pass, add a cost to this alternative corresponding
1686 to what we would add if this register were not in the
1687 appropriate class. */
1691 += (may_move_in_cost[mode]
1692 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1693 [(int) classes[i]]);
1697 /* Otherwise, if this alternative wins, either because we
1698 have already determined that or if we have a hard register of
1699 the proper class, there is no cost for this alternative. */
1702 || (GET_CODE (op) == REG
1703 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1706 /* If registers are valid, the cost of this alternative includes
1707 copying the object to and/or from a register. */
1709 else if (classes[i] != NO_REGS)
1711 if (recog_data.operand_type[i] != OP_OUT)
1712 alt_cost += copy_cost (op, mode, classes[i], 1);
1714 if (recog_data.operand_type[i] != OP_IN)
1715 alt_cost += copy_cost (op, mode, classes[i], 0);
1718 /* The only other way this alternative can be used is if this is a
1719 constant that could be placed into memory. */
1721 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1722 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1730 /* Finally, update the costs with the information we've calculated
1731 about this alternative. */
1733 for (i = 0; i < n_ops; i++)
1734 if (GET_CODE (ops[i]) == REG
1735 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1737 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1738 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1740 pp->mem_cost = MIN (pp->mem_cost,
1741 (qq->mem_cost + alt_cost) * scale);
1743 for (class = 0; class < N_REG_CLASSES; class++)
1744 pp->cost[class] = MIN (pp->cost[class],
1745 (qq->cost[class] + alt_cost) * scale);
1749 /* If this insn is a single set copying operand 1 to operand 0
1750 and one operand is a pseudo with the other a hard reg or a pseudo
1751 that prefers a register that is in its own register class then
1752 we may want to adjust the cost of that register class to -1.
1754 Avoid the adjustment if the source does not die to avoid stressing of
1755 register allocator by preferrencing two coliding registers into single
1758 Also avoid the adjustment if a copy between registers of the class
1759 is expensive (ten times the cost of a default copy is considered
1760 arbitrarily expensive). This avoids losing when the preferred class
1761 is very expensive as the source of a copy instruction. */
1763 if ((set = single_set (insn)) != 0
1764 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1765 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1766 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1767 for (i = 0; i <= 1; i++)
1768 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1770 unsigned int regno = REGNO (ops[!i]);
1771 enum machine_mode mode = GET_MODE (ops[!i]);
1775 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1777 enum reg_class pref = reg_pref[regno].prefclass;
1779 if ((reg_class_size[(unsigned char) pref]
1780 == CLASS_MAX_NREGS (pref, mode))
1781 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1782 op_costs[i].cost[(unsigned char) pref] = -1;
1784 else if (regno < FIRST_PSEUDO_REGISTER)
1785 for (class = 0; class < N_REG_CLASSES; class++)
1786 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1787 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1789 if (reg_class_size[class] == 1)
1790 op_costs[i].cost[class] = -1;
1793 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1795 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1800 if (nr == HARD_REGNO_NREGS (regno,mode))
1801 op_costs[i].cost[class] = -1;
1807 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1808 TO_P is zero) a register of class CLASS in mode MODE.
1810 X must not be a pseudo. */
1813 copy_cost (x, mode, class, to_p)
1815 enum machine_mode mode ATTRIBUTE_UNUSED;
1816 enum reg_class class;
1817 int to_p ATTRIBUTE_UNUSED;
1819 #ifdef HAVE_SECONDARY_RELOADS
1820 enum reg_class secondary_class = NO_REGS;
1823 /* If X is a SCRATCH, there is actually nothing to move since we are
1824 assuming optimal allocation. */
1826 if (GET_CODE (x) == SCRATCH)
1829 /* Get the class we will actually use for a reload. */
1830 class = PREFERRED_RELOAD_CLASS (x, class);
1832 #ifdef HAVE_SECONDARY_RELOADS
1833 /* If we need a secondary reload (we assume here that we are using
1834 the secondary reload as an intermediate, not a scratch register), the
1835 cost is that to load the input into the intermediate register, then
1836 to copy them. We use a special value of TO_P to avoid recursion. */
1838 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1840 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1843 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1845 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1848 if (secondary_class != NO_REGS)
1849 return (move_cost[mode][(int) secondary_class][(int) class]
1850 + copy_cost (x, mode, secondary_class, 2));
1851 #endif /* HAVE_SECONDARY_RELOADS */
1853 /* For memory, use the memory move cost, for (hard) registers, use the
1854 cost to move between the register classes, and use 2 for everything
1855 else (constants). */
1857 if (GET_CODE (x) == MEM || class == NO_REGS)
1858 return MEMORY_MOVE_COST (mode, class, to_p);
1860 else if (GET_CODE (x) == REG)
1861 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1864 /* If this is a constant, we may eventually want to call rtx_cost here. */
1865 return COSTS_N_INSNS (1);
1868 /* Record the pseudo registers we must reload into hard registers
1869 in a subexpression of a memory address, X.
1871 CLASS is the class that the register needs to be in and is either
1872 BASE_REG_CLASS or INDEX_REG_CLASS.
1874 SCALE is twice the amount to multiply the cost by (it is twice so we
1875 can represent half-cost adjustments). */
1878 record_address_regs (x, class, scale)
1880 enum reg_class class;
1883 register enum rtx_code code = GET_CODE (x);
1896 /* When we have an address that is a sum,
1897 we must determine whether registers are "base" or "index" regs.
1898 If there is a sum of two registers, we must choose one to be
1899 the "base". Luckily, we can use the REG_POINTER to make a good
1900 choice most of the time. We only need to do this on machines
1901 that can have two registers in an address and where the base
1902 and index register classes are different.
1904 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1905 that seems bogus since it should only be set when we are sure
1906 the register is being used as a pointer. */
1909 rtx arg0 = XEXP (x, 0);
1910 rtx arg1 = XEXP (x, 1);
1911 register enum rtx_code code0 = GET_CODE (arg0);
1912 register enum rtx_code code1 = GET_CODE (arg1);
1914 /* Look inside subregs. */
1915 if (code0 == SUBREG)
1916 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1917 if (code1 == SUBREG)
1918 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1920 /* If this machine only allows one register per address, it must
1921 be in the first operand. */
1923 if (MAX_REGS_PER_ADDRESS == 1)
1924 record_address_regs (arg0, class, scale);
1926 /* If index and base registers are the same on this machine, just
1927 record registers in any non-constant operands. We assume here,
1928 as well as in the tests below, that all addresses are in
1931 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1933 record_address_regs (arg0, class, scale);
1934 if (! CONSTANT_P (arg1))
1935 record_address_regs (arg1, class, scale);
1938 /* If the second operand is a constant integer, it doesn't change
1939 what class the first operand must be. */
1941 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1942 record_address_regs (arg0, class, scale);
1944 /* If the second operand is a symbolic constant, the first operand
1945 must be an index register. */
1947 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1948 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1950 /* If both operands are registers but one is already a hard register
1951 of index or base class, give the other the class that the hard
1954 #ifdef REG_OK_FOR_BASE_P
1955 else if (code0 == REG && code1 == REG
1956 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1957 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1958 record_address_regs (arg1,
1959 REG_OK_FOR_BASE_P (arg0)
1960 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1962 else if (code0 == REG && code1 == REG
1963 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1964 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1965 record_address_regs (arg0,
1966 REG_OK_FOR_BASE_P (arg1)
1967 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1971 /* If one operand is known to be a pointer, it must be the base
1972 with the other operand the index. Likewise if the other operand
1975 else if ((code0 == REG && REG_POINTER (arg0))
1978 record_address_regs (arg0, BASE_REG_CLASS, scale);
1979 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1981 else if ((code1 == REG && REG_POINTER (arg1))
1984 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1985 record_address_regs (arg1, BASE_REG_CLASS, scale);
1988 /* Otherwise, count equal chances that each might be a base
1989 or index register. This case should be rare. */
1993 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1994 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1995 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1996 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2001 /* Double the importance of a pseudo register that is incremented
2002 or decremented, since it would take two extra insns
2003 if it ends up in the wrong place. */
2006 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
2007 if (REG_P (XEXP (XEXP (x, 1), 1)))
2008 record_address_regs (XEXP (XEXP (x, 1), 1),
2009 INDEX_REG_CLASS, 2 * scale);
2016 /* Double the importance of a pseudo register that is incremented
2017 or decremented, since it would take two extra insns
2018 if it ends up in the wrong place. If the operand is a pseudo,
2019 show it is being used in an INC_DEC context. */
2021 #ifdef FORBIDDEN_INC_DEC_CLASSES
2022 if (GET_CODE (XEXP (x, 0)) == REG
2023 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2024 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2027 record_address_regs (XEXP (x, 0), class, 2 * scale);
2032 register struct costs *pp = &costs[REGNO (x)];
2035 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2037 for (i = 0; i < N_REG_CLASSES; i++)
2038 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2044 register const char *fmt = GET_RTX_FORMAT (code);
2046 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2048 record_address_regs (XEXP (x, i), class, scale);
2053 #ifdef FORBIDDEN_INC_DEC_CLASSES
2055 /* Return 1 if REG is valid as an auto-increment memory reference
2056 to an object of MODE. */
2059 auto_inc_dec_reg_p (reg, mode)
2061 enum machine_mode mode;
2063 if (HAVE_POST_INCREMENT
2064 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2067 if (HAVE_POST_DECREMENT
2068 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2071 if (HAVE_PRE_INCREMENT
2072 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2075 if (HAVE_PRE_DECREMENT
2076 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2083 static short *renumber;
2084 static size_t regno_allocated;
2085 static unsigned int reg_n_max;
2087 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2088 reg_scan and flow_analysis that are indexed by the register number. If
2089 NEW_P is non zero, initialize all of the registers, otherwise only
2090 initialize the new registers allocated. The same table is kept from
2091 function to function, only reallocating it when we need more room. If
2092 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2095 allocate_reg_info (num_regs, new_p, renumber_p)
2101 size_t size_renumber;
2102 size_t min = (new_p) ? 0 : reg_n_max;
2103 struct reg_info_data *reg_data;
2105 if (num_regs > regno_allocated)
2107 size_t old_allocated = regno_allocated;
2109 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2110 size_renumber = regno_allocated * sizeof (short);
2114 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2115 renumber = (short *) xmalloc (size_renumber);
2116 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2117 * sizeof (struct reg_pref));
2122 VARRAY_GROW (reg_n_info, regno_allocated);
2124 if (new_p) /* if we're zapping everything, no need to realloc */
2126 free ((char *)renumber);
2127 free ((char *)reg_pref);
2128 renumber = (short *) xmalloc (size_renumber);
2129 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2130 * sizeof (struct reg_pref));
2135 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2136 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2138 * sizeof (struct reg_pref));
2142 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2143 + sizeof (struct reg_info_data) - sizeof (reg_info);
2144 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2145 reg_data->min_index = old_allocated;
2146 reg_data->max_index = regno_allocated - 1;
2147 reg_data->next = reg_info_head;
2148 reg_info_head = reg_data;
2151 reg_n_max = num_regs;
2154 /* Loop through each of the segments allocated for the actual
2155 reg_info pages, and set up the pointers, zero the pages, etc. */
2156 for (reg_data = reg_info_head;
2157 reg_data && reg_data->max_index >= min;
2158 reg_data = reg_data->next)
2160 size_t min_index = reg_data->min_index;
2161 size_t max_index = reg_data->max_index;
2162 size_t max = MIN (max_index, num_regs);
2163 size_t local_min = min - min_index;
2166 if (reg_data->min_index > num_regs)
2169 if (min < min_index)
2171 if (!reg_data->used_p) /* page just allocated with calloc */
2172 reg_data->used_p = 1; /* no need to zero */
2174 memset ((char *) ®_data->data[local_min], 0,
2175 sizeof (reg_info) * (max - min_index - local_min + 1));
2177 for (i = min_index+local_min; i <= max; i++)
2179 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2180 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2182 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2183 reg_pref_buffer[i].altclass = (char) NO_REGS;
2188 /* If {pref,alt}class have already been allocated, update the pointers to
2189 the newly realloced ones. */
2191 reg_pref = reg_pref_buffer;
2194 reg_renumber = renumber;
2196 /* Tell the regset code about the new number of registers */
2197 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2200 /* Free up the space allocated by allocate_reg_info. */
2206 struct reg_info_data *reg_data;
2207 struct reg_info_data *reg_next;
2209 VARRAY_FREE (reg_n_info);
2210 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2212 reg_next = reg_data->next;
2213 free ((char *)reg_data);
2216 free (reg_pref_buffer);
2217 reg_pref_buffer = (struct reg_pref *)0;
2218 reg_info_head = (struct reg_info_data *)0;
2219 renumber = (short *)0;
2221 regno_allocated = 0;
2225 /* This is the `regscan' pass of the compiler, run just before cse
2226 and again just before loop.
2228 It finds the first and last use of each pseudo-register
2229 and records them in the vectors regno_first_uid, regno_last_uid
2230 and counts the number of sets in the vector reg_n_sets.
2232 REPEAT is nonzero the second time this is called. */
2234 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2235 Always at least 3, since the combiner could put that many together
2236 and we want this to remain correct for all the remaining passes.
2237 This corresponds to the maximum number of times note_stores will call
2238 a function for any insn. */
2242 /* Used as a temporary to record the largest number of registers in
2243 PARALLEL in a SET_DEST. This is added to max_parallel. */
2245 static int max_set_parallel;
2248 reg_scan (f, nregs, repeat)
2251 int repeat ATTRIBUTE_UNUSED;
2255 allocate_reg_info (nregs, TRUE, FALSE);
2257 max_set_parallel = 0;
2259 for (insn = f; insn; insn = NEXT_INSN (insn))
2260 if (GET_CODE (insn) == INSN
2261 || GET_CODE (insn) == CALL_INSN
2262 || GET_CODE (insn) == JUMP_INSN)
2264 if (GET_CODE (PATTERN (insn)) == PARALLEL
2265 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2266 max_parallel = XVECLEN (PATTERN (insn), 0);
2267 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2269 if (REG_NOTES (insn))
2270 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2273 max_parallel += max_set_parallel;
2276 /* Update 'regscan' information by looking at the insns
2277 from FIRST to LAST. Some new REGs have been created,
2278 and any REG with number greater than OLD_MAX_REGNO is
2279 such a REG. We only update information for those. */
2282 reg_scan_update (first, last, old_max_regno)
2285 unsigned int old_max_regno;
2289 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2291 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2292 if (GET_CODE (insn) == INSN
2293 || GET_CODE (insn) == CALL_INSN
2294 || GET_CODE (insn) == JUMP_INSN)
2296 if (GET_CODE (PATTERN (insn)) == PARALLEL
2297 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2298 max_parallel = XVECLEN (PATTERN (insn), 0);
2299 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2301 if (REG_NOTES (insn))
2302 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2306 /* X is the expression to scan. INSN is the insn it appears in.
2307 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2308 We should only record information for REGs with numbers
2309 greater than or equal to MIN_REGNO. */
2312 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2316 unsigned int min_regno;
2318 register enum rtx_code code;
2322 code = GET_CODE (x);
2338 unsigned int regno = REGNO (x);
2340 if (regno >= min_regno)
2342 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2344 REGNO_LAST_UID (regno) = INSN_UID (insn);
2345 if (REGNO_FIRST_UID (regno) == 0)
2346 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2353 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2355 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2360 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2364 /* Count a set of the destination if it is a register. */
2365 for (dest = SET_DEST (x);
2366 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2367 || GET_CODE (dest) == ZERO_EXTEND;
2368 dest = XEXP (dest, 0))
2371 /* For a PARALLEL, record the number of things (less the usual one for a
2372 SET) that are set. */
2373 if (GET_CODE (dest) == PARALLEL)
2374 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2376 if (GET_CODE (dest) == REG
2377 && REGNO (dest) >= min_regno)
2378 REG_N_SETS (REGNO (dest))++;
2380 /* If this is setting a pseudo from another pseudo or the sum of a
2381 pseudo and a constant integer and the other pseudo is known to be
2382 a pointer, set the destination to be a pointer as well.
2384 Likewise if it is setting the destination from an address or from a
2385 value equivalent to an address or to the sum of an address and
2388 But don't do any of this if the pseudo corresponds to a user
2389 variable since it should have already been set as a pointer based
2392 if (GET_CODE (SET_DEST (x)) == REG
2393 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2394 && REGNO (SET_DEST (x)) >= min_regno
2395 /* If the destination pseudo is set more than once, then other
2396 sets might not be to a pointer value (consider access to a
2397 union in two threads of control in the presense of global
2398 optimizations). So only set REG_POINTER on the destination
2399 pseudo if this is the only set of that pseudo. */
2400 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2401 && ! REG_USERVAR_P (SET_DEST (x))
2402 && ! REG_POINTER (SET_DEST (x))
2403 && ((GET_CODE (SET_SRC (x)) == REG
2404 && REG_POINTER (SET_SRC (x)))
2405 || ((GET_CODE (SET_SRC (x)) == PLUS
2406 || GET_CODE (SET_SRC (x)) == LO_SUM)
2407 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2408 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2409 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2410 || GET_CODE (SET_SRC (x)) == CONST
2411 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2412 || GET_CODE (SET_SRC (x)) == LABEL_REF
2413 || (GET_CODE (SET_SRC (x)) == HIGH
2414 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2415 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2416 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2417 || ((GET_CODE (SET_SRC (x)) == PLUS
2418 || GET_CODE (SET_SRC (x)) == LO_SUM)
2419 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2420 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2421 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2422 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2423 && (GET_CODE (XEXP (note, 0)) == CONST
2424 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2425 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2426 REG_POINTER (SET_DEST (x)) = 1;
2428 /* ... fall through ... */
2432 register const char *fmt = GET_RTX_FORMAT (code);
2434 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2437 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2438 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2441 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2442 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2449 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2453 reg_class_subset_p (c1, c2)
2454 register enum reg_class c1;
2455 register enum reg_class c2;
2457 if (c1 == c2) return 1;
2462 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2463 reg_class_contents[(int)c2],
2468 /* Return nonzero if there is a register that is in both C1 and C2. */
2471 reg_classes_intersect_p (c1, c2)
2472 register enum reg_class c1;
2473 register enum reg_class c2;
2480 if (c1 == c2) return 1;
2482 if (c1 == ALL_REGS || c2 == ALL_REGS)
2485 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2486 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2488 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2495 /* Release any memory allocated by register sets. */
2498 regset_release_memory ()
2500 bitmap_release_memory ();