1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "insn-flags.h"
30 #include "insn-codes.h"
31 #include "hard-reg-set.h"
38 #include "basic-block.h"
41 #ifndef STACK_PUSH_CODE
42 #ifdef STACK_GROWS_DOWNWARD
43 #define STACK_PUSH_CODE PRE_DEC
45 #define STACK_PUSH_CODE PRE_INC
49 #ifndef STACK_POP_CODE
50 #ifdef STACK_GROWS_DOWNWARD
51 #define STACK_POP_CODE POST_INC
53 #define STACK_POP_CODE POST_DEC
57 static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
58 static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
59 static rtx *find_constant_term_loc PARAMS ((rtx *));
60 static int insn_invalid_p PARAMS ((rtx));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized (insn)
118 if (INSN_CODE (insn) < 0)
119 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
120 return INSN_CODE (insn);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x)
132 const char **constraints;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x));
140 constrain_operands (1);
141 return which_alternative >= 0;
144 noperands = asm_noperands (x);
150 operands = (rtx *) alloca (noperands * sizeof (rtx));
151 constraints = (const char **) alloca (noperands * sizeof (char *));
153 decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR);
155 for (i = 0; i < noperands; i++)
157 const char *c = constraints[i];
160 if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0')
161 c = constraints[c[0] - '0'];
163 if (! asm_operand_ok (operands[i], c))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t *changes;
181 static int changes_allocated;
183 static int num_changes = 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object, loc, new, in_group)
212 if (old == new || rtx_equal_p (old, new))
215 if (in_group == 0 && num_changes != 0)
220 /* Save the information describing this change. */
221 if (num_changes >= changes_allocated)
223 if (changes_allocated == 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated = MAX_RECOG_OPERANDS * 5;
228 changes_allocated *= 2;
231 (change_t*) xrealloc (changes,
232 sizeof (change_t) * changes_allocated);
235 changes[num_changes].object = object;
236 changes[num_changes].loc = loc;
237 changes[num_changes].old = old;
239 if (object && GET_CODE (object) != MEM)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes[num_changes].old_code = INSN_CODE (object);
244 INSN_CODE (object) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn)
265 int icode = recog_memoized (insn);
266 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
268 if (is_asm && ! check_asm_operands (PATTERN (insn)))
270 if (! is_asm && icode < 0)
273 /* After reload, verify that all constraints are satisfied. */
274 if (reload_completed)
278 if (! constrain_operands (1))
285 /* Apply a group of changes previously issued with `validate_change'.
286 Return 1 if all changes are valid, zero otherwise. */
289 apply_change_group ()
293 /* The changes have been applied and all INSN_CODEs have been reset to force
296 The changes are valid if we aren't given an object, or if we are
297 given a MEM and it still is a valid address, or if this is in insn
298 and it is recognized. In the latter case, if reload has completed,
299 we also require that the operands meet the constraints for
302 for (i = 0; i < num_changes; i++)
304 rtx object = changes[i].object;
309 if (GET_CODE (object) == MEM)
311 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
314 else if (insn_invalid_p (object))
316 rtx pat = PATTERN (object);
318 /* Perhaps we couldn't recognize the insn because there were
319 extra CLOBBERs at the end. If so, try to re-recognize
320 without the last CLOBBER (later iterations will cause each of
321 them to be eliminated, in turn). But don't do this if we
322 have an ASM_OPERAND. */
323 if (GET_CODE (pat) == PARALLEL
324 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
325 && asm_noperands (PATTERN (object)) < 0)
329 if (XVECLEN (pat, 0) == 2)
330 newpat = XVECEXP (pat, 0, 0);
336 = gen_rtx_PARALLEL (VOIDmode,
337 gen_rtvec (XVECLEN (pat, 0) - 1));
338 for (j = 0; j < XVECLEN (newpat, 0); j++)
339 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
342 /* Add a new change to this group to replace the pattern
343 with this new pattern. Then consider this change
344 as having succeeded. The change we added will
345 cause the entire call to fail if things remain invalid.
347 Note that this can lose if a later change than the one
348 we are processing specified &XVECEXP (PATTERN (object), 0, X)
349 but this shouldn't occur. */
351 validate_change (object, &PATTERN (object), newpat, 1);
353 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
354 /* If this insn is a CLOBBER or USE, it is always valid, but is
362 if (i == num_changes)
374 /* Return the number of changes so far in the current group. */
377 num_validated_changes ()
382 /* Retract the changes numbered NUM and up. */
390 /* Back out all the changes. Do this in the opposite order in which
392 for (i = num_changes - 1; i >= num; i--)
394 *changes[i].loc = changes[i].old;
395 if (changes[i].object && GET_CODE (changes[i].object) != MEM)
396 INSN_CODE (changes[i].object) = changes[i].old_code;
401 /* Replace every occurrence of FROM in X with TO. Mark each change with
402 validate_change passing OBJECT. */
405 validate_replace_rtx_1 (loc, from, to, object)
407 rtx from, to, object;
410 register const char *fmt;
411 register rtx x = *loc;
417 /* X matches FROM if it is the same rtx or they are both referring to the
418 same register in the same mode. Avoid calling rtx_equal_p unless the
419 operands look similar. */
422 || (GET_CODE (x) == REG && GET_CODE (from) == REG
423 && GET_MODE (x) == GET_MODE (from)
424 && REGNO (x) == REGNO (from))
425 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
426 && rtx_equal_p (x, from)))
428 validate_change (object, loc, to, 1);
432 /* For commutative or comparison operations, try replacing each argument
433 separately and seeing if we made any changes. If so, put a constant
435 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
437 int prev_changes = num_changes;
439 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
440 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
441 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
443 validate_change (object, loc,
444 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
445 : swap_condition (code),
446 GET_MODE (x), XEXP (x, 1),
454 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
455 done the substitution, otherwise we won't. */
460 /* If we have a PLUS whose second operand is now a CONST_INT, use
461 plus_constant to try to simplify it. */
462 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
463 validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
468 if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
470 validate_change (object, loc,
471 plus_constant (XEXP (x, 0), - INTVAL (to)),
479 /* In these cases, the operation to be performed depends on the mode
480 of the operand. If we are replacing the operand with a VOIDmode
481 constant, we lose the information. So try to simplify the operation
482 in that case. If it fails, substitute in something that we know
483 won't be recognized. */
484 if (GET_MODE (to) == VOIDmode
485 && (XEXP (x, 0) == from
486 || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG
487 && GET_MODE (XEXP (x, 0)) == GET_MODE (from)
488 && REGNO (XEXP (x, 0)) == REGNO (from))))
490 rtx new = simplify_unary_operation (code, GET_MODE (x), to,
493 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
495 validate_change (object, loc, new, 1);
501 /* If we have a SUBREG of a register that we are replacing and we are
502 replacing it with a MEM, make a new MEM and try replacing the
503 SUBREG with it. Don't do this if the MEM has a mode-dependent address
504 or if we would be widening it. */
506 if (SUBREG_REG (x) == from
507 && GET_CODE (from) == REG
508 && GET_CODE (to) == MEM
509 && ! mode_dependent_address_p (XEXP (to, 0))
510 && ! MEM_VOLATILE_P (to)
511 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
513 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
514 enum machine_mode mode = GET_MODE (x);
517 if (BYTES_BIG_ENDIAN)
518 offset += (MIN (UNITS_PER_WORD,
519 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
520 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
522 new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
523 MEM_COPY_ATTRIBUTES (new, to);
524 validate_change (object, loc, new, 1);
531 /* If we are replacing a register with memory, try to change the memory
532 to be the mode required for memory in extract operations (this isn't
533 likely to be an insertion operation; if it was, nothing bad will
534 happen, we might just fail in some cases). */
536 if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM
537 && GET_CODE (XEXP (x, 1)) == CONST_INT
538 && GET_CODE (XEXP (x, 2)) == CONST_INT
539 && ! mode_dependent_address_p (XEXP (to, 0))
540 && ! MEM_VOLATILE_P (to))
542 enum machine_mode wanted_mode = VOIDmode;
543 enum machine_mode is_mode = GET_MODE (to);
544 int pos = INTVAL (XEXP (x, 2));
547 if (code == ZERO_EXTRACT)
549 wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
550 if (wanted_mode == VOIDmode)
551 wanted_mode = word_mode;
555 if (code == SIGN_EXTRACT)
557 wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode;
558 if (wanted_mode == VOIDmode)
559 wanted_mode = word_mode;
563 /* If we have a narrower mode, we can do something. */
564 if (wanted_mode != VOIDmode
565 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
567 int offset = pos / BITS_PER_UNIT;
570 /* If the bytes and bits are counted differently, we
571 must adjust the offset. */
572 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
573 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
576 pos %= GET_MODE_BITSIZE (wanted_mode);
578 newmem = gen_rtx_MEM (wanted_mode,
579 plus_constant (XEXP (to, 0), offset));
580 MEM_COPY_ATTRIBUTES (newmem, to);
582 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
583 validate_change (object, &XEXP (x, 0), newmem, 1);
593 /* For commutative or comparison operations we've already performed
594 replacements. Don't try to perform them again. */
595 if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
597 fmt = GET_RTX_FORMAT (code);
598 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
601 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
602 else if (fmt[i] == 'E')
603 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
604 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
609 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
610 with TO. After all changes have been made, validate by seeing
611 if INSN is still valid. */
614 validate_replace_rtx_subexp (from, to, insn, loc)
615 rtx from, to, insn, *loc;
617 validate_replace_rtx_1 (loc, from, to, insn);
618 return apply_change_group ();
621 /* Try replacing every occurrence of FROM in INSN with TO. After all
622 changes have been made, validate by seeing if INSN is still valid. */
625 validate_replace_rtx (from, to, insn)
628 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
629 return apply_change_group ();
632 /* Try replacing every occurrence of FROM in INSN with TO. After all
633 changes have been made, validate by seeing if INSN is still valid. */
636 validate_replace_rtx_group (from, to, insn)
639 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
642 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
643 SET_DESTs. After all changes have been made, validate by seeing if
644 INSN is still valid. */
647 validate_replace_src (from, to, insn)
650 if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
651 || GET_CODE (PATTERN (insn)) != SET)
654 validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn);
655 if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
656 validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0),
658 return apply_change_group ();
662 /* Return 1 if the insn using CC0 set by INSN does not contain
663 any ordered tests applied to the condition codes.
664 EQ and NE tests do not count. */
667 next_insn_tests_no_inequality (insn)
670 register rtx next = next_cc0_user (insn);
672 /* If there is no next insn, we have to take the conservative choice. */
676 return ((GET_CODE (next) == JUMP_INSN
677 || GET_CODE (next) == INSN
678 || GET_CODE (next) == CALL_INSN)
679 && ! inequality_comparisons_p (PATTERN (next)));
682 #if 0 /* This is useless since the insn that sets the cc's
683 must be followed immediately by the use of them. */
684 /* Return 1 if the CC value set up by INSN is not used. */
687 next_insns_test_no_inequality (insn)
690 register rtx next = NEXT_INSN (insn);
692 for (; next != 0; next = NEXT_INSN (next))
694 if (GET_CODE (next) == CODE_LABEL
695 || GET_CODE (next) == BARRIER)
697 if (GET_CODE (next) == NOTE)
699 if (inequality_comparisons_p (PATTERN (next)))
701 if (sets_cc0_p (PATTERN (next)) == 1)
703 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
711 /* This is used by find_single_use to locate an rtx that contains exactly one
712 use of DEST, which is typically either a REG or CC0. It returns a
713 pointer to the innermost rtx expression containing DEST. Appearances of
714 DEST that are being used to totally replace it are not counted. */
717 find_single_use_1 (dest, loc)
722 enum rtx_code code = GET_CODE (x);
739 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
740 of a REG that occupies all of the REG, the insn uses DEST if
741 it is mentioned in the destination or the source. Otherwise, we
742 need just check the source. */
743 if (GET_CODE (SET_DEST (x)) != CC0
744 && GET_CODE (SET_DEST (x)) != PC
745 && GET_CODE (SET_DEST (x)) != REG
746 && ! (GET_CODE (SET_DEST (x)) == SUBREG
747 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
748 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
749 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
750 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
751 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
754 return find_single_use_1 (dest, &SET_SRC (x));
758 return find_single_use_1 (dest, &XEXP (x, 0));
764 /* If it wasn't one of the common cases above, check each expression and
765 vector of this code. Look for a unique usage of DEST. */
767 fmt = GET_RTX_FORMAT (code);
768 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
772 if (dest == XEXP (x, i)
773 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
774 && REGNO (dest) == REGNO (XEXP (x, i))))
777 this_result = find_single_use_1 (dest, &XEXP (x, i));
780 result = this_result;
781 else if (this_result)
782 /* Duplicate usage. */
785 else if (fmt[i] == 'E')
789 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
791 if (XVECEXP (x, i, j) == dest
792 || (GET_CODE (dest) == REG
793 && GET_CODE (XVECEXP (x, i, j)) == REG
794 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
797 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
800 result = this_result;
801 else if (this_result)
810 /* See if DEST, produced in INSN, is used only a single time in the
811 sequel. If so, return a pointer to the innermost rtx expression in which
814 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
816 This routine will return usually zero either before flow is called (because
817 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
818 note can't be trusted).
820 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
821 care about REG_DEAD notes or LOG_LINKS.
823 Otherwise, we find the single use by finding an insn that has a
824 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
825 only referenced once in that insn, we know that it must be the first
826 and last insn referencing DEST. */
829 find_single_use (dest, insn, ploc)
841 next = NEXT_INSN (insn);
843 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
846 result = find_single_use_1 (dest, &PATTERN (next));
853 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
856 for (next = next_nonnote_insn (insn);
857 next != 0 && GET_CODE (next) != CODE_LABEL;
858 next = next_nonnote_insn (next))
859 if (INSN_P (next) && dead_or_set_p (next, dest))
861 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
862 if (XEXP (link, 0) == insn)
867 result = find_single_use_1 (dest, &PATTERN (next));
877 /* Return 1 if OP is a valid general operand for machine mode MODE.
878 This is either a register reference, a memory reference,
879 or a constant. In the case of a memory reference, the address
880 is checked for general validity for the target machine.
882 Register and memory references must have mode MODE in order to be valid,
883 but some constants have no machine mode and are valid for any mode.
885 If MODE is VOIDmode, OP is checked for validity for whatever mode
888 The main use of this function is as a predicate in match_operand
889 expressions in the machine description.
891 For an explanation of this function's behavior for registers of
892 class NO_REGS, see the comment for `register_operand'. */
895 general_operand (op, mode)
897 enum machine_mode mode;
899 register enum rtx_code code = GET_CODE (op);
900 int mode_altering_drug = 0;
902 if (mode == VOIDmode)
903 mode = GET_MODE (op);
905 /* Don't accept CONST_INT or anything similar
906 if the caller wants something floating. */
907 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
908 && GET_MODE_CLASS (mode) != MODE_INT
909 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
913 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
915 #ifdef LEGITIMATE_PIC_OPERAND_P
916 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
918 && LEGITIMATE_CONSTANT_P (op));
920 /* Except for certain constants with VOIDmode, already checked for,
921 OP's mode must match MODE if MODE specifies a mode. */
923 if (GET_MODE (op) != mode)
928 #ifdef INSN_SCHEDULING
929 /* On machines that have insn scheduling, we want all memory
930 reference to be explicit, so outlaw paradoxical SUBREGs. */
931 if (GET_CODE (SUBREG_REG (op)) == MEM
932 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
936 op = SUBREG_REG (op);
937 code = GET_CODE (op);
939 /* No longer needed, since (SUBREG (MEM...))
940 will load the MEM into a reload reg in the MEM's own mode. */
941 mode_altering_drug = 1;
946 /* A register whose class is NO_REGS is not a general operand. */
947 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
948 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
952 register rtx y = XEXP (op, 0);
954 if (! volatile_ok && MEM_VOLATILE_P (op))
957 if (GET_CODE (y) == ADDRESSOF)
960 /* Use the mem's mode, since it will be reloaded thus. */
961 mode = GET_MODE (op);
962 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
965 /* Pretend this is an operand for now; we'll run force_operand
966 on its replacement in fixup_var_refs_1. */
967 if (code == ADDRESSOF)
973 if (mode_altering_drug)
974 return ! mode_dependent_address_p (XEXP (op, 0));
978 /* Return 1 if OP is a valid memory address for a memory reference
981 The main use of this function is as a predicate in match_operand
982 expressions in the machine description. */
985 address_operand (op, mode)
987 enum machine_mode mode;
989 return memory_address_p (mode, op);
992 /* Return 1 if OP is a register reference of mode MODE.
993 If MODE is VOIDmode, accept a register in any mode.
995 The main use of this function is as a predicate in match_operand
996 expressions in the machine description.
998 As a special exception, registers whose class is NO_REGS are
999 not accepted by `register_operand'. The reason for this change
1000 is to allow the representation of special architecture artifacts
1001 (such as a condition code register) without extending the rtl
1002 definitions. Since registers of class NO_REGS cannot be used
1003 as registers in any case where register classes are examined,
1004 it is most consistent to keep this function from accepting them. */
1007 register_operand (op, mode)
1009 enum machine_mode mode;
1011 if (GET_MODE (op) != mode && mode != VOIDmode)
1014 if (GET_CODE (op) == SUBREG)
1016 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1017 because it is guaranteed to be reloaded into one.
1018 Just make sure the MEM is valid in itself.
1019 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1020 but currently it does result from (SUBREG (REG)...) where the
1021 reg went on the stack.) */
1022 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1023 return general_operand (op, mode);
1025 #ifdef CLASS_CANNOT_CHANGE_MODE
1026 if (GET_CODE (SUBREG_REG (op)) == REG
1027 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
1028 && (TEST_HARD_REG_BIT
1029 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
1030 REGNO (SUBREG_REG (op))))
1031 && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
1032 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
1033 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
1037 op = SUBREG_REG (op);
1040 /* If we have an ADDRESSOF, consider it valid since it will be
1041 converted into something that will not be a MEM. */
1042 if (GET_CODE (op) == ADDRESSOF)
1045 /* We don't consider registers whose class is NO_REGS
1046 to be a register operand. */
1047 return (GET_CODE (op) == REG
1048 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1049 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1052 /* Return 1 for a register in Pmode; ignore the tested mode. */
1055 pmode_register_operand (op, mode)
1057 enum machine_mode mode ATTRIBUTE_UNUSED;
1059 return register_operand (op, Pmode);
1062 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1063 or a hard register. */
1066 scratch_operand (op, mode)
1068 enum machine_mode mode;
1070 if (GET_MODE (op) != mode && mode != VOIDmode)
1073 return (GET_CODE (op) == SCRATCH
1074 || (GET_CODE (op) == REG
1075 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1078 /* Return 1 if OP is a valid immediate operand for mode MODE.
1080 The main use of this function is as a predicate in match_operand
1081 expressions in the machine description. */
1084 immediate_operand (op, mode)
1086 enum machine_mode mode;
1088 /* Don't accept CONST_INT or anything similar
1089 if the caller wants something floating. */
1090 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1091 && GET_MODE_CLASS (mode) != MODE_INT
1092 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1095 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1096 result in 0/1. It seems a safe assumption that this is
1097 in range for everyone. */
1098 if (GET_CODE (op) == CONSTANT_P_RTX)
1101 return (CONSTANT_P (op)
1102 && (GET_MODE (op) == mode || mode == VOIDmode
1103 || GET_MODE (op) == VOIDmode)
1104 #ifdef LEGITIMATE_PIC_OPERAND_P
1105 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1107 && LEGITIMATE_CONSTANT_P (op));
1110 /* Returns 1 if OP is an operand that is a CONST_INT. */
1113 const_int_operand (op, mode)
1115 enum machine_mode mode ATTRIBUTE_UNUSED;
1117 return GET_CODE (op) == CONST_INT;
1120 /* Returns 1 if OP is an operand that is a constant integer or constant
1121 floating-point number. */
1124 const_double_operand (op, mode)
1126 enum machine_mode mode;
1128 /* Don't accept CONST_INT or anything similar
1129 if the caller wants something floating. */
1130 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1131 && GET_MODE_CLASS (mode) != MODE_INT
1132 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1135 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
1136 && (mode == VOIDmode || GET_MODE (op) == mode
1137 || GET_MODE (op) == VOIDmode));
1140 /* Return 1 if OP is a general operand that is not an immediate operand. */
1143 nonimmediate_operand (op, mode)
1145 enum machine_mode mode;
1147 return (general_operand (op, mode) && ! CONSTANT_P (op));
1150 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1153 nonmemory_operand (op, mode)
1155 enum machine_mode mode;
1157 if (CONSTANT_P (op))
1159 /* Don't accept CONST_INT or anything similar
1160 if the caller wants something floating. */
1161 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1162 && GET_MODE_CLASS (mode) != MODE_INT
1163 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1166 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1167 || mode == VOIDmode)
1168 #ifdef LEGITIMATE_PIC_OPERAND_P
1169 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1171 && LEGITIMATE_CONSTANT_P (op));
1174 if (GET_MODE (op) != mode && mode != VOIDmode)
1177 if (GET_CODE (op) == SUBREG)
1179 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1180 because it is guaranteed to be reloaded into one.
1181 Just make sure the MEM is valid in itself.
1182 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1183 but currently it does result from (SUBREG (REG)...) where the
1184 reg went on the stack.) */
1185 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1186 return general_operand (op, mode);
1187 op = SUBREG_REG (op);
1190 /* We don't consider registers whose class is NO_REGS
1191 to be a register operand. */
1192 return (GET_CODE (op) == REG
1193 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1194 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1197 /* Return 1 if OP is a valid operand that stands for pushing a
1198 value of mode MODE onto the stack.
1200 The main use of this function is as a predicate in match_operand
1201 expressions in the machine description. */
1204 push_operand (op, mode)
1206 enum machine_mode mode;
1208 if (GET_CODE (op) != MEM)
1211 if (mode != VOIDmode && GET_MODE (op) != mode)
1216 if (GET_CODE (op) != STACK_PUSH_CODE)
1219 return XEXP (op, 0) == stack_pointer_rtx;
1222 /* Return 1 if OP is a valid operand that stands for popping a
1223 value of mode MODE off the stack.
1225 The main use of this function is as a predicate in match_operand
1226 expressions in the machine description. */
1229 pop_operand (op, mode)
1231 enum machine_mode mode;
1233 if (GET_CODE (op) != MEM)
1236 if (mode != VOIDmode && GET_MODE (op) != mode)
1241 if (GET_CODE (op) != STACK_POP_CODE)
1244 return XEXP (op, 0) == stack_pointer_rtx;
1247 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1250 memory_address_p (mode, addr)
1251 enum machine_mode mode ATTRIBUTE_UNUSED;
1254 if (GET_CODE (addr) == ADDRESSOF)
1257 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1264 /* Return 1 if OP is a valid memory reference with mode MODE,
1265 including a valid address.
1267 The main use of this function is as a predicate in match_operand
1268 expressions in the machine description. */
1271 memory_operand (op, mode)
1273 enum machine_mode mode;
1277 if (! reload_completed)
1278 /* Note that no SUBREG is a memory operand before end of reload pass,
1279 because (SUBREG (MEM...)) forces reloading into a register. */
1280 return GET_CODE (op) == MEM && general_operand (op, mode);
1282 if (mode != VOIDmode && GET_MODE (op) != mode)
1286 if (GET_CODE (inner) == SUBREG)
1287 inner = SUBREG_REG (inner);
1289 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1292 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1293 that is, a memory reference whose address is a general_operand. */
1296 indirect_operand (op, mode)
1298 enum machine_mode mode;
1300 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1301 if (! reload_completed
1302 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1304 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1305 rtx inner = SUBREG_REG (op);
1307 if (BYTES_BIG_ENDIAN)
1308 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1309 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1311 if (mode != VOIDmode && GET_MODE (op) != mode)
1314 /* The only way that we can have a general_operand as the resulting
1315 address is if OFFSET is zero and the address already is an operand
1316 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1319 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1320 || (GET_CODE (XEXP (inner, 0)) == PLUS
1321 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1322 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1323 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1326 return (GET_CODE (op) == MEM
1327 && memory_operand (op, mode)
1328 && general_operand (XEXP (op, 0), Pmode));
1331 /* Return 1 if this is a comparison operator. This allows the use of
1332 MATCH_OPERATOR to recognize all the branch insns. */
1335 comparison_operator (op, mode)
1337 enum machine_mode mode;
1339 return ((mode == VOIDmode || GET_MODE (op) == mode)
1340 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1343 /* If BODY is an insn body that uses ASM_OPERANDS,
1344 return the number of operands (both input and output) in the insn.
1345 Otherwise return -1. */
1348 asm_noperands (body)
1351 if (GET_CODE (body) == ASM_OPERANDS)
1352 /* No output operands: return number of input operands. */
1353 return ASM_OPERANDS_INPUT_LENGTH (body);
1354 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1355 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1356 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1357 else if (GET_CODE (body) == PARALLEL
1358 && GET_CODE (XVECEXP (body, 0, 0)) == SET
1359 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1361 /* Multiple output operands, or 1 output plus some clobbers:
1362 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1366 /* Count backwards through CLOBBERs to determine number of SETs. */
1367 for (i = XVECLEN (body, 0); i > 0; i--)
1369 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1371 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1375 /* N_SETS is now number of output operands. */
1378 /* Verify that all the SETs we have
1379 came from a single original asm_operands insn
1380 (so that invalid combinations are blocked). */
1381 for (i = 0; i < n_sets; i++)
1383 rtx elt = XVECEXP (body, 0, i);
1384 if (GET_CODE (elt) != SET)
1386 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1388 /* If these ASM_OPERANDS rtx's came from different original insns
1389 then they aren't allowed together. */
1390 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1391 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1394 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1397 else if (GET_CODE (body) == PARALLEL
1398 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1400 /* 0 outputs, but some clobbers:
1401 body is [(asm_operands ...) (clobber (reg ...))...]. */
1404 /* Make sure all the other parallel things really are clobbers. */
1405 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1406 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1409 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1415 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1416 copy its operands (both input and output) into the vector OPERANDS,
1417 the locations of the operands within the insn into the vector OPERAND_LOCS,
1418 and the constraints for the operands into CONSTRAINTS.
1419 Write the modes of the operands into MODES.
1420 Return the assembler-template.
1422 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1423 we don't store that info. */
1426 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1430 const char **constraints;
1431 enum machine_mode *modes;
1435 const char *template = 0;
1437 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1439 rtx asmop = SET_SRC (body);
1440 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1442 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1444 for (i = 1; i < noperands; i++)
1447 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1449 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1451 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1453 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1456 /* The output is in the SET.
1457 Its constraint is in the ASM_OPERANDS itself. */
1459 operands[0] = SET_DEST (body);
1461 operand_locs[0] = &SET_DEST (body);
1463 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1465 modes[0] = GET_MODE (SET_DEST (body));
1466 template = ASM_OPERANDS_TEMPLATE (asmop);
1468 else if (GET_CODE (body) == ASM_OPERANDS)
1471 /* No output operands: BODY is (asm_operands ....). */
1473 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1475 /* The input operands are found in the 1st element vector. */
1476 /* Constraints for inputs are in the 2nd element vector. */
1477 for (i = 0; i < noperands; i++)
1480 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1482 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1484 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1486 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1488 template = ASM_OPERANDS_TEMPLATE (asmop);
1490 else if (GET_CODE (body) == PARALLEL
1491 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1493 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1494 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1495 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1496 int nout = 0; /* Does not include CLOBBERs. */
1498 /* At least one output, plus some CLOBBERs. */
1500 /* The outputs are in the SETs.
1501 Their constraints are in the ASM_OPERANDS itself. */
1502 for (i = 0; i < nparallel; i++)
1504 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1505 break; /* Past last SET */
1508 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1510 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1512 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1514 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1518 for (i = 0; i < nin; i++)
1521 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1523 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1525 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1527 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1530 template = ASM_OPERANDS_TEMPLATE (asmop);
1532 else if (GET_CODE (body) == PARALLEL
1533 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1535 /* No outputs, but some CLOBBERs. */
1537 rtx asmop = XVECEXP (body, 0, 0);
1538 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1540 for (i = 0; i < nin; i++)
1543 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1545 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1547 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1549 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1552 template = ASM_OPERANDS_TEMPLATE (asmop);
1558 /* Check if an asm_operand matches it's constraints.
1559 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1562 asm_operand_ok (op, constraint)
1564 const char *constraint;
1568 /* Use constrain_operands after reload. */
1569 if (reload_completed)
1574 char c = *constraint++;
1588 case '0': case '1': case '2': case '3': case '4':
1589 case '5': case '6': case '7': case '8': case '9':
1590 /* For best results, our caller should have given us the
1591 proper matching constraint, but we can't actually fail
1592 the check if they didn't. Indicate that results are
1598 if (address_operand (op, VOIDmode))
1603 case 'V': /* non-offsettable */
1604 if (memory_operand (op, VOIDmode))
1608 case 'o': /* offsettable */
1609 if (offsettable_nonstrict_memref_p (op))
1614 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1615 excepting those that expand_call created. Further, on some
1616 machines which do not have generalized auto inc/dec, an inc/dec
1617 is not a memory_operand.
1619 Match any memory and hope things are resolved after reload. */
1621 if (GET_CODE (op) == MEM
1623 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1624 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1629 if (GET_CODE (op) == MEM
1631 || GET_CODE (XEXP (op, 0)) == PRE_INC
1632 || GET_CODE (XEXP (op, 0)) == POST_INC))
1637 #ifndef REAL_ARITHMETIC
1638 /* Match any floating double constant, but only if
1639 we can examine the bits of it reliably. */
1640 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1641 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1642 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1648 if (GET_CODE (op) == CONST_DOUBLE)
1653 if (GET_CODE (op) == CONST_DOUBLE
1654 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
1658 if (GET_CODE (op) == CONST_DOUBLE
1659 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
1664 if (GET_CODE (op) == CONST_INT
1665 || (GET_CODE (op) == CONST_DOUBLE
1666 && GET_MODE (op) == VOIDmode))
1672 #ifdef LEGITIMATE_PIC_OPERAND_P
1673 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1680 if (GET_CODE (op) == CONST_INT
1681 || (GET_CODE (op) == CONST_DOUBLE
1682 && GET_MODE (op) == VOIDmode))
1687 if (GET_CODE (op) == CONST_INT
1688 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
1692 if (GET_CODE (op) == CONST_INT
1693 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
1697 if (GET_CODE (op) == CONST_INT
1698 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
1702 if (GET_CODE (op) == CONST_INT
1703 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
1707 if (GET_CODE (op) == CONST_INT
1708 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
1712 if (GET_CODE (op) == CONST_INT
1713 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
1717 if (GET_CODE (op) == CONST_INT
1718 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
1722 if (GET_CODE (op) == CONST_INT
1723 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
1731 if (general_operand (op, VOIDmode))
1736 /* For all other letters, we first check for a register class,
1737 otherwise it is an EXTRA_CONSTRAINT. */
1738 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1741 if (GET_MODE (op) == BLKmode)
1743 if (register_operand (op, VOIDmode))
1746 #ifdef EXTRA_CONSTRAINT
1747 if (EXTRA_CONSTRAINT (op, c))
1757 /* Given an rtx *P, if it is a sum containing an integer constant term,
1758 return the location (type rtx *) of the pointer to that constant term.
1759 Otherwise, return a null pointer. */
1762 find_constant_term_loc (p)
1766 register enum rtx_code code = GET_CODE (*p);
1768 /* If *P IS such a constant term, P is its location. */
1770 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1774 /* Otherwise, if not a sum, it has no constant term. */
1776 if (GET_CODE (*p) != PLUS)
1779 /* If one of the summands is constant, return its location. */
1781 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1782 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1785 /* Otherwise, check each summand for containing a constant term. */
1787 if (XEXP (*p, 0) != 0)
1789 tem = find_constant_term_loc (&XEXP (*p, 0));
1794 if (XEXP (*p, 1) != 0)
1796 tem = find_constant_term_loc (&XEXP (*p, 1));
1804 /* Return 1 if OP is a memory reference
1805 whose address contains no side effects
1806 and remains valid after the addition
1807 of a positive integer less than the
1808 size of the object being referenced.
1810 We assume that the original address is valid and do not check it.
1812 This uses strict_memory_address_p as a subroutine, so
1813 don't use it before reload. */
1816 offsettable_memref_p (op)
1819 return ((GET_CODE (op) == MEM)
1820 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1823 /* Similar, but don't require a strictly valid mem ref:
1824 consider pseudo-regs valid as index or base regs. */
1827 offsettable_nonstrict_memref_p (op)
1830 return ((GET_CODE (op) == MEM)
1831 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1834 /* Return 1 if Y is a memory address which contains no side effects
1835 and would remain valid after the addition of a positive integer
1836 less than the size of that mode.
1838 We assume that the original address is valid and do not check it.
1839 We do check that it is valid for narrower modes.
1841 If STRICTP is nonzero, we require a strictly valid address,
1842 for the sake of use in reload.c. */
1845 offsettable_address_p (strictp, mode, y)
1847 enum machine_mode mode;
1850 register enum rtx_code ycode = GET_CODE (y);
1854 int (*addressp) PARAMS ((enum machine_mode, rtx)) =
1855 (strictp ? strict_memory_address_p : memory_address_p);
1856 unsigned int mode_sz = GET_MODE_SIZE (mode);
1858 if (CONSTANT_ADDRESS_P (y))
1861 /* Adjusting an offsettable address involves changing to a narrower mode.
1862 Make sure that's OK. */
1864 if (mode_dependent_address_p (y))
1867 /* ??? How much offset does an offsettable BLKmode reference need?
1868 Clearly that depends on the situation in which it's being used.
1869 However, the current situation in which we test 0xffffffff is
1870 less than ideal. Caveat user. */
1872 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1874 /* If the expression contains a constant term,
1875 see if it remains valid when max possible offset is added. */
1877 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1882 *y2 = plus_constant (*y2, mode_sz - 1);
1883 /* Use QImode because an odd displacement may be automatically invalid
1884 for any wider mode. But it should be valid for a single byte. */
1885 good = (*addressp) (QImode, y);
1887 /* In any case, restore old contents of memory. */
1892 if (GET_RTX_CLASS (ycode) == 'a')
1895 /* The offset added here is chosen as the maximum offset that
1896 any instruction could need to add when operating on something
1897 of the specified mode. We assume that if Y and Y+c are
1898 valid addresses then so is Y+d for all 0<d<c. */
1900 z = plus_constant_for_output (y, mode_sz - 1);
1902 /* Use QImode because an odd displacement may be automatically invalid
1903 for any wider mode. But it should be valid for a single byte. */
1904 return (*addressp) (QImode, z);
1907 /* Return 1 if ADDR is an address-expression whose effect depends
1908 on the mode of the memory reference it is used in.
1910 Autoincrement addressing is a typical example of mode-dependence
1911 because the amount of the increment depends on the mode. */
1914 mode_dependent_address_p (addr)
1915 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1917 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1919 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1920 win: ATTRIBUTE_UNUSED_LABEL
1924 /* Return 1 if OP is a general operand
1925 other than a memory ref with a mode dependent address. */
1928 mode_independent_operand (op, mode)
1929 enum machine_mode mode;
1934 if (! general_operand (op, mode))
1937 if (GET_CODE (op) != MEM)
1940 addr = XEXP (op, 0);
1941 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
1943 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1944 lose: ATTRIBUTE_UNUSED_LABEL
1948 /* Given an operand OP that is a valid memory reference which
1949 satisfies offsettable_memref_p, return a new memory reference whose
1950 address has been adjusted by OFFSET. OFFSET should be positive and
1951 less than the size of the object referenced. */
1954 adj_offsettable_operand (op, offset)
1958 register enum rtx_code code = GET_CODE (op);
1962 register rtx y = XEXP (op, 0);
1965 if (CONSTANT_ADDRESS_P (y))
1967 new = gen_rtx_MEM (GET_MODE (op),
1968 plus_constant_for_output (y, offset));
1969 MEM_COPY_ATTRIBUTES (new, op);
1973 if (GET_CODE (y) == PLUS)
1976 register rtx *const_loc;
1980 const_loc = find_constant_term_loc (&z);
1983 *const_loc = plus_constant_for_output (*const_loc, offset);
1988 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
1989 MEM_COPY_ATTRIBUTES (new, op);
1995 /* Analyze INSN and fill in recog_data. */
2004 rtx body = PATTERN (insn);
2006 recog_data.n_operands = 0;
2007 recog_data.n_alternatives = 0;
2008 recog_data.n_dups = 0;
2010 switch (GET_CODE (body))
2022 recog_data.n_operands = noperands = asm_noperands (body);
2025 /* This insn is an `asm' with operands. */
2027 /* expand_asm_operands makes sure there aren't too many operands. */
2028 if (noperands > MAX_RECOG_OPERANDS)
2031 /* Now get the operand values and constraints out of the insn. */
2032 decode_asm_operands (body, recog_data.operand,
2033 recog_data.operand_loc,
2034 recog_data.constraints,
2035 recog_data.operand_mode);
2038 const char *p = recog_data.constraints[0];
2039 recog_data.n_alternatives = 1;
2041 recog_data.n_alternatives += (*p++ == ',');
2049 /* Ordinary insn: recognize it, get the operands via insn_extract
2050 and get the constraints. */
2052 icode = recog_memoized (insn);
2054 fatal_insn_not_found (insn);
2056 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2057 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2058 recog_data.n_dups = insn_data[icode].n_dups;
2060 insn_extract (insn);
2062 for (i = 0; i < noperands; i++)
2064 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2065 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2066 /* VOIDmode match_operands gets mode from their real operand. */
2067 if (recog_data.operand_mode[i] == VOIDmode)
2068 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2071 for (i = 0; i < noperands; i++)
2072 recog_data.operand_type[i]
2073 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2074 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2077 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
2081 /* After calling extract_insn, you can use this function to extract some
2082 information from the constraint strings into a more usable form.
2083 The collected data is stored in recog_op_alt. */
2085 preprocess_constraints ()
2089 memset (recog_op_alt, 0, sizeof recog_op_alt);
2090 for (i = 0; i < recog_data.n_operands; i++)
2093 struct operand_alternative *op_alt;
2094 const char *p = recog_data.constraints[i];
2096 op_alt = recog_op_alt[i];
2098 for (j = 0; j < recog_data.n_alternatives; j++)
2100 op_alt[j].class = NO_REGS;
2101 op_alt[j].constraint = p;
2102 op_alt[j].matches = -1;
2103 op_alt[j].matched = -1;
2105 if (*p == '\0' || *p == ',')
2107 op_alt[j].anything_ok = 1;
2117 while (c != ',' && c != '\0');
2118 if (c == ',' || c == '\0')
2123 case '=': case '+': case '*': case '%':
2124 case 'E': case 'F': case 'G': case 'H':
2125 case 's': case 'i': case 'n':
2126 case 'I': case 'J': case 'K': case 'L':
2127 case 'M': case 'N': case 'O': case 'P':
2128 /* These don't say anything we care about. */
2132 op_alt[j].reject += 6;
2135 op_alt[j].reject += 600;
2138 op_alt[j].earlyclobber = 1;
2141 case '0': case '1': case '2': case '3': case '4':
2142 case '5': case '6': case '7': case '8': case '9':
2143 op_alt[j].matches = c - '0';
2144 recog_op_alt[op_alt[j].matches][j].matched = i;
2148 op_alt[j].memory_ok = 1;
2151 op_alt[j].decmem_ok = 1;
2154 op_alt[j].incmem_ok = 1;
2157 op_alt[j].nonoffmem_ok = 1;
2160 op_alt[j].offmem_ok = 1;
2163 op_alt[j].anything_ok = 1;
2167 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS];
2171 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
2175 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
2183 /* Check the operands of an insn against the insn's operand constraints
2184 and return 1 if they are valid.
2185 The information about the insn's operands, constraints, operand modes
2186 etc. is obtained from the global variables set up by extract_insn.
2188 WHICH_ALTERNATIVE is set to a number which indicates which
2189 alternative of constraints was matched: 0 for the first alternative,
2190 1 for the next, etc.
2192 In addition, when two operands are match
2193 and it happens that the output operand is (reg) while the
2194 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2195 make the output operand look like the input.
2196 This is because the output operand is the one the template will print.
2198 This is used in final, just before printing the assembler code and by
2199 the routines that determine an insn's attribute.
2201 If STRICT is a positive non-zero value, it means that we have been
2202 called after reload has been completed. In that case, we must
2203 do all checks strictly. If it is zero, it means that we have been called
2204 before reload has completed. In that case, we first try to see if we can
2205 find an alternative that matches strictly. If not, we try again, this
2206 time assuming that reload will fix up the insn. This provides a "best
2207 guess" for the alternative and is used to compute attributes of insns prior
2208 to reload. A negative value of STRICT is used for this internal call. */
2216 constrain_operands (strict)
2219 const char *constraints[MAX_RECOG_OPERANDS];
2220 int matching_operands[MAX_RECOG_OPERANDS];
2221 int earlyclobber[MAX_RECOG_OPERANDS];
2224 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2225 int funny_match_index;
2227 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2230 for (c = 0; c < recog_data.n_operands; c++)
2232 constraints[c] = recog_data.constraints[c];
2233 matching_operands[c] = -1;
2236 which_alternative = 0;
2238 while (which_alternative < recog_data.n_alternatives)
2242 funny_match_index = 0;
2244 for (opno = 0; opno < recog_data.n_operands; opno++)
2246 register rtx op = recog_data.operand[opno];
2247 enum machine_mode mode = GET_MODE (op);
2248 register const char *p = constraints[opno];
2253 earlyclobber[opno] = 0;
2255 /* A unary operator may be accepted by the predicate, but it
2256 is irrelevant for matching constraints. */
2257 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
2260 if (GET_CODE (op) == SUBREG)
2262 if (GET_CODE (SUBREG_REG (op)) == REG
2263 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2264 offset = SUBREG_WORD (op);
2265 op = SUBREG_REG (op);
2268 /* An empty constraint or empty alternative
2269 allows anything which matched the pattern. */
2270 if (*p == 0 || *p == ',')
2273 while (*p && (c = *p++) != ',')
2276 case '?': case '!': case '*': case '%':
2281 /* Ignore rest of this alternative as far as
2282 constraint checking is concerned. */
2283 while (*p && *p != ',')
2288 earlyclobber[opno] = 1;
2291 case '0': case '1': case '2': case '3': case '4':
2292 case '5': case '6': case '7': case '8': case '9':
2294 /* This operand must be the same as a previous one.
2295 This kind of constraint is used for instructions such
2296 as add when they take only two operands.
2298 Note that the lower-numbered operand is passed first.
2300 If we are not testing strictly, assume that this constraint
2301 will be satisfied. */
2306 rtx op1 = recog_data.operand[c - '0'];
2307 rtx op2 = recog_data.operand[opno];
2309 /* A unary operator may be accepted by the predicate,
2310 but it is irrelevant for matching constraints. */
2311 if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
2312 op1 = XEXP (op1, 0);
2313 if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
2314 op2 = XEXP (op2, 0);
2316 val = operands_match_p (op1, op2);
2319 matching_operands[opno] = c - '0';
2320 matching_operands[c - '0'] = opno;
2324 /* If output is *x and input is *--x,
2325 arrange later to change the output to *--x as well,
2326 since the output op is the one that will be printed. */
2327 if (val == 2 && strict > 0)
2329 funny_match[funny_match_index].this = opno;
2330 funny_match[funny_match_index++].other = c - '0';
2335 /* p is used for address_operands. When we are called by
2336 gen_reload, no one will have checked that the address is
2337 strictly valid, i.e., that all pseudos requiring hard regs
2338 have gotten them. */
2340 || (strict_memory_address_p (recog_data.operand_mode[opno],
2345 /* No need to check general_operand again;
2346 it was done in insn-recog.c. */
2348 /* Anything goes unless it is a REG and really has a hard reg
2349 but the hard reg is not in the class GENERAL_REGS. */
2351 || GENERAL_REGS == ALL_REGS
2352 || GET_CODE (op) != REG
2353 || (reload_in_progress
2354 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2355 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2360 /* This is used for a MATCH_SCRATCH in the cases when
2361 we don't actually need anything. So anything goes
2367 if (GET_CODE (op) == MEM
2368 /* Before reload, accept what reload can turn into mem. */
2369 || (strict < 0 && CONSTANT_P (op))
2370 /* During reload, accept a pseudo */
2371 || (reload_in_progress && GET_CODE (op) == REG
2372 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2377 if (GET_CODE (op) == MEM
2378 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2379 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2384 if (GET_CODE (op) == MEM
2385 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2386 || GET_CODE (XEXP (op, 0)) == POST_INC))
2391 #ifndef REAL_ARITHMETIC
2392 /* Match any CONST_DOUBLE, but only if
2393 we can examine the bits of it reliably. */
2394 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2395 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2396 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
2399 if (GET_CODE (op) == CONST_DOUBLE)
2404 if (GET_CODE (op) == CONST_DOUBLE)
2410 if (GET_CODE (op) == CONST_DOUBLE
2411 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
2416 if (GET_CODE (op) == CONST_INT
2417 || (GET_CODE (op) == CONST_DOUBLE
2418 && GET_MODE (op) == VOIDmode))
2421 if (CONSTANT_P (op))
2426 if (GET_CODE (op) == CONST_INT
2427 || (GET_CODE (op) == CONST_DOUBLE
2428 && GET_MODE (op) == VOIDmode))
2440 if (GET_CODE (op) == CONST_INT
2441 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
2446 if (GET_CODE (op) == MEM
2447 && ((strict > 0 && ! offsettable_memref_p (op))
2449 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
2450 || (reload_in_progress
2451 && !(GET_CODE (op) == REG
2452 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2457 if ((strict > 0 && offsettable_memref_p (op))
2458 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2459 /* Before reload, accept what reload can handle. */
2461 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
2462 /* During reload, accept a pseudo */
2463 || (reload_in_progress && GET_CODE (op) == REG
2464 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2470 enum reg_class class;
2472 class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c));
2473 if (class != NO_REGS)
2477 && GET_CODE (op) == REG
2478 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2479 || (strict == 0 && GET_CODE (op) == SCRATCH)
2480 || (GET_CODE (op) == REG
2481 && reg_fits_class_p (op, class, offset, mode)))
2484 #ifdef EXTRA_CONSTRAINT
2485 else if (EXTRA_CONSTRAINT (op, c))
2492 constraints[opno] = p;
2493 /* If this operand did not win somehow,
2494 this alternative loses. */
2498 /* This alternative won; the operands are ok.
2499 Change whichever operands this alternative says to change. */
2504 /* See if any earlyclobber operand conflicts with some other
2508 for (eopno = 0; eopno < recog_data.n_operands; eopno++)
2509 /* Ignore earlyclobber operands now in memory,
2510 because we would often report failure when we have
2511 two memory operands, one of which was formerly a REG. */
2512 if (earlyclobber[eopno]
2513 && GET_CODE (recog_data.operand[eopno]) == REG)
2514 for (opno = 0; opno < recog_data.n_operands; opno++)
2515 if ((GET_CODE (recog_data.operand[opno]) == MEM
2516 || recog_data.operand_type[opno] != OP_OUT)
2518 /* Ignore things like match_operator operands. */
2519 && *recog_data.constraints[opno] != 0
2520 && ! (matching_operands[opno] == eopno
2521 && operands_match_p (recog_data.operand[opno],
2522 recog_data.operand[eopno]))
2523 && ! safe_from_earlyclobber (recog_data.operand[opno],
2524 recog_data.operand[eopno]))
2529 while (--funny_match_index >= 0)
2531 recog_data.operand[funny_match[funny_match_index].other]
2532 = recog_data.operand[funny_match[funny_match_index].this];
2539 which_alternative++;
2542 /* If we are about to reject this, but we are not to test strictly,
2543 try a very loose test. Only return failure if it fails also. */
2545 return constrain_operands (-1);
2550 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2551 is a hard reg in class CLASS when its regno is offset by OFFSET
2552 and changed to mode MODE.
2553 If REG occupies multiple hard regs, all of them must be in CLASS. */
2556 reg_fits_class_p (operand, class, offset, mode)
2558 register enum reg_class class;
2560 enum machine_mode mode;
2562 register int regno = REGNO (operand);
2563 if (regno < FIRST_PSEUDO_REGISTER
2564 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2569 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2571 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2580 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2583 split_all_insns (upd_life)
2590 blocks = sbitmap_alloc (n_basic_blocks);
2591 sbitmap_zero (blocks);
2594 for (i = n_basic_blocks - 1; i >= 0; --i)
2596 basic_block bb = BASIC_BLOCK (i);
2599 for (insn = bb->head; insn ; insn = next)
2603 /* Can't use `next_real_insn' because that might go across
2604 CODE_LABELS and short-out basic blocks. */
2605 next = NEXT_INSN (insn);
2606 if (! INSN_P (insn))
2609 /* Don't split no-op move insns. These should silently
2610 disappear later in final. Splitting such insns would
2611 break the code that handles REG_NO_CONFLICT blocks. */
2613 else if ((set = single_set (insn)) != NULL
2614 && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
2616 /* Nops get in the way while scheduling, so delete them
2617 now if register allocation has already been done. It
2618 is too risky to try to do this before register
2619 allocation, and there are unlikely to be very many
2620 nops then anyways. */
2621 if (reload_completed)
2623 PUT_CODE (insn, NOTE);
2624 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2625 NOTE_SOURCE_FILE (insn) = 0;
2630 /* Split insns here to get max fine-grain parallelism. */
2631 rtx first = PREV_INSN (insn);
2632 rtx last = try_split (PATTERN (insn), insn, 1);
2636 SET_BIT (blocks, i);
2639 /* try_split returns the NOTE that INSN became. */
2640 first = NEXT_INSN (first);
2641 PUT_CODE (insn, NOTE);
2642 NOTE_SOURCE_FILE (insn) = 0;
2643 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2645 if (insn == bb->end)
2653 if (insn == bb->end)
2657 /* ??? When we're called from just after reload, the CFG is in bad
2658 shape, and we may have fallen off the end. This could be fixed
2659 by having reload not try to delete unreachable code. Otherwise
2660 assert we found the end insn. */
2661 if (insn == NULL && upd_life)
2665 if (changed && upd_life)
2667 compute_bb_for_insn (get_max_uid ());
2668 count_or_remove_death_notes (blocks, 1);
2669 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
2672 sbitmap_free (blocks);
2675 #ifdef HAVE_peephole2
2676 struct peep2_insn_data
2682 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2683 static int peep2_current;
2685 /* A non-insn marker indicating the last insn of the block.
2686 The live_before regset for this element is correct, indicating
2687 global_live_at_end for the block. */
2688 #define PEEP2_EOB pc_rtx
2690 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2691 does not exist. Used by the recognizer to find the next insn to match
2692 in a multi-insn pattern. */
2698 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2702 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2703 n -= MAX_INSNS_PER_PEEP2 + 1;
2705 if (peep2_insn_data[n].insn == PEEP2_EOB)
2707 return peep2_insn_data[n].insn;
2710 /* Return true if REGNO is dead before the Nth non-note insn
2714 peep2_regno_dead_p (ofs, regno)
2718 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2721 ofs += peep2_current;
2722 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2723 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2725 if (peep2_insn_data[ofs].insn == NULL_RTX)
2728 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2731 /* Similarly for a REG. */
2734 peep2_reg_dead_p (ofs, reg)
2740 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2743 ofs += peep2_current;
2744 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2745 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2747 if (peep2_insn_data[ofs].insn == NULL_RTX)
2750 regno = REGNO (reg);
2751 n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2753 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2758 /* Try to find a hard register of mode MODE, matching the register class in
2759 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2760 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2761 in which case the only condition is that the register must be available
2762 before CURRENT_INSN.
2763 Registers that already have bits set in REG_SET will not be considered.
2765 If an appropriate register is available, it will be returned and the
2766 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2770 peep2_find_free_register (from, to, class_str, mode, reg_set)
2772 const char *class_str;
2773 enum machine_mode mode;
2774 HARD_REG_SET *reg_set;
2776 static int search_ofs;
2777 enum reg_class class;
2781 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1)
2784 from += peep2_current;
2785 if (from >= MAX_INSNS_PER_PEEP2 + 1)
2786 from -= MAX_INSNS_PER_PEEP2 + 1;
2787 to += peep2_current;
2788 if (to >= MAX_INSNS_PER_PEEP2 + 1)
2789 to -= MAX_INSNS_PER_PEEP2 + 1;
2791 if (peep2_insn_data[from].insn == NULL_RTX)
2793 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
2797 HARD_REG_SET this_live;
2799 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
2801 if (peep2_insn_data[from].insn == NULL_RTX)
2803 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
2804 IOR_HARD_REG_SET (live, this_live);
2807 class = (class_str[0] == 'r' ? GENERAL_REGS
2808 : REG_CLASS_FROM_LETTER (class_str[0]));
2810 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2812 int raw_regno, regno, success, j;
2814 /* Distribute the free registers as much as possible. */
2815 raw_regno = search_ofs + i;
2816 if (raw_regno >= FIRST_PSEUDO_REGISTER)
2817 raw_regno -= FIRST_PSEUDO_REGISTER;
2818 #ifdef REG_ALLOC_ORDER
2819 regno = reg_alloc_order[raw_regno];
2824 /* Don't allocate fixed registers. */
2825 if (fixed_regs[regno])
2827 /* Make sure the register is of the right class. */
2828 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno))
2830 /* And can support the mode we need. */
2831 if (! HARD_REGNO_MODE_OK (regno, mode))
2833 /* And that we don't create an extra save/restore. */
2834 if (! call_used_regs[regno] && ! regs_ever_live[regno])
2836 /* And we don't clobber traceback for noreturn functions. */
2837 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
2838 && (! reload_completed || frame_pointer_needed))
2842 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2844 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
2845 || TEST_HARD_REG_BIT (live, regno + j))
2853 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2854 SET_HARD_REG_BIT (*reg_set, regno + j);
2856 /* Start the next search with the next register. */
2857 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
2859 search_ofs = raw_regno;
2861 return gen_rtx_REG (mode, regno);
2869 /* Perform the peephole2 optimization pass. */
2872 peephole2_optimize (dump_file)
2873 FILE *dump_file ATTRIBUTE_UNUSED;
2875 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
2879 #ifdef HAVE_conditional_execution
2884 /* Initialize the regsets we're going to use. */
2885 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
2886 peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]);
2887 live = INITIALIZE_REG_SET (rs_heads[i]);
2889 #ifdef HAVE_conditional_execution
2890 blocks = sbitmap_alloc (n_basic_blocks);
2891 sbitmap_zero (blocks);
2894 count_or_remove_death_notes (NULL, 1);
2897 for (b = n_basic_blocks - 1; b >= 0; --b)
2899 basic_block bb = BASIC_BLOCK (b);
2900 struct propagate_block_info *pbi;
2902 /* Indicate that all slots except the last holds invalid data. */
2903 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
2904 peep2_insn_data[i].insn = NULL_RTX;
2906 /* Indicate that the last slot contains live_after data. */
2907 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
2908 peep2_current = MAX_INSNS_PER_PEEP2;
2910 /* Start up propagation. */
2911 COPY_REG_SET (live, bb->global_live_at_end);
2912 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
2914 #ifdef HAVE_conditional_execution
2915 pbi = init_propagate_block_info (bb, live, NULL, 0);
2917 pbi = init_propagate_block_info (bb, live, NULL, PROP_DEATH_NOTES);
2920 for (insn = bb->end; ; insn = prev)
2922 prev = PREV_INSN (insn);
2928 /* Record this insn. */
2929 if (--peep2_current < 0)
2930 peep2_current = MAX_INSNS_PER_PEEP2;
2931 peep2_insn_data[peep2_current].insn = insn;
2932 propagate_one_insn (pbi, insn);
2933 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
2935 /* Match the peephole. */
2936 try = peephole2_insns (PATTERN (insn), insn, &match_len);
2939 i = match_len + peep2_current;
2940 if (i >= MAX_INSNS_PER_PEEP2 + 1)
2941 i -= MAX_INSNS_PER_PEEP2 + 1;
2943 /* Replace the old sequence with the new. */
2944 flow_delete_insn_chain (insn, peep2_insn_data[i].insn);
2945 try = emit_insn_after (try, prev);
2947 /* Adjust the basic block boundaries. */
2948 if (peep2_insn_data[i].insn == bb->end)
2950 if (insn == bb->head)
2951 bb->head = NEXT_INSN (prev);
2953 #ifdef HAVE_conditional_execution
2954 /* With conditional execution, we cannot back up the
2955 live information so easily, since the conditional
2956 death data structures are not so self-contained.
2957 So record that we've made a modification to this
2958 block and update life information at the end. */
2959 SET_BIT (blocks, b);
2962 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
2963 peep2_insn_data[i].insn = NULL_RTX;
2964 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
2966 /* Back up lifetime information past the end of the
2967 newly created sequence. */
2968 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
2970 COPY_REG_SET (live, peep2_insn_data[i].live_before);
2972 /* Update life information for the new sequence. */
2978 i = MAX_INSNS_PER_PEEP2;
2979 peep2_insn_data[i].insn = try;
2980 propagate_one_insn (pbi, try);
2981 COPY_REG_SET (peep2_insn_data[i].live_before, live);
2983 try = PREV_INSN (try);
2985 while (try != prev);
2987 /* ??? Should verify that LIVE now matches what we
2988 had before the new sequence. */
2995 if (insn == bb->head)
2999 free_propagate_block_info (pbi);
3002 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3003 FREE_REG_SET (peep2_insn_data[i].live_before);
3004 FREE_REG_SET (live);
3006 #ifdef HAVE_conditional_execution
3007 count_or_remove_death_notes (blocks, 1);
3008 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
3009 sbitmap_free (blocks);
3012 #endif /* HAVE_peephole2 */