1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 #include "insn-config.h"
25 #include "insn-attr.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
30 #include "hard-reg-set.h"
34 #ifndef STACK_PUSH_CODE
35 #ifdef STACK_GROWS_DOWNWARD
36 #define STACK_PUSH_CODE PRE_DEC
38 #define STACK_PUSH_CODE PRE_INC
42 /* Import from final.c: */
43 extern rtx alter_subreg ();
45 int strict_memory_address_p ();
46 int memory_address_p ();
48 /* Nonzero means allow operands to be volatile.
49 This should be 0 if you are generating rtl, such as if you are calling
50 the functions in optabs.c and expmed.c (most of the time).
51 This should be 1 if all valid insns need to be recognized,
52 such as in regclass.c and final.c and reload.c.
54 init_recog and init_recog_no_volatile are responsible for setting this. */
58 /* On return from `constrain_operands', indicate which alternative
61 int which_alternative;
63 /* Nonzero after end of reload pass.
64 Set to 1 or 0 by toplev.c.
65 Controls the significance of (SUBREG (MEM)). */
69 /* Initialize data used by the function `recog'.
70 This must be called once in the compilation of a function
71 before any insn recognition may be done in the function. */
74 init_recog_no_volatile ()
85 /* Try recognizing the instruction INSN,
86 and return the code number that results.
87 Remeber the code so that repeated calls do not
88 need to spend the time for actual rerecognition.
90 This function is the normal interface to instruction recognition.
91 The automatically-generated function `recog' is normally called
92 through this one. (The only exception is in combine.c.) */
98 if (INSN_CODE (insn) < 0)
99 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
100 return INSN_CODE (insn);
103 /* Check that X is an insn-body for an `asm' with operands
104 and that the operands mentioned in it are legitimate. */
107 check_asm_operands (x)
110 int noperands = asm_noperands (x);
119 operands = (rtx *) alloca (noperands * sizeof (rtx));
120 decode_asm_operands (x, operands, NULL_PTR, NULL_PTR, NULL_PTR);
122 for (i = 0; i < noperands; i++)
123 if (!general_operand (operands[i], VOIDmode))
129 /* Static data for the next two routines.
131 The maximum number of changes supported is defined as the maximum
132 number of operands times 5. This allows for repeated substitutions
133 inside complex indexed address, or, alternatively, changes in up
136 #define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5)
138 static rtx change_objects[MAX_CHANGE_LOCS];
139 static int change_old_codes[MAX_CHANGE_LOCS];
140 static rtx *change_locs[MAX_CHANGE_LOCS];
141 static rtx change_olds[MAX_CHANGE_LOCS];
143 static int num_changes = 0;
145 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
146 at which NEW will be placed. If OBJECT is zero, no validation is done,
147 the change is simply made.
149 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
150 will be called with the address and mode as parameters. If OBJECT is
151 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
154 IN_GROUP is non-zero if this is part of a group of changes that must be
155 performed as a group. In that case, the changes will be stored. The
156 function `apply_change_group' will validate and apply the changes.
158 If IN_GROUP is zero, this is a single change. Try to recognize the insn
159 or validate the memory reference with the change applied. If the result
160 is not valid for the machine, suppress the change and return zero.
161 Otherwise, perform the change and return 1. */
164 validate_change (object, loc, new, in_group)
172 if (old == new || rtx_equal_p (old, new))
175 if (num_changes >= MAX_CHANGE_LOCS
176 || (in_group == 0 && num_changes != 0))
181 /* Save the information describing this change. */
182 change_objects[num_changes] = object;
183 change_locs[num_changes] = loc;
184 change_olds[num_changes] = old;
186 if (object && GET_CODE (object) != MEM)
188 /* Set INSN_CODE to force rerecognition of insn. Save old code in
190 change_old_codes[num_changes] = INSN_CODE (object);
191 INSN_CODE (object) = -1;
196 /* If we are making a group of changes, return 1. Otherwise, validate the
197 change group we made. */
202 return apply_change_group ();
205 /* Apply a group of changes previously issued with `validate_change'.
206 Return 1 if all changes are valid, zero otherwise. */
209 apply_change_group ()
213 /* The changes have been applied and all INSN_CODEs have been reset to force
216 The changes are valid if we aren't given an object, or if we are
217 given a MEM and it still is a valid address, or if this is in insn
218 and it is recognized. In the latter case, if reload has completed,
219 we also require that the operands meet the constraints for
220 the insn. We do not allow modifying an ASM_OPERANDS after reload
221 has completed because verifying the constraints is too difficult. */
223 for (i = 0; i < num_changes; i++)
225 rtx object = change_objects[i];
230 if (GET_CODE (object) == MEM)
232 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
235 else if ((recog_memoized (object) < 0
236 && (asm_noperands (PATTERN (object)) < 0
237 || ! check_asm_operands (PATTERN (object))
238 || reload_completed))
240 && (insn_extract (object),
241 ! constrain_operands (INSN_CODE (object), 1))))
243 rtx pat = PATTERN (object);
245 /* Perhaps we couldn't recognize the insn because there were
246 extra CLOBBERs at the end. If so, try to re-recognize
247 without the last CLOBBER (later iterations will cause each of
248 them to be eliminated, in turn). But don't do this if we
249 have an ASM_OPERAND. */
250 if (GET_CODE (pat) == PARALLEL
251 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
252 && asm_noperands (PATTERN (object)) < 0)
256 if (XVECLEN (pat, 0) == 2)
257 newpat = XVECEXP (pat, 0, 0);
262 newpat = gen_rtx (PARALLEL, VOIDmode,
263 gen_rtvec (XVECLEN (pat, 0) - 1));
264 for (j = 0; j < XVECLEN (newpat, 0); j++)
265 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
268 /* Add a new change to this group to replace the pattern
269 with this new pattern. Then consider this change
270 as having succeeded. The change we added will
271 cause the entire call to fail if things remain invalid.
273 Note that this can lose if a later change than the one
274 we are processing specified &XVECEXP (PATTERN (object), 0, X)
275 but this shouldn't occur. */
277 validate_change (object, &PATTERN (object), newpat, 1);
279 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
280 /* If this insn is a CLOBBER or USE, it is always valid, but is
288 if (i == num_changes)
300 /* Return the number of changes so far in the current group. */
303 num_validated_changes ()
308 /* Retract the changes numbered NUM and up. */
316 /* Back out all the changes. Do this in the opposite order in which
318 for (i = num_changes - 1; i >= num; i--)
320 *change_locs[i] = change_olds[i];
321 if (change_objects[i] && GET_CODE (change_objects[i]) != MEM)
322 INSN_CODE (change_objects[i]) = change_old_codes[i];
327 /* Replace every occurrence of FROM in X with TO. Mark each change with
328 validate_change passing OBJECT. */
331 validate_replace_rtx_1 (loc, from, to, object)
333 rtx from, to, object;
337 register rtx x = *loc;
338 enum rtx_code code = GET_CODE (x);
340 /* X matches FROM if it is the same rtx or they are both referring to the
341 same register in the same mode. Avoid calling rtx_equal_p unless the
342 operands look similar. */
345 || (GET_CODE (x) == REG && GET_CODE (from) == REG
346 && GET_MODE (x) == GET_MODE (from)
347 && REGNO (x) == REGNO (from))
348 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
349 && rtx_equal_p (x, from)))
351 validate_change (object, loc, to, 1);
355 /* For commutative or comparison operations, try replacing each argument
356 separately and seeing if we made any changes. If so, put a constant
358 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
360 int prev_changes = num_changes;
362 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
363 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
364 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
366 validate_change (object, loc,
367 gen_rtx (GET_RTX_CLASS (code) == 'c' ? code
368 : swap_condition (code),
369 GET_MODE (x), XEXP (x, 1), XEXP (x, 0)),
379 /* If we have have a PLUS whose second operand is now a CONST_INT, use
380 plus_constant to try to simplify it. */
381 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
382 validate_change (object, loc,
383 plus_constant (XEXP (x, 0), INTVAL (XEXP (x, 1))), 1);
388 /* In these cases, the operation to be performed depends on the mode
389 of the operand. If we are replacing the operand with a VOIDmode
390 constant, we lose the information. So try to simplify the operation
391 in that case. If it fails, substitute in something that we know
392 won't be recognized. */
393 if (GET_MODE (to) == VOIDmode
394 && (XEXP (x, 0) == from
395 || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG
396 && GET_MODE (XEXP (x, 0)) == GET_MODE (from)
397 && REGNO (XEXP (x, 0)) == REGNO (from))))
399 rtx new = simplify_unary_operation (code, GET_MODE (x), to,
402 new = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
404 validate_change (object, loc, new, 1);
410 /* If we have a SUBREG of a register that we are replacing and we are
411 replacing it with a MEM, make a new MEM and try replacing the
412 SUBREG with it. Don't do this if the MEM has a mode-dependent address
413 or if we would be widening it. */
415 if (SUBREG_REG (x) == from
416 && GET_CODE (from) == REG
417 && GET_CODE (to) == MEM
418 && ! mode_dependent_address_p (XEXP (to, 0))
419 && ! MEM_VOLATILE_P (to)
420 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
422 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
423 enum machine_mode mode = GET_MODE (x);
427 offset += (MIN (UNITS_PER_WORD,
428 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
429 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
432 new = gen_rtx (MEM, mode, plus_constant (XEXP (to, 0), offset));
433 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to);
434 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to);
435 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to);
436 validate_change (object, loc, new, 1);
443 /* If we are replacing a register with memory, try to change the memory
444 to be the mode required for memory in extract operations (this isn't
445 likely to be an insertion operation; if it was, nothing bad will
446 happen, we might just fail in some cases). */
448 if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM
449 && GET_CODE (XEXP (x, 1)) == CONST_INT
450 && GET_CODE (XEXP (x, 2)) == CONST_INT
451 && ! mode_dependent_address_p (XEXP (to, 0))
452 && ! MEM_VOLATILE_P (to))
454 enum machine_mode wanted_mode = VOIDmode;
455 enum machine_mode is_mode = GET_MODE (to);
456 int width = INTVAL (XEXP (x, 1));
457 int pos = INTVAL (XEXP (x, 2));
460 if (code == ZERO_EXTRACT)
461 wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
464 if (code == SIGN_EXTRACT)
465 wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
468 /* If we have a narrower mode, we can do something. */
469 if (wanted_mode != VOIDmode
470 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
472 int offset = pos / BITS_PER_UNIT;
475 /* If the bytes and bits are counted differently, we
476 must adjust the offset. */
477 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
478 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
482 pos %= GET_MODE_BITSIZE (wanted_mode);
484 newmem = gen_rtx (MEM, wanted_mode,
485 plus_constant (XEXP (to, 0), offset));
486 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to);
487 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (to);
488 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (to);
490 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
491 validate_change (object, &XEXP (x, 0), newmem, 1);
498 fmt = GET_RTX_FORMAT (code);
499 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
502 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
503 else if (fmt[i] == 'E')
504 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
505 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
509 /* Try replacing every occurrence of FROM in INSN with TO. After all
510 changes have been made, validate by seeing if INSN is still valid. */
513 validate_replace_rtx (from, to, insn)
516 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
517 return apply_change_group ();
521 /* Return 1 if the insn using CC0 set by INSN does not contain
522 any ordered tests applied to the condition codes.
523 EQ and NE tests do not count. */
526 next_insn_tests_no_inequality (insn)
529 register rtx next = next_cc0_user (insn);
531 /* If there is no next insn, we have to take the conservative choice. */
535 return ((GET_CODE (next) == JUMP_INSN
536 || GET_CODE (next) == INSN
537 || GET_CODE (next) == CALL_INSN)
538 && ! inequality_comparisons_p (PATTERN (next)));
541 #if 0 /* This is useless since the insn that sets the cc's
542 must be followed immediately by the use of them. */
543 /* Return 1 if the CC value set up by INSN is not used. */
546 next_insns_test_no_inequality (insn)
549 register rtx next = NEXT_INSN (insn);
551 for (; next != 0; next = NEXT_INSN (next))
553 if (GET_CODE (next) == CODE_LABEL
554 || GET_CODE (next) == BARRIER)
556 if (GET_CODE (next) == NOTE)
558 if (inequality_comparisons_p (PATTERN (next)))
560 if (sets_cc0_p (PATTERN (next)) == 1)
562 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
570 /* This is used by find_single_use to locate an rtx that contains exactly one
571 use of DEST, which is typically either a REG or CC0. It returns a
572 pointer to the innermost rtx expression containing DEST. Appearances of
573 DEST that are being used to totally replace it are not counted. */
576 find_single_use_1 (dest, loc)
581 enum rtx_code code = GET_CODE (x);
598 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
599 of a REG that occupies all of the REG, the insn uses DEST if
600 it is mentioned in the destination or the source. Otherwise, we
601 need just check the source. */
602 if (GET_CODE (SET_DEST (x)) != CC0
603 && GET_CODE (SET_DEST (x)) != PC
604 && GET_CODE (SET_DEST (x)) != REG
605 && ! (GET_CODE (SET_DEST (x)) == SUBREG
606 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
607 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
608 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
609 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
610 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
613 return find_single_use_1 (dest, &SET_SRC (x));
617 return find_single_use_1 (dest, &XEXP (x, 0));
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
623 fmt = GET_RTX_FORMAT (code);
624 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
628 if (dest == XEXP (x, i)
629 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
630 && REGNO (dest) == REGNO (XEXP (x, i))))
633 this_result = find_single_use_1 (dest, &XEXP (x, i));
636 result = this_result;
637 else if (this_result)
638 /* Duplicate usage. */
641 else if (fmt[i] == 'E')
645 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
647 if (XVECEXP (x, i, j) == dest
648 || (GET_CODE (dest) == REG
649 && GET_CODE (XVECEXP (x, i, j)) == REG
650 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
653 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
656 result = this_result;
657 else if (this_result)
666 /* See if DEST, produced in INSN, is used only a single time in the
667 sequel. If so, return a pointer to the innermost rtx expression in which
670 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
672 This routine will return usually zero either before flow is called (because
673 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
674 note can't be trusted).
676 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
677 care about REG_DEAD notes or LOG_LINKS.
679 Otherwise, we find the single use by finding an insn that has a
680 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
681 only referenced once in that insn, we know that it must be the first
682 and last insn referencing DEST. */
685 find_single_use (dest, insn, ploc)
697 next = NEXT_INSN (insn);
699 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
702 result = find_single_use_1 (dest, &PATTERN (next));
709 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
712 for (next = next_nonnote_insn (insn);
713 next != 0 && GET_CODE (next) != CODE_LABEL;
714 next = next_nonnote_insn (next))
715 if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest))
717 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
718 if (XEXP (link, 0) == insn)
723 result = find_single_use_1 (dest, &PATTERN (next));
733 /* Return 1 if OP is a valid general operand for machine mode MODE.
734 This is either a register reference, a memory reference,
735 or a constant. In the case of a memory reference, the address
736 is checked for general validity for the target machine.
738 Register and memory references must have mode MODE in order to be valid,
739 but some constants have no machine mode and are valid for any mode.
741 If MODE is VOIDmode, OP is checked for validity for whatever mode
744 The main use of this function is as a predicate in match_operand
745 expressions in the machine description.
747 For an explanation of this function's behavior for registers of
748 class NO_REGS, see the comment for `register_operand'. */
751 general_operand (op, mode)
753 enum machine_mode mode;
755 register enum rtx_code code = GET_CODE (op);
756 int mode_altering_drug = 0;
758 if (mode == VOIDmode)
759 mode = GET_MODE (op);
761 /* Don't accept CONST_INT or anything similar
762 if the caller wants something floating. */
763 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
764 && GET_MODE_CLASS (mode) != MODE_INT)
768 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
769 #ifdef LEGITIMATE_PIC_OPERAND_P
770 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
772 && LEGITIMATE_CONSTANT_P (op));
774 /* Except for certain constants with VOIDmode, already checked for,
775 OP's mode must match MODE if MODE specifies a mode. */
777 if (GET_MODE (op) != mode)
782 #ifdef INSN_SCHEDULING
783 /* On machines that have insn scheduling, we want all memory
784 reference to be explicit, so outlaw paradoxical SUBREGs. */
785 if (GET_CODE (SUBREG_REG (op)) == MEM
786 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
790 op = SUBREG_REG (op);
791 code = GET_CODE (op);
793 /* No longer needed, since (SUBREG (MEM...))
794 will load the MEM into a reload reg in the MEM's own mode. */
795 mode_altering_drug = 1;
800 /* A register whose class is NO_REGS is not a general operand. */
801 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
802 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
806 register rtx y = XEXP (op, 0);
807 if (! volatile_ok && MEM_VOLATILE_P (op))
809 /* Use the mem's mode, since it will be reloaded thus. */
810 mode = GET_MODE (op);
811 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
816 if (mode_altering_drug)
817 return ! mode_dependent_address_p (XEXP (op, 0));
821 /* Return 1 if OP is a valid memory address for a memory reference
824 The main use of this function is as a predicate in match_operand
825 expressions in the machine description. */
828 address_operand (op, mode)
830 enum machine_mode mode;
832 return memory_address_p (mode, op);
835 /* Return 1 if OP is a register reference of mode MODE.
836 If MODE is VOIDmode, accept a register in any mode.
838 The main use of this function is as a predicate in match_operand
839 expressions in the machine description.
841 As a special exception, registers whose class is NO_REGS are
842 not accepted by `register_operand'. The reason for this change
843 is to allow the representation of special architecture artifacts
844 (such as a condition code register) without extending the rtl
845 definitions. Since registers of class NO_REGS cannot be used
846 as registers in any case where register classes are examined,
847 it is most consistent to keep this function from accepting them. */
850 register_operand (op, mode)
852 enum machine_mode mode;
854 if (GET_MODE (op) != mode && mode != VOIDmode)
857 if (GET_CODE (op) == SUBREG)
859 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
860 because it is guaranteed to be reloaded into one.
861 Just make sure the MEM is valid in itself.
862 (Ideally, (SUBREG (MEM)...) should not exist after reload,
863 but currently it does result from (SUBREG (REG)...) where the
864 reg went on the stack.) */
865 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
866 return general_operand (op, mode);
867 op = SUBREG_REG (op);
870 /* We don't consider registers whose class is NO_REGS
871 to be a register operand. */
872 return (GET_CODE (op) == REG
873 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
874 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
877 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
878 or a hard register. */
881 scratch_operand (op, mode)
883 enum machine_mode mode;
885 return (GET_MODE (op) == mode
886 && (GET_CODE (op) == SCRATCH
887 || (GET_CODE (op) == REG
888 && REGNO (op) < FIRST_PSEUDO_REGISTER)));
891 /* Return 1 if OP is a valid immediate operand for mode MODE.
893 The main use of this function is as a predicate in match_operand
894 expressions in the machine description. */
897 immediate_operand (op, mode)
899 enum machine_mode mode;
901 /* Don't accept CONST_INT or anything similar
902 if the caller wants something floating. */
903 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
904 && GET_MODE_CLASS (mode) != MODE_INT)
907 return (CONSTANT_P (op)
908 && (GET_MODE (op) == mode || mode == VOIDmode
909 || GET_MODE (op) == VOIDmode)
910 #ifdef LEGITIMATE_PIC_OPERAND_P
911 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
913 && LEGITIMATE_CONSTANT_P (op));
916 /* Returns 1 if OP is an operand that is a CONST_INT. */
919 const_int_operand (op, mode)
921 enum machine_mode mode;
923 return GET_CODE (op) == CONST_INT;
926 /* Returns 1 if OP is an operand that is a constant integer or constant
927 floating-point number. */
930 const_double_operand (op, mode)
932 enum machine_mode mode;
934 /* Don't accept CONST_INT or anything similar
935 if the caller wants something floating. */
936 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
937 && GET_MODE_CLASS (mode) != MODE_INT)
940 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
941 && (mode == VOIDmode || GET_MODE (op) == mode
942 || GET_MODE (op) == VOIDmode));
945 /* Return 1 if OP is a general operand that is not an immediate operand. */
948 nonimmediate_operand (op, mode)
950 enum machine_mode mode;
952 return (general_operand (op, mode) && ! CONSTANT_P (op));
955 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
958 nonmemory_operand (op, mode)
960 enum machine_mode mode;
964 /* Don't accept CONST_INT or anything similar
965 if the caller wants something floating. */
966 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
967 && GET_MODE_CLASS (mode) != MODE_INT)
970 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
971 #ifdef LEGITIMATE_PIC_OPERAND_P
972 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
974 && LEGITIMATE_CONSTANT_P (op));
977 if (GET_MODE (op) != mode && mode != VOIDmode)
980 if (GET_CODE (op) == SUBREG)
982 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
983 because it is guaranteed to be reloaded into one.
984 Just make sure the MEM is valid in itself.
985 (Ideally, (SUBREG (MEM)...) should not exist after reload,
986 but currently it does result from (SUBREG (REG)...) where the
987 reg went on the stack.) */
988 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
989 return general_operand (op, mode);
990 op = SUBREG_REG (op);
993 /* We don't consider registers whose class is NO_REGS
994 to be a register operand. */
995 return (GET_CODE (op) == REG
996 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
997 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1000 /* Return 1 if OP is a valid operand that stands for pushing a
1001 value of mode MODE onto the stack.
1003 The main use of this function is as a predicate in match_operand
1004 expressions in the machine description. */
1007 push_operand (op, mode)
1009 enum machine_mode mode;
1011 if (GET_CODE (op) != MEM)
1014 if (GET_MODE (op) != mode)
1019 if (GET_CODE (op) != STACK_PUSH_CODE)
1022 return XEXP (op, 0) == stack_pointer_rtx;
1025 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1028 memory_address_p (mode, addr)
1029 enum machine_mode mode;
1032 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1039 /* Return 1 if OP is a valid memory reference with mode MODE,
1040 including a valid address.
1042 The main use of this function is as a predicate in match_operand
1043 expressions in the machine description. */
1046 memory_operand (op, mode)
1048 enum machine_mode mode;
1052 if (! reload_completed)
1053 /* Note that no SUBREG is a memory operand before end of reload pass,
1054 because (SUBREG (MEM...)) forces reloading into a register. */
1055 return GET_CODE (op) == MEM && general_operand (op, mode);
1057 if (mode != VOIDmode && GET_MODE (op) != mode)
1061 if (GET_CODE (inner) == SUBREG)
1062 inner = SUBREG_REG (inner);
1064 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1067 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1068 that is, a memory reference whose address is a general_operand. */
1071 indirect_operand (op, mode)
1073 enum machine_mode mode;
1075 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1076 if (! reload_completed
1077 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1079 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1080 rtx inner = SUBREG_REG (op);
1082 #if BYTES_BIG_ENDIAN
1083 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1084 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1087 /* The only way that we can have a general_operand as the resulting
1088 address is if OFFSET is zero and the address already is an operand
1089 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1092 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1093 || (GET_CODE (XEXP (inner, 0)) == PLUS
1094 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1095 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1096 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1099 return (GET_CODE (op) == MEM
1100 && memory_operand (op, mode)
1101 && general_operand (XEXP (op, 0), Pmode));
1104 /* Return 1 if this is a comparison operator. This allows the use of
1105 MATCH_OPERATOR to recognize all the branch insns. */
1108 comparison_operator (op, mode)
1110 enum machine_mode mode;
1112 return ((mode == VOIDmode || GET_MODE (op) == mode)
1113 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1116 /* If BODY is an insn body that uses ASM_OPERANDS,
1117 return the number of operands (both input and output) in the insn.
1118 Otherwise return -1. */
1121 asm_noperands (body)
1124 if (GET_CODE (body) == ASM_OPERANDS)
1125 /* No output operands: return number of input operands. */
1126 return ASM_OPERANDS_INPUT_LENGTH (body);
1127 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1128 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1129 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1130 else if (GET_CODE (body) == PARALLEL
1131 && GET_CODE (XVECEXP (body, 0, 0)) == SET
1132 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1134 /* Multiple output operands, or 1 output plus some clobbers:
1135 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1139 /* Count backwards through CLOBBERs to determine number of SETs. */
1140 for (i = XVECLEN (body, 0); i > 0; i--)
1142 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1144 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1148 /* N_SETS is now number of output operands. */
1151 /* Verify that all the SETs we have
1152 came from a single original asm_operands insn
1153 (so that invalid combinations are blocked). */
1154 for (i = 0; i < n_sets; i++)
1156 rtx elt = XVECEXP (body, 0, i);
1157 if (GET_CODE (elt) != SET)
1159 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1161 /* If these ASM_OPERANDS rtx's came from different original insns
1162 then they aren't allowed together. */
1163 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1164 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1167 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1170 else if (GET_CODE (body) == PARALLEL
1171 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1173 /* 0 outputs, but some clobbers:
1174 body is [(asm_operands ...) (clobber (reg ...))...]. */
1177 /* Make sure all the other parallel things really are clobbers. */
1178 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1179 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1182 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1188 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1189 copy its operands (both input and output) into the vector OPERANDS,
1190 the locations of the operands within the insn into the vector OPERAND_LOCS,
1191 and the constraints for the operands into CONSTRAINTS.
1192 Write the modes of the operands into MODES.
1193 Return the assembler-template.
1195 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1196 we don't store that info. */
1199 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1204 enum machine_mode *modes;
1210 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1212 rtx asmop = SET_SRC (body);
1213 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1215 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1217 for (i = 1; i < noperands; i++)
1220 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1222 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1224 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1226 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1229 /* The output is in the SET.
1230 Its constraint is in the ASM_OPERANDS itself. */
1232 operands[0] = SET_DEST (body);
1234 operand_locs[0] = &SET_DEST (body);
1236 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1238 modes[0] = GET_MODE (SET_DEST (body));
1239 template = ASM_OPERANDS_TEMPLATE (asmop);
1241 else if (GET_CODE (body) == ASM_OPERANDS)
1244 /* No output operands: BODY is (asm_operands ....). */
1246 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1248 /* The input operands are found in the 1st element vector. */
1249 /* Constraints for inputs are in the 2nd element vector. */
1250 for (i = 0; i < noperands; i++)
1253 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1255 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1257 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1259 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1261 template = ASM_OPERANDS_TEMPLATE (asmop);
1263 else if (GET_CODE (body) == PARALLEL
1264 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1266 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1267 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1268 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1269 int nout = 0; /* Does not include CLOBBERs. */
1271 /* At least one output, plus some CLOBBERs. */
1273 /* The outputs are in the SETs.
1274 Their constraints are in the ASM_OPERANDS itself. */
1275 for (i = 0; i < nparallel; i++)
1277 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1278 break; /* Past last SET */
1281 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1283 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1285 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1287 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1291 for (i = 0; i < nin; i++)
1294 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1296 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1298 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1300 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1303 template = ASM_OPERANDS_TEMPLATE (asmop);
1305 else if (GET_CODE (body) == PARALLEL
1306 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1308 /* No outputs, but some CLOBBERs. */
1310 rtx asmop = XVECEXP (body, 0, 0);
1311 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1313 for (i = 0; i < nin; i++)
1316 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1318 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1320 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1322 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1325 template = ASM_OPERANDS_TEMPLATE (asmop);
1331 /* Given an rtx *P, if it is a sum containing an integer constant term,
1332 return the location (type rtx *) of the pointer to that constant term.
1333 Otherwise, return a null pointer. */
1336 find_constant_term_loc (p)
1340 register enum rtx_code code = GET_CODE (*p);
1342 /* If *P IS such a constant term, P is its location. */
1344 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1348 /* Otherwise, if not a sum, it has no constant term. */
1350 if (GET_CODE (*p) != PLUS)
1353 /* If one of the summands is constant, return its location. */
1355 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1356 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1359 /* Otherwise, check each summand for containing a constant term. */
1361 if (XEXP (*p, 0) != 0)
1363 tem = find_constant_term_loc (&XEXP (*p, 0));
1368 if (XEXP (*p, 1) != 0)
1370 tem = find_constant_term_loc (&XEXP (*p, 1));
1378 /* Return 1 if OP is a memory reference
1379 whose address contains no side effects
1380 and remains valid after the addition
1381 of a positive integer less than the
1382 size of the object being referenced.
1384 We assume that the original address is valid and do not check it.
1386 This uses strict_memory_address_p as a subroutine, so
1387 don't use it before reload. */
1390 offsettable_memref_p (op)
1393 return ((GET_CODE (op) == MEM)
1394 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1397 /* Similar, but don't require a strictly valid mem ref:
1398 consider pseudo-regs valid as index or base regs. */
1401 offsettable_nonstrict_memref_p (op)
1404 return ((GET_CODE (op) == MEM)
1405 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1408 /* Return 1 if Y is a memory address which contains no side effects
1409 and would remain valid after the addition of a positive integer
1410 less than the size of that mode.
1412 We assume that the original address is valid and do not check it.
1413 We do check that it is valid for narrower modes.
1415 If STRICTP is nonzero, we require a strictly valid address,
1416 for the sake of use in reload.c. */
1419 offsettable_address_p (strictp, mode, y)
1421 enum machine_mode mode;
1424 register enum rtx_code ycode = GET_CODE (y);
1428 int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p);
1430 if (CONSTANT_ADDRESS_P (y))
1433 /* Adjusting an offsettable address involves changing to a narrower mode.
1434 Make sure that's OK. */
1436 if (mode_dependent_address_p (y))
1439 /* If the expression contains a constant term,
1440 see if it remains valid when max possible offset is added. */
1442 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1447 *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1);
1448 /* Use QImode because an odd displacement may be automatically invalid
1449 for any wider mode. But it should be valid for a single byte. */
1450 good = (*addressp) (QImode, y);
1452 /* In any case, restore old contents of memory. */
1457 if (ycode == PRE_DEC || ycode == PRE_INC
1458 || ycode == POST_DEC || ycode == POST_INC)
1461 /* The offset added here is chosen as the maximum offset that
1462 any instruction could need to add when operating on something
1463 of the specified mode. We assume that if Y and Y+c are
1464 valid addresses then so is Y+d for all 0<d<c. */
1466 z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1);
1468 /* Use QImode because an odd displacement may be automatically invalid
1469 for any wider mode. But it should be valid for a single byte. */
1470 return (*addressp) (QImode, z);
1473 /* Return 1 if ADDR is an address-expression whose effect depends
1474 on the mode of the memory reference it is used in.
1476 Autoincrement addressing is a typical example of mode-dependence
1477 because the amount of the increment depends on the mode. */
1480 mode_dependent_address_p (addr)
1483 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1489 /* Return 1 if OP is a general operand
1490 other than a memory ref with a mode dependent address. */
1493 mode_independent_operand (op, mode)
1494 enum machine_mode mode;
1499 if (! general_operand (op, mode))
1502 if (GET_CODE (op) != MEM)
1505 addr = XEXP (op, 0);
1506 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
1512 /* Given an operand OP that is a valid memory reference
1513 which satisfies offsettable_memref_p,
1514 return a new memory reference whose address has been adjusted by OFFSET.
1515 OFFSET should be positive and less than the size of the object referenced.
1519 adj_offsettable_operand (op, offset)
1523 register enum rtx_code code = GET_CODE (op);
1527 register rtx y = XEXP (op, 0);
1530 if (CONSTANT_ADDRESS_P (y))
1532 new = gen_rtx (MEM, GET_MODE (op), plus_constant_for_output (y, offset));
1533 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1537 if (GET_CODE (y) == PLUS)
1540 register rtx *const_loc;
1544 const_loc = find_constant_term_loc (&z);
1547 *const_loc = plus_constant_for_output (*const_loc, offset);
1552 new = gen_rtx (MEM, GET_MODE (op), plus_constant_for_output (y, offset));
1553 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1559 #ifdef REGISTER_CONSTRAINTS
1561 /* Check the operands of an insn (found in recog_operands)
1562 against the insn's operand constraints (found via INSN_CODE_NUM)
1563 and return 1 if they are valid.
1565 WHICH_ALTERNATIVE is set to a number which indicates which
1566 alternative of constraints was matched: 0 for the first alternative,
1567 1 for the next, etc.
1569 In addition, when two operands are match
1570 and it happens that the output operand is (reg) while the
1571 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
1572 make the output operand look like the input.
1573 This is because the output operand is the one the template will print.
1575 This is used in final, just before printing the assembler code and by
1576 the routines that determine an insn's attribute.
1578 If STRICT is a positive non-zero value, it means that we have been
1579 called after reload has been completed. In that case, we must
1580 do all checks strictly. If it is zero, it means that we have been called
1581 before reload has completed. In that case, we first try to see if we can
1582 find an alternative that matches strictly. If not, we try again, this
1583 time assuming that reload will fix up the insn. This provides a "best
1584 guess" for the alternative and is used to compute attributes of insns prior
1585 to reload. A negative value of STRICT is used for this internal call. */
1593 constrain_operands (insn_code_num, strict)
1597 char *constraints[MAX_RECOG_OPERANDS];
1598 int matching_operands[MAX_RECOG_OPERANDS];
1599 enum op_type {OP_IN, OP_OUT, OP_INOUT} op_types[MAX_RECOG_OPERANDS];
1600 int earlyclobber[MAX_RECOG_OPERANDS];
1602 int noperands = insn_n_operands[insn_code_num];
1604 struct funny_match funny_match[MAX_RECOG_OPERANDS];
1605 int funny_match_index;
1606 int nalternatives = insn_n_alternatives[insn_code_num];
1608 if (noperands == 0 || nalternatives == 0)
1611 for (c = 0; c < noperands; c++)
1613 constraints[c] = insn_operand_constraint[insn_code_num][c];
1614 matching_operands[c] = -1;
1615 op_types[c] = OP_IN;
1618 which_alternative = 0;
1620 while (which_alternative < nalternatives)
1624 funny_match_index = 0;
1626 for (opno = 0; opno < noperands; opno++)
1628 register rtx op = recog_operand[opno];
1629 enum machine_mode mode = GET_MODE (op);
1630 register char *p = constraints[opno];
1635 earlyclobber[opno] = 0;
1637 if (GET_CODE (op) == SUBREG)
1639 if (GET_CODE (SUBREG_REG (op)) == REG
1640 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
1641 offset = SUBREG_WORD (op);
1642 op = SUBREG_REG (op);
1645 /* An empty constraint or empty alternative
1646 allows anything which matched the pattern. */
1647 if (*p == 0 || *p == ',')
1650 while (*p && (c = *p++) != ',')
1661 op_types[opno] = OP_OUT;
1665 op_types[opno] = OP_INOUT;
1669 earlyclobber[opno] = 1;
1677 /* This operand must be the same as a previous one.
1678 This kind of constraint is used for instructions such
1679 as add when they take only two operands.
1681 Note that the lower-numbered operand is passed first.
1683 If we are not testing strictly, assume that this constraint
1684 will be satisfied. */
1688 val = operands_match_p (recog_operand[c - '0'],
1689 recog_operand[opno]);
1691 matching_operands[opno] = c - '0';
1692 matching_operands[c - '0'] = opno;
1696 /* If output is *x and input is *--x,
1697 arrange later to change the output to *--x as well,
1698 since the output op is the one that will be printed. */
1699 if (val == 2 && strict > 0)
1701 funny_match[funny_match_index].this = opno;
1702 funny_match[funny_match_index++].other = c - '0';
1707 /* p is used for address_operands. When we are called by
1708 gen_input_reload, no one will have checked that the
1709 address is strictly valid, i.e., that all pseudos
1710 requiring hard regs have gotten them. */
1712 || (strict_memory_address_p
1713 (insn_operand_mode[insn_code_num][opno], op)))
1717 /* No need to check general_operand again;
1718 it was done in insn-recog.c. */
1720 /* Anything goes unless it is a REG and really has a hard reg
1721 but the hard reg is not in the class GENERAL_REGS. */
1723 || GENERAL_REGS == ALL_REGS
1724 || GET_CODE (op) != REG
1725 || (reload_in_progress
1726 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1727 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
1734 && GET_CODE (op) == REG
1735 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1736 || (strict == 0 && GET_CODE (op) == SCRATCH)
1737 || (GET_CODE (op) == REG
1738 && (GENERAL_REGS == ALL_REGS
1739 || reg_fits_class_p (op, GENERAL_REGS,
1745 /* This is used for a MATCH_SCRATCH in the cases when we
1746 don't actually need anything. So anything goes any time. */
1751 if (GET_CODE (op) == MEM
1752 /* Before reload, accept what reload can turn into mem. */
1753 || (strict < 0 && CONSTANT_P (op))
1754 /* During reload, accept a pseudo */
1755 || (reload_in_progress && GET_CODE (op) == REG
1756 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
1761 if (GET_CODE (op) == MEM
1762 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1763 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1768 if (GET_CODE (op) == MEM
1769 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1770 || GET_CODE (XEXP (op, 0)) == POST_INC))
1775 /* Match any CONST_DOUBLE, but only if
1776 we can examine the bits of it reliably. */
1777 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1778 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1779 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1781 if (GET_CODE (op) == CONST_DOUBLE)
1786 if (GET_CODE (op) == CONST_DOUBLE)
1792 if (GET_CODE (op) == CONST_DOUBLE
1793 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1798 if (GET_CODE (op) == CONST_INT
1799 || (GET_CODE (op) == CONST_DOUBLE
1800 && GET_MODE (op) == VOIDmode))
1803 if (CONSTANT_P (op))
1808 if (GET_CODE (op) == CONST_INT
1809 || (GET_CODE (op) == CONST_DOUBLE
1810 && GET_MODE (op) == VOIDmode))
1822 if (GET_CODE (op) == CONST_INT
1823 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1827 #ifdef EXTRA_CONSTRAINT
1833 if (EXTRA_CONSTRAINT (op, c))
1839 if (GET_CODE (op) == MEM
1840 && ! offsettable_memref_p (op))
1845 if ((strict > 0 && offsettable_memref_p (op))
1846 || (strict == 0 && offsettable_nonstrict_memref_p (op))
1847 /* Before reload, accept what reload can handle. */
1849 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
1850 /* During reload, accept a pseudo */
1851 || (reload_in_progress && GET_CODE (op) == REG
1852 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
1859 && GET_CODE (op) == REG
1860 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1861 || (strict == 0 && GET_CODE (op) == SCRATCH)
1862 || (GET_CODE (op) == REG
1863 && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c),
1868 constraints[opno] = p;
1869 /* If this operand did not win somehow,
1870 this alternative loses. */
1874 /* This alternative won; the operands are ok.
1875 Change whichever operands this alternative says to change. */
1880 /* See if any earlyclobber operand conflicts with some other
1884 for (eopno = 0; eopno < noperands; eopno++)
1885 /* Ignore earlyclobber operands now in memory,
1886 because we would often report failure when we have
1887 two memory operands, one of which was formerly a REG. */
1888 if (earlyclobber[eopno]
1889 && GET_CODE (recog_operand[eopno]) == REG)
1890 for (opno = 0; opno < noperands; opno++)
1891 if ((GET_CODE (recog_operand[opno]) == MEM
1892 || op_types[opno] != OP_OUT)
1894 && constraints[opno] != 0
1895 && ! (matching_operands[opno] == eopno
1896 && rtx_equal_p (recog_operand[opno],
1897 recog_operand[eopno]))
1898 && ! safe_from_earlyclobber (recog_operand[opno],
1899 recog_operand[eopno]))
1904 while (--funny_match_index >= 0)
1906 recog_operand[funny_match[funny_match_index].other]
1907 = recog_operand[funny_match[funny_match_index].this];
1914 which_alternative++;
1917 /* If we are about to reject this, but we are not to test strictly,
1918 try a very loose test. Only return failure if it fails also. */
1920 return constrain_operands (insn_code_num, -1);
1925 /* Return 1 iff OPERAND (assumed to be a REG rtx)
1926 is a hard reg in class CLASS when its regno is offsetted by OFFSET
1927 and changed to mode MODE.
1928 If REG occupies multiple hard regs, all of them must be in CLASS. */
1931 reg_fits_class_p (operand, class, offset, mode)
1933 register enum reg_class class;
1935 enum machine_mode mode;
1937 register int regno = REGNO (operand);
1938 if (regno < FIRST_PSEUDO_REGISTER
1939 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1944 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
1946 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1955 #endif /* REGISTER_CONSTRAINTS */