1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "insn-flags.h"
30 #include "insn-codes.h"
31 #include "hard-reg-set.h"
38 #include "basic-block.h"
41 #ifndef STACK_PUSH_CODE
42 #ifdef STACK_GROWS_DOWNWARD
43 #define STACK_PUSH_CODE PRE_DEC
45 #define STACK_PUSH_CODE PRE_INC
49 #ifndef STACK_POP_CODE
50 #ifdef STACK_GROWS_DOWNWARD
51 #define STACK_POP_CODE POST_INC
53 #define STACK_POP_CODE POST_DEC
57 static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
58 static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
59 static rtx *find_constant_term_loc PARAMS ((rtx *));
60 static int insn_invalid_p PARAMS ((rtx));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized (insn)
118 if (INSN_CODE (insn) < 0)
119 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
120 return INSN_CODE (insn);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x)
132 const char **constraints;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x));
140 constrain_operands (1);
141 return which_alternative >= 0;
144 noperands = asm_noperands (x);
150 operands = (rtx *) alloca (noperands * sizeof (rtx));
151 constraints = (const char **) alloca (noperands * sizeof (char *));
153 decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR);
155 for (i = 0; i < noperands; i++)
157 const char *c = constraints[i];
160 if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0')
161 c = constraints[c[0] - '0'];
163 if (! asm_operand_ok (operands[i], c))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t *changes;
181 static int changes_allocated;
183 static int num_changes = 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object, loc, new, in_group)
212 if (old == new || rtx_equal_p (old, new))
215 if (in_group == 0 && num_changes != 0)
220 /* Save the information describing this change. */
221 if (num_changes >= changes_allocated)
223 if (changes_allocated == 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated = MAX_RECOG_OPERANDS * 5;
228 changes_allocated *= 2;
231 (change_t*) xrealloc (changes,
232 sizeof (change_t) * changes_allocated);
235 changes[num_changes].object = object;
236 changes[num_changes].loc = loc;
237 changes[num_changes].old = old;
239 if (object && GET_CODE (object) != MEM)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes[num_changes].old_code = INSN_CODE (object);
244 INSN_CODE (object) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn)
265 int icode = recog_memoized (insn);
266 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
268 if (is_asm && ! check_asm_operands (PATTERN (insn)))
270 if (! is_asm && icode < 0)
273 /* After reload, verify that all constraints are satisfied. */
274 if (reload_completed)
278 if (! constrain_operands (1))
285 /* Apply a group of changes previously issued with `validate_change'.
286 Return 1 if all changes are valid, zero otherwise. */
289 apply_change_group ()
293 /* The changes have been applied and all INSN_CODEs have been reset to force
296 The changes are valid if we aren't given an object, or if we are
297 given a MEM and it still is a valid address, or if this is in insn
298 and it is recognized. In the latter case, if reload has completed,
299 we also require that the operands meet the constraints for
302 for (i = 0; i < num_changes; i++)
304 rtx object = changes[i].object;
309 if (GET_CODE (object) == MEM)
311 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
314 else if (insn_invalid_p (object))
316 rtx pat = PATTERN (object);
318 /* Perhaps we couldn't recognize the insn because there were
319 extra CLOBBERs at the end. If so, try to re-recognize
320 without the last CLOBBER (later iterations will cause each of
321 them to be eliminated, in turn). But don't do this if we
322 have an ASM_OPERAND. */
323 if (GET_CODE (pat) == PARALLEL
324 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
325 && asm_noperands (PATTERN (object)) < 0)
329 if (XVECLEN (pat, 0) == 2)
330 newpat = XVECEXP (pat, 0, 0);
336 = gen_rtx_PARALLEL (VOIDmode,
337 gen_rtvec (XVECLEN (pat, 0) - 1));
338 for (j = 0; j < XVECLEN (newpat, 0); j++)
339 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
342 /* Add a new change to this group to replace the pattern
343 with this new pattern. Then consider this change
344 as having succeeded. The change we added will
345 cause the entire call to fail if things remain invalid.
347 Note that this can lose if a later change than the one
348 we are processing specified &XVECEXP (PATTERN (object), 0, X)
349 but this shouldn't occur. */
351 validate_change (object, &PATTERN (object), newpat, 1);
353 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
354 /* If this insn is a CLOBBER or USE, it is always valid, but is
362 if (i == num_changes)
374 /* Return the number of changes so far in the current group. */
377 num_validated_changes ()
382 /* Retract the changes numbered NUM and up. */
390 /* Back out all the changes. Do this in the opposite order in which
392 for (i = num_changes - 1; i >= num; i--)
394 *changes[i].loc = changes[i].old;
395 if (changes[i].object && GET_CODE (changes[i].object) != MEM)
396 INSN_CODE (changes[i].object) = changes[i].old_code;
401 /* Replace every occurrence of FROM in X with TO. Mark each change with
402 validate_change passing OBJECT. */
405 validate_replace_rtx_1 (loc, from, to, object)
407 rtx from, to, object;
410 register const char *fmt;
411 register rtx x = *loc;
412 enum rtx_code code = GET_CODE (x);
414 /* X matches FROM if it is the same rtx or they are both referring to the
415 same register in the same mode. Avoid calling rtx_equal_p unless the
416 operands look similar. */
419 || (GET_CODE (x) == REG && GET_CODE (from) == REG
420 && GET_MODE (x) == GET_MODE (from)
421 && REGNO (x) == REGNO (from))
422 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
423 && rtx_equal_p (x, from)))
425 validate_change (object, loc, to, 1);
429 /* For commutative or comparison operations, try replacing each argument
430 separately and seeing if we made any changes. If so, put a constant
432 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
434 int prev_changes = num_changes;
436 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
437 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
438 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
440 validate_change (object, loc,
441 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
442 : swap_condition (code),
443 GET_MODE (x), XEXP (x, 1),
451 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
452 done the substitution, otherwise we won't. */
457 /* If we have a PLUS whose second operand is now a CONST_INT, use
458 plus_constant to try to simplify it. */
459 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
460 validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
465 if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
467 validate_change (object, loc,
468 plus_constant (XEXP (x, 0), - INTVAL (to)),
476 /* In these cases, the operation to be performed depends on the mode
477 of the operand. If we are replacing the operand with a VOIDmode
478 constant, we lose the information. So try to simplify the operation
479 in that case. If it fails, substitute in something that we know
480 won't be recognized. */
481 if (GET_MODE (to) == VOIDmode
482 && (XEXP (x, 0) == from
483 || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG
484 && GET_MODE (XEXP (x, 0)) == GET_MODE (from)
485 && REGNO (XEXP (x, 0)) == REGNO (from))))
487 rtx new = simplify_unary_operation (code, GET_MODE (x), to,
490 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
492 validate_change (object, loc, new, 1);
498 /* If we have a SUBREG of a register that we are replacing and we are
499 replacing it with a MEM, make a new MEM and try replacing the
500 SUBREG with it. Don't do this if the MEM has a mode-dependent address
501 or if we would be widening it. */
503 if (SUBREG_REG (x) == from
504 && GET_CODE (from) == REG
505 && GET_CODE (to) == MEM
506 && ! mode_dependent_address_p (XEXP (to, 0))
507 && ! MEM_VOLATILE_P (to)
508 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
510 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
511 enum machine_mode mode = GET_MODE (x);
514 if (BYTES_BIG_ENDIAN)
515 offset += (MIN (UNITS_PER_WORD,
516 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
517 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
519 new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
520 MEM_COPY_ATTRIBUTES (new, to);
521 validate_change (object, loc, new, 1);
528 /* If we are replacing a register with memory, try to change the memory
529 to be the mode required for memory in extract operations (this isn't
530 likely to be an insertion operation; if it was, nothing bad will
531 happen, we might just fail in some cases). */
533 if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM
534 && GET_CODE (XEXP (x, 1)) == CONST_INT
535 && GET_CODE (XEXP (x, 2)) == CONST_INT
536 && ! mode_dependent_address_p (XEXP (to, 0))
537 && ! MEM_VOLATILE_P (to))
539 enum machine_mode wanted_mode = VOIDmode;
540 enum machine_mode is_mode = GET_MODE (to);
541 int pos = INTVAL (XEXP (x, 2));
544 if (code == ZERO_EXTRACT)
546 wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
547 if (wanted_mode == VOIDmode)
548 wanted_mode = word_mode;
552 if (code == SIGN_EXTRACT)
554 wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode;
555 if (wanted_mode == VOIDmode)
556 wanted_mode = word_mode;
560 /* If we have a narrower mode, we can do something. */
561 if (wanted_mode != VOIDmode
562 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
564 int offset = pos / BITS_PER_UNIT;
567 /* If the bytes and bits are counted differently, we
568 must adjust the offset. */
569 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
570 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
573 pos %= GET_MODE_BITSIZE (wanted_mode);
575 newmem = gen_rtx_MEM (wanted_mode,
576 plus_constant (XEXP (to, 0), offset));
577 MEM_COPY_ATTRIBUTES (newmem, to);
579 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
580 validate_change (object, &XEXP (x, 0), newmem, 1);
590 /* For commutative or comparison operations we've already performed
591 replacements. Don't try to perform them again. */
592 if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
594 fmt = GET_RTX_FORMAT (code);
595 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
598 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
599 else if (fmt[i] == 'E')
600 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
601 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
606 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
607 with TO. After all changes have been made, validate by seeing
608 if INSN is still valid. */
611 validate_replace_rtx_subexp (from, to, insn, loc)
612 rtx from, to, insn, *loc;
614 validate_replace_rtx_1 (loc, from, to, insn);
615 return apply_change_group ();
618 /* Try replacing every occurrence of FROM in INSN with TO. After all
619 changes have been made, validate by seeing if INSN is still valid. */
622 validate_replace_rtx (from, to, insn)
625 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
626 return apply_change_group ();
629 /* Try replacing every occurrence of FROM in INSN with TO. After all
630 changes have been made, validate by seeing if INSN is still valid. */
633 validate_replace_rtx_group (from, to, insn)
636 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
639 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
640 SET_DESTs. After all changes have been made, validate by seeing if
641 INSN is still valid. */
644 validate_replace_src (from, to, insn)
647 if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
648 || GET_CODE (PATTERN (insn)) != SET)
651 validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn);
652 if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
653 validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0),
655 return apply_change_group ();
659 /* Return 1 if the insn using CC0 set by INSN does not contain
660 any ordered tests applied to the condition codes.
661 EQ and NE tests do not count. */
664 next_insn_tests_no_inequality (insn)
667 register rtx next = next_cc0_user (insn);
669 /* If there is no next insn, we have to take the conservative choice. */
673 return ((GET_CODE (next) == JUMP_INSN
674 || GET_CODE (next) == INSN
675 || GET_CODE (next) == CALL_INSN)
676 && ! inequality_comparisons_p (PATTERN (next)));
679 #if 0 /* This is useless since the insn that sets the cc's
680 must be followed immediately by the use of them. */
681 /* Return 1 if the CC value set up by INSN is not used. */
684 next_insns_test_no_inequality (insn)
687 register rtx next = NEXT_INSN (insn);
689 for (; next != 0; next = NEXT_INSN (next))
691 if (GET_CODE (next) == CODE_LABEL
692 || GET_CODE (next) == BARRIER)
694 if (GET_CODE (next) == NOTE)
696 if (inequality_comparisons_p (PATTERN (next)))
698 if (sets_cc0_p (PATTERN (next)) == 1)
700 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
708 /* This is used by find_single_use to locate an rtx that contains exactly one
709 use of DEST, which is typically either a REG or CC0. It returns a
710 pointer to the innermost rtx expression containing DEST. Appearances of
711 DEST that are being used to totally replace it are not counted. */
714 find_single_use_1 (dest, loc)
719 enum rtx_code code = GET_CODE (x);
736 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
737 of a REG that occupies all of the REG, the insn uses DEST if
738 it is mentioned in the destination or the source. Otherwise, we
739 need just check the source. */
740 if (GET_CODE (SET_DEST (x)) != CC0
741 && GET_CODE (SET_DEST (x)) != PC
742 && GET_CODE (SET_DEST (x)) != REG
743 && ! (GET_CODE (SET_DEST (x)) == SUBREG
744 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
745 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
746 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
747 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
748 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
751 return find_single_use_1 (dest, &SET_SRC (x));
755 return find_single_use_1 (dest, &XEXP (x, 0));
761 /* If it wasn't one of the common cases above, check each expression and
762 vector of this code. Look for a unique usage of DEST. */
764 fmt = GET_RTX_FORMAT (code);
765 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
769 if (dest == XEXP (x, i)
770 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
771 && REGNO (dest) == REGNO (XEXP (x, i))))
774 this_result = find_single_use_1 (dest, &XEXP (x, i));
777 result = this_result;
778 else if (this_result)
779 /* Duplicate usage. */
782 else if (fmt[i] == 'E')
786 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
788 if (XVECEXP (x, i, j) == dest
789 || (GET_CODE (dest) == REG
790 && GET_CODE (XVECEXP (x, i, j)) == REG
791 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
794 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
797 result = this_result;
798 else if (this_result)
807 /* See if DEST, produced in INSN, is used only a single time in the
808 sequel. If so, return a pointer to the innermost rtx expression in which
811 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
813 This routine will return usually zero either before flow is called (because
814 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
815 note can't be trusted).
817 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
818 care about REG_DEAD notes or LOG_LINKS.
820 Otherwise, we find the single use by finding an insn that has a
821 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
822 only referenced once in that insn, we know that it must be the first
823 and last insn referencing DEST. */
826 find_single_use (dest, insn, ploc)
838 next = NEXT_INSN (insn);
840 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
843 result = find_single_use_1 (dest, &PATTERN (next));
850 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
853 for (next = next_nonnote_insn (insn);
854 next != 0 && GET_CODE (next) != CODE_LABEL;
855 next = next_nonnote_insn (next))
856 if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest))
858 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
859 if (XEXP (link, 0) == insn)
864 result = find_single_use_1 (dest, &PATTERN (next));
874 /* Return 1 if OP is a valid general operand for machine mode MODE.
875 This is either a register reference, a memory reference,
876 or a constant. In the case of a memory reference, the address
877 is checked for general validity for the target machine.
879 Register and memory references must have mode MODE in order to be valid,
880 but some constants have no machine mode and are valid for any mode.
882 If MODE is VOIDmode, OP is checked for validity for whatever mode
885 The main use of this function is as a predicate in match_operand
886 expressions in the machine description.
888 For an explanation of this function's behavior for registers of
889 class NO_REGS, see the comment for `register_operand'. */
892 general_operand (op, mode)
894 enum machine_mode mode;
896 register enum rtx_code code = GET_CODE (op);
897 int mode_altering_drug = 0;
899 if (mode == VOIDmode)
900 mode = GET_MODE (op);
902 /* Don't accept CONST_INT or anything similar
903 if the caller wants something floating. */
904 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
905 && GET_MODE_CLASS (mode) != MODE_INT
906 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
910 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
912 #ifdef LEGITIMATE_PIC_OPERAND_P
913 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
915 && LEGITIMATE_CONSTANT_P (op));
917 /* Except for certain constants with VOIDmode, already checked for,
918 OP's mode must match MODE if MODE specifies a mode. */
920 if (GET_MODE (op) != mode)
925 #ifdef INSN_SCHEDULING
926 /* On machines that have insn scheduling, we want all memory
927 reference to be explicit, so outlaw paradoxical SUBREGs. */
928 if (GET_CODE (SUBREG_REG (op)) == MEM
929 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
933 op = SUBREG_REG (op);
934 code = GET_CODE (op);
936 /* No longer needed, since (SUBREG (MEM...))
937 will load the MEM into a reload reg in the MEM's own mode. */
938 mode_altering_drug = 1;
943 /* A register whose class is NO_REGS is not a general operand. */
944 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
945 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
949 register rtx y = XEXP (op, 0);
951 if (! volatile_ok && MEM_VOLATILE_P (op))
954 if (GET_CODE (y) == ADDRESSOF)
957 /* Use the mem's mode, since it will be reloaded thus. */
958 mode = GET_MODE (op);
959 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
962 /* Pretend this is an operand for now; we'll run force_operand
963 on its replacement in fixup_var_refs_1. */
964 if (code == ADDRESSOF)
970 if (mode_altering_drug)
971 return ! mode_dependent_address_p (XEXP (op, 0));
975 /* Return 1 if OP is a valid memory address for a memory reference
978 The main use of this function is as a predicate in match_operand
979 expressions in the machine description. */
982 address_operand (op, mode)
984 enum machine_mode mode;
986 return memory_address_p (mode, op);
989 /* Return 1 if OP is a register reference of mode MODE.
990 If MODE is VOIDmode, accept a register in any mode.
992 The main use of this function is as a predicate in match_operand
993 expressions in the machine description.
995 As a special exception, registers whose class is NO_REGS are
996 not accepted by `register_operand'. The reason for this change
997 is to allow the representation of special architecture artifacts
998 (such as a condition code register) without extending the rtl
999 definitions. Since registers of class NO_REGS cannot be used
1000 as registers in any case where register classes are examined,
1001 it is most consistent to keep this function from accepting them. */
1004 register_operand (op, mode)
1006 enum machine_mode mode;
1008 if (GET_MODE (op) != mode && mode != VOIDmode)
1011 if (GET_CODE (op) == SUBREG)
1013 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1014 because it is guaranteed to be reloaded into one.
1015 Just make sure the MEM is valid in itself.
1016 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1017 but currently it does result from (SUBREG (REG)...) where the
1018 reg went on the stack.) */
1019 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1020 return general_operand (op, mode);
1022 #ifdef CLASS_CANNOT_CHANGE_MODE
1023 if (GET_CODE (SUBREG_REG (op)) == REG
1024 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
1025 && (TEST_HARD_REG_BIT
1026 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
1027 REGNO (SUBREG_REG (op))))
1028 && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
1029 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
1030 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
1034 op = SUBREG_REG (op);
1037 /* If we have an ADDRESSOF, consider it valid since it will be
1038 converted into something that will not be a MEM. */
1039 if (GET_CODE (op) == ADDRESSOF)
1042 /* We don't consider registers whose class is NO_REGS
1043 to be a register operand. */
1044 return (GET_CODE (op) == REG
1045 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1046 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1049 /* Return 1 for a register in Pmode; ignore the tested mode. */
1052 pmode_register_operand (op, mode)
1054 enum machine_mode mode ATTRIBUTE_UNUSED;
1056 return register_operand (op, Pmode);
1059 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1060 or a hard register. */
1063 scratch_operand (op, mode)
1065 enum machine_mode mode;
1067 if (GET_MODE (op) != mode && mode != VOIDmode)
1070 return (GET_CODE (op) == SCRATCH
1071 || (GET_CODE (op) == REG
1072 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1075 /* Return 1 if OP is a valid immediate operand for mode MODE.
1077 The main use of this function is as a predicate in match_operand
1078 expressions in the machine description. */
1081 immediate_operand (op, mode)
1083 enum machine_mode mode;
1085 /* Don't accept CONST_INT or anything similar
1086 if the caller wants something floating. */
1087 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1088 && GET_MODE_CLASS (mode) != MODE_INT
1089 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1092 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1093 result in 0/1. It seems a safe assumption that this is
1094 in range for everyone. */
1095 if (GET_CODE (op) == CONSTANT_P_RTX)
1098 return (CONSTANT_P (op)
1099 && (GET_MODE (op) == mode || mode == VOIDmode
1100 || GET_MODE (op) == VOIDmode)
1101 #ifdef LEGITIMATE_PIC_OPERAND_P
1102 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1104 && LEGITIMATE_CONSTANT_P (op));
1107 /* Returns 1 if OP is an operand that is a CONST_INT. */
1110 const_int_operand (op, mode)
1112 enum machine_mode mode ATTRIBUTE_UNUSED;
1114 return GET_CODE (op) == CONST_INT;
1117 /* Returns 1 if OP is an operand that is a constant integer or constant
1118 floating-point number. */
1121 const_double_operand (op, mode)
1123 enum machine_mode mode;
1125 /* Don't accept CONST_INT or anything similar
1126 if the caller wants something floating. */
1127 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1128 && GET_MODE_CLASS (mode) != MODE_INT
1129 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1132 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
1133 && (mode == VOIDmode || GET_MODE (op) == mode
1134 || GET_MODE (op) == VOIDmode));
1137 /* Return 1 if OP is a general operand that is not an immediate operand. */
1140 nonimmediate_operand (op, mode)
1142 enum machine_mode mode;
1144 return (general_operand (op, mode) && ! CONSTANT_P (op));
1147 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1150 nonmemory_operand (op, mode)
1152 enum machine_mode mode;
1154 if (CONSTANT_P (op))
1156 /* Don't accept CONST_INT or anything similar
1157 if the caller wants something floating. */
1158 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1159 && GET_MODE_CLASS (mode) != MODE_INT
1160 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1163 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1164 || mode == VOIDmode)
1165 #ifdef LEGITIMATE_PIC_OPERAND_P
1166 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1168 && LEGITIMATE_CONSTANT_P (op));
1171 if (GET_MODE (op) != mode && mode != VOIDmode)
1174 if (GET_CODE (op) == SUBREG)
1176 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1177 because it is guaranteed to be reloaded into one.
1178 Just make sure the MEM is valid in itself.
1179 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1180 but currently it does result from (SUBREG (REG)...) where the
1181 reg went on the stack.) */
1182 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1183 return general_operand (op, mode);
1184 op = SUBREG_REG (op);
1187 /* We don't consider registers whose class is NO_REGS
1188 to be a register operand. */
1189 return (GET_CODE (op) == REG
1190 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1191 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1194 /* Return 1 if OP is a valid operand that stands for pushing a
1195 value of mode MODE onto the stack.
1197 The main use of this function is as a predicate in match_operand
1198 expressions in the machine description. */
1201 push_operand (op, mode)
1203 enum machine_mode mode;
1205 if (GET_CODE (op) != MEM)
1208 if (mode != VOIDmode && GET_MODE (op) != mode)
1213 if (GET_CODE (op) != STACK_PUSH_CODE)
1216 return XEXP (op, 0) == stack_pointer_rtx;
1219 /* Return 1 if OP is a valid operand that stands for popping a
1220 value of mode MODE off the stack.
1222 The main use of this function is as a predicate in match_operand
1223 expressions in the machine description. */
1226 pop_operand (op, mode)
1228 enum machine_mode mode;
1230 if (GET_CODE (op) != MEM)
1233 if (mode != VOIDmode && GET_MODE (op) != mode)
1238 if (GET_CODE (op) != STACK_POP_CODE)
1241 return XEXP (op, 0) == stack_pointer_rtx;
1244 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1247 memory_address_p (mode, addr)
1248 enum machine_mode mode ATTRIBUTE_UNUSED;
1251 if (GET_CODE (addr) == ADDRESSOF)
1254 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1261 /* Return 1 if OP is a valid memory reference with mode MODE,
1262 including a valid address.
1264 The main use of this function is as a predicate in match_operand
1265 expressions in the machine description. */
1268 memory_operand (op, mode)
1270 enum machine_mode mode;
1274 if (! reload_completed)
1275 /* Note that no SUBREG is a memory operand before end of reload pass,
1276 because (SUBREG (MEM...)) forces reloading into a register. */
1277 return GET_CODE (op) == MEM && general_operand (op, mode);
1279 if (mode != VOIDmode && GET_MODE (op) != mode)
1283 if (GET_CODE (inner) == SUBREG)
1284 inner = SUBREG_REG (inner);
1286 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1289 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1290 that is, a memory reference whose address is a general_operand. */
1293 indirect_operand (op, mode)
1295 enum machine_mode mode;
1297 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1298 if (! reload_completed
1299 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1301 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1302 rtx inner = SUBREG_REG (op);
1304 if (BYTES_BIG_ENDIAN)
1305 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1306 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1308 if (mode != VOIDmode && GET_MODE (op) != mode)
1311 /* The only way that we can have a general_operand as the resulting
1312 address is if OFFSET is zero and the address already is an operand
1313 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1316 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1317 || (GET_CODE (XEXP (inner, 0)) == PLUS
1318 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1319 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1320 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1323 return (GET_CODE (op) == MEM
1324 && memory_operand (op, mode)
1325 && general_operand (XEXP (op, 0), Pmode));
1328 /* Return 1 if this is a comparison operator. This allows the use of
1329 MATCH_OPERATOR to recognize all the branch insns. */
1332 comparison_operator (op, mode)
1334 enum machine_mode mode;
1336 return ((mode == VOIDmode || GET_MODE (op) == mode)
1337 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1340 /* If BODY is an insn body that uses ASM_OPERANDS,
1341 return the number of operands (both input and output) in the insn.
1342 Otherwise return -1. */
1345 asm_noperands (body)
1348 if (GET_CODE (body) == ASM_OPERANDS)
1349 /* No output operands: return number of input operands. */
1350 return ASM_OPERANDS_INPUT_LENGTH (body);
1351 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1352 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1353 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1354 else if (GET_CODE (body) == PARALLEL
1355 && GET_CODE (XVECEXP (body, 0, 0)) == SET
1356 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1358 /* Multiple output operands, or 1 output plus some clobbers:
1359 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1363 /* Count backwards through CLOBBERs to determine number of SETs. */
1364 for (i = XVECLEN (body, 0); i > 0; i--)
1366 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1368 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1372 /* N_SETS is now number of output operands. */
1375 /* Verify that all the SETs we have
1376 came from a single original asm_operands insn
1377 (so that invalid combinations are blocked). */
1378 for (i = 0; i < n_sets; i++)
1380 rtx elt = XVECEXP (body, 0, i);
1381 if (GET_CODE (elt) != SET)
1383 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1385 /* If these ASM_OPERANDS rtx's came from different original insns
1386 then they aren't allowed together. */
1387 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1388 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1391 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1394 else if (GET_CODE (body) == PARALLEL
1395 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1397 /* 0 outputs, but some clobbers:
1398 body is [(asm_operands ...) (clobber (reg ...))...]. */
1401 /* Make sure all the other parallel things really are clobbers. */
1402 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1403 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1406 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1412 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1413 copy its operands (both input and output) into the vector OPERANDS,
1414 the locations of the operands within the insn into the vector OPERAND_LOCS,
1415 and the constraints for the operands into CONSTRAINTS.
1416 Write the modes of the operands into MODES.
1417 Return the assembler-template.
1419 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1420 we don't store that info. */
1423 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1427 const char **constraints;
1428 enum machine_mode *modes;
1432 const char *template = 0;
1434 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1436 rtx asmop = SET_SRC (body);
1437 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1439 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1441 for (i = 1; i < noperands; i++)
1444 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1446 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1448 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1450 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1453 /* The output is in the SET.
1454 Its constraint is in the ASM_OPERANDS itself. */
1456 operands[0] = SET_DEST (body);
1458 operand_locs[0] = &SET_DEST (body);
1460 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1462 modes[0] = GET_MODE (SET_DEST (body));
1463 template = ASM_OPERANDS_TEMPLATE (asmop);
1465 else if (GET_CODE (body) == ASM_OPERANDS)
1468 /* No output operands: BODY is (asm_operands ....). */
1470 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1472 /* The input operands are found in the 1st element vector. */
1473 /* Constraints for inputs are in the 2nd element vector. */
1474 for (i = 0; i < noperands; i++)
1477 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1479 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1481 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1483 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1485 template = ASM_OPERANDS_TEMPLATE (asmop);
1487 else if (GET_CODE (body) == PARALLEL
1488 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1490 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1491 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1492 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1493 int nout = 0; /* Does not include CLOBBERs. */
1495 /* At least one output, plus some CLOBBERs. */
1497 /* The outputs are in the SETs.
1498 Their constraints are in the ASM_OPERANDS itself. */
1499 for (i = 0; i < nparallel; i++)
1501 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1502 break; /* Past last SET */
1505 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1507 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1509 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1511 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1515 for (i = 0; i < nin; i++)
1518 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1520 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1522 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1524 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1527 template = ASM_OPERANDS_TEMPLATE (asmop);
1529 else if (GET_CODE (body) == PARALLEL
1530 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1532 /* No outputs, but some CLOBBERs. */
1534 rtx asmop = XVECEXP (body, 0, 0);
1535 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1537 for (i = 0; i < nin; i++)
1540 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1542 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1544 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1546 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1549 template = ASM_OPERANDS_TEMPLATE (asmop);
1555 /* Check if an asm_operand matches it's constraints.
1556 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1559 asm_operand_ok (op, constraint)
1561 const char *constraint;
1565 /* Use constrain_operands after reload. */
1566 if (reload_completed)
1571 switch (*constraint++)
1584 case '0': case '1': case '2': case '3': case '4':
1585 case '5': case '6': case '7': case '8': case '9':
1586 /* For best results, our caller should have given us the
1587 proper matching constraint, but we can't actually fail
1588 the check if they didn't. Indicate that results are
1594 if (address_operand (op, VOIDmode))
1599 case 'V': /* non-offsettable */
1600 if (memory_operand (op, VOIDmode))
1604 case 'o': /* offsettable */
1605 if (offsettable_nonstrict_memref_p (op))
1610 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1611 excepting those that expand_call created. Further, on some
1612 machines which do not have generalized auto inc/dec, an inc/dec
1613 is not a memory_operand.
1615 Match any memory and hope things are resolved after reload. */
1617 if (GET_CODE (op) == MEM
1619 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1620 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1625 if (GET_CODE (op) == MEM
1627 || GET_CODE (XEXP (op, 0)) == PRE_INC
1628 || GET_CODE (XEXP (op, 0)) == POST_INC))
1633 #ifndef REAL_ARITHMETIC
1634 /* Match any floating double constant, but only if
1635 we can examine the bits of it reliably. */
1636 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1637 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1638 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1644 if (GET_CODE (op) == CONST_DOUBLE)
1649 if (GET_CODE (op) == CONST_DOUBLE
1650 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
1654 if (GET_CODE (op) == CONST_DOUBLE
1655 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
1660 if (GET_CODE (op) == CONST_INT
1661 || (GET_CODE (op) == CONST_DOUBLE
1662 && GET_MODE (op) == VOIDmode))
1668 #ifdef LEGITIMATE_PIC_OPERAND_P
1669 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1676 if (GET_CODE (op) == CONST_INT
1677 || (GET_CODE (op) == CONST_DOUBLE
1678 && GET_MODE (op) == VOIDmode))
1683 if (GET_CODE (op) == CONST_INT
1684 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
1688 if (GET_CODE (op) == CONST_INT
1689 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
1693 if (GET_CODE (op) == CONST_INT
1694 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
1698 if (GET_CODE (op) == CONST_INT
1699 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
1703 if (GET_CODE (op) == CONST_INT
1704 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
1708 if (GET_CODE (op) == CONST_INT
1709 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
1713 if (GET_CODE (op) == CONST_INT
1714 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
1718 if (GET_CODE (op) == CONST_INT
1719 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
1727 if (general_operand (op, VOIDmode))
1731 #ifdef EXTRA_CONSTRAINT
1733 if (EXTRA_CONSTRAINT (op, 'Q'))
1737 if (EXTRA_CONSTRAINT (op, 'R'))
1741 if (EXTRA_CONSTRAINT (op, 'S'))
1745 if (EXTRA_CONSTRAINT (op, 'T'))
1749 if (EXTRA_CONSTRAINT (op, 'U'))
1756 if (GET_MODE (op) == BLKmode)
1758 if (register_operand (op, VOIDmode))
1767 /* Given an rtx *P, if it is a sum containing an integer constant term,
1768 return the location (type rtx *) of the pointer to that constant term.
1769 Otherwise, return a null pointer. */
1772 find_constant_term_loc (p)
1776 register enum rtx_code code = GET_CODE (*p);
1778 /* If *P IS such a constant term, P is its location. */
1780 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1784 /* Otherwise, if not a sum, it has no constant term. */
1786 if (GET_CODE (*p) != PLUS)
1789 /* If one of the summands is constant, return its location. */
1791 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1792 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1795 /* Otherwise, check each summand for containing a constant term. */
1797 if (XEXP (*p, 0) != 0)
1799 tem = find_constant_term_loc (&XEXP (*p, 0));
1804 if (XEXP (*p, 1) != 0)
1806 tem = find_constant_term_loc (&XEXP (*p, 1));
1814 /* Return 1 if OP is a memory reference
1815 whose address contains no side effects
1816 and remains valid after the addition
1817 of a positive integer less than the
1818 size of the object being referenced.
1820 We assume that the original address is valid and do not check it.
1822 This uses strict_memory_address_p as a subroutine, so
1823 don't use it before reload. */
1826 offsettable_memref_p (op)
1829 return ((GET_CODE (op) == MEM)
1830 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1833 /* Similar, but don't require a strictly valid mem ref:
1834 consider pseudo-regs valid as index or base regs. */
1837 offsettable_nonstrict_memref_p (op)
1840 return ((GET_CODE (op) == MEM)
1841 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1844 /* Return 1 if Y is a memory address which contains no side effects
1845 and would remain valid after the addition of a positive integer
1846 less than the size of that mode.
1848 We assume that the original address is valid and do not check it.
1849 We do check that it is valid for narrower modes.
1851 If STRICTP is nonzero, we require a strictly valid address,
1852 for the sake of use in reload.c. */
1855 offsettable_address_p (strictp, mode, y)
1857 enum machine_mode mode;
1860 register enum rtx_code ycode = GET_CODE (y);
1864 int (*addressp) PARAMS ((enum machine_mode, rtx)) =
1865 (strictp ? strict_memory_address_p : memory_address_p);
1866 unsigned int mode_sz = GET_MODE_SIZE (mode);
1868 if (CONSTANT_ADDRESS_P (y))
1871 /* Adjusting an offsettable address involves changing to a narrower mode.
1872 Make sure that's OK. */
1874 if (mode_dependent_address_p (y))
1877 /* ??? How much offset does an offsettable BLKmode reference need?
1878 Clearly that depends on the situation in which it's being used.
1879 However, the current situation in which we test 0xffffffff is
1880 less than ideal. Caveat user. */
1882 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1884 /* If the expression contains a constant term,
1885 see if it remains valid when max possible offset is added. */
1887 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1892 *y2 = plus_constant (*y2, mode_sz - 1);
1893 /* Use QImode because an odd displacement may be automatically invalid
1894 for any wider mode. But it should be valid for a single byte. */
1895 good = (*addressp) (QImode, y);
1897 /* In any case, restore old contents of memory. */
1902 if (GET_RTX_CLASS (ycode) == 'a')
1905 /* The offset added here is chosen as the maximum offset that
1906 any instruction could need to add when operating on something
1907 of the specified mode. We assume that if Y and Y+c are
1908 valid addresses then so is Y+d for all 0<d<c. */
1910 z = plus_constant_for_output (y, mode_sz - 1);
1912 /* Use QImode because an odd displacement may be automatically invalid
1913 for any wider mode. But it should be valid for a single byte. */
1914 return (*addressp) (QImode, z);
1917 /* Return 1 if ADDR is an address-expression whose effect depends
1918 on the mode of the memory reference it is used in.
1920 Autoincrement addressing is a typical example of mode-dependence
1921 because the amount of the increment depends on the mode. */
1924 mode_dependent_address_p (addr)
1925 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1927 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1929 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1930 win: ATTRIBUTE_UNUSED_LABEL
1934 /* Return 1 if OP is a general operand
1935 other than a memory ref with a mode dependent address. */
1938 mode_independent_operand (op, mode)
1939 enum machine_mode mode;
1944 if (! general_operand (op, mode))
1947 if (GET_CODE (op) != MEM)
1950 addr = XEXP (op, 0);
1951 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
1953 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1954 lose: ATTRIBUTE_UNUSED_LABEL
1958 /* Given an operand OP that is a valid memory reference which
1959 satisfies offsettable_memref_p, return a new memory reference whose
1960 address has been adjusted by OFFSET. OFFSET should be positive and
1961 less than the size of the object referenced. */
1964 adj_offsettable_operand (op, offset)
1968 register enum rtx_code code = GET_CODE (op);
1972 register rtx y = XEXP (op, 0);
1975 if (CONSTANT_ADDRESS_P (y))
1977 new = gen_rtx_MEM (GET_MODE (op),
1978 plus_constant_for_output (y, offset));
1979 MEM_COPY_ATTRIBUTES (new, op);
1983 if (GET_CODE (y) == PLUS)
1986 register rtx *const_loc;
1990 const_loc = find_constant_term_loc (&z);
1993 *const_loc = plus_constant_for_output (*const_loc, offset);
1998 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
1999 MEM_COPY_ATTRIBUTES (new, op);
2005 /* Analyze INSN and fill in recog_data. */
2014 rtx body = PATTERN (insn);
2016 recog_data.n_operands = 0;
2017 recog_data.n_alternatives = 0;
2018 recog_data.n_dups = 0;
2020 switch (GET_CODE (body))
2032 recog_data.n_operands = noperands = asm_noperands (body);
2035 /* This insn is an `asm' with operands. */
2037 /* expand_asm_operands makes sure there aren't too many operands. */
2038 if (noperands > MAX_RECOG_OPERANDS)
2041 /* Now get the operand values and constraints out of the insn. */
2042 decode_asm_operands (body, recog_data.operand,
2043 recog_data.operand_loc,
2044 recog_data.constraints,
2045 recog_data.operand_mode);
2048 const char *p = recog_data.constraints[0];
2049 recog_data.n_alternatives = 1;
2051 recog_data.n_alternatives += (*p++ == ',');
2059 /* Ordinary insn: recognize it, get the operands via insn_extract
2060 and get the constraints. */
2062 icode = recog_memoized (insn);
2064 fatal_insn_not_found (insn);
2066 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2067 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2068 recog_data.n_dups = insn_data[icode].n_dups;
2070 insn_extract (insn);
2072 for (i = 0; i < noperands; i++)
2074 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2075 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2078 for (i = 0; i < noperands; i++)
2079 recog_data.operand_type[i]
2080 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2081 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2084 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
2088 /* After calling extract_insn, you can use this function to extract some
2089 information from the constraint strings into a more usable form.
2090 The collected data is stored in recog_op_alt. */
2092 preprocess_constraints ()
2096 memset (recog_op_alt, 0, sizeof recog_op_alt);
2097 for (i = 0; i < recog_data.n_operands; i++)
2100 struct operand_alternative *op_alt;
2101 const char *p = recog_data.constraints[i];
2103 op_alt = recog_op_alt[i];
2105 for (j = 0; j < recog_data.n_alternatives; j++)
2107 op_alt[j].class = NO_REGS;
2108 op_alt[j].constraint = p;
2109 op_alt[j].matches = -1;
2110 op_alt[j].matched = -1;
2112 if (*p == '\0' || *p == ',')
2114 op_alt[j].anything_ok = 1;
2124 while (c != ',' && c != '\0');
2125 if (c == ',' || c == '\0')
2130 case '=': case '+': case '*': case '%':
2131 case 'E': case 'F': case 'G': case 'H':
2132 case 's': case 'i': case 'n':
2133 case 'I': case 'J': case 'K': case 'L':
2134 case 'M': case 'N': case 'O': case 'P':
2135 #ifdef EXTRA_CONSTRAINT
2136 case 'Q': case 'R': case 'S': case 'T': case 'U':
2138 /* These don't say anything we care about. */
2142 op_alt[j].reject += 6;
2145 op_alt[j].reject += 600;
2148 op_alt[j].earlyclobber = 1;
2151 case '0': case '1': case '2': case '3': case '4':
2152 case '5': case '6': case '7': case '8': case '9':
2153 op_alt[j].matches = c - '0';
2154 recog_op_alt[op_alt[j].matches][j].matched = i;
2158 op_alt[j].memory_ok = 1;
2161 op_alt[j].decmem_ok = 1;
2164 op_alt[j].incmem_ok = 1;
2167 op_alt[j].nonoffmem_ok = 1;
2170 op_alt[j].offmem_ok = 1;
2173 op_alt[j].anything_ok = 1;
2177 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS];
2181 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
2185 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
2193 /* Check the operands of an insn against the insn's operand constraints
2194 and return 1 if they are valid.
2195 The information about the insn's operands, constraints, operand modes
2196 etc. is obtained from the global variables set up by extract_insn.
2198 WHICH_ALTERNATIVE is set to a number which indicates which
2199 alternative of constraints was matched: 0 for the first alternative,
2200 1 for the next, etc.
2202 In addition, when two operands are match
2203 and it happens that the output operand is (reg) while the
2204 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2205 make the output operand look like the input.
2206 This is because the output operand is the one the template will print.
2208 This is used in final, just before printing the assembler code and by
2209 the routines that determine an insn's attribute.
2211 If STRICT is a positive non-zero value, it means that we have been
2212 called after reload has been completed. In that case, we must
2213 do all checks strictly. If it is zero, it means that we have been called
2214 before reload has completed. In that case, we first try to see if we can
2215 find an alternative that matches strictly. If not, we try again, this
2216 time assuming that reload will fix up the insn. This provides a "best
2217 guess" for the alternative and is used to compute attributes of insns prior
2218 to reload. A negative value of STRICT is used for this internal call. */
2226 constrain_operands (strict)
2229 const char *constraints[MAX_RECOG_OPERANDS];
2230 int matching_operands[MAX_RECOG_OPERANDS];
2231 int earlyclobber[MAX_RECOG_OPERANDS];
2234 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2235 int funny_match_index;
2237 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2240 for (c = 0; c < recog_data.n_operands; c++)
2242 constraints[c] = recog_data.constraints[c];
2243 matching_operands[c] = -1;
2246 which_alternative = 0;
2248 while (which_alternative < recog_data.n_alternatives)
2252 funny_match_index = 0;
2254 for (opno = 0; opno < recog_data.n_operands; opno++)
2256 register rtx op = recog_data.operand[opno];
2257 enum machine_mode mode = GET_MODE (op);
2258 register const char *p = constraints[opno];
2263 earlyclobber[opno] = 0;
2265 /* A unary operator may be accepted by the predicate, but it
2266 is irrelevant for matching constraints. */
2267 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
2270 if (GET_CODE (op) == SUBREG)
2272 if (GET_CODE (SUBREG_REG (op)) == REG
2273 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2274 offset = SUBREG_WORD (op);
2275 op = SUBREG_REG (op);
2278 /* An empty constraint or empty alternative
2279 allows anything which matched the pattern. */
2280 if (*p == 0 || *p == ',')
2283 while (*p && (c = *p++) != ',')
2286 case '?': case '!': case '*': case '%':
2291 /* Ignore rest of this alternative as far as
2292 constraint checking is concerned. */
2293 while (*p && *p != ',')
2298 earlyclobber[opno] = 1;
2301 case '0': case '1': case '2': case '3': case '4':
2302 case '5': case '6': case '7': case '8': case '9':
2304 /* This operand must be the same as a previous one.
2305 This kind of constraint is used for instructions such
2306 as add when they take only two operands.
2308 Note that the lower-numbered operand is passed first.
2310 If we are not testing strictly, assume that this constraint
2311 will be satisfied. */
2316 rtx op1 = recog_data.operand[c - '0'];
2317 rtx op2 = recog_data.operand[opno];
2319 /* A unary operator may be accepted by the predicate,
2320 but it is irrelevant for matching constraints. */
2321 if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
2322 op1 = XEXP (op1, 0);
2323 if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
2324 op2 = XEXP (op2, 0);
2326 val = operands_match_p (op1, op2);
2329 matching_operands[opno] = c - '0';
2330 matching_operands[c - '0'] = opno;
2334 /* If output is *x and input is *--x,
2335 arrange later to change the output to *--x as well,
2336 since the output op is the one that will be printed. */
2337 if (val == 2 && strict > 0)
2339 funny_match[funny_match_index].this = opno;
2340 funny_match[funny_match_index++].other = c - '0';
2345 /* p is used for address_operands. When we are called by
2346 gen_reload, no one will have checked that the address is
2347 strictly valid, i.e., that all pseudos requiring hard regs
2348 have gotten them. */
2350 || (strict_memory_address_p (recog_data.operand_mode[opno],
2355 /* No need to check general_operand again;
2356 it was done in insn-recog.c. */
2358 /* Anything goes unless it is a REG and really has a hard reg
2359 but the hard reg is not in the class GENERAL_REGS. */
2361 || GENERAL_REGS == ALL_REGS
2362 || GET_CODE (op) != REG
2363 || (reload_in_progress
2364 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2365 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2372 && GET_CODE (op) == REG
2373 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2374 || (strict == 0 && GET_CODE (op) == SCRATCH)
2375 || (GET_CODE (op) == REG
2376 && ((GENERAL_REGS == ALL_REGS
2377 && REGNO (op) < FIRST_PSEUDO_REGISTER)
2378 || reg_fits_class_p (op, GENERAL_REGS,
2384 /* This is used for a MATCH_SCRATCH in the cases when
2385 we don't actually need anything. So anything goes
2391 if (GET_CODE (op) == MEM
2392 /* Before reload, accept what reload can turn into mem. */
2393 || (strict < 0 && CONSTANT_P (op))
2394 /* During reload, accept a pseudo */
2395 || (reload_in_progress && GET_CODE (op) == REG
2396 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2401 if (GET_CODE (op) == MEM
2402 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2403 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2408 if (GET_CODE (op) == MEM
2409 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2410 || GET_CODE (XEXP (op, 0)) == POST_INC))
2415 #ifndef REAL_ARITHMETIC
2416 /* Match any CONST_DOUBLE, but only if
2417 we can examine the bits of it reliably. */
2418 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2419 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2420 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
2423 if (GET_CODE (op) == CONST_DOUBLE)
2428 if (GET_CODE (op) == CONST_DOUBLE)
2434 if (GET_CODE (op) == CONST_DOUBLE
2435 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
2440 if (GET_CODE (op) == CONST_INT
2441 || (GET_CODE (op) == CONST_DOUBLE
2442 && GET_MODE (op) == VOIDmode))
2445 if (CONSTANT_P (op))
2450 if (GET_CODE (op) == CONST_INT
2451 || (GET_CODE (op) == CONST_DOUBLE
2452 && GET_MODE (op) == VOIDmode))
2464 if (GET_CODE (op) == CONST_INT
2465 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
2469 #ifdef EXTRA_CONSTRAINT
2475 if (EXTRA_CONSTRAINT (op, c))
2481 if (GET_CODE (op) == MEM
2482 && ((strict > 0 && ! offsettable_memref_p (op))
2484 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
2485 || (reload_in_progress
2486 && !(GET_CODE (op) == REG
2487 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2492 if ((strict > 0 && offsettable_memref_p (op))
2493 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2494 /* Before reload, accept what reload can handle. */
2496 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
2497 /* During reload, accept a pseudo */
2498 || (reload_in_progress && GET_CODE (op) == REG
2499 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2506 && GET_CODE (op) == REG
2507 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2508 || (strict == 0 && GET_CODE (op) == SCRATCH)
2509 || (GET_CODE (op) == REG
2510 && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c),
2515 constraints[opno] = p;
2516 /* If this operand did not win somehow,
2517 this alternative loses. */
2521 /* This alternative won; the operands are ok.
2522 Change whichever operands this alternative says to change. */
2527 /* See if any earlyclobber operand conflicts with some other
2531 for (eopno = 0; eopno < recog_data.n_operands; eopno++)
2532 /* Ignore earlyclobber operands now in memory,
2533 because we would often report failure when we have
2534 two memory operands, one of which was formerly a REG. */
2535 if (earlyclobber[eopno]
2536 && GET_CODE (recog_data.operand[eopno]) == REG)
2537 for (opno = 0; opno < recog_data.n_operands; opno++)
2538 if ((GET_CODE (recog_data.operand[opno]) == MEM
2539 || recog_data.operand_type[opno] != OP_OUT)
2541 /* Ignore things like match_operator operands. */
2542 && *recog_data.constraints[opno] != 0
2543 && ! (matching_operands[opno] == eopno
2544 && operands_match_p (recog_data.operand[opno],
2545 recog_data.operand[eopno]))
2546 && ! safe_from_earlyclobber (recog_data.operand[opno],
2547 recog_data.operand[eopno]))
2552 while (--funny_match_index >= 0)
2554 recog_data.operand[funny_match[funny_match_index].other]
2555 = recog_data.operand[funny_match[funny_match_index].this];
2562 which_alternative++;
2565 /* If we are about to reject this, but we are not to test strictly,
2566 try a very loose test. Only return failure if it fails also. */
2568 return constrain_operands (-1);
2573 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2574 is a hard reg in class CLASS when its regno is offset by OFFSET
2575 and changed to mode MODE.
2576 If REG occupies multiple hard regs, all of them must be in CLASS. */
2579 reg_fits_class_p (operand, class, offset, mode)
2581 register enum reg_class class;
2583 enum machine_mode mode;
2585 register int regno = REGNO (operand);
2586 if (regno < FIRST_PSEUDO_REGISTER
2587 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2592 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2594 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2603 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2606 split_all_insns (upd_life)
2613 blocks = sbitmap_alloc (n_basic_blocks);
2614 sbitmap_zero (blocks);
2617 for (i = n_basic_blocks - 1; i >= 0; --i)
2619 basic_block bb = BASIC_BLOCK (i);
2622 for (insn = bb->head; insn ; insn = next)
2626 /* Can't use `next_real_insn' because that might go across
2627 CODE_LABELS and short-out basic blocks. */
2628 next = NEXT_INSN (insn);
2629 if (GET_CODE (insn) != INSN)
2632 /* Don't split no-op move insns. These should silently
2633 disappear later in final. Splitting such insns would
2634 break the code that handles REG_NO_CONFLICT blocks. */
2636 else if ((set = single_set (insn)) != NULL
2637 && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
2639 /* Nops get in the way while scheduling, so delete them
2640 now if register allocation has already been done. It
2641 is too risky to try to do this before register
2642 allocation, and there are unlikely to be very many
2643 nops then anyways. */
2644 if (reload_completed)
2646 PUT_CODE (insn, NOTE);
2647 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2648 NOTE_SOURCE_FILE (insn) = 0;
2653 /* Split insns here to get max fine-grain parallelism. */
2654 rtx first = PREV_INSN (insn);
2655 rtx last = try_split (PATTERN (insn), insn, 1);
2659 SET_BIT (blocks, i);
2662 /* try_split returns the NOTE that INSN became. */
2663 first = NEXT_INSN (first);
2664 PUT_CODE (insn, NOTE);
2665 NOTE_SOURCE_FILE (insn) = 0;
2666 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2668 if (insn == bb->end)
2676 if (insn == bb->end)
2680 /* ??? When we're called from just after reload, the CFG is in bad
2681 shape, and we may have fallen off the end. This could be fixed
2682 by having reload not try to delete unreachable code. Otherwise
2683 assert we found the end insn. */
2684 if (insn == NULL && upd_life)
2688 if (changed && upd_life)
2690 compute_bb_for_insn (get_max_uid ());
2691 count_or_remove_death_notes (blocks, 1);
2692 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
2695 sbitmap_free (blocks);
2698 #ifdef HAVE_peephole2
2699 struct peep2_insn_data
2705 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2706 static int peep2_current;
2708 /* A non-insn marker indicating the last insn of the block.
2709 The live_before regset for this element is correct, indicating
2710 global_live_at_end for the block. */
2711 #define PEEP2_EOB pc_rtx
2713 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2714 does not exist. Used by the recognizer to find the next insn to match
2715 in a multi-insn pattern. */
2721 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2725 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2726 n -= MAX_INSNS_PER_PEEP2 + 1;
2728 if (peep2_insn_data[n].insn == PEEP2_EOB)
2730 return peep2_insn_data[n].insn;
2733 /* Return true if REGNO is dead before the Nth non-note insn
2737 peep2_regno_dead_p (ofs, regno)
2741 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2744 ofs += peep2_current;
2745 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2746 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2748 if (peep2_insn_data[ofs].insn == NULL_RTX)
2751 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2754 /* Similarly for a REG. */
2757 peep2_reg_dead_p (ofs, reg)
2763 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2766 ofs += peep2_current;
2767 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2768 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2770 if (peep2_insn_data[ofs].insn == NULL_RTX)
2773 regno = REGNO (reg);
2774 n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2776 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2781 /* Try to find a hard register of mode MODE, matching the register class in
2782 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2783 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2784 in which case the only condition is that the register must be available
2785 before CURRENT_INSN.
2786 Registers that already have bits set in REG_SET will not be considered.
2788 If an appropriate register is available, it will be returned and the
2789 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2793 peep2_find_free_register (from, to, class_str, mode, reg_set)
2795 const char *class_str;
2796 enum machine_mode mode;
2797 HARD_REG_SET *reg_set;
2799 static int search_ofs;
2800 enum reg_class class;
2804 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1)
2807 from += peep2_current;
2808 if (from >= MAX_INSNS_PER_PEEP2 + 1)
2809 from -= MAX_INSNS_PER_PEEP2 + 1;
2810 to += peep2_current;
2811 if (to >= MAX_INSNS_PER_PEEP2 + 1)
2812 to -= MAX_INSNS_PER_PEEP2 + 1;
2814 if (peep2_insn_data[from].insn == NULL_RTX)
2816 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
2820 HARD_REG_SET this_live;
2822 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
2824 if (peep2_insn_data[from].insn == NULL_RTX)
2826 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
2827 IOR_HARD_REG_SET (live, this_live);
2830 class = (class_str[0] == 'r' ? GENERAL_REGS
2831 : REG_CLASS_FROM_LETTER (class_str[0]));
2833 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2835 int raw_regno, regno, success, j;
2837 /* Distribute the free registers as much as possible. */
2838 raw_regno = search_ofs + i;
2839 if (raw_regno >= FIRST_PSEUDO_REGISTER)
2840 raw_regno -= FIRST_PSEUDO_REGISTER;
2841 #ifdef REG_ALLOC_ORDER
2842 regno = reg_alloc_order[raw_regno];
2847 /* Don't allocate fixed registers. */
2848 if (fixed_regs[regno])
2850 /* Make sure the register is of the right class. */
2851 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno))
2853 /* And can support the mode we need. */
2854 if (! HARD_REGNO_MODE_OK (regno, mode))
2856 /* And that we don't create an extra save/restore. */
2857 if (! call_used_regs[regno] && ! regs_ever_live[regno])
2859 /* And we don't clobber traceback for noreturn functions. */
2860 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
2861 && (! reload_completed || frame_pointer_needed))
2865 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2867 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
2868 || TEST_HARD_REG_BIT (live, regno + j))
2876 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2877 SET_HARD_REG_BIT (*reg_set, regno + j);
2879 /* Start the next search with the next register. */
2880 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
2882 search_ofs = raw_regno;
2884 return gen_rtx_REG (mode, regno);
2892 /* Perform the peephole2 optimization pass. */
2895 peephole2_optimize (dump_file)
2896 FILE *dump_file ATTRIBUTE_UNUSED;
2898 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
2902 #ifdef HAVE_conditional_execution
2907 /* Initialize the regsets we're going to use. */
2908 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
2909 peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]);
2910 live = INITIALIZE_REG_SET (rs_heads[i]);
2912 #ifdef HAVE_conditional_execution
2913 blocks = sbitmap_alloc (n_basic_blocks);
2914 sbitmap_zero (blocks);
2917 count_or_remove_death_notes (NULL, 1);
2920 for (b = n_basic_blocks - 1; b >= 0; --b)
2922 basic_block bb = BASIC_BLOCK (b);
2923 struct propagate_block_info *pbi;
2925 /* Indicate that all slots except the last holds invalid data. */
2926 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
2927 peep2_insn_data[i].insn = NULL_RTX;
2929 /* Indicate that the last slot contains live_after data. */
2930 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
2931 peep2_current = MAX_INSNS_PER_PEEP2;
2933 /* Start up propagation. */
2934 COPY_REG_SET (live, bb->global_live_at_end);
2935 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
2937 #ifdef HAVE_conditional_execution
2938 pbi = init_propagate_block_info (bb, live, NULL, 0);
2940 pbi = init_propagate_block_info (bb, live, NULL, PROP_DEATH_NOTES);
2943 for (insn = bb->end; ; insn = prev)
2945 prev = PREV_INSN (insn);
2951 /* Record this insn. */
2952 if (--peep2_current < 0)
2953 peep2_current = MAX_INSNS_PER_PEEP2;
2954 peep2_insn_data[peep2_current].insn = insn;
2955 propagate_one_insn (pbi, insn);
2956 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
2958 /* Match the peephole. */
2959 try = peephole2_insns (PATTERN (insn), insn, &match_len);
2962 i = match_len + peep2_current;
2963 if (i >= MAX_INSNS_PER_PEEP2 + 1)
2964 i -= MAX_INSNS_PER_PEEP2 + 1;
2966 /* Replace the old sequence with the new. */
2967 flow_delete_insn_chain (insn, peep2_insn_data[i].insn);
2968 try = emit_insn_after (try, prev);
2970 /* Adjust the basic block boundaries. */
2971 if (peep2_insn_data[i].insn == bb->end)
2973 if (insn == bb->head)
2974 bb->head = NEXT_INSN (prev);
2976 #ifdef HAVE_conditional_execution
2977 /* With conditional execution, we cannot back up the
2978 live information so easily, since the conditional
2979 death data structures are not so self-contained.
2980 So record that we've made a modification to this
2981 block and update life information at the end. */
2982 SET_BIT (blocks, b);
2985 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
2986 peep2_insn_data[i].insn = NULL_RTX;
2987 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
2989 /* Back up lifetime information past the end of the
2990 newly created sequence. */
2991 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
2993 COPY_REG_SET (live, peep2_insn_data[i].live_before);
2995 /* Update life information for the new sequence. */
3001 i = MAX_INSNS_PER_PEEP2;
3002 peep2_insn_data[i].insn = try;
3003 propagate_one_insn (pbi, try);
3004 COPY_REG_SET (peep2_insn_data[i].live_before, live);
3006 try = PREV_INSN (try);
3008 while (try != prev);
3010 /* ??? Should verify that LIVE now matches what we
3011 had before the new sequence. */
3018 if (insn == bb->head)
3022 free_propagate_block_info (pbi);
3025 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3026 FREE_REG_SET (peep2_insn_data[i].live_before);
3027 FREE_REG_SET (live);
3029 #ifdef HAVE_conditional_execution
3030 count_or_remove_death_notes (blocks, 1);
3031 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
3032 sbitmap_free (blocks);
3035 #endif /* HAVE_peephole2 */