1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
34 #include "addresses.h"
40 #include "basic-block.h"
45 #include "tree-pass.h"
48 #ifndef STACK_PUSH_CODE
49 #ifdef STACK_GROWS_DOWNWARD
50 #define STACK_PUSH_CODE PRE_DEC
52 #define STACK_PUSH_CODE PRE_INC
56 #ifndef STACK_POP_CODE
57 #ifdef STACK_GROWS_DOWNWARD
58 #define STACK_POP_CODE POST_INC
60 #define STACK_POP_CODE POST_DEC
64 #ifndef HAVE_ATTR_enabled
66 get_attr_enabled (rtx insn ATTRIBUTE_UNUSED)
72 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx, bool);
73 static void validate_replace_src_1 (rtx *, void *);
74 static rtx split_insn (rtx);
76 /* Nonzero means allow operands to be volatile.
77 This should be 0 if you are generating rtl, such as if you are calling
78 the functions in optabs.c and expmed.c (most of the time).
79 This should be 1 if all valid insns need to be recognized,
80 such as in reginfo.c and final.c and reload.c.
82 init_recog and init_recog_no_volatile are responsible for setting this. */
86 struct recog_data recog_data;
88 /* Contains a vector of operand_alternative structures for every operand.
89 Set up by preprocess_constraints. */
90 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
92 /* On return from `constrain_operands', indicate which alternative
95 int which_alternative;
97 /* Nonzero after end of reload pass.
98 Set to 1 or 0 by toplev.c.
99 Controls the significance of (SUBREG (MEM)). */
101 int reload_completed;
103 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
104 int epilogue_completed;
106 /* Initialize data used by the function `recog'.
107 This must be called once in the compilation of a function
108 before any insn recognition may be done in the function. */
111 init_recog_no_volatile (void)
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (rtx x)
131 const char **constraints;
134 /* Post-reload, be more strict with things. */
135 if (reload_completed)
137 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
138 extract_insn (make_insn_raw (x));
139 constrain_operands (1);
140 return which_alternative >= 0;
143 noperands = asm_noperands (x);
149 operands = XALLOCAVEC (rtx, noperands);
150 constraints = XALLOCAVEC (const char *, noperands);
152 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
154 for (i = 0; i < noperands; i++)
156 const char *c = constraints[i];
159 if (! asm_operand_ok (operands[i], c, constraints))
166 /* Static data for the next two routines. */
168 typedef struct change_t
177 static change_t *changes;
178 static int changes_allocated;
180 static int num_changes = 0;
182 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
183 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
184 the change is simply made.
186 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
187 will be called with the address and mode as parameters. If OBJECT is
188 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
191 IN_GROUP is nonzero if this is part of a group of changes that must be
192 performed as a group. In that case, the changes will be stored. The
193 function `apply_change_group' will validate and apply the changes.
195 If IN_GROUP is zero, this is a single change. Try to recognize the insn
196 or validate the memory reference with the change applied. If the result
197 is not valid for the machine, suppress the change and return zero.
198 Otherwise, perform the change and return 1. */
201 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
205 if (old == new_rtx || rtx_equal_p (old, new_rtx))
208 gcc_assert (in_group != 0 || num_changes == 0);
212 /* Save the information describing this change. */
213 if (num_changes >= changes_allocated)
215 if (changes_allocated == 0)
216 /* This value allows for repeated substitutions inside complex
217 indexed addresses, or changes in up to 5 insns. */
218 changes_allocated = MAX_RECOG_OPERANDS * 5;
220 changes_allocated *= 2;
222 changes = XRESIZEVEC (change_t, changes, changes_allocated);
225 changes[num_changes].object = object;
226 changes[num_changes].loc = loc;
227 changes[num_changes].old = old;
228 changes[num_changes].unshare = unshare;
230 if (object && !MEM_P (object))
232 /* Set INSN_CODE to force rerecognition of insn. Save old code in
234 changes[num_changes].old_code = INSN_CODE (object);
235 INSN_CODE (object) = -1;
240 /* If we are making a group of changes, return 1. Otherwise, validate the
241 change group we made. */
246 return apply_change_group ();
249 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
253 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
255 return validate_change_1 (object, loc, new_rtx, in_group, false);
258 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
262 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
264 return validate_change_1 (object, loc, new_rtx, in_group, true);
268 /* Keep X canonicalized if some changes have made it non-canonical; only
269 modifies the operands of X, not (for example) its code. Simplifications
270 are not the job of this routine.
272 Return true if anything was changed. */
274 canonicalize_change_group (rtx insn, rtx x)
276 if (COMMUTATIVE_P (x)
277 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
279 /* Oops, the caller has made X no longer canonical.
280 Let's redo the changes in the correct order. */
281 rtx tem = XEXP (x, 0);
282 validate_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
283 validate_change (insn, &XEXP (x, 1), tem, 1);
291 /* This subroutine of apply_change_group verifies whether the changes to INSN
292 were valid; i.e. whether INSN can still be recognized. */
295 insn_invalid_p (rtx insn)
297 rtx pat = PATTERN (insn);
298 int num_clobbers = 0;
299 /* If we are before reload and the pattern is a SET, see if we can add
301 int icode = recog (pat, insn,
302 (GET_CODE (pat) == SET
303 && ! reload_completed && ! reload_in_progress)
304 ? &num_clobbers : 0);
305 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
308 /* If this is an asm and the operand aren't legal, then fail. Likewise if
309 this is not an asm and the insn wasn't recognized. */
310 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
311 || (!is_asm && icode < 0))
314 /* If we have to add CLOBBERs, fail if we have to add ones that reference
315 hard registers since our callers can't know if they are live or not.
316 Otherwise, add them. */
317 if (num_clobbers > 0)
321 if (added_clobbers_hard_reg_p (icode))
324 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
325 XVECEXP (newpat, 0, 0) = pat;
326 add_clobbers (newpat, icode);
327 PATTERN (insn) = pat = newpat;
330 /* After reload, verify that all constraints are satisfied. */
331 if (reload_completed)
335 if (! constrain_operands (1))
339 INSN_CODE (insn) = icode;
343 /* Return number of changes made and not validated yet. */
345 num_changes_pending (void)
350 /* Tentatively apply the changes numbered NUM and up.
351 Return 1 if all changes are valid, zero otherwise. */
354 verify_changes (int num)
357 rtx last_validated = NULL_RTX;
359 /* The changes have been applied and all INSN_CODEs have been reset to force
362 The changes are valid if we aren't given an object, or if we are
363 given a MEM and it still is a valid address, or if this is in insn
364 and it is recognized. In the latter case, if reload has completed,
365 we also require that the operands meet the constraints for
368 for (i = num; i < num_changes; i++)
370 rtx object = changes[i].object;
372 /* If there is no object to test or if it is the same as the one we
373 already tested, ignore it. */
374 if (object == 0 || object == last_validated)
379 if (! memory_address_addr_space_p (GET_MODE (object),
381 MEM_ADDR_SPACE (object)))
384 else if (REG_P (changes[i].old)
385 && asm_noperands (PATTERN (object)) > 0
386 && REG_EXPR (changes[i].old) != NULL_TREE
387 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
388 && DECL_REGISTER (REG_EXPR (changes[i].old)))
390 /* Don't allow changes of hard register operands to inline
391 assemblies if they have been defined as register asm ("x"). */
394 else if (DEBUG_INSN_P (object))
396 else if (insn_invalid_p (object))
398 rtx pat = PATTERN (object);
400 /* Perhaps we couldn't recognize the insn because there were
401 extra CLOBBERs at the end. If so, try to re-recognize
402 without the last CLOBBER (later iterations will cause each of
403 them to be eliminated, in turn). But don't do this if we
404 have an ASM_OPERAND. */
405 if (GET_CODE (pat) == PARALLEL
406 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
407 && asm_noperands (PATTERN (object)) < 0)
411 if (XVECLEN (pat, 0) == 2)
412 newpat = XVECEXP (pat, 0, 0);
418 = gen_rtx_PARALLEL (VOIDmode,
419 rtvec_alloc (XVECLEN (pat, 0) - 1));
420 for (j = 0; j < XVECLEN (newpat, 0); j++)
421 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
424 /* Add a new change to this group to replace the pattern
425 with this new pattern. Then consider this change
426 as having succeeded. The change we added will
427 cause the entire call to fail if things remain invalid.
429 Note that this can lose if a later change than the one
430 we are processing specified &XVECEXP (PATTERN (object), 0, X)
431 but this shouldn't occur. */
433 validate_change (object, &PATTERN (object), newpat, 1);
436 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
437 || GET_CODE (pat) == VAR_LOCATION)
438 /* If this insn is a CLOBBER or USE, it is always valid, but is
444 last_validated = object;
447 return (i == num_changes);
450 /* A group of changes has previously been issued with validate_change
451 and verified with verify_changes. Call df_insn_rescan for each of
452 the insn changed and clear num_changes. */
455 confirm_change_group (void)
458 rtx last_object = NULL;
460 for (i = 0; i < num_changes; i++)
462 rtx object = changes[i].object;
464 if (changes[i].unshare)
465 *changes[i].loc = copy_rtx (*changes[i].loc);
467 /* Avoid unnecessary rescanning when multiple changes to same instruction
471 if (object != last_object && last_object && INSN_P (last_object))
472 df_insn_rescan (last_object);
473 last_object = object;
477 if (last_object && INSN_P (last_object))
478 df_insn_rescan (last_object);
482 /* Apply a group of changes previously issued with `validate_change'.
483 If all changes are valid, call confirm_change_group and return 1,
484 otherwise, call cancel_changes and return 0. */
487 apply_change_group (void)
489 if (verify_changes (0))
491 confirm_change_group ();
502 /* Return the number of changes so far in the current group. */
505 num_validated_changes (void)
510 /* Retract the changes numbered NUM and up. */
513 cancel_changes (int num)
517 /* Back out all the changes. Do this in the opposite order in which
519 for (i = num_changes - 1; i >= num; i--)
521 *changes[i].loc = changes[i].old;
522 if (changes[i].object && !MEM_P (changes[i].object))
523 INSN_CODE (changes[i].object) = changes[i].old_code;
528 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
532 simplify_while_replacing (rtx *loc, rtx to, rtx object,
533 enum machine_mode op0_mode)
536 enum rtx_code code = GET_CODE (x);
539 if (SWAPPABLE_OPERANDS_P (x)
540 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
542 validate_unshare_change (object, loc,
543 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
544 : swap_condition (code),
545 GET_MODE (x), XEXP (x, 1),
554 /* If we have a PLUS whose second operand is now a CONST_INT, use
555 simplify_gen_binary to try to simplify it.
556 ??? We may want later to remove this, once simplification is
557 separated from this function. */
558 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
559 validate_change (object, loc,
561 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
564 if (CONST_INT_P (XEXP (x, 1))
565 || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE)
566 validate_change (object, loc,
568 (PLUS, GET_MODE (x), XEXP (x, 0),
569 simplify_gen_unary (NEG,
570 GET_MODE (x), XEXP (x, 1),
575 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
577 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
579 /* If any of the above failed, substitute in something that
580 we know won't be recognized. */
582 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
583 validate_change (object, loc, new_rtx, 1);
587 /* All subregs possible to simplify should be simplified. */
588 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
591 /* Subregs of VOIDmode operands are incorrect. */
592 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
593 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
595 validate_change (object, loc, new_rtx, 1);
599 /* If we are replacing a register with memory, try to change the memory
600 to be the mode required for memory in extract operations (this isn't
601 likely to be an insertion operation; if it was, nothing bad will
602 happen, we might just fail in some cases). */
604 if (MEM_P (XEXP (x, 0))
605 && CONST_INT_P (XEXP (x, 1))
606 && CONST_INT_P (XEXP (x, 2))
607 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0))
608 && !MEM_VOLATILE_P (XEXP (x, 0)))
610 enum machine_mode wanted_mode = VOIDmode;
611 enum machine_mode is_mode = GET_MODE (XEXP (x, 0));
612 int pos = INTVAL (XEXP (x, 2));
614 if (GET_CODE (x) == ZERO_EXTRACT)
616 enum machine_mode new_mode
617 = mode_for_extraction (EP_extzv, 1);
618 if (new_mode != MAX_MACHINE_MODE)
619 wanted_mode = new_mode;
621 else if (GET_CODE (x) == SIGN_EXTRACT)
623 enum machine_mode new_mode
624 = mode_for_extraction (EP_extv, 1);
625 if (new_mode != MAX_MACHINE_MODE)
626 wanted_mode = new_mode;
629 /* If we have a narrower mode, we can do something. */
630 if (wanted_mode != VOIDmode
631 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
633 int offset = pos / BITS_PER_UNIT;
636 /* If the bytes and bits are counted differently, we
637 must adjust the offset. */
638 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
640 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
643 pos %= GET_MODE_BITSIZE (wanted_mode);
645 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
647 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
648 validate_change (object, &XEXP (x, 0), newmem, 1);
659 /* Replace every occurrence of FROM in X with TO. Mark each change with
660 validate_change passing OBJECT. */
663 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object,
670 enum machine_mode op0_mode = VOIDmode;
671 int prev_changes = num_changes;
677 fmt = GET_RTX_FORMAT (code);
679 op0_mode = GET_MODE (XEXP (x, 0));
681 /* X matches FROM if it is the same rtx or they are both referring to the
682 same register in the same mode. Avoid calling rtx_equal_p unless the
683 operands look similar. */
686 || (REG_P (x) && REG_P (from)
687 && GET_MODE (x) == GET_MODE (from)
688 && REGNO (x) == REGNO (from))
689 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
690 && rtx_equal_p (x, from)))
692 validate_unshare_change (object, loc, to, 1);
696 /* Call ourself recursively to perform the replacements.
697 We must not replace inside already replaced expression, otherwise we
698 get infinite recursion for replacements like (reg X)->(subreg (reg X))
699 done by regmove, so we must special case shared ASM_OPERANDS. */
701 if (GET_CODE (x) == PARALLEL)
703 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
705 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
706 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
708 /* Verify that operands are really shared. */
709 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
710 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
712 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
713 from, to, object, simplify);
716 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
721 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
724 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
725 else if (fmt[i] == 'E')
726 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
727 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
731 /* If we didn't substitute, there is nothing more to do. */
732 if (num_changes == prev_changes)
735 /* Allow substituted expression to have different mode. This is used by
736 regmove to change mode of pseudo register. */
737 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
738 op0_mode = GET_MODE (XEXP (x, 0));
740 /* Do changes needed to keep rtx consistent. Don't do any other
741 simplifications, as it is not our job. */
743 simplify_while_replacing (loc, to, object, op0_mode);
746 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
747 with TO. After all changes have been made, validate by seeing
748 if INSN is still valid. */
751 validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc)
753 validate_replace_rtx_1 (loc, from, to, insn, true);
754 return apply_change_group ();
757 /* Try replacing every occurrence of FROM in INSN with TO. After all
758 changes have been made, validate by seeing if INSN is still valid. */
761 validate_replace_rtx (rtx from, rtx to, rtx insn)
763 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
764 return apply_change_group ();
767 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
768 is a part of INSN. After all changes have been made, validate by seeing if
770 validate_replace_rtx (from, to, insn) is equivalent to
771 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
774 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx insn)
776 validate_replace_rtx_1 (where, from, to, insn, true);
777 return apply_change_group ();
780 /* Same as above, but do not simplify rtx afterwards. */
782 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
785 validate_replace_rtx_1 (where, from, to, insn, false);
786 return apply_change_group ();
790 /* Try replacing every occurrence of FROM in INSN with TO. This also
791 will replace in REG_EQUAL and REG_EQUIV notes. */
794 validate_replace_rtx_group (rtx from, rtx to, rtx insn)
797 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
798 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
799 if (REG_NOTE_KIND (note) == REG_EQUAL
800 || REG_NOTE_KIND (note) == REG_EQUIV)
801 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true);
804 /* Function called by note_uses to replace used subexpressions. */
805 struct validate_replace_src_data
807 rtx from; /* Old RTX */
808 rtx to; /* New RTX */
809 rtx insn; /* Insn in which substitution is occurring. */
813 validate_replace_src_1 (rtx *x, void *data)
815 struct validate_replace_src_data *d
816 = (struct validate_replace_src_data *) data;
818 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
821 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
825 validate_replace_src_group (rtx from, rtx to, rtx insn)
827 struct validate_replace_src_data d;
832 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
835 /* Try simplify INSN.
836 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
837 pattern and return true if something was simplified. */
840 validate_simplify_insn (rtx insn)
846 pat = PATTERN (insn);
848 if (GET_CODE (pat) == SET)
850 newpat = simplify_rtx (SET_SRC (pat));
851 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
852 validate_change (insn, &SET_SRC (pat), newpat, 1);
853 newpat = simplify_rtx (SET_DEST (pat));
854 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
855 validate_change (insn, &SET_DEST (pat), newpat, 1);
857 else if (GET_CODE (pat) == PARALLEL)
858 for (i = 0; i < XVECLEN (pat, 0); i++)
860 rtx s = XVECEXP (pat, 0, i);
862 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
864 newpat = simplify_rtx (SET_SRC (s));
865 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
866 validate_change (insn, &SET_SRC (s), newpat, 1);
867 newpat = simplify_rtx (SET_DEST (s));
868 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
869 validate_change (insn, &SET_DEST (s), newpat, 1);
872 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
876 /* Return 1 if the insn using CC0 set by INSN does not contain
877 any ordered tests applied to the condition codes.
878 EQ and NE tests do not count. */
881 next_insn_tests_no_inequality (rtx insn)
883 rtx next = next_cc0_user (insn);
885 /* If there is no next insn, we have to take the conservative choice. */
889 return (INSN_P (next)
890 && ! inequality_comparisons_p (PATTERN (next)));
894 /* Return 1 if OP is a valid general operand for machine mode MODE.
895 This is either a register reference, a memory reference,
896 or a constant. In the case of a memory reference, the address
897 is checked for general validity for the target machine.
899 Register and memory references must have mode MODE in order to be valid,
900 but some constants have no machine mode and are valid for any mode.
902 If MODE is VOIDmode, OP is checked for validity for whatever mode
905 The main use of this function is as a predicate in match_operand
906 expressions in the machine description.
908 For an explanation of this function's behavior for registers of
909 class NO_REGS, see the comment for `register_operand'. */
912 general_operand (rtx op, enum machine_mode mode)
914 enum rtx_code code = GET_CODE (op);
916 if (mode == VOIDmode)
917 mode = GET_MODE (op);
919 /* Don't accept CONST_INT or anything similar
920 if the caller wants something floating. */
921 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
922 && GET_MODE_CLASS (mode) != MODE_INT
923 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
928 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
932 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
934 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
935 && LEGITIMATE_CONSTANT_P (op));
937 /* Except for certain constants with VOIDmode, already checked for,
938 OP's mode must match MODE if MODE specifies a mode. */
940 if (GET_MODE (op) != mode)
945 rtx sub = SUBREG_REG (op);
947 #ifdef INSN_SCHEDULING
948 /* On machines that have insn scheduling, we want all memory
949 reference to be explicit, so outlaw paradoxical SUBREGs.
950 However, we must allow them after reload so that they can
951 get cleaned up by cleanup_subreg_operands. */
952 if (!reload_completed && MEM_P (sub)
953 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub)))
956 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
957 may result in incorrect reference. We should simplify all valid
958 subregs of MEM anyway. But allow this after reload because we
959 might be called from cleanup_subreg_operands.
961 ??? This is a kludge. */
962 if (!reload_completed && SUBREG_BYTE (op) != 0
966 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
967 create such rtl, and we must reject it. */
968 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
969 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
973 code = GET_CODE (op);
977 /* A register whose class is NO_REGS is not a general operand. */
978 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
979 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
983 rtx y = XEXP (op, 0);
985 if (! volatile_ok && MEM_VOLATILE_P (op))
988 /* Use the mem's mode, since it will be reloaded thus. */
989 if (memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
996 /* Return 1 if OP is a valid memory address for a memory reference
999 The main use of this function is as a predicate in match_operand
1000 expressions in the machine description. */
1003 address_operand (rtx op, enum machine_mode mode)
1005 return memory_address_p (mode, op);
1008 /* Return 1 if OP is a register reference of mode MODE.
1009 If MODE is VOIDmode, accept a register in any mode.
1011 The main use of this function is as a predicate in match_operand
1012 expressions in the machine description.
1014 As a special exception, registers whose class is NO_REGS are
1015 not accepted by `register_operand'. The reason for this change
1016 is to allow the representation of special architecture artifacts
1017 (such as a condition code register) without extending the rtl
1018 definitions. Since registers of class NO_REGS cannot be used
1019 as registers in any case where register classes are examined,
1020 it is most consistent to keep this function from accepting them. */
1023 register_operand (rtx op, enum machine_mode mode)
1025 if (GET_MODE (op) != mode && mode != VOIDmode)
1028 if (GET_CODE (op) == SUBREG)
1030 rtx sub = SUBREG_REG (op);
1032 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1033 because it is guaranteed to be reloaded into one.
1034 Just make sure the MEM is valid in itself.
1035 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1036 but currently it does result from (SUBREG (REG)...) where the
1037 reg went on the stack.) */
1038 if (! reload_completed && MEM_P (sub))
1039 return general_operand (op, mode);
1041 #ifdef CANNOT_CHANGE_MODE_CLASS
1043 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1044 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1045 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1046 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT)
1050 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1051 create such rtl, and we must reject it. */
1052 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1053 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
1059 /* We don't consider registers whose class is NO_REGS
1060 to be a register operand. */
1062 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1063 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1066 /* Return 1 for a register in Pmode; ignore the tested mode. */
1069 pmode_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1071 return register_operand (op, Pmode);
1074 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1075 or a hard register. */
1078 scratch_operand (rtx op, enum machine_mode mode)
1080 if (GET_MODE (op) != mode && mode != VOIDmode)
1083 return (GET_CODE (op) == SCRATCH
1085 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1088 /* Return 1 if OP is a valid immediate operand for mode MODE.
1090 The main use of this function is as a predicate in match_operand
1091 expressions in the machine description. */
1094 immediate_operand (rtx op, enum machine_mode mode)
1096 /* Don't accept CONST_INT or anything similar
1097 if the caller wants something floating. */
1098 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1099 && GET_MODE_CLASS (mode) != MODE_INT
1100 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1103 if (CONST_INT_P (op)
1105 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1108 return (CONSTANT_P (op)
1109 && (GET_MODE (op) == mode || mode == VOIDmode
1110 || GET_MODE (op) == VOIDmode)
1111 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1112 && LEGITIMATE_CONSTANT_P (op));
1115 /* Returns 1 if OP is an operand that is a CONST_INT. */
1118 const_int_operand (rtx op, enum machine_mode mode)
1120 if (!CONST_INT_P (op))
1123 if (mode != VOIDmode
1124 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1130 /* Returns 1 if OP is an operand that is a constant integer or constant
1131 floating-point number. */
1134 const_double_operand (rtx op, enum machine_mode mode)
1136 /* Don't accept CONST_INT or anything similar
1137 if the caller wants something floating. */
1138 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1139 && GET_MODE_CLASS (mode) != MODE_INT
1140 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1143 return ((GET_CODE (op) == CONST_DOUBLE || CONST_INT_P (op))
1144 && (mode == VOIDmode || GET_MODE (op) == mode
1145 || GET_MODE (op) == VOIDmode));
1148 /* Return 1 if OP is a general operand that is not an immediate operand. */
1151 nonimmediate_operand (rtx op, enum machine_mode mode)
1153 return (general_operand (op, mode) && ! CONSTANT_P (op));
1156 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1159 nonmemory_operand (rtx op, enum machine_mode mode)
1161 if (CONSTANT_P (op))
1163 /* Don't accept CONST_INT or anything similar
1164 if the caller wants something floating. */
1165 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1166 && GET_MODE_CLASS (mode) != MODE_INT
1167 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1170 if (CONST_INT_P (op)
1172 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1175 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1176 || mode == VOIDmode)
1177 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1178 && LEGITIMATE_CONSTANT_P (op));
1181 if (GET_MODE (op) != mode && mode != VOIDmode)
1184 if (GET_CODE (op) == SUBREG)
1186 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1187 because it is guaranteed to be reloaded into one.
1188 Just make sure the MEM is valid in itself.
1189 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1190 but currently it does result from (SUBREG (REG)...) where the
1191 reg went on the stack.) */
1192 if (! reload_completed && MEM_P (SUBREG_REG (op)))
1193 return general_operand (op, mode);
1194 op = SUBREG_REG (op);
1197 /* We don't consider registers whose class is NO_REGS
1198 to be a register operand. */
1200 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1201 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1204 /* Return 1 if OP is a valid operand that stands for pushing a
1205 value of mode MODE onto the stack.
1207 The main use of this function is as a predicate in match_operand
1208 expressions in the machine description. */
1211 push_operand (rtx op, enum machine_mode mode)
1213 unsigned int rounded_size = GET_MODE_SIZE (mode);
1215 #ifdef PUSH_ROUNDING
1216 rounded_size = PUSH_ROUNDING (rounded_size);
1222 if (mode != VOIDmode && GET_MODE (op) != mode)
1227 if (rounded_size == GET_MODE_SIZE (mode))
1229 if (GET_CODE (op) != STACK_PUSH_CODE)
1234 if (GET_CODE (op) != PRE_MODIFY
1235 || GET_CODE (XEXP (op, 1)) != PLUS
1236 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1237 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1238 #ifdef STACK_GROWS_DOWNWARD
1239 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size
1241 || INTVAL (XEXP (XEXP (op, 1), 1)) != (int) rounded_size
1247 return XEXP (op, 0) == stack_pointer_rtx;
1250 /* Return 1 if OP is a valid operand that stands for popping a
1251 value of mode MODE off the stack.
1253 The main use of this function is as a predicate in match_operand
1254 expressions in the machine description. */
1257 pop_operand (rtx op, enum machine_mode mode)
1262 if (mode != VOIDmode && GET_MODE (op) != mode)
1267 if (GET_CODE (op) != STACK_POP_CODE)
1270 return XEXP (op, 0) == stack_pointer_rtx;
1273 /* Return 1 if ADDR is a valid memory address
1274 for mode MODE in address space AS. */
1277 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1278 rtx addr, addr_space_t as)
1280 #ifdef GO_IF_LEGITIMATE_ADDRESS
1281 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1282 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1288 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1292 /* Return 1 if OP is a valid memory reference with mode MODE,
1293 including a valid address.
1295 The main use of this function is as a predicate in match_operand
1296 expressions in the machine description. */
1299 memory_operand (rtx op, enum machine_mode mode)
1303 if (! reload_completed)
1304 /* Note that no SUBREG is a memory operand before end of reload pass,
1305 because (SUBREG (MEM...)) forces reloading into a register. */
1306 return MEM_P (op) && general_operand (op, mode);
1308 if (mode != VOIDmode && GET_MODE (op) != mode)
1312 if (GET_CODE (inner) == SUBREG)
1313 inner = SUBREG_REG (inner);
1315 return (MEM_P (inner) && general_operand (op, mode));
1318 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1319 that is, a memory reference whose address is a general_operand. */
1322 indirect_operand (rtx op, enum machine_mode mode)
1324 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1325 if (! reload_completed
1326 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1328 int offset = SUBREG_BYTE (op);
1329 rtx inner = SUBREG_REG (op);
1331 if (mode != VOIDmode && GET_MODE (op) != mode)
1334 /* The only way that we can have a general_operand as the resulting
1335 address is if OFFSET is zero and the address already is an operand
1336 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1339 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1340 || (GET_CODE (XEXP (inner, 0)) == PLUS
1341 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1342 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1343 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1347 && memory_operand (op, mode)
1348 && general_operand (XEXP (op, 0), Pmode));
1351 /* Return 1 if this is an ordered comparison operator (not including
1352 ORDERED and UNORDERED). */
1355 ordered_comparison_operator (rtx op, enum machine_mode mode)
1357 if (mode != VOIDmode && GET_MODE (op) != mode)
1359 switch (GET_CODE (op))
1377 /* Return 1 if this is a comparison operator. This allows the use of
1378 MATCH_OPERATOR to recognize all the branch insns. */
1381 comparison_operator (rtx op, enum machine_mode mode)
1383 return ((mode == VOIDmode || GET_MODE (op) == mode)
1384 && COMPARISON_P (op));
1387 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1390 extract_asm_operands (rtx body)
1393 switch (GET_CODE (body))
1399 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1400 tmp = SET_SRC (body);
1401 if (GET_CODE (tmp) == ASM_OPERANDS)
1406 tmp = XVECEXP (body, 0, 0);
1407 if (GET_CODE (tmp) == ASM_OPERANDS)
1409 if (GET_CODE (tmp) == SET)
1411 tmp = SET_SRC (tmp);
1412 if (GET_CODE (tmp) == ASM_OPERANDS)
1423 /* If BODY is an insn body that uses ASM_OPERANDS,
1424 return the number of operands (both input and output) in the insn.
1425 Otherwise return -1. */
1428 asm_noperands (const_rtx body)
1430 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1436 if (GET_CODE (body) == SET)
1438 else if (GET_CODE (body) == PARALLEL)
1441 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1443 /* Multiple output operands, or 1 output plus some clobbers:
1445 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1446 /* Count backwards through CLOBBERs to determine number of SETs. */
1447 for (i = XVECLEN (body, 0); i > 0; i--)
1449 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1451 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1455 /* N_SETS is now number of output operands. */
1458 /* Verify that all the SETs we have
1459 came from a single original asm_operands insn
1460 (so that invalid combinations are blocked). */
1461 for (i = 0; i < n_sets; i++)
1463 rtx elt = XVECEXP (body, 0, i);
1464 if (GET_CODE (elt) != SET)
1466 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1468 /* If these ASM_OPERANDS rtx's came from different original insns
1469 then they aren't allowed together. */
1470 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1471 != ASM_OPERANDS_INPUT_VEC (asm_op))
1477 /* 0 outputs, but some clobbers:
1478 body is [(asm_operands ...) (clobber (reg ...))...]. */
1479 /* Make sure all the other parallel things really are clobbers. */
1480 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1481 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1486 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1487 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1490 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1491 copy its operands (both input and output) into the vector OPERANDS,
1492 the locations of the operands within the insn into the vector OPERAND_LOCS,
1493 and the constraints for the operands into CONSTRAINTS.
1494 Write the modes of the operands into MODES.
1495 Return the assembler-template.
1497 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1498 we don't store that info. */
1501 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1502 const char **constraints, enum machine_mode *modes,
1505 int nbase = 0, n, i;
1508 switch (GET_CODE (body))
1511 /* Zero output asm: BODY is (asm_operands ...). */
1516 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1517 asmop = SET_SRC (body);
1519 /* The output is in the SET.
1520 Its constraint is in the ASM_OPERANDS itself. */
1522 operands[0] = SET_DEST (body);
1524 operand_locs[0] = &SET_DEST (body);
1526 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1528 modes[0] = GET_MODE (SET_DEST (body));
1534 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1536 asmop = XVECEXP (body, 0, 0);
1537 if (GET_CODE (asmop) == SET)
1539 asmop = SET_SRC (asmop);
1541 /* At least one output, plus some CLOBBERs. The outputs are in
1542 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1543 for (i = 0; i < nparallel; i++)
1545 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1546 break; /* Past last SET */
1548 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1550 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1552 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1554 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1565 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1566 for (i = 0; i < n; i++)
1569 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1571 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1573 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1575 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1579 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1580 for (i = 0; i < n; i++)
1583 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1585 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1587 constraints[nbase + i] = "";
1589 modes[nbase + i] = Pmode;
1593 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1595 return ASM_OPERANDS_TEMPLATE (asmop);
1598 /* Check if an asm_operand matches its constraints.
1599 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1602 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1606 /* Use constrain_operands after reload. */
1607 gcc_assert (!reload_completed);
1609 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1610 many alternatives as required to match the other operands. */
1611 if (*constraint == '\0')
1616 char c = *constraint;
1633 case '0': case '1': case '2': case '3': case '4':
1634 case '5': case '6': case '7': case '8': case '9':
1635 /* If caller provided constraints pointer, look up
1636 the maching constraint. Otherwise, our caller should have
1637 given us the proper matching constraint, but we can't
1638 actually fail the check if they didn't. Indicate that
1639 results are inconclusive. */
1643 unsigned long match;
1645 match = strtoul (constraint, &end, 10);
1647 result = asm_operand_ok (op, constraints[match], NULL);
1648 constraint = (const char *) end;
1654 while (ISDIGIT (*constraint));
1661 if (address_operand (op, VOIDmode))
1665 case TARGET_MEM_CONSTRAINT:
1666 case 'V': /* non-offsettable */
1667 if (memory_operand (op, VOIDmode))
1671 case 'o': /* offsettable */
1672 if (offsettable_nonstrict_memref_p (op))
1677 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1678 excepting those that expand_call created. Further, on some
1679 machines which do not have generalized auto inc/dec, an inc/dec
1680 is not a memory_operand.
1682 Match any memory and hope things are resolved after reload. */
1686 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1687 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1694 || GET_CODE (XEXP (op, 0)) == PRE_INC
1695 || GET_CODE (XEXP (op, 0)) == POST_INC))
1701 if (GET_CODE (op) == CONST_DOUBLE
1702 || (GET_CODE (op) == CONST_VECTOR
1703 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
1708 if (GET_CODE (op) == CONST_DOUBLE
1709 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', constraint))
1713 if (GET_CODE (op) == CONST_DOUBLE
1714 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'H', constraint))
1719 if (CONST_INT_P (op)
1720 || (GET_CODE (op) == CONST_DOUBLE
1721 && GET_MODE (op) == VOIDmode))
1726 if (CONSTANT_P (op) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
1731 if (CONST_INT_P (op)
1732 || (GET_CODE (op) == CONST_DOUBLE
1733 && GET_MODE (op) == VOIDmode))
1738 if (CONST_INT_P (op)
1739 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'I', constraint))
1743 if (CONST_INT_P (op)
1744 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'J', constraint))
1748 if (CONST_INT_P (op)
1749 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'K', constraint))
1753 if (CONST_INT_P (op)
1754 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'L', constraint))
1758 if (CONST_INT_P (op)
1759 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'M', constraint))
1763 if (CONST_INT_P (op)
1764 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'N', constraint))
1768 if (CONST_INT_P (op)
1769 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'O', constraint))
1773 if (CONST_INT_P (op)
1774 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'P', constraint))
1783 if (general_operand (op, VOIDmode))
1788 /* For all other letters, we first check for a register class,
1789 otherwise it is an EXTRA_CONSTRAINT. */
1790 if (REG_CLASS_FROM_CONSTRAINT (c, constraint) != NO_REGS)
1793 if (GET_MODE (op) == BLKmode)
1795 if (register_operand (op, VOIDmode))
1798 #ifdef EXTRA_CONSTRAINT_STR
1799 else if (EXTRA_MEMORY_CONSTRAINT (c, constraint))
1800 /* Every memory operand can be reloaded to fit. */
1801 result = result || memory_operand (op, VOIDmode);
1802 else if (EXTRA_ADDRESS_CONSTRAINT (c, constraint))
1803 /* Every address operand can be reloaded to fit. */
1804 result = result || address_operand (op, VOIDmode);
1805 else if (EXTRA_CONSTRAINT_STR (op, c, constraint))
1810 len = CONSTRAINT_LEN (c, constraint);
1813 while (--len && *constraint);
1821 /* Given an rtx *P, if it is a sum containing an integer constant term,
1822 return the location (type rtx *) of the pointer to that constant term.
1823 Otherwise, return a null pointer. */
1826 find_constant_term_loc (rtx *p)
1829 enum rtx_code code = GET_CODE (*p);
1831 /* If *P IS such a constant term, P is its location. */
1833 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1837 /* Otherwise, if not a sum, it has no constant term. */
1839 if (GET_CODE (*p) != PLUS)
1842 /* If one of the summands is constant, return its location. */
1844 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1845 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1848 /* Otherwise, check each summand for containing a constant term. */
1850 if (XEXP (*p, 0) != 0)
1852 tem = find_constant_term_loc (&XEXP (*p, 0));
1857 if (XEXP (*p, 1) != 0)
1859 tem = find_constant_term_loc (&XEXP (*p, 1));
1867 /* Return 1 if OP is a memory reference
1868 whose address contains no side effects
1869 and remains valid after the addition
1870 of a positive integer less than the
1871 size of the object being referenced.
1873 We assume that the original address is valid and do not check it.
1875 This uses strict_memory_address_p as a subroutine, so
1876 don't use it before reload. */
1879 offsettable_memref_p (rtx op)
1881 return ((MEM_P (op))
1882 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1883 MEM_ADDR_SPACE (op)));
1886 /* Similar, but don't require a strictly valid mem ref:
1887 consider pseudo-regs valid as index or base regs. */
1890 offsettable_nonstrict_memref_p (rtx op)
1892 return ((MEM_P (op))
1893 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1894 MEM_ADDR_SPACE (op)));
1897 /* Return 1 if Y is a memory address which contains no side effects
1898 and would remain valid for address space AS after the addition of
1899 a positive integer less than the size of that mode.
1901 We assume that the original address is valid and do not check it.
1902 We do check that it is valid for narrower modes.
1904 If STRICTP is nonzero, we require a strictly valid address,
1905 for the sake of use in reload.c. */
1908 offsettable_address_addr_space_p (int strictp, enum machine_mode mode, rtx y,
1911 enum rtx_code ycode = GET_CODE (y);
1915 int (*addressp) (enum machine_mode, rtx, addr_space_t) =
1916 (strictp ? strict_memory_address_addr_space_p
1917 : memory_address_addr_space_p);
1918 unsigned int mode_sz = GET_MODE_SIZE (mode);
1920 if (CONSTANT_ADDRESS_P (y))
1923 /* Adjusting an offsettable address involves changing to a narrower mode.
1924 Make sure that's OK. */
1926 if (mode_dependent_address_p (y))
1929 /* ??? How much offset does an offsettable BLKmode reference need?
1930 Clearly that depends on the situation in which it's being used.
1931 However, the current situation in which we test 0xffffffff is
1932 less than ideal. Caveat user. */
1934 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1936 /* If the expression contains a constant term,
1937 see if it remains valid when max possible offset is added. */
1939 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1944 *y2 = plus_constant (*y2, mode_sz - 1);
1945 /* Use QImode because an odd displacement may be automatically invalid
1946 for any wider mode. But it should be valid for a single byte. */
1947 good = (*addressp) (QImode, y, as);
1949 /* In any case, restore old contents of memory. */
1954 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1957 /* The offset added here is chosen as the maximum offset that
1958 any instruction could need to add when operating on something
1959 of the specified mode. We assume that if Y and Y+c are
1960 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1961 go inside a LO_SUM here, so we do so as well. */
1962 if (GET_CODE (y) == LO_SUM
1964 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
1965 z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0),
1966 plus_constant (XEXP (y, 1), mode_sz - 1));
1968 z = plus_constant (y, mode_sz - 1);
1970 /* Use QImode because an odd displacement may be automatically invalid
1971 for any wider mode. But it should be valid for a single byte. */
1972 return (*addressp) (QImode, z, as);
1975 /* Return 1 if ADDR is an address-expression whose effect depends
1976 on the mode of the memory reference it is used in.
1978 Autoincrement addressing is a typical example of mode-dependence
1979 because the amount of the increment depends on the mode. */
1982 mode_dependent_address_p (rtx addr)
1984 /* Auto-increment addressing with anything other than post_modify
1985 or pre_modify always introduces a mode dependency. Catch such
1986 cases now instead of deferring to the target. */
1987 if (GET_CODE (addr) == PRE_INC
1988 || GET_CODE (addr) == POST_INC
1989 || GET_CODE (addr) == PRE_DEC
1990 || GET_CODE (addr) == POST_DEC)
1993 return targetm.mode_dependent_address_p (addr);
1996 /* Like extract_insn, but save insn extracted and don't extract again, when
1997 called again for the same insn expecting that recog_data still contain the
1998 valid information. This is used primary by gen_attr infrastructure that
1999 often does extract insn again and again. */
2001 extract_insn_cached (rtx insn)
2003 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2005 extract_insn (insn);
2006 recog_data.insn = insn;
2009 /* Do cached extract_insn, constrain_operands and complain about failures.
2010 Used by insn_attrtab. */
2012 extract_constrain_insn_cached (rtx insn)
2014 extract_insn_cached (insn);
2015 if (which_alternative == -1
2016 && !constrain_operands (reload_completed))
2017 fatal_insn_not_found (insn);
2020 /* Do cached constrain_operands and complain about failures. */
2022 constrain_operands_cached (int strict)
2024 if (which_alternative == -1)
2025 return constrain_operands (strict);
2030 /* Analyze INSN and fill in recog_data. */
2033 extract_insn (rtx insn)
2038 rtx body = PATTERN (insn);
2040 recog_data.n_operands = 0;
2041 recog_data.n_alternatives = 0;
2042 recog_data.n_dups = 0;
2044 switch (GET_CODE (body))
2055 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2060 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2061 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2062 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2068 recog_data.n_operands = noperands = asm_noperands (body);
2071 /* This insn is an `asm' with operands. */
2073 /* expand_asm_operands makes sure there aren't too many operands. */
2074 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2076 /* Now get the operand values and constraints out of the insn. */
2077 decode_asm_operands (body, recog_data.operand,
2078 recog_data.operand_loc,
2079 recog_data.constraints,
2080 recog_data.operand_mode, NULL);
2081 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2084 const char *p = recog_data.constraints[0];
2085 recog_data.n_alternatives = 1;
2087 recog_data.n_alternatives += (*p++ == ',');
2091 fatal_insn_not_found (insn);
2095 /* Ordinary insn: recognize it, get the operands via insn_extract
2096 and get the constraints. */
2098 icode = recog_memoized (insn);
2100 fatal_insn_not_found (insn);
2102 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2103 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2104 recog_data.n_dups = insn_data[icode].n_dups;
2106 insn_extract (insn);
2108 for (i = 0; i < noperands; i++)
2110 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2111 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2112 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2113 /* VOIDmode match_operands gets mode from their real operand. */
2114 if (recog_data.operand_mode[i] == VOIDmode)
2115 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2118 for (i = 0; i < noperands; i++)
2119 recog_data.operand_type[i]
2120 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2121 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2124 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2126 if (INSN_CODE (insn) < 0)
2127 for (i = 0; i < recog_data.n_alternatives; i++)
2128 recog_data.alternative_enabled_p[i] = true;
2131 recog_data.insn = insn;
2132 for (i = 0; i < recog_data.n_alternatives; i++)
2134 which_alternative = i;
2135 recog_data.alternative_enabled_p[i] = get_attr_enabled (insn);
2139 recog_data.insn = NULL;
2140 which_alternative = -1;
2143 /* After calling extract_insn, you can use this function to extract some
2144 information from the constraint strings into a more usable form.
2145 The collected data is stored in recog_op_alt. */
2147 preprocess_constraints (void)
2151 for (i = 0; i < recog_data.n_operands; i++)
2152 memset (recog_op_alt[i], 0, (recog_data.n_alternatives
2153 * sizeof (struct operand_alternative)));
2155 for (i = 0; i < recog_data.n_operands; i++)
2158 struct operand_alternative *op_alt;
2159 const char *p = recog_data.constraints[i];
2161 op_alt = recog_op_alt[i];
2163 for (j = 0; j < recog_data.n_alternatives; j++)
2165 op_alt[j].cl = NO_REGS;
2166 op_alt[j].constraint = p;
2167 op_alt[j].matches = -1;
2168 op_alt[j].matched = -1;
2170 if (!recog_data.alternative_enabled_p[j])
2172 p = skip_alternative (p);
2176 if (*p == '\0' || *p == ',')
2178 op_alt[j].anything_ok = 1;
2188 while (c != ',' && c != '\0');
2189 if (c == ',' || c == '\0')
2197 case '=': case '+': case '*': case '%':
2198 case 'E': case 'F': case 'G': case 'H':
2199 case 's': case 'i': case 'n':
2200 case 'I': case 'J': case 'K': case 'L':
2201 case 'M': case 'N': case 'O': case 'P':
2202 /* These don't say anything we care about. */
2206 op_alt[j].reject += 6;
2209 op_alt[j].reject += 600;
2212 op_alt[j].earlyclobber = 1;
2215 case '0': case '1': case '2': case '3': case '4':
2216 case '5': case '6': case '7': case '8': case '9':
2219 op_alt[j].matches = strtoul (p, &end, 10);
2220 recog_op_alt[op_alt[j].matches][j].matched = i;
2225 case TARGET_MEM_CONSTRAINT:
2226 op_alt[j].memory_ok = 1;
2229 op_alt[j].decmem_ok = 1;
2232 op_alt[j].incmem_ok = 1;
2235 op_alt[j].nonoffmem_ok = 1;
2238 op_alt[j].offmem_ok = 1;
2241 op_alt[j].anything_ok = 1;
2245 op_alt[j].is_address = 1;
2246 op_alt[j].cl = reg_class_subunion[(int) op_alt[j].cl]
2247 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
2253 reg_class_subunion[(int) op_alt[j].cl][(int) GENERAL_REGS];
2257 if (EXTRA_MEMORY_CONSTRAINT (c, p))
2259 op_alt[j].memory_ok = 1;
2262 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
2264 op_alt[j].is_address = 1;
2266 = (reg_class_subunion
2267 [(int) op_alt[j].cl]
2268 [(int) base_reg_class (VOIDmode, ADDRESS,
2274 = (reg_class_subunion
2275 [(int) op_alt[j].cl]
2276 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
2279 p += CONSTRAINT_LEN (c, p);
2285 /* Check the operands of an insn against the insn's operand constraints
2286 and return 1 if they are valid.
2287 The information about the insn's operands, constraints, operand modes
2288 etc. is obtained from the global variables set up by extract_insn.
2290 WHICH_ALTERNATIVE is set to a number which indicates which
2291 alternative of constraints was matched: 0 for the first alternative,
2292 1 for the next, etc.
2294 In addition, when two operands are required to match
2295 and it happens that the output operand is (reg) while the
2296 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2297 make the output operand look like the input.
2298 This is because the output operand is the one the template will print.
2300 This is used in final, just before printing the assembler code and by
2301 the routines that determine an insn's attribute.
2303 If STRICT is a positive nonzero value, it means that we have been
2304 called after reload has been completed. In that case, we must
2305 do all checks strictly. If it is zero, it means that we have been called
2306 before reload has completed. In that case, we first try to see if we can
2307 find an alternative that matches strictly. If not, we try again, this
2308 time assuming that reload will fix up the insn. This provides a "best
2309 guess" for the alternative and is used to compute attributes of insns prior
2310 to reload. A negative value of STRICT is used for this internal call. */
2318 constrain_operands (int strict)
2320 const char *constraints[MAX_RECOG_OPERANDS];
2321 int matching_operands[MAX_RECOG_OPERANDS];
2322 int earlyclobber[MAX_RECOG_OPERANDS];
2325 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2326 int funny_match_index;
2328 which_alternative = 0;
2329 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2332 for (c = 0; c < recog_data.n_operands; c++)
2334 constraints[c] = recog_data.constraints[c];
2335 matching_operands[c] = -1;
2340 int seen_earlyclobber_at = -1;
2343 funny_match_index = 0;
2345 if (!recog_data.alternative_enabled_p[which_alternative])
2349 for (i = 0; i < recog_data.n_operands; i++)
2350 constraints[i] = skip_alternative (constraints[i]);
2352 which_alternative++;
2356 for (opno = 0; opno < recog_data.n_operands; opno++)
2358 rtx op = recog_data.operand[opno];
2359 enum machine_mode mode = GET_MODE (op);
2360 const char *p = constraints[opno];
2366 earlyclobber[opno] = 0;
2368 /* A unary operator may be accepted by the predicate, but it
2369 is irrelevant for matching constraints. */
2373 if (GET_CODE (op) == SUBREG)
2375 if (REG_P (SUBREG_REG (op))
2376 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2377 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2378 GET_MODE (SUBREG_REG (op)),
2381 op = SUBREG_REG (op);
2384 /* An empty constraint or empty alternative
2385 allows anything which matched the pattern. */
2386 if (*p == 0 || *p == ',')
2390 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2399 case '?': case '!': case '*': case '%':
2404 /* Ignore rest of this alternative as far as
2405 constraint checking is concerned. */
2408 while (*p && *p != ',');
2413 earlyclobber[opno] = 1;
2414 if (seen_earlyclobber_at < 0)
2415 seen_earlyclobber_at = opno;
2418 case '0': case '1': case '2': case '3': case '4':
2419 case '5': case '6': case '7': case '8': case '9':
2421 /* This operand must be the same as a previous one.
2422 This kind of constraint is used for instructions such
2423 as add when they take only two operands.
2425 Note that the lower-numbered operand is passed first.
2427 If we are not testing strictly, assume that this
2428 constraint will be satisfied. */
2433 match = strtoul (p, &end, 10);
2440 rtx op1 = recog_data.operand[match];
2441 rtx op2 = recog_data.operand[opno];
2443 /* A unary operator may be accepted by the predicate,
2444 but it is irrelevant for matching constraints. */
2446 op1 = XEXP (op1, 0);
2448 op2 = XEXP (op2, 0);
2450 val = operands_match_p (op1, op2);
2453 matching_operands[opno] = match;
2454 matching_operands[match] = opno;
2459 /* If output is *x and input is *--x, arrange later
2460 to change the output to *--x as well, since the
2461 output op is the one that will be printed. */
2462 if (val == 2 && strict > 0)
2464 funny_match[funny_match_index].this_op = opno;
2465 funny_match[funny_match_index++].other = match;
2472 /* p is used for address_operands. When we are called by
2473 gen_reload, no one will have checked that the address is
2474 strictly valid, i.e., that all pseudos requiring hard regs
2475 have gotten them. */
2477 || (strict_memory_address_p (recog_data.operand_mode[opno],
2482 /* No need to check general_operand again;
2483 it was done in insn-recog.c. Well, except that reload
2484 doesn't check the validity of its replacements, but
2485 that should only matter when there's a bug. */
2487 /* Anything goes unless it is a REG and really has a hard reg
2488 but the hard reg is not in the class GENERAL_REGS. */
2492 || GENERAL_REGS == ALL_REGS
2493 || (reload_in_progress
2494 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2495 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2498 else if (strict < 0 || general_operand (op, mode))
2503 /* This is used for a MATCH_SCRATCH in the cases when
2504 we don't actually need anything. So anything goes
2509 case TARGET_MEM_CONSTRAINT:
2510 /* Memory operands must be valid, to the extent
2511 required by STRICT. */
2515 && !strict_memory_address_addr_space_p
2516 (GET_MODE (op), XEXP (op, 0),
2517 MEM_ADDR_SPACE (op)))
2520 && !memory_address_addr_space_p
2521 (GET_MODE (op), XEXP (op, 0),
2522 MEM_ADDR_SPACE (op)))
2526 /* Before reload, accept what reload can turn into mem. */
2527 else if (strict < 0 && CONSTANT_P (op))
2529 /* During reload, accept a pseudo */
2530 else if (reload_in_progress && REG_P (op)
2531 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2537 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2538 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2544 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2545 || GET_CODE (XEXP (op, 0)) == POST_INC))
2551 if (GET_CODE (op) == CONST_DOUBLE
2552 || (GET_CODE (op) == CONST_VECTOR
2553 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
2559 if (GET_CODE (op) == CONST_DOUBLE
2560 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
2565 if (CONST_INT_P (op)
2566 || (GET_CODE (op) == CONST_DOUBLE
2567 && GET_MODE (op) == VOIDmode))
2570 if (CONSTANT_P (op))
2575 if (CONST_INT_P (op)
2576 || (GET_CODE (op) == CONST_DOUBLE
2577 && GET_MODE (op) == VOIDmode))
2589 if (CONST_INT_P (op)
2590 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
2596 && ((strict > 0 && ! offsettable_memref_p (op))
2598 && !(CONSTANT_P (op) || MEM_P (op)))
2599 || (reload_in_progress
2601 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2606 if ((strict > 0 && offsettable_memref_p (op))
2607 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2608 /* Before reload, accept what reload can handle. */
2610 && (CONSTANT_P (op) || MEM_P (op)))
2611 /* During reload, accept a pseudo */
2612 || (reload_in_progress && REG_P (op)
2613 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2622 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p));
2628 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2629 || (strict == 0 && GET_CODE (op) == SCRATCH)
2631 && reg_fits_class_p (op, cl, offset, mode)))
2634 #ifdef EXTRA_CONSTRAINT_STR
2635 else if (EXTRA_CONSTRAINT_STR (op, c, p))
2638 else if (EXTRA_MEMORY_CONSTRAINT (c, p)
2639 /* Every memory operand can be reloaded to fit. */
2640 && ((strict < 0 && MEM_P (op))
2641 /* Before reload, accept what reload can turn
2643 || (strict < 0 && CONSTANT_P (op))
2644 /* During reload, accept a pseudo */
2645 || (reload_in_progress && REG_P (op)
2646 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2648 else if (EXTRA_ADDRESS_CONSTRAINT (c, p)
2649 /* Every address operand can be reloaded to fit. */
2656 while (p += len, c);
2658 constraints[opno] = p;
2659 /* If this operand did not win somehow,
2660 this alternative loses. */
2664 /* This alternative won; the operands are ok.
2665 Change whichever operands this alternative says to change. */
2670 /* See if any earlyclobber operand conflicts with some other
2673 if (strict > 0 && seen_earlyclobber_at >= 0)
2674 for (eopno = seen_earlyclobber_at;
2675 eopno < recog_data.n_operands;
2677 /* Ignore earlyclobber operands now in memory,
2678 because we would often report failure when we have
2679 two memory operands, one of which was formerly a REG. */
2680 if (earlyclobber[eopno]
2681 && REG_P (recog_data.operand[eopno]))
2682 for (opno = 0; opno < recog_data.n_operands; opno++)
2683 if ((MEM_P (recog_data.operand[opno])
2684 || recog_data.operand_type[opno] != OP_OUT)
2686 /* Ignore things like match_operator operands. */
2687 && *recog_data.constraints[opno] != 0
2688 && ! (matching_operands[opno] == eopno
2689 && operands_match_p (recog_data.operand[opno],
2690 recog_data.operand[eopno]))
2691 && ! safe_from_earlyclobber (recog_data.operand[opno],
2692 recog_data.operand[eopno]))
2697 while (--funny_match_index >= 0)
2699 recog_data.operand[funny_match[funny_match_index].other]
2700 = recog_data.operand[funny_match[funny_match_index].this_op];
2707 which_alternative++;
2709 while (which_alternative < recog_data.n_alternatives);
2711 which_alternative = -1;
2712 /* If we are about to reject this, but we are not to test strictly,
2713 try a very loose test. Only return failure if it fails also. */
2715 return constrain_operands (-1);
2720 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2721 is a hard reg in class CLASS when its regno is offset by OFFSET
2722 and changed to mode MODE.
2723 If REG occupies multiple hard regs, all of them must be in CLASS. */
2726 reg_fits_class_p (rtx operand, enum reg_class cl, int offset,
2727 enum machine_mode mode)
2729 int regno = REGNO (operand);
2734 return (regno < FIRST_PSEUDO_REGISTER
2735 && in_hard_reg_set_p (reg_class_contents[(int) cl],
2736 mode, regno + offset));
2739 /* Split single instruction. Helper function for split_all_insns and
2740 split_all_insns_noflow. Return last insn in the sequence if successful,
2741 or NULL if unsuccessful. */
2744 split_insn (rtx insn)
2746 /* Split insns here to get max fine-grain parallelism. */
2747 rtx first = PREV_INSN (insn);
2748 rtx last = try_split (PATTERN (insn), insn, 1);
2749 rtx insn_set, last_set, note;
2754 /* If the original instruction was a single set that was known to be
2755 equivalent to a constant, see if we can say the same about the last
2756 instruction in the split sequence. The two instructions must set
2757 the same destination. */
2758 insn_set = single_set (insn);
2761 last_set = single_set (last);
2762 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2764 note = find_reg_equal_equiv_note (insn);
2765 if (note && CONSTANT_P (XEXP (note, 0)))
2766 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2767 else if (CONSTANT_P (SET_SRC (insn_set)))
2768 set_unique_reg_note (last, REG_EQUAL, SET_SRC (insn_set));
2772 /* try_split returns the NOTE that INSN became. */
2773 SET_INSN_DELETED (insn);
2775 /* ??? Coddle to md files that generate subregs in post-reload
2776 splitters instead of computing the proper hard register. */
2777 if (reload_completed && first != last)
2779 first = NEXT_INSN (first);
2783 cleanup_subreg_operands (first);
2786 first = NEXT_INSN (first);
2793 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2796 split_all_insns (void)
2802 blocks = sbitmap_alloc (last_basic_block);
2803 sbitmap_zero (blocks);
2806 FOR_EACH_BB_REVERSE (bb)
2809 bool finish = false;
2811 rtl_profile_for_bb (bb);
2812 for (insn = BB_HEAD (bb); !finish ; insn = next)
2814 /* Can't use `next_real_insn' because that might go across
2815 CODE_LABELS and short-out basic blocks. */
2816 next = NEXT_INSN (insn);
2817 finish = (insn == BB_END (bb));
2820 rtx set = single_set (insn);
2822 /* Don't split no-op move insns. These should silently
2823 disappear later in final. Splitting such insns would
2824 break the code that handles LIBCALL blocks. */
2825 if (set && set_noop_p (set))
2827 /* Nops get in the way while scheduling, so delete them
2828 now if register allocation has already been done. It
2829 is too risky to try to do this before register
2830 allocation, and there are unlikely to be very many
2831 nops then anyways. */
2832 if (reload_completed)
2833 delete_insn_and_edges (insn);
2837 rtx last = split_insn (insn);
2840 /* The split sequence may include barrier, but the
2841 BB boundary we are interested in will be set to
2844 while (BARRIER_P (last))
2845 last = PREV_INSN (last);
2846 SET_BIT (blocks, bb->index);
2854 default_rtl_profile ();
2856 find_many_sub_basic_blocks (blocks);
2858 #ifdef ENABLE_CHECKING
2859 verify_flow_info ();
2862 sbitmap_free (blocks);
2865 /* Same as split_all_insns, but do not expect CFG to be available.
2866 Used by machine dependent reorg passes. */
2869 split_all_insns_noflow (void)
2873 for (insn = get_insns (); insn; insn = next)
2875 next = NEXT_INSN (insn);
2878 /* Don't split no-op move insns. These should silently
2879 disappear later in final. Splitting such insns would
2880 break the code that handles LIBCALL blocks. */
2881 rtx set = single_set (insn);
2882 if (set && set_noop_p (set))
2884 /* Nops get in the way while scheduling, so delete them
2885 now if register allocation has already been done. It
2886 is too risky to try to do this before register
2887 allocation, and there are unlikely to be very many
2890 ??? Should we use delete_insn when the CFG isn't valid? */
2891 if (reload_completed)
2892 delete_insn_and_edges (insn);
2901 #ifdef HAVE_peephole2
2902 struct peep2_insn_data
2908 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2909 static int peep2_current;
2910 /* The number of instructions available to match a peep2. */
2911 int peep2_current_count;
2913 /* A non-insn marker indicating the last insn of the block.
2914 The live_before regset for this element is correct, indicating
2915 DF_LIVE_OUT for the block. */
2916 #define PEEP2_EOB pc_rtx
2918 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2919 does not exist. Used by the recognizer to find the next insn to match
2920 in a multi-insn pattern. */
2923 peep2_next_insn (int n)
2925 gcc_assert (n <= peep2_current_count);
2928 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2929 n -= MAX_INSNS_PER_PEEP2 + 1;
2931 return peep2_insn_data[n].insn;
2934 /* Return true if REGNO is dead before the Nth non-note insn
2938 peep2_regno_dead_p (int ofs, int regno)
2940 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
2942 ofs += peep2_current;
2943 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2944 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2946 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
2948 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2951 /* Similarly for a REG. */
2954 peep2_reg_dead_p (int ofs, rtx reg)
2958 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
2960 ofs += peep2_current;
2961 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2962 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2964 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
2966 regno = REGNO (reg);
2967 n = hard_regno_nregs[regno][GET_MODE (reg)];
2969 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2974 /* Try to find a hard register of mode MODE, matching the register class in
2975 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2976 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2977 in which case the only condition is that the register must be available
2978 before CURRENT_INSN.
2979 Registers that already have bits set in REG_SET will not be considered.
2981 If an appropriate register is available, it will be returned and the
2982 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2986 peep2_find_free_register (int from, int to, const char *class_str,
2987 enum machine_mode mode, HARD_REG_SET *reg_set)
2989 static int search_ofs;
2994 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
2995 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
2997 from += peep2_current;
2998 if (from >= MAX_INSNS_PER_PEEP2 + 1)
2999 from -= MAX_INSNS_PER_PEEP2 + 1;
3000 to += peep2_current;
3001 if (to >= MAX_INSNS_PER_PEEP2 + 1)
3002 to -= MAX_INSNS_PER_PEEP2 + 1;
3004 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3005 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3009 HARD_REG_SET this_live;
3011 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
3013 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3014 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
3015 IOR_HARD_REG_SET (live, this_live);
3018 cl = (class_str[0] == 'r' ? GENERAL_REGS
3019 : REG_CLASS_FROM_CONSTRAINT (class_str[0], class_str));
3021 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3023 int raw_regno, regno, success, j;
3025 /* Distribute the free registers as much as possible. */
3026 raw_regno = search_ofs + i;
3027 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3028 raw_regno -= FIRST_PSEUDO_REGISTER;
3029 #ifdef REG_ALLOC_ORDER
3030 regno = reg_alloc_order[raw_regno];
3035 /* Don't allocate fixed registers. */
3036 if (fixed_regs[regno])
3038 /* Don't allocate global registers. */
3039 if (global_regs[regno])
3041 /* Make sure the register is of the right class. */
3042 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno))
3044 /* And can support the mode we need. */
3045 if (! HARD_REGNO_MODE_OK (regno, mode))
3047 /* And that we don't create an extra save/restore. */
3048 if (! call_used_regs[regno] && ! df_regs_ever_live_p (regno))
3050 if (! targetm.hard_regno_scratch_ok (regno))
3053 /* And we don't clobber traceback for noreturn functions. */
3054 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
3055 && (! reload_completed || frame_pointer_needed))
3059 for (j = hard_regno_nregs[regno][mode] - 1; j >= 0; j--)
3061 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3062 || TEST_HARD_REG_BIT (live, regno + j))
3070 add_to_hard_reg_set (reg_set, mode, regno);
3072 /* Start the next search with the next register. */
3073 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3075 search_ofs = raw_regno;
3077 return gen_rtx_REG (mode, regno);
3085 /* Forget all currently tracked instructions, only remember current
3089 peep2_reinit_state (regset live)
3093 /* Indicate that all slots except the last holds invalid data. */
3094 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3095 peep2_insn_data[i].insn = NULL_RTX;
3096 peep2_current_count = 0;
3098 /* Indicate that the last slot contains live_after data. */
3099 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3100 peep2_current = MAX_INSNS_PER_PEEP2;
3102 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3105 /* Perform the peephole2 optimization pass. */
3108 peephole2_optimize (void)
3114 bool do_cleanup_cfg = false;
3115 bool do_rebuild_jump_labels = false;
3117 df_set_flags (DF_LR_RUN_DCE);
3120 /* Initialize the regsets we're going to use. */
3121 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3122 peep2_insn_data[i].live_before = BITMAP_ALLOC (®_obstack);
3123 live = BITMAP_ALLOC (®_obstack);
3125 FOR_EACH_BB_REVERSE (bb)
3127 rtl_profile_for_bb (bb);
3129 /* Start up propagation. */
3130 bitmap_copy (live, DF_LR_OUT (bb));
3131 df_simulate_initialize_backwards (bb, live);
3132 peep2_reinit_state (live);
3134 for (insn = BB_END (bb); ; insn = prev)
3136 prev = PREV_INSN (insn);
3137 if (NONDEBUG_INSN_P (insn))
3139 rtx attempt, before_try, x;
3142 bool was_call = false;
3144 /* Record this insn. */
3145 if (--peep2_current < 0)
3146 peep2_current = MAX_INSNS_PER_PEEP2;
3147 if (peep2_current_count < MAX_INSNS_PER_PEEP2
3148 && peep2_insn_data[peep2_current].insn == NULL_RTX)
3149 peep2_current_count++;
3150 peep2_insn_data[peep2_current].insn = insn;
3151 df_simulate_one_insn_backwards (bb, insn, live);
3152 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
3154 if (RTX_FRAME_RELATED_P (insn))
3156 /* If an insn has RTX_FRAME_RELATED_P set, peephole
3157 substitution would lose the
3158 REG_FRAME_RELATED_EXPR that is attached. */
3159 peep2_reinit_state (live);
3163 /* Match the peephole. */
3164 attempt = peephole2_insns (PATTERN (insn), insn, &match_len);
3166 if (attempt != NULL)
3168 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3169 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3170 cfg-related call notes. */
3171 for (i = 0; i <= match_len; ++i)
3174 rtx old_insn, new_insn, note;
3176 j = i + peep2_current;
3177 if (j >= MAX_INSNS_PER_PEEP2 + 1)
3178 j -= MAX_INSNS_PER_PEEP2 + 1;
3179 old_insn = peep2_insn_data[j].insn;
3180 if (!CALL_P (old_insn))
3185 while (new_insn != NULL_RTX)
3187 if (CALL_P (new_insn))
3189 new_insn = NEXT_INSN (new_insn);
3192 gcc_assert (new_insn != NULL_RTX);
3194 CALL_INSN_FUNCTION_USAGE (new_insn)
3195 = CALL_INSN_FUNCTION_USAGE (old_insn);
3197 for (note = REG_NOTES (old_insn);
3199 note = XEXP (note, 1))
3200 switch (REG_NOTE_KIND (note))
3204 add_reg_note (new_insn, REG_NOTE_KIND (note),
3208 /* Discard all other reg notes. */
3212 /* Croak if there is another call in the sequence. */
3213 while (++i <= match_len)
3215 j = i + peep2_current;
3216 if (j >= MAX_INSNS_PER_PEEP2 + 1)
3217 j -= MAX_INSNS_PER_PEEP2 + 1;
3218 old_insn = peep2_insn_data[j].insn;
3219 gcc_assert (!CALL_P (old_insn));
3224 i = match_len + peep2_current;
3225 if (i >= MAX_INSNS_PER_PEEP2 + 1)
3226 i -= MAX_INSNS_PER_PEEP2 + 1;
3228 note = find_reg_note (peep2_insn_data[i].insn,
3229 REG_EH_REGION, NULL_RTX);
3231 /* Replace the old sequence with the new. */
3232 attempt = emit_insn_after_setloc (attempt,
3233 peep2_insn_data[i].insn,
3234 INSN_LOCATOR (peep2_insn_data[i].insn));
3235 before_try = PREV_INSN (insn);
3236 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3238 /* Re-insert the EH_REGION notes. */
3239 if (note || (was_call && nonlocal_goto_handler_labels))
3244 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3245 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3249 copy_reg_eh_region_note_backward (note, attempt,
3253 for (x = attempt ; x != before_try ; x = PREV_INSN (x))
3254 if (x != BB_END (bb)
3255 && (can_throw_internal (x)
3256 || can_nonlocal_goto (x)))
3261 nfte = split_block (bb, x);
3262 flags = (eh_edge->flags
3263 & (EDGE_EH | EDGE_ABNORMAL));
3265 flags |= EDGE_ABNORMAL_CALL;
3266 nehe = make_edge (nfte->src, eh_edge->dest,
3269 nehe->probability = eh_edge->probability;
3271 = REG_BR_PROB_BASE - nehe->probability;
3273 do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3278 /* Converting possibly trapping insn to non-trapping is
3279 possible. Zap dummy outgoing edges. */
3280 do_cleanup_cfg |= purge_dead_edges (bb);
3283 if (targetm.have_conditional_execution ())
3285 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3286 peep2_insn_data[i].insn = NULL_RTX;
3287 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
3288 peep2_current_count = 0;
3292 /* Back up lifetime information past the end of the
3293 newly created sequence. */
3294 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
3296 bitmap_copy (live, peep2_insn_data[i].live_before);
3298 /* Update life information for the new sequence. */
3305 i = MAX_INSNS_PER_PEEP2;
3306 if (peep2_current_count < MAX_INSNS_PER_PEEP2
3307 && peep2_insn_data[i].insn == NULL_RTX)
3308 peep2_current_count++;
3309 peep2_insn_data[i].insn = x;
3311 df_simulate_one_insn_backwards (bb, x, live);
3312 bitmap_copy (peep2_insn_data[i].live_before,
3322 /* If we generated a jump instruction, it won't have
3323 JUMP_LABEL set. Recompute after we're done. */
3324 for (x = attempt; x != before_try; x = PREV_INSN (x))
3327 do_rebuild_jump_labels = true;
3333 if (insn == BB_HEAD (bb))
3338 default_rtl_profile ();
3339 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3340 BITMAP_FREE (peep2_insn_data[i].live_before);
3342 if (do_rebuild_jump_labels)
3343 rebuild_jump_labels (get_insns ());
3345 #endif /* HAVE_peephole2 */
3347 /* Common predicates for use with define_bypass. */
3349 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3350 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3351 must be either a single_set or a PARALLEL with SETs inside. */
3354 store_data_bypass_p (rtx out_insn, rtx in_insn)
3356 rtx out_set, in_set;
3357 rtx out_pat, in_pat;
3358 rtx out_exp, in_exp;
3361 in_set = single_set (in_insn);
3364 if (!MEM_P (SET_DEST (in_set)))
3367 out_set = single_set (out_insn);
3370 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
3375 out_pat = PATTERN (out_insn);
3377 if (GET_CODE (out_pat) != PARALLEL)
3380 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3382 out_exp = XVECEXP (out_pat, 0, i);
3384 if (GET_CODE (out_exp) == CLOBBER)
3387 gcc_assert (GET_CODE (out_exp) == SET);
3389 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3396 in_pat = PATTERN (in_insn);
3397 gcc_assert (GET_CODE (in_pat) == PARALLEL);
3399 for (i = 0; i < XVECLEN (in_pat, 0); i++)
3401 in_exp = XVECEXP (in_pat, 0, i);
3403 if (GET_CODE (in_exp) == CLOBBER)
3406 gcc_assert (GET_CODE (in_exp) == SET);
3408 if (!MEM_P (SET_DEST (in_exp)))
3411 out_set = single_set (out_insn);
3414 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_exp)))
3419 out_pat = PATTERN (out_insn);
3420 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3422 for (j = 0; j < XVECLEN (out_pat, 0); j++)
3424 out_exp = XVECEXP (out_pat, 0, j);
3426 if (GET_CODE (out_exp) == CLOBBER)
3429 gcc_assert (GET_CODE (out_exp) == SET);
3431 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_exp)))
3441 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3442 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3443 or multiple set; IN_INSN should be single_set for truth, but for convenience
3444 of insn categorization may be any JUMP or CALL insn. */
3447 if_test_bypass_p (rtx out_insn, rtx in_insn)
3449 rtx out_set, in_set;
3451 in_set = single_set (in_insn);
3454 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3458 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3460 in_set = SET_SRC (in_set);
3462 out_set = single_set (out_insn);
3465 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3466 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3474 out_pat = PATTERN (out_insn);
3475 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3477 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3479 rtx exp = XVECEXP (out_pat, 0, i);
3481 if (GET_CODE (exp) == CLOBBER)
3484 gcc_assert (GET_CODE (exp) == SET);
3486 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3487 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3496 gate_handle_peephole2 (void)
3498 return (optimize > 0 && flag_peephole2);
3502 rest_of_handle_peephole2 (void)
3504 #ifdef HAVE_peephole2
3505 peephole2_optimize ();
3510 struct rtl_opt_pass pass_peephole2 =
3514 "peephole2", /* name */
3515 gate_handle_peephole2, /* gate */
3516 rest_of_handle_peephole2, /* execute */
3519 0, /* static_pass_number */
3520 TV_PEEPHOLE2, /* tv_id */
3521 0, /* properties_required */
3522 0, /* properties_provided */
3523 0, /* properties_destroyed */
3524 0, /* todo_flags_start */
3525 TODO_df_finish | TODO_verify_rtl_sharing |
3526 TODO_dump_func /* todo_flags_finish */
3531 rest_of_handle_split_all_insns (void)
3537 struct rtl_opt_pass pass_split_all_insns =
3541 "split1", /* name */
3543 rest_of_handle_split_all_insns, /* execute */
3546 0, /* static_pass_number */
3547 TV_NONE, /* tv_id */
3548 0, /* properties_required */
3549 0, /* properties_provided */
3550 0, /* properties_destroyed */
3551 0, /* todo_flags_start */
3552 TODO_dump_func /* todo_flags_finish */
3557 rest_of_handle_split_after_reload (void)
3559 /* If optimizing, then go ahead and split insns now. */
3567 struct rtl_opt_pass pass_split_after_reload =
3571 "split2", /* name */
3573 rest_of_handle_split_after_reload, /* execute */
3576 0, /* static_pass_number */
3577 TV_NONE, /* tv_id */
3578 0, /* properties_required */
3579 0, /* properties_provided */
3580 0, /* properties_destroyed */
3581 0, /* todo_flags_start */
3582 TODO_dump_func /* todo_flags_finish */
3587 gate_handle_split_before_regstack (void)
3589 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3590 /* If flow2 creates new instructions which need splitting
3591 and scheduling after reload is not done, they might not be
3592 split until final which doesn't allow splitting
3593 if HAVE_ATTR_length. */
3594 # ifdef INSN_SCHEDULING
3595 return (optimize && !flag_schedule_insns_after_reload);
3605 rest_of_handle_split_before_regstack (void)
3611 struct rtl_opt_pass pass_split_before_regstack =
3615 "split3", /* name */
3616 gate_handle_split_before_regstack, /* gate */
3617 rest_of_handle_split_before_regstack, /* execute */
3620 0, /* static_pass_number */
3621 TV_NONE, /* tv_id */
3622 0, /* properties_required */
3623 0, /* properties_provided */
3624 0, /* properties_destroyed */
3625 0, /* todo_flags_start */
3626 TODO_dump_func /* todo_flags_finish */
3631 gate_handle_split_before_sched2 (void)
3633 #ifdef INSN_SCHEDULING
3634 return optimize > 0 && flag_schedule_insns_after_reload;
3641 rest_of_handle_split_before_sched2 (void)
3643 #ifdef INSN_SCHEDULING
3649 struct rtl_opt_pass pass_split_before_sched2 =
3653 "split4", /* name */
3654 gate_handle_split_before_sched2, /* gate */
3655 rest_of_handle_split_before_sched2, /* execute */
3658 0, /* static_pass_number */
3659 TV_NONE, /* tv_id */
3660 0, /* properties_required */
3661 0, /* properties_provided */
3662 0, /* properties_destroyed */
3663 0, /* todo_flags_start */
3665 TODO_dump_func /* todo_flags_finish */
3669 /* The placement of the splitting that we do for shorten_branches
3670 depends on whether regstack is used by the target or not. */
3672 gate_do_final_split (void)
3674 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3681 struct rtl_opt_pass pass_split_for_shorten_branches =
3685 "split5", /* name */
3686 gate_do_final_split, /* gate */
3687 split_all_insns_noflow, /* execute */
3690 0, /* static_pass_number */
3691 TV_NONE, /* tv_id */
3692 0, /* properties_required */
3693 0, /* properties_provided */
3694 0, /* properties_destroyed */
3695 0, /* todo_flags_start */
3696 TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */