1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "insn-flags.h"
30 #include "insn-codes.h"
31 #include "hard-reg-set.h"
38 #include "basic-block.h"
41 #ifndef STACK_PUSH_CODE
42 #ifdef STACK_GROWS_DOWNWARD
43 #define STACK_PUSH_CODE PRE_DEC
45 #define STACK_PUSH_CODE PRE_INC
49 #ifndef STACK_POP_CODE
50 #ifdef STACK_GROWS_DOWNWARD
51 #define STACK_POP_CODE POST_INC
53 #define STACK_POP_CODE POST_DEC
57 static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
58 static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
59 static rtx *find_constant_term_loc PARAMS ((rtx *));
60 static int insn_invalid_p PARAMS ((rtx));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized_1 (insn)
118 if (INSN_CODE (insn) < 0)
119 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
120 return INSN_CODE (insn);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x)
132 const char **constraints;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x));
140 constrain_operands (1);
141 return which_alternative >= 0;
144 noperands = asm_noperands (x);
150 operands = (rtx *) alloca (noperands * sizeof (rtx));
151 constraints = (const char **) alloca (noperands * sizeof (char *));
153 decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR);
155 for (i = 0; i < noperands; i++)
157 const char *c = constraints[i];
160 if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0')
161 c = constraints[c[0] - '0'];
163 if (! asm_operand_ok (operands[i], c))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t *changes;
181 static int changes_allocated;
183 static int num_changes = 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object, loc, new, in_group)
212 if (old == new || rtx_equal_p (old, new))
215 if (in_group == 0 && num_changes != 0)
220 /* Save the information describing this change. */
221 if (num_changes >= changes_allocated)
223 if (changes_allocated == 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated = MAX_RECOG_OPERANDS * 5;
228 changes_allocated *= 2;
231 (change_t*) xrealloc (changes,
232 sizeof (change_t) * changes_allocated);
235 changes[num_changes].object = object;
236 changes[num_changes].loc = loc;
237 changes[num_changes].old = old;
239 if (object && GET_CODE (object) != MEM)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes[num_changes].old_code = INSN_CODE (object);
244 INSN_CODE (object) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn)
265 int icode = recog_memoized (insn);
266 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
268 if (is_asm && ! check_asm_operands (PATTERN (insn)))
270 if (! is_asm && icode < 0)
273 /* After reload, verify that all constraints are satisfied. */
274 if (reload_completed)
278 if (! constrain_operands (1))
285 /* Apply a group of changes previously issued with `validate_change'.
286 Return 1 if all changes are valid, zero otherwise. */
289 apply_change_group ()
293 /* The changes have been applied and all INSN_CODEs have been reset to force
296 The changes are valid if we aren't given an object, or if we are
297 given a MEM and it still is a valid address, or if this is in insn
298 and it is recognized. In the latter case, if reload has completed,
299 we also require that the operands meet the constraints for
302 for (i = 0; i < num_changes; i++)
304 rtx object = changes[i].object;
309 if (GET_CODE (object) == MEM)
311 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
314 else if (insn_invalid_p (object))
316 rtx pat = PATTERN (object);
318 /* Perhaps we couldn't recognize the insn because there were
319 extra CLOBBERs at the end. If so, try to re-recognize
320 without the last CLOBBER (later iterations will cause each of
321 them to be eliminated, in turn). But don't do this if we
322 have an ASM_OPERAND. */
323 if (GET_CODE (pat) == PARALLEL
324 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
325 && asm_noperands (PATTERN (object)) < 0)
329 if (XVECLEN (pat, 0) == 2)
330 newpat = XVECEXP (pat, 0, 0);
336 = gen_rtx_PARALLEL (VOIDmode,
337 gen_rtvec (XVECLEN (pat, 0) - 1));
338 for (j = 0; j < XVECLEN (newpat, 0); j++)
339 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
342 /* Add a new change to this group to replace the pattern
343 with this new pattern. Then consider this change
344 as having succeeded. The change we added will
345 cause the entire call to fail if things remain invalid.
347 Note that this can lose if a later change than the one
348 we are processing specified &XVECEXP (PATTERN (object), 0, X)
349 but this shouldn't occur. */
351 validate_change (object, &PATTERN (object), newpat, 1);
353 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
354 /* If this insn is a CLOBBER or USE, it is always valid, but is
362 if (i == num_changes)
374 /* Return the number of changes so far in the current group. */
377 num_validated_changes ()
382 /* Retract the changes numbered NUM and up. */
390 /* Back out all the changes. Do this in the opposite order in which
392 for (i = num_changes - 1; i >= num; i--)
394 *changes[i].loc = changes[i].old;
395 if (changes[i].object && GET_CODE (changes[i].object) != MEM)
396 INSN_CODE (changes[i].object) = changes[i].old_code;
401 /* Replace every occurrence of FROM in X with TO. Mark each change with
402 validate_change passing OBJECT. */
405 validate_replace_rtx_1 (loc, from, to, object)
407 rtx from, to, object;
410 register const char *fmt;
411 register rtx x = *loc;
417 /* X matches FROM if it is the same rtx or they are both referring to the
418 same register in the same mode. Avoid calling rtx_equal_p unless the
419 operands look similar. */
422 || (GET_CODE (x) == REG && GET_CODE (from) == REG
423 && GET_MODE (x) == GET_MODE (from)
424 && REGNO (x) == REGNO (from))
425 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
426 && rtx_equal_p (x, from)))
428 validate_change (object, loc, to, 1);
432 /* For commutative or comparison operations, try replacing each argument
433 separately and seeing if we made any changes. If so, put a constant
435 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
437 int prev_changes = num_changes;
439 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
440 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
441 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
443 validate_change (object, loc,
444 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
445 : swap_condition (code),
446 GET_MODE (x), XEXP (x, 1),
454 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
455 done the substitution, otherwise we won't. */
460 /* If we have a PLUS whose second operand is now a CONST_INT, use
461 plus_constant to try to simplify it. */
462 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
463 validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
468 if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
470 validate_change (object, loc,
471 plus_constant (XEXP (x, 0), - INTVAL (to)),
479 /* In these cases, the operation to be performed depends on the mode
480 of the operand. If we are replacing the operand with a VOIDmode
481 constant, we lose the information. So try to simplify the operation
482 in that case. If it fails, substitute in something that we know
483 won't be recognized. */
484 if (GET_MODE (to) == VOIDmode
485 && rtx_equal_p (XEXP (x, 0), from))
487 rtx new = simplify_unary_operation (code, GET_MODE (x), to,
490 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
492 validate_change (object, loc, new, 1);
498 /* In case we are replacing by constant, attempt to simplify it to non-SUBREG
499 expression. We can't do this later, since the information about inner mode
501 if (CONSTANT_P (to) && rtx_equal_p (SUBREG_REG (x), from))
503 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD
504 && GET_MODE_SIZE (GET_MODE (from)) > UNITS_PER_WORD
505 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
507 rtx temp = operand_subword (to, SUBREG_WORD (x),
511 validate_change (object, loc, temp, 1);
515 if (subreg_lowpart_p (x))
517 rtx new = gen_lowpart_if_possible (GET_MODE (x), to);
520 validate_change (object, loc, new, 1);
525 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
526 since we are saying that the high bits don't matter. */
527 if (GET_MODE (to) == VOIDmode
528 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (from)))
530 validate_change (object, loc, to, 1);
535 /* Changing mode twice with SUBREG => just change it once,
536 or not at all if changing back to starting mode. */
537 if (GET_CODE (to) == SUBREG
538 && rtx_equal_p (SUBREG_REG (x), from))
540 if (GET_MODE (x) == GET_MODE (SUBREG_REG (to))
541 && SUBREG_WORD (x) == 0 && SUBREG_WORD (to) == 0)
543 validate_change (object, loc, SUBREG_REG (to), 1);
547 validate_change (object, loc,
548 gen_rtx_SUBREG (GET_MODE (x), SUBREG_REG (to),
549 SUBREG_WORD (x) + SUBREG_WORD (to)), 1);
553 /* If we have a SUBREG of a register that we are replacing and we are
554 replacing it with a MEM, make a new MEM and try replacing the
555 SUBREG with it. Don't do this if the MEM has a mode-dependent address
556 or if we would be widening it. */
558 if (GET_CODE (from) == REG
559 && GET_CODE (to) == MEM
560 && rtx_equal_p (SUBREG_REG (x), from)
561 && ! mode_dependent_address_p (XEXP (to, 0))
562 && ! MEM_VOLATILE_P (to)
563 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
565 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
566 enum machine_mode mode = GET_MODE (x);
569 if (BYTES_BIG_ENDIAN)
570 offset += (MIN (UNITS_PER_WORD,
571 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
572 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
574 new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
575 MEM_COPY_ATTRIBUTES (new, to);
576 validate_change (object, loc, new, 1);
583 /* If we are replacing a register with memory, try to change the memory
584 to be the mode required for memory in extract operations (this isn't
585 likely to be an insertion operation; if it was, nothing bad will
586 happen, we might just fail in some cases). */
588 if (GET_CODE (from) == REG && GET_CODE (to) == MEM
589 && rtx_equal_p (XEXP (x, 0), from)
590 && GET_CODE (XEXP (x, 1)) == CONST_INT
591 && GET_CODE (XEXP (x, 2)) == CONST_INT
592 && ! mode_dependent_address_p (XEXP (to, 0))
593 && ! MEM_VOLATILE_P (to))
595 enum machine_mode wanted_mode = VOIDmode;
596 enum machine_mode is_mode = GET_MODE (to);
597 int pos = INTVAL (XEXP (x, 2));
600 if (code == ZERO_EXTRACT)
602 wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
603 if (wanted_mode == VOIDmode)
604 wanted_mode = word_mode;
608 if (code == SIGN_EXTRACT)
610 wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode;
611 if (wanted_mode == VOIDmode)
612 wanted_mode = word_mode;
616 /* If we have a narrower mode, we can do something. */
617 if (wanted_mode != VOIDmode
618 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
620 int offset = pos / BITS_PER_UNIT;
623 /* If the bytes and bits are counted differently, we
624 must adjust the offset. */
625 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
626 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
629 pos %= GET_MODE_BITSIZE (wanted_mode);
631 newmem = gen_rtx_MEM (wanted_mode,
632 plus_constant (XEXP (to, 0), offset));
633 MEM_COPY_ATTRIBUTES (newmem, to);
635 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
636 validate_change (object, &XEXP (x, 0), newmem, 1);
646 /* For commutative or comparison operations we've already performed
647 replacements. Don't try to perform them again. */
648 if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
650 fmt = GET_RTX_FORMAT (code);
651 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
654 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
655 else if (fmt[i] == 'E')
656 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
657 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
662 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
663 with TO. After all changes have been made, validate by seeing
664 if INSN is still valid. */
667 validate_replace_rtx_subexp (from, to, insn, loc)
668 rtx from, to, insn, *loc;
670 validate_replace_rtx_1 (loc, from, to, insn);
671 return apply_change_group ();
674 /* Try replacing every occurrence of FROM in INSN with TO. After all
675 changes have been made, validate by seeing if INSN is still valid. */
678 validate_replace_rtx (from, to, insn)
681 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
682 return apply_change_group ();
685 /* Try replacing every occurrence of FROM in INSN with TO. After all
686 changes have been made, validate by seeing if INSN is still valid. */
689 validate_replace_rtx_group (from, to, insn)
692 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
695 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
696 SET_DESTs. After all changes have been made, validate by seeing if
697 INSN is still valid. */
700 validate_replace_src (from, to, insn)
703 if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
704 || GET_CODE (PATTERN (insn)) != SET)
707 validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn);
708 if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
709 validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0),
711 return apply_change_group ();
715 /* Return 1 if the insn using CC0 set by INSN does not contain
716 any ordered tests applied to the condition codes.
717 EQ and NE tests do not count. */
720 next_insn_tests_no_inequality (insn)
723 register rtx next = next_cc0_user (insn);
725 /* If there is no next insn, we have to take the conservative choice. */
729 return ((GET_CODE (next) == JUMP_INSN
730 || GET_CODE (next) == INSN
731 || GET_CODE (next) == CALL_INSN)
732 && ! inequality_comparisons_p (PATTERN (next)));
735 #if 0 /* This is useless since the insn that sets the cc's
736 must be followed immediately by the use of them. */
737 /* Return 1 if the CC value set up by INSN is not used. */
740 next_insns_test_no_inequality (insn)
743 register rtx next = NEXT_INSN (insn);
745 for (; next != 0; next = NEXT_INSN (next))
747 if (GET_CODE (next) == CODE_LABEL
748 || GET_CODE (next) == BARRIER)
750 if (GET_CODE (next) == NOTE)
752 if (inequality_comparisons_p (PATTERN (next)))
754 if (sets_cc0_p (PATTERN (next)) == 1)
756 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
764 /* This is used by find_single_use to locate an rtx that contains exactly one
765 use of DEST, which is typically either a REG or CC0. It returns a
766 pointer to the innermost rtx expression containing DEST. Appearances of
767 DEST that are being used to totally replace it are not counted. */
770 find_single_use_1 (dest, loc)
775 enum rtx_code code = GET_CODE (x);
792 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
793 of a REG that occupies all of the REG, the insn uses DEST if
794 it is mentioned in the destination or the source. Otherwise, we
795 need just check the source. */
796 if (GET_CODE (SET_DEST (x)) != CC0
797 && GET_CODE (SET_DEST (x)) != PC
798 && GET_CODE (SET_DEST (x)) != REG
799 && ! (GET_CODE (SET_DEST (x)) == SUBREG
800 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
801 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
802 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
803 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
804 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
807 return find_single_use_1 (dest, &SET_SRC (x));
811 return find_single_use_1 (dest, &XEXP (x, 0));
817 /* If it wasn't one of the common cases above, check each expression and
818 vector of this code. Look for a unique usage of DEST. */
820 fmt = GET_RTX_FORMAT (code);
821 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
825 if (dest == XEXP (x, i)
826 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
827 && REGNO (dest) == REGNO (XEXP (x, i))))
830 this_result = find_single_use_1 (dest, &XEXP (x, i));
833 result = this_result;
834 else if (this_result)
835 /* Duplicate usage. */
838 else if (fmt[i] == 'E')
842 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
844 if (XVECEXP (x, i, j) == dest
845 || (GET_CODE (dest) == REG
846 && GET_CODE (XVECEXP (x, i, j)) == REG
847 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
850 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
853 result = this_result;
854 else if (this_result)
863 /* See if DEST, produced in INSN, is used only a single time in the
864 sequel. If so, return a pointer to the innermost rtx expression in which
867 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
869 This routine will return usually zero either before flow is called (because
870 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
871 note can't be trusted).
873 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
874 care about REG_DEAD notes or LOG_LINKS.
876 Otherwise, we find the single use by finding an insn that has a
877 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
878 only referenced once in that insn, we know that it must be the first
879 and last insn referencing DEST. */
882 find_single_use (dest, insn, ploc)
894 next = NEXT_INSN (insn);
896 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
899 result = find_single_use_1 (dest, &PATTERN (next));
906 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
909 for (next = next_nonnote_insn (insn);
910 next != 0 && GET_CODE (next) != CODE_LABEL;
911 next = next_nonnote_insn (next))
912 if (INSN_P (next) && dead_or_set_p (next, dest))
914 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
915 if (XEXP (link, 0) == insn)
920 result = find_single_use_1 (dest, &PATTERN (next));
930 /* Return 1 if OP is a valid general operand for machine mode MODE.
931 This is either a register reference, a memory reference,
932 or a constant. In the case of a memory reference, the address
933 is checked for general validity for the target machine.
935 Register and memory references must have mode MODE in order to be valid,
936 but some constants have no machine mode and are valid for any mode.
938 If MODE is VOIDmode, OP is checked for validity for whatever mode
941 The main use of this function is as a predicate in match_operand
942 expressions in the machine description.
944 For an explanation of this function's behavior for registers of
945 class NO_REGS, see the comment for `register_operand'. */
948 general_operand (op, mode)
950 enum machine_mode mode;
952 register enum rtx_code code = GET_CODE (op);
953 int mode_altering_drug = 0;
955 if (mode == VOIDmode)
956 mode = GET_MODE (op);
958 /* Don't accept CONST_INT or anything similar
959 if the caller wants something floating. */
960 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
961 && GET_MODE_CLASS (mode) != MODE_INT
962 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
966 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
968 #ifdef LEGITIMATE_PIC_OPERAND_P
969 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
971 && LEGITIMATE_CONSTANT_P (op));
973 /* Except for certain constants with VOIDmode, already checked for,
974 OP's mode must match MODE if MODE specifies a mode. */
976 if (GET_MODE (op) != mode)
981 #ifdef INSN_SCHEDULING
982 /* On machines that have insn scheduling, we want all memory
983 reference to be explicit, so outlaw paradoxical SUBREGs. */
984 if (GET_CODE (SUBREG_REG (op)) == MEM
985 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
989 op = SUBREG_REG (op);
990 code = GET_CODE (op);
992 /* No longer needed, since (SUBREG (MEM...))
993 will load the MEM into a reload reg in the MEM's own mode. */
994 mode_altering_drug = 1;
999 /* A register whose class is NO_REGS is not a general operand. */
1000 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1001 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
1005 register rtx y = XEXP (op, 0);
1007 if (! volatile_ok && MEM_VOLATILE_P (op))
1010 if (GET_CODE (y) == ADDRESSOF)
1013 /* Use the mem's mode, since it will be reloaded thus. */
1014 mode = GET_MODE (op);
1015 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
1018 /* Pretend this is an operand for now; we'll run force_operand
1019 on its replacement in fixup_var_refs_1. */
1020 if (code == ADDRESSOF)
1026 if (mode_altering_drug)
1027 return ! mode_dependent_address_p (XEXP (op, 0));
1031 /* Return 1 if OP is a valid memory address for a memory reference
1034 The main use of this function is as a predicate in match_operand
1035 expressions in the machine description. */
1038 address_operand (op, mode)
1040 enum machine_mode mode;
1042 return memory_address_p (mode, op);
1045 /* Return 1 if OP is a register reference of mode MODE.
1046 If MODE is VOIDmode, accept a register in any mode.
1048 The main use of this function is as a predicate in match_operand
1049 expressions in the machine description.
1051 As a special exception, registers whose class is NO_REGS are
1052 not accepted by `register_operand'. The reason for this change
1053 is to allow the representation of special architecture artifacts
1054 (such as a condition code register) without extending the rtl
1055 definitions. Since registers of class NO_REGS cannot be used
1056 as registers in any case where register classes are examined,
1057 it is most consistent to keep this function from accepting them. */
1060 register_operand (op, mode)
1062 enum machine_mode mode;
1064 if (GET_MODE (op) != mode && mode != VOIDmode)
1067 if (GET_CODE (op) == SUBREG)
1069 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1070 because it is guaranteed to be reloaded into one.
1071 Just make sure the MEM is valid in itself.
1072 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1073 but currently it does result from (SUBREG (REG)...) where the
1074 reg went on the stack.) */
1075 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1076 return general_operand (op, mode);
1078 #ifdef CLASS_CANNOT_CHANGE_MODE
1079 if (GET_CODE (SUBREG_REG (op)) == REG
1080 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
1081 && (TEST_HARD_REG_BIT
1082 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
1083 REGNO (SUBREG_REG (op))))
1084 && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
1085 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
1086 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
1090 op = SUBREG_REG (op);
1093 /* If we have an ADDRESSOF, consider it valid since it will be
1094 converted into something that will not be a MEM. */
1095 if (GET_CODE (op) == ADDRESSOF)
1098 /* We don't consider registers whose class is NO_REGS
1099 to be a register operand. */
1100 return (GET_CODE (op) == REG
1101 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1102 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1105 /* Return 1 for a register in Pmode; ignore the tested mode. */
1108 pmode_register_operand (op, mode)
1110 enum machine_mode mode ATTRIBUTE_UNUSED;
1112 return register_operand (op, Pmode);
1115 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1116 or a hard register. */
1119 scratch_operand (op, mode)
1121 enum machine_mode mode;
1123 if (GET_MODE (op) != mode && mode != VOIDmode)
1126 return (GET_CODE (op) == SCRATCH
1127 || (GET_CODE (op) == REG
1128 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1131 /* Return 1 if OP is a valid immediate operand for mode MODE.
1133 The main use of this function is as a predicate in match_operand
1134 expressions in the machine description. */
1137 immediate_operand (op, mode)
1139 enum machine_mode mode;
1141 /* Don't accept CONST_INT or anything similar
1142 if the caller wants something floating. */
1143 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1144 && GET_MODE_CLASS (mode) != MODE_INT
1145 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1148 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1149 result in 0/1. It seems a safe assumption that this is
1150 in range for everyone. */
1151 if (GET_CODE (op) == CONSTANT_P_RTX)
1154 return (CONSTANT_P (op)
1155 && (GET_MODE (op) == mode || mode == VOIDmode
1156 || GET_MODE (op) == VOIDmode)
1157 #ifdef LEGITIMATE_PIC_OPERAND_P
1158 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1160 && LEGITIMATE_CONSTANT_P (op));
1163 /* Returns 1 if OP is an operand that is a CONST_INT. */
1166 const_int_operand (op, mode)
1168 enum machine_mode mode ATTRIBUTE_UNUSED;
1170 return GET_CODE (op) == CONST_INT;
1173 /* Returns 1 if OP is an operand that is a constant integer or constant
1174 floating-point number. */
1177 const_double_operand (op, mode)
1179 enum machine_mode mode;
1181 /* Don't accept CONST_INT or anything similar
1182 if the caller wants something floating. */
1183 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1184 && GET_MODE_CLASS (mode) != MODE_INT
1185 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1188 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
1189 && (mode == VOIDmode || GET_MODE (op) == mode
1190 || GET_MODE (op) == VOIDmode));
1193 /* Return 1 if OP is a general operand that is not an immediate operand. */
1196 nonimmediate_operand (op, mode)
1198 enum machine_mode mode;
1200 return (general_operand (op, mode) && ! CONSTANT_P (op));
1203 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1206 nonmemory_operand (op, mode)
1208 enum machine_mode mode;
1210 if (CONSTANT_P (op))
1212 /* Don't accept CONST_INT or anything similar
1213 if the caller wants something floating. */
1214 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1215 && GET_MODE_CLASS (mode) != MODE_INT
1216 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1219 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1220 || mode == VOIDmode)
1221 #ifdef LEGITIMATE_PIC_OPERAND_P
1222 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1224 && LEGITIMATE_CONSTANT_P (op));
1227 if (GET_MODE (op) != mode && mode != VOIDmode)
1230 if (GET_CODE (op) == SUBREG)
1232 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1233 because it is guaranteed to be reloaded into one.
1234 Just make sure the MEM is valid in itself.
1235 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1236 but currently it does result from (SUBREG (REG)...) where the
1237 reg went on the stack.) */
1238 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1239 return general_operand (op, mode);
1240 op = SUBREG_REG (op);
1243 /* We don't consider registers whose class is NO_REGS
1244 to be a register operand. */
1245 return (GET_CODE (op) == REG
1246 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1247 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1250 /* Return 1 if OP is a valid operand that stands for pushing a
1251 value of mode MODE onto the stack.
1253 The main use of this function is as a predicate in match_operand
1254 expressions in the machine description. */
1257 push_operand (op, mode)
1259 enum machine_mode mode;
1261 if (GET_CODE (op) != MEM)
1264 if (mode != VOIDmode && GET_MODE (op) != mode)
1269 if (GET_CODE (op) != STACK_PUSH_CODE)
1272 return XEXP (op, 0) == stack_pointer_rtx;
1275 /* Return 1 if OP is a valid operand that stands for popping a
1276 value of mode MODE off the stack.
1278 The main use of this function is as a predicate in match_operand
1279 expressions in the machine description. */
1282 pop_operand (op, mode)
1284 enum machine_mode mode;
1286 if (GET_CODE (op) != MEM)
1289 if (mode != VOIDmode && GET_MODE (op) != mode)
1294 if (GET_CODE (op) != STACK_POP_CODE)
1297 return XEXP (op, 0) == stack_pointer_rtx;
1300 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1303 memory_address_p (mode, addr)
1304 enum machine_mode mode ATTRIBUTE_UNUSED;
1307 if (GET_CODE (addr) == ADDRESSOF)
1310 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1317 /* Return 1 if OP is a valid memory reference with mode MODE,
1318 including a valid address.
1320 The main use of this function is as a predicate in match_operand
1321 expressions in the machine description. */
1324 memory_operand (op, mode)
1326 enum machine_mode mode;
1330 if (! reload_completed)
1331 /* Note that no SUBREG is a memory operand before end of reload pass,
1332 because (SUBREG (MEM...)) forces reloading into a register. */
1333 return GET_CODE (op) == MEM && general_operand (op, mode);
1335 if (mode != VOIDmode && GET_MODE (op) != mode)
1339 if (GET_CODE (inner) == SUBREG)
1340 inner = SUBREG_REG (inner);
1342 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1345 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1346 that is, a memory reference whose address is a general_operand. */
1349 indirect_operand (op, mode)
1351 enum machine_mode mode;
1353 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1354 if (! reload_completed
1355 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1357 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1358 rtx inner = SUBREG_REG (op);
1360 if (BYTES_BIG_ENDIAN)
1361 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1362 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1364 if (mode != VOIDmode && GET_MODE (op) != mode)
1367 /* The only way that we can have a general_operand as the resulting
1368 address is if OFFSET is zero and the address already is an operand
1369 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1372 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1373 || (GET_CODE (XEXP (inner, 0)) == PLUS
1374 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1375 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1376 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1379 return (GET_CODE (op) == MEM
1380 && memory_operand (op, mode)
1381 && general_operand (XEXP (op, 0), Pmode));
1384 /* Return 1 if this is a comparison operator. This allows the use of
1385 MATCH_OPERATOR to recognize all the branch insns. */
1388 comparison_operator (op, mode)
1390 enum machine_mode mode;
1392 return ((mode == VOIDmode || GET_MODE (op) == mode)
1393 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1396 /* If BODY is an insn body that uses ASM_OPERANDS,
1397 return the number of operands (both input and output) in the insn.
1398 Otherwise return -1. */
1401 asm_noperands (body)
1404 switch (GET_CODE (body))
1407 /* No output operands: return number of input operands. */
1408 return ASM_OPERANDS_INPUT_LENGTH (body);
1410 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1411 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1412 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1416 if (GET_CODE (XVECEXP (body, 0, 0)) == SET
1417 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1419 /* Multiple output operands, or 1 output plus some clobbers:
1420 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1424 /* Count backwards through CLOBBERs to determine number of SETs. */
1425 for (i = XVECLEN (body, 0); i > 0; i--)
1427 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1429 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1433 /* N_SETS is now number of output operands. */
1436 /* Verify that all the SETs we have
1437 came from a single original asm_operands insn
1438 (so that invalid combinations are blocked). */
1439 for (i = 0; i < n_sets; i++)
1441 rtx elt = XVECEXP (body, 0, i);
1442 if (GET_CODE (elt) != SET)
1444 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1446 /* If these ASM_OPERANDS rtx's came from different original insns
1447 then they aren't allowed together. */
1448 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1449 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1452 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1455 else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1457 /* 0 outputs, but some clobbers:
1458 body is [(asm_operands ...) (clobber (reg ...))...]. */
1461 /* Make sure all the other parallel things really are clobbers. */
1462 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1463 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1466 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1475 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1476 copy its operands (both input and output) into the vector OPERANDS,
1477 the locations of the operands within the insn into the vector OPERAND_LOCS,
1478 and the constraints for the operands into CONSTRAINTS.
1479 Write the modes of the operands into MODES.
1480 Return the assembler-template.
1482 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1483 we don't store that info. */
1486 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1490 const char **constraints;
1491 enum machine_mode *modes;
1495 const char *template = 0;
1497 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1499 rtx asmop = SET_SRC (body);
1500 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1502 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1504 for (i = 1; i < noperands; i++)
1507 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1509 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1511 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1513 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1516 /* The output is in the SET.
1517 Its constraint is in the ASM_OPERANDS itself. */
1519 operands[0] = SET_DEST (body);
1521 operand_locs[0] = &SET_DEST (body);
1523 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1525 modes[0] = GET_MODE (SET_DEST (body));
1526 template = ASM_OPERANDS_TEMPLATE (asmop);
1528 else if (GET_CODE (body) == ASM_OPERANDS)
1531 /* No output operands: BODY is (asm_operands ....). */
1533 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1535 /* The input operands are found in the 1st element vector. */
1536 /* Constraints for inputs are in the 2nd element vector. */
1537 for (i = 0; i < noperands; i++)
1540 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1542 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1544 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1546 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1548 template = ASM_OPERANDS_TEMPLATE (asmop);
1550 else if (GET_CODE (body) == PARALLEL
1551 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1553 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1554 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1555 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1556 int nout = 0; /* Does not include CLOBBERs. */
1558 /* At least one output, plus some CLOBBERs. */
1560 /* The outputs are in the SETs.
1561 Their constraints are in the ASM_OPERANDS itself. */
1562 for (i = 0; i < nparallel; i++)
1564 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1565 break; /* Past last SET */
1568 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1570 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1572 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1574 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1578 for (i = 0; i < nin; i++)
1581 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1583 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1585 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1587 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1590 template = ASM_OPERANDS_TEMPLATE (asmop);
1592 else if (GET_CODE (body) == PARALLEL
1593 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1595 /* No outputs, but some CLOBBERs. */
1597 rtx asmop = XVECEXP (body, 0, 0);
1598 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1600 for (i = 0; i < nin; i++)
1603 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1605 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1607 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1609 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1612 template = ASM_OPERANDS_TEMPLATE (asmop);
1618 /* Check if an asm_operand matches it's constraints.
1619 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1622 asm_operand_ok (op, constraint)
1624 const char *constraint;
1628 /* Use constrain_operands after reload. */
1629 if (reload_completed)
1634 char c = *constraint++;
1648 case '0': case '1': case '2': case '3': case '4':
1649 case '5': case '6': case '7': case '8': case '9':
1650 /* For best results, our caller should have given us the
1651 proper matching constraint, but we can't actually fail
1652 the check if they didn't. Indicate that results are
1658 if (address_operand (op, VOIDmode))
1663 case 'V': /* non-offsettable */
1664 if (memory_operand (op, VOIDmode))
1668 case 'o': /* offsettable */
1669 if (offsettable_nonstrict_memref_p (op))
1674 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1675 excepting those that expand_call created. Further, on some
1676 machines which do not have generalized auto inc/dec, an inc/dec
1677 is not a memory_operand.
1679 Match any memory and hope things are resolved after reload. */
1681 if (GET_CODE (op) == MEM
1683 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1684 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1689 if (GET_CODE (op) == MEM
1691 || GET_CODE (XEXP (op, 0)) == PRE_INC
1692 || GET_CODE (XEXP (op, 0)) == POST_INC))
1697 #ifndef REAL_ARITHMETIC
1698 /* Match any floating double constant, but only if
1699 we can examine the bits of it reliably. */
1700 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1701 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1702 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1708 if (GET_CODE (op) == CONST_DOUBLE)
1713 if (GET_CODE (op) == CONST_DOUBLE
1714 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
1718 if (GET_CODE (op) == CONST_DOUBLE
1719 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
1724 if (GET_CODE (op) == CONST_INT
1725 || (GET_CODE (op) == CONST_DOUBLE
1726 && GET_MODE (op) == VOIDmode))
1732 #ifdef LEGITIMATE_PIC_OPERAND_P
1733 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1740 if (GET_CODE (op) == CONST_INT
1741 || (GET_CODE (op) == CONST_DOUBLE
1742 && GET_MODE (op) == VOIDmode))
1747 if (GET_CODE (op) == CONST_INT
1748 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
1752 if (GET_CODE (op) == CONST_INT
1753 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
1757 if (GET_CODE (op) == CONST_INT
1758 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
1762 if (GET_CODE (op) == CONST_INT
1763 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
1767 if (GET_CODE (op) == CONST_INT
1768 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
1772 if (GET_CODE (op) == CONST_INT
1773 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
1777 if (GET_CODE (op) == CONST_INT
1778 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
1782 if (GET_CODE (op) == CONST_INT
1783 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
1791 if (general_operand (op, VOIDmode))
1796 /* For all other letters, we first check for a register class,
1797 otherwise it is an EXTRA_CONSTRAINT. */
1798 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1801 if (GET_MODE (op) == BLKmode)
1803 if (register_operand (op, VOIDmode))
1806 #ifdef EXTRA_CONSTRAINT
1807 if (EXTRA_CONSTRAINT (op, c))
1817 /* Given an rtx *P, if it is a sum containing an integer constant term,
1818 return the location (type rtx *) of the pointer to that constant term.
1819 Otherwise, return a null pointer. */
1822 find_constant_term_loc (p)
1826 register enum rtx_code code = GET_CODE (*p);
1828 /* If *P IS such a constant term, P is its location. */
1830 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1834 /* Otherwise, if not a sum, it has no constant term. */
1836 if (GET_CODE (*p) != PLUS)
1839 /* If one of the summands is constant, return its location. */
1841 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1842 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1845 /* Otherwise, check each summand for containing a constant term. */
1847 if (XEXP (*p, 0) != 0)
1849 tem = find_constant_term_loc (&XEXP (*p, 0));
1854 if (XEXP (*p, 1) != 0)
1856 tem = find_constant_term_loc (&XEXP (*p, 1));
1864 /* Return 1 if OP is a memory reference
1865 whose address contains no side effects
1866 and remains valid after the addition
1867 of a positive integer less than the
1868 size of the object being referenced.
1870 We assume that the original address is valid and do not check it.
1872 This uses strict_memory_address_p as a subroutine, so
1873 don't use it before reload. */
1876 offsettable_memref_p (op)
1879 return ((GET_CODE (op) == MEM)
1880 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1883 /* Similar, but don't require a strictly valid mem ref:
1884 consider pseudo-regs valid as index or base regs. */
1887 offsettable_nonstrict_memref_p (op)
1890 return ((GET_CODE (op) == MEM)
1891 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1894 /* Return 1 if Y is a memory address which contains no side effects
1895 and would remain valid after the addition of a positive integer
1896 less than the size of that mode.
1898 We assume that the original address is valid and do not check it.
1899 We do check that it is valid for narrower modes.
1901 If STRICTP is nonzero, we require a strictly valid address,
1902 for the sake of use in reload.c. */
1905 offsettable_address_p (strictp, mode, y)
1907 enum machine_mode mode;
1910 register enum rtx_code ycode = GET_CODE (y);
1914 int (*addressp) PARAMS ((enum machine_mode, rtx)) =
1915 (strictp ? strict_memory_address_p : memory_address_p);
1916 unsigned int mode_sz = GET_MODE_SIZE (mode);
1918 if (CONSTANT_ADDRESS_P (y))
1921 /* Adjusting an offsettable address involves changing to a narrower mode.
1922 Make sure that's OK. */
1924 if (mode_dependent_address_p (y))
1927 /* ??? How much offset does an offsettable BLKmode reference need?
1928 Clearly that depends on the situation in which it's being used.
1929 However, the current situation in which we test 0xffffffff is
1930 less than ideal. Caveat user. */
1932 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1934 /* If the expression contains a constant term,
1935 see if it remains valid when max possible offset is added. */
1937 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1942 *y2 = plus_constant (*y2, mode_sz - 1);
1943 /* Use QImode because an odd displacement may be automatically invalid
1944 for any wider mode. But it should be valid for a single byte. */
1945 good = (*addressp) (QImode, y);
1947 /* In any case, restore old contents of memory. */
1952 if (GET_RTX_CLASS (ycode) == 'a')
1955 /* The offset added here is chosen as the maximum offset that
1956 any instruction could need to add when operating on something
1957 of the specified mode. We assume that if Y and Y+c are
1958 valid addresses then so is Y+d for all 0<d<c. */
1960 z = plus_constant_for_output (y, mode_sz - 1);
1962 /* Use QImode because an odd displacement may be automatically invalid
1963 for any wider mode. But it should be valid for a single byte. */
1964 return (*addressp) (QImode, z);
1967 /* Return 1 if ADDR is an address-expression whose effect depends
1968 on the mode of the memory reference it is used in.
1970 Autoincrement addressing is a typical example of mode-dependence
1971 because the amount of the increment depends on the mode. */
1974 mode_dependent_address_p (addr)
1975 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1977 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1979 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1980 win: ATTRIBUTE_UNUSED_LABEL
1984 /* Return 1 if OP is a general operand
1985 other than a memory ref with a mode dependent address. */
1988 mode_independent_operand (op, mode)
1989 enum machine_mode mode;
1994 if (! general_operand (op, mode))
1997 if (GET_CODE (op) != MEM)
2000 addr = XEXP (op, 0);
2001 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
2003 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2004 lose: ATTRIBUTE_UNUSED_LABEL
2008 /* Given an operand OP that is a valid memory reference which
2009 satisfies offsettable_memref_p, return a new memory reference whose
2010 address has been adjusted by OFFSET. OFFSET should be positive and
2011 less than the size of the object referenced. */
2014 adj_offsettable_operand (op, offset)
2018 register enum rtx_code code = GET_CODE (op);
2022 register rtx y = XEXP (op, 0);
2025 if (CONSTANT_ADDRESS_P (y))
2027 new = gen_rtx_MEM (GET_MODE (op),
2028 plus_constant_for_output (y, offset));
2029 MEM_COPY_ATTRIBUTES (new, op);
2033 if (GET_CODE (y) == PLUS)
2036 register rtx *const_loc;
2040 const_loc = find_constant_term_loc (&z);
2043 *const_loc = plus_constant_for_output (*const_loc, offset);
2048 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
2049 MEM_COPY_ATTRIBUTES (new, op);
2055 /* Like extract_insn, but save insn extracted and don't extract again, when
2056 called again for the same insn expecting that recog_data still contain the
2057 valid information. This is used primary by gen_attr infrastructure that
2058 often does extract insn again and again. */
2060 extract_insn_cached (insn)
2063 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2065 extract_insn (insn);
2066 recog_data.insn = insn;
2068 /* Do cached extract_insn, constrain_operand and complain about failures.
2069 Used by insn_attrtab. */
2071 extract_constrain_insn_cached (insn)
2074 extract_insn_cached (insn);
2075 if (which_alternative == -1
2076 && !constrain_operands (reload_completed))
2077 fatal_insn_not_found (insn);
2079 /* Do cached constrain_operand and complain about failures. */
2081 constrain_operands_cached (strict)
2084 if (which_alternative == -1)
2085 return constrain_operands (strict);
2090 /* Analyze INSN and fill in recog_data. */
2099 rtx body = PATTERN (insn);
2101 recog_data.insn = NULL;
2102 recog_data.n_operands = 0;
2103 recog_data.n_alternatives = 0;
2104 recog_data.n_dups = 0;
2105 which_alternative = -1;
2107 switch (GET_CODE (body))
2117 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2122 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2123 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2124 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2130 recog_data.n_operands = noperands = asm_noperands (body);
2133 /* This insn is an `asm' with operands. */
2135 /* expand_asm_operands makes sure there aren't too many operands. */
2136 if (noperands > MAX_RECOG_OPERANDS)
2139 /* Now get the operand values and constraints out of the insn. */
2140 decode_asm_operands (body, recog_data.operand,
2141 recog_data.operand_loc,
2142 recog_data.constraints,
2143 recog_data.operand_mode);
2146 const char *p = recog_data.constraints[0];
2147 recog_data.n_alternatives = 1;
2149 recog_data.n_alternatives += (*p++ == ',');
2153 fatal_insn_not_found (insn);
2157 /* Ordinary insn: recognize it, get the operands via insn_extract
2158 and get the constraints. */
2160 icode = recog_memoized (insn);
2162 fatal_insn_not_found (insn);
2164 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2165 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2166 recog_data.n_dups = insn_data[icode].n_dups;
2168 insn_extract (insn);
2170 for (i = 0; i < noperands; i++)
2172 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2173 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2174 /* VOIDmode match_operands gets mode from their real operand. */
2175 if (recog_data.operand_mode[i] == VOIDmode)
2176 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2179 for (i = 0; i < noperands; i++)
2180 recog_data.operand_type[i]
2181 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2182 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2185 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
2189 /* After calling extract_insn, you can use this function to extract some
2190 information from the constraint strings into a more usable form.
2191 The collected data is stored in recog_op_alt. */
2193 preprocess_constraints ()
2197 memset (recog_op_alt, 0, sizeof recog_op_alt);
2198 for (i = 0; i < recog_data.n_operands; i++)
2201 struct operand_alternative *op_alt;
2202 const char *p = recog_data.constraints[i];
2204 op_alt = recog_op_alt[i];
2206 for (j = 0; j < recog_data.n_alternatives; j++)
2208 op_alt[j].class = NO_REGS;
2209 op_alt[j].constraint = p;
2210 op_alt[j].matches = -1;
2211 op_alt[j].matched = -1;
2213 if (*p == '\0' || *p == ',')
2215 op_alt[j].anything_ok = 1;
2225 while (c != ',' && c != '\0');
2226 if (c == ',' || c == '\0')
2231 case '=': case '+': case '*': case '%':
2232 case 'E': case 'F': case 'G': case 'H':
2233 case 's': case 'i': case 'n':
2234 case 'I': case 'J': case 'K': case 'L':
2235 case 'M': case 'N': case 'O': case 'P':
2236 /* These don't say anything we care about. */
2240 op_alt[j].reject += 6;
2243 op_alt[j].reject += 600;
2246 op_alt[j].earlyclobber = 1;
2249 case '0': case '1': case '2': case '3': case '4':
2250 case '5': case '6': case '7': case '8': case '9':
2251 op_alt[j].matches = c - '0';
2252 recog_op_alt[op_alt[j].matches][j].matched = i;
2256 op_alt[j].memory_ok = 1;
2259 op_alt[j].decmem_ok = 1;
2262 op_alt[j].incmem_ok = 1;
2265 op_alt[j].nonoffmem_ok = 1;
2268 op_alt[j].offmem_ok = 1;
2271 op_alt[j].anything_ok = 1;
2275 op_alt[j].is_address = 1;
2276 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS];
2280 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
2284 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
2292 /* Check the operands of an insn against the insn's operand constraints
2293 and return 1 if they are valid.
2294 The information about the insn's operands, constraints, operand modes
2295 etc. is obtained from the global variables set up by extract_insn.
2297 WHICH_ALTERNATIVE is set to a number which indicates which
2298 alternative of constraints was matched: 0 for the first alternative,
2299 1 for the next, etc.
2301 In addition, when two operands are match
2302 and it happens that the output operand is (reg) while the
2303 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2304 make the output operand look like the input.
2305 This is because the output operand is the one the template will print.
2307 This is used in final, just before printing the assembler code and by
2308 the routines that determine an insn's attribute.
2310 If STRICT is a positive non-zero value, it means that we have been
2311 called after reload has been completed. In that case, we must
2312 do all checks strictly. If it is zero, it means that we have been called
2313 before reload has completed. In that case, we first try to see if we can
2314 find an alternative that matches strictly. If not, we try again, this
2315 time assuming that reload will fix up the insn. This provides a "best
2316 guess" for the alternative and is used to compute attributes of insns prior
2317 to reload. A negative value of STRICT is used for this internal call. */
2325 constrain_operands (strict)
2328 const char *constraints[MAX_RECOG_OPERANDS];
2329 int matching_operands[MAX_RECOG_OPERANDS];
2330 int earlyclobber[MAX_RECOG_OPERANDS];
2333 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2334 int funny_match_index;
2336 which_alternative = 0;
2337 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2340 for (c = 0; c < recog_data.n_operands; c++)
2342 constraints[c] = recog_data.constraints[c];
2343 matching_operands[c] = -1;
2350 funny_match_index = 0;
2352 for (opno = 0; opno < recog_data.n_operands; opno++)
2354 register rtx op = recog_data.operand[opno];
2355 enum machine_mode mode = GET_MODE (op);
2356 register const char *p = constraints[opno];
2361 earlyclobber[opno] = 0;
2363 /* A unary operator may be accepted by the predicate, but it
2364 is irrelevant for matching constraints. */
2365 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
2368 if (GET_CODE (op) == SUBREG)
2370 if (GET_CODE (SUBREG_REG (op)) == REG
2371 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2372 offset = SUBREG_WORD (op);
2373 op = SUBREG_REG (op);
2376 /* An empty constraint or empty alternative
2377 allows anything which matched the pattern. */
2378 if (*p == 0 || *p == ',')
2381 while (*p && (c = *p++) != ',')
2384 case '?': case '!': case '*': case '%':
2389 /* Ignore rest of this alternative as far as
2390 constraint checking is concerned. */
2391 while (*p && *p != ',')
2396 earlyclobber[opno] = 1;
2399 case '0': case '1': case '2': case '3': case '4':
2400 case '5': case '6': case '7': case '8': case '9':
2402 /* This operand must be the same as a previous one.
2403 This kind of constraint is used for instructions such
2404 as add when they take only two operands.
2406 Note that the lower-numbered operand is passed first.
2408 If we are not testing strictly, assume that this constraint
2409 will be satisfied. */
2414 rtx op1 = recog_data.operand[c - '0'];
2415 rtx op2 = recog_data.operand[opno];
2417 /* A unary operator may be accepted by the predicate,
2418 but it is irrelevant for matching constraints. */
2419 if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
2420 op1 = XEXP (op1, 0);
2421 if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
2422 op2 = XEXP (op2, 0);
2424 val = operands_match_p (op1, op2);
2427 matching_operands[opno] = c - '0';
2428 matching_operands[c - '0'] = opno;
2432 /* If output is *x and input is *--x,
2433 arrange later to change the output to *--x as well,
2434 since the output op is the one that will be printed. */
2435 if (val == 2 && strict > 0)
2437 funny_match[funny_match_index].this = opno;
2438 funny_match[funny_match_index++].other = c - '0';
2443 /* p is used for address_operands. When we are called by
2444 gen_reload, no one will have checked that the address is
2445 strictly valid, i.e., that all pseudos requiring hard regs
2446 have gotten them. */
2448 || (strict_memory_address_p (recog_data.operand_mode[opno],
2453 /* No need to check general_operand again;
2454 it was done in insn-recog.c. */
2456 /* Anything goes unless it is a REG and really has a hard reg
2457 but the hard reg is not in the class GENERAL_REGS. */
2459 || GENERAL_REGS == ALL_REGS
2460 || GET_CODE (op) != REG
2461 || (reload_in_progress
2462 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2463 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2468 /* This is used for a MATCH_SCRATCH in the cases when
2469 we don't actually need anything. So anything goes
2475 if (GET_CODE (op) == MEM
2476 /* Before reload, accept what reload can turn into mem. */
2477 || (strict < 0 && CONSTANT_P (op))
2478 /* During reload, accept a pseudo */
2479 || (reload_in_progress && GET_CODE (op) == REG
2480 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2485 if (GET_CODE (op) == MEM
2486 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2487 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2492 if (GET_CODE (op) == MEM
2493 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2494 || GET_CODE (XEXP (op, 0)) == POST_INC))
2499 #ifndef REAL_ARITHMETIC
2500 /* Match any CONST_DOUBLE, but only if
2501 we can examine the bits of it reliably. */
2502 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2503 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2504 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
2507 if (GET_CODE (op) == CONST_DOUBLE)
2512 if (GET_CODE (op) == CONST_DOUBLE)
2518 if (GET_CODE (op) == CONST_DOUBLE
2519 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
2524 if (GET_CODE (op) == CONST_INT
2525 || (GET_CODE (op) == CONST_DOUBLE
2526 && GET_MODE (op) == VOIDmode))
2529 if (CONSTANT_P (op))
2534 if (GET_CODE (op) == CONST_INT
2535 || (GET_CODE (op) == CONST_DOUBLE
2536 && GET_MODE (op) == VOIDmode))
2548 if (GET_CODE (op) == CONST_INT
2549 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
2554 if (GET_CODE (op) == MEM
2555 && ((strict > 0 && ! offsettable_memref_p (op))
2557 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
2558 || (reload_in_progress
2559 && !(GET_CODE (op) == REG
2560 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2565 if ((strict > 0 && offsettable_memref_p (op))
2566 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2567 /* Before reload, accept what reload can handle. */
2569 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
2570 /* During reload, accept a pseudo */
2571 || (reload_in_progress && GET_CODE (op) == REG
2572 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2578 enum reg_class class;
2580 class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c));
2581 if (class != NO_REGS)
2585 && GET_CODE (op) == REG
2586 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2587 || (strict == 0 && GET_CODE (op) == SCRATCH)
2588 || (GET_CODE (op) == REG
2589 && reg_fits_class_p (op, class, offset, mode)))
2592 #ifdef EXTRA_CONSTRAINT
2593 else if (EXTRA_CONSTRAINT (op, c))
2600 constraints[opno] = p;
2601 /* If this operand did not win somehow,
2602 this alternative loses. */
2606 /* This alternative won; the operands are ok.
2607 Change whichever operands this alternative says to change. */
2612 /* See if any earlyclobber operand conflicts with some other
2616 for (eopno = 0; eopno < recog_data.n_operands; eopno++)
2617 /* Ignore earlyclobber operands now in memory,
2618 because we would often report failure when we have
2619 two memory operands, one of which was formerly a REG. */
2620 if (earlyclobber[eopno]
2621 && GET_CODE (recog_data.operand[eopno]) == REG)
2622 for (opno = 0; opno < recog_data.n_operands; opno++)
2623 if ((GET_CODE (recog_data.operand[opno]) == MEM
2624 || recog_data.operand_type[opno] != OP_OUT)
2626 /* Ignore things like match_operator operands. */
2627 && *recog_data.constraints[opno] != 0
2628 && ! (matching_operands[opno] == eopno
2629 && operands_match_p (recog_data.operand[opno],
2630 recog_data.operand[eopno]))
2631 && ! safe_from_earlyclobber (recog_data.operand[opno],
2632 recog_data.operand[eopno]))
2637 while (--funny_match_index >= 0)
2639 recog_data.operand[funny_match[funny_match_index].other]
2640 = recog_data.operand[funny_match[funny_match_index].this];
2647 which_alternative++;
2649 while (which_alternative < recog_data.n_alternatives);
2651 which_alternative = -1;
2652 /* If we are about to reject this, but we are not to test strictly,
2653 try a very loose test. Only return failure if it fails also. */
2655 return constrain_operands (-1);
2660 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2661 is a hard reg in class CLASS when its regno is offset by OFFSET
2662 and changed to mode MODE.
2663 If REG occupies multiple hard regs, all of them must be in CLASS. */
2666 reg_fits_class_p (operand, class, offset, mode)
2668 register enum reg_class class;
2670 enum machine_mode mode;
2672 register int regno = REGNO (operand);
2673 if (regno < FIRST_PSEUDO_REGISTER
2674 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2679 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2681 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2690 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2693 split_all_insns (upd_life)
2700 blocks = sbitmap_alloc (n_basic_blocks);
2701 sbitmap_zero (blocks);
2704 for (i = n_basic_blocks - 1; i >= 0; --i)
2706 basic_block bb = BASIC_BLOCK (i);
2709 for (insn = bb->head; insn ; insn = next)
2713 /* Can't use `next_real_insn' because that might go across
2714 CODE_LABELS and short-out basic blocks. */
2715 next = NEXT_INSN (insn);
2716 if (! INSN_P (insn))
2719 /* Don't split no-op move insns. These should silently
2720 disappear later in final. Splitting such insns would
2721 break the code that handles REG_NO_CONFLICT blocks. */
2723 else if ((set = single_set (insn)) != NULL
2724 && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
2726 /* Nops get in the way while scheduling, so delete them
2727 now if register allocation has already been done. It
2728 is too risky to try to do this before register
2729 allocation, and there are unlikely to be very many
2730 nops then anyways. */
2731 if (reload_completed)
2733 PUT_CODE (insn, NOTE);
2734 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2735 NOTE_SOURCE_FILE (insn) = 0;
2740 /* Split insns here to get max fine-grain parallelism. */
2741 rtx first = PREV_INSN (insn);
2742 rtx last = try_split (PATTERN (insn), insn, 1);
2746 SET_BIT (blocks, i);
2749 /* try_split returns the NOTE that INSN became. */
2750 first = NEXT_INSN (first);
2751 PUT_CODE (insn, NOTE);
2752 NOTE_SOURCE_FILE (insn) = 0;
2753 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2755 if (insn == bb->end)
2761 /* ??? Coddle to md files that generate subregs in post-
2762 reload splitters instead of computing the proper
2764 if (reload_completed)
2768 cleanup_subreg_operands (first);
2771 first = NEXT_INSN (first);
2776 if (insn == bb->end)
2780 /* ??? When we're called from just after reload, the CFG is in bad
2781 shape, and we may have fallen off the end. This could be fixed
2782 by having reload not try to delete unreachable code. Otherwise
2783 assert we found the end insn. */
2784 if (insn == NULL && upd_life)
2788 if (changed && upd_life)
2790 compute_bb_for_insn (get_max_uid ());
2791 count_or_remove_death_notes (blocks, 1);
2792 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
2795 sbitmap_free (blocks);
2798 #ifdef HAVE_peephole2
2799 struct peep2_insn_data
2805 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2806 static int peep2_current;
2808 /* A non-insn marker indicating the last insn of the block.
2809 The live_before regset for this element is correct, indicating
2810 global_live_at_end for the block. */
2811 #define PEEP2_EOB pc_rtx
2813 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2814 does not exist. Used by the recognizer to find the next insn to match
2815 in a multi-insn pattern. */
2821 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2825 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2826 n -= MAX_INSNS_PER_PEEP2 + 1;
2828 if (peep2_insn_data[n].insn == PEEP2_EOB)
2830 return peep2_insn_data[n].insn;
2833 /* Return true if REGNO is dead before the Nth non-note insn
2837 peep2_regno_dead_p (ofs, regno)
2841 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2844 ofs += peep2_current;
2845 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2846 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2848 if (peep2_insn_data[ofs].insn == NULL_RTX)
2851 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2854 /* Similarly for a REG. */
2857 peep2_reg_dead_p (ofs, reg)
2863 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2866 ofs += peep2_current;
2867 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2868 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2870 if (peep2_insn_data[ofs].insn == NULL_RTX)
2873 regno = REGNO (reg);
2874 n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2876 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2881 /* Try to find a hard register of mode MODE, matching the register class in
2882 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2883 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2884 in which case the only condition is that the register must be available
2885 before CURRENT_INSN.
2886 Registers that already have bits set in REG_SET will not be considered.
2888 If an appropriate register is available, it will be returned and the
2889 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2893 peep2_find_free_register (from, to, class_str, mode, reg_set)
2895 const char *class_str;
2896 enum machine_mode mode;
2897 HARD_REG_SET *reg_set;
2899 static int search_ofs;
2900 enum reg_class class;
2904 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1)
2907 from += peep2_current;
2908 if (from >= MAX_INSNS_PER_PEEP2 + 1)
2909 from -= MAX_INSNS_PER_PEEP2 + 1;
2910 to += peep2_current;
2911 if (to >= MAX_INSNS_PER_PEEP2 + 1)
2912 to -= MAX_INSNS_PER_PEEP2 + 1;
2914 if (peep2_insn_data[from].insn == NULL_RTX)
2916 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
2920 HARD_REG_SET this_live;
2922 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
2924 if (peep2_insn_data[from].insn == NULL_RTX)
2926 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
2927 IOR_HARD_REG_SET (live, this_live);
2930 class = (class_str[0] == 'r' ? GENERAL_REGS
2931 : REG_CLASS_FROM_LETTER (class_str[0]));
2933 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2935 int raw_regno, regno, success, j;
2937 /* Distribute the free registers as much as possible. */
2938 raw_regno = search_ofs + i;
2939 if (raw_regno >= FIRST_PSEUDO_REGISTER)
2940 raw_regno -= FIRST_PSEUDO_REGISTER;
2941 #ifdef REG_ALLOC_ORDER
2942 regno = reg_alloc_order[raw_regno];
2947 /* Don't allocate fixed registers. */
2948 if (fixed_regs[regno])
2950 /* Make sure the register is of the right class. */
2951 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno))
2953 /* And can support the mode we need. */
2954 if (! HARD_REGNO_MODE_OK (regno, mode))
2956 /* And that we don't create an extra save/restore. */
2957 if (! call_used_regs[regno] && ! regs_ever_live[regno])
2959 /* And we don't clobber traceback for noreturn functions. */
2960 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
2961 && (! reload_completed || frame_pointer_needed))
2965 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2967 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
2968 || TEST_HARD_REG_BIT (live, regno + j))
2976 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2977 SET_HARD_REG_BIT (*reg_set, regno + j);
2979 /* Start the next search with the next register. */
2980 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
2982 search_ofs = raw_regno;
2984 return gen_rtx_REG (mode, regno);
2992 /* Perform the peephole2 optimization pass. */
2995 peephole2_optimize (dump_file)
2996 FILE *dump_file ATTRIBUTE_UNUSED;
2998 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
3002 #ifdef HAVE_conditional_execution
3007 /* Initialize the regsets we're going to use. */
3008 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3009 peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]);
3010 live = INITIALIZE_REG_SET (rs_heads[i]);
3012 #ifdef HAVE_conditional_execution
3013 blocks = sbitmap_alloc (n_basic_blocks);
3014 sbitmap_zero (blocks);
3017 count_or_remove_death_notes (NULL, 1);
3020 for (b = n_basic_blocks - 1; b >= 0; --b)
3022 basic_block bb = BASIC_BLOCK (b);
3023 struct propagate_block_info *pbi;
3025 /* Indicate that all slots except the last holds invalid data. */
3026 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3027 peep2_insn_data[i].insn = NULL_RTX;
3029 /* Indicate that the last slot contains live_after data. */
3030 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3031 peep2_current = MAX_INSNS_PER_PEEP2;
3033 /* Start up propagation. */
3034 COPY_REG_SET (live, bb->global_live_at_end);
3035 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3037 #ifdef HAVE_conditional_execution
3038 pbi = init_propagate_block_info (bb, live, NULL, 0);
3040 pbi = init_propagate_block_info (bb, live, NULL, PROP_DEATH_NOTES);
3043 for (insn = bb->end; ; insn = prev)
3045 prev = PREV_INSN (insn);
3051 /* Record this insn. */
3052 if (--peep2_current < 0)
3053 peep2_current = MAX_INSNS_PER_PEEP2;
3054 peep2_insn_data[peep2_current].insn = insn;
3055 propagate_one_insn (pbi, insn);
3056 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
3058 /* Match the peephole. */
3059 try = peephole2_insns (PATTERN (insn), insn, &match_len);
3062 i = match_len + peep2_current;
3063 if (i >= MAX_INSNS_PER_PEEP2 + 1)
3064 i -= MAX_INSNS_PER_PEEP2 + 1;
3066 /* Replace the old sequence with the new. */
3067 flow_delete_insn_chain (insn, peep2_insn_data[i].insn);
3068 try = emit_insn_after (try, prev);
3070 /* Adjust the basic block boundaries. */
3071 if (peep2_insn_data[i].insn == bb->end)
3073 if (insn == bb->head)
3074 bb->head = NEXT_INSN (prev);
3076 #ifdef HAVE_conditional_execution
3077 /* With conditional execution, we cannot back up the
3078 live information so easily, since the conditional
3079 death data structures are not so self-contained.
3080 So record that we've made a modification to this
3081 block and update life information at the end. */
3082 SET_BIT (blocks, b);
3085 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3086 peep2_insn_data[i].insn = NULL_RTX;
3087 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
3089 /* Back up lifetime information past the end of the
3090 newly created sequence. */
3091 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
3093 COPY_REG_SET (live, peep2_insn_data[i].live_before);
3095 /* Update life information for the new sequence. */
3101 i = MAX_INSNS_PER_PEEP2;
3102 peep2_insn_data[i].insn = try;
3103 propagate_one_insn (pbi, try);
3104 COPY_REG_SET (peep2_insn_data[i].live_before, live);
3106 try = PREV_INSN (try);
3108 while (try != prev);
3110 /* ??? Should verify that LIVE now matches what we
3111 had before the new sequence. */
3118 if (insn == bb->head)
3122 free_propagate_block_info (pbi);
3125 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3126 FREE_REG_SET (peep2_insn_data[i].live_before);
3127 FREE_REG_SET (live);
3129 #ifdef HAVE_conditional_execution
3130 count_or_remove_death_notes (blocks, 1);
3131 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
3132 sbitmap_free (blocks);
3135 #endif /* HAVE_peephole2 */