1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "insn-config.h"
26 #include "insn-attr.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
31 #include "hard-reg-set.h"
35 #ifndef STACK_PUSH_CODE
36 #ifdef STACK_GROWS_DOWNWARD
37 #define STACK_PUSH_CODE PRE_DEC
39 #define STACK_PUSH_CODE PRE_INC
43 /* Import from final.c: */
44 extern rtx alter_subreg ();
46 static rtx *find_single_use_1 PROTO((rtx, rtx *));
48 /* Nonzero means allow operands to be volatile.
49 This should be 0 if you are generating rtl, such as if you are calling
50 the functions in optabs.c and expmed.c (most of the time).
51 This should be 1 if all valid insns need to be recognized,
52 such as in regclass.c and final.c and reload.c.
54 init_recog and init_recog_no_volatile are responsible for setting this. */
58 /* On return from `constrain_operands', indicate which alternative
61 int which_alternative;
63 /* Nonzero after end of reload pass.
64 Set to 1 or 0 by toplev.c.
65 Controls the significance of (SUBREG (MEM)). */
69 /* Initialize data used by the function `recog'.
70 This must be called once in the compilation of a function
71 before any insn recognition may be done in the function. */
74 init_recog_no_volatile ()
85 /* Try recognizing the instruction INSN,
86 and return the code number that results.
87 Remember the code so that repeated calls do not
88 need to spend the time for actual rerecognition.
90 This function is the normal interface to instruction recognition.
91 The automatically-generated function `recog' is normally called
92 through this one. (The only exception is in combine.c.) */
98 if (INSN_CODE (insn) < 0)
99 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
100 return INSN_CODE (insn);
103 /* Check that X is an insn-body for an `asm' with operands
104 and that the operands mentioned in it are legitimate. */
107 check_asm_operands (x)
110 int noperands = asm_noperands (x);
119 operands = (rtx *) alloca (noperands * sizeof (rtx));
120 decode_asm_operands (x, operands, NULL_PTR, NULL_PTR, NULL_PTR);
122 for (i = 0; i < noperands; i++)
123 if (!general_operand (operands[i], VOIDmode))
129 /* Static data for the next two routines.
131 The maximum number of changes supported is defined as the maximum
132 number of operands times 5. This allows for repeated substitutions
133 inside complex indexed address, or, alternatively, changes in up
136 #define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5)
138 static rtx change_objects[MAX_CHANGE_LOCS];
139 static int change_old_codes[MAX_CHANGE_LOCS];
140 static rtx *change_locs[MAX_CHANGE_LOCS];
141 static rtx change_olds[MAX_CHANGE_LOCS];
143 static int num_changes = 0;
145 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
146 at which NEW will be placed. If OBJECT is zero, no validation is done,
147 the change is simply made.
149 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
150 will be called with the address and mode as parameters. If OBJECT is
151 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
154 IN_GROUP is non-zero if this is part of a group of changes that must be
155 performed as a group. In that case, the changes will be stored. The
156 function `apply_change_group' will validate and apply the changes.
158 If IN_GROUP is zero, this is a single change. Try to recognize the insn
159 or validate the memory reference with the change applied. If the result
160 is not valid for the machine, suppress the change and return zero.
161 Otherwise, perform the change and return 1. */
164 validate_change (object, loc, new, in_group)
172 if (old == new || rtx_equal_p (old, new))
175 if (num_changes >= MAX_CHANGE_LOCS
176 || (in_group == 0 && num_changes != 0))
181 /* Save the information describing this change. */
182 change_objects[num_changes] = object;
183 change_locs[num_changes] = loc;
184 change_olds[num_changes] = old;
186 if (object && GET_CODE (object) != MEM)
188 /* Set INSN_CODE to force rerecognition of insn. Save old code in
190 change_old_codes[num_changes] = INSN_CODE (object);
191 INSN_CODE (object) = -1;
196 /* If we are making a group of changes, return 1. Otherwise, validate the
197 change group we made. */
202 return apply_change_group ();
205 /* Apply a group of changes previously issued with `validate_change'.
206 Return 1 if all changes are valid, zero otherwise. */
209 apply_change_group ()
213 /* The changes have been applied and all INSN_CODEs have been reset to force
216 The changes are valid if we aren't given an object, or if we are
217 given a MEM and it still is a valid address, or if this is in insn
218 and it is recognized. In the latter case, if reload has completed,
219 we also require that the operands meet the constraints for
220 the insn. We do not allow modifying an ASM_OPERANDS after reload
221 has completed because verifying the constraints is too difficult. */
223 for (i = 0; i < num_changes; i++)
225 rtx object = change_objects[i];
230 if (GET_CODE (object) == MEM)
232 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
235 else if ((recog_memoized (object) < 0
236 && (asm_noperands (PATTERN (object)) < 0
237 || ! check_asm_operands (PATTERN (object))
238 || reload_completed))
240 && (insn_extract (object),
241 ! constrain_operands (INSN_CODE (object), 1))))
243 rtx pat = PATTERN (object);
245 /* Perhaps we couldn't recognize the insn because there were
246 extra CLOBBERs at the end. If so, try to re-recognize
247 without the last CLOBBER (later iterations will cause each of
248 them to be eliminated, in turn). But don't do this if we
249 have an ASM_OPERAND. */
250 if (GET_CODE (pat) == PARALLEL
251 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
252 && asm_noperands (PATTERN (object)) < 0)
256 if (XVECLEN (pat, 0) == 2)
257 newpat = XVECEXP (pat, 0, 0);
262 newpat = gen_rtx_PARALLEL (VOIDmode,
263 gen_rtvec (XVECLEN (pat, 0) - 1));
264 for (j = 0; j < XVECLEN (newpat, 0); j++)
265 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
268 /* Add a new change to this group to replace the pattern
269 with this new pattern. Then consider this change
270 as having succeeded. The change we added will
271 cause the entire call to fail if things remain invalid.
273 Note that this can lose if a later change than the one
274 we are processing specified &XVECEXP (PATTERN (object), 0, X)
275 but this shouldn't occur. */
277 validate_change (object, &PATTERN (object), newpat, 1);
279 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
280 /* If this insn is a CLOBBER or USE, it is always valid, but is
288 if (i == num_changes)
300 /* Return the number of changes so far in the current group. */
303 num_validated_changes ()
308 /* Retract the changes numbered NUM and up. */
316 /* Back out all the changes. Do this in the opposite order in which
318 for (i = num_changes - 1; i >= num; i--)
320 *change_locs[i] = change_olds[i];
321 if (change_objects[i] && GET_CODE (change_objects[i]) != MEM)
322 INSN_CODE (change_objects[i]) = change_old_codes[i];
327 /* Replace every occurrence of FROM in X with TO. Mark each change with
328 validate_change passing OBJECT. */
331 validate_replace_rtx_1 (loc, from, to, object)
333 rtx from, to, object;
337 register rtx x = *loc;
338 enum rtx_code code = GET_CODE (x);
340 /* X matches FROM if it is the same rtx or they are both referring to the
341 same register in the same mode. Avoid calling rtx_equal_p unless the
342 operands look similar. */
345 || (GET_CODE (x) == REG && GET_CODE (from) == REG
346 && GET_MODE (x) == GET_MODE (from)
347 && REGNO (x) == REGNO (from))
348 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
349 && rtx_equal_p (x, from)))
351 validate_change (object, loc, to, 1);
355 /* For commutative or comparison operations, try replacing each argument
356 separately and seeing if we made any changes. If so, put a constant
358 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
360 int prev_changes = num_changes;
362 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
363 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
364 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
366 validate_change (object, loc,
367 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
368 : swap_condition (code),
369 GET_MODE (x), XEXP (x, 1),
377 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
378 done the substitution, otherwise we won't. */
383 /* If we have have a PLUS whose second operand is now a CONST_INT, use
384 plus_constant to try to simplify it. */
385 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
386 validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
391 if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
393 validate_change (object, loc,
394 plus_constant (XEXP (x, 0), - INTVAL (to)),
402 /* In these cases, the operation to be performed depends on the mode
403 of the operand. If we are replacing the operand with a VOIDmode
404 constant, we lose the information. So try to simplify the operation
405 in that case. If it fails, substitute in something that we know
406 won't be recognized. */
407 if (GET_MODE (to) == VOIDmode
408 && (XEXP (x, 0) == from
409 || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG
410 && GET_MODE (XEXP (x, 0)) == GET_MODE (from)
411 && REGNO (XEXP (x, 0)) == REGNO (from))))
413 rtx new = simplify_unary_operation (code, GET_MODE (x), to,
416 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
418 validate_change (object, loc, new, 1);
424 /* If we have a SUBREG of a register that we are replacing and we are
425 replacing it with a MEM, make a new MEM and try replacing the
426 SUBREG with it. Don't do this if the MEM has a mode-dependent address
427 or if we would be widening it. */
429 if (SUBREG_REG (x) == from
430 && GET_CODE (from) == REG
431 && GET_CODE (to) == MEM
432 && ! mode_dependent_address_p (XEXP (to, 0))
433 && ! MEM_VOLATILE_P (to)
434 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
436 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
437 enum machine_mode mode = GET_MODE (x);
440 if (BYTES_BIG_ENDIAN)
441 offset += (MIN (UNITS_PER_WORD,
442 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
443 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
445 new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
446 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to);
447 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to);
448 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to);
449 validate_change (object, loc, new, 1);
456 /* If we are replacing a register with memory, try to change the memory
457 to be the mode required for memory in extract operations (this isn't
458 likely to be an insertion operation; if it was, nothing bad will
459 happen, we might just fail in some cases). */
461 if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM
462 && GET_CODE (XEXP (x, 1)) == CONST_INT
463 && GET_CODE (XEXP (x, 2)) == CONST_INT
464 && ! mode_dependent_address_p (XEXP (to, 0))
465 && ! MEM_VOLATILE_P (to))
467 enum machine_mode wanted_mode = VOIDmode;
468 enum machine_mode is_mode = GET_MODE (to);
469 int pos = INTVAL (XEXP (x, 2));
472 if (code == ZERO_EXTRACT)
473 wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
476 if (code == SIGN_EXTRACT)
477 wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
480 /* If we have a narrower mode, we can do something. */
481 if (wanted_mode != VOIDmode
482 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
484 int offset = pos / BITS_PER_UNIT;
487 /* If the bytes and bits are counted differently, we
488 must adjust the offset. */
489 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
490 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
493 pos %= GET_MODE_BITSIZE (wanted_mode);
495 newmem = gen_rtx_MEM (wanted_mode,
496 plus_constant (XEXP (to, 0), offset));
497 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to);
498 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (to);
499 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (to);
501 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
502 validate_change (object, &XEXP (x, 0), newmem, 1);
512 /* For commutative or comparison operations we've already performed
513 replacements. Don't try to perform them again. */
514 if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
516 fmt = GET_RTX_FORMAT (code);
517 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
520 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
521 else if (fmt[i] == 'E')
522 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
523 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
528 /* Try replacing every occurrence of FROM in INSN with TO. After all
529 changes have been made, validate by seeing if INSN is still valid. */
532 validate_replace_rtx (from, to, insn)
535 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
536 return apply_change_group ();
540 /* Return 1 if the insn using CC0 set by INSN does not contain
541 any ordered tests applied to the condition codes.
542 EQ and NE tests do not count. */
545 next_insn_tests_no_inequality (insn)
548 register rtx next = next_cc0_user (insn);
550 /* If there is no next insn, we have to take the conservative choice. */
554 return ((GET_CODE (next) == JUMP_INSN
555 || GET_CODE (next) == INSN
556 || GET_CODE (next) == CALL_INSN)
557 && ! inequality_comparisons_p (PATTERN (next)));
560 #if 0 /* This is useless since the insn that sets the cc's
561 must be followed immediately by the use of them. */
562 /* Return 1 if the CC value set up by INSN is not used. */
565 next_insns_test_no_inequality (insn)
568 register rtx next = NEXT_INSN (insn);
570 for (; next != 0; next = NEXT_INSN (next))
572 if (GET_CODE (next) == CODE_LABEL
573 || GET_CODE (next) == BARRIER)
575 if (GET_CODE (next) == NOTE)
577 if (inequality_comparisons_p (PATTERN (next)))
579 if (sets_cc0_p (PATTERN (next)) == 1)
581 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
589 /* This is used by find_single_use to locate an rtx that contains exactly one
590 use of DEST, which is typically either a REG or CC0. It returns a
591 pointer to the innermost rtx expression containing DEST. Appearances of
592 DEST that are being used to totally replace it are not counted. */
595 find_single_use_1 (dest, loc)
600 enum rtx_code code = GET_CODE (x);
617 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
618 of a REG that occupies all of the REG, the insn uses DEST if
619 it is mentioned in the destination or the source. Otherwise, we
620 need just check the source. */
621 if (GET_CODE (SET_DEST (x)) != CC0
622 && GET_CODE (SET_DEST (x)) != PC
623 && GET_CODE (SET_DEST (x)) != REG
624 && ! (GET_CODE (SET_DEST (x)) == SUBREG
625 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
626 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
627 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
628 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
629 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
632 return find_single_use_1 (dest, &SET_SRC (x));
636 return find_single_use_1 (dest, &XEXP (x, 0));
642 /* If it wasn't one of the common cases above, check each expression and
643 vector of this code. Look for a unique usage of DEST. */
645 fmt = GET_RTX_FORMAT (code);
646 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
650 if (dest == XEXP (x, i)
651 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
652 && REGNO (dest) == REGNO (XEXP (x, i))))
655 this_result = find_single_use_1 (dest, &XEXP (x, i));
658 result = this_result;
659 else if (this_result)
660 /* Duplicate usage. */
663 else if (fmt[i] == 'E')
667 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
669 if (XVECEXP (x, i, j) == dest
670 || (GET_CODE (dest) == REG
671 && GET_CODE (XVECEXP (x, i, j)) == REG
672 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
675 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
678 result = this_result;
679 else if (this_result)
688 /* See if DEST, produced in INSN, is used only a single time in the
689 sequel. If so, return a pointer to the innermost rtx expression in which
692 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
694 This routine will return usually zero either before flow is called (because
695 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
696 note can't be trusted).
698 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
699 care about REG_DEAD notes or LOG_LINKS.
701 Otherwise, we find the single use by finding an insn that has a
702 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
703 only referenced once in that insn, we know that it must be the first
704 and last insn referencing DEST. */
707 find_single_use (dest, insn, ploc)
719 next = NEXT_INSN (insn);
721 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
724 result = find_single_use_1 (dest, &PATTERN (next));
731 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
734 for (next = next_nonnote_insn (insn);
735 next != 0 && GET_CODE (next) != CODE_LABEL;
736 next = next_nonnote_insn (next))
737 if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest))
739 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
740 if (XEXP (link, 0) == insn)
745 result = find_single_use_1 (dest, &PATTERN (next));
755 /* Return 1 if OP is a valid general operand for machine mode MODE.
756 This is either a register reference, a memory reference,
757 or a constant. In the case of a memory reference, the address
758 is checked for general validity for the target machine.
760 Register and memory references must have mode MODE in order to be valid,
761 but some constants have no machine mode and are valid for any mode.
763 If MODE is VOIDmode, OP is checked for validity for whatever mode
766 The main use of this function is as a predicate in match_operand
767 expressions in the machine description.
769 For an explanation of this function's behavior for registers of
770 class NO_REGS, see the comment for `register_operand'. */
773 general_operand (op, mode)
775 enum machine_mode mode;
777 register enum rtx_code code = GET_CODE (op);
778 int mode_altering_drug = 0;
780 if (mode == VOIDmode)
781 mode = GET_MODE (op);
783 /* Don't accept CONST_INT or anything similar
784 if the caller wants something floating. */
785 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
786 && GET_MODE_CLASS (mode) != MODE_INT
787 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
791 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
792 #ifdef LEGITIMATE_PIC_OPERAND_P
793 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
795 && LEGITIMATE_CONSTANT_P (op));
797 /* Except for certain constants with VOIDmode, already checked for,
798 OP's mode must match MODE if MODE specifies a mode. */
800 if (GET_MODE (op) != mode)
805 #ifdef INSN_SCHEDULING
806 /* On machines that have insn scheduling, we want all memory
807 reference to be explicit, so outlaw paradoxical SUBREGs. */
808 if (GET_CODE (SUBREG_REG (op)) == MEM
809 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
813 op = SUBREG_REG (op);
814 code = GET_CODE (op);
816 /* No longer needed, since (SUBREG (MEM...))
817 will load the MEM into a reload reg in the MEM's own mode. */
818 mode_altering_drug = 1;
823 /* A register whose class is NO_REGS is not a general operand. */
824 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
825 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
829 register rtx y = XEXP (op, 0);
830 if (! volatile_ok && MEM_VOLATILE_P (op))
832 if (GET_CODE (y) == ADDRESSOF)
834 /* Use the mem's mode, since it will be reloaded thus. */
835 mode = GET_MODE (op);
836 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
839 /* Pretend this is an operand for now; we'll run force_operand
840 on its replacement in fixup_var_refs_1. */
841 if (code == ADDRESSOF)
847 if (mode_altering_drug)
848 return ! mode_dependent_address_p (XEXP (op, 0));
852 /* Return 1 if OP is a valid memory address for a memory reference
855 The main use of this function is as a predicate in match_operand
856 expressions in the machine description. */
859 address_operand (op, mode)
861 enum machine_mode mode;
863 return memory_address_p (mode, op);
866 /* Return 1 if OP is a register reference of mode MODE.
867 If MODE is VOIDmode, accept a register in any mode.
869 The main use of this function is as a predicate in match_operand
870 expressions in the machine description.
872 As a special exception, registers whose class is NO_REGS are
873 not accepted by `register_operand'. The reason for this change
874 is to allow the representation of special architecture artifacts
875 (such as a condition code register) without extending the rtl
876 definitions. Since registers of class NO_REGS cannot be used
877 as registers in any case where register classes are examined,
878 it is most consistent to keep this function from accepting them. */
881 register_operand (op, mode)
883 enum machine_mode mode;
885 if (GET_MODE (op) != mode && mode != VOIDmode)
888 if (GET_CODE (op) == SUBREG)
890 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
891 because it is guaranteed to be reloaded into one.
892 Just make sure the MEM is valid in itself.
893 (Ideally, (SUBREG (MEM)...) should not exist after reload,
894 but currently it does result from (SUBREG (REG)...) where the
895 reg went on the stack.) */
896 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
897 return general_operand (op, mode);
899 #ifdef CLASS_CANNOT_CHANGE_SIZE
900 if (GET_CODE (SUBREG_REG (op)) == REG
901 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
902 && TEST_HARD_REG_BIT (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
903 REGNO (SUBREG_REG (op)))
904 && (GET_MODE_SIZE (mode)
905 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
906 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
907 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
911 op = SUBREG_REG (op);
914 /* We don't consider registers whose class is NO_REGS
915 to be a register operand. */
916 return (GET_CODE (op) == REG
917 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
918 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
921 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
922 or a hard register. */
925 scratch_operand (op, mode)
927 enum machine_mode mode;
929 return (GET_MODE (op) == mode
930 && (GET_CODE (op) == SCRATCH
931 || (GET_CODE (op) == REG
932 && REGNO (op) < FIRST_PSEUDO_REGISTER)));
935 /* Return 1 if OP is a valid immediate operand for mode MODE.
937 The main use of this function is as a predicate in match_operand
938 expressions in the machine description. */
941 immediate_operand (op, mode)
943 enum machine_mode mode;
945 /* Don't accept CONST_INT or anything similar
946 if the caller wants something floating. */
947 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
948 && GET_MODE_CLASS (mode) != MODE_INT
949 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
952 return (CONSTANT_P (op)
953 && (GET_MODE (op) == mode || mode == VOIDmode
954 || GET_MODE (op) == VOIDmode)
955 #ifdef LEGITIMATE_PIC_OPERAND_P
956 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
958 && LEGITIMATE_CONSTANT_P (op));
961 /* Returns 1 if OP is an operand that is a CONST_INT. */
964 const_int_operand (op, mode)
966 enum machine_mode mode;
968 return GET_CODE (op) == CONST_INT;
971 /* Returns 1 if OP is an operand that is a constant integer or constant
972 floating-point number. */
975 const_double_operand (op, mode)
977 enum machine_mode mode;
979 /* Don't accept CONST_INT or anything similar
980 if the caller wants something floating. */
981 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
982 && GET_MODE_CLASS (mode) != MODE_INT
983 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
986 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
987 && (mode == VOIDmode || GET_MODE (op) == mode
988 || GET_MODE (op) == VOIDmode));
991 /* Return 1 if OP is a general operand that is not an immediate operand. */
994 nonimmediate_operand (op, mode)
996 enum machine_mode mode;
998 return (general_operand (op, mode) && ! CONSTANT_P (op));
1001 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1004 nonmemory_operand (op, mode)
1006 enum machine_mode mode;
1008 if (CONSTANT_P (op))
1010 /* Don't accept CONST_INT or anything similar
1011 if the caller wants something floating. */
1012 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1013 && GET_MODE_CLASS (mode) != MODE_INT
1014 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1017 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
1018 #ifdef LEGITIMATE_PIC_OPERAND_P
1019 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1021 && LEGITIMATE_CONSTANT_P (op));
1024 if (GET_MODE (op) != mode && mode != VOIDmode)
1027 if (GET_CODE (op) == SUBREG)
1029 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1030 because it is guaranteed to be reloaded into one.
1031 Just make sure the MEM is valid in itself.
1032 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1033 but currently it does result from (SUBREG (REG)...) where the
1034 reg went on the stack.) */
1035 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1036 return general_operand (op, mode);
1037 op = SUBREG_REG (op);
1040 /* We don't consider registers whose class is NO_REGS
1041 to be a register operand. */
1042 return (GET_CODE (op) == REG
1043 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1044 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1047 /* Return 1 if OP is a valid operand that stands for pushing a
1048 value of mode MODE onto the stack.
1050 The main use of this function is as a predicate in match_operand
1051 expressions in the machine description. */
1054 push_operand (op, mode)
1056 enum machine_mode mode;
1058 if (GET_CODE (op) != MEM)
1061 if (GET_MODE (op) != mode)
1066 if (GET_CODE (op) != STACK_PUSH_CODE)
1069 return XEXP (op, 0) == stack_pointer_rtx;
1072 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1075 memory_address_p (mode, addr)
1076 enum machine_mode mode;
1079 if (GET_CODE (addr) == ADDRESSOF)
1082 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1089 /* Return 1 if OP is a valid memory reference with mode MODE,
1090 including a valid address.
1092 The main use of this function is as a predicate in match_operand
1093 expressions in the machine description. */
1096 memory_operand (op, mode)
1098 enum machine_mode mode;
1102 if (! reload_completed)
1103 /* Note that no SUBREG is a memory operand before end of reload pass,
1104 because (SUBREG (MEM...)) forces reloading into a register. */
1105 return GET_CODE (op) == MEM && general_operand (op, mode);
1107 if (mode != VOIDmode && GET_MODE (op) != mode)
1111 if (GET_CODE (inner) == SUBREG)
1112 inner = SUBREG_REG (inner);
1114 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1117 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1118 that is, a memory reference whose address is a general_operand. */
1121 indirect_operand (op, mode)
1123 enum machine_mode mode;
1125 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1126 if (! reload_completed
1127 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1129 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1130 rtx inner = SUBREG_REG (op);
1132 if (BYTES_BIG_ENDIAN)
1133 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1134 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1136 if (mode != VOIDmode && GET_MODE (op) != mode)
1139 /* The only way that we can have a general_operand as the resulting
1140 address is if OFFSET is zero and the address already is an operand
1141 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1144 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1145 || (GET_CODE (XEXP (inner, 0)) == PLUS
1146 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1147 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1148 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1151 return (GET_CODE (op) == MEM
1152 && memory_operand (op, mode)
1153 && general_operand (XEXP (op, 0), Pmode));
1156 /* Return 1 if this is a comparison operator. This allows the use of
1157 MATCH_OPERATOR to recognize all the branch insns. */
1160 comparison_operator (op, mode)
1162 enum machine_mode mode;
1164 return ((mode == VOIDmode || GET_MODE (op) == mode)
1165 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1168 /* If BODY is an insn body that uses ASM_OPERANDS,
1169 return the number of operands (both input and output) in the insn.
1170 Otherwise return -1. */
1173 asm_noperands (body)
1176 if (GET_CODE (body) == ASM_OPERANDS)
1177 /* No output operands: return number of input operands. */
1178 return ASM_OPERANDS_INPUT_LENGTH (body);
1179 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1180 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1181 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1182 else if (GET_CODE (body) == PARALLEL
1183 && GET_CODE (XVECEXP (body, 0, 0)) == SET
1184 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1186 /* Multiple output operands, or 1 output plus some clobbers:
1187 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1191 /* Count backwards through CLOBBERs to determine number of SETs. */
1192 for (i = XVECLEN (body, 0); i > 0; i--)
1194 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1196 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1200 /* N_SETS is now number of output operands. */
1203 /* Verify that all the SETs we have
1204 came from a single original asm_operands insn
1205 (so that invalid combinations are blocked). */
1206 for (i = 0; i < n_sets; i++)
1208 rtx elt = XVECEXP (body, 0, i);
1209 if (GET_CODE (elt) != SET)
1211 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1213 /* If these ASM_OPERANDS rtx's came from different original insns
1214 then they aren't allowed together. */
1215 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1216 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1219 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1222 else if (GET_CODE (body) == PARALLEL
1223 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1225 /* 0 outputs, but some clobbers:
1226 body is [(asm_operands ...) (clobber (reg ...))...]. */
1229 /* Make sure all the other parallel things really are clobbers. */
1230 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1231 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1234 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1240 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1241 copy its operands (both input and output) into the vector OPERANDS,
1242 the locations of the operands within the insn into the vector OPERAND_LOCS,
1243 and the constraints for the operands into CONSTRAINTS.
1244 Write the modes of the operands into MODES.
1245 Return the assembler-template.
1247 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1248 we don't store that info. */
1251 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1256 enum machine_mode *modes;
1262 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1264 rtx asmop = SET_SRC (body);
1265 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1267 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1269 for (i = 1; i < noperands; i++)
1272 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1274 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1276 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1278 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1281 /* The output is in the SET.
1282 Its constraint is in the ASM_OPERANDS itself. */
1284 operands[0] = SET_DEST (body);
1286 operand_locs[0] = &SET_DEST (body);
1288 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1290 modes[0] = GET_MODE (SET_DEST (body));
1291 template = ASM_OPERANDS_TEMPLATE (asmop);
1293 else if (GET_CODE (body) == ASM_OPERANDS)
1296 /* No output operands: BODY is (asm_operands ....). */
1298 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1300 /* The input operands are found in the 1st element vector. */
1301 /* Constraints for inputs are in the 2nd element vector. */
1302 for (i = 0; i < noperands; i++)
1305 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1307 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1309 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1311 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1313 template = ASM_OPERANDS_TEMPLATE (asmop);
1315 else if (GET_CODE (body) == PARALLEL
1316 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1318 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1319 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1320 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1321 int nout = 0; /* Does not include CLOBBERs. */
1323 /* At least one output, plus some CLOBBERs. */
1325 /* The outputs are in the SETs.
1326 Their constraints are in the ASM_OPERANDS itself. */
1327 for (i = 0; i < nparallel; i++)
1329 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1330 break; /* Past last SET */
1333 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1335 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1337 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1339 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1343 for (i = 0; i < nin; i++)
1346 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1348 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1350 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1352 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1355 template = ASM_OPERANDS_TEMPLATE (asmop);
1357 else if (GET_CODE (body) == PARALLEL
1358 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1360 /* No outputs, but some CLOBBERs. */
1362 rtx asmop = XVECEXP (body, 0, 0);
1363 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1365 for (i = 0; i < nin; i++)
1368 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1370 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1372 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1374 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1377 template = ASM_OPERANDS_TEMPLATE (asmop);
1383 /* Given an rtx *P, if it is a sum containing an integer constant term,
1384 return the location (type rtx *) of the pointer to that constant term.
1385 Otherwise, return a null pointer. */
1388 find_constant_term_loc (p)
1392 register enum rtx_code code = GET_CODE (*p);
1394 /* If *P IS such a constant term, P is its location. */
1396 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1400 /* Otherwise, if not a sum, it has no constant term. */
1402 if (GET_CODE (*p) != PLUS)
1405 /* If one of the summands is constant, return its location. */
1407 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1408 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1411 /* Otherwise, check each summand for containing a constant term. */
1413 if (XEXP (*p, 0) != 0)
1415 tem = find_constant_term_loc (&XEXP (*p, 0));
1420 if (XEXP (*p, 1) != 0)
1422 tem = find_constant_term_loc (&XEXP (*p, 1));
1430 /* Return 1 if OP is a memory reference
1431 whose address contains no side effects
1432 and remains valid after the addition
1433 of a positive integer less than the
1434 size of the object being referenced.
1436 We assume that the original address is valid and do not check it.
1438 This uses strict_memory_address_p as a subroutine, so
1439 don't use it before reload. */
1442 offsettable_memref_p (op)
1445 return ((GET_CODE (op) == MEM)
1446 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1449 /* Similar, but don't require a strictly valid mem ref:
1450 consider pseudo-regs valid as index or base regs. */
1453 offsettable_nonstrict_memref_p (op)
1456 return ((GET_CODE (op) == MEM)
1457 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1460 /* Return 1 if Y is a memory address which contains no side effects
1461 and would remain valid after the addition of a positive integer
1462 less than the size of that mode.
1464 We assume that the original address is valid and do not check it.
1465 We do check that it is valid for narrower modes.
1467 If STRICTP is nonzero, we require a strictly valid address,
1468 for the sake of use in reload.c. */
1471 offsettable_address_p (strictp, mode, y)
1473 enum machine_mode mode;
1476 register enum rtx_code ycode = GET_CODE (y);
1480 int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p);
1482 if (CONSTANT_ADDRESS_P (y))
1485 /* Adjusting an offsettable address involves changing to a narrower mode.
1486 Make sure that's OK. */
1488 if (mode_dependent_address_p (y))
1491 /* If the expression contains a constant term,
1492 see if it remains valid when max possible offset is added. */
1494 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1499 *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1);
1500 /* Use QImode because an odd displacement may be automatically invalid
1501 for any wider mode. But it should be valid for a single byte. */
1502 good = (*addressp) (QImode, y);
1504 /* In any case, restore old contents of memory. */
1509 if (ycode == PRE_DEC || ycode == PRE_INC
1510 || ycode == POST_DEC || ycode == POST_INC)
1513 /* The offset added here is chosen as the maximum offset that
1514 any instruction could need to add when operating on something
1515 of the specified mode. We assume that if Y and Y+c are
1516 valid addresses then so is Y+d for all 0<d<c. */
1518 z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1);
1520 /* Use QImode because an odd displacement may be automatically invalid
1521 for any wider mode. But it should be valid for a single byte. */
1522 return (*addressp) (QImode, z);
1525 /* Return 1 if ADDR is an address-expression whose effect depends
1526 on the mode of the memory reference it is used in.
1528 Autoincrement addressing is a typical example of mode-dependence
1529 because the amount of the increment depends on the mode. */
1532 mode_dependent_address_p (addr)
1535 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1541 /* Return 1 if OP is a general operand
1542 other than a memory ref with a mode dependent address. */
1545 mode_independent_operand (op, mode)
1546 enum machine_mode mode;
1551 if (! general_operand (op, mode))
1554 if (GET_CODE (op) != MEM)
1557 addr = XEXP (op, 0);
1558 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
1564 /* Given an operand OP that is a valid memory reference
1565 which satisfies offsettable_memref_p,
1566 return a new memory reference whose address has been adjusted by OFFSET.
1567 OFFSET should be positive and less than the size of the object referenced.
1571 adj_offsettable_operand (op, offset)
1575 register enum rtx_code code = GET_CODE (op);
1579 register rtx y = XEXP (op, 0);
1582 if (CONSTANT_ADDRESS_P (y))
1584 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
1585 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1589 if (GET_CODE (y) == PLUS)
1592 register rtx *const_loc;
1596 const_loc = find_constant_term_loc (&z);
1599 *const_loc = plus_constant_for_output (*const_loc, offset);
1604 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
1605 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1611 #ifdef REGISTER_CONSTRAINTS
1613 /* Check the operands of an insn (found in recog_operands)
1614 against the insn's operand constraints (found via INSN_CODE_NUM)
1615 and return 1 if they are valid.
1617 WHICH_ALTERNATIVE is set to a number which indicates which
1618 alternative of constraints was matched: 0 for the first alternative,
1619 1 for the next, etc.
1621 In addition, when two operands are match
1622 and it happens that the output operand is (reg) while the
1623 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
1624 make the output operand look like the input.
1625 This is because the output operand is the one the template will print.
1627 This is used in final, just before printing the assembler code and by
1628 the routines that determine an insn's attribute.
1630 If STRICT is a positive non-zero value, it means that we have been
1631 called after reload has been completed. In that case, we must
1632 do all checks strictly. If it is zero, it means that we have been called
1633 before reload has completed. In that case, we first try to see if we can
1634 find an alternative that matches strictly. If not, we try again, this
1635 time assuming that reload will fix up the insn. This provides a "best
1636 guess" for the alternative and is used to compute attributes of insns prior
1637 to reload. A negative value of STRICT is used for this internal call. */
1645 constrain_operands (insn_code_num, strict)
1649 char *constraints[MAX_RECOG_OPERANDS];
1650 int matching_operands[MAX_RECOG_OPERANDS];
1651 enum op_type {OP_IN, OP_OUT, OP_INOUT} op_types[MAX_RECOG_OPERANDS];
1652 int earlyclobber[MAX_RECOG_OPERANDS];
1654 int noperands = insn_n_operands[insn_code_num];
1656 struct funny_match funny_match[MAX_RECOG_OPERANDS];
1657 int funny_match_index;
1658 int nalternatives = insn_n_alternatives[insn_code_num];
1660 if (noperands == 0 || nalternatives == 0)
1663 for (c = 0; c < noperands; c++)
1665 constraints[c] = insn_operand_constraint[insn_code_num][c];
1666 matching_operands[c] = -1;
1667 op_types[c] = OP_IN;
1670 which_alternative = 0;
1672 while (which_alternative < nalternatives)
1676 funny_match_index = 0;
1678 for (opno = 0; opno < noperands; opno++)
1680 register rtx op = recog_operand[opno];
1681 enum machine_mode mode = GET_MODE (op);
1682 register char *p = constraints[opno];
1687 earlyclobber[opno] = 0;
1689 /* A unary operator may be accepted by the predicate, but it
1690 is irrelevant for matching constraints. */
1691 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
1694 if (GET_CODE (op) == SUBREG)
1696 if (GET_CODE (SUBREG_REG (op)) == REG
1697 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
1698 offset = SUBREG_WORD (op);
1699 op = SUBREG_REG (op);
1702 /* An empty constraint or empty alternative
1703 allows anything which matched the pattern. */
1704 if (*p == 0 || *p == ',')
1707 while (*p && (c = *p++) != ',')
1717 /* Ignore rest of this alternative as far as
1718 constraint checking is concerned. */
1719 while (*p && *p != ',')
1724 op_types[opno] = OP_OUT;
1728 op_types[opno] = OP_INOUT;
1732 earlyclobber[opno] = 1;
1740 /* This operand must be the same as a previous one.
1741 This kind of constraint is used for instructions such
1742 as add when they take only two operands.
1744 Note that the lower-numbered operand is passed first.
1746 If we are not testing strictly, assume that this constraint
1747 will be satisfied. */
1751 val = operands_match_p (recog_operand[c - '0'],
1752 recog_operand[opno]);
1754 matching_operands[opno] = c - '0';
1755 matching_operands[c - '0'] = opno;
1759 /* If output is *x and input is *--x,
1760 arrange later to change the output to *--x as well,
1761 since the output op is the one that will be printed. */
1762 if (val == 2 && strict > 0)
1764 funny_match[funny_match_index].this = opno;
1765 funny_match[funny_match_index++].other = c - '0';
1770 /* p is used for address_operands. When we are called by
1771 gen_reload, no one will have checked that the address is
1772 strictly valid, i.e., that all pseudos requiring hard regs
1773 have gotten them. */
1775 || (strict_memory_address_p
1776 (insn_operand_mode[insn_code_num][opno], op)))
1780 /* No need to check general_operand again;
1781 it was done in insn-recog.c. */
1783 /* Anything goes unless it is a REG and really has a hard reg
1784 but the hard reg is not in the class GENERAL_REGS. */
1786 || GENERAL_REGS == ALL_REGS
1787 || GET_CODE (op) != REG
1788 || (reload_in_progress
1789 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1790 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
1797 && GET_CODE (op) == REG
1798 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1799 || (strict == 0 && GET_CODE (op) == SCRATCH)
1800 || (GET_CODE (op) == REG
1801 && ((GENERAL_REGS == ALL_REGS
1802 && REGNO (op) < FIRST_PSEUDO_REGISTER)
1803 || reg_fits_class_p (op, GENERAL_REGS,
1809 /* This is used for a MATCH_SCRATCH in the cases when
1810 we don't actually need anything. So anything goes
1816 if (GET_CODE (op) == MEM
1817 /* Before reload, accept what reload can turn into mem. */
1818 || (strict < 0 && CONSTANT_P (op))
1819 /* During reload, accept a pseudo */
1820 || (reload_in_progress && GET_CODE (op) == REG
1821 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
1826 if (GET_CODE (op) == MEM
1827 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1828 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1833 if (GET_CODE (op) == MEM
1834 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1835 || GET_CODE (XEXP (op, 0)) == POST_INC))
1840 #ifndef REAL_ARITHMETIC
1841 /* Match any CONST_DOUBLE, but only if
1842 we can examine the bits of it reliably. */
1843 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1844 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1845 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1848 if (GET_CODE (op) == CONST_DOUBLE)
1853 if (GET_CODE (op) == CONST_DOUBLE)
1859 if (GET_CODE (op) == CONST_DOUBLE
1860 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1865 if (GET_CODE (op) == CONST_INT
1866 || (GET_CODE (op) == CONST_DOUBLE
1867 && GET_MODE (op) == VOIDmode))
1870 if (CONSTANT_P (op))
1875 if (GET_CODE (op) == CONST_INT
1876 || (GET_CODE (op) == CONST_DOUBLE
1877 && GET_MODE (op) == VOIDmode))
1889 if (GET_CODE (op) == CONST_INT
1890 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1894 #ifdef EXTRA_CONSTRAINT
1900 if (EXTRA_CONSTRAINT (op, c))
1906 if (GET_CODE (op) == MEM
1907 && ((strict > 0 && ! offsettable_memref_p (op))
1909 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
1910 || (reload_in_progress
1911 && !(GET_CODE (op) == REG
1912 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
1917 if ((strict > 0 && offsettable_memref_p (op))
1918 || (strict == 0 && offsettable_nonstrict_memref_p (op))
1919 /* Before reload, accept what reload can handle. */
1921 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
1922 /* During reload, accept a pseudo */
1923 || (reload_in_progress && GET_CODE (op) == REG
1924 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
1931 && GET_CODE (op) == REG
1932 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1933 || (strict == 0 && GET_CODE (op) == SCRATCH)
1934 || (GET_CODE (op) == REG
1935 && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c),
1940 constraints[opno] = p;
1941 /* If this operand did not win somehow,
1942 this alternative loses. */
1946 /* This alternative won; the operands are ok.
1947 Change whichever operands this alternative says to change. */
1952 /* See if any earlyclobber operand conflicts with some other
1956 for (eopno = 0; eopno < noperands; eopno++)
1957 /* Ignore earlyclobber operands now in memory,
1958 because we would often report failure when we have
1959 two memory operands, one of which was formerly a REG. */
1960 if (earlyclobber[eopno]
1961 && GET_CODE (recog_operand[eopno]) == REG)
1962 for (opno = 0; opno < noperands; opno++)
1963 if ((GET_CODE (recog_operand[opno]) == MEM
1964 || op_types[opno] != OP_OUT)
1966 /* Ignore things like match_operator operands. */
1967 && *insn_operand_constraint[insn_code_num][opno] != 0
1968 && ! (matching_operands[opno] == eopno
1969 && operands_match_p (recog_operand[opno],
1970 recog_operand[eopno]))
1971 && ! safe_from_earlyclobber (recog_operand[opno],
1972 recog_operand[eopno]))
1977 while (--funny_match_index >= 0)
1979 recog_operand[funny_match[funny_match_index].other]
1980 = recog_operand[funny_match[funny_match_index].this];
1987 which_alternative++;
1990 /* If we are about to reject this, but we are not to test strictly,
1991 try a very loose test. Only return failure if it fails also. */
1993 return constrain_operands (insn_code_num, -1);
1998 /* Return 1 iff OPERAND (assumed to be a REG rtx)
1999 is a hard reg in class CLASS when its regno is offset by OFFSET
2000 and changed to mode MODE.
2001 If REG occupies multiple hard regs, all of them must be in CLASS. */
2004 reg_fits_class_p (operand, class, offset, mode)
2006 register enum reg_class class;
2008 enum machine_mode mode;
2010 register int regno = REGNO (operand);
2011 if (regno < FIRST_PSEUDO_REGISTER
2012 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2017 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2019 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2028 #endif /* REGISTER_CONSTRAINTS */