1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
43 #include "diagnostic-core.h"
49 #include "tree-pass.h"
53 static int reload_cse_noop_set_p (rtx);
54 static void reload_cse_simplify (rtx, rtx);
55 static void reload_cse_regs_1 (rtx);
56 static int reload_cse_simplify_set (rtx, rtx);
57 static int reload_cse_simplify_operands (rtx, rtx);
59 static void reload_combine (void);
60 static void reload_combine_note_use (rtx *, rtx, int, rtx);
61 static void reload_combine_note_store (rtx, const_rtx, void *);
63 static bool reload_cse_move2add (rtx);
64 static void move2add_note_store (rtx, const_rtx, void *);
66 /* Call cse / combine like post-reload optimization phases.
67 FIRST is the first instruction. */
69 reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
72 reload_cse_regs_1 (first);
74 moves_converted = reload_cse_move2add (first);
75 if (flag_expensive_optimizations)
79 reload_cse_regs_1 (first);
83 /* See whether a single set SET is a noop. */
85 reload_cse_noop_set_p (rtx set)
87 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
90 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
93 /* Try to simplify INSN. */
95 reload_cse_simplify (rtx insn, rtx testreg)
97 rtx body = PATTERN (insn);
99 if (GET_CODE (body) == SET)
103 /* Simplify even if we may think it is a no-op.
104 We may think a memory load of a value smaller than WORD_SIZE
105 is redundant because we haven't taken into account possible
106 implicit extension. reload_cse_simplify_set() will bring
107 this out, so it's safer to simplify before we delete. */
108 count += reload_cse_simplify_set (body, insn);
110 if (!count && reload_cse_noop_set_p (body))
112 rtx value = SET_DEST (body);
114 && ! REG_FUNCTION_VALUE_P (value))
116 delete_insn_and_edges (insn);
121 apply_change_group ();
123 reload_cse_simplify_operands (insn, testreg);
125 else if (GET_CODE (body) == PARALLEL)
129 rtx value = NULL_RTX;
131 /* Registers mentioned in the clobber list for an asm cannot be reused
132 within the body of the asm. Invalidate those registers now so that
133 we don't try to substitute values for them. */
134 if (asm_noperands (body) >= 0)
136 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
138 rtx part = XVECEXP (body, 0, i);
139 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
140 cselib_invalidate_rtx (XEXP (part, 0));
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
148 rtx part = XVECEXP (body, 0, i);
149 if (GET_CODE (part) == SET)
151 if (! reload_cse_noop_set_p (part))
153 if (REG_P (SET_DEST (part))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
158 value = SET_DEST (part);
161 else if (GET_CODE (part) != CLOBBER)
167 delete_insn_and_edges (insn);
168 /* We're done with this insn. */
172 /* It's not a no-op, but we can try to simplify it. */
173 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
174 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
175 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
178 apply_change_group ();
180 reload_cse_simplify_operands (insn, testreg);
184 /* Do a very simple CSE pass over the hard registers.
186 This function detects no-op moves where we happened to assign two
187 different pseudo-registers to the same hard register, and then
188 copied one to the other. Reload will generate a useless
189 instruction copying a register to itself.
191 This function also detects cases where we load a value from memory
192 into two different registers, and (if memory is more expensive than
193 registers) changes it to simply copy the first register into the
196 Another optimization is performed that scans the operands of each
197 instruction to see whether the value is already available in a
198 hard register. It then replaces the operand with the hard register
199 if possible, much like an optional reload would. */
202 reload_cse_regs_1 (rtx first)
205 rtx testreg = gen_rtx_REG (VOIDmode, -1);
207 cselib_init (CSELIB_RECORD_MEMORY);
208 init_alias_analysis ();
210 for (insn = first; insn; insn = NEXT_INSN (insn))
213 reload_cse_simplify (insn, testreg);
215 cselib_process_insn (insn);
219 end_alias_analysis ();
223 /* Try to simplify a single SET instruction. SET is the set pattern.
224 INSN is the instruction it came from.
225 This function only handles one case: if we set a register to a value
226 which is not a register, we try to find that value in some other register
227 and change the set into a register copy. */
230 reload_cse_simplify_set (rtx set, rtx insn)
235 enum reg_class dclass;
238 struct elt_loc_list *l;
239 #ifdef LOAD_EXTEND_OP
240 enum rtx_code extend_op = UNKNOWN;
242 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
244 dreg = true_regnum (SET_DEST (set));
249 if (side_effects_p (src) || true_regnum (src) >= 0)
252 dclass = REGNO_REG_CLASS (dreg);
254 #ifdef LOAD_EXTEND_OP
255 /* When replacing a memory with a register, we need to honor assumptions
256 that combine made wrt the contents of sign bits. We'll do this by
257 generating an extend instruction instead of a reg->reg copy. Thus
258 the destination must be a register that we can widen. */
260 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
261 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
262 && !REG_P (SET_DEST (set)))
266 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
270 /* If memory loads are cheaper than register copies, don't change them. */
272 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
273 else if (REG_P (src))
274 old_cost = register_move_cost (GET_MODE (src),
275 REGNO_REG_CLASS (REGNO (src)), dclass);
277 old_cost = rtx_cost (src, SET, speed);
279 for (l = val->locs; l; l = l->next)
281 rtx this_rtx = l->loc;
284 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
286 #ifdef LOAD_EXTEND_OP
287 if (extend_op != UNKNOWN)
289 HOST_WIDE_INT this_val;
291 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
292 constants, such as SYMBOL_REF, cannot be extended. */
293 if (!CONST_INT_P (this_rtx))
296 this_val = INTVAL (this_rtx);
300 this_val &= GET_MODE_MASK (GET_MODE (src));
303 /* ??? In theory we're already extended. */
304 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
309 this_rtx = GEN_INT (this_val);
312 this_cost = rtx_cost (this_rtx, SET, speed);
314 else if (REG_P (this_rtx))
316 #ifdef LOAD_EXTEND_OP
317 if (extend_op != UNKNOWN)
319 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
320 this_cost = rtx_cost (this_rtx, SET, speed);
324 this_cost = register_move_cost (GET_MODE (this_rtx),
325 REGNO_REG_CLASS (REGNO (this_rtx)),
331 /* If equal costs, prefer registers over anything else. That
332 tends to lead to smaller instructions on some machines. */
333 if (this_cost < old_cost
334 || (this_cost == old_cost
336 && !REG_P (SET_SRC (set))))
338 #ifdef LOAD_EXTEND_OP
339 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
340 && extend_op != UNKNOWN
341 #ifdef CANNOT_CHANGE_MODE_CLASS
342 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
344 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
348 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
349 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
350 validate_change (insn, &SET_DEST (set), wide_dest, 1);
354 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
355 old_cost = this_cost, did_change = 1;
362 /* Try to replace operands in INSN with equivalent values that are already
363 in registers. This can be viewed as optional reloading.
365 For each non-register operand in the insn, see if any hard regs are
366 known to be equivalent to that operand. Record the alternatives which
367 can accept these hard registers. Among all alternatives, select the
368 ones which are better or equal to the one currently matching, where
369 "better" is in terms of '?' and '!' constraints. Among the remaining
370 alternatives, select the one which replaces most operands with
374 reload_cse_simplify_operands (rtx insn, rtx testreg)
378 /* For each operand, all registers that are equivalent to it. */
379 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
381 const char *constraints[MAX_RECOG_OPERANDS];
383 /* Vector recording how bad an alternative is. */
384 int *alternative_reject;
385 /* Vector recording how many registers can be introduced by choosing
387 int *alternative_nregs;
388 /* Array of vectors recording, for each operand and each alternative,
389 which hard register to substitute, or -1 if the operand should be
391 int *op_alt_regno[MAX_RECOG_OPERANDS];
392 /* Array of alternatives, sorted in order of decreasing desirability. */
393 int *alternative_order;
397 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
400 /* Figure out which alternative currently matches. */
401 if (! constrain_operands (1))
402 fatal_insn_not_found (insn);
404 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
405 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
406 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
407 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
408 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
410 /* For each operand, find out which regs are equivalent. */
411 for (i = 0; i < recog_data.n_operands; i++)
414 struct elt_loc_list *l;
417 CLEAR_HARD_REG_SET (equiv_regs[i]);
419 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
420 right, so avoid the problem here. Likewise if we have a constant
421 and the insn pattern doesn't tell us the mode we need. */
422 if (LABEL_P (recog_data.operand[i])
423 || (CONSTANT_P (recog_data.operand[i])
424 && recog_data.operand_mode[i] == VOIDmode))
427 op = recog_data.operand[i];
428 #ifdef LOAD_EXTEND_OP
430 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
431 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
433 rtx set = single_set (insn);
435 /* We might have multiple sets, some of which do implicit
436 extension. Punt on this for now. */
439 /* If the destination is also a MEM or a STRICT_LOW_PART, no
441 Also, if there is an explicit extension, we don't have to
442 worry about an implicit one. */
443 else if (MEM_P (SET_DEST (set))
444 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
445 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
446 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
447 ; /* Continue ordinary processing. */
448 #ifdef CANNOT_CHANGE_MODE_CLASS
449 /* If the register cannot change mode to word_mode, it follows that
450 it cannot have been used in word_mode. */
451 else if (REG_P (SET_DEST (set))
452 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
454 REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
455 ; /* Continue ordinary processing. */
457 /* If this is a straight load, make the extension explicit. */
458 else if (REG_P (SET_DEST (set))
459 && recog_data.n_operands == 2
460 && SET_SRC (set) == op
461 && SET_DEST (set) == recog_data.operand[1-i])
463 validate_change (insn, recog_data.operand_loc[i],
464 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)),
467 validate_change (insn, recog_data.operand_loc[1-i],
468 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
470 if (! apply_change_group ())
472 return reload_cse_simplify_operands (insn, testreg);
475 /* ??? There might be arithmetic operations with memory that are
476 safe to optimize, but is it worth the trouble? */
479 #endif /* LOAD_EXTEND_OP */
480 v = cselib_lookup (op, recog_data.operand_mode[i], 0);
484 for (l = v->locs; l; l = l->next)
486 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
489 for (i = 0; i < recog_data.n_operands; i++)
491 enum machine_mode mode;
495 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
496 for (j = 0; j < recog_data.n_alternatives; j++)
497 op_alt_regno[i][j] = -1;
499 p = constraints[i] = recog_data.constraints[i];
500 mode = recog_data.operand_mode[i];
502 /* Add the reject values for each alternative given by the constraints
511 alternative_reject[j] += 3;
513 alternative_reject[j] += 300;
516 /* We won't change operands which are already registers. We
517 also don't want to modify output operands. */
518 regno = true_regnum (recog_data.operand[i]);
520 || constraints[i][0] == '='
521 || constraints[i][0] == '+')
524 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
526 enum reg_class rclass = NO_REGS;
528 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
531 SET_REGNO_RAW (testreg, regno);
532 PUT_MODE (testreg, mode);
534 /* We found a register equal to this operand. Now look for all
535 alternatives that can accept this register and have not been
536 assigned a register they can use yet. */
545 case '=': case '+': case '?':
546 case '#': case '&': case '!':
548 case '0': case '1': case '2': case '3': case '4':
549 case '5': case '6': case '7': case '8': case '9':
550 case '<': case '>': case 'V': case 'o':
551 case 'E': case 'F': case 'G': case 'H':
552 case 's': case 'i': case 'n':
553 case 'I': case 'J': case 'K': case 'L':
554 case 'M': case 'N': case 'O': case 'P':
555 case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
556 /* These don't say anything we care about. */
560 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
565 = (reg_class_subunion
567 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
571 /* See if REGNO fits this alternative, and set it up as the
572 replacement register if we don't have one for this
573 alternative yet and the operand being replaced is not
574 a cheap CONST_INT. */
575 if (op_alt_regno[i][j] == -1
576 && recog_data.alternative_enabled_p[j]
577 && reg_fits_class_p (testreg, rclass, 0, mode)
578 && (!CONST_INT_P (recog_data.operand[i])
579 || (rtx_cost (recog_data.operand[i], SET,
580 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
581 > rtx_cost (testreg, SET,
582 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))))))
584 alternative_nregs[j]++;
585 op_alt_regno[i][j] = regno;
591 p += CONSTRAINT_LEN (c, p);
599 /* Record all alternatives which are better or equal to the currently
600 matching one in the alternative_order array. */
601 for (i = j = 0; i < recog_data.n_alternatives; i++)
602 if (alternative_reject[i] <= alternative_reject[which_alternative])
603 alternative_order[j++] = i;
604 recog_data.n_alternatives = j;
606 /* Sort it. Given a small number of alternatives, a dumb algorithm
607 won't hurt too much. */
608 for (i = 0; i < recog_data.n_alternatives - 1; i++)
611 int best_reject = alternative_reject[alternative_order[i]];
612 int best_nregs = alternative_nregs[alternative_order[i]];
615 for (j = i + 1; j < recog_data.n_alternatives; j++)
617 int this_reject = alternative_reject[alternative_order[j]];
618 int this_nregs = alternative_nregs[alternative_order[j]];
620 if (this_reject < best_reject
621 || (this_reject == best_reject && this_nregs > best_nregs))
624 best_reject = this_reject;
625 best_nregs = this_nregs;
629 tmp = alternative_order[best];
630 alternative_order[best] = alternative_order[i];
631 alternative_order[i] = tmp;
634 /* Substitute the operands as determined by op_alt_regno for the best
636 j = alternative_order[0];
638 for (i = 0; i < recog_data.n_operands; i++)
640 enum machine_mode mode = recog_data.operand_mode[i];
641 if (op_alt_regno[i][j] == -1)
644 validate_change (insn, recog_data.operand_loc[i],
645 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
648 for (i = recog_data.n_dups - 1; i >= 0; i--)
650 int op = recog_data.dup_num[i];
651 enum machine_mode mode = recog_data.operand_mode[op];
653 if (op_alt_regno[op][j] == -1)
656 validate_change (insn, recog_data.dup_loc[i],
657 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
660 return apply_change_group ();
663 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
665 This code might also be useful when reload gave up on reg+reg addressing
666 because of clashes between the return register and INDEX_REG_CLASS. */
668 /* The maximum number of uses of a register we can keep track of to
669 replace them with reg+reg addressing. */
670 #define RELOAD_COMBINE_MAX_USES 16
672 /* Describes a recorded use of a register. */
675 /* The insn where a register has been used. */
677 /* Points to the memory reference enclosing the use, if any, NULL_RTX
680 /* Location of the register withing INSN. */
682 /* The reverse uid of the insn. */
686 /* If the register is used in some unknown fashion, USE_INDEX is negative.
687 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
688 indicates where it is first set or clobbered.
689 Otherwise, USE_INDEX is the index of the last encountered use of the
690 register (which is first among these we have seen since we scan backwards).
691 USE_RUID indicates the first encountered, i.e. last, of these uses.
692 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
693 with a constant offset; OFFSET contains this constant in that case.
694 STORE_RUID is always meaningful if we only want to use a value in a
695 register in a different place: it denotes the next insn in the insn
696 stream (i.e. the last encountered) that sets or clobbers the register.
697 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
700 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
706 bool all_offsets_match;
707 } reg_state[FIRST_PSEUDO_REGISTER];
709 /* Reverse linear uid. This is increased in reload_combine while scanning
710 the instructions from last to first. It is used to set last_label_ruid
711 and the store_ruid / use_ruid fields in reg_state. */
712 static int reload_combine_ruid;
714 /* The RUID of the last label we encountered in reload_combine. */
715 static int last_label_ruid;
717 /* The RUID of the last jump we encountered in reload_combine. */
718 static int last_jump_ruid;
720 /* The register numbers of the first and last index register. A value of
721 -1 in LAST_INDEX_REG indicates that we've previously computed these
722 values and found no suitable index registers. */
723 static int first_index_reg = -1;
724 static int last_index_reg;
726 #define LABEL_LIVE(LABEL) \
727 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
729 /* Subroutine of reload_combine_split_ruids, called to fix up a single
730 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
733 reload_combine_split_one_ruid (int *pruid, int split_ruid)
735 if (*pruid > split_ruid)
739 /* Called when we insert a new insn in a position we've already passed in
740 the scan. Examine all our state, increasing all ruids that are higher
741 than SPLIT_RUID by one in order to make room for a new insn. */
744 reload_combine_split_ruids (int split_ruid)
748 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
749 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
750 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
752 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
754 int j, idx = reg_state[i].use_index;
755 reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid);
756 reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid);
757 reload_combine_split_one_ruid (®_state[i].real_store_ruid,
761 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
763 reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid,
769 /* Called when we are about to rescan a previously encountered insn with
770 reload_combine_note_use after modifying some part of it. This clears all
771 information about uses in that particular insn. */
774 reload_combine_purge_insn_uses (rtx insn)
778 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
780 int j, k, idx = reg_state[i].use_index;
783 j = k = RELOAD_COMBINE_MAX_USES;
786 if (reg_state[i].reg_use[j].insn != insn)
790 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
793 reg_state[i].use_index = k;
797 /* Called when we need to forget about all uses of REGNO after an insn
798 which is identified by RUID. */
801 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
803 int j, k, idx = reg_state[regno].use_index;
806 j = k = RELOAD_COMBINE_MAX_USES;
809 if (reg_state[regno].reg_use[j].ruid >= ruid)
813 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
816 reg_state[regno].use_index = k;
819 /* Find the use of REGNO with the ruid that is highest among those
820 lower than RUID_LIMIT, and return it if it is the only use of this
821 reg in the insn. Return NULL otherwise. */
823 static struct reg_use *
824 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
826 int i, best_ruid = 0;
827 int use_idx = reg_state[regno].use_index;
828 struct reg_use *retval;
833 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
835 struct reg_use *use = reg_state[regno].reg_use + i;
836 int this_ruid = use->ruid;
837 if (this_ruid >= ruid_limit)
839 if (this_ruid > best_ruid)
841 best_ruid = this_ruid;
844 else if (this_ruid == best_ruid)
847 if (last_label_ruid >= best_ruid)
852 /* After we've moved an add insn, fix up any debug insns that occur
853 between the old location of the add and the new location. REG is
854 the destination register of the add insn; REPLACEMENT is the
855 SET_SRC of the add. FROM and TO specify the range in which we
856 should make this change on debug insns. */
859 fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
862 for (insn = from; insn != to; insn = NEXT_INSN (insn))
866 if (!DEBUG_INSN_P (insn))
869 t = INSN_VAR_LOCATION_LOC (insn);
870 t = simplify_replace_rtx (t, reg, replacement);
871 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
875 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
876 with SRC in the insn described by USE, taking costs into account. Return
877 true if we made the replacement. */
880 try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
882 rtx use_insn = use->insn;
883 rtx mem = use->containing_mem;
884 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
888 addr_space_t as = MEM_ADDR_SPACE (mem);
889 rtx oldaddr = XEXP (mem, 0);
890 rtx newaddr = NULL_RTX;
891 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
894 newaddr = simplify_replace_rtx (oldaddr, reg, src);
895 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
897 XEXP (mem, 0) = newaddr;
898 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
899 XEXP (mem, 0) = oldaddr;
900 if (new_cost <= old_cost
901 && validate_change (use_insn,
902 &XEXP (mem, 0), newaddr, 0))
908 rtx new_set = single_set (use_insn);
910 && REG_P (SET_DEST (new_set))
911 && GET_CODE (SET_SRC (new_set)) == PLUS
912 && REG_P (XEXP (SET_SRC (new_set), 0))
913 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
916 int old_cost = rtx_cost (SET_SRC (new_set), SET, speed);
918 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
919 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
921 if (rtx_cost (new_src, SET, speed) <= old_cost
922 && validate_change (use_insn, &SET_SRC (new_set),
930 /* Called by reload_combine when scanning INSN. This function tries to detect
931 patterns where a constant is added to a register, and the result is used
933 Return true if no further processing is needed on INSN; false if it wasn't
934 recognized and should be handled normally. */
937 reload_combine_recognize_const_pattern (rtx insn)
939 int from_ruid = reload_combine_ruid;
940 rtx set, pat, reg, src, addreg;
944 rtx add_moved_after_insn = NULL_RTX;
945 int add_moved_after_ruid = 0;
946 int clobbered_regno = -1;
948 set = single_set (insn);
952 reg = SET_DEST (set);
955 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
956 || GET_MODE (reg) != Pmode
957 || reg == stack_pointer_rtx)
962 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
963 uses of REG1 inside an address, or inside another add insn. If
964 possible and profitable, merge the addition into subsequent
966 if (GET_CODE (src) != PLUS
967 || !REG_P (XEXP (src, 0))
968 || !CONSTANT_P (XEXP (src, 1)))
971 addreg = XEXP (src, 0);
972 must_move_add = rtx_equal_p (reg, addreg);
974 pat = PATTERN (insn);
975 if (must_move_add && set != pat)
977 /* We have to be careful when moving the add; apart from the
978 single_set there may also be clobbers. Recognize one special
979 case, that of one clobber alongside the set (likely a clobber
980 of the CC register). */
981 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
982 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
983 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
984 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
986 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
991 use = reload_combine_closest_single_use (regno, from_ruid);
994 /* Start the search for the next use from here. */
995 from_ruid = use->ruid;
997 if (use && GET_MODE (*use->usep) == Pmode)
999 bool delete_add = false;
1000 rtx use_insn = use->insn;
1001 int use_ruid = use->ruid;
1003 /* Avoid moving the add insn past a jump. */
1004 if (must_move_add && use_ruid <= last_jump_ruid)
1007 /* If the add clobbers another hard reg in parallel, don't move
1008 it past a real set of this hard reg. */
1009 if (must_move_add && clobbered_regno >= 0
1010 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
1013 gcc_assert (reg_state[regno].store_ruid <= use_ruid);
1014 /* Avoid moving a use of ADDREG past a point where it is stored. */
1015 if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
1018 /* We also must not move the addition past an insn that sets
1019 the same register, unless we can combine two add insns. */
1020 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
1022 if (use->containing_mem == NULL_RTX)
1028 if (try_replace_in_use (use, reg, src))
1030 reload_combine_purge_insn_uses (use_insn);
1031 reload_combine_note_use (&PATTERN (use_insn), use_insn,
1032 use_ruid, NULL_RTX);
1036 fixup_debug_insns (reg, src, insn, use_insn);
1042 add_moved_after_insn = use_insn;
1043 add_moved_after_ruid = use_ruid;
1048 /* If we get here, we couldn't handle this use. */
1054 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1055 /* Process the add normally. */
1058 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1060 reorder_insns (insn, insn, add_moved_after_insn);
1061 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1062 reload_combine_split_ruids (add_moved_after_ruid - 1);
1063 reload_combine_note_use (&PATTERN (insn), insn,
1064 add_moved_after_ruid, NULL_RTX);
1065 reg_state[regno].store_ruid = add_moved_after_ruid;
1070 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1071 can handle and improve. Return true if no further processing is needed on
1072 INSN; false if it wasn't recognized and should be handled normally. */
1075 reload_combine_recognize_pattern (rtx insn)
1080 set = single_set (insn);
1081 if (set == NULL_RTX)
1084 reg = SET_DEST (set);
1085 src = SET_SRC (set);
1087 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
1090 regno = REGNO (reg);
1092 /* Look for (set (REGX) (CONST_INT))
1093 (set (REGX) (PLUS (REGX) (REGY)))
1095 ... (MEM (REGX)) ...
1097 (set (REGZ) (CONST_INT))
1099 ... (MEM (PLUS (REGZ) (REGY)))... .
1101 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1102 and that we know all uses of REGX before it dies.
1103 Also, explicitly check that REGX != REGY; our life information
1104 does not yet show whether REGY changes in this insn. */
1106 if (GET_CODE (src) == PLUS
1107 && reg_state[regno].all_offsets_match
1108 && last_index_reg != -1
1109 && REG_P (XEXP (src, 1))
1110 && rtx_equal_p (XEXP (src, 0), reg)
1111 && !rtx_equal_p (XEXP (src, 1), reg)
1112 && reg_state[regno].use_index >= 0
1113 && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
1114 && last_label_ruid < reg_state[regno].use_ruid)
1116 rtx base = XEXP (src, 1);
1117 rtx prev = prev_nonnote_nondebug_insn (insn);
1118 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1119 rtx index_reg = NULL_RTX;
1120 rtx reg_sum = NULL_RTX;
1123 /* Now we need to set INDEX_REG to an index register (denoted as
1124 REGZ in the illustration above) and REG_SUM to the expression
1125 register+register that we want to use to substitute uses of REG
1126 (typically in MEMs) with. First check REG and BASE for being
1127 index registers; we can use them even if they are not dead. */
1128 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1129 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1137 /* Otherwise, look for a free index register. Since we have
1138 checked above that neither REG nor BASE are index registers,
1139 if we find anything at all, it will be different from these
1141 for (i = first_index_reg; i <= last_index_reg; i++)
1143 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1144 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1145 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1146 && (call_used_regs[i] || df_regs_ever_live_p (i))
1147 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
1148 && !fixed_regs[i] && !global_regs[i]
1149 && hard_regno_nregs[i][GET_MODE (reg)] == 1
1150 && targetm.hard_regno_scratch_ok (i))
1152 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1153 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1159 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1160 (REGY), i.e. BASE, is not clobbered before the last use we'll
1164 && CONST_INT_P (SET_SRC (prev_set))
1165 && rtx_equal_p (SET_DEST (prev_set), reg)
1166 && (reg_state[REGNO (base)].store_ruid
1167 <= reg_state[regno].use_ruid))
1169 /* Change destination register and, if necessary, the constant
1170 value in PREV, the constant loading instruction. */
1171 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1172 if (reg_state[regno].offset != const0_rtx)
1173 validate_change (prev,
1174 &SET_SRC (prev_set),
1175 GEN_INT (INTVAL (SET_SRC (prev_set))
1176 + INTVAL (reg_state[regno].offset)),
1179 /* Now for every use of REG that we have recorded, replace REG
1181 for (i = reg_state[regno].use_index;
1182 i < RELOAD_COMBINE_MAX_USES; i++)
1183 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1184 reg_state[regno].reg_use[i].usep,
1185 /* Each change must have its own
1189 if (apply_change_group ())
1191 struct reg_use *lowest_ruid = NULL;
1193 /* For every new use of REG_SUM, we have to record the use
1194 of BASE therein, i.e. operand 1. */
1195 for (i = reg_state[regno].use_index;
1196 i < RELOAD_COMBINE_MAX_USES; i++)
1198 struct reg_use *use = reg_state[regno].reg_use + i;
1199 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1200 use->ruid, use->containing_mem);
1201 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1205 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1207 /* Delete the reg-reg addition. */
1210 if (reg_state[regno].offset != const0_rtx)
1211 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1213 remove_reg_equal_equiv_notes (prev);
1215 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1224 reload_combine (void)
1229 int min_labelno, n_labels;
1230 HARD_REG_SET ever_live_at_start, *label_live;
1232 /* To avoid wasting too much time later searching for an index register,
1233 determine the minimum and maximum index register numbers. */
1234 if (INDEX_REG_CLASS == NO_REGS)
1235 last_index_reg = -1;
1236 else if (first_index_reg == -1 && last_index_reg == 0)
1238 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1239 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1241 if (first_index_reg == -1)
1242 first_index_reg = r;
1247 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1248 to -1 so we'll know to quit early the next time we get here. */
1249 if (first_index_reg == -1)
1251 last_index_reg = -1;
1256 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1257 information is a bit fuzzy immediately after reload, but it's
1258 still good enough to determine which registers are live at a jump
1260 min_labelno = get_first_label_num ();
1261 n_labels = max_label_num () - min_labelno;
1262 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1263 CLEAR_HARD_REG_SET (ever_live_at_start);
1265 FOR_EACH_BB_REVERSE (bb)
1267 insn = BB_HEAD (bb);
1271 bitmap live_in = df_get_live_in (bb);
1273 REG_SET_TO_HARD_REG_SET (live, live_in);
1274 compute_use_by_pseudos (&live, live_in);
1275 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
1276 IOR_HARD_REG_SET (ever_live_at_start, live);
1280 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1281 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1282 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1284 reg_state[r].store_ruid = 0;
1285 reg_state[r].real_store_ruid = 0;
1287 reg_state[r].use_index = -1;
1289 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1292 for (insn = get_last_insn (); insn; insn = prev)
1294 bool control_flow_insn;
1297 prev = PREV_INSN (insn);
1299 /* We cannot do our optimization across labels. Invalidating all the use
1300 information we have would be costly, so we just note where the label
1301 is and then later disable any optimization that would cross it. */
1303 last_label_ruid = reload_combine_ruid;
1304 else if (BARRIER_P (insn))
1305 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1306 if (! fixed_regs[r])
1307 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1309 if (! NONDEBUG_INSN_P (insn))
1312 reload_combine_ruid++;
1314 control_flow_insn = control_flow_insn_p (insn);
1315 if (control_flow_insn)
1316 last_jump_ruid = reload_combine_ruid;
1318 if (reload_combine_recognize_const_pattern (insn)
1319 || reload_combine_recognize_pattern (insn))
1322 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
1328 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1329 if (call_used_regs[r])
1331 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1332 reg_state[r].store_ruid = reload_combine_ruid;
1335 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1336 link = XEXP (link, 1))
1338 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
1339 if (REG_P (usage_rtx))
1342 unsigned int start_reg = REGNO (usage_rtx);
1343 unsigned int num_regs
1344 = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)];
1345 unsigned int end_reg = start_reg + num_regs - 1;
1346 for (i = start_reg; i <= end_reg; i++)
1347 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
1349 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1350 reg_state[i].store_ruid = reload_combine_ruid;
1353 reg_state[i].use_index = -1;
1358 if (control_flow_insn && GET_CODE (PATTERN (insn)) != RETURN)
1360 /* Non-spill registers might be used at the call destination in
1361 some unknown fashion, so we have to mark the unknown use. */
1364 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1365 && JUMP_LABEL (insn))
1366 live = &LABEL_LIVE (JUMP_LABEL (insn));
1368 live = &ever_live_at_start;
1370 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1371 if (TEST_HARD_REG_BIT (*live, r))
1372 reg_state[r].use_index = -1;
1375 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
1378 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1380 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0)))
1382 int regno = REGNO (XEXP (note, 0));
1383 reg_state[regno].store_ruid = reload_combine_ruid;
1384 reg_state[regno].real_store_ruid = reload_combine_ruid;
1385 reg_state[regno].use_index = -1;
1393 /* Check if DST is a register or a subreg of a register; if it is,
1394 update store_ruid, real_store_ruid and use_index in the reg_state
1395 structure accordingly. Called via note_stores from reload_combine. */
1398 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1402 enum machine_mode mode = GET_MODE (dst);
1404 if (GET_CODE (dst) == SUBREG)
1406 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1407 GET_MODE (SUBREG_REG (dst)),
1410 dst = SUBREG_REG (dst);
1414 regno += REGNO (dst);
1416 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1417 careful with registers / register parts that are not full words.
1418 Similarly for ZERO_EXTRACT. */
1419 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1420 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1422 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1424 reg_state[i].use_index = -1;
1425 reg_state[i].store_ruid = reload_combine_ruid;
1426 reg_state[i].real_store_ruid = reload_combine_ruid;
1431 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1433 reg_state[i].store_ruid = reload_combine_ruid;
1434 if (GET_CODE (set) == SET)
1435 reg_state[i].real_store_ruid = reload_combine_ruid;
1436 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1441 /* XP points to a piece of rtl that has to be checked for any uses of
1443 *XP is the pattern of INSN, or a part of it.
1444 Called from reload_combine, and recursively by itself. */
1446 reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
1449 enum rtx_code code = x->code;
1452 rtx offset = const0_rtx; /* For the REG case below. */
1457 if (REG_P (SET_DEST (x)))
1459 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1465 /* If this is the USE of a return value, we can't change it. */
1466 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1468 /* Mark the return register as used in an unknown fashion. */
1469 rtx reg = XEXP (x, 0);
1470 int regno = REGNO (reg);
1471 int nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1473 while (--nregs >= 0)
1474 reg_state[regno + nregs].use_index = -1;
1480 if (REG_P (SET_DEST (x)))
1482 /* No spurious CLOBBERs of pseudo registers may remain. */
1483 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1489 /* We are interested in (plus (reg) (const_int)) . */
1490 if (!REG_P (XEXP (x, 0))
1491 || !CONST_INT_P (XEXP (x, 1)))
1493 offset = XEXP (x, 1);
1498 int regno = REGNO (x);
1502 /* No spurious USEs of pseudo registers may remain. */
1503 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1505 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1507 /* We can't substitute into multi-hard-reg uses. */
1510 while (--nregs >= 0)
1511 reg_state[regno + nregs].use_index = -1;
1515 /* We may be called to update uses in previously seen insns.
1516 Don't add uses beyond the last store we saw. */
1517 if (ruid < reg_state[regno].store_ruid)
1520 /* If this register is already used in some unknown fashion, we
1522 If we decrement the index from zero to -1, we can't store more
1523 uses, so this register becomes used in an unknown fashion. */
1524 use_index = --reg_state[regno].use_index;
1528 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1530 /* This is the first use of this register we have seen since we
1531 marked it as dead. */
1532 reg_state[regno].offset = offset;
1533 reg_state[regno].all_offsets_match = true;
1534 reg_state[regno].use_ruid = ruid;
1538 if (reg_state[regno].use_ruid > ruid)
1539 reg_state[regno].use_ruid = ruid;
1541 if (! rtx_equal_p (offset, reg_state[regno].offset))
1542 reg_state[regno].all_offsets_match = false;
1545 reg_state[regno].reg_use[use_index].insn = insn;
1546 reg_state[regno].reg_use[use_index].ruid = ruid;
1547 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1548 reg_state[regno].reg_use[use_index].usep = xp;
1560 /* Recursively process the components of X. */
1561 fmt = GET_RTX_FORMAT (code);
1562 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1565 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1566 else if (fmt[i] == 'E')
1568 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1569 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1575 /* See if we can reduce the cost of a constant by replacing a move
1576 with an add. We track situations in which a register is set to a
1577 constant or to a register plus a constant. */
1578 /* We cannot do our optimization across labels. Invalidating all the
1579 information about register contents we have would be costly, so we
1580 use move2add_last_label_luid to note where the label is and then
1581 later disable any optimization that would cross it.
1582 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1583 are only valid if reg_set_luid[n] is greater than
1584 move2add_last_label_luid. */
1585 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1587 /* If reg_base_reg[n] is negative, register n has been set to
1588 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1589 If reg_base_reg[n] is non-negative, register n has been set to the
1590 sum of reg_offset[n] and the value of register reg_base_reg[n]
1591 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1592 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1593 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1594 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1595 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1597 /* move2add_luid is linearly increased while scanning the instructions
1598 from first to last. It is used to set reg_set_luid in
1599 reload_cse_move2add and move2add_note_store. */
1600 static int move2add_luid;
1602 /* move2add_last_label_luid is set whenever a label is found. Labels
1603 invalidate all previously collected reg_offset data. */
1604 static int move2add_last_label_luid;
1606 /* ??? We don't know how zero / sign extension is handled, hence we
1607 can't go from a narrower to a wider mode. */
1608 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1609 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1610 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1611 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
1612 GET_MODE_BITSIZE (INMODE))))
1614 /* This function is called with INSN that sets REG to (SYM + OFF),
1615 while REG is known to already have value (SYM + offset).
1616 This function tries to change INSN into an add instruction
1617 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1618 It also updates the information about REG's known value.
1619 Return true if we made a change. */
1622 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
1624 rtx pat = PATTERN (insn);
1625 rtx src = SET_SRC (pat);
1626 int regno = REGNO (reg);
1627 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
1629 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1630 bool changed = false;
1632 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1633 use (set (reg) (reg)) instead.
1634 We don't delete this insn, nor do we convert it into a
1635 note, to avoid losing register notes or the return
1636 value flag. jump2 already knows how to get rid of
1638 if (new_src == const0_rtx)
1640 /* If the constants are different, this is a
1641 truncation, that, if turned into (set (reg)
1642 (reg)), would be discarded. Maybe we should
1643 try a truncMN pattern? */
1644 if (INTVAL (off) == reg_offset [regno])
1645 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1649 struct full_rtx_costs oldcst, newcst;
1650 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1652 get_full_rtx_cost (pat, SET, &oldcst);
1653 SET_SRC (pat) = tem;
1654 get_full_rtx_cost (pat, SET, &newcst);
1655 SET_SRC (pat) = src;
1657 if (costs_lt_p (&newcst, &oldcst, speed)
1658 && have_add2_insn (reg, new_src))
1659 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1660 else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
1662 enum machine_mode narrow_mode;
1663 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
1664 narrow_mode != VOIDmode
1665 && narrow_mode != GET_MODE (reg);
1666 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
1668 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1669 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
1670 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
1672 rtx narrow_reg = gen_rtx_REG (narrow_mode,
1674 rtx narrow_src = gen_int_mode (INTVAL (off),
1677 = gen_rtx_SET (VOIDmode,
1678 gen_rtx_STRICT_LOW_PART (VOIDmode,
1681 changed = validate_change (insn, &PATTERN (insn),
1689 reg_set_luid[regno] = move2add_luid;
1690 reg_base_reg[regno] = -1;
1691 reg_mode[regno] = GET_MODE (reg);
1692 reg_symbol_ref[regno] = sym;
1693 reg_offset[regno] = INTVAL (off);
1698 /* This function is called with INSN that sets REG to (SYM + OFF),
1699 but REG doesn't have known value (SYM + offset). This function
1700 tries to find another register which is known to already have
1701 value (SYM + offset) and change INSN into an add instruction
1702 (set (REG) (plus (the found register) (OFF - offset))) if such
1703 a register is found. It also updates the information about
1705 Return true iff we made a change. */
1708 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
1710 rtx pat = PATTERN (insn);
1711 rtx src = SET_SRC (pat);
1712 int regno = REGNO (reg);
1714 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1716 bool changed = false;
1717 struct full_rtx_costs oldcst, newcst, mincst;
1720 init_costs_to_max (&mincst);
1721 get_full_rtx_cost (pat, SET, &oldcst);
1723 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
1724 SET_SRC (pat) = plus_expr;
1726 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1727 if (reg_set_luid[i] > move2add_last_label_luid
1728 && reg_mode[i] == GET_MODE (reg)
1729 && reg_base_reg[i] < 0
1730 && reg_symbol_ref[i] != NULL_RTX
1731 && rtx_equal_p (sym, reg_symbol_ref[i]))
1733 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
1735 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1736 use (set (reg) (reg)) instead.
1737 We don't delete this insn, nor do we convert it into a
1738 note, to avoid losing register notes or the return
1739 value flag. jump2 already knows how to get rid of
1741 if (new_src == const0_rtx)
1743 init_costs_to_zero (&mincst);
1749 XEXP (plus_expr, 1) = new_src;
1750 get_full_rtx_cost (pat, SET, &newcst);
1752 if (costs_lt_p (&newcst, &mincst, speed))
1759 SET_SRC (pat) = src;
1761 if (costs_lt_p (&mincst, &oldcst, speed))
1765 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1768 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
1770 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1772 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1775 reg_set_luid[regno] = move2add_luid;
1776 reg_base_reg[regno] = -1;
1777 reg_mode[regno] = GET_MODE (reg);
1778 reg_symbol_ref[regno] = sym;
1779 reg_offset[regno] = INTVAL (off);
1783 /* Convert move insns with constant inputs to additions if they are cheaper.
1784 Return true if any changes were made. */
1786 reload_cse_move2add (rtx first)
1790 bool changed = false;
1792 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1794 reg_set_luid[i] = 0;
1796 reg_base_reg[i] = 0;
1797 reg_symbol_ref[i] = NULL_RTX;
1798 reg_mode[i] = VOIDmode;
1801 move2add_last_label_luid = 0;
1803 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1809 move2add_last_label_luid = move2add_luid;
1810 /* We're going to increment move2add_luid twice after a
1811 label, so that we can use move2add_last_label_luid + 1 as
1812 the luid for constants. */
1816 if (! INSN_P (insn))
1818 pat = PATTERN (insn);
1819 /* For simplicity, we only perform this optimization on
1820 straightforward SETs. */
1821 if (GET_CODE (pat) == SET
1822 && REG_P (SET_DEST (pat)))
1824 rtx reg = SET_DEST (pat);
1825 int regno = REGNO (reg);
1826 rtx src = SET_SRC (pat);
1828 /* Check if we have valid information on the contents of this
1829 register in the mode of REG. */
1830 if (reg_set_luid[regno] > move2add_last_label_luid
1831 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
1832 && dbg_cnt (cse2_move2add))
1834 /* Try to transform (set (REGX) (CONST_INT A))
1836 (set (REGX) (CONST_INT B))
1838 (set (REGX) (CONST_INT A))
1840 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1842 (set (REGX) (CONST_INT A))
1844 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1847 if (CONST_INT_P (src)
1848 && reg_base_reg[regno] < 0
1849 && reg_symbol_ref[regno] == NULL_RTX)
1851 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1855 /* Try to transform (set (REGX) (REGY))
1856 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1859 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1862 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1864 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1865 else if (REG_P (src)
1866 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1867 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1868 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
1869 reg_mode[REGNO (src)]))
1871 rtx next = next_nonnote_nondebug_insn (insn);
1874 set = single_set (next);
1876 && SET_DEST (set) == reg
1877 && GET_CODE (SET_SRC (set)) == PLUS
1878 && XEXP (SET_SRC (set), 0) == reg
1879 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1881 rtx src3 = XEXP (SET_SRC (set), 1);
1882 HOST_WIDE_INT added_offset = INTVAL (src3);
1883 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1884 HOST_WIDE_INT regno_offset = reg_offset[regno];
1886 gen_int_mode (added_offset
1890 bool success = false;
1891 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1893 if (new_src == const0_rtx)
1894 /* See above why we create (set (reg) (reg)) here. */
1896 = validate_change (next, &SET_SRC (set), reg, 0);
1899 rtx old_src = SET_SRC (set);
1900 struct full_rtx_costs oldcst, newcst;
1901 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1903 get_full_rtx_cost (set, SET, &oldcst);
1904 SET_SRC (set) = tem;
1905 get_full_rtx_cost (tem, SET, &newcst);
1906 SET_SRC (set) = old_src;
1907 costs_add_n_insns (&oldcst, 1);
1909 if (costs_lt_p (&newcst, &oldcst, speed)
1910 && have_add2_insn (reg, new_src))
1912 rtx newpat = gen_rtx_SET (VOIDmode, reg, tem);
1914 = validate_change (next, &PATTERN (next),
1922 reg_mode[regno] = GET_MODE (reg);
1924 trunc_int_for_mode (added_offset + base_offset,
1932 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1934 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
1936 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1938 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
1939 if ((GET_CODE (src) == SYMBOL_REF
1940 || (GET_CODE (src) == CONST
1941 && GET_CODE (XEXP (src, 0)) == PLUS
1942 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
1943 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
1944 && dbg_cnt (cse2_move2add))
1948 if (GET_CODE (src) == SYMBOL_REF)
1955 sym = XEXP (XEXP (src, 0), 0);
1956 off = XEXP (XEXP (src, 0), 1);
1959 /* If the reg already contains the value which is sum of
1960 sym and some constant value, we can use an add2 insn. */
1961 if (reg_set_luid[regno] > move2add_last_label_luid
1962 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
1963 && reg_base_reg[regno] < 0
1964 && reg_symbol_ref[regno] != NULL_RTX
1965 && rtx_equal_p (sym, reg_symbol_ref[regno]))
1966 changed |= move2add_use_add2_insn (reg, sym, off, insn);
1968 /* Otherwise, we have to find a register whose value is sum
1969 of sym and some constant value. */
1971 changed |= move2add_use_add3_insn (reg, sym, off, insn);
1977 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1979 if (REG_NOTE_KIND (note) == REG_INC
1980 && REG_P (XEXP (note, 0)))
1982 /* Reset the information about this register. */
1983 int regno = REGNO (XEXP (note, 0));
1984 if (regno < FIRST_PSEUDO_REGISTER)
1985 reg_set_luid[regno] = 0;
1988 note_stores (PATTERN (insn), move2add_note_store, insn);
1990 /* If INSN is a conditional branch, we try to extract an
1991 implicit set out of it. */
1992 if (any_condjump_p (insn))
1994 rtx cnd = fis_get_condition (insn);
1997 && GET_CODE (cnd) == NE
1998 && REG_P (XEXP (cnd, 0))
1999 && !reg_set_p (XEXP (cnd, 0), insn)
2000 /* The following two checks, which are also in
2001 move2add_note_store, are intended to reduce the
2002 number of calls to gen_rtx_SET to avoid memory
2003 allocation if possible. */
2004 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
2005 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1
2006 && CONST_INT_P (XEXP (cnd, 1)))
2009 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
2010 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
2014 /* If this is a CALL_INSN, all call used registers are stored with
2018 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
2020 if (call_used_regs[i])
2021 /* Reset the information about this register. */
2022 reg_set_luid[i] = 0;
2029 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2031 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2032 Called from reload_cse_move2add via note_stores. */
2035 move2add_note_store (rtx dst, const_rtx set, void *data)
2037 rtx insn = (rtx) data;
2038 unsigned int regno = 0;
2039 unsigned int nregs = 0;
2041 enum machine_mode mode = GET_MODE (dst);
2043 if (GET_CODE (dst) == SUBREG)
2045 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
2046 GET_MODE (SUBREG_REG (dst)),
2049 nregs = subreg_nregs (dst);
2050 dst = SUBREG_REG (dst);
2053 /* Some targets do argument pushes without adding REG_INC notes. */
2057 dst = XEXP (dst, 0);
2058 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
2059 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
2060 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
2066 regno += REGNO (dst);
2068 nregs = hard_regno_nregs[regno][mode];
2070 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2071 && nregs == 1 && GET_CODE (set) == SET)
2073 rtx note, sym = NULL_RTX;
2076 note = find_reg_equal_equiv_note (insn);
2077 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2079 sym = XEXP (note, 0);
2082 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2083 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2084 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2085 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2087 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2088 off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1));
2091 if (sym != NULL_RTX)
2093 reg_base_reg[regno] = -1;
2094 reg_symbol_ref[regno] = sym;
2095 reg_offset[regno] = off;
2096 reg_mode[regno] = mode;
2097 reg_set_luid[regno] = move2add_luid;
2102 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2103 && nregs == 1 && GET_CODE (set) == SET
2104 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2105 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2107 rtx src = SET_SRC (set);
2109 HOST_WIDE_INT offset;
2111 /* This may be different from mode, if SET_DEST (set) is a
2113 enum machine_mode dst_mode = GET_MODE (dst);
2115 switch (GET_CODE (src))
2118 if (REG_P (XEXP (src, 0)))
2120 base_reg = XEXP (src, 0);
2122 if (CONST_INT_P (XEXP (src, 1)))
2123 offset = INTVAL (XEXP (src, 1));
2124 else if (REG_P (XEXP (src, 1))
2125 && (reg_set_luid[REGNO (XEXP (src, 1))]
2126 > move2add_last_label_luid)
2127 && (MODES_OK_FOR_MOVE2ADD
2128 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
2130 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
2131 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
2132 offset = reg_offset[REGNO (XEXP (src, 1))];
2133 /* Maybe the first register is known to be a
2135 else if (reg_set_luid[REGNO (base_reg)]
2136 > move2add_last_label_luid
2137 && (MODES_OK_FOR_MOVE2ADD
2138 (dst_mode, reg_mode[REGNO (base_reg)]))
2139 && reg_base_reg[REGNO (base_reg)] < 0
2140 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
2142 offset = reg_offset[REGNO (base_reg)];
2143 base_reg = XEXP (src, 1);
2162 /* Start tracking the register as a constant. */
2163 reg_base_reg[regno] = -1;
2164 reg_symbol_ref[regno] = NULL_RTX;
2165 reg_offset[regno] = INTVAL (SET_SRC (set));
2166 /* We assign the same luid to all registers set to constants. */
2167 reg_set_luid[regno] = move2add_last_label_luid + 1;
2168 reg_mode[regno] = mode;
2173 /* Invalidate the contents of the register. */
2174 reg_set_luid[regno] = 0;
2178 base_regno = REGNO (base_reg);
2179 /* If information about the base register is not valid, set it
2180 up as a new base register, pretending its value is known
2181 starting from the current insn. */
2182 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
2184 reg_base_reg[base_regno] = base_regno;
2185 reg_symbol_ref[base_regno] = NULL_RTX;
2186 reg_offset[base_regno] = 0;
2187 reg_set_luid[base_regno] = move2add_luid;
2188 reg_mode[base_regno] = mode;
2190 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
2191 reg_mode[base_regno]))
2194 reg_mode[regno] = mode;
2196 /* Copy base information from our base register. */
2197 reg_set_luid[regno] = reg_set_luid[base_regno];
2198 reg_base_reg[regno] = reg_base_reg[base_regno];
2199 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2201 /* Compute the sum of the offsets or constants. */
2202 reg_offset[regno] = trunc_int_for_mode (offset
2203 + reg_offset[base_regno],
2208 unsigned int endregno = regno + nregs;
2210 for (i = regno; i < endregno; i++)
2211 /* Reset the information about this register. */
2212 reg_set_luid[i] = 0;
2217 gate_handle_postreload (void)
2219 return (optimize > 0 && reload_completed);
2224 rest_of_handle_postreload (void)
2226 if (!dbg_cnt (postreload_cse))
2229 /* Do a very simple CSE pass over just the hard registers. */
2230 reload_cse_regs (get_insns ());
2231 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2232 Remove any EH edges associated with them. */
2233 if (cfun->can_throw_non_call_exceptions)
2234 purge_all_dead_edges ();
2239 struct rtl_opt_pass pass_postreload_cse =
2243 "postreload", /* name */
2244 gate_handle_postreload, /* gate */
2245 rest_of_handle_postreload, /* execute */
2248 0, /* static_pass_number */
2249 TV_RELOAD_CSE_REGS, /* tv_id */
2250 0, /* properties_required */
2251 0, /* properties_provided */
2252 0, /* properties_destroyed */
2253 0, /* todo_flags_start */
2254 TODO_df_finish | TODO_verify_rtl_sharing |
2255 TODO_dump_func /* todo_flags_finish */