1 /* Swing Modulo Scheduling implementation.
2 Copyright (C) 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Ayal Zaks and Mustafa Hagog <zaks,mustafa@il.ibm.com>
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "insn-attr.h"
40 #include "sched-int.h"
42 #include "cfglayout.h"
51 #include "tree-pass.h"
53 #ifdef INSN_SCHEDULING
55 /* This file contains the implementation of the Swing Modulo Scheduler,
56 described in the following references:
57 [1] J. Llosa, A. Gonzalez, E. Ayguade, M. Valero., and J. Eckhardt.
58 Lifetime--sensitive modulo scheduling in a production environment.
59 IEEE Trans. on Comps., 50(3), March 2001
60 [2] J. Llosa, A. Gonzalez, E. Ayguade, and M. Valero.
61 Swing Modulo Scheduling: A Lifetime Sensitive Approach.
62 PACT '96 , pages 80-87, October 1996 (Boston - Massachusetts - USA).
64 The basic structure is:
65 1. Build a data-dependence graph (DDG) for each loop.
66 2. Use the DDG to order the insns of a loop (not in topological order
67 necessarily, but rather) trying to place each insn after all its
68 predecessors _or_ after all its successors.
69 3. Compute MII: a lower bound on the number of cycles to schedule the loop.
70 4. Use the ordering to perform list-scheduling of the loop:
71 1. Set II = MII. We will try to schedule the loop within II cycles.
72 2. Try to schedule the insns one by one according to the ordering.
73 For each insn compute an interval of cycles by considering already-
74 scheduled preds and succs (and associated latencies); try to place
75 the insn in the cycles of this window checking for potential
76 resource conflicts (using the DFA interface).
77 Note: this is different from the cycle-scheduling of schedule_insns;
78 here the insns are not scheduled monotonically top-down (nor bottom-
80 3. If failed in scheduling all insns - bump II++ and try again, unless
81 II reaches an upper bound MaxII, in which case report failure.
82 5. If we succeeded in scheduling the loop within II cycles, we now
83 generate prolog and epilog, decrease the counter of the loop, and
84 perform modulo variable expansion for live ranges that span more than
85 II cycles (i.e. use register copies to prevent a def from overwriting
86 itself before reaching the use).
90 /* This page defines partial-schedule structures and functions for
93 typedef struct partial_schedule *partial_schedule_ptr;
94 typedef struct ps_insn *ps_insn_ptr;
96 /* The minimum (absolute) cycle that a node of ps was scheduled in. */
97 #define PS_MIN_CYCLE(ps) (((partial_schedule_ptr)(ps))->min_cycle)
99 /* The maximum (absolute) cycle that a node of ps was scheduled in. */
100 #define PS_MAX_CYCLE(ps) (((partial_schedule_ptr)(ps))->max_cycle)
102 /* Perform signed modulo, always returning a non-negative value. */
103 #define SMODULO(x,y) ((x) % (y) < 0 ? ((x) % (y) + (y)) : (x) % (y))
105 /* The number of different iterations the nodes in ps span, assuming
106 the stage boundaries are placed efficiently. */
107 #define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
108 + 1 + (ps)->ii - 1) / (ps)->ii)
110 /* A single instruction in the partial schedule. */
113 /* The corresponding DDG_NODE. */
116 /* The (absolute) cycle in which the PS instruction is scheduled.
117 Same as SCHED_TIME (node). */
120 /* The next/prev PS_INSN in the same row. */
121 ps_insn_ptr next_in_row,
124 /* The number of nodes in the same row that come after this node. */
128 /* Holds the partial schedule as an array of II rows. Each entry of the
129 array points to a linked list of PS_INSNs, which represents the
130 instructions that are scheduled for that row. */
131 struct partial_schedule
133 int ii; /* Number of rows in the partial schedule. */
134 int history; /* Threshold for conflict checking using DFA. */
136 /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii). */
139 /* The earliest absolute cycle of an insn in the partial schedule. */
142 /* The latest absolute cycle of an insn in the partial schedule. */
145 ddg_ptr g; /* The DDG of the insns in the partial schedule. */
148 /* We use this to record all the register replacements we do in
149 the kernel so we can undo SMS if it is not profitable. */
150 struct undo_replace_buff_elem
155 struct undo_replace_buff_elem *next;
160 static partial_schedule_ptr create_partial_schedule (int ii, ddg_ptr, int history);
161 static void free_partial_schedule (partial_schedule_ptr);
162 static void reset_partial_schedule (partial_schedule_ptr, int new_ii);
163 void print_partial_schedule (partial_schedule_ptr, FILE *);
164 static int kernel_number_of_cycles (rtx first_insn, rtx last_insn);
165 static ps_insn_ptr ps_add_node_check_conflicts (partial_schedule_ptr,
166 ddg_node_ptr node, int cycle,
167 sbitmap must_precede,
168 sbitmap must_follow);
169 static void rotate_partial_schedule (partial_schedule_ptr, int);
170 void set_row_column_for_ps (partial_schedule_ptr);
171 static bool ps_unschedule_node (partial_schedule_ptr, ddg_node_ptr );
174 /* This page defines constants and structures for the modulo scheduling
177 /* As in haifa-sched.c: */
178 /* issue_rate is the number of insns that can be scheduled in the same
179 machine cycle. It can be defined in the config/mach/mach.h file,
180 otherwise we set it to 1. */
182 static int issue_rate;
184 static int sms_order_nodes (ddg_ptr, int, int * result);
185 static void set_node_sched_params (ddg_ptr);
186 static partial_schedule_ptr sms_schedule_by_order (ddg_ptr, int, int, int *);
187 static void permute_partial_schedule (partial_schedule_ptr ps, rtx last);
188 static void generate_prolog_epilog (partial_schedule_ptr ,struct loop * loop, rtx);
189 static void duplicate_insns_of_cycles (partial_schedule_ptr ps,
190 int from_stage, int to_stage,
193 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
194 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
195 #define SCHED_FIRST_REG_MOVE(x) \
196 (((node_sched_params_ptr)(x)->aux.info)->first_reg_move)
197 #define SCHED_NREG_MOVES(x) \
198 (((node_sched_params_ptr)(x)->aux.info)->nreg_moves)
199 #define SCHED_ROW(x) (((node_sched_params_ptr)(x)->aux.info)->row)
200 #define SCHED_STAGE(x) (((node_sched_params_ptr)(x)->aux.info)->stage)
201 #define SCHED_COLUMN(x) (((node_sched_params_ptr)(x)->aux.info)->column)
203 /* The scheduling parameters held for each node. */
204 typedef struct node_sched_params
206 int asap; /* A lower-bound on the absolute scheduling cycle. */
207 int time; /* The absolute scheduling cycle (time >= asap). */
209 /* The following field (first_reg_move) is a pointer to the first
210 register-move instruction added to handle the modulo-variable-expansion
211 of the register defined by this node. This register-move copies the
212 original register defined by the node. */
215 /* The number of register-move instructions added, immediately preceding
219 int row; /* Holds time % ii. */
220 int stage; /* Holds time / ii. */
222 /* The column of a node inside the ps. If nodes u, v are on the same row,
223 u will precede v if column (u) < column (v). */
225 } *node_sched_params_ptr;
228 /* The following three functions are copied from the current scheduler
229 code in order to use sched_analyze() for computing the dependencies.
230 They are used when initializing the sched_info structure. */
232 sms_print_insn (rtx insn, int aligned ATTRIBUTE_UNUSED)
236 sprintf (tmp, "i%4d", INSN_UID (insn));
241 compute_jump_reg_dependencies (rtx insn ATTRIBUTE_UNUSED,
242 regset cond_exec ATTRIBUTE_UNUSED,
243 regset used ATTRIBUTE_UNUSED,
244 regset set ATTRIBUTE_UNUSED)
248 static struct sched_info sms_sched_info =
257 compute_jump_reg_dependencies,
262 NULL, NULL, NULL, NULL, NULL,
263 #ifdef ENABLE_CHECKING
270 /* Return the register decremented and tested in INSN,
271 or zero if it is not a decrement-and-branch insn. */
274 doloop_register_get (rtx insn ATTRIBUTE_UNUSED)
276 #ifdef HAVE_doloop_end
277 rtx pattern, reg, condition;
282 pattern = PATTERN (insn);
283 condition = doloop_condition_get (pattern);
287 if (REG_P (XEXP (condition, 0)))
288 reg = XEXP (condition, 0);
289 else if (GET_CODE (XEXP (condition, 0)) == PLUS
290 && REG_P (XEXP (XEXP (condition, 0), 0)))
291 reg = XEXP (XEXP (condition, 0), 0);
301 /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
302 that the number of iterations is a compile-time constant. If so,
303 return the rtx that sets COUNT_REG to a constant, and set COUNT to
304 this constant. Otherwise return 0. */
306 const_iteration_count (rtx count_reg, basic_block pre_header,
307 HOST_WIDEST_INT * count)
315 get_ebb_head_tail (pre_header, pre_header, &head, &tail);
317 for (insn = tail; insn != PREV_INSN (head); insn = PREV_INSN (insn))
318 if (INSN_P (insn) && single_set (insn) &&
319 rtx_equal_p (count_reg, SET_DEST (single_set (insn))))
321 rtx pat = single_set (insn);
323 if (GET_CODE (SET_SRC (pat)) == CONST_INT)
325 *count = INTVAL (SET_SRC (pat));
335 /* A very simple resource-based lower bound on the initiation interval.
336 ??? Improve the accuracy of this bound by considering the
337 utilization of various units. */
341 return (g->num_nodes / issue_rate);
345 /* Points to the array that contains the sched data for each node. */
346 static node_sched_params_ptr node_sched_params;
348 /* Allocate sched_params for each node and initialize it. Assumes that
349 the aux field of each node contain the asap bound (computed earlier),
350 and copies it into the sched_params field. */
352 set_node_sched_params (ddg_ptr g)
356 /* Allocate for each node in the DDG a place to hold the "sched_data". */
357 /* Initialize ASAP/ALAP/HIGHT to zero. */
358 node_sched_params = (node_sched_params_ptr)
359 xcalloc (g->num_nodes,
360 sizeof (struct node_sched_params));
362 /* Set the pointer of the general data of the node to point to the
363 appropriate sched_params structure. */
364 for (i = 0; i < g->num_nodes; i++)
366 /* Watch out for aliasing problems? */
367 node_sched_params[i].asap = g->nodes[i].aux.count;
368 g->nodes[i].aux.info = &node_sched_params[i];
373 print_node_sched_params (FILE * file, int num_nodes)
379 for (i = 0; i < num_nodes; i++)
381 node_sched_params_ptr nsp = &node_sched_params[i];
382 rtx reg_move = nsp->first_reg_move;
385 fprintf (file, "Node %d:\n", i);
386 fprintf (file, " asap = %d:\n", nsp->asap);
387 fprintf (file, " time = %d:\n", nsp->time);
388 fprintf (file, " nreg_moves = %d:\n", nsp->nreg_moves);
389 for (j = 0; j < nsp->nreg_moves; j++)
391 fprintf (file, " reg_move = ");
392 print_rtl_single (file, reg_move);
393 reg_move = PREV_INSN (reg_move);
398 /* Calculate an upper bound for II. SMS should not schedule the loop if it
399 requires more cycles than this bound. Currently set to the sum of the
400 longest latency edge for each node. Reset based on experiments. */
402 calculate_maxii (ddg_ptr g)
407 for (i = 0; i < g->num_nodes; i++)
409 ddg_node_ptr u = &g->nodes[i];
411 int max_edge_latency = 0;
413 for (e = u->out; e; e = e->next_out)
414 max_edge_latency = MAX (max_edge_latency, e->latency);
416 maxii += max_edge_latency;
422 Breaking intra-loop register anti-dependences:
423 Each intra-loop register anti-dependence implies a cross-iteration true
424 dependence of distance 1. Therefore, we can remove such false dependencies
425 and figure out if the partial schedule broke them by checking if (for a
426 true-dependence of distance 1): SCHED_TIME (def) < SCHED_TIME (use) and
427 if so generate a register move. The number of such moves is equal to:
428 SCHED_TIME (use) - SCHED_TIME (def) { 0 broken
429 nreg_moves = ----------------------------------- + 1 - { dependence.
432 static struct undo_replace_buff_elem *
433 generate_reg_moves (partial_schedule_ptr ps)
438 struct undo_replace_buff_elem *reg_move_replaces = NULL;
440 for (i = 0; i < g->num_nodes; i++)
442 ddg_node_ptr u = &g->nodes[i];
444 int nreg_moves = 0, i_reg_move;
445 sbitmap *uses_of_defs;
447 rtx prev_reg, old_reg;
449 /* Compute the number of reg_moves needed for u, by looking at life
450 ranges started at u (excluding self-loops). */
451 for (e = u->out; e; e = e->next_out)
452 if (e->type == TRUE_DEP && e->dest != e->src)
454 int nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
456 if (e->distance == 1)
457 nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
459 /* If dest precedes src in the schedule of the kernel, then dest
460 will read before src writes and we can save one reg_copy. */
461 if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
462 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
465 nreg_moves = MAX (nreg_moves, nreg_moves4e);
471 /* Every use of the register defined by node may require a different
472 copy of this register, depending on the time the use is scheduled.
473 Set a bitmap vector, telling which nodes use each copy of this
475 uses_of_defs = sbitmap_vector_alloc (nreg_moves, g->num_nodes);
476 sbitmap_vector_zero (uses_of_defs, nreg_moves);
477 for (e = u->out; e; e = e->next_out)
478 if (e->type == TRUE_DEP && e->dest != e->src)
480 int dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
482 if (e->distance == 1)
483 dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
485 if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
486 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
490 SET_BIT (uses_of_defs[dest_copy - 1], e->dest->cuid);
493 /* Now generate the reg_moves, attaching relevant uses to them. */
494 SCHED_NREG_MOVES (u) = nreg_moves;
495 old_reg = prev_reg = copy_rtx (SET_DEST (single_set (u->insn)));
496 last_reg_move = u->insn;
498 for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
500 unsigned int i_use = 0;
501 rtx new_reg = gen_reg_rtx (GET_MODE (prev_reg));
502 rtx reg_move = gen_move_insn (new_reg, prev_reg);
503 sbitmap_iterator sbi;
505 add_insn_before (reg_move, last_reg_move);
506 last_reg_move = reg_move;
508 if (!SCHED_FIRST_REG_MOVE (u))
509 SCHED_FIRST_REG_MOVE (u) = reg_move;
511 EXECUTE_IF_SET_IN_SBITMAP (uses_of_defs[i_reg_move], 0, i_use, sbi)
513 struct undo_replace_buff_elem *rep;
515 rep = (struct undo_replace_buff_elem *)
516 xcalloc (1, sizeof (struct undo_replace_buff_elem));
517 rep->insn = g->nodes[i_use].insn;
518 rep->orig_reg = old_reg;
519 rep->new_reg = new_reg;
521 if (! reg_move_replaces)
522 reg_move_replaces = rep;
525 rep->next = reg_move_replaces;
526 reg_move_replaces = rep;
529 replace_rtx (g->nodes[i_use].insn, old_reg, new_reg);
534 sbitmap_vector_free (uses_of_defs);
536 return reg_move_replaces;
539 /* We call this when we want to undo the SMS schedule for a given loop.
540 One of the things that we do is to delete the register moves generated
541 for the sake of SMS; this function deletes the register move instructions
542 recorded in the undo buffer. */
544 undo_generate_reg_moves (partial_schedule_ptr ps,
545 struct undo_replace_buff_elem *reg_move_replaces)
549 for (i = 0; i < ps->g->num_nodes; i++)
551 ddg_node_ptr u = &ps->g->nodes[i];
553 rtx crr = SCHED_FIRST_REG_MOVE (u);
555 for (j = 0; j < SCHED_NREG_MOVES (u); j++)
557 prev = PREV_INSN (crr);
561 SCHED_FIRST_REG_MOVE (u) = NULL_RTX;
564 while (reg_move_replaces)
566 struct undo_replace_buff_elem *rep = reg_move_replaces;
568 reg_move_replaces = reg_move_replaces->next;
569 replace_rtx (rep->insn, rep->new_reg, rep->orig_reg);
573 /* Free memory allocated for the undo buffer. */
575 free_undo_replace_buff (struct undo_replace_buff_elem *reg_move_replaces)
578 while (reg_move_replaces)
580 struct undo_replace_buff_elem *rep = reg_move_replaces;
582 reg_move_replaces = reg_move_replaces->next;
587 /* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values
588 of SCHED_ROW and SCHED_STAGE. */
590 normalize_sched_times (partial_schedule_ptr ps)
594 int amount = PS_MIN_CYCLE (ps);
597 /* Don't include the closing branch assuming that it is the last node. */
598 for (i = 0; i < g->num_nodes - 1; i++)
600 ddg_node_ptr u = &g->nodes[i];
601 int normalized_time = SCHED_TIME (u) - amount;
603 gcc_assert (normalized_time >= 0);
605 SCHED_TIME (u) = normalized_time;
606 SCHED_ROW (u) = normalized_time % ii;
607 SCHED_STAGE (u) = normalized_time / ii;
611 /* Set SCHED_COLUMN of each node according to its position in PS. */
613 set_columns_for_ps (partial_schedule_ptr ps)
617 for (row = 0; row < ps->ii; row++)
619 ps_insn_ptr cur_insn = ps->rows[row];
622 for (; cur_insn; cur_insn = cur_insn->next_in_row)
623 SCHED_COLUMN (cur_insn->node) = column++;
627 /* Permute the insns according to their order in PS, from row 0 to
628 row ii-1, and position them right before LAST. This schedules
629 the insns of the loop kernel. */
631 permute_partial_schedule (partial_schedule_ptr ps, rtx last)
637 for (row = 0; row < ii ; row++)
638 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
639 if (PREV_INSN (last) != ps_ij->node->insn)
640 reorder_insns_nobb (ps_ij->node->first_note, ps_ij->node->insn,
644 /* As part of undoing SMS we return to the original ordering of the
645 instructions inside the loop kernel. Given the partial schedule PS, this
646 function returns the ordering of the instruction according to their CUID
647 in the DDG (PS->G), which is the original order of the instruction before
650 undo_permute_partial_schedule (partial_schedule_ptr ps, rtx last)
654 for (i = 0 ; i < ps->g->num_nodes; i++)
655 if (last == ps->g->nodes[i].insn
656 || last == ps->g->nodes[i].first_note)
658 else if (PREV_INSN (last) != ps->g->nodes[i].insn)
659 reorder_insns_nobb (ps->g->nodes[i].first_note, ps->g->nodes[i].insn,
663 /* Used to generate the prologue & epilogue. Duplicate the subset of
664 nodes whose stages are between FROM_STAGE and TO_STAGE (inclusive
665 of both), together with a prefix/suffix of their reg_moves. */
667 duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
668 int to_stage, int for_prolog)
673 for (row = 0; row < ps->ii; row++)
674 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
676 ddg_node_ptr u_node = ps_ij->node;
678 rtx reg_move = NULL_RTX;
682 /* SCHED_STAGE (u_node) >= from_stage == 0. Generate increasing
683 number of reg_moves starting with the second occurrence of
684 u_node, which is generated if its SCHED_STAGE <= to_stage. */
685 i_reg_moves = to_stage - SCHED_STAGE (u_node) + 1;
686 i_reg_moves = MAX (i_reg_moves, 0);
687 i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
689 /* The reg_moves start from the *first* reg_move backwards. */
692 reg_move = SCHED_FIRST_REG_MOVE (u_node);
693 for (j = 1; j < i_reg_moves; j++)
694 reg_move = PREV_INSN (reg_move);
697 else /* It's for the epilog. */
699 /* SCHED_STAGE (u_node) <= to_stage. Generate all reg_moves,
700 starting to decrease one stage after u_node no longer occurs;
701 that is, generate all reg_moves until
702 SCHED_STAGE (u_node) == from_stage - 1. */
703 i_reg_moves = SCHED_NREG_MOVES (u_node)
704 - (from_stage - SCHED_STAGE (u_node) - 1);
705 i_reg_moves = MAX (i_reg_moves, 0);
706 i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
708 /* The reg_moves start from the *last* reg_move forwards. */
711 reg_move = SCHED_FIRST_REG_MOVE (u_node);
712 for (j = 1; j < SCHED_NREG_MOVES (u_node); j++)
713 reg_move = PREV_INSN (reg_move);
717 for (j = 0; j < i_reg_moves; j++, reg_move = NEXT_INSN (reg_move))
718 emit_insn (copy_rtx (PATTERN (reg_move)));
719 if (SCHED_STAGE (u_node) >= from_stage
720 && SCHED_STAGE (u_node) <= to_stage)
721 duplicate_insn_chain (u_node->first_note, u_node->insn);
726 /* Generate the instructions (including reg_moves) for prolog & epilog. */
728 generate_prolog_epilog (partial_schedule_ptr ps, struct loop * loop, rtx count_reg)
731 int last_stage = PS_STAGE_COUNT (ps) - 1;
734 /* Generate the prolog, inserting its insns on the loop-entry edge. */
738 /* Generate a subtract instruction at the beginning of the prolog to
739 adjust the loop count by STAGE_COUNT. */
740 emit_insn (gen_sub2_insn (count_reg, GEN_INT (last_stage)));
742 for (i = 0; i < last_stage; i++)
743 duplicate_insns_of_cycles (ps, 0, i, 1);
745 /* Put the prolog , on the one and only entry edge. */
746 e = loop_preheader_edge (loop);
747 loop_split_edge_with(e , get_insns());
751 /* Generate the epilog, inserting its insns on the loop-exit edge. */
754 for (i = 0; i < last_stage; i++)
755 duplicate_insns_of_cycles (ps, i + 1, last_stage, 0);
757 /* Put the epilogue on the one and only one exit edge. */
758 gcc_assert (loop->single_exit);
759 e = loop->single_exit;
760 loop_split_edge_with(e , get_insns());
764 /* Return true if all the BBs of the loop are empty except the
767 loop_single_full_bb_p (struct loop *loop)
770 basic_block *bbs = get_loop_body (loop);
772 for (i = 0; i < loop->num_nodes ; i++)
775 bool empty_bb = true;
777 if (bbs[i] == loop->header)
780 /* Make sure that basic blocks other than the header
781 have only notes labels or jumps. */
782 get_ebb_head_tail (bbs[i], bbs[i], &head, &tail);
783 for (; head != NEXT_INSN (tail); head = NEXT_INSN (head))
785 if (NOTE_P (head) || LABEL_P (head)
786 || (INSN_P (head) && JUMP_P (head)))
802 /* A simple loop from SMS point of view; it is a loop that is composed of
803 either a single basic block or two BBs - a header and a latch. */
804 #define SIMPLE_SMS_LOOP_P(loop) ((loop->num_nodes < 3 ) \
805 && (EDGE_COUNT (loop->latch->preds) == 1) \
806 && (EDGE_COUNT (loop->latch->succs) == 1))
808 /* Return true if the loop is in its canonical form and false if not.
809 i.e. SIMPLE_SMS_LOOP_P and have one preheader block, and single exit. */
811 loop_canon_p (struct loop *loop)
814 if (loop->inner || ! loop->outer)
817 if (!loop->single_exit)
821 fprintf (dump_file, "SMS loop many exits ");
826 if (! SIMPLE_SMS_LOOP_P (loop) && ! loop_single_full_bb_p (loop))
830 fprintf (dump_file, "SMS loop many BBs. ");
838 /* If there are more than one entry for the loop,
839 make it one by splitting the first entry edge and
840 redirecting the others to the new BB. */
842 canon_loop (struct loop *loop)
847 /* Avoid annoying special cases of edges going to exit
849 FOR_EACH_EDGE (e, i, EXIT_BLOCK_PTR->preds)
850 if ((e->flags & EDGE_FALLTHRU) && (EDGE_COUNT (e->src->succs) > 1))
851 loop_split_edge_with (e, NULL_RTX);
853 if (loop->latch == loop->header
854 || EDGE_COUNT (loop->latch->succs) > 1)
856 FOR_EACH_EDGE (e, i, loop->header->preds)
857 if (e->src == loop->latch)
859 loop_split_edge_with (e, NULL_RTX);
863 /* Main entry point, perform SMS scheduling on the loops of the function
864 that consist of single basic blocks. */
868 static int passes = 0;
873 unsigned i,num_loops;
874 partial_schedule_ptr ps;
877 basic_block bb = NULL;
878 /* vars to the versioning only if needed*/
880 basic_block condition_bb = NULL;
882 gcov_type trip_count = 0;
884 loops = loop_optimizer_init (LOOPS_HAVE_PREHEADERS
885 | LOOPS_HAVE_MARKED_SINGLE_EXITS);
887 return; /* There is no loops to schedule. */
889 /* Initialize issue_rate. */
890 if (targetm.sched.issue_rate)
892 int temp = reload_completed;
894 reload_completed = 1;
895 issue_rate = targetm.sched.issue_rate ();
896 reload_completed = temp;
901 /* Initialize the scheduler. */
902 current_sched_info = &sms_sched_info;
905 /* Init Data Flow analysis, to be used in interloop dep calculation. */
906 df = df_init (DF_HARD_REGS | DF_EQUIV_NOTES | DF_SUBREGS);
907 df_rd_add_problem (df, 0);
908 df_ru_add_problem (df, 0);
909 df_chain_add_problem (df, DF_DU_CHAIN | DF_UD_CHAIN);
913 df_dump (df, dump_file);
915 /* Allocate memory to hold the DDG array one entry for each loop.
916 We use loop->num as index into this array. */
917 g_arr = XCNEWVEC (ddg_ptr, loops->num);
920 /* Build DDGs for all the relevant loops and hold them in G_ARR
921 indexed by the loop index. */
922 for (i = 0; i < loops->num; i++)
926 struct loop *loop = loops->parray[i];
929 if ((passes++ > MAX_SMS_LOOP_NUMBER) && (MAX_SMS_LOOP_NUMBER != -1))
932 fprintf (dump_file, "SMS reached MAX_PASSES... \n");
937 if (! loop_canon_p (loop))
940 if (! loop_single_full_bb_p (loop))
945 get_ebb_head_tail (bb, bb, &head, &tail);
946 latch_edge = loop_latch_edge (loop);
947 gcc_assert (loop->single_exit);
948 if (loop->single_exit->count)
949 trip_count = latch_edge->count / loop->single_exit->count;
951 /* Perfrom SMS only on loops that their average count is above threshold. */
953 if ( latch_edge->count
954 && (latch_edge->count < loop->single_exit->count * SMS_LOOP_AVERAGE_COUNT_THRESHOLD))
958 fprintf (dump_file, "SMS single-bb-loop\n");
959 if (profile_info && flag_branch_probabilities)
961 fprintf (dump_file, "SMS loop-count ");
962 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
963 (HOST_WIDEST_INT) bb->count);
964 fprintf (dump_file, "\n");
965 fprintf (dump_file, "SMS trip-count ");
966 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
967 (HOST_WIDEST_INT) trip_count);
968 fprintf (dump_file, "\n");
969 fprintf (dump_file, "SMS profile-sum-max ");
970 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
971 (HOST_WIDEST_INT) profile_info->sum_max);
972 fprintf (dump_file, "\n");
978 /* Make sure this is a doloop. */
979 if ( !(count_reg = doloop_register_get (tail)))
982 /* Don't handle BBs with calls or barriers, or !single_set insns. */
983 for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
986 || (INSN_P (insn) && !JUMP_P (insn)
987 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE))
990 if (insn != NEXT_INSN (tail))
995 fprintf (dump_file, "SMS loop-with-call\n");
996 else if (BARRIER_P (insn))
997 fprintf (dump_file, "SMS loop-with-barrier\n");
999 fprintf (dump_file, "SMS loop-with-not-single-set\n");
1000 print_rtl_single (dump_file, insn);
1006 if (! (g = create_ddg (bb, df, 0)))
1009 fprintf (dump_file, "SMS doloop\n");
1016 /* Release Data Flow analysis data structures. */
1020 /* We don't want to perform SMS on new loops - created by versioning. */
1021 num_loops = loops->num;
1022 /* Go over the built DDGs and perfrom SMS for each one of them. */
1023 for (i = 0; i < num_loops; i++)
1026 rtx count_reg, count_init;
1028 unsigned stage_count = 0;
1029 HOST_WIDEST_INT loop_count = 0;
1030 struct loop *loop = loops->parray[i];
1032 if (! (g = g_arr[i]))
1036 print_ddg (dump_file, g);
1038 get_ebb_head_tail (loop->header, loop->header, &head, &tail);
1040 latch_edge = loop_latch_edge (loop);
1041 gcc_assert (loop->single_exit);
1042 if (loop->single_exit->count)
1043 trip_count = latch_edge->count / loop->single_exit->count;
1047 fprintf (dump_file, "SMS single-bb-loop\n");
1048 if (profile_info && flag_branch_probabilities)
1050 fprintf (dump_file, "SMS loop-count ");
1051 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1052 (HOST_WIDEST_INT) bb->count);
1053 fprintf (dump_file, "\n");
1054 fprintf (dump_file, "SMS profile-sum-max ");
1055 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1056 (HOST_WIDEST_INT) profile_info->sum_max);
1057 fprintf (dump_file, "\n");
1059 fprintf (dump_file, "SMS doloop\n");
1060 fprintf (dump_file, "SMS built-ddg %d\n", g->num_nodes);
1061 fprintf (dump_file, "SMS num-loads %d\n", g->num_loads);
1062 fprintf (dump_file, "SMS num-stores %d\n", g->num_stores);
1066 /* In case of th loop have doloop register it gets special
1068 count_init = NULL_RTX;
1069 if ((count_reg = doloop_register_get (tail)))
1071 basic_block pre_header;
1073 pre_header = loop_preheader_edge (loop)->src;
1074 count_init = const_iteration_count (count_reg, pre_header,
1077 gcc_assert (count_reg);
1079 if (dump_file && count_init)
1081 fprintf (dump_file, "SMS const-doloop ");
1082 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1084 fprintf (dump_file, "\n");
1087 node_order = XNEWVEC (int, g->num_nodes);
1089 mii = 1; /* Need to pass some estimate of mii. */
1090 rec_mii = sms_order_nodes (g, mii, node_order);
1091 mii = MAX (res_MII (g), rec_mii);
1092 maxii = (calculate_maxii (g) * SMS_MAX_II_FACTOR) / 100;
1095 fprintf (dump_file, "SMS iis %d %d %d (rec_mii, mii, maxii)\n",
1096 rec_mii, mii, maxii);
1098 /* After sms_order_nodes and before sms_schedule_by_order, to copy over
1100 set_node_sched_params (g);
1102 ps = sms_schedule_by_order (g, mii, maxii, node_order);
1105 stage_count = PS_STAGE_COUNT (ps);
1107 /* Stage count of 1 means that there is no interleaving between
1108 iterations, let the scheduling passes do the job. */
1110 || (count_init && (loop_count <= stage_count))
1111 || (flag_branch_probabilities && (trip_count <= stage_count)))
1115 fprintf (dump_file, "SMS failed... \n");
1116 fprintf (dump_file, "SMS sched-failed (stage-count=%d, loop-count=", stage_count);
1117 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
1118 fprintf (dump_file, ", trip-count=");
1119 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
1120 fprintf (dump_file, ")\n");
1126 int orig_cycles = kernel_number_of_cycles (BB_HEAD (g->bb), BB_END (g->bb));
1128 struct undo_replace_buff_elem *reg_move_replaces;
1133 "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
1135 print_partial_schedule (ps, dump_file);
1137 "SMS Branch (%d) will later be scheduled at cycle %d.\n",
1138 g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
1141 /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
1142 the closing_branch was scheduled and should appear in the last (ii-1)
1143 row. Otherwise, we are free to schedule the branch, and we let nodes
1144 that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
1145 row; this should reduce stage_count to minimum. */
1146 normalize_sched_times (ps);
1147 rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
1148 set_columns_for_ps (ps);
1150 /* Generate the kernel just to be able to measure its cycles. */
1151 permute_partial_schedule (ps, g->closing_branch->first_note);
1152 reg_move_replaces = generate_reg_moves (ps);
1154 /* Get the number of cycles the new kernel expect to execute in. */
1155 new_cycles = kernel_number_of_cycles (BB_HEAD (g->bb), BB_END (g->bb));
1157 /* Get back to the original loop so we can do loop versioning. */
1158 undo_permute_partial_schedule (ps, g->closing_branch->first_note);
1159 if (reg_move_replaces)
1160 undo_generate_reg_moves (ps, reg_move_replaces);
1162 if ( new_cycles >= orig_cycles)
1164 /* SMS is not profitable so undo the permutation and reg move generation
1165 and return the kernel to its original state. */
1167 fprintf (dump_file, "Undoing SMS because it is not profitable.\n");
1174 /* case the BCT count is not known , Do loop-versioning */
1175 if (count_reg && ! count_init)
1177 rtx comp_rtx = gen_rtx_fmt_ee (GT, VOIDmode, count_reg,
1178 GEN_INT(stage_count));
1180 nloop = loop_version (loops, loop, comp_rtx, &condition_bb,
1184 /* Set new iteration count of loop kernel. */
1185 if (count_reg && count_init)
1186 SET_SRC (single_set (count_init)) = GEN_INT (loop_count
1189 /* Now apply the scheduled kernel to the RTL of the loop. */
1190 permute_partial_schedule (ps, g->closing_branch->first_note);
1192 /* Mark this loop as software pipelined so the later
1193 scheduling passes doesn't touch it. */
1194 if (! flag_resched_modulo_sched)
1195 g->bb->flags |= BB_DISABLE_SCHEDULE;
1196 /* The life-info is not valid any more. */
1197 g->bb->flags |= BB_DIRTY;
1199 reg_move_replaces = generate_reg_moves (ps);
1201 print_node_sched_params (dump_file, g->num_nodes);
1202 /* Generate prolog and epilog. */
1203 if (count_reg && !count_init)
1204 generate_prolog_epilog (ps, loop, count_reg);
1206 generate_prolog_epilog (ps, loop, NULL_RTX);
1208 free_undo_replace_buff (reg_move_replaces);
1211 free_partial_schedule (ps);
1212 free (node_sched_params);
1219 /* Release scheduler data, needed until now because of DFA. */
1221 loop_optimizer_finalize (loops);
1224 /* The SMS scheduling algorithm itself
1225 -----------------------------------
1226 Input: 'O' an ordered list of insns of a loop.
1227 Output: A scheduling of the loop - kernel, prolog, and epilogue.
1229 'Q' is the empty Set
1230 'PS' is the partial schedule; it holds the currently scheduled nodes with
1232 'PSP' previously scheduled predecessors.
1233 'PSS' previously scheduled successors.
1234 't(u)' the cycle where u is scheduled.
1235 'l(u)' is the latency of u.
1236 'd(v,u)' is the dependence distance from v to u.
1237 'ASAP(u)' the earliest time at which u could be scheduled as computed in
1238 the node ordering phase.
1239 'check_hardware_resources_conflicts(u, PS, c)'
1240 run a trace around cycle/slot through DFA model
1241 to check resource conflicts involving instruction u
1242 at cycle c given the partial schedule PS.
1243 'add_to_partial_schedule_at_time(u, PS, c)'
1244 Add the node/instruction u to the partial schedule
1246 'calculate_register_pressure(PS)'
1247 Given a schedule of instructions, calculate the register
1248 pressure it implies. One implementation could be the
1249 maximum number of overlapping live ranges.
1250 'maxRP' The maximum allowed register pressure, it is usually derived from the number
1251 registers available in the hardware.
1255 3. for each node u in O in pre-computed order
1256 4. if (PSP(u) != Q && PSS(u) == Q) then
1257 5. Early_start(u) = max ( t(v) + l(v) - d(v,u)*II ) over all every v in PSP(u).
1258 6. start = Early_start; end = Early_start + II - 1; step = 1
1259 11. else if (PSP(u) == Q && PSS(u) != Q) then
1260 12. Late_start(u) = min ( t(v) - l(v) + d(v,u)*II ) over all every v in PSS(u).
1261 13. start = Late_start; end = Late_start - II + 1; step = -1
1262 14. else if (PSP(u) != Q && PSS(u) != Q) then
1263 15. Early_start(u) = max ( t(v) + l(v) - d(v,u)*II ) over all every v in PSP(u).
1264 16. Late_start(u) = min ( t(v) - l(v) + d(v,u)*II ) over all every v in PSS(u).
1265 17. start = Early_start;
1266 18. end = min(Early_start + II - 1 , Late_start);
1268 20. else "if (PSP(u) == Q && PSS(u) == Q)"
1269 21. start = ASAP(u); end = start + II - 1; step = 1
1273 24. for (c = start ; c != end ; c += step)
1274 25. if check_hardware_resources_conflicts(u, PS, c) then
1275 26. add_to_partial_schedule_at_time(u, PS, c)
1280 31. if (success == false) then
1282 33. if (II > maxII) then
1283 34. finish - failed to schedule
1288 39. if (calculate_register_pressure(PS) > maxRP) then
1291 42. compute epilogue & prologue
1292 43. finish - succeeded to schedule
1295 /* A limit on the number of cycles that resource conflicts can span. ??? Should
1296 be provided by DFA, and be dependent on the type of insn scheduled. Currently
1297 set to 0 to save compile time. */
1298 #define DFA_HISTORY SMS_DFA_HISTORY
1300 /* Given the partial schedule PS, this function calculates and returns the
1301 cycles in which we can schedule the node with the given index I.
1302 NOTE: Here we do the backtracking in SMS, in some special cases. We have
1303 noticed that there are several cases in which we fail to SMS the loop
1304 because the sched window of a node is empty due to tight data-deps. In
1305 such cases we want to unschedule some of the predecessors/successors
1306 until we get non-empty scheduling window. It returns -1 if the
1307 scheduling window is empty and zero otherwise. */
1310 get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
1311 sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
1313 int start, step, end;
1315 int u = nodes_order [i];
1316 ddg_node_ptr u_node = &ps->g->nodes[u];
1317 sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
1318 sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
1319 sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
1320 sbitmap u_node_succs = NODE_SUCCESSORS (u_node);
1324 /* 1. compute sched window for u (start, end, step). */
1327 psp_not_empty = sbitmap_a_and_b_cg (psp, u_node_preds, sched_nodes);
1328 pss_not_empty = sbitmap_a_and_b_cg (pss, u_node_succs, sched_nodes);
1330 if (psp_not_empty && !pss_not_empty)
1332 int early_start = INT_MIN;
1335 for (e = u_node->in; e != 0; e = e->next_in)
1337 ddg_node_ptr v_node = e->src;
1338 if (TEST_BIT (sched_nodes, v_node->cuid))
1340 int node_st = SCHED_TIME (v_node)
1341 + e->latency - (e->distance * ii);
1343 early_start = MAX (early_start, node_st);
1345 if (e->data_type == MEM_DEP)
1346 end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1349 start = early_start;
1350 end = MIN (end, early_start + ii);
1354 else if (!psp_not_empty && pss_not_empty)
1356 int late_start = INT_MAX;
1359 for (e = u_node->out; e != 0; e = e->next_out)
1361 ddg_node_ptr v_node = e->dest;
1362 if (TEST_BIT (sched_nodes, v_node->cuid))
1364 late_start = MIN (late_start,
1365 SCHED_TIME (v_node) - e->latency
1366 + (e->distance * ii));
1367 if (e->data_type == MEM_DEP)
1368 end = MAX (end, SCHED_TIME (v_node) - ii + 1);
1372 end = MAX (end, late_start - ii);
1376 else if (psp_not_empty && pss_not_empty)
1378 int early_start = INT_MIN;
1379 int late_start = INT_MAX;
1383 for (e = u_node->in; e != 0; e = e->next_in)
1385 ddg_node_ptr v_node = e->src;
1387 if (TEST_BIT (sched_nodes, v_node->cuid))
1389 early_start = MAX (early_start,
1390 SCHED_TIME (v_node) + e->latency
1391 - (e->distance * ii));
1392 if (e->data_type == MEM_DEP)
1393 end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1396 for (e = u_node->out; e != 0; e = e->next_out)
1398 ddg_node_ptr v_node = e->dest;
1400 if (TEST_BIT (sched_nodes, v_node->cuid))
1402 late_start = MIN (late_start,
1403 SCHED_TIME (v_node) - e->latency
1404 + (e->distance * ii));
1405 if (e->data_type == MEM_DEP)
1406 start = MAX (start, SCHED_TIME (v_node) - ii + 1);
1409 start = MAX (start, early_start);
1410 end = MIN (end, MIN (early_start + ii, late_start + 1));
1413 else /* psp is empty && pss is empty. */
1415 start = SCHED_ASAP (u_node);
1426 if ((start >= end && step == 1) || (start <= end && step == -1))
1432 /* This function implements the scheduling algorithm for SMS according to the
1434 static partial_schedule_ptr
1435 sms_schedule_by_order (ddg_ptr g, int mii, int maxii, int *nodes_order)
1439 int try_again_with_larger_ii = true;
1440 int num_nodes = g->num_nodes;
1442 int start, end, step; /* Place together into one struct? */
1443 sbitmap sched_nodes = sbitmap_alloc (num_nodes);
1444 sbitmap must_precede = sbitmap_alloc (num_nodes);
1445 sbitmap must_follow = sbitmap_alloc (num_nodes);
1446 sbitmap tobe_scheduled = sbitmap_alloc (num_nodes);
1448 partial_schedule_ptr ps = create_partial_schedule (ii, g, DFA_HISTORY);
1450 sbitmap_ones (tobe_scheduled);
1451 sbitmap_zero (sched_nodes);
1453 while ((! sbitmap_equal (tobe_scheduled, sched_nodes)
1454 || try_again_with_larger_ii ) && ii < maxii)
1457 bool unscheduled_nodes = false;
1460 fprintf(dump_file, "Starting with ii=%d\n", ii);
1461 if (try_again_with_larger_ii)
1463 try_again_with_larger_ii = false;
1464 sbitmap_zero (sched_nodes);
1467 for (i = 0; i < num_nodes; i++)
1469 int u = nodes_order[i];
1470 ddg_node_ptr u_node = &ps->g->nodes[u];
1471 rtx insn = u_node->insn;
1475 RESET_BIT (tobe_scheduled, u);
1479 if (JUMP_P (insn)) /* Closing branch handled later. */
1481 RESET_BIT (tobe_scheduled, u);
1485 if (TEST_BIT (sched_nodes, u))
1488 /* Try to get non-empty scheduling window. */
1490 while (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start, &step, &end) < 0
1493 unscheduled_nodes = true;
1494 if (TEST_BIT (NODE_PREDECESSORS (u_node), nodes_order[j - 1])
1495 || TEST_BIT (NODE_SUCCESSORS (u_node), nodes_order[j - 1]))
1497 ps_unschedule_node (ps, &ps->g->nodes[nodes_order[j - 1]]);
1498 RESET_BIT (sched_nodes, nodes_order [j - 1]);
1504 /* ??? Try backtracking instead of immediately ii++? */
1506 try_again_with_larger_ii = true;
1507 reset_partial_schedule (ps, ii);
1510 /* 2. Try scheduling u in window. */
1512 fprintf(dump_file, "Trying to schedule node %d in (%d .. %d) step %d\n",
1513 u, start, end, step);
1515 /* use must_follow & must_precede bitmaps to determine order
1516 of nodes within the cycle. */
1517 sbitmap_zero (must_precede);
1518 sbitmap_zero (must_follow);
1519 for (e = u_node->in; e != 0; e = e->next_in)
1520 if (TEST_BIT (sched_nodes, e->src->cuid)
1521 && e->latency == (ii * e->distance)
1522 && start == SCHED_TIME (e->src))
1523 SET_BIT (must_precede, e->src->cuid);
1525 for (e = u_node->out; e != 0; e = e->next_out)
1526 if (TEST_BIT (sched_nodes, e->dest->cuid)
1527 && e->latency == (ii * e->distance)
1528 && end == SCHED_TIME (e->dest))
1529 SET_BIT (must_follow, e->dest->cuid);
1532 if ((step > 0 && start < end) || (step < 0 && start > end))
1533 for (c = start; c != end; c += step)
1537 psi = ps_add_node_check_conflicts (ps, u_node, c,
1543 SCHED_TIME (u_node) = c;
1544 SET_BIT (sched_nodes, u);
1547 fprintf(dump_file, "Schedule in %d\n", c);
1553 /* ??? Try backtracking instead of immediately ii++? */
1555 try_again_with_larger_ii = true;
1556 reset_partial_schedule (ps, ii);
1559 if (unscheduled_nodes)
1562 /* ??? If (success), check register pressure estimates. */
1563 } /* Continue with next node. */
1564 } /* While try_again_with_larger_ii. */
1566 sbitmap_free (sched_nodes);
1567 sbitmap_free (must_precede);
1568 sbitmap_free (must_follow);
1569 sbitmap_free (tobe_scheduled);
1573 free_partial_schedule (ps);
1580 /* This page implements the algorithm for ordering the nodes of a DDG
1581 for modulo scheduling, activated through the
1582 "int sms_order_nodes (ddg_ptr, int mii, int * result)" API. */
1584 #define ORDER_PARAMS(x) ((struct node_order_params *) (x)->aux.info)
1585 #define ASAP(x) (ORDER_PARAMS ((x))->asap)
1586 #define ALAP(x) (ORDER_PARAMS ((x))->alap)
1587 #define HEIGHT(x) (ORDER_PARAMS ((x))->height)
1588 #define MOB(x) (ALAP ((x)) - ASAP ((x)))
1589 #define DEPTH(x) (ASAP ((x)))
1591 typedef struct node_order_params * nopa;
1593 static void order_nodes_of_sccs (ddg_all_sccs_ptr, int * result);
1594 static int order_nodes_in_scc (ddg_ptr, sbitmap, sbitmap, int*, int);
1595 static nopa calculate_order_params (ddg_ptr, int mii);
1596 static int find_max_asap (ddg_ptr, sbitmap);
1597 static int find_max_hv_min_mob (ddg_ptr, sbitmap);
1598 static int find_max_dv_min_mob (ddg_ptr, sbitmap);
1600 enum sms_direction {BOTTOMUP, TOPDOWN};
1602 struct node_order_params
1609 /* Check if NODE_ORDER contains a permutation of 0 .. NUM_NODES-1. */
1611 check_nodes_order (int *node_order, int num_nodes)
1614 sbitmap tmp = sbitmap_alloc (num_nodes);
1618 for (i = 0; i < num_nodes; i++)
1620 int u = node_order[i];
1622 gcc_assert (u < num_nodes && u >= 0 && !TEST_BIT (tmp, u));
1630 /* Order the nodes of G for scheduling and pass the result in
1631 NODE_ORDER. Also set aux.count of each node to ASAP.
1632 Return the recMII for the given DDG. */
1634 sms_order_nodes (ddg_ptr g, int mii, int * node_order)
1638 ddg_all_sccs_ptr sccs = create_ddg_all_sccs (g);
1640 nopa nops = calculate_order_params (g, mii);
1642 order_nodes_of_sccs (sccs, node_order);
1644 if (sccs->num_sccs > 0)
1645 /* First SCC has the largest recurrence_length. */
1646 rec_mii = sccs->sccs[0]->recurrence_length;
1648 /* Save ASAP before destroying node_order_params. */
1649 for (i = 0; i < g->num_nodes; i++)
1651 ddg_node_ptr v = &g->nodes[i];
1652 v->aux.count = ASAP (v);
1656 free_ddg_all_sccs (sccs);
1657 check_nodes_order (node_order, g->num_nodes);
1663 order_nodes_of_sccs (ddg_all_sccs_ptr all_sccs, int * node_order)
1666 ddg_ptr g = all_sccs->ddg;
1667 int num_nodes = g->num_nodes;
1668 sbitmap prev_sccs = sbitmap_alloc (num_nodes);
1669 sbitmap on_path = sbitmap_alloc (num_nodes);
1670 sbitmap tmp = sbitmap_alloc (num_nodes);
1671 sbitmap ones = sbitmap_alloc (num_nodes);
1673 sbitmap_zero (prev_sccs);
1674 sbitmap_ones (ones);
1676 /* Perfrom the node ordering starting from the SCC with the highest recMII.
1677 For each SCC order the nodes according to their ASAP/ALAP/HEIGHT etc. */
1678 for (i = 0; i < all_sccs->num_sccs; i++)
1680 ddg_scc_ptr scc = all_sccs->sccs[i];
1682 /* Add nodes on paths from previous SCCs to the current SCC. */
1683 find_nodes_on_paths (on_path, g, prev_sccs, scc->nodes);
1684 sbitmap_a_or_b (tmp, scc->nodes, on_path);
1686 /* Add nodes on paths from the current SCC to previous SCCs. */
1687 find_nodes_on_paths (on_path, g, scc->nodes, prev_sccs);
1688 sbitmap_a_or_b (tmp, tmp, on_path);
1690 /* Remove nodes of previous SCCs from current extended SCC. */
1691 sbitmap_difference (tmp, tmp, prev_sccs);
1693 pos = order_nodes_in_scc (g, prev_sccs, tmp, node_order, pos);
1694 /* Above call to order_nodes_in_scc updated prev_sccs |= tmp. */
1697 /* Handle the remaining nodes that do not belong to any scc. Each call
1698 to order_nodes_in_scc handles a single connected component. */
1699 while (pos < g->num_nodes)
1701 sbitmap_difference (tmp, ones, prev_sccs);
1702 pos = order_nodes_in_scc (g, prev_sccs, tmp, node_order, pos);
1704 sbitmap_free (prev_sccs);
1705 sbitmap_free (on_path);
1707 sbitmap_free (ones);
1710 /* MII is needed if we consider backarcs (that do not close recursive cycles). */
1711 static struct node_order_params *
1712 calculate_order_params (ddg_ptr g, int mii ATTRIBUTE_UNUSED)
1716 int num_nodes = g->num_nodes;
1718 /* Allocate a place to hold ordering params for each node in the DDG. */
1719 nopa node_order_params_arr;
1721 /* Initialize of ASAP/ALAP/HEIGHT to zero. */
1722 node_order_params_arr = (nopa) xcalloc (num_nodes,
1723 sizeof (struct node_order_params));
1725 /* Set the aux pointer of each node to point to its order_params structure. */
1726 for (u = 0; u < num_nodes; u++)
1727 g->nodes[u].aux.info = &node_order_params_arr[u];
1729 /* Disregarding a backarc from each recursive cycle to obtain a DAG,
1730 calculate ASAP, ALAP, mobility, distance, and height for each node
1731 in the dependence (direct acyclic) graph. */
1733 /* We assume that the nodes in the array are in topological order. */
1736 for (u = 0; u < num_nodes; u++)
1738 ddg_node_ptr u_node = &g->nodes[u];
1741 for (e = u_node->in; e; e = e->next_in)
1742 if (e->distance == 0)
1743 ASAP (u_node) = MAX (ASAP (u_node),
1744 ASAP (e->src) + e->latency);
1745 max_asap = MAX (max_asap, ASAP (u_node));
1748 for (u = num_nodes - 1; u > -1; u--)
1750 ddg_node_ptr u_node = &g->nodes[u];
1752 ALAP (u_node) = max_asap;
1753 HEIGHT (u_node) = 0;
1754 for (e = u_node->out; e; e = e->next_out)
1755 if (e->distance == 0)
1757 ALAP (u_node) = MIN (ALAP (u_node),
1758 ALAP (e->dest) - e->latency);
1759 HEIGHT (u_node) = MAX (HEIGHT (u_node),
1760 HEIGHT (e->dest) + e->latency);
1764 return node_order_params_arr;
1768 find_max_asap (ddg_ptr g, sbitmap nodes)
1773 sbitmap_iterator sbi;
1775 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1777 ddg_node_ptr u_node = &g->nodes[u];
1779 if (max_asap < ASAP (u_node))
1781 max_asap = ASAP (u_node);
1789 find_max_hv_min_mob (ddg_ptr g, sbitmap nodes)
1793 int min_mob = INT_MAX;
1795 sbitmap_iterator sbi;
1797 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1799 ddg_node_ptr u_node = &g->nodes[u];
1801 if (max_hv < HEIGHT (u_node))
1803 max_hv = HEIGHT (u_node);
1804 min_mob = MOB (u_node);
1807 else if ((max_hv == HEIGHT (u_node))
1808 && (min_mob > MOB (u_node)))
1810 min_mob = MOB (u_node);
1818 find_max_dv_min_mob (ddg_ptr g, sbitmap nodes)
1822 int min_mob = INT_MAX;
1824 sbitmap_iterator sbi;
1826 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1828 ddg_node_ptr u_node = &g->nodes[u];
1830 if (max_dv < DEPTH (u_node))
1832 max_dv = DEPTH (u_node);
1833 min_mob = MOB (u_node);
1836 else if ((max_dv == DEPTH (u_node))
1837 && (min_mob > MOB (u_node)))
1839 min_mob = MOB (u_node);
1846 /* Places the nodes of SCC into the NODE_ORDER array starting
1847 at position POS, according to the SMS ordering algorithm.
1848 NODES_ORDERED (in&out parameter) holds the bitset of all nodes in
1849 the NODE_ORDER array, starting from position zero. */
1851 order_nodes_in_scc (ddg_ptr g, sbitmap nodes_ordered, sbitmap scc,
1852 int * node_order, int pos)
1854 enum sms_direction dir;
1855 int num_nodes = g->num_nodes;
1856 sbitmap workset = sbitmap_alloc (num_nodes);
1857 sbitmap tmp = sbitmap_alloc (num_nodes);
1858 sbitmap zero_bitmap = sbitmap_alloc (num_nodes);
1859 sbitmap predecessors = sbitmap_alloc (num_nodes);
1860 sbitmap successors = sbitmap_alloc (num_nodes);
1862 sbitmap_zero (predecessors);
1863 find_predecessors (predecessors, g, nodes_ordered);
1865 sbitmap_zero (successors);
1866 find_successors (successors, g, nodes_ordered);
1869 if (sbitmap_a_and_b_cg (tmp, predecessors, scc))
1871 sbitmap_copy (workset, tmp);
1874 else if (sbitmap_a_and_b_cg (tmp, successors, scc))
1876 sbitmap_copy (workset, tmp);
1883 sbitmap_zero (workset);
1884 if ((u = find_max_asap (g, scc)) >= 0)
1885 SET_BIT (workset, u);
1889 sbitmap_zero (zero_bitmap);
1890 while (!sbitmap_equal (workset, zero_bitmap))
1893 ddg_node_ptr v_node;
1894 sbitmap v_node_preds;
1895 sbitmap v_node_succs;
1899 while (!sbitmap_equal (workset, zero_bitmap))
1901 v = find_max_hv_min_mob (g, workset);
1902 v_node = &g->nodes[v];
1903 node_order[pos++] = v;
1904 v_node_succs = NODE_SUCCESSORS (v_node);
1905 sbitmap_a_and_b (tmp, v_node_succs, scc);
1907 /* Don't consider the already ordered successors again. */
1908 sbitmap_difference (tmp, tmp, nodes_ordered);
1909 sbitmap_a_or_b (workset, workset, tmp);
1910 RESET_BIT (workset, v);
1911 SET_BIT (nodes_ordered, v);
1914 sbitmap_zero (predecessors);
1915 find_predecessors (predecessors, g, nodes_ordered);
1916 sbitmap_a_and_b (workset, predecessors, scc);
1920 while (!sbitmap_equal (workset, zero_bitmap))
1922 v = find_max_dv_min_mob (g, workset);
1923 v_node = &g->nodes[v];
1924 node_order[pos++] = v;
1925 v_node_preds = NODE_PREDECESSORS (v_node);
1926 sbitmap_a_and_b (tmp, v_node_preds, scc);
1928 /* Don't consider the already ordered predecessors again. */
1929 sbitmap_difference (tmp, tmp, nodes_ordered);
1930 sbitmap_a_or_b (workset, workset, tmp);
1931 RESET_BIT (workset, v);
1932 SET_BIT (nodes_ordered, v);
1935 sbitmap_zero (successors);
1936 find_successors (successors, g, nodes_ordered);
1937 sbitmap_a_and_b (workset, successors, scc);
1941 sbitmap_free (workset);
1942 sbitmap_free (zero_bitmap);
1943 sbitmap_free (predecessors);
1944 sbitmap_free (successors);
1949 /* This page contains functions for manipulating partial-schedules during
1950 modulo scheduling. */
1952 /* Create a partial schedule and allocate a memory to hold II rows. */
1954 static partial_schedule_ptr
1955 create_partial_schedule (int ii, ddg_ptr g, int history)
1957 partial_schedule_ptr ps = XNEW (struct partial_schedule);
1958 ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
1960 ps->history = history;
1961 ps->min_cycle = INT_MAX;
1962 ps->max_cycle = INT_MIN;
1968 /* Free the PS_INSNs in rows array of the given partial schedule.
1969 ??? Consider caching the PS_INSN's. */
1971 free_ps_insns (partial_schedule_ptr ps)
1975 for (i = 0; i < ps->ii; i++)
1979 ps_insn_ptr ps_insn = ps->rows[i]->next_in_row;
1982 ps->rows[i] = ps_insn;
1988 /* Free all the memory allocated to the partial schedule. */
1991 free_partial_schedule (partial_schedule_ptr ps)
2000 /* Clear the rows array with its PS_INSNs, and create a new one with
2004 reset_partial_schedule (partial_schedule_ptr ps, int new_ii)
2009 if (new_ii == ps->ii)
2011 ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii
2012 * sizeof (ps_insn_ptr));
2013 memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr));
2015 ps->min_cycle = INT_MAX;
2016 ps->max_cycle = INT_MIN;
2019 /* Prints the partial schedule as an ii rows array, for each rows
2020 print the ids of the insns in it. */
2022 print_partial_schedule (partial_schedule_ptr ps, FILE *dump)
2026 for (i = 0; i < ps->ii; i++)
2028 ps_insn_ptr ps_i = ps->rows[i];
2030 fprintf (dump, "\n[CYCLE %d ]: ", i);
2033 fprintf (dump, "%d, ",
2034 INSN_UID (ps_i->node->insn));
2035 ps_i = ps_i->next_in_row;
2040 /* Creates an object of PS_INSN and initializes it to the given parameters. */
2042 create_ps_insn (ddg_node_ptr node, int rest_count, int cycle)
2044 ps_insn_ptr ps_i = XNEW (struct ps_insn);
2047 ps_i->next_in_row = NULL;
2048 ps_i->prev_in_row = NULL;
2049 ps_i->row_rest_count = rest_count;
2050 ps_i->cycle = cycle;
2056 /* Removes the given PS_INSN from the partial schedule. Returns false if the
2057 node is not found in the partial schedule, else returns true. */
2059 remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i)
2066 row = SMODULO (ps_i->cycle, ps->ii);
2067 if (! ps_i->prev_in_row)
2069 if (ps_i != ps->rows[row])
2072 ps->rows[row] = ps_i->next_in_row;
2074 ps->rows[row]->prev_in_row = NULL;
2078 ps_i->prev_in_row->next_in_row = ps_i->next_in_row;
2079 if (ps_i->next_in_row)
2080 ps_i->next_in_row->prev_in_row = ps_i->prev_in_row;
2086 /* Unlike what literature describes for modulo scheduling (which focuses
2087 on VLIW machines) the order of the instructions inside a cycle is
2088 important. Given the bitmaps MUST_FOLLOW and MUST_PRECEDE we know
2089 where the current instruction should go relative to the already
2090 scheduled instructions in the given cycle. Go over these
2091 instructions and find the first possible column to put it in. */
2093 ps_insn_find_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
2094 sbitmap must_precede, sbitmap must_follow)
2096 ps_insn_ptr next_ps_i;
2097 ps_insn_ptr first_must_follow = NULL;
2098 ps_insn_ptr last_must_precede = NULL;
2104 row = SMODULO (ps_i->cycle, ps->ii);
2106 /* Find the first must follow and the last must precede
2107 and insert the node immediately after the must precede
2108 but make sure that it there is no must follow after it. */
2109 for (next_ps_i = ps->rows[row];
2111 next_ps_i = next_ps_i->next_in_row)
2113 if (TEST_BIT (must_follow, next_ps_i->node->cuid)
2114 && ! first_must_follow)
2115 first_must_follow = next_ps_i;
2116 if (TEST_BIT (must_precede, next_ps_i->node->cuid))
2118 /* If we have already met a node that must follow, then
2119 there is no possible column. */
2120 if (first_must_follow)
2123 last_must_precede = next_ps_i;
2127 /* Now insert the node after INSERT_AFTER_PSI. */
2129 if (! last_must_precede)
2131 ps_i->next_in_row = ps->rows[row];
2132 ps_i->prev_in_row = NULL;
2133 if (ps_i->next_in_row)
2134 ps_i->next_in_row->prev_in_row = ps_i;
2135 ps->rows[row] = ps_i;
2139 ps_i->next_in_row = last_must_precede->next_in_row;
2140 last_must_precede->next_in_row = ps_i;
2141 ps_i->prev_in_row = last_must_precede;
2142 if (ps_i->next_in_row)
2143 ps_i->next_in_row->prev_in_row = ps_i;
2149 /* Advances the PS_INSN one column in its current row; returns false
2150 in failure and true in success. Bit N is set in MUST_FOLLOW if
2151 the node with cuid N must be come after the node pointed to by
2152 PS_I when scheduled in the same cycle. */
2154 ps_insn_advance_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
2155 sbitmap must_follow)
2157 ps_insn_ptr prev, next;
2159 ddg_node_ptr next_node;
2164 row = SMODULO (ps_i->cycle, ps->ii);
2166 if (! ps_i->next_in_row)
2169 next_node = ps_i->next_in_row->node;
2171 /* Check if next_in_row is dependent on ps_i, both having same sched
2172 times (typically ANTI_DEP). If so, ps_i cannot skip over it. */
2173 if (TEST_BIT (must_follow, next_node->cuid))
2176 /* Advance PS_I over its next_in_row in the doubly linked list. */
2177 prev = ps_i->prev_in_row;
2178 next = ps_i->next_in_row;
2180 if (ps_i == ps->rows[row])
2181 ps->rows[row] = next;
2183 ps_i->next_in_row = next->next_in_row;
2185 if (next->next_in_row)
2186 next->next_in_row->prev_in_row = ps_i;
2188 next->next_in_row = ps_i;
2189 ps_i->prev_in_row = next;
2191 next->prev_in_row = prev;
2193 prev->next_in_row = next;
2198 /* Inserts a DDG_NODE to the given partial schedule at the given cycle.
2199 Returns 0 if this is not possible and a PS_INSN otherwise. Bit N is
2200 set in MUST_PRECEDE/MUST_FOLLOW if the node with cuid N must be come
2201 before/after (respectively) the node pointed to by PS_I when scheduled
2202 in the same cycle. */
2204 add_node_to_ps (partial_schedule_ptr ps, ddg_node_ptr node, int cycle,
2205 sbitmap must_precede, sbitmap must_follow)
2209 int row = SMODULO (cycle, ps->ii);
2212 && ps->rows[row]->row_rest_count >= issue_rate)
2216 rest_count += ps->rows[row]->row_rest_count;
2218 ps_i = create_ps_insn (node, rest_count, cycle);
2220 /* Finds and inserts PS_I according to MUST_FOLLOW and
2222 if (! ps_insn_find_column (ps, ps_i, must_precede, must_follow))
2231 /* Advance time one cycle. Assumes DFA is being used. */
2233 advance_one_cycle (void)
2235 if (targetm.sched.dfa_pre_cycle_insn)
2236 state_transition (curr_state,
2237 targetm.sched.dfa_pre_cycle_insn ());
2239 state_transition (curr_state, NULL);
2241 if (targetm.sched.dfa_post_cycle_insn)
2242 state_transition (curr_state,
2243 targetm.sched.dfa_post_cycle_insn ());
2246 /* Given the kernel of a loop (from FIRST_INSN to LAST_INSN), finds
2247 the number of cycles according to DFA that the kernel fits in,
2248 we use this to check if we done well with SMS after we add
2249 register moves. In some cases register moves overhead makes
2250 it even worse than the original loop. We want SMS to be performed
2251 when it gives less cycles after register moves are added. */
2253 kernel_number_of_cycles (rtx first_insn, rtx last_insn)
2257 int can_issue_more = issue_rate;
2259 state_reset (curr_state);
2261 for (insn = first_insn;
2262 insn != NULL_RTX && insn != last_insn;
2263 insn = NEXT_INSN (insn))
2265 if (! INSN_P (insn) || GET_CODE (PATTERN (insn)) == USE)
2268 /* Check if there is room for the current insn. */
2269 if (!can_issue_more || state_dead_lock_p (curr_state))
2272 advance_one_cycle ();
2273 can_issue_more = issue_rate;
2276 /* Update the DFA state and return with failure if the DFA found
2277 recource conflicts. */
2278 if (state_transition (curr_state, insn) >= 0)
2281 advance_one_cycle ();
2282 can_issue_more = issue_rate;
2285 if (targetm.sched.variable_issue)
2287 targetm.sched.variable_issue (sched_dump, sched_verbose,
2288 insn, can_issue_more);
2289 /* A naked CLOBBER or USE generates no instruction, so don't
2290 let them consume issue slots. */
2291 else if (GET_CODE (PATTERN (insn)) != USE
2292 && GET_CODE (PATTERN (insn)) != CLOBBER)
2298 /* Checks if PS has resource conflicts according to DFA, starting from
2299 FROM cycle to TO cycle; returns true if there are conflicts and false
2300 if there are no conflicts. Assumes DFA is being used. */
2302 ps_has_conflicts (partial_schedule_ptr ps, int from, int to)
2306 state_reset (curr_state);
2308 for (cycle = from; cycle <= to; cycle++)
2310 ps_insn_ptr crr_insn;
2311 /* Holds the remaining issue slots in the current row. */
2312 int can_issue_more = issue_rate;
2314 /* Walk through the DFA for the current row. */
2315 for (crr_insn = ps->rows[SMODULO (cycle, ps->ii)];
2317 crr_insn = crr_insn->next_in_row)
2319 rtx insn = crr_insn->node->insn;
2324 /* Check if there is room for the current insn. */
2325 if (!can_issue_more || state_dead_lock_p (curr_state))
2328 /* Update the DFA state and return with failure if the DFA found
2329 recource conflicts. */
2330 if (state_transition (curr_state, insn) >= 0)
2333 if (targetm.sched.variable_issue)
2335 targetm.sched.variable_issue (sched_dump, sched_verbose,
2336 insn, can_issue_more);
2337 /* A naked CLOBBER or USE generates no instruction, so don't
2338 let them consume issue slots. */
2339 else if (GET_CODE (PATTERN (insn)) != USE
2340 && GET_CODE (PATTERN (insn)) != CLOBBER)
2344 /* Advance the DFA to the next cycle. */
2345 advance_one_cycle ();
2350 /* Checks if the given node causes resource conflicts when added to PS at
2351 cycle C. If not the node is added to PS and returned; otherwise zero
2352 is returned. Bit N is set in MUST_PRECEDE/MUST_FOLLOW if the node with
2353 cuid N must be come before/after (respectively) the node pointed to by
2354 PS_I when scheduled in the same cycle. */
2356 ps_add_node_check_conflicts (partial_schedule_ptr ps, ddg_node_ptr n,
2357 int c, sbitmap must_precede,
2358 sbitmap must_follow)
2360 int has_conflicts = 0;
2363 /* First add the node to the PS, if this succeeds check for
2364 conflicts, trying different issue slots in the same row. */
2365 if (! (ps_i = add_node_to_ps (ps, n, c, must_precede, must_follow)))
2366 return NULL; /* Failed to insert the node at the given cycle. */
2368 has_conflicts = ps_has_conflicts (ps, c, c)
2370 && ps_has_conflicts (ps,
2374 /* Try different issue slots to find one that the given node can be
2375 scheduled in without conflicts. */
2376 while (has_conflicts)
2378 if (! ps_insn_advance_column (ps, ps_i, must_follow))
2380 has_conflicts = ps_has_conflicts (ps, c, c)
2382 && ps_has_conflicts (ps,
2389 remove_node_from_ps (ps, ps_i);
2393 ps->min_cycle = MIN (ps->min_cycle, c);
2394 ps->max_cycle = MAX (ps->max_cycle, c);
2398 /* Rotate the rows of PS such that insns scheduled at time
2399 START_CYCLE will appear in row 0. Updates max/min_cycles. */
2401 rotate_partial_schedule (partial_schedule_ptr ps, int start_cycle)
2403 int i, row, backward_rotates;
2404 int last_row = ps->ii - 1;
2406 if (start_cycle == 0)
2409 backward_rotates = SMODULO (start_cycle, ps->ii);
2411 /* Revisit later and optimize this into a single loop. */
2412 for (i = 0; i < backward_rotates; i++)
2414 ps_insn_ptr first_row = ps->rows[0];
2416 for (row = 0; row < last_row; row++)
2417 ps->rows[row] = ps->rows[row+1];
2419 ps->rows[last_row] = first_row;
2422 ps->max_cycle -= start_cycle;
2423 ps->min_cycle -= start_cycle;
2426 /* Remove the node N from the partial schedule PS; because we restart the DFA
2427 each time we want to check for resource conflicts; this is equivalent to
2428 unscheduling the node N. */
2430 ps_unschedule_node (partial_schedule_ptr ps, ddg_node_ptr n)
2433 int row = SMODULO (SCHED_TIME (n), ps->ii);
2435 if (row < 0 || row > ps->ii)
2438 for (ps_i = ps->rows[row];
2439 ps_i && ps_i->node != n;
2440 ps_i = ps_i->next_in_row);
2444 return remove_node_from_ps (ps, ps_i);
2446 #endif /* INSN_SCHEDULING */
2449 gate_handle_sms (void)
2451 return (optimize > 0 && flag_modulo_sched);
2455 /* Run instruction scheduler. */
2456 /* Perform SMS module scheduling. */
2458 rest_of_handle_sms (void)
2460 #ifdef INSN_SCHEDULING
2463 /* We want to be able to create new pseudos. */
2465 /* Collect loop information to be used in SMS. */
2466 cfg_layout_initialize (CLEANUP_UPDATE_LIFE);
2469 /* Update the life information, because we add pseudos. */
2470 max_regno = max_reg_num ();
2471 allocate_reg_info (max_regno, FALSE, FALSE);
2472 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES,
2475 | PROP_KILL_DEAD_CODE
2476 | PROP_SCAN_DEAD_CODE));
2480 /* Finalize layout changes. */
2482 if (bb->next_bb != EXIT_BLOCK_PTR)
2483 bb->aux = bb->next_bb;
2484 cfg_layout_finalize ();
2485 free_dominance_info (CDI_DOMINATORS);
2486 #endif /* INSN_SCHEDULING */
2490 struct tree_opt_pass pass_sms =
2493 gate_handle_sms, /* gate */
2494 rest_of_handle_sms, /* execute */
2497 0, /* static_pass_number */
2499 0, /* properties_required */
2500 0, /* properties_provided */
2501 0, /* properties_destroyed */
2502 TODO_dump_func, /* todo_flags_start */
2504 TODO_ggc_collect, /* todo_flags_finish */