1 @c Copyright (C) 1988, 89, 92, 93, 94, 96, 1998, 2000 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Patterns:: How to write instruction patterns.
23 * Example:: An explained example of a @code{define_insn} pattern.
24 * RTL Template:: The RTL template defines what insns match a pattern.
25 * Output Template:: The output template says how to make assembler code
27 * Output Statement:: For more generality, write C code to output
29 * Constraints:: When not all operands are general operands.
30 * Standard Names:: Names mark patterns to use for code generation.
31 * Pattern Ordering:: When the order of patterns makes a difference.
32 * Dependent Patterns:: Having one pattern may make you need another.
33 * Jump Patterns:: Special considerations for patterns for jump insns.
34 * Insn Canonicalizations::Canonicalization of Instructions
35 * Expander Definitions::Generating a sequence of several RTL insns
36 for a standard operation.
37 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
38 * Peephole Definitions::Defining machine-specific peephole optimizations.
39 * Insn Attributes:: Specifying the value of attributes for generated insns.
43 @section Everything about Instruction Patterns
45 @cindex instruction patterns
48 Each instruction pattern contains an incomplete RTL expression, with pieces
49 to be filled in later, operand constraints that restrict how the pieces can
50 be filled in, and an output pattern or C code to generate the assembler
51 output, all wrapped up in a @code{define_insn} expression.
53 A @code{define_insn} is an RTL expression containing four or five operands:
57 An optional name. The presence of a name indicate that this instruction
58 pattern can perform a certain standard job for the RTL-generation
59 pass of the compiler. This pass knows certain names and will use
60 the instruction patterns with those names, if the names are defined
61 in the machine description.
63 The absence of a name is indicated by writing an empty string
64 where the name should go. Nameless instruction patterns are never
65 used for generating RTL code, but they may permit several simpler insns
66 to be combined later on.
68 Names that are not thus known and used in RTL-generation have no
69 effect; they are equivalent to no name at all.
72 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
73 RTL expressions which show what the instruction should look like. It is
74 incomplete because it may contain @code{match_operand},
75 @code{match_operator}, and @code{match_dup} expressions that stand for
76 operands of the instruction.
78 If the vector has only one element, that element is the template for the
79 instruction pattern. If the vector has multiple elements, then the
80 instruction pattern is a @code{parallel} expression containing the
84 @cindex pattern conditions
85 @cindex conditions, in patterns
86 A condition. This is a string which contains a C expression that is
87 the final test to decide whether an insn body matches this pattern.
89 @cindex named patterns and conditions
90 For a named pattern, the condition (if present) may not depend on
91 the data in the insn being matched, but only the target-machine-type
92 flags. The compiler needs to test these conditions during
93 initialization in order to learn exactly which named instructions are
94 available in a particular run.
97 For nameless patterns, the condition is applied only when matching an
98 individual insn, and only after the insn has matched the pattern's
99 recognition template. The insn's operands may be found in the vector
103 The @dfn{output template}: a string that says how to output matching
104 insns as assembler code. @samp{%} in this string specifies where
105 to substitute the value of an operand. @xref{Output Template}.
107 When simple substitution isn't general enough, you can specify a piece
108 of C code to compute the output. @xref{Output Statement}.
111 Optionally, a vector containing the values of attributes for insns matching
112 this pattern. @xref{Insn Attributes}.
116 @section Example of @code{define_insn}
117 @cindex @code{define_insn} example
119 Here is an actual example of an instruction pattern, for the 68000/68020.
124 (match_operand:SI 0 "general_operand" "rm"))]
127 @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
129 return \"cmpl #0,%0\"; @}")
132 This is an instruction that sets the condition codes based on the value of
133 a general operand. It has no condition, so any insn whose RTL description
134 has the form shown may be handled according to this pattern. The name
135 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
136 pass that, when it is necessary to test such a value, an insn to do so
137 can be constructed using this pattern.
139 The output control string is a piece of C code which chooses which
140 output template to return based on the kind of operand and the specific
141 type of CPU for which code is being generated.
143 @samp{"rm"} is an operand constraint. Its meaning is explained below.
146 @section RTL Template
147 @cindex RTL insn template
148 @cindex generating insns
149 @cindex insns, generating
150 @cindex recognizing insns
151 @cindex insns, recognizing
153 The RTL template is used to define which insns match the particular pattern
154 and how to find their operands. For named patterns, the RTL template also
155 says how to construct an insn from specified operands.
157 Construction involves substituting specified operands into a copy of the
158 template. Matching involves determining the values that serve as the
159 operands in the insn being matched. Both of these activities are
160 controlled by special expression types that direct matching and
161 substitution of the operands.
164 @findex match_operand
165 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
166 This expression is a placeholder for operand number @var{n} of
167 the insn. When constructing an insn, operand number @var{n}
168 will be substituted at this point. When matching an insn, whatever
169 appears at this position in the insn will be taken as operand
170 number @var{n}; but it must satisfy @var{predicate} or this instruction
171 pattern will not match at all.
173 Operand numbers must be chosen consecutively counting from zero in
174 each instruction pattern. There may be only one @code{match_operand}
175 expression in the pattern for each operand number. Usually operands
176 are numbered in the order of appearance in @code{match_operand}
177 expressions. In the case of a @code{define_expand}, any operand numbers
178 used only in @code{match_dup} expressions have higher values than all
179 other operand numbers.
181 @var{predicate} is a string that is the name of a C function that accepts two
182 arguments, an expression and a machine mode. During matching, the
183 function will be called with the putative operand as the expression and
184 @var{m} as the mode argument (if @var{m} is not specified,
185 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
186 any mode). If it returns zero, this instruction pattern fails to match.
187 @var{predicate} may be an empty string; then it means no test is to be done
188 on the operand, so anything which occurs in this position is valid.
190 Most of the time, @var{predicate} will reject modes other than @var{m}---but
191 not always. For example, the predicate @code{address_operand} uses
192 @var{m} as the mode of memory ref that the address should be valid for.
193 Many predicates accept @code{const_int} nodes even though their mode is
196 @var{constraint} controls reloading and the choice of the best register
197 class to use for a value, as explained later (@pxref{Constraints}).
199 People are often unclear on the difference between the constraint and the
200 predicate. The predicate helps decide whether a given insn matches the
201 pattern. The constraint plays no role in this decision; instead, it
202 controls various decisions in the case of an insn which does match.
204 @findex general_operand
205 On CISC machines, the most common @var{predicate} is
206 @code{"general_operand"}. This function checks that the putative
207 operand is either a constant, a register or a memory reference, and that
208 it is valid for mode @var{m}.
210 @findex register_operand
211 For an operand that must be a register, @var{predicate} should be
212 @code{"register_operand"}. Using @code{"general_operand"} would be
213 valid, since the reload pass would copy any non-register operands
214 through registers, but this would make GNU CC do extra work, it would
215 prevent invariant operands (such as constant) from being removed from
216 loops, and it would prevent the register allocator from doing the best
217 possible job. On RISC machines, it is usually most efficient to allow
218 @var{predicate} to accept only objects that the constraints allow.
220 @findex immediate_operand
221 For an operand that must be a constant, you must be sure to either use
222 @code{"immediate_operand"} for @var{predicate}, or make the instruction
223 pattern's extra condition require a constant, or both. You cannot
224 expect the constraints to do this work! If the constraints allow only
225 constants, but the predicate allows something else, the compiler will
226 crash when that case arises.
228 @findex match_scratch
229 @item (match_scratch:@var{m} @var{n} @var{constraint})
230 This expression is also a placeholder for operand number @var{n}
231 and indicates that operand must be a @code{scratch} or @code{reg}
234 When matching patterns, this is equivalent to
237 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
240 but, when generating RTL, it produces a (@code{scratch}:@var{m})
243 If the last few expressions in a @code{parallel} are @code{clobber}
244 expressions whose operands are either a hard register or
245 @code{match_scratch}, the combiner can add or delete them when
246 necessary. @xref{Side Effects}.
249 @item (match_dup @var{n})
250 This expression is also a placeholder for operand number @var{n}.
251 It is used when the operand needs to appear more than once in the
254 In construction, @code{match_dup} acts just like @code{match_operand}:
255 the operand is substituted into the insn being constructed. But in
256 matching, @code{match_dup} behaves differently. It assumes that operand
257 number @var{n} has already been determined by a @code{match_operand}
258 appearing earlier in the recognition template, and it matches only an
259 identical-looking expression.
261 @findex match_operator
262 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
263 This pattern is a kind of placeholder for a variable RTL expression
266 When constructing an insn, it stands for an RTL expression whose
267 expression code is taken from that of operand @var{n}, and whose
268 operands are constructed from the patterns @var{operands}.
270 When matching an expression, it matches an expression if the function
271 @var{predicate} returns nonzero on that expression @emph{and} the
272 patterns @var{operands} match the operands of the expression.
274 Suppose that the function @code{commutative_operator} is defined as
275 follows, to match any expression whose operator is one of the
276 commutative arithmetic operators of RTL and whose mode is @var{mode}:
280 commutative_operator (x, mode)
282 enum machine_mode mode;
284 enum rtx_code code = GET_CODE (x);
285 if (GET_MODE (x) != mode)
287 return (GET_RTX_CLASS (code) == 'c'
288 || code == EQ || code == NE);
292 Then the following pattern will match any RTL expression consisting
293 of a commutative operator applied to two general operands:
296 (match_operator:SI 3 "commutative_operator"
297 [(match_operand:SI 1 "general_operand" "g")
298 (match_operand:SI 2 "general_operand" "g")])
301 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
302 because the expressions to be matched all contain two operands.
304 When this pattern does match, the two operands of the commutative
305 operator are recorded as operands 1 and 2 of the insn. (This is done
306 by the two instances of @code{match_operand}.) Operand 3 of the insn
307 will be the entire commutative expression: use @code{GET_CODE
308 (operands[3])} to see which commutative operator was used.
310 The machine mode @var{m} of @code{match_operator} works like that of
311 @code{match_operand}: it is passed as the second argument to the
312 predicate function, and that function is solely responsible for
313 deciding whether the expression to be matched ``has'' that mode.
315 When constructing an insn, argument 3 of the gen-function will specify
316 the operation (i.e. the expression code) for the expression to be
317 made. It should be an RTL expression, whose expression code is copied
318 into a new expression whose operands are arguments 1 and 2 of the
319 gen-function. The subexpressions of argument 3 are not used;
320 only its expression code matters.
322 When @code{match_operator} is used in a pattern for matching an insn,
323 it usually best if the operand number of the @code{match_operator}
324 is higher than that of the actual operands of the insn. This improves
325 register allocation because the register allocator often looks at
326 operands 1 and 2 of insns to see if it can do register tying.
328 There is no way to specify constraints in @code{match_operator}. The
329 operand of the insn which corresponds to the @code{match_operator}
330 never has any constraints because it is never reloaded as a whole.
331 However, if parts of its @var{operands} are matched by
332 @code{match_operand} patterns, those parts may have constraints of
336 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
337 Like @code{match_dup}, except that it applies to operators instead of
338 operands. When constructing an insn, operand number @var{n} will be
339 substituted at this point. But in matching, @code{match_op_dup} behaves
340 differently. It assumes that operand number @var{n} has already been
341 determined by a @code{match_operator} appearing earlier in the
342 recognition template, and it matches only an identical-looking
345 @findex match_parallel
346 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
347 This pattern is a placeholder for an insn that consists of a
348 @code{parallel} expression with a variable number of elements. This
349 expression should only appear at the top level of an insn pattern.
351 When constructing an insn, operand number @var{n} will be substituted at
352 this point. When matching an insn, it matches if the body of the insn
353 is a @code{parallel} expression with at least as many elements as the
354 vector of @var{subpat} expressions in the @code{match_parallel}, if each
355 @var{subpat} matches the corresponding element of the @code{parallel},
356 @emph{and} the function @var{predicate} returns nonzero on the
357 @code{parallel} that is the body of the insn. It is the responsibility
358 of the predicate to validate elements of the @code{parallel} beyond
359 those listed in the @code{match_parallel}.@refill
361 A typical use of @code{match_parallel} is to match load and store
362 multiple expressions, which can contain a variable number of elements
363 in a @code{parallel}. For example,
364 @c the following is *still* going over. need to change the code.
365 @c also need to work on grouping of this example. --mew 1feb93
369 [(match_parallel 0 "load_multiple_operation"
370 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
371 (match_operand:SI 2 "memory_operand" "m"))
373 (clobber (reg:SI 179))])]
378 This example comes from @file{a29k.md}. The function
379 @code{load_multiple_operations} is defined in @file{a29k.c} and checks
380 that subsequent elements in the @code{parallel} are the same as the
381 @code{set} in the pattern, except that they are referencing subsequent
382 registers and memory locations.
384 An insn that matches this pattern might look like:
388 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
390 (clobber (reg:SI 179))
392 (mem:SI (plus:SI (reg:SI 100)
395 (mem:SI (plus:SI (reg:SI 100)
399 @findex match_par_dup
400 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
401 Like @code{match_op_dup}, but for @code{match_parallel} instead of
402 @code{match_operator}.
405 @item (match_insn @var{predicate})
406 Match a complete insn. Unlike the other @code{match_*} recognizers,
407 @code{match_insn} does not take an operand number.
409 The machine mode @var{m} of @code{match_insn} works like that of
410 @code{match_operand}: it is passed as the second argument to the
411 predicate function, and that function is solely responsible for
412 deciding whether the expression to be matched ``has'' that mode.
415 @item (match_insn2 @var{n} @var{predicate})
416 Match a complete insn.
418 The machine mode @var{m} of @code{match_insn2} works like that of
419 @code{match_operand}: it is passed as the second argument to the
420 predicate function, and that function is solely responsible for
421 deciding whether the expression to be matched ``has'' that mode.
425 @node Output Template
426 @section Output Templates and Operand Substitution
427 @cindex output templates
428 @cindex operand substitution
430 @cindex @samp{%} in template
432 The @dfn{output template} is a string which specifies how to output the
433 assembler code for an instruction pattern. Most of the template is a
434 fixed string which is output literally. The character @samp{%} is used
435 to specify where to substitute an operand; it can also be used to
436 identify places where different variants of the assembler require
439 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
440 operand @var{n} at that point in the string.
442 @samp{%} followed by a letter and a digit says to output an operand in an
443 alternate fashion. Four letters have standard, built-in meanings described
444 below. The machine description macro @code{PRINT_OPERAND} can define
445 additional letters with nonstandard meanings.
447 @samp{%c@var{digit}} can be used to substitute an operand that is a
448 constant value without the syntax that normally indicates an immediate
451 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
452 the constant is negated before printing.
454 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
455 memory reference, with the actual operand treated as the address. This may
456 be useful when outputting a ``load address'' instruction, because often the
457 assembler syntax for such an instruction requires you to write the operand
458 as if it were a memory reference.
460 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
463 @samp{%=} outputs a number which is unique to each instruction in the
464 entire compilation. This is useful for making local labels to be
465 referred to more than once in a single template that generates multiple
466 assembler instructions.
468 @samp{%} followed by a punctuation character specifies a substitution that
469 does not use an operand. Only one case is standard: @samp{%%} outputs a
470 @samp{%} into the assembler code. Other nonstandard cases can be
471 defined in the @code{PRINT_OPERAND} macro. You must also define
472 which punctuation characters are valid with the
473 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
477 The template may generate multiple assembler instructions. Write the text
478 for the instructions, with @samp{\;} between them.
480 @cindex matching operands
481 When the RTL contains two operands which are required by constraint to match
482 each other, the output template must refer only to the lower-numbered operand.
483 Matching operands are not always identical, and the rest of the compiler
484 arranges to put the proper RTL expression for printing into the lower-numbered
487 One use of nonstandard letters or punctuation following @samp{%} is to
488 distinguish between different assembler languages for the same machine; for
489 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
490 requires periods in most opcode names, while MIT syntax does not. For
491 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
492 syntax. The same file of patterns is used for both kinds of output syntax,
493 but the character sequence @samp{%.} is used in each place where Motorola
494 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
495 defines the sequence to output a period; the macro for MIT syntax defines
498 @cindex @code{#} in template
499 As a special case, a template consisting of the single character @code{#}
500 instructs the compiler to first split the insn, and then output the
501 resulting instructions separately. This helps eliminate redundancy in the
502 output templates. If you have a @code{define_insn} that needs to emit
503 multiple assembler instructions, and there is an matching @code{define_split}
504 already defined, then you can simply use @code{#} as the output template
505 instead of writing an output template that emits the multiple assembler
508 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
509 of the form @samp{@{option0|option1|option2@}} in the templates. These
510 describe multiple variants of assembler language syntax.
511 @xref{Instruction Output}.
513 @node Output Statement
514 @section C Statements for Assembler Output
515 @cindex output statements
516 @cindex C statements for assembler output
517 @cindex generating assembler output
519 Often a single fixed template string cannot produce correct and efficient
520 assembler code for all the cases that are recognized by a single
521 instruction pattern. For example, the opcodes may depend on the kinds of
522 operands; or some unfortunate combinations of operands may require extra
523 machine instructions.
525 If the output control string starts with a @samp{@@}, then it is actually
526 a series of templates, each on a separate line. (Blank lines and
527 leading spaces and tabs are ignored.) The templates correspond to the
528 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
529 if a target machine has a two-address add instruction @samp{addr} to add
530 into a register and another @samp{addm} to add a register to memory, you
531 might write this pattern:
534 (define_insn "addsi3"
535 [(set (match_operand:SI 0 "general_operand" "=r,m")
536 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
537 (match_operand:SI 2 "general_operand" "g,r")))]
544 @cindex @code{*} in template
545 @cindex asterisk in template
546 If the output control string starts with a @samp{*}, then it is not an
547 output template but rather a piece of C program that should compute a
548 template. It should execute a @code{return} statement to return the
549 template-string you want. Most such templates use C string literals, which
550 require doublequote characters to delimit them. To include these
551 doublequote characters in the string, prefix each one with @samp{\}.
553 The operands may be found in the array @code{operands}, whose C data type
556 It is very common to select different ways of generating assembler code
557 based on whether an immediate operand is within a certain range. Be
558 careful when doing this, because the result of @code{INTVAL} is an
559 integer on the host machine. If the host machine has more bits in an
560 @code{int} than the target machine has in the mode in which the constant
561 will be used, then some of the bits you get from @code{INTVAL} will be
562 superfluous. For proper results, you must carefully disregard the
563 values of those bits.
565 @findex output_asm_insn
566 It is possible to output an assembler instruction and then go on to output
567 or compute more of them, using the subroutine @code{output_asm_insn}. This
568 receives two arguments: a template-string and a vector of operands. The
569 vector may be @code{operands}, or it may be another array of @code{rtx}
570 that you declare locally and initialize yourself.
572 @findex which_alternative
573 When an insn pattern has multiple alternatives in its constraints, often
574 the appearance of the assembler code is determined mostly by which alternative
575 was matched. When this is so, the C code can test the variable
576 @code{which_alternative}, which is the ordinal number of the alternative
577 that was actually satisfied (0 for the first, 1 for the second alternative,
580 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
581 for registers and @samp{clrmem} for memory locations. Here is how
582 a pattern could use @code{which_alternative} to choose between them:
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
590 return (which_alternative == 0
591 ? \"clrreg %0\" : \"clrmem %0\");
595 The example above, where the assembler code to generate was
596 @emph{solely} determined by the alternative, could also have been specified
597 as follows, having the output control string start with a @samp{@@}:
602 [(set (match_operand:SI 0 "general_operand" "=r,m")
612 @c Most of this node appears by itself (in a different place) even
613 @c when the INTERNALS flag is clear. Passages that require the full
614 @c manual's context are conditionalized to appear only in the full manual.
617 @section Operand Constraints
618 @cindex operand constraints
621 Each @code{match_operand} in an instruction pattern can specify a
622 constraint for the type of operands allowed.
626 @section Constraints for @code{asm} Operands
627 @cindex operand constraints, @code{asm}
628 @cindex constraints, @code{asm}
629 @cindex @code{asm} constraints
631 Here are specific details on what constraint letters you can use with
634 Constraints can say whether
635 an operand may be in a register, and which kinds of register; whether the
636 operand can be a memory reference, and which kinds of address; whether the
637 operand may be an immediate constant, and which possible values it may
638 have. Constraints can also require two operands to match.
642 * Simple Constraints:: Basic use of constraints.
643 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
644 * Class Preferences:: Constraints guide which hard register to put things in.
645 * Modifiers:: More precise control over effects of constraints.
646 * Machine Constraints:: Existing constraints for some particular machines.
652 * Simple Constraints:: Basic use of constraints.
653 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
654 * Modifiers:: More precise control over effects of constraints.
655 * Machine Constraints:: Special constraints for some particular machines.
659 @node Simple Constraints
660 @subsection Simple Constraints
661 @cindex simple constraints
663 The simplest kind of constraint is a string full of letters, each of
664 which describes one kind of operand that is permitted. Here are
665 the letters that are allowed:
669 Whitespace characters are ignored and can be inserted at any position
670 except the first. This enables each alternative for different operands to
671 be visually aligned in the machine description even if they have different
672 number of constraints and modifiers.
674 @cindex @samp{m} in constraint
675 @cindex memory references in constraints
677 A memory operand is allowed, with any kind of address that the machine
680 @cindex offsettable address
681 @cindex @samp{o} in constraint
683 A memory operand is allowed, but only if the address is
684 @dfn{offsettable}. This means that adding a small integer (actually,
685 the width in bytes of the operand, as determined by its machine mode)
686 may be added to the address and the result is also a valid memory
689 @cindex autoincrement/decrement addressing
690 For example, an address which is constant is offsettable; so is an
691 address that is the sum of a register and a constant (as long as a
692 slightly larger constant is also within the range of address-offsets
693 supported by the machine); but an autoincrement or autodecrement
694 address is not offsettable. More complicated indirect/indexed
695 addresses may or may not be offsettable depending on the other
696 addressing modes that the machine supports.
698 Note that in an output operand which can be matched by another
699 operand, the constraint letter @samp{o} is valid only when accompanied
700 by both @samp{<} (if the target machine has predecrement addressing)
701 and @samp{>} (if the target machine has preincrement addressing).
703 @cindex @samp{V} in constraint
705 A memory operand that is not offsettable. In other words, anything that
706 would fit the @samp{m} constraint but not the @samp{o} constraint.
708 @cindex @samp{<} in constraint
710 A memory operand with autodecrement addressing (either predecrement or
711 postdecrement) is allowed.
713 @cindex @samp{>} in constraint
715 A memory operand with autoincrement addressing (either preincrement or
716 postincrement) is allowed.
718 @cindex @samp{r} in constraint
719 @cindex registers in constraints
721 A register operand is allowed provided that it is in a general
724 @cindex @samp{d} in constraint
725 @item @samp{d}, @samp{a}, @samp{f}, @dots{}
726 Other letters can be defined in machine-dependent fashion to stand for
727 particular classes of registers. @samp{d}, @samp{a} and @samp{f} are
728 defined on the 68000/68020 to stand for data, address and floating
731 @cindex constants in constraints
732 @cindex @samp{i} in constraint
734 An immediate integer operand (one with constant value) is allowed.
735 This includes symbolic constants whose values will be known only at
738 @cindex @samp{n} in constraint
740 An immediate integer operand with a known numeric value is allowed.
741 Many systems cannot support assembly-time constants for operands less
742 than a word wide. Constraints for these operands should use @samp{n}
743 rather than @samp{i}.
745 @cindex @samp{I} in constraint
746 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
747 Other letters in the range @samp{I} through @samp{P} may be defined in
748 a machine-dependent fashion to permit immediate integer operands with
749 explicit integer values in specified ranges. For example, on the
750 68000, @samp{I} is defined to stand for the range of values 1 to 8.
751 This is the range permitted as a shift count in the shift
754 @cindex @samp{E} in constraint
756 An immediate floating operand (expression code @code{const_double}) is
757 allowed, but only if the target floating point format is the same as
758 that of the host machine (on which the compiler is running).
760 @cindex @samp{F} in constraint
762 An immediate floating operand (expression code @code{const_double}) is
765 @cindex @samp{G} in constraint
766 @cindex @samp{H} in constraint
767 @item @samp{G}, @samp{H}
768 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
769 permit immediate floating operands in particular ranges of values.
771 @cindex @samp{s} in constraint
773 An immediate integer operand whose value is not an explicit integer is
776 This might appear strange; if an insn allows a constant operand with a
777 value not known at compile time, it certainly must allow any known
778 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
779 better code to be generated.
781 For example, on the 68000 in a fullword instruction it is possible to
782 use an immediate operand; but if the immediate value is between -128
783 and 127, better code results from loading the value into a register and
784 using the register. This is because the load into the register can be
785 done with a @samp{moveq} instruction. We arrange for this to happen
786 by defining the letter @samp{K} to mean ``any integer outside the
787 range -128 to 127'', and then specifying @samp{Ks} in the operand
790 @cindex @samp{g} in constraint
792 Any register, memory or immediate integer operand is allowed, except for
793 registers that are not general registers.
795 @cindex @samp{X} in constraint
798 Any operand whatsoever is allowed, even if it does not satisfy
799 @code{general_operand}. This is normally used in the constraint of
800 a @code{match_scratch} when certain alternatives will not actually
801 require a scratch register.
804 Any operand whatsoever is allowed.
807 @cindex @samp{0} in constraint
808 @cindex digits in constraint
809 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
810 An operand that matches the specified operand number is allowed. If a
811 digit is used together with letters within the same alternative, the
812 digit should come last.
814 @cindex matching constraint
815 @cindex constraint, matching
816 This is called a @dfn{matching constraint} and what it really means is
817 that the assembler has only a single operand that fills two roles
819 considered separate in the RTL insn. For example, an add insn has two
820 input operands and one output operand in the RTL, but on most CISC
823 which @code{asm} distinguishes. For example, an add instruction uses
824 two input operands and an output operand, but on most CISC
826 machines an add instruction really has only two operands, one of them an
827 input-output operand:
833 Matching constraints are used in these circumstances.
834 More precisely, the two operands that match must include one input-only
835 operand and one output-only operand. Moreover, the digit must be a
836 smaller number than the number of the operand that uses it in the
840 For operands to match in a particular case usually means that they
841 are identical-looking RTL expressions. But in a few special cases
842 specific kinds of dissimilarity are allowed. For example, @code{*x}
843 as an input operand will match @code{*x++} as an output operand.
844 For proper results in such cases, the output template should always
845 use the output-operand's number when printing the operand.
848 @cindex load address instruction
849 @cindex push address instruction
850 @cindex address constraints
851 @cindex @samp{p} in constraint
853 An operand that is a valid memory address is allowed. This is
854 for ``load address'' and ``push address'' instructions.
856 @findex address_operand
857 @samp{p} in the constraint must be accompanied by @code{address_operand}
858 as the predicate in the @code{match_operand}. This predicate interprets
859 the mode specified in the @code{match_operand} as the mode of the memory
860 reference for which the address would be valid.
862 @cindex extensible constraints
863 @cindex @samp{Q}, in constraint
864 @item @samp{Q}, @samp{R}, @samp{S}, @dots{} @samp{U}
865 Letters in the range @samp{Q} through @samp{U} may be defined in a
866 machine-dependent fashion to stand for arbitrary operand types.
868 The machine description macro @code{EXTRA_CONSTRAINT} is passed the
869 operand as its first argument and the constraint letter as its
872 A typical use for this would be to distinguish certain types of
873 memory references that affect other insn operands.
875 Do not define these constraint letters to accept register references
876 (@code{reg}); the reload pass does not expect this and would not handle
882 In order to have valid assembler code, each operand must satisfy
883 its constraint. But a failure to do so does not prevent the pattern
884 from applying to an insn. Instead, it directs the compiler to modify
885 the code so that the constraint will be satisfied. Usually this is
886 done by copying an operand into a register.
888 Contrast, therefore, the two instruction patterns that follow:
892 [(set (match_operand:SI 0 "general_operand" "=r")
893 (plus:SI (match_dup 0)
894 (match_operand:SI 1 "general_operand" "r")))]
900 which has two operands, one of which must appear in two places, and
904 [(set (match_operand:SI 0 "general_operand" "=r")
905 (plus:SI (match_operand:SI 1 "general_operand" "0")
906 (match_operand:SI 2 "general_operand" "r")))]
912 which has three operands, two of which are required by a constraint to be
913 identical. If we are considering an insn of the form
916 (insn @var{n} @var{prev} @var{next}
918 (plus:SI (reg:SI 6) (reg:SI 109)))
923 the first pattern would not apply at all, because this insn does not
924 contain two identical subexpressions in the right place. The pattern would
925 say, ``That does not look like an add instruction; try other patterns.''
926 The second pattern would say, ``Yes, that's an add instruction, but there
927 is something wrong with it.'' It would direct the reload pass of the
928 compiler to generate additional insns to make the constraint true. The
929 results might look like this:
932 (insn @var{n2} @var{prev} @var{n}
933 (set (reg:SI 3) (reg:SI 6))
936 (insn @var{n} @var{n2} @var{next}
938 (plus:SI (reg:SI 3) (reg:SI 109)))
942 It is up to you to make sure that each operand, in each pattern, has
943 constraints that can handle any RTL expression that could be present for
944 that operand. (When multiple alternatives are in use, each pattern must,
945 for each possible combination of operand expressions, have at least one
946 alternative which can handle that combination of operands.) The
947 constraints don't need to @emph{allow} any possible operand---when this is
948 the case, they do not constrain---but they must at least point the way to
949 reloading any possible operand so that it will fit.
953 If the constraint accepts whatever operands the predicate permits,
954 there is no problem: reloading is never necessary for this operand.
956 For example, an operand whose constraints permit everything except
957 registers is safe provided its predicate rejects registers.
959 An operand whose predicate accepts only constant values is safe
960 provided its constraints include the letter @samp{i}. If any possible
961 constant value is accepted, then nothing less than @samp{i} will do;
962 if the predicate is more selective, then the constraints may also be
966 Any operand expression can be reloaded by copying it into a register.
967 So if an operand's constraints allow some kind of register, it is
968 certain to be safe. It need not permit all classes of registers; the
969 compiler knows how to copy a register into another register of the
970 proper class in order to make an instruction valid.
972 @cindex nonoffsettable memory reference
973 @cindex memory reference, nonoffsettable
975 A nonoffsettable memory reference can be reloaded by copying the
976 address into a register. So if the constraint uses the letter
977 @samp{o}, all memory references are taken care of.
980 A constant operand can be reloaded by allocating space in memory to
981 hold it as preinitialized data. Then the memory reference can be used
982 in place of the constant. So if the constraint uses the letters
983 @samp{o} or @samp{m}, constant operands are not a problem.
986 If the constraint permits a constant and a pseudo register used in an insn
987 was not allocated to a hard register and is equivalent to a constant,
988 the register will be replaced with the constant. If the predicate does
989 not permit a constant and the insn is re-recognized for some reason, the
990 compiler will crash. Thus the predicate must always recognize any
991 objects allowed by the constraint.
994 If the operand's predicate can recognize registers, but the constraint does
995 not permit them, it can make the compiler crash. When this operand happens
996 to be a register, the reload pass will be stymied, because it does not know
997 how to copy a register temporarily into memory.
999 If the predicate accepts a unary operator, the constraint applies to the
1000 operand. For example, the MIPS processor at ISA level 3 supports an
1001 instruction which adds two registers in @code{SImode} to produce a
1002 @code{DImode} result, but only if the registers are correctly sign
1003 extended. This predicate for the input operands accepts a
1004 @code{sign_extend} of an @code{SImode} register. Write the constraint
1005 to indicate the type of register that is required for the operand of the
1009 @node Multi-Alternative
1010 @subsection Multiple Alternative Constraints
1011 @cindex multiple alternative constraints
1013 Sometimes a single instruction has multiple alternative sets of possible
1014 operands. For example, on the 68000, a logical-or instruction can combine
1015 register or an immediate value into memory, or it can combine any kind of
1016 operand into a register; but it cannot combine one memory location into
1019 These constraints are represented as multiple alternatives. An alternative
1020 can be described by a series of letters for each operand. The overall
1021 constraint for an operand is made from the letters for this operand
1022 from the first alternative, a comma, the letters for this operand from
1023 the second alternative, a comma, and so on until the last alternative.
1025 Here is how it is done for fullword logical-or on the 68000:
1028 (define_insn "iorsi3"
1029 [(set (match_operand:SI 0 "general_operand" "=m,d")
1030 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1031 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1035 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1036 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1037 2. The second alternative has @samp{d} (data register) for operand 0,
1038 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1039 @samp{%} in the constraints apply to all the alternatives; their
1040 meaning is explained in the next section (@pxref{Class Preferences}).
1043 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1044 If all the operands fit any one alternative, the instruction is valid.
1045 Otherwise, for each alternative, the compiler counts how many instructions
1046 must be added to copy the operands so that that alternative applies.
1047 The alternative requiring the least copying is chosen. If two alternatives
1048 need the same amount of copying, the one that comes first is chosen.
1049 These choices can be altered with the @samp{?} and @samp{!} characters:
1052 @cindex @samp{?} in constraint
1053 @cindex question mark
1055 Disparage slightly the alternative that the @samp{?} appears in,
1056 as a choice when no alternative applies exactly. The compiler regards
1057 this alternative as one unit more costly for each @samp{?} that appears
1060 @cindex @samp{!} in constraint
1061 @cindex exclamation point
1063 Disparage severely the alternative that the @samp{!} appears in.
1064 This alternative can still be used if it fits without reloading,
1065 but if reloading is needed, some other alternative will be used.
1069 When an insn pattern has multiple alternatives in its constraints, often
1070 the appearance of the assembler code is determined mostly by which
1071 alternative was matched. When this is so, the C code for writing the
1072 assembler code can use the variable @code{which_alternative}, which is
1073 the ordinal number of the alternative that was actually satisfied (0 for
1074 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1078 @node Class Preferences
1079 @subsection Register Class Preferences
1080 @cindex class preference constraints
1081 @cindex register class preference constraints
1083 @cindex voting between constraint alternatives
1084 The operand constraints have another function: they enable the compiler
1085 to decide which kind of hardware register a pseudo register is best
1086 allocated to. The compiler examines the constraints that apply to the
1087 insns that use the pseudo register, looking for the machine-dependent
1088 letters such as @samp{d} and @samp{a} that specify classes of registers.
1089 The pseudo register is put in whichever class gets the most ``votes''.
1090 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1091 favor of a general register. The machine description says which registers
1092 are considered general.
1094 Of course, on some machines all registers are equivalent, and no register
1095 classes are defined. Then none of this complexity is relevant.
1099 @subsection Constraint Modifier Characters
1100 @cindex modifiers in constraints
1101 @cindex constraint modifier characters
1103 @c prevent bad page break with this line
1104 Here are constraint modifier characters.
1107 @cindex @samp{=} in constraint
1109 Means that this operand is write-only for this instruction: the previous
1110 value is discarded and replaced by output data.
1112 @cindex @samp{+} in constraint
1114 Means that this operand is both read and written by the instruction.
1116 When the compiler fixes up the operands to satisfy the constraints,
1117 it needs to know which operands are inputs to the instruction and
1118 which are outputs from it. @samp{=} identifies an output; @samp{+}
1119 identifies an operand that is both input and output; all other operands
1120 are assumed to be input only.
1122 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1123 first character of the constraint string.
1125 @cindex @samp{&} in constraint
1126 @cindex earlyclobber operand
1128 Means (in a particular alternative) that this operand is an
1129 @dfn{earlyclobber} operand, which is modified before the instruction is
1130 finished using the input operands. Therefore, this operand may not lie
1131 in a register that is used as an input operand or as part of any memory
1134 @samp{&} applies only to the alternative in which it is written. In
1135 constraints with multiple alternatives, sometimes one alternative
1136 requires @samp{&} while others do not. See, for example, the
1137 @samp{movdf} insn of the 68000.
1139 An input operand can be tied to an earlyclobber operand if its only
1140 use as an input occurs before the early result is written. Adding
1141 alternatives of this form often allows GCC to produce better code
1142 when only some of the inputs can be affected by the earlyclobber.
1143 See, for example, the @samp{mulsi3} insn of the ARM.
1145 @samp{&} does not obviate the need to write @samp{=}.
1147 @cindex @samp{%} in constraint
1149 Declares the instruction to be commutative for this operand and the
1150 following operand. This means that the compiler may interchange the
1151 two operands if that is the cheapest way to make all operands fit the
1154 This is often used in patterns for addition instructions
1155 that really have only two operands: the result must go in one of the
1156 arguments. Here for example, is how the 68000 halfword-add
1157 instruction is defined:
1160 (define_insn "addhi3"
1161 [(set (match_operand:HI 0 "general_operand" "=m,r")
1162 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1163 (match_operand:HI 2 "general_operand" "di,g")))]
1168 @cindex @samp{#} in constraint
1170 Says that all following characters, up to the next comma, are to be
1171 ignored as a constraint. They are significant only for choosing
1172 register preferences.
1175 @cindex @samp{*} in constraint
1177 Says that the following character should be ignored when choosing
1178 register preferences. @samp{*} has no effect on the meaning of the
1179 constraint as a constraint, and no effect on reloading.
1181 Here is an example: the 68000 has an instruction to sign-extend a
1182 halfword in a data register, and can also sign-extend a value by
1183 copying it into an address register. While either kind of register is
1184 acceptable, the constraints on an address-register destination are
1185 less strict, so it is best if register allocation makes an address
1186 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1187 constraint letter (for data register) is ignored when computing
1188 register preferences.
1191 (define_insn "extendhisi2"
1192 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1194 (match_operand:HI 1 "general_operand" "0,g")))]
1200 @node Machine Constraints
1201 @subsection Constraints for Particular Machines
1202 @cindex machine specific constraints
1203 @cindex constraints, machine specific
1205 Whenever possible, you should use the general-purpose constraint letters
1206 in @code{asm} arguments, since they will convey meaning more readily to
1207 people reading your code. Failing that, use the constraint letters
1208 that usually have very similar meanings across architectures. The most
1209 commonly used constraints are @samp{m} and @samp{r} (for memory and
1210 general-purpose registers respectively; @pxref{Simple Constraints}), and
1211 @samp{I}, usually the letter indicating the most common
1212 immediate-constant format.
1214 For each machine architecture, the @file{config/@var{machine}.h} file
1215 defines additional constraints. These constraints are used by the
1216 compiler itself for instruction generation, as well as for @code{asm}
1217 statements; therefore, some of the constraints are not particularly
1218 interesting for @code{asm}. The constraints are defined through these
1222 @item REG_CLASS_FROM_LETTER
1223 Register class constraints (usually lower case).
1225 @item CONST_OK_FOR_LETTER_P
1226 Immediate constant constraints, for non-floating point constants of
1227 word size or smaller precision (usually upper case).
1229 @item CONST_DOUBLE_OK_FOR_LETTER_P
1230 Immediate constant constraints, for all floating point constants and for
1231 constants of greater than word size precision (usually upper case).
1233 @item EXTRA_CONSTRAINT
1234 Special cases of registers or memory. This macro is not required, and
1235 is only defined for some machines.
1238 Inspecting these macro definitions in the compiler source for your
1239 machine is the best way to be certain you have the right constraints.
1240 However, here is a summary of the machine-dependent constraints
1241 available on some particular machines.
1244 @item ARM family---@file{arm.h}
1247 Floating-point register
1250 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1254 Floating-point constant that would satisfy the constraint @samp{F} if it
1258 Integer that is valid as an immediate operand in a data processing
1259 instruction. That is, an integer in the range 0 to 255 rotated by a
1263 Integer in the range -4095 to 4095
1266 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1269 Integer that satisfies constraint @samp{I} when negated (twos complement)
1272 Integer in the range 0 to 32
1275 A memory reference where the exact address is in a single register
1276 (`@samp{m}' is preferable for @code{asm} statements)
1279 An item in the constant pool
1282 A symbol in the text segment of the current file
1285 @item AMD 29000 family---@file{a29k.h}
1291 Byte Pointer (@samp{BP}) register
1297 Special purpose register
1300 First accumulator register
1303 Other accumulator register
1306 Floating point register
1309 Constant greater than 0, less than 0x100
1312 Constant greater than 0, less than 0x10000
1315 Constant whose high 24 bits are on (1)
1318 16 bit constant whose high 8 bits are on (1)
1321 32 bit constant whose high 16 bits are on (1)
1324 32 bit negative constant that fits in 8 bits
1327 The constant 0x80000000 or, on the 29050, any 32 bit constant
1328 whose low 16 bits are 0.
1331 16 bit negative constant that fits in 8 bits
1335 A floating point constant (in @code{asm} statements, use the machine
1336 independent @samp{E} or @samp{F} instead)
1339 @item IBM RS6000---@file{rs6000.h}
1342 Address base register
1345 Floating point register
1348 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1357 @samp{LINK} register
1360 @samp{CR} register (condition register) number 0
1363 @samp{CR} register (condition register)
1366 @samp{FPMEM} stack memory for FPR-GPR transfers
1369 Signed 16 bit constant
1372 Unsigned 16 bit constant shifted left 16 bits (use @samp{L} instead for
1373 @code{SImode} constants)
1376 Unsigned 16 bit constant
1379 Signed 16 bit constant shifted left 16 bits
1382 Constant larger than 31
1391 Constant whose negation is a signed 16 bit constant
1394 Floating point constant that can be loaded into a register with one
1395 instruction per word
1398 Memory operand that is an offset from a register (@samp{m} is preferable
1399 for @code{asm} statements)
1405 Constant suitable as a 64-bit mask operand
1408 Constant suitable as a 32-bit mask operand
1411 System V Release 4 small data area reference
1414 @item Intel 386---@file{i386.h}
1417 @samp{a}, @code{b}, @code{c}, or @code{d} register
1420 @samp{a}, or @code{d} register (for 64-bit ints)
1423 Floating point register
1426 First (top of stack) floating point register
1429 Second floating point register
1450 Constant in range 0 to 31 (for 32 bit shifts)
1453 Constant in range 0 to 63 (for 64 bit shifts)
1462 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1465 Constant in range 0 to 255 (for @code{out} instruction)
1468 Standard 80387 floating point constant
1471 @item Intel 960---@file{i960.h}
1474 Floating point register (@code{fp0} to @code{fp3})
1477 Local register (@code{r0} to @code{r15})
1480 Global register (@code{g0} to @code{g15})
1483 Any local or global register
1486 Integers from 0 to 31
1492 Integers from -31 to 0
1501 @item MIPS---@file{mips.h}
1504 General-purpose integer register
1507 Floating-point register (if available)
1516 @samp{Hi} or @samp{Lo} register
1519 General-purpose integer register
1522 Floating-point status register
1525 Signed 16 bit constant (for arithmetic instructions)
1531 Zero-extended 16-bit constant (for logic instructions)
1534 Constant with low 16 bits zero (can be loaded with @code{lui})
1537 32 bit constant which requires two instructions to load (a constant
1538 which is not @samp{I}, @samp{K}, or @samp{L})
1541 Negative 16 bit constant
1547 Positive 16 bit constant
1553 Memory reference that can be loaded with more than one instruction
1554 (@samp{m} is preferable for @code{asm} statements)
1557 Memory reference that can be loaded with one instruction
1558 (@samp{m} is preferable for @code{asm} statements)
1561 Memory reference in external OSF/rose PIC format
1562 (@samp{m} is preferable for @code{asm} statements)
1565 @item Motorola 680x0---@file{m68k.h}
1574 68881 floating-point register, if available
1577 Sun FPA (floating-point) register, if available
1580 First 16 Sun FPA registers, if available
1583 Integer in the range 1 to 8
1586 16 bit signed number
1589 Signed number whose magnitude is greater than 0x80
1592 Integer in the range -8 to -1
1595 Signed number whose magnitude is greater than 0x100
1598 Floating point constant that is not a 68881 constant
1601 Floating point constant that can be used by Sun FPA
1605 @item SPARC---@file{sparc.h}
1608 Floating-point register that can hold 32 or 64 bit values.
1611 Floating-point register that can hold 64 or 128 bit values.
1614 Signed 13 bit constant
1620 32 bit constant with the low 12 bits clear (a constant that can be
1621 loaded with the @code{sethi} instruction)
1627 Signed 13 bit constant, sign-extended to 32 or 64 bits
1630 Floating-point constant whose integral representation can
1631 be moved into an integer register using a single sethi
1635 Floating-point constant whose integral representation can
1636 be moved into an integer register using a single mov
1640 Floating-point constant whose integral representation can
1641 be moved into an integer register using a high/lo_sum
1642 instruction sequence
1645 Memory address aligned to an 8-byte boundary
1652 @item TMS320C3x/C4x---@file{c4x.h}
1655 Auxiliary (address) register (ar0-ar7)
1658 Stack pointer register (sp)
1661 Standard (32 bit) precision integer register
1664 Extended (40 bit) precision register (r0-r11)
1667 Block count register (bk)
1670 Extended (40 bit) precision low register (r0-r7)
1673 Extended (40 bit) precision register (r0-r1)
1676 Extended (40 bit) precision register (r2-r3)
1679 Repeat count register (rc)
1682 Index register (ir0-ir1)
1685 Status (condition code) register (st)
1688 Data page register (dp)
1694 Immediate 16 bit floating-point constant
1697 Signed 16 bit constant
1700 Signed 8 bit constant
1703 Signed 5 bit constant
1706 Unsigned 16 bit constant
1709 Unsigned 8 bit constant
1712 Ones complement of unsigned 16 bit constant
1715 High 16 bit constant (32 bit constant with 16 LSBs zero)
1718 Indirect memory reference with signed 8 bit or index register displacement
1721 Indirect memory reference with unsigned 5 bit displacement
1724 Indirect memory reference with 1 bit or index register displacement
1727 Direct memory reference
1736 @node Standard Names
1737 @section Standard Pattern Names For Generation
1738 @cindex standard pattern names
1739 @cindex pattern names
1740 @cindex names, pattern
1742 Here is a table of the instruction names that are meaningful in the RTL
1743 generation pass of the compiler. Giving one of these names to an
1744 instruction pattern tells the RTL generation pass that it can use the
1745 pattern to accomplish a certain task.
1748 @cindex @code{mov@var{m}} instruction pattern
1749 @item @samp{mov@var{m}}
1750 Here @var{m} stands for a two-letter machine mode name, in lower case.
1751 This instruction pattern moves data with that machine mode from operand
1752 1 to operand 0. For example, @samp{movsi} moves full-word data.
1754 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1755 own mode is wider than @var{m}, the effect of this instruction is
1756 to store the specified value in the part of the register that corresponds
1757 to mode @var{m}. The effect on the rest of the register is undefined.
1759 This class of patterns is special in several ways. First of all, each
1760 of these names @emph{must} be defined, because there is no other way
1761 to copy a datum from one place to another.
1763 Second, these patterns are not used solely in the RTL generation pass.
1764 Even the reload pass can generate move insns to copy values from stack
1765 slots into temporary registers. When it does so, one of the operands is
1766 a hard register and the other is an operand that can need to be reloaded
1770 Therefore, when given such a pair of operands, the pattern must generate
1771 RTL which needs no reloading and needs no temporary registers---no
1772 registers other than the operands. For example, if you support the
1773 pattern with a @code{define_expand}, then in such a case the
1774 @code{define_expand} mustn't call @code{force_reg} or any other such
1775 function which might generate new pseudo registers.
1777 This requirement exists even for subword modes on a RISC machine where
1778 fetching those modes from memory normally requires several insns and
1779 some temporary registers. Look in @file{spur.md} to see how the
1780 requirement can be satisfied.
1782 @findex change_address
1783 During reload a memory reference with an invalid address may be passed
1784 as an operand. Such an address will be replaced with a valid address
1785 later in the reload pass. In this case, nothing may be done with the
1786 address except to use it as it stands. If it is copied, it will not be
1787 replaced with a valid address. No attempt should be made to make such
1788 an address into a valid address and no routine (such as
1789 @code{change_address}) that will do so may be called. Note that
1790 @code{general_operand} will fail when applied to such an address.
1792 @findex reload_in_progress
1793 The global variable @code{reload_in_progress} (which must be explicitly
1794 declared if required) can be used to determine whether such special
1795 handling is required.
1797 The variety of operands that have reloads depends on the rest of the
1798 machine description, but typically on a RISC machine these can only be
1799 pseudo registers that did not get hard registers, while on other
1800 machines explicit memory references will get optional reloads.
1802 If a scratch register is required to move an object to or from memory,
1803 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
1805 If there are cases needing
1806 scratch registers after reload, you must define
1807 @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
1808 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1809 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1810 them. @xref{Register Classes}.
1812 @findex no_new_pseudos
1813 The global variable @code{no_new_pseudos} can be used to determine if it
1814 is unsafe to create new pseudo registers. If this variable is nonzero, then
1815 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
1817 The constraints on a @samp{mov@var{m}} must permit moving any hard
1818 register to any other hard register provided that
1819 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
1820 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
1822 It is obligatory to support floating point @samp{mov@var{m}}
1823 instructions into and out of any registers that can hold fixed point
1824 values, because unions and structures (which have modes @code{SImode} or
1825 @code{DImode}) can be in those registers and they may have floating
1828 There may also be a need to support fixed point @samp{mov@var{m}}
1829 instructions in and out of floating point registers. Unfortunately, I
1830 have forgotten why this was so, and I don't know whether it is still
1831 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
1832 floating point registers, then the constraints of the fixed point
1833 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
1834 reload into a floating point register.
1836 @cindex @code{reload_in} instruction pattern
1837 @cindex @code{reload_out} instruction pattern
1838 @item @samp{reload_in@var{m}}
1839 @itemx @samp{reload_out@var{m}}
1840 Like @samp{mov@var{m}}, but used when a scratch register is required to
1841 move between operand 0 and operand 1. Operand 2 describes the scratch
1842 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
1843 macro in @pxref{Register Classes}.
1845 @cindex @code{movstrict@var{m}} instruction pattern
1846 @item @samp{movstrict@var{m}}
1847 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
1848 with mode @var{m} of a register whose natural mode is wider,
1849 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
1850 any of the register except the part which belongs to mode @var{m}.
1852 @cindex @code{load_multiple} instruction pattern
1853 @item @samp{load_multiple}
1854 Load several consecutive memory locations into consecutive registers.
1855 Operand 0 is the first of the consecutive registers, operand 1
1856 is the first memory location, and operand 2 is a constant: the
1857 number of consecutive registers.
1859 Define this only if the target machine really has such an instruction;
1860 do not define this if the most efficient way of loading consecutive
1861 registers from memory is to do them one at a time.
1863 On some machines, there are restrictions as to which consecutive
1864 registers can be stored into memory, such as particular starting or
1865 ending register numbers or only a range of valid counts. For those
1866 machines, use a @code{define_expand} (@pxref{Expander Definitions})
1867 and make the pattern fail if the restrictions are not met.
1869 Write the generated insn as a @code{parallel} with elements being a
1870 @code{set} of one register from the appropriate memory location (you may
1871 also need @code{use} or @code{clobber} elements). Use a
1872 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
1873 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
1876 @cindex @samp{store_multiple} instruction pattern
1877 @item @samp{store_multiple}
1878 Similar to @samp{load_multiple}, but store several consecutive registers
1879 into consecutive memory locations. Operand 0 is the first of the
1880 consecutive memory locations, operand 1 is the first register, and
1881 operand 2 is a constant: the number of consecutive registers.
1883 @cindex @code{add@var{m}3} instruction pattern
1884 @item @samp{add@var{m}3}
1885 Add operand 2 and operand 1, storing the result in operand 0. All operands
1886 must have mode @var{m}. This can be used even on two-address machines, by
1887 means of constraints requiring operands 1 and 0 to be the same location.
1889 @cindex @code{sub@var{m}3} instruction pattern
1890 @cindex @code{mul@var{m}3} instruction pattern
1891 @cindex @code{div@var{m}3} instruction pattern
1892 @cindex @code{udiv@var{m}3} instruction pattern
1893 @cindex @code{mod@var{m}3} instruction pattern
1894 @cindex @code{umod@var{m}3} instruction pattern
1895 @cindex @code{smin@var{m}3} instruction pattern
1896 @cindex @code{smax@var{m}3} instruction pattern
1897 @cindex @code{umin@var{m}3} instruction pattern
1898 @cindex @code{umax@var{m}3} instruction pattern
1899 @cindex @code{and@var{m}3} instruction pattern
1900 @cindex @code{ior@var{m}3} instruction pattern
1901 @cindex @code{xor@var{m}3} instruction pattern
1902 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
1903 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
1904 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
1905 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
1906 Similar, for other arithmetic operations.
1908 @cindex @code{mulhisi3} instruction pattern
1909 @item @samp{mulhisi3}
1910 Multiply operands 1 and 2, which have mode @code{HImode}, and store
1911 a @code{SImode} product in operand 0.
1913 @cindex @code{mulqihi3} instruction pattern
1914 @cindex @code{mulsidi3} instruction pattern
1915 @item @samp{mulqihi3}, @samp{mulsidi3}
1916 Similar widening-multiplication instructions of other widths.
1918 @cindex @code{umulqihi3} instruction pattern
1919 @cindex @code{umulhisi3} instruction pattern
1920 @cindex @code{umulsidi3} instruction pattern
1921 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
1922 Similar widening-multiplication instructions that do unsigned
1925 @cindex @code{smul@var{m}3_highpart} instruction pattern
1926 @item @samp{smul@var{m}3_highpart}
1927 Perform a signed multiplication of operands 1 and 2, which have mode
1928 @var{m}, and store the most significant half of the product in operand 0.
1929 The least significant half of the product is discarded.
1931 @cindex @code{umul@var{m}3_highpart} instruction pattern
1932 @item @samp{umul@var{m}3_highpart}
1933 Similar, but the multiplication is unsigned.
1935 @cindex @code{divmod@var{m}4} instruction pattern
1936 @item @samp{divmod@var{m}4}
1937 Signed division that produces both a quotient and a remainder.
1938 Operand 1 is divided by operand 2 to produce a quotient stored
1939 in operand 0 and a remainder stored in operand 3.
1941 For machines with an instruction that produces both a quotient and a
1942 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
1943 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
1944 allows optimization in the relatively common case when both the quotient
1945 and remainder are computed.
1947 If an instruction that just produces a quotient or just a remainder
1948 exists and is more efficient than the instruction that produces both,
1949 write the output routine of @samp{divmod@var{m}4} to call
1950 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
1951 quotient or remainder and generate the appropriate instruction.
1953 @cindex @code{udivmod@var{m}4} instruction pattern
1954 @item @samp{udivmod@var{m}4}
1955 Similar, but does unsigned division.
1957 @cindex @code{ashl@var{m}3} instruction pattern
1958 @item @samp{ashl@var{m}3}
1959 Arithmetic-shift operand 1 left by a number of bits specified by operand
1960 2, and store the result in operand 0. Here @var{m} is the mode of
1961 operand 0 and operand 1; operand 2's mode is specified by the
1962 instruction pattern, and the compiler will convert the operand to that
1963 mode before generating the instruction.
1965 @cindex @code{ashr@var{m}3} instruction pattern
1966 @cindex @code{lshr@var{m}3} instruction pattern
1967 @cindex @code{rotl@var{m}3} instruction pattern
1968 @cindex @code{rotr@var{m}3} instruction pattern
1969 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
1970 Other shift and rotate instructions, analogous to the
1971 @code{ashl@var{m}3} instructions.
1973 @cindex @code{neg@var{m}2} instruction pattern
1974 @item @samp{neg@var{m}2}
1975 Negate operand 1 and store the result in operand 0.
1977 @cindex @code{abs@var{m}2} instruction pattern
1978 @item @samp{abs@var{m}2}
1979 Store the absolute value of operand 1 into operand 0.
1981 @cindex @code{sqrt@var{m}2} instruction pattern
1982 @item @samp{sqrt@var{m}2}
1983 Store the square root of operand 1 into operand 0.
1985 The @code{sqrt} built-in function of C always uses the mode which
1986 corresponds to the C data type @code{double}.
1988 @cindex @code{ffs@var{m}2} instruction pattern
1989 @item @samp{ffs@var{m}2}
1990 Store into operand 0 one plus the index of the least significant 1-bit
1991 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
1992 of operand 0; operand 1's mode is specified by the instruction
1993 pattern, and the compiler will convert the operand to that mode before
1994 generating the instruction.
1996 The @code{ffs} built-in function of C always uses the mode which
1997 corresponds to the C data type @code{int}.
1999 @cindex @code{one_cmpl@var{m}2} instruction pattern
2000 @item @samp{one_cmpl@var{m}2}
2001 Store the bitwise-complement of operand 1 into operand 0.
2003 @cindex @code{cmp@var{m}} instruction pattern
2004 @item @samp{cmp@var{m}}
2005 Compare operand 0 and operand 1, and set the condition codes.
2006 The RTL pattern should look like this:
2009 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2010 (match_operand:@var{m} 1 @dots{})))
2013 @cindex @code{tst@var{m}} instruction pattern
2014 @item @samp{tst@var{m}}
2015 Compare operand 0 against zero, and set the condition codes.
2016 The RTL pattern should look like this:
2019 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2022 @samp{tst@var{m}} patterns should not be defined for machines that do
2023 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2024 would no longer be clear which @code{set} operations were comparisons.
2025 The @samp{cmp@var{m}} patterns should be used instead.
2027 @cindex @code{movstr@var{m}} instruction pattern
2028 @item @samp{movstr@var{m}}
2029 Block move instruction. The addresses of the destination and source
2030 strings are the first two operands, and both are in mode @code{Pmode}.
2032 The number of bytes to move is the third operand, in mode @var{m}.
2033 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2034 generate better code knowing the range of valid lengths is smaller than
2035 those representable in a full word, you should provide a pattern with a
2036 mode corresponding to the range of values you can handle efficiently
2037 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2038 that appear negative) and also a pattern with @code{word_mode}.
2040 The fourth operand is the known shared alignment of the source and
2041 destination, in the form of a @code{const_int} rtx. Thus, if the
2042 compiler knows that both source and destination are word-aligned,
2043 it may provide the value 4 for this operand.
2045 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2046 beneficial if the patterns for smaller modes have fewer restrictions
2047 on their first, second and fourth operands. Note that the mode @var{m}
2048 in @code{movstr@var{m}} does not impose any restriction on the mode of
2049 individually moved data units in the block.
2051 These patterns need not give special consideration to the possibility
2052 that the source and destination strings might overlap.
2054 @cindex @code{clrstr@var{m}} instruction pattern
2055 @item @samp{clrstr@var{m}}
2056 Block clear instruction. The addresses of the destination string is the
2057 first operand, in mode @code{Pmode}. The number of bytes to clear is
2058 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2059 a discussion of the choice of mode.
2061 The third operand is the known alignment of the destination, in the form
2062 of a @code{const_int} rtx. Thus, if the compiler knows that the
2063 destination is word-aligned, it may provide the value 4 for this
2066 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2068 @cindex @code{cmpstr@var{m}} instruction pattern
2069 @item @samp{cmpstr@var{m}}
2070 Block compare instruction, with five operands. Operand 0 is the output;
2071 it has mode @var{m}. The remaining four operands are like the operands
2072 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2073 byte by byte in lexicographic order. The effect of the instruction is
2074 to store a value in operand 0 whose sign indicates the result of the
2077 @cindex @code{strlen@var{m}} instruction pattern
2078 @item @samp{strlen@var{m}}
2079 Compute the length of a string, with three operands.
2080 Operand 0 is the result (of mode @var{m}), operand 1 is
2081 a @code{mem} referring to the first character of the string,
2082 operand 2 is the character to search for (normally zero),
2083 and operand 3 is a constant describing the known alignment
2084 of the beginning of the string.
2086 @cindex @code{float@var{mn}2} instruction pattern
2087 @item @samp{float@var{m}@var{n}2}
2088 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2089 floating point mode @var{n} and store in operand 0 (which has mode
2092 @cindex @code{floatuns@var{mn}2} instruction pattern
2093 @item @samp{floatuns@var{m}@var{n}2}
2094 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2095 to floating point mode @var{n} and store in operand 0 (which has mode
2098 @cindex @code{fix@var{mn}2} instruction pattern
2099 @item @samp{fix@var{m}@var{n}2}
2100 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2101 point mode @var{n} as a signed number and store in operand 0 (which
2102 has mode @var{n}). This instruction's result is defined only when
2103 the value of operand 1 is an integer.
2105 @cindex @code{fixuns@var{mn}2} instruction pattern
2106 @item @samp{fixuns@var{m}@var{n}2}
2107 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2108 point mode @var{n} as an unsigned number and store in operand 0 (which
2109 has mode @var{n}). This instruction's result is defined only when the
2110 value of operand 1 is an integer.
2112 @cindex @code{ftrunc@var{m}2} instruction pattern
2113 @item @samp{ftrunc@var{m}2}
2114 Convert operand 1 (valid for floating point mode @var{m}) to an
2115 integer value, still represented in floating point mode @var{m}, and
2116 store it in operand 0 (valid for floating point mode @var{m}).
2118 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2119 @item @samp{fix_trunc@var{m}@var{n}2}
2120 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2121 of mode @var{m} by converting the value to an integer.
2123 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2124 @item @samp{fixuns_trunc@var{m}@var{n}2}
2125 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2126 value of mode @var{m} by converting the value to an integer.
2128 @cindex @code{trunc@var{mn}2} instruction pattern
2129 @item @samp{trunc@var{m}@var{n}2}
2130 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2131 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2132 point or both floating point.
2134 @cindex @code{extend@var{mn}2} instruction pattern
2135 @item @samp{extend@var{m}@var{n}2}
2136 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2137 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2138 point or both floating point.
2140 @cindex @code{zero_extend@var{mn}2} instruction pattern
2141 @item @samp{zero_extend@var{m}@var{n}2}
2142 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2143 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2146 @cindex @code{extv} instruction pattern
2148 Extract a bit field from operand 1 (a register or memory operand), where
2149 operand 2 specifies the width in bits and operand 3 the starting bit,
2150 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2151 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2152 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2153 be valid for @code{word_mode}.
2155 The RTL generation pass generates this instruction only with constants
2156 for operands 2 and 3.
2158 The bit-field value is sign-extended to a full word integer
2159 before it is stored in operand 0.
2161 @cindex @code{extzv} instruction pattern
2163 Like @samp{extv} except that the bit-field value is zero-extended.
2165 @cindex @code{insv} instruction pattern
2167 Store operand 3 (which must be valid for @code{word_mode}) into a bit
2168 field in operand 0, where operand 1 specifies the width in bits and
2169 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2170 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2171 Operands 1 and 2 must be valid for @code{word_mode}.
2173 The RTL generation pass generates this instruction only with constants
2174 for operands 1 and 2.
2176 @cindex @code{mov@var{mode}cc} instruction pattern
2177 @item @samp{mov@var{mode}cc}
2178 Conditionally move operand 2 or operand 3 into operand 0 according to the
2179 comparison in operand 1. If the comparison is true, operand 2 is moved
2180 into operand 0, otherwise operand 3 is moved.
2182 The mode of the operands being compared need not be the same as the operands
2183 being moved. Some machines, sparc64 for example, have instructions that
2184 conditionally move an integer value based on the floating point condition
2185 codes and vice versa.
2187 If the machine does not have conditional move instructions, do not
2188 define these patterns.
2190 @cindex @code{s@var{cond}} instruction pattern
2191 @item @samp{s@var{cond}}
2192 Store zero or nonzero in the operand according to the condition codes.
2193 Value stored is nonzero iff the condition @var{cond} is true.
2194 @var{cond} is the name of a comparison operation expression code, such
2195 as @code{eq}, @code{lt} or @code{leu}.
2197 You specify the mode that the operand must have when you write the
2198 @code{match_operand} expression. The compiler automatically sees
2199 which mode you have used and supplies an operand of that mode.
2201 The value stored for a true condition must have 1 as its low bit, or
2202 else must be negative. Otherwise the instruction is not suitable and
2203 you should omit it from the machine description. You describe to the
2204 compiler exactly which value is stored by defining the macro
2205 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2206 found that can be used for all the @samp{s@var{cond}} patterns, you
2207 should omit those operations from the machine description.
2209 These operations may fail, but should do so only in relatively
2210 uncommon cases; if they would fail for common cases involving
2211 integer comparisons, it is best to omit these patterns.
2213 If these operations are omitted, the compiler will usually generate code
2214 that copies the constant one to the target and branches around an
2215 assignment of zero to the target. If this code is more efficient than
2216 the potential instructions used for the @samp{s@var{cond}} pattern
2217 followed by those required to convert the result into a 1 or a zero in
2218 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2219 the machine description.
2221 @cindex @code{b@var{cond}} instruction pattern
2222 @item @samp{b@var{cond}}
2223 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2224 refers to the label to jump to. Jump if the condition codes meet
2225 condition @var{cond}.
2227 Some machines do not follow the model assumed here where a comparison
2228 instruction is followed by a conditional branch instruction. In that
2229 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2230 simply store the operands away and generate all the required insns in a
2231 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2232 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2233 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2234 pattern or a @samp{tst@var{m}} pattern.
2236 Machines that use a pseudo register for the condition code value, or
2237 where the mode used for the comparison depends on the condition being
2238 tested, should also use the above mechanism. @xref{Jump Patterns}.
2240 The above discussion also applies to the @samp{mov@var{mode}cc} and
2241 @samp{s@var{cond}} patterns.
2243 @cindex @code{call} instruction pattern
2245 Subroutine call instruction returning no value. Operand 0 is the
2246 function to call; operand 1 is the number of bytes of arguments pushed
2247 as a @code{const_int}; operand 2 is the number of registers used as
2250 On most machines, operand 2 is not actually stored into the RTL
2251 pattern. It is supplied for the sake of some RISC machines which need
2252 to put this information into the assembler code; they can put it in
2253 the RTL instead of operand 1.
2255 Operand 0 should be a @code{mem} RTX whose address is the address of the
2256 function. Note, however, that this address can be a @code{symbol_ref}
2257 expression even if it would not be a legitimate memory address on the
2258 target machine. If it is also not a valid argument for a call
2259 instruction, the pattern for this operation should be a
2260 @code{define_expand} (@pxref{Expander Definitions}) that places the
2261 address into a register and uses that register in the call instruction.
2263 @cindex @code{call_value} instruction pattern
2264 @item @samp{call_value}
2265 Subroutine call instruction returning a value. Operand 0 is the hard
2266 register in which the value is returned. There are three more
2267 operands, the same as the three operands of the @samp{call}
2268 instruction (but with numbers increased by one).
2270 Subroutines that return @code{BLKmode} objects use the @samp{call}
2273 @cindex @code{call_pop} instruction pattern
2274 @cindex @code{call_value_pop} instruction pattern
2275 @item @samp{call_pop}, @samp{call_value_pop}
2276 Similar to @samp{call} and @samp{call_value}, except used if defined and
2277 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2278 that contains both the function call and a @code{set} to indicate the
2279 adjustment made to the frame pointer.
2281 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2282 patterns increases the number of functions for which the frame pointer
2283 can be eliminated, if desired.
2285 @cindex @code{untyped_call} instruction pattern
2286 @item @samp{untyped_call}
2287 Subroutine call instruction returning a value of any type. Operand 0 is
2288 the function to call; operand 1 is a memory location where the result of
2289 calling the function is to be stored; operand 2 is a @code{parallel}
2290 expression where each element is a @code{set} expression that indicates
2291 the saving of a function return value into the result block.
2293 This instruction pattern should be defined to support
2294 @code{__builtin_apply} on machines where special instructions are needed
2295 to call a subroutine with arbitrary arguments or to save the value
2296 returned. This instruction pattern is required on machines that have
2297 multiple registers that can hold a return value (i.e.
2298 @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2300 @cindex @code{return} instruction pattern
2302 Subroutine return instruction. This instruction pattern name should be
2303 defined only if a single instruction can do all the work of returning
2306 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2307 RTL generation phase. In this case it is to support machines where
2308 multiple instructions are usually needed to return from a function, but
2309 some class of functions only requires one instruction to implement a
2310 return. Normally, the applicable functions are those which do not need
2311 to save any registers or allocate stack space.
2313 @findex reload_completed
2314 @findex leaf_function_p
2315 For such machines, the condition specified in this pattern should only
2316 be true when @code{reload_completed} is non-zero and the function's
2317 epilogue would only be a single instruction. For machines with register
2318 windows, the routine @code{leaf_function_p} may be used to determine if
2319 a register window push is required.
2321 Machines that have conditional return instructions should define patterns
2327 (if_then_else (match_operator
2328 0 "comparison_operator"
2329 [(cc0) (const_int 0)])
2336 where @var{condition} would normally be the same condition specified on the
2337 named @samp{return} pattern.
2339 @cindex @code{untyped_return} instruction pattern
2340 @item @samp{untyped_return}
2341 Untyped subroutine return instruction. This instruction pattern should
2342 be defined to support @code{__builtin_return} on machines where special
2343 instructions are needed to return a value of any type.
2345 Operand 0 is a memory location where the result of calling a function
2346 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2347 expression where each element is a @code{set} expression that indicates
2348 the restoring of a function return value from the result block.
2350 @cindex @code{nop} instruction pattern
2352 No-op instruction. This instruction pattern name should always be defined
2353 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2356 @cindex @code{indirect_jump} instruction pattern
2357 @item @samp{indirect_jump}
2358 An instruction to jump to an address which is operand zero.
2359 This pattern name is mandatory on all machines.
2361 @cindex @code{casesi} instruction pattern
2363 Instruction to jump through a dispatch table, including bounds checking.
2364 This instruction takes five operands:
2368 The index to dispatch on, which has mode @code{SImode}.
2371 The lower bound for indices in the table, an integer constant.
2374 The total range of indices in the table---the largest index
2375 minus the smallest one (both inclusive).
2378 A label that precedes the table itself.
2381 A label to jump to if the index has a value outside the bounds.
2382 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2383 then an out-of-bounds index drops through to the code following
2384 the jump table instead of jumping to this label. In that case,
2385 this label is not actually used by the @samp{casesi} instruction,
2386 but it is always provided as an operand.)
2389 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2390 @code{jump_insn}. The number of elements in the table is one plus the
2391 difference between the upper bound and the lower bound.
2393 @cindex @code{tablejump} instruction pattern
2394 @item @samp{tablejump}
2395 Instruction to jump to a variable address. This is a low-level
2396 capability which can be used to implement a dispatch table when there
2397 is no @samp{casesi} pattern.
2399 This pattern requires two operands: the address or offset, and a label
2400 which should immediately precede the jump table. If the macro
2401 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2402 operand is an offset which counts from the address of the table; otherwise,
2403 it is an absolute address to jump to. In either case, the first operand has
2406 The @samp{tablejump} insn is always the last insn before the jump
2407 table it uses. Its assembler code normally has no need to use the
2408 second operand, but you should incorporate it in the RTL pattern so
2409 that the jump optimizer will not delete the table as unreachable code.
2411 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2412 @item @samp{canonicalize_funcptr_for_compare}
2413 Canonicalize the function pointer in operand 1 and store the result
2416 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2417 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2418 and also has mode @code{Pmode}.
2420 Canonicalization of a function pointer usually involves computing
2421 the address of the function which would be called if the function
2422 pointer were used in an indirect call.
2424 Only define this pattern if function pointers on the target machine
2425 can have different values but still call the same function when
2426 used in an indirect call.
2428 @cindex @code{save_stack_block} instruction pattern
2429 @cindex @code{save_stack_function} instruction pattern
2430 @cindex @code{save_stack_nonlocal} instruction pattern
2431 @cindex @code{restore_stack_block} instruction pattern
2432 @cindex @code{restore_stack_function} instruction pattern
2433 @cindex @code{restore_stack_nonlocal} instruction pattern
2434 @item @samp{save_stack_block}
2435 @itemx @samp{save_stack_function}
2436 @itemx @samp{save_stack_nonlocal}
2437 @itemx @samp{restore_stack_block}
2438 @itemx @samp{restore_stack_function}
2439 @itemx @samp{restore_stack_nonlocal}
2440 Most machines save and restore the stack pointer by copying it to or
2441 from an object of mode @code{Pmode}. Do not define these patterns on
2444 Some machines require special handling for stack pointer saves and
2445 restores. On those machines, define the patterns corresponding to the
2446 non-standard cases by using a @code{define_expand} (@pxref{Expander
2447 Definitions}) that produces the required insns. The three types of
2448 saves and restores are:
2452 @samp{save_stack_block} saves the stack pointer at the start of a block
2453 that allocates a variable-sized object, and @samp{restore_stack_block}
2454 restores the stack pointer when the block is exited.
2457 @samp{save_stack_function} and @samp{restore_stack_function} do a
2458 similar job for the outermost block of a function and are used when the
2459 function allocates variable-sized objects or calls @code{alloca}. Only
2460 the epilogue uses the restored stack pointer, allowing a simpler save or
2461 restore sequence on some machines.
2464 @samp{save_stack_nonlocal} is used in functions that contain labels
2465 branched to by nested functions. It saves the stack pointer in such a
2466 way that the inner function can use @samp{restore_stack_nonlocal} to
2467 restore the stack pointer. The compiler generates code to restore the
2468 frame and argument pointer registers, but some machines require saving
2469 and restoring additional data such as register window information or
2470 stack backchains. Place insns in these patterns to save and restore any
2474 When saving the stack pointer, operand 0 is the save area and operand 1
2475 is the stack pointer. The mode used to allocate the save area defaults
2476 to @code{Pmode} but you can override that choice by defining the
2477 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
2478 specify an integral mode, or @code{VOIDmode} if no save area is needed
2479 for a particular type of save (either because no save is needed or
2480 because a machine-specific save area can be used). Operand 0 is the
2481 stack pointer and operand 1 is the save area for restore operations. If
2482 @samp{save_stack_block} is defined, operand 0 must not be
2483 @code{VOIDmode} since these saves can be arbitrarily nested.
2485 A save area is a @code{mem} that is at a constant offset from
2486 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2487 nonlocal gotos and a @code{reg} in the other two cases.
2489 @cindex @code{allocate_stack} instruction pattern
2490 @item @samp{allocate_stack}
2491 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2492 the stack pointer to create space for dynamically allocated data.
2494 Store the resultant pointer to this space into operand 0. If you
2495 are allocating space from the main stack, do this by emitting a
2496 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2497 If you are allocating the space elsewhere, generate code to copy the
2498 location of the space to operand 0. In the latter case, you must
2499 ensure this space gets freed when the corresponding space on the main
2502 Do not define this pattern if all that must be done is the subtraction.
2503 Some machines require other operations such as stack probes or
2504 maintaining the back chain. Define this pattern to emit those
2505 operations in addition to updating the stack pointer.
2507 @cindex @code{probe} instruction pattern
2509 Some machines require instructions to be executed after space is
2510 allocated from the stack, for example to generate a reference at
2511 the bottom of the stack.
2513 If you need to emit instructions before the stack has been adjusted,
2514 put them into the @samp{allocate_stack} pattern. Otherwise, define
2515 this pattern to emit the required instructions.
2517 No operands are provided.
2519 @cindex @code{check_stack} instruction pattern
2520 @item @samp{check_stack}
2521 If stack checking cannot be done on your system by probing the stack with
2522 a load or store instruction (@pxref{Stack Checking}), define this pattern
2523 to perform the needed check and signaling an error if the stack
2524 has overflowed. The single operand is the location in the stack furthest
2525 from the current stack pointer that you need to validate. Normally,
2526 on machines where this pattern is needed, you would obtain the stack
2527 limit from a global or thread-specific variable or register.
2529 @cindex @code{nonlocal_goto} instruction pattern
2530 @item @samp{nonlocal_goto}
2531 Emit code to generate a non-local goto, e.g., a jump from one function
2532 to a label in an outer function. This pattern has four arguments,
2533 each representing a value to be used in the jump. The first
2534 argument is to be loaded into the frame pointer, the second is
2535 the address to branch to (code to dispatch to the actual label),
2536 the third is the address of a location where the stack is saved,
2537 and the last is the address of the label, to be placed in the
2538 location for the incoming static chain.
2540 On most machines you need not define this pattern, since GNU CC will
2541 already generate the correct code, which is to load the frame pointer
2542 and static chain, restore the stack (using the
2543 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2544 to the dispatcher. You need only define this pattern if this code will
2545 not work on your machine.
2547 @cindex @code{nonlocal_goto_receiver} instruction pattern
2548 @item @samp{nonlocal_goto_receiver}
2549 This pattern, if defined, contains code needed at the target of a
2550 nonlocal goto after the code already generated by GNU CC. You will not
2551 normally need to define this pattern. A typical reason why you might
2552 need this pattern is if some value, such as a pointer to a global table,
2553 must be restored when the frame pointer is restored. Note that a nonlocal
2554 goto only occurs within a unit-of-translation, so a global table pointer
2555 that is shared by all functions of a given module need not be restored.
2556 There are no arguments.
2558 @cindex @code{exception_receiver} instruction pattern
2559 @item @samp{exception_receiver}
2560 This pattern, if defined, contains code needed at the site of an
2561 exception handler that isn't needed at the site of a nonlocal goto. You
2562 will not normally need to define this pattern. A typical reason why you
2563 might need this pattern is if some value, such as a pointer to a global
2564 table, must be restored after control flow is branched to the handler of
2565 an exception. There are no arguments.
2567 @cindex @code{builtin_setjmp_setup} instruction pattern
2568 @item @samp{builtin_setjmp_setup}
2569 This pattern, if defined, contains additional code needed to initialize
2570 the @code{jmp_buf}. You will not normally need to define this pattern.
2571 A typical reason why you might need this pattern is if some value, such
2572 as a pointer to a global table, must be restored. Though it is
2573 preferred that the pointer value be recalculated if possible (given the
2574 address of a label for instance). The single argument is a pointer to
2575 the @code{jmp_buf}. Note that the buffer is five words long and that
2576 the first three are normally used by the generic mechanism.
2578 @cindex @code{builtin_setjmp_receiver} instruction pattern
2579 @item @samp{builtin_setjmp_receiver}
2580 This pattern, if defined, contains code needed at the site of an
2581 builtin setjmp that isn't needed at the site of a nonlocal goto. You
2582 will not normally need to define this pattern. A typical reason why you
2583 might need this pattern is if some value, such as a pointer to a global
2584 table, must be restored. It takes one argument, which is the label
2585 to which builtin_longjmp transfered control; this pattern may be emitted
2586 at a small offset from that label.
2588 @cindex @code{builtin_longjmp} instruction pattern
2589 @item @samp{builtin_longjmp}
2590 This pattern, if defined, performs the entire action of the longjmp.
2591 You will not normally need to define this pattern unless you also define
2592 @code{builtin_setjmp_setup}. The single argument is a pointer to the
2595 @cindex @code{eh_epilogue} instruction pattern
2596 @item @samp{eh_epilogue}
2597 This pattern, if defined, affects the way @code{__builtin_eh_return},
2598 and thence @code{__throw} are built. It is intended to allow communication
2599 between the exception handling machinery and the normal epilogue code
2602 The pattern takes three arguments. The first is the exception context
2603 pointer. This will have already been copied to the function return
2604 register appropriate for a pointer; normally this can be ignored. The
2605 second argument is an offset to be added to the stack pointer. It will
2606 have been copied to some arbitrary call-clobbered hard reg so that it
2607 will survive until after reload to when the normal epilogue is generated.
2608 The final argument is the address of the exception handler to which
2609 the function should return. This will normally need to copied by the
2610 pattern to some special register.
2612 This pattern must be defined if @code{RETURN_ADDR_RTX} does not yield
2613 something that can be reliably and permanently modified, i.e. a fixed
2614 hard register or a stack memory reference.
2616 @cindex @code{prologue} instruction pattern
2617 @item @samp{prologue}
2618 This pattern, if defined, emits RTL for entry to a function. The function
2619 entry is resposible for setting up the stack frame, initializing the frame
2620 pointer register, saving callee saved registers, etc.
2622 Using a prologue pattern is generally preferred over defining
2623 @code{FUNCTION_PROLOGUE} to emit assembly code for the prologue.
2625 The @code{prologue} pattern is particularly useful for targets which perform
2626 instruction scheduling.
2628 @cindex @code{epilogue} instruction pattern
2629 @item @samp{epilogue}
2630 This pattern, if defined, emits RTL for exit from a function. The function
2631 exit is resposible for deallocating the stack frame, restoring callee saved
2632 registers and emitting the return instruction.
2634 Using an epilogue pattern is generally preferred over defining
2635 @code{FUNCTION_EPILOGUE} to emit assembly code for the prologue.
2637 The @code{epilogue} pattern is particularly useful for targets which perform
2638 instruction scheduling or which have delay slots for their return instruction.
2640 @cindex @code{sibcall_epilogue} instruction pattern
2641 @item @samp{sibcall_epilogue}
2642 This pattern, if defined, emits RTL for exit from a function without the final
2643 branch back to the calling function. This pattern will be emitted before any
2644 sibling call (aka tail call) sites.
2646 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
2647 parameter passing or any stack slots for arguments passed to the current
2650 @cindex @code{trap} instruction pattern
2652 This pattern, if defined, signals an error, typically by causing some
2653 kind of signal to be raised. Among other places, it is used by the Java
2654 frontend to signal `invalid array index' exceptions.
2656 @cindex @code{conditional_trap} instruction pattern
2657 @item @samp{conditional_trap}
2658 Conditional trap instruction. Operand 0 is a piece of RTL which
2659 performs a comparison. Operand 1 is the trap code, an integer.
2661 A typical @code{conditional_trap} pattern looks like
2664 (define_insn "conditional_trap"
2665 [(trap_if (match_operator 0 "trap_operator"
2666 [(cc0) (const_int 0)])
2667 (match_operand 1 "const_int_operand" "i"))]
2674 @node Pattern Ordering
2675 @section When the Order of Patterns Matters
2676 @cindex Pattern Ordering
2677 @cindex Ordering of Patterns
2679 Sometimes an insn can match more than one instruction pattern. Then the
2680 pattern that appears first in the machine description is the one used.
2681 Therefore, more specific patterns (patterns that will match fewer things)
2682 and faster instructions (those that will produce better code when they
2683 do match) should usually go first in the description.
2685 In some cases the effect of ordering the patterns can be used to hide
2686 a pattern when it is not valid. For example, the 68000 has an
2687 instruction for converting a fullword to floating point and another
2688 for converting a byte to floating point. An instruction converting
2689 an integer to floating point could match either one. We put the
2690 pattern to convert the fullword first to make sure that one will
2691 be used rather than the other. (Otherwise a large integer might
2692 be generated as a single-byte immediate quantity, which would not work.)
2693 Instead of using this pattern ordering it would be possible to make the
2694 pattern for convert-a-byte smart enough to deal properly with any
2697 @node Dependent Patterns
2698 @section Interdependence of Patterns
2699 @cindex Dependent Patterns
2700 @cindex Interdependence of Patterns
2702 Every machine description must have a named pattern for each of the
2703 conditional branch names @samp{b@var{cond}}. The recognition template
2704 must always have the form
2708 (if_then_else (@var{cond} (cc0) (const_int 0))
2709 (label_ref (match_operand 0 "" ""))
2714 In addition, every machine description must have an anonymous pattern
2715 for each of the possible reverse-conditional branches. Their templates
2720 (if_then_else (@var{cond} (cc0) (const_int 0))
2722 (label_ref (match_operand 0 "" ""))))
2726 They are necessary because jump optimization can turn direct-conditional
2727 branches into reverse-conditional branches.
2729 It is often convenient to use the @code{match_operator} construct to
2730 reduce the number of patterns that must be specified for branches. For
2736 (if_then_else (match_operator 0 "comparison_operator"
2737 [(cc0) (const_int 0)])
2739 (label_ref (match_operand 1 "" ""))))]
2744 In some cases machines support instructions identical except for the
2745 machine mode of one or more operands. For example, there may be
2746 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
2750 (set (match_operand:SI 0 @dots{})
2751 (extend:SI (match_operand:HI 1 @dots{})))
2753 (set (match_operand:SI 0 @dots{})
2754 (extend:SI (match_operand:QI 1 @dots{})))
2758 Constant integers do not specify a machine mode, so an instruction to
2759 extend a constant value could match either pattern. The pattern it
2760 actually will match is the one that appears first in the file. For correct
2761 results, this must be the one for the widest possible mode (@code{HImode},
2762 here). If the pattern matches the @code{QImode} instruction, the results
2763 will be incorrect if the constant value does not actually fit that mode.
2765 Such instructions to extend constants are rarely generated because they are
2766 optimized away, but they do occasionally happen in nonoptimized
2769 If a constraint in a pattern allows a constant, the reload pass may
2770 replace a register with a constant permitted by the constraint in some
2771 cases. Similarly for memory references. Because of this substitution,
2772 you should not provide separate patterns for increment and decrement
2773 instructions. Instead, they should be generated from the same pattern
2774 that supports register-register add insns by examining the operands and
2775 generating the appropriate machine instruction.
2778 @section Defining Jump Instruction Patterns
2779 @cindex jump instruction patterns
2780 @cindex defining jump instruction patterns
2782 For most machines, GNU CC assumes that the machine has a condition code.
2783 A comparison insn sets the condition code, recording the results of both
2784 signed and unsigned comparison of the given operands. A separate branch
2785 insn tests the condition code and branches or not according its value.
2786 The branch insns come in distinct signed and unsigned flavors. Many
2787 common machines, such as the Vax, the 68000 and the 32000, work this
2790 Some machines have distinct signed and unsigned compare instructions, and
2791 only one set of conditional branch instructions. The easiest way to handle
2792 these machines is to treat them just like the others until the final stage
2793 where assembly code is written. At this time, when outputting code for the
2794 compare instruction, peek ahead at the following branch using
2795 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
2796 being output, in the output-writing code in an instruction pattern.) If
2797 the RTL says that is an unsigned branch, output an unsigned compare;
2798 otherwise output a signed compare. When the branch itself is output, you
2799 can treat signed and unsigned branches identically.
2801 The reason you can do this is that GNU CC always generates a pair of
2802 consecutive RTL insns, possibly separated by @code{note} insns, one to
2803 set the condition code and one to test it, and keeps the pair inviolate
2806 To go with this technique, you must define the machine-description macro
2807 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
2808 compare instruction is superfluous.
2810 Some machines have compare-and-branch instructions and no condition code.
2811 A similar technique works for them. When it is time to ``output'' a
2812 compare instruction, record its operands in two static variables. When
2813 outputting the branch-on-condition-code instruction that follows, actually
2814 output a compare-and-branch instruction that uses the remembered operands.
2816 It also works to define patterns for compare-and-branch instructions.
2817 In optimizing compilation, the pair of compare and branch instructions
2818 will be combined according to these patterns. But this does not happen
2819 if optimization is not requested. So you must use one of the solutions
2820 above in addition to any special patterns you define.
2822 In many RISC machines, most instructions do not affect the condition
2823 code and there may not even be a separate condition code register. On
2824 these machines, the restriction that the definition and use of the
2825 condition code be adjacent insns is not necessary and can prevent
2826 important optimizations. For example, on the IBM RS/6000, there is a
2827 delay for taken branches unless the condition code register is set three
2828 instructions earlier than the conditional branch. The instruction
2829 scheduler cannot perform this optimization if it is not permitted to
2830 separate the definition and use of the condition code register.
2832 On these machines, do not use @code{(cc0)}, but instead use a register
2833 to represent the condition code. If there is a specific condition code
2834 register in the machine, use a hard register. If the condition code or
2835 comparison result can be placed in any general register, or if there are
2836 multiple condition registers, use a pseudo register.
2838 @findex prev_cc0_setter
2839 @findex next_cc0_user
2840 On some machines, the type of branch instruction generated may depend on
2841 the way the condition code was produced; for example, on the 68k and
2842 Sparc, setting the condition code directly from an add or subtract
2843 instruction does not clear the overflow bit the way that a test
2844 instruction does, so a different branch instruction must be used for
2845 some conditional branches. For machines that use @code{(cc0)}, the set
2846 and use of the condition code must be adjacent (separated only by
2847 @code{note} insns) allowing flags in @code{cc_status} to be used.
2848 (@xref{Condition Code}.) Also, the comparison and branch insns can be
2849 located from each other by using the functions @code{prev_cc0_setter}
2850 and @code{next_cc0_user}.
2852 However, this is not true on machines that do not use @code{(cc0)}. On
2853 those machines, no assumptions can be made about the adjacency of the
2854 compare and branch insns and the above methods cannot be used. Instead,
2855 we use the machine mode of the condition code register to record
2856 different formats of the condition code register.
2858 Registers used to store the condition code value should have a mode that
2859 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
2860 additional modes are required (as for the add example mentioned above in
2861 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
2862 additional modes required (@pxref{Condition Code}). Also define
2863 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
2865 If it is known during RTL generation that a different mode will be
2866 required (for example, if the machine has separate compare instructions
2867 for signed and unsigned quantities, like most IBM processors), they can
2868 be specified at that time.
2870 If the cases that require different modes would be made by instruction
2871 combination, the macro @code{SELECT_CC_MODE} determines which machine
2872 mode should be used for the comparison result. The patterns should be
2873 written using that mode. To support the case of the add on the Sparc
2874 discussed above, we have the pattern
2878 [(set (reg:CC_NOOV 0)
2880 (plus:SI (match_operand:SI 0 "register_operand" "%r")
2881 (match_operand:SI 1 "arith_operand" "rI"))
2887 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
2888 for comparisons whose argument is a @code{plus}.
2890 @node Insn Canonicalizations
2891 @section Canonicalization of Instructions
2892 @cindex canonicalization of instructions
2893 @cindex insn canonicalization
2895 There are often cases where multiple RTL expressions could represent an
2896 operation performed by a single machine instruction. This situation is
2897 most commonly encountered with logical, branch, and multiply-accumulate
2898 instructions. In such cases, the compiler attempts to convert these
2899 multiple RTL expressions into a single canonical form to reduce the
2900 number of insn patterns required.
2902 In addition to algebraic simplifications, following canonicalizations
2907 For commutative and comparison operators, a constant is always made the
2908 second operand. If a machine only supports a constant as the second
2909 operand, only patterns that match a constant in the second operand need
2912 @cindex @code{neg}, canonicalization of
2913 @cindex @code{not}, canonicalization of
2914 @cindex @code{mult}, canonicalization of
2915 @cindex @code{plus}, canonicalization of
2916 @cindex @code{minus}, canonicalization of
2917 For these operators, if only one operand is a @code{neg}, @code{not},
2918 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
2921 @cindex @code{compare}, canonicalization of
2923 For the @code{compare} operator, a constant is always the second operand
2924 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
2925 machines, there are rare cases where the compiler might want to construct
2926 a @code{compare} with a constant as the first operand. However, these
2927 cases are not common enough for it to be worthwhile to provide a pattern
2928 matching a constant as the first operand unless the machine actually has
2929 such an instruction.
2931 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
2932 @code{minus} is made the first operand under the same conditions as
2936 @code{(minus @var{x} (const_int @var{n}))} is converted to
2937 @code{(plus @var{x} (const_int @var{-n}))}.
2940 Within address computations (i.e., inside @code{mem}), a left shift is
2941 converted into the appropriate multiplication by a power of two.
2943 @cindex @code{ior}, canonicalization of
2944 @cindex @code{and}, canonicalization of
2945 @cindex De Morgan's law
2947 De`Morgan's Law is used to move bitwise negation inside a bitwise
2948 logical-and or logical-or operation. If this results in only one
2949 operand being a @code{not} expression, it will be the first one.
2951 A machine that has an instruction that performs a bitwise logical-and of one
2952 operand with the bitwise negation of the other should specify the pattern
2953 for that instruction as
2957 [(set (match_operand:@var{m} 0 @dots{})
2958 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
2959 (match_operand:@var{m} 2 @dots{})))]
2965 Similarly, a pattern for a ``NAND'' instruction should be written
2969 [(set (match_operand:@var{m} 0 @dots{})
2970 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
2971 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
2976 In both cases, it is not necessary to include patterns for the many
2977 logically equivalent RTL expressions.
2979 @cindex @code{xor}, canonicalization of
2981 The only possible RTL expressions involving both bitwise exclusive-or
2982 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
2983 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
2986 The sum of three items, one of which is a constant, will only appear in
2990 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
2994 On machines that do not use @code{cc0},
2995 @code{(compare @var{x} (const_int 0))} will be converted to
2998 @cindex @code{zero_extract}, canonicalization of
2999 @cindex @code{sign_extract}, canonicalization of
3001 Equality comparisons of a group of bits (usually a single bit) with zero
3002 will be written using @code{zero_extract} rather than the equivalent
3003 @code{and} or @code{sign_extract} operations.
3007 @node Expander Definitions
3008 @section Defining RTL Sequences for Code Generation
3009 @cindex expander definitions
3010 @cindex code generation RTL sequences
3011 @cindex defining RTL sequences for code generation
3013 On some target machines, some standard pattern names for RTL generation
3014 cannot be handled with single insn, but a sequence of RTL insns can
3015 represent them. For these target machines, you can write a
3016 @code{define_expand} to specify how to generate the sequence of RTL.
3018 @findex define_expand
3019 A @code{define_expand} is an RTL expression that looks almost like a
3020 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3021 only for RTL generation and it can produce more than one RTL insn.
3023 A @code{define_expand} RTX has four operands:
3027 The name. Each @code{define_expand} must have a name, since the only
3028 use for it is to refer to it by name.
3031 The RTL template. This is a vector of RTL expressions representing
3032 a sequence of separate instructions. Unlike @code{define_insn}, there
3033 is no implicit surrounding @code{PARALLEL}.
3036 The condition, a string containing a C expression. This expression is
3037 used to express how the availability of this pattern depends on
3038 subclasses of target machine, selected by command-line options when GNU
3039 CC is run. This is just like the condition of a @code{define_insn} that
3040 has a standard name. Therefore, the condition (if present) may not
3041 depend on the data in the insn being matched, but only the
3042 target-machine-type flags. The compiler needs to test these conditions
3043 during initialization in order to learn exactly which named instructions
3044 are available in a particular run.
3047 The preparation statements, a string containing zero or more C
3048 statements which are to be executed before RTL code is generated from
3051 Usually these statements prepare temporary registers for use as
3052 internal operands in the RTL template, but they can also generate RTL
3053 insns directly by calling routines such as @code{emit_insn}, etc.
3054 Any such insns precede the ones that come from the RTL template.
3057 Every RTL insn emitted by a @code{define_expand} must match some
3058 @code{define_insn} in the machine description. Otherwise, the compiler
3059 will crash when trying to generate code for the insn or trying to optimize
3062 The RTL template, in addition to controlling generation of RTL insns,
3063 also describes the operands that need to be specified when this pattern
3064 is used. In particular, it gives a predicate for each operand.
3066 A true operand, which needs to be specified in order to generate RTL from
3067 the pattern, should be described with a @code{match_operand} in its first
3068 occurrence in the RTL template. This enters information on the operand's
3069 predicate into the tables that record such things. GNU CC uses the
3070 information to preload the operand into a register if that is required for
3071 valid RTL code. If the operand is referred to more than once, subsequent
3072 references should use @code{match_dup}.
3074 The RTL template may also refer to internal ``operands'' which are
3075 temporary registers or labels used only within the sequence made by the
3076 @code{define_expand}. Internal operands are substituted into the RTL
3077 template with @code{match_dup}, never with @code{match_operand}. The
3078 values of the internal operands are not passed in as arguments by the
3079 compiler when it requests use of this pattern. Instead, they are computed
3080 within the pattern, in the preparation statements. These statements
3081 compute the values and store them into the appropriate elements of
3082 @code{operands} so that @code{match_dup} can find them.
3084 There are two special macros defined for use in the preparation statements:
3085 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3092 Use the @code{DONE} macro to end RTL generation for the pattern. The
3093 only RTL insns resulting from the pattern on this occasion will be
3094 those already emitted by explicit calls to @code{emit_insn} within the
3095 preparation statements; the RTL template will not be generated.
3099 Make the pattern fail on this occasion. When a pattern fails, it means
3100 that the pattern was not truly available. The calling routines in the
3101 compiler will try other strategies for code generation using other patterns.
3103 Failure is currently supported only for binary (addition, multiplication,
3104 shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
3108 Here is an example, the definition of left-shift for the SPUR chip:
3112 (define_expand "ashlsi3"
3113 [(set (match_operand:SI 0 "register_operand" "")
3117 (match_operand:SI 1 "register_operand" "")
3118 (match_operand:SI 2 "nonmemory_operand" "")))]
3127 if (GET_CODE (operands[2]) != CONST_INT
3128 || (unsigned) INTVAL (operands[2]) > 3)
3135 This example uses @code{define_expand} so that it can generate an RTL insn
3136 for shifting when the shift-count is in the supported range of 0 to 3 but
3137 fail in other cases where machine insns aren't available. When it fails,
3138 the compiler tries another strategy using different patterns (such as, a
3141 If the compiler were able to handle nontrivial condition-strings in
3142 patterns with names, then it would be possible to use a
3143 @code{define_insn} in that case. Here is another case (zero-extension
3144 on the 68000) which makes more use of the power of @code{define_expand}:
3147 (define_expand "zero_extendhisi2"
3148 [(set (match_operand:SI 0 "general_operand" "")
3150 (set (strict_low_part
3154 (match_operand:HI 1 "general_operand" ""))]
3156 "operands[1] = make_safe_from (operands[1], operands[0]);")
3160 @findex make_safe_from
3161 Here two RTL insns are generated, one to clear the entire output operand
3162 and the other to copy the input operand into its low half. This sequence
3163 is incorrect if the input operand refers to [the old value of] the output
3164 operand, so the preparation statement makes sure this isn't so. The
3165 function @code{make_safe_from} copies the @code{operands[1]} into a
3166 temporary register if it refers to @code{operands[0]}. It does this
3167 by emitting another RTL insn.
3169 Finally, a third example shows the use of an internal operand.
3170 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3171 against a halfword mask. But this mask cannot be represented by a
3172 @code{const_int} because the constant value is too large to be legitimate
3173 on this machine. So it must be copied into a register with
3174 @code{force_reg} and then the register used in the @code{and}.
3177 (define_expand "zero_extendhisi2"
3178 [(set (match_operand:SI 0 "register_operand" "")
3180 (match_operand:HI 1 "register_operand" "")
3185 = force_reg (SImode, GEN_INT (65535)); ")
3188 @strong{Note:} If the @code{define_expand} is used to serve a
3189 standard binary or unary arithmetic operation or a bitfield operation,
3190 then the last insn it generates must not be a @code{code_label},
3191 @code{barrier} or @code{note}. It must be an @code{insn},
3192 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3193 at the end, emit an insn to copy the result of the operation into
3194 itself. Such an insn will generate no code, but it can avoid problems
3195 in the compiler.@refill
3197 @node Insn Splitting
3198 @section Defining How to Split Instructions
3199 @cindex insn splitting
3200 @cindex instruction splitting
3201 @cindex splitting instructions
3203 There are two cases where you should specify how to split a pattern into
3204 multiple insns. On machines that have instructions requiring delay
3205 slots (@pxref{Delay Slots}) or that have instructions whose output is
3206 not available for multiple cycles (@pxref{Function Units}), the compiler
3207 phases that optimize these cases need to be able to move insns into
3208 one-instruction delay slots. However, some insns may generate more than one
3209 machine instruction. These insns cannot be placed into a delay slot.
3211 Often you can rewrite the single insn as a list of individual insns,
3212 each corresponding to one machine instruction. The disadvantage of
3213 doing so is that it will cause the compilation to be slower and require
3214 more space. If the resulting insns are too complex, it may also
3215 suppress some optimizations. The compiler splits the insn if there is a
3216 reason to believe that it might improve instruction or delay slot
3219 The insn combiner phase also splits putative insns. If three insns are
3220 merged into one insn with a complex expression that cannot be matched by
3221 some @code{define_insn} pattern, the combiner phase attempts to split
3222 the complex pattern into two insns that are recognized. Usually it can
3223 break the complex pattern into two patterns by splitting out some
3224 subexpression. However, in some other cases, such as performing an
3225 addition of a large constant in two insns on a RISC machine, the way to
3226 split the addition into two insns is machine-dependent.
3228 @findex define_split
3229 The @code{define_split} definition tells the compiler how to split a
3230 complex insn into several simpler insns. It looks like this:
3234 [@var{insn-pattern}]
3236 [@var{new-insn-pattern-1}
3237 @var{new-insn-pattern-2}
3239 "@var{preparation statements}")
3242 @var{insn-pattern} is a pattern that needs to be split and
3243 @var{condition} is the final condition to be tested, as in a
3244 @code{define_insn}. When an insn matching @var{insn-pattern} and
3245 satisfying @var{condition} is found, it is replaced in the insn list
3246 with the insns given by @var{new-insn-pattern-1},
3247 @var{new-insn-pattern-2}, etc.
3249 The @var{preparation statements} are similar to those statements that
3250 are specified for @code{define_expand} (@pxref{Expander Definitions})
3251 and are executed before the new RTL is generated to prepare for the
3252 generated code or emit some insns whose pattern is not fixed. Unlike
3253 those in @code{define_expand}, however, these statements must not
3254 generate any new pseudo-registers. Once reload has completed, they also
3255 must not allocate any space in the stack frame.
3257 Patterns are matched against @var{insn-pattern} in two different
3258 circumstances. If an insn needs to be split for delay slot scheduling
3259 or insn scheduling, the insn is already known to be valid, which means
3260 that it must have been matched by some @code{define_insn} and, if
3261 @code{reload_completed} is non-zero, is known to satisfy the constraints
3262 of that @code{define_insn}. In that case, the new insn patterns must
3263 also be insns that are matched by some @code{define_insn} and, if
3264 @code{reload_completed} is non-zero, must also satisfy the constraints
3265 of those definitions.
3267 As an example of this usage of @code{define_split}, consider the following
3268 example from @file{a29k.md}, which splits a @code{sign_extend} from
3269 @code{HImode} to @code{SImode} into a pair of shift insns:
3273 [(set (match_operand:SI 0 "gen_reg_operand" "")
3274 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3277 (ashift:SI (match_dup 1)
3280 (ashiftrt:SI (match_dup 0)
3283 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3286 When the combiner phase tries to split an insn pattern, it is always the
3287 case that the pattern is @emph{not} matched by any @code{define_insn}.
3288 The combiner pass first tries to split a single @code{set} expression
3289 and then the same @code{set} expression inside a @code{parallel}, but
3290 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3291 register. In these cases, the combiner expects exactly two new insn
3292 patterns to be generated. It will verify that these patterns match some
3293 @code{define_insn} definitions, so you need not do this test in the
3294 @code{define_split} (of course, there is no point in writing a
3295 @code{define_split} that will never produce insns that match).
3297 Here is an example of this use of @code{define_split}, taken from
3302 [(set (match_operand:SI 0 "gen_reg_operand" "")
3303 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3304 (match_operand:SI 2 "non_add_cint_operand" "")))]
3306 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3307 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3310 int low = INTVAL (operands[2]) & 0xffff;
3311 int high = (unsigned) INTVAL (operands[2]) >> 16;
3314 high++, low |= 0xffff0000;
3316 operands[3] = GEN_INT (high << 16);
3317 operands[4] = GEN_INT (low);
3321 Here the predicate @code{non_add_cint_operand} matches any
3322 @code{const_int} that is @emph{not} a valid operand of a single add
3323 insn. The add with the smaller displacement is written so that it
3324 can be substituted into the address of a subsequent operation.
3326 An example that uses a scratch register, from the same file, generates
3327 an equality comparison of a register and a large constant:
3331 [(set (match_operand:CC 0 "cc_reg_operand" "")
3332 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3333 (match_operand:SI 2 "non_short_cint_operand" "")))
3334 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3335 "find_single_use (operands[0], insn, 0)
3336 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3337 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3338 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3339 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3342 /* Get the constant we are comparing against, C, and see what it
3343 looks like sign-extended to 16 bits. Then see what constant
3344 could be XOR'ed with C to get the sign-extended value. */
3346 int c = INTVAL (operands[2]);
3347 int sextc = (c << 16) >> 16;
3348 int xorv = c ^ sextc;
3350 operands[4] = GEN_INT (xorv);
3351 operands[5] = GEN_INT (sextc);
3355 To avoid confusion, don't write a single @code{define_split} that
3356 accepts some insns that match some @code{define_insn} as well as some
3357 insns that don't. Instead, write two separate @code{define_split}
3358 definitions, one for the insns that are valid and one for the insns that
3361 @node Peephole Definitions
3362 @section Machine-Specific Peephole Optimizers
3363 @cindex peephole optimizer definitions
3364 @cindex defining peephole optimizers
3366 In addition to instruction patterns the @file{md} file may contain
3367 definitions of machine-specific peephole optimizations.
3369 The combiner does not notice certain peephole optimizations when the data
3370 flow in the program does not suggest that it should try them. For example,
3371 sometimes two consecutive insns related in purpose can be combined even
3372 though the second one does not appear to use a register computed in the
3373 first one. A machine-specific peephole optimizer can detect such
3376 There are two forms of peephole definitions that may be used. The
3377 original @code{define_peephole} is run at assembly output time to
3378 match insns and substitute assembly text. Use of @code{define_peephole}
3381 A newer @code{define_peephole2} matches insns and substitutes new
3382 insns. The @code{peephole2} pass is run after register allocation
3383 but before scheduling, which may result in much better code for
3384 targets that do scheduling.
3387 * define_peephole:: RTL to Text Peephole Optimizers
3388 * define_peephole2:: RTL to RTL Peephole Optimizers
3391 @node define_peephole
3392 @subsection RTL to Text Peephole Optimizers
3393 @findex define_peephole
3396 A definition looks like this:
3400 [@var{insn-pattern-1}
3401 @var{insn-pattern-2}
3405 "@var{optional insn-attributes}")
3409 The last string operand may be omitted if you are not using any
3410 machine-specific information in this machine description. If present,
3411 it must obey the same rules as in a @code{define_insn}.
3413 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
3414 consecutive insns. The optimization applies to a sequence of insns when
3415 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
3416 the next, and so on.@refill
3418 Each of the insns matched by a peephole must also match a
3419 @code{define_insn}. Peepholes are checked only at the last stage just
3420 before code generation, and only optionally. Therefore, any insn which
3421 would match a peephole but no @code{define_insn} will cause a crash in code
3422 generation in an unoptimized compilation, or at various optimization
3425 The operands of the insns are matched with @code{match_operands},
3426 @code{match_operator}, and @code{match_dup}, as usual. What is not
3427 usual is that the operand numbers apply to all the insn patterns in the
3428 definition. So, you can check for identical operands in two insns by
3429 using @code{match_operand} in one insn and @code{match_dup} in the
3432 The operand constraints used in @code{match_operand} patterns do not have
3433 any direct effect on the applicability of the peephole, but they will
3434 be validated afterward, so make sure your constraints are general enough
3435 to apply whenever the peephole matches. If the peephole matches
3436 but the constraints are not satisfied, the compiler will crash.
3438 It is safe to omit constraints in all the operands of the peephole; or
3439 you can write constraints which serve as a double-check on the criteria
3442 Once a sequence of insns matches the patterns, the @var{condition} is
3443 checked. This is a C expression which makes the final decision whether to
3444 perform the optimization (we do so if the expression is nonzero). If
3445 @var{condition} is omitted (in other words, the string is empty) then the
3446 optimization is applied to every sequence of insns that matches the
3449 The defined peephole optimizations are applied after register allocation
3450 is complete. Therefore, the peephole definition can check which
3451 operands have ended up in which kinds of registers, just by looking at
3454 @findex prev_active_insn
3455 The way to refer to the operands in @var{condition} is to write
3456 @code{operands[@var{i}]} for operand number @var{i} (as matched by
3457 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
3458 to refer to the last of the insns being matched; use
3459 @code{prev_active_insn} to find the preceding insns.
3461 @findex dead_or_set_p
3462 When optimizing computations with intermediate results, you can use
3463 @var{condition} to match only when the intermediate results are not used
3464 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
3465 @var{op})}, where @var{insn} is the insn in which you expect the value
3466 to be used for the last time (from the value of @code{insn}, together
3467 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
3468 value (from @code{operands[@var{i}]}).@refill
3470 Applying the optimization means replacing the sequence of insns with one
3471 new insn. The @var{template} controls ultimate output of assembler code
3472 for this combined insn. It works exactly like the template of a
3473 @code{define_insn}. Operand numbers in this template are the same ones
3474 used in matching the original sequence of insns.
3476 The result of a defined peephole optimizer does not need to match any of
3477 the insn patterns in the machine description; it does not even have an
3478 opportunity to match them. The peephole optimizer definition itself serves
3479 as the insn pattern to control how the insn is output.
3481 Defined peephole optimizers are run as assembler code is being output,
3482 so the insns they produce are never combined or rearranged in any way.
3484 Here is an example, taken from the 68000 machine description:
3488 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3489 (set (match_operand:DF 0 "register_operand" "=f")
3490 (match_operand:DF 1 "register_operand" "ad"))]
3491 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3495 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3497 output_asm_insn (\"move.l %1,(sp)\", xoperands);
3498 output_asm_insn (\"move.l %1,-(sp)\", operands);
3499 return \"fmove.d (sp)+,%0\";
3501 output_asm_insn (\"movel %1,sp@@\", xoperands);
3502 output_asm_insn (\"movel %1,sp@@-\", operands);
3503 return \"fmoved sp@@+,%0\";
3510 The effect of this optimization is to change
3536 If a peephole matches a sequence including one or more jump insns, you must
3537 take account of the flags such as @code{CC_REVERSED} which specify that the
3538 condition codes are represented in an unusual manner. The compiler
3539 automatically alters any ordinary conditional jumps which occur in such
3540 situations, but the compiler cannot alter jumps which have been replaced by
3541 peephole optimizations. So it is up to you to alter the assembler code
3542 that the peephole produces. Supply C code to write the assembler output,
3543 and in this C code check the condition code status flags and change the
3544 assembler code as appropriate.
3547 @var{insn-pattern-1} and so on look @emph{almost} like the second
3548 operand of @code{define_insn}. There is one important difference: the
3549 second operand of @code{define_insn} consists of one or more RTX's
3550 enclosed in square brackets. Usually, there is only one: then the same
3551 action can be written as an element of a @code{define_peephole}. But
3552 when there are multiple actions in a @code{define_insn}, they are
3553 implicitly enclosed in a @code{parallel}. Then you must explicitly
3554 write the @code{parallel}, and the square brackets within it, in the
3555 @code{define_peephole}. Thus, if an insn pattern looks like this,
3558 (define_insn "divmodsi4"
3559 [(set (match_operand:SI 0 "general_operand" "=d")
3560 (div:SI (match_operand:SI 1 "general_operand" "0")
3561 (match_operand:SI 2 "general_operand" "dmsK")))
3562 (set (match_operand:SI 3 "general_operand" "=d")
3563 (mod:SI (match_dup 1) (match_dup 2)))]
3565 "divsl%.l %2,%3:%0")
3569 then the way to mention this insn in a peephole is as follows:
3575 [(set (match_operand:SI 0 "general_operand" "=d")
3576 (div:SI (match_operand:SI 1 "general_operand" "0")
3577 (match_operand:SI 2 "general_operand" "dmsK")))
3578 (set (match_operand:SI 3 "general_operand" "=d")
3579 (mod:SI (match_dup 1) (match_dup 2)))])
3584 @node define_peephole2
3585 @subsection RTL to RTL Peephole Optimizers
3586 @findex define_peephole2
3588 The @code{define_peephole2} definition tells the compiler how to
3589 substitute one sequence of instructions for another sequence,
3590 what additional scratch registers may be needed and what their
3595 [@var{insn-pattern-1}
3596 @var{insn-pattern-2}
3599 [@var{new-insn-pattern-1}
3600 @var{new-insn-pattern-2}
3602 "@var{preparation statements}")
3605 The definition is almost identical to @code{define_split}
3606 (@pxref{Insn Splitting}) except that the pattern to match is not a
3607 single instruction, but a sequence of instructions.
3609 It is possible to request additional scratch registers for use in the
3610 output template. If appropriate registers are not free, the pattern
3611 will simply not match.
3613 @findex match_scratch
3615 Scratch registers are requested with a @code{match_scratch} pattern at
3616 the top level of the input pattern. The allocated register (initially) will
3617 be dead at the point requested within the original sequence. If the scratch
3618 is used at more than a single point, a @code{match_dup} pattern at the
3619 top level of the input pattern marks the last position in the input sequence
3620 at which the register must be available.
3622 Here is an example from the IA-32 machine description:
3626 [(match_scratch:SI 2 "r")
3627 (parallel [(set (match_operand:SI 0 "register_operand" "")
3628 (match_operator:SI 3 "arith_or_logical_operator"
3630 (match_operand:SI 1 "memory_operand" "")]))
3631 (clobber (reg:CC 17))])]
3632 "! optimize_size && ! TARGET_READ_MODIFY"
3633 [(set (match_dup 2) (match_dup 1))
3634 (parallel [(set (match_dup 0)
3635 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
3636 (clobber (reg:CC 17))])]
3641 This pattern tries to split a load from its use in the hopes that we'll be
3642 able to schedule around the memory load latency. It allocates a single
3643 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
3644 to be live only at the point just before the arithmetic.
3646 A real example requring extended scratch lifetimes is harder to come by,
3647 so here's a silly made-up example:
3651 [(match_scratch:SI 4 "r")
3652 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
3653 (set (match_operand:SI 2 "" "") (match_dup 1))
3655 (set (match_operand:SI 3 "" "") (match_dup 1))]
3656 "@var{determine 1 does not overlap 0 and 2}"
3657 [(set (match_dup 4) (match_dup 1))
3658 (set (match_dup 0) (match_dup 4))
3659 (set (match_dup 2) (match_dup 4))]
3660 (set (match_dup 3) (match_dup 4))]
3665 If we had not added the @code{(match_dup 4)} in the middle of the input
3666 sequence, it might have been the case that the register we chose at the
3667 beginning of the sequence is killed by the first or second @code{set}.
3669 @node Insn Attributes
3670 @section Instruction Attributes
3671 @cindex insn attributes
3672 @cindex instruction attributes
3674 In addition to describing the instruction supported by the target machine,
3675 the @file{md} file also defines a group of @dfn{attributes} and a set of
3676 values for each. Every generated insn is assigned a value for each attribute.
3677 One possible attribute would be the effect that the insn has on the machine's
3678 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
3679 to track the condition codes.
3682 * Defining Attributes:: Specifying attributes and their values.
3683 * Expressions:: Valid expressions for attribute values.
3684 * Tagging Insns:: Assigning attribute values to insns.
3685 * Attr Example:: An example of assigning attributes.
3686 * Insn Lengths:: Computing the length of insns.
3687 * Constant Attributes:: Defining attributes that are constant.
3688 * Delay Slots:: Defining delay slots required for a machine.
3689 * Function Units:: Specifying information for insn scheduling.
3692 @node Defining Attributes
3693 @subsection Defining Attributes and their Values
3694 @cindex defining attributes and their values
3695 @cindex attributes, defining
3698 The @code{define_attr} expression is used to define each attribute required
3699 by the target machine. It looks like:
3702 (define_attr @var{name} @var{list-of-values} @var{default})
3705 @var{name} is a string specifying the name of the attribute being defined.
3707 @var{list-of-values} is either a string that specifies a comma-separated
3708 list of values that can be assigned to the attribute, or a null string to
3709 indicate that the attribute takes numeric values.
3711 @var{default} is an attribute expression that gives the value of this
3712 attribute for insns that match patterns whose definition does not include
3713 an explicit value for this attribute. @xref{Attr Example}, for more
3714 information on the handling of defaults. @xref{Constant Attributes},
3715 for information on attributes that do not depend on any particular insn.
3718 For each defined attribute, a number of definitions are written to the
3719 @file{insn-attr.h} file. For cases where an explicit set of values is
3720 specified for an attribute, the following are defined:
3724 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
3727 An enumeral class is defined for @samp{attr_@var{name}} with
3728 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
3729 the attribute name and value are first converted to upper case.
3732 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
3733 returns the attribute value for that insn.
3736 For example, if the following is present in the @file{md} file:
3739 (define_attr "type" "branch,fp,load,store,arith" @dots{})
3743 the following lines will be written to the file @file{insn-attr.h}.
3746 #define HAVE_ATTR_type
3747 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
3748 TYPE_STORE, TYPE_ARITH@};
3749 extern enum attr_type get_attr_type ();
3752 If the attribute takes numeric values, no @code{enum} type will be
3753 defined and the function to obtain the attribute's value will return
3757 @subsection Attribute Expressions
3758 @cindex attribute expressions
3760 RTL expressions used to define attributes use the codes described above
3761 plus a few specific to attribute definitions, to be discussed below.
3762 Attribute value expressions must have one of the following forms:
3765 @cindex @code{const_int} and attributes
3766 @item (const_int @var{i})
3767 The integer @var{i} specifies the value of a numeric attribute. @var{i}
3768 must be non-negative.
3770 The value of a numeric attribute can be specified either with a
3771 @code{const_int}, or as an integer represented as a string in
3772 @code{const_string}, @code{eq_attr} (see below), @code{attr},
3773 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
3774 overrides on specific instructions (@pxref{Tagging Insns}).
3776 @cindex @code{const_string} and attributes
3777 @item (const_string @var{value})
3778 The string @var{value} specifies a constant attribute value.
3779 If @var{value} is specified as @samp{"*"}, it means that the default value of
3780 the attribute is to be used for the insn containing this expression.
3781 @samp{"*"} obviously cannot be used in the @var{default} expression
3782 of a @code{define_attr}.@refill
3784 If the attribute whose value is being specified is numeric, @var{value}
3785 must be a string containing a non-negative integer (normally
3786 @code{const_int} would be used in this case). Otherwise, it must
3787 contain one of the valid values for the attribute.
3789 @cindex @code{if_then_else} and attributes
3790 @item (if_then_else @var{test} @var{true-value} @var{false-value})
3791 @var{test} specifies an attribute test, whose format is defined below.
3792 The value of this expression is @var{true-value} if @var{test} is true,
3793 otherwise it is @var{false-value}.
3795 @cindex @code{cond} and attributes
3796 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
3797 The first operand of this expression is a vector containing an even
3798 number of expressions and consisting of pairs of @var{test} and @var{value}
3799 expressions. The value of the @code{cond} expression is that of the
3800 @var{value} corresponding to the first true @var{test} expression. If
3801 none of the @var{test} expressions are true, the value of the @code{cond}
3802 expression is that of the @var{default} expression.
3805 @var{test} expressions can have one of the following forms:
3808 @cindex @code{const_int} and attribute tests
3809 @item (const_int @var{i})
3810 This test is true if @var{i} is non-zero and false otherwise.
3812 @cindex @code{not} and attributes
3813 @cindex @code{ior} and attributes
3814 @cindex @code{and} and attributes
3815 @item (not @var{test})
3816 @itemx (ior @var{test1} @var{test2})
3817 @itemx (and @var{test1} @var{test2})
3818 These tests are true if the indicated logical function is true.
3820 @cindex @code{match_operand} and attributes
3821 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
3822 This test is true if operand @var{n} of the insn whose attribute value
3823 is being determined has mode @var{m} (this part of the test is ignored
3824 if @var{m} is @code{VOIDmode}) and the function specified by the string
3825 @var{pred} returns a non-zero value when passed operand @var{n} and mode
3826 @var{m} (this part of the test is ignored if @var{pred} is the null
3829 The @var{constraints} operand is ignored and should be the null string.
3831 @cindex @code{le} and attributes
3832 @cindex @code{leu} and attributes
3833 @cindex @code{lt} and attributes
3834 @cindex @code{gt} and attributes
3835 @cindex @code{gtu} and attributes
3836 @cindex @code{ge} and attributes
3837 @cindex @code{geu} and attributes
3838 @cindex @code{ne} and attributes
3839 @cindex @code{eq} and attributes
3840 @cindex @code{plus} and attributes
3841 @cindex @code{minus} and attributes
3842 @cindex @code{mult} and attributes
3843 @cindex @code{div} and attributes
3844 @cindex @code{mod} and attributes
3845 @cindex @code{abs} and attributes
3846 @cindex @code{neg} and attributes
3847 @cindex @code{ashift} and attributes
3848 @cindex @code{lshiftrt} and attributes
3849 @cindex @code{ashiftrt} and attributes
3850 @item (le @var{arith1} @var{arith2})
3851 @itemx (leu @var{arith1} @var{arith2})
3852 @itemx (lt @var{arith1} @var{arith2})
3853 @itemx (ltu @var{arith1} @var{arith2})
3854 @itemx (gt @var{arith1} @var{arith2})
3855 @itemx (gtu @var{arith1} @var{arith2})
3856 @itemx (ge @var{arith1} @var{arith2})
3857 @itemx (geu @var{arith1} @var{arith2})
3858 @itemx (ne @var{arith1} @var{arith2})
3859 @itemx (eq @var{arith1} @var{arith2})
3860 These tests are true if the indicated comparison of the two arithmetic
3861 expressions is true. Arithmetic expressions are formed with
3862 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
3863 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
3864 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill
3867 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
3868 Lengths},for additional forms). @code{symbol_ref} is a string
3869 denoting a C expression that yields an @code{int} when evaluated by the
3870 @samp{get_attr_@dots{}} routine. It should normally be a global
3874 @item (eq_attr @var{name} @var{value})
3875 @var{name} is a string specifying the name of an attribute.
3877 @var{value} is a string that is either a valid value for attribute
3878 @var{name}, a comma-separated list of values, or @samp{!} followed by a
3879 value or list. If @var{value} does not begin with a @samp{!}, this
3880 test is true if the value of the @var{name} attribute of the current
3881 insn is in the list specified by @var{value}. If @var{value} begins
3882 with a @samp{!}, this test is true if the attribute's value is
3883 @emph{not} in the specified list.
3888 (eq_attr "type" "load,store")
3895 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
3898 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
3899 value of the compiler variable @code{which_alternative}
3900 (@pxref{Output Statement}) and the values must be small integers. For
3904 (eq_attr "alternative" "2,3")
3911 (ior (eq (symbol_ref "which_alternative") (const_int 2))
3912 (eq (symbol_ref "which_alternative") (const_int 3)))
3915 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
3916 where the value of the attribute being tested is known for all insns matching
3917 a particular pattern. This is by far the most common case.@refill
3920 @item (attr_flag @var{name})
3921 The value of an @code{attr_flag} expression is true if the flag
3922 specified by @var{name} is true for the @code{insn} currently being
3925 @var{name} is a string specifying one of a fixed set of flags to test.
3926 Test the flags @code{forward} and @code{backward} to determine the
3927 direction of a conditional branch. Test the flags @code{very_likely},
3928 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
3929 if a conditional branch is expected to be taken.
3931 If the @code{very_likely} flag is true, then the @code{likely} flag is also
3932 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
3934 This example describes a conditional branch delay slot which
3935 can be nullified for forward branches that are taken (annul-true) or
3936 for backward branches which are not taken (annul-false).
3939 (define_delay (eq_attr "type" "cbranch")
3940 [(eq_attr "in_branch_delay" "true")
3941 (and (eq_attr "in_branch_delay" "true")
3942 (attr_flag "forward"))
3943 (and (eq_attr "in_branch_delay" "true")
3944 (attr_flag "backward"))])
3947 The @code{forward} and @code{backward} flags are false if the current
3948 @code{insn} being scheduled is not a conditional branch.
3950 The @code{very_likely} and @code{likely} flags are true if the
3951 @code{insn} being scheduled is not a conditional branch.
3952 The @code{very_unlikely} and @code{unlikely} flags are false if the
3953 @code{insn} being scheduled is not a conditional branch.
3955 @code{attr_flag} is only used during delay slot scheduling and has no
3956 meaning to other passes of the compiler.
3959 @item (attr @var{name})
3960 The value of another attribute is returned. This is most useful
3961 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
3962 produce more efficient code for non-numeric attributes.
3966 @subsection Assigning Attribute Values to Insns
3967 @cindex tagging insns
3968 @cindex assigning attribute values to insns
3970 The value assigned to an attribute of an insn is primarily determined by
3971 which pattern is matched by that insn (or which @code{define_peephole}
3972 generated it). Every @code{define_insn} and @code{define_peephole} can
3973 have an optional last argument to specify the values of attributes for
3974 matching insns. The value of any attribute not specified in a particular
3975 insn is set to the default value for that attribute, as specified in its
3976 @code{define_attr}. Extensive use of default values for attributes
3977 permits the specification of the values for only one or two attributes
3978 in the definition of most insn patterns, as seen in the example in the
3979 next section.@refill
3981 The optional last argument of @code{define_insn} and
3982 @code{define_peephole} is a vector of expressions, each of which defines
3983 the value for a single attribute. The most general way of assigning an
3984 attribute's value is to use a @code{set} expression whose first operand is an
3985 @code{attr} expression giving the name of the attribute being set. The
3986 second operand of the @code{set} is an attribute expression
3987 (@pxref{Expressions}) giving the value of the attribute.@refill
3989 When the attribute value depends on the @samp{alternative} attribute
3990 (i.e., which is the applicable alternative in the constraint of the
3991 insn), the @code{set_attr_alternative} expression can be used. It
3992 allows the specification of a vector of attribute expressions, one for
3996 When the generality of arbitrary attribute expressions is not required,
3997 the simpler @code{set_attr} expression can be used, which allows
3998 specifying a string giving either a single attribute value or a list
3999 of attribute values, one for each alternative.
4001 The form of each of the above specifications is shown below. In each case,
4002 @var{name} is a string specifying the attribute to be set.
4005 @item (set_attr @var{name} @var{value-string})
4006 @var{value-string} is either a string giving the desired attribute value,
4007 or a string containing a comma-separated list giving the values for
4008 succeeding alternatives. The number of elements must match the number
4009 of alternatives in the constraint of the insn pattern.
4011 Note that it may be useful to specify @samp{*} for some alternative, in
4012 which case the attribute will assume its default value for insns matching
4015 @findex set_attr_alternative
4016 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
4017 Depending on the alternative of the insn, the value will be one of the
4018 specified values. This is a shorthand for using a @code{cond} with
4019 tests on the @samp{alternative} attribute.
4022 @item (set (attr @var{name}) @var{value})
4023 The first operand of this @code{set} must be the special RTL expression
4024 @code{attr}, whose sole operand is a string giving the name of the
4025 attribute being set. @var{value} is the value of the attribute.
4028 The following shows three different ways of representing the same
4029 attribute value specification:
4032 (set_attr "type" "load,store,arith")
4034 (set_attr_alternative "type"
4035 [(const_string "load") (const_string "store")
4036 (const_string "arith")])
4039 (cond [(eq_attr "alternative" "1") (const_string "load")
4040 (eq_attr "alternative" "2") (const_string "store")]
4041 (const_string "arith")))
4045 @findex define_asm_attributes
4046 The @code{define_asm_attributes} expression provides a mechanism to
4047 specify the attributes assigned to insns produced from an @code{asm}
4048 statement. It has the form:
4051 (define_asm_attributes [@var{attr-sets}])
4055 where @var{attr-sets} is specified the same as for both the
4056 @code{define_insn} and the @code{define_peephole} expressions.
4058 These values will typically be the ``worst case'' attribute values. For
4059 example, they might indicate that the condition code will be clobbered.
4061 A specification for a @code{length} attribute is handled specially. The
4062 way to compute the length of an @code{asm} insn is to multiply the
4063 length specified in the expression @code{define_asm_attributes} by the
4064 number of machine instructions specified in the @code{asm} statement,
4065 determined by counting the number of semicolons and newlines in the
4066 string. Therefore, the value of the @code{length} attribute specified
4067 in a @code{define_asm_attributes} should be the maximum possible length
4068 of a single machine instruction.
4071 @subsection Example of Attribute Specifications
4072 @cindex attribute specifications example
4073 @cindex attribute specifications
4075 The judicious use of defaulting is important in the efficient use of
4076 insn attributes. Typically, insns are divided into @dfn{types} and an
4077 attribute, customarily called @code{type}, is used to represent this
4078 value. This attribute is normally used only to define the default value
4079 for other attributes. An example will clarify this usage.
4081 Assume we have a RISC machine with a condition code and in which only
4082 full-word operations are performed in registers. Let us assume that we
4083 can divide all insns into loads, stores, (integer) arithmetic
4084 operations, floating point operations, and branches.
4086 Here we will concern ourselves with determining the effect of an insn on
4087 the condition code and will limit ourselves to the following possible
4088 effects: The condition code can be set unpredictably (clobbered), not
4089 be changed, be set to agree with the results of the operation, or only
4090 changed if the item previously set into the condition code has been
4093 Here is part of a sample @file{md} file for such a machine:
4096 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
4098 (define_attr "cc" "clobber,unchanged,set,change0"
4099 (cond [(eq_attr "type" "load")
4100 (const_string "change0")
4101 (eq_attr "type" "store,branch")
4102 (const_string "unchanged")
4103 (eq_attr "type" "arith")
4104 (if_then_else (match_operand:SI 0 "" "")
4105 (const_string "set")
4106 (const_string "clobber"))]
4107 (const_string "clobber")))
4110 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
4111 (match_operand:SI 1 "general_operand" "r,m,r"))]
4117 [(set_attr "type" "arith,load,store")])
4120 Note that we assume in the above example that arithmetic operations
4121 performed on quantities smaller than a machine word clobber the condition
4122 code since they will set the condition code to a value corresponding to the
4126 @subsection Computing the Length of an Insn
4127 @cindex insn lengths, computing
4128 @cindex computing the length of an insn
4130 For many machines, multiple types of branch instructions are provided, each
4131 for different length branch displacements. In most cases, the assembler
4132 will choose the correct instruction to use. However, when the assembler
4133 cannot do so, GCC can when a special attribute, the @samp{length}
4134 attribute, is defined. This attribute must be defined to have numeric
4135 values by specifying a null string in its @code{define_attr}.
4137 In the case of the @samp{length} attribute, two additional forms of
4138 arithmetic terms are allowed in test expressions:
4141 @cindex @code{match_dup} and attributes
4142 @item (match_dup @var{n})
4143 This refers to the address of operand @var{n} of the current insn, which
4144 must be a @code{label_ref}.
4146 @cindex @code{pc} and attributes
4148 This refers to the address of the @emph{current} insn. It might have
4149 been more consistent with other usage to make this the address of the
4150 @emph{next} insn but this would be confusing because the length of the
4151 current insn is to be computed.
4154 @cindex @code{addr_vec}, length of
4155 @cindex @code{addr_diff_vec}, length of
4156 For normal insns, the length will be determined by value of the
4157 @samp{length} attribute. In the case of @code{addr_vec} and
4158 @code{addr_diff_vec} insn patterns, the length is computed as
4159 the number of vectors multiplied by the size of each vector.
4161 Lengths are measured in addressable storage units (bytes).
4163 The following macros can be used to refine the length computation:
4166 @findex FIRST_INSN_ADDRESS
4167 @item FIRST_INSN_ADDRESS
4168 When the @code{length} insn attribute is used, this macro specifies the
4169 value to be assigned to the address of the first insn in a function. If
4170 not specified, 0 is used.
4172 @findex ADJUST_INSN_LENGTH
4173 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
4174 If defined, modifies the length assigned to instruction @var{insn} as a
4175 function of the context in which it is used. @var{length} is an lvalue
4176 that contains the initially computed length of the insn and should be
4177 updated with the correct length of the insn.
4179 This macro will normally not be required. A case in which it is
4180 required is the ROMP. On this machine, the size of an @code{addr_vec}
4181 insn must be increased by two to compensate for the fact that alignment
4185 @findex get_attr_length
4186 The routine that returns @code{get_attr_length} (the value of the
4187 @code{length} attribute) can be used by the output routine to
4188 determine the form of the branch instruction to be written, as the
4189 example below illustrates.
4191 As an example of the specification of variable-length branches, consider
4192 the IBM 360. If we adopt the convention that a register will be set to
4193 the starting address of a function, we can jump to labels within 4k of
4194 the start using a four-byte instruction. Otherwise, we need a six-byte
4195 sequence to load the address from memory and then branch to it.
4197 On such a machine, a pattern for a branch instruction might be specified
4203 (label_ref (match_operand 0 "" "")))]
4207 return (get_attr_length (insn) == 4
4208 ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
4210 [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
4215 @node Constant Attributes
4216 @subsection Constant Attributes
4217 @cindex constant attributes
4219 A special form of @code{define_attr}, where the expression for the
4220 default value is a @code{const} expression, indicates an attribute that
4221 is constant for a given run of the compiler. Constant attributes may be
4222 used to specify which variety of processor is used. For example,
4225 (define_attr "cpu" "m88100,m88110,m88000"
4227 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
4228 (symbol_ref "TARGET_88110") (const_string "m88110")]
4229 (const_string "m88000"))))
4231 (define_attr "memory" "fast,slow"
4233 (if_then_else (symbol_ref "TARGET_FAST_MEM")
4234 (const_string "fast")
4235 (const_string "slow"))))
4238 The routine generated for constant attributes has no parameters as it
4239 does not depend on any particular insn. RTL expressions used to define
4240 the value of a constant attribute may use the @code{symbol_ref} form,
4241 but may not use either the @code{match_operand} form or @code{eq_attr}
4242 forms involving insn attributes.
4245 @subsection Delay Slot Scheduling
4246 @cindex delay slots, defining
4248 The insn attribute mechanism can be used to specify the requirements for
4249 delay slots, if any, on a target machine. An instruction is said to
4250 require a @dfn{delay slot} if some instructions that are physically
4251 after the instruction are executed as if they were located before it.
4252 Classic examples are branch and call instructions, which often execute
4253 the following instruction before the branch or call is performed.
4255 On some machines, conditional branch instructions can optionally
4256 @dfn{annul} instructions in the delay slot. This means that the
4257 instruction will not be executed for certain branch outcomes. Both
4258 instructions that annul if the branch is true and instructions that
4259 annul if the branch is false are supported.
4261 Delay slot scheduling differs from instruction scheduling in that
4262 determining whether an instruction needs a delay slot is dependent only
4263 on the type of instruction being generated, not on data flow between the
4264 instructions. See the next section for a discussion of data-dependent
4265 instruction scheduling.
4267 @findex define_delay
4268 The requirement of an insn needing one or more delay slots is indicated
4269 via the @code{define_delay} expression. It has the following form:
4272 (define_delay @var{test}
4273 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
4274 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
4278 @var{test} is an attribute test that indicates whether this
4279 @code{define_delay} applies to a particular insn. If so, the number of
4280 required delay slots is determined by the length of the vector specified
4281 as the second argument. An insn placed in delay slot @var{n} must
4282 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
4283 attribute test that specifies which insns may be annulled if the branch
4284 is true. Similarly, @var{annul-false-n} specifies which insns in the
4285 delay slot may be annulled if the branch is false. If annulling is not
4286 supported for that delay slot, @code{(nil)} should be coded.@refill
4288 For example, in the common case where branch and call insns require
4289 a single delay slot, which may contain any insn other than a branch or
4290 call, the following would be placed in the @file{md} file:
4293 (define_delay (eq_attr "type" "branch,call")
4294 [(eq_attr "type" "!branch,call") (nil) (nil)])
4297 Multiple @code{define_delay} expressions may be specified. In this
4298 case, each such expression specifies different delay slot requirements
4299 and there must be no insn for which tests in two @code{define_delay}
4300 expressions are both true.
4302 For example, if we have a machine that requires one delay slot for branches
4303 but two for calls, no delay slot can contain a branch or call insn,
4304 and any valid insn in the delay slot for the branch can be annulled if the
4305 branch is true, we might represent this as follows:
4308 (define_delay (eq_attr "type" "branch")
4309 [(eq_attr "type" "!branch,call")
4310 (eq_attr "type" "!branch,call")
4313 (define_delay (eq_attr "type" "call")
4314 [(eq_attr "type" "!branch,call") (nil) (nil)
4315 (eq_attr "type" "!branch,call") (nil) (nil)])
4317 @c the above is *still* too long. --mew 4feb93
4319 @node Function Units
4320 @subsection Specifying Function Units
4321 @cindex function units, for scheduling
4323 On most RISC machines, there are instructions whose results are not
4324 available for a specific number of cycles. Common cases are instructions
4325 that load data from memory. On many machines, a pipeline stall will result
4326 if the data is referenced too soon after the load instruction.
4328 In addition, many newer microprocessors have multiple function units, usually
4329 one for integer and one for floating point, and often will incur pipeline
4330 stalls when a result that is needed is not yet ready.
4332 The descriptions in this section allow the specification of how much
4333 time must elapse between the execution of an instruction and the time
4334 when its result is used. It also allows specification of when the
4335 execution of an instruction will delay execution of similar instructions
4336 due to function unit conflicts.
4338 For the purposes of the specifications in this section, a machine is
4339 divided into @dfn{function units}, each of which execute a specific
4340 class of instructions in first-in-first-out order. Function units that
4341 accept one instruction each cycle and allow a result to be used in the
4342 succeeding instruction (usually via forwarding) need not be specified.
4343 Classic RISC microprocessors will normally have a single function unit,
4344 which we can call @samp{memory}. The newer ``superscalar'' processors
4345 will often have function units for floating point operations, usually at
4346 least a floating point adder and multiplier.
4348 @findex define_function_unit
4349 Each usage of a function units by a class of insns is specified with a
4350 @code{define_function_unit} expression, which looks like this:
4353 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4354 @var{test} @var{ready-delay} @var{issue-delay}
4355 [@var{conflict-list}])
4358 @var{name} is a string giving the name of the function unit.
4360 @var{multiplicity} is an integer specifying the number of identical
4361 units in the processor. If more than one unit is specified, they will
4362 be scheduled independently. Only truly independent units should be
4363 counted; a pipelined unit should be specified as a single unit. (The
4364 only common example of a machine that has multiple function units for a
4365 single instruction class that are truly independent and not pipelined
4366 are the two multiply and two increment units of the CDC 6600.)
4368 @var{simultaneity} specifies the maximum number of insns that can be
4369 executing in each instance of the function unit simultaneously or zero
4370 if the unit is pipelined and has no limit.
4372 All @code{define_function_unit} definitions referring to function unit
4373 @var{name} must have the same name and values for @var{multiplicity} and
4376 @var{test} is an attribute test that selects the insns we are describing
4377 in this definition. Note that an insn may use more than one function
4378 unit and a function unit may be specified in more than one
4379 @code{define_function_unit}.
4381 @var{ready-delay} is an integer that specifies the number of cycles
4382 after which the result of the instruction can be used without
4383 introducing any stalls.
4385 @var{issue-delay} is an integer that specifies the number of cycles
4386 after the instruction matching the @var{test} expression begins using
4387 this unit until a subsequent instruction can begin. A cost of @var{N}
4388 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4389 be delayed if an earlier instruction has a longer @var{ready-delay}
4390 value. This blocking effect is computed using the @var{simultaneity},
4391 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4392 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4393 unit is taken to block for the @var{ready-delay} cycles of the executing
4394 insn, and smaller values of @var{issue-delay} are ignored.
4396 @var{conflict-list} is an optional list giving detailed conflict costs
4397 for this unit. If specified, it is a list of condition test expressions
4398 to be applied to insns chosen to execute in @var{name} following the
4399 particular insn matching @var{test} that is already executing in
4400 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4401 conflict cost; for insns not in the list, the cost is zero. If not
4402 specified, @var{conflict-list} defaults to all instructions that use the
4405 Typical uses of this vector are where a floating point function unit can
4406 pipeline either single- or double-precision operations, but not both, or
4407 where a memory unit can pipeline loads, but not stores, etc.
4409 As an example, consider a classic RISC machine where the result of a
4410 load instruction is not available for two cycles (a single ``delay''
4411 instruction is required) and where only one load instruction can be executed
4412 simultaneously. This would be specified as:
4415 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4418 For the case of a floating point function unit that can pipeline either
4419 single or double precision, but not both, the following could be specified:
4422 (define_function_unit
4423 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4424 (define_function_unit
4425 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4428 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4429 and uses all the specifications in the @code{define_function_unit}
4430 expression. It has recently come to our attention that these
4431 specifications may not allow modeling of some of the newer
4432 ``superscalar'' processors that have insns using multiple pipelined
4433 units. These insns will cause a potential conflict for the second unit
4434 used during their execution and there is no way of representing that
4435 conflict. We welcome any examples of how function unit conflicts work
4436 in such processors and suggestions for their representation.