1 @c Copyright (C) 1988, 89, 92, 93, 94, 96, 1998, 2000 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Constraints:: When not all operands are general operands.
31 * Standard Names:: Names mark patterns to use for code generation.
32 * Pattern Ordering:: When the order of patterns makes a difference.
33 * Dependent Patterns:: Having one pattern may make you need another.
34 * Jump Patterns:: Special considerations for patterns for jump insns.
35 * Insn Canonicalizations::Canonicalization of Instructions
36 * Expander Definitions::Generating a sequence of several RTL insns
37 for a standard operation.
38 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
39 * Peephole Definitions::Defining machine-specific peephole optimizations.
40 * Insn Attributes:: Specifying the value of attributes for generated insns.
41 * Conditional Execution::Generating @code{define_insn} patterns for
43 * Constant Definitions::Defining symbolic constants that can be used in the
48 @section Overview of How the Machine Description is Used
50 There are three main conversions that happen in the compiler:
55 The front end reads the source code and builds a parse tree.
58 The parse tree is used to generate an RTL insn list based on named
62 The insn list is matched against the RTL templates to produce assembler
67 For the generate pass, only the names of the insns matter, from either a
68 named @code{define_insn} or a @code{define_expand}. The compiler will
69 choose the pattern with the right name and apply the operands according
70 to the documentation later in this chapter, without regard for the RTL
71 template or operand constraints. Note that the names the compiler looks
72 for are hard-coded in the compiler - it will ignore unnamed patterns and
73 patterns with names it doesn't know about, but if you don't provide a
74 named pattern it needs, it will abort.
76 If a @code{define_insn} is used, the template given is inserted into the
77 insn list. If a @code{define_expand} is used, one of three things
78 happens, based on the condition logic. The condition logic may manually
79 create new insns for the insn list, say via @code{emit_insn()}, and
80 invoke DONE. For certain named patterns, it may invoke FAIL to tell the
81 compiler to use an alternate way of performing that task. If it invokes
82 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
83 is inserted, as if the @code{define_expand} were a @code{define_insn}.
85 Once the insn list is generated, various optimization passes convert,
86 replace, and rearrange the insns in the insn list. This is where the
87 @code{define_split} and @code{define_peephole} patterns get used, for
90 Finally, the insn list's RTL is matched up with the RTL templates in the
91 @code{define_insn} patterns, and those patterns are used to emit the
92 final assembly code. For this purpose, each named @code{define_insn}
93 acts like it's unnamed, since the names are ignored.
96 @section Everything about Instruction Patterns
98 @cindex instruction patterns
101 Each instruction pattern contains an incomplete RTL expression, with pieces
102 to be filled in later, operand constraints that restrict how the pieces can
103 be filled in, and an output pattern or C code to generate the assembler
104 output, all wrapped up in a @code{define_insn} expression.
106 A @code{define_insn} is an RTL expression containing four or five operands:
110 An optional name. The presence of a name indicate that this instruction
111 pattern can perform a certain standard job for the RTL-generation
112 pass of the compiler. This pass knows certain names and will use
113 the instruction patterns with those names, if the names are defined
114 in the machine description.
116 The absence of a name is indicated by writing an empty string
117 where the name should go. Nameless instruction patterns are never
118 used for generating RTL code, but they may permit several simpler insns
119 to be combined later on.
121 Names that are not thus known and used in RTL-generation have no
122 effect; they are equivalent to no name at all.
124 For the purpose of debugging the compiler, you may also specify a
125 name beginning with the @samp{*} character. Such a name is used only
126 for identifying the instruction in RTL dumps; it is entirely equivalent
127 to having a nameless pattern for all other purposes.
130 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
131 RTL expressions which show what the instruction should look like. It is
132 incomplete because it may contain @code{match_operand},
133 @code{match_operator}, and @code{match_dup} expressions that stand for
134 operands of the instruction.
136 If the vector has only one element, that element is the template for the
137 instruction pattern. If the vector has multiple elements, then the
138 instruction pattern is a @code{parallel} expression containing the
142 @cindex pattern conditions
143 @cindex conditions, in patterns
144 A condition. This is a string which contains a C expression that is
145 the final test to decide whether an insn body matches this pattern.
147 @cindex named patterns and conditions
148 For a named pattern, the condition (if present) may not depend on
149 the data in the insn being matched, but only the target-machine-type
150 flags. The compiler needs to test these conditions during
151 initialization in order to learn exactly which named instructions are
152 available in a particular run.
155 For nameless patterns, the condition is applied only when matching an
156 individual insn, and only after the insn has matched the pattern's
157 recognition template. The insn's operands may be found in the vector
161 The @dfn{output template}: a string that says how to output matching
162 insns as assembler code. @samp{%} in this string specifies where
163 to substitute the value of an operand. @xref{Output Template}.
165 When simple substitution isn't general enough, you can specify a piece
166 of C code to compute the output. @xref{Output Statement}.
169 Optionally, a vector containing the values of attributes for insns matching
170 this pattern. @xref{Insn Attributes}.
174 @section Example of @code{define_insn}
175 @cindex @code{define_insn} example
177 Here is an actual example of an instruction pattern, for the 68000/68020.
182 (match_operand:SI 0 "general_operand" "rm"))]
185 @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
187 return \"cmpl #0,%0\"; @}")
190 This is an instruction that sets the condition codes based on the value of
191 a general operand. It has no condition, so any insn whose RTL description
192 has the form shown may be handled according to this pattern. The name
193 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
194 pass that, when it is necessary to test such a value, an insn to do so
195 can be constructed using this pattern.
197 The output control string is a piece of C code which chooses which
198 output template to return based on the kind of operand and the specific
199 type of CPU for which code is being generated.
201 @samp{"rm"} is an operand constraint. Its meaning is explained below.
204 @section RTL Template
205 @cindex RTL insn template
206 @cindex generating insns
207 @cindex insns, generating
208 @cindex recognizing insns
209 @cindex insns, recognizing
211 The RTL template is used to define which insns match the particular pattern
212 and how to find their operands. For named patterns, the RTL template also
213 says how to construct an insn from specified operands.
215 Construction involves substituting specified operands into a copy of the
216 template. Matching involves determining the values that serve as the
217 operands in the insn being matched. Both of these activities are
218 controlled by special expression types that direct matching and
219 substitution of the operands.
222 @findex match_operand
223 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
224 This expression is a placeholder for operand number @var{n} of
225 the insn. When constructing an insn, operand number @var{n}
226 will be substituted at this point. When matching an insn, whatever
227 appears at this position in the insn will be taken as operand
228 number @var{n}; but it must satisfy @var{predicate} or this instruction
229 pattern will not match at all.
231 Operand numbers must be chosen consecutively counting from zero in
232 each instruction pattern. There may be only one @code{match_operand}
233 expression in the pattern for each operand number. Usually operands
234 are numbered in the order of appearance in @code{match_operand}
235 expressions. In the case of a @code{define_expand}, any operand numbers
236 used only in @code{match_dup} expressions have higher values than all
237 other operand numbers.
239 @var{predicate} is a string that is the name of a C function that accepts two
240 arguments, an expression and a machine mode. During matching, the
241 function will be called with the putative operand as the expression and
242 @var{m} as the mode argument (if @var{m} is not specified,
243 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
244 any mode). If it returns zero, this instruction pattern fails to match.
245 @var{predicate} may be an empty string; then it means no test is to be done
246 on the operand, so anything which occurs in this position is valid.
248 Most of the time, @var{predicate} will reject modes other than @var{m}---but
249 not always. For example, the predicate @code{address_operand} uses
250 @var{m} as the mode of memory ref that the address should be valid for.
251 Many predicates accept @code{const_int} nodes even though their mode is
254 @var{constraint} controls reloading and the choice of the best register
255 class to use for a value, as explained later (@pxref{Constraints}).
257 People are often unclear on the difference between the constraint and the
258 predicate. The predicate helps decide whether a given insn matches the
259 pattern. The constraint plays no role in this decision; instead, it
260 controls various decisions in the case of an insn which does match.
262 @findex general_operand
263 On CISC machines, the most common @var{predicate} is
264 @code{"general_operand"}. This function checks that the putative
265 operand is either a constant, a register or a memory reference, and that
266 it is valid for mode @var{m}.
268 @findex register_operand
269 For an operand that must be a register, @var{predicate} should be
270 @code{"register_operand"}. Using @code{"general_operand"} would be
271 valid, since the reload pass would copy any non-register operands
272 through registers, but this would make GNU CC do extra work, it would
273 prevent invariant operands (such as constant) from being removed from
274 loops, and it would prevent the register allocator from doing the best
275 possible job. On RISC machines, it is usually most efficient to allow
276 @var{predicate} to accept only objects that the constraints allow.
278 @findex immediate_operand
279 For an operand that must be a constant, you must be sure to either use
280 @code{"immediate_operand"} for @var{predicate}, or make the instruction
281 pattern's extra condition require a constant, or both. You cannot
282 expect the constraints to do this work! If the constraints allow only
283 constants, but the predicate allows something else, the compiler will
284 crash when that case arises.
286 @findex match_scratch
287 @item (match_scratch:@var{m} @var{n} @var{constraint})
288 This expression is also a placeholder for operand number @var{n}
289 and indicates that operand must be a @code{scratch} or @code{reg}
292 When matching patterns, this is equivalent to
295 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
298 but, when generating RTL, it produces a (@code{scratch}:@var{m})
301 If the last few expressions in a @code{parallel} are @code{clobber}
302 expressions whose operands are either a hard register or
303 @code{match_scratch}, the combiner can add or delete them when
304 necessary. @xref{Side Effects}.
307 @item (match_dup @var{n})
308 This expression is also a placeholder for operand number @var{n}.
309 It is used when the operand needs to appear more than once in the
312 In construction, @code{match_dup} acts just like @code{match_operand}:
313 the operand is substituted into the insn being constructed. But in
314 matching, @code{match_dup} behaves differently. It assumes that operand
315 number @var{n} has already been determined by a @code{match_operand}
316 appearing earlier in the recognition template, and it matches only an
317 identical-looking expression.
319 Note that @code{match_dup} should not be used to tell the compiler that
320 a particular register is being used for two operands (example:
321 @code{add} that adds one register to another; the second register is
322 both an input operand and the output operand). Use a matching
323 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
324 operand is used in two places in the template, such as an instruction
325 that computes both a quotient and a remainder, where the opcode takes
326 two input operands but the RTL template has to refer to each of those
327 twice; once for the quotient pattern and once for the remainder pattern.
329 @findex match_operator
330 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
331 This pattern is a kind of placeholder for a variable RTL expression
334 When constructing an insn, it stands for an RTL expression whose
335 expression code is taken from that of operand @var{n}, and whose
336 operands are constructed from the patterns @var{operands}.
338 When matching an expression, it matches an expression if the function
339 @var{predicate} returns nonzero on that expression @emph{and} the
340 patterns @var{operands} match the operands of the expression.
342 Suppose that the function @code{commutative_operator} is defined as
343 follows, to match any expression whose operator is one of the
344 commutative arithmetic operators of RTL and whose mode is @var{mode}:
348 commutative_operator (x, mode)
350 enum machine_mode mode;
352 enum rtx_code code = GET_CODE (x);
353 if (GET_MODE (x) != mode)
355 return (GET_RTX_CLASS (code) == 'c'
356 || code == EQ || code == NE);
360 Then the following pattern will match any RTL expression consisting
361 of a commutative operator applied to two general operands:
364 (match_operator:SI 3 "commutative_operator"
365 [(match_operand:SI 1 "general_operand" "g")
366 (match_operand:SI 2 "general_operand" "g")])
369 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
370 because the expressions to be matched all contain two operands.
372 When this pattern does match, the two operands of the commutative
373 operator are recorded as operands 1 and 2 of the insn. (This is done
374 by the two instances of @code{match_operand}.) Operand 3 of the insn
375 will be the entire commutative expression: use @code{GET_CODE
376 (operands[3])} to see which commutative operator was used.
378 The machine mode @var{m} of @code{match_operator} works like that of
379 @code{match_operand}: it is passed as the second argument to the
380 predicate function, and that function is solely responsible for
381 deciding whether the expression to be matched ``has'' that mode.
383 When constructing an insn, argument 3 of the gen-function will specify
384 the operation (i.e. the expression code) for the expression to be
385 made. It should be an RTL expression, whose expression code is copied
386 into a new expression whose operands are arguments 1 and 2 of the
387 gen-function. The subexpressions of argument 3 are not used;
388 only its expression code matters.
390 When @code{match_operator} is used in a pattern for matching an insn,
391 it usually best if the operand number of the @code{match_operator}
392 is higher than that of the actual operands of the insn. This improves
393 register allocation because the register allocator often looks at
394 operands 1 and 2 of insns to see if it can do register tying.
396 There is no way to specify constraints in @code{match_operator}. The
397 operand of the insn which corresponds to the @code{match_operator}
398 never has any constraints because it is never reloaded as a whole.
399 However, if parts of its @var{operands} are matched by
400 @code{match_operand} patterns, those parts may have constraints of
404 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
405 Like @code{match_dup}, except that it applies to operators instead of
406 operands. When constructing an insn, operand number @var{n} will be
407 substituted at this point. But in matching, @code{match_op_dup} behaves
408 differently. It assumes that operand number @var{n} has already been
409 determined by a @code{match_operator} appearing earlier in the
410 recognition template, and it matches only an identical-looking
413 @findex match_parallel
414 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
415 This pattern is a placeholder for an insn that consists of a
416 @code{parallel} expression with a variable number of elements. This
417 expression should only appear at the top level of an insn pattern.
419 When constructing an insn, operand number @var{n} will be substituted at
420 this point. When matching an insn, it matches if the body of the insn
421 is a @code{parallel} expression with at least as many elements as the
422 vector of @var{subpat} expressions in the @code{match_parallel}, if each
423 @var{subpat} matches the corresponding element of the @code{parallel},
424 @emph{and} the function @var{predicate} returns nonzero on the
425 @code{parallel} that is the body of the insn. It is the responsibility
426 of the predicate to validate elements of the @code{parallel} beyond
427 those listed in the @code{match_parallel}.@refill
429 A typical use of @code{match_parallel} is to match load and store
430 multiple expressions, which can contain a variable number of elements
431 in a @code{parallel}. For example,
432 @c the following is *still* going over. need to change the code.
433 @c also need to work on grouping of this example. --mew 1feb93
437 [(match_parallel 0 "load_multiple_operation"
438 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
439 (match_operand:SI 2 "memory_operand" "m"))
441 (clobber (reg:SI 179))])]
446 This example comes from @file{a29k.md}. The function
447 @code{load_multiple_operations} is defined in @file{a29k.c} and checks
448 that subsequent elements in the @code{parallel} are the same as the
449 @code{set} in the pattern, except that they are referencing subsequent
450 registers and memory locations.
452 An insn that matches this pattern might look like:
456 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
458 (clobber (reg:SI 179))
460 (mem:SI (plus:SI (reg:SI 100)
463 (mem:SI (plus:SI (reg:SI 100)
467 @findex match_par_dup
468 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
469 Like @code{match_op_dup}, but for @code{match_parallel} instead of
470 @code{match_operator}.
473 @item (match_insn @var{predicate})
474 Match a complete insn. Unlike the other @code{match_*} recognizers,
475 @code{match_insn} does not take an operand number.
477 The machine mode @var{m} of @code{match_insn} works like that of
478 @code{match_operand}: it is passed as the second argument to the
479 predicate function, and that function is solely responsible for
480 deciding whether the expression to be matched ``has'' that mode.
483 @item (match_insn2 @var{n} @var{predicate})
484 Match a complete insn.
486 The machine mode @var{m} of @code{match_insn2} works like that of
487 @code{match_operand}: it is passed as the second argument to the
488 predicate function, and that function is solely responsible for
489 deciding whether the expression to be matched ``has'' that mode.
493 @node Output Template
494 @section Output Templates and Operand Substitution
495 @cindex output templates
496 @cindex operand substitution
498 @cindex @samp{%} in template
500 The @dfn{output template} is a string which specifies how to output the
501 assembler code for an instruction pattern. Most of the template is a
502 fixed string which is output literally. The character @samp{%} is used
503 to specify where to substitute an operand; it can also be used to
504 identify places where different variants of the assembler require
507 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
508 operand @var{n} at that point in the string.
510 @samp{%} followed by a letter and a digit says to output an operand in an
511 alternate fashion. Four letters have standard, built-in meanings described
512 below. The machine description macro @code{PRINT_OPERAND} can define
513 additional letters with nonstandard meanings.
515 @samp{%c@var{digit}} can be used to substitute an operand that is a
516 constant value without the syntax that normally indicates an immediate
519 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
520 the constant is negated before printing.
522 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
523 memory reference, with the actual operand treated as the address. This may
524 be useful when outputting a ``load address'' instruction, because often the
525 assembler syntax for such an instruction requires you to write the operand
526 as if it were a memory reference.
528 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
531 @samp{%=} outputs a number which is unique to each instruction in the
532 entire compilation. This is useful for making local labels to be
533 referred to more than once in a single template that generates multiple
534 assembler instructions.
536 @samp{%} followed by a punctuation character specifies a substitution that
537 does not use an operand. Only one case is standard: @samp{%%} outputs a
538 @samp{%} into the assembler code. Other nonstandard cases can be
539 defined in the @code{PRINT_OPERAND} macro. You must also define
540 which punctuation characters are valid with the
541 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
545 The template may generate multiple assembler instructions. Write the text
546 for the instructions, with @samp{\;} between them.
548 @cindex matching operands
549 When the RTL contains two operands which are required by constraint to match
550 each other, the output template must refer only to the lower-numbered operand.
551 Matching operands are not always identical, and the rest of the compiler
552 arranges to put the proper RTL expression for printing into the lower-numbered
555 One use of nonstandard letters or punctuation following @samp{%} is to
556 distinguish between different assembler languages for the same machine; for
557 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
558 requires periods in most opcode names, while MIT syntax does not. For
559 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
560 syntax. The same file of patterns is used for both kinds of output syntax,
561 but the character sequence @samp{%.} is used in each place where Motorola
562 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
563 defines the sequence to output a period; the macro for MIT syntax defines
566 @cindex @code{#} in template
567 As a special case, a template consisting of the single character @code{#}
568 instructs the compiler to first split the insn, and then output the
569 resulting instructions separately. This helps eliminate redundancy in the
570 output templates. If you have a @code{define_insn} that needs to emit
571 multiple assembler instructions, and there is an matching @code{define_split}
572 already defined, then you can simply use @code{#} as the output template
573 instead of writing an output template that emits the multiple assembler
576 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
577 of the form @samp{@{option0|option1|option2@}} in the templates. These
578 describe multiple variants of assembler language syntax.
579 @xref{Instruction Output}.
581 @node Output Statement
582 @section C Statements for Assembler Output
583 @cindex output statements
584 @cindex C statements for assembler output
585 @cindex generating assembler output
587 Often a single fixed template string cannot produce correct and efficient
588 assembler code for all the cases that are recognized by a single
589 instruction pattern. For example, the opcodes may depend on the kinds of
590 operands; or some unfortunate combinations of operands may require extra
591 machine instructions.
593 If the output control string starts with a @samp{@@}, then it is actually
594 a series of templates, each on a separate line. (Blank lines and
595 leading spaces and tabs are ignored.) The templates correspond to the
596 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
597 if a target machine has a two-address add instruction @samp{addr} to add
598 into a register and another @samp{addm} to add a register to memory, you
599 might write this pattern:
602 (define_insn "addsi3"
603 [(set (match_operand:SI 0 "general_operand" "=r,m")
604 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
605 (match_operand:SI 2 "general_operand" "g,r")))]
612 @cindex @code{*} in template
613 @cindex asterisk in template
614 If the output control string starts with a @samp{*}, then it is not an
615 output template but rather a piece of C program that should compute a
616 template. It should execute a @code{return} statement to return the
617 template-string you want. Most such templates use C string literals, which
618 require doublequote characters to delimit them. To include these
619 doublequote characters in the string, prefix each one with @samp{\}.
621 The operands may be found in the array @code{operands}, whose C data type
624 It is very common to select different ways of generating assembler code
625 based on whether an immediate operand is within a certain range. Be
626 careful when doing this, because the result of @code{INTVAL} is an
627 integer on the host machine. If the host machine has more bits in an
628 @code{int} than the target machine has in the mode in which the constant
629 will be used, then some of the bits you get from @code{INTVAL} will be
630 superfluous. For proper results, you must carefully disregard the
631 values of those bits.
633 @findex output_asm_insn
634 It is possible to output an assembler instruction and then go on to output
635 or compute more of them, using the subroutine @code{output_asm_insn}. This
636 receives two arguments: a template-string and a vector of operands. The
637 vector may be @code{operands}, or it may be another array of @code{rtx}
638 that you declare locally and initialize yourself.
640 @findex which_alternative
641 When an insn pattern has multiple alternatives in its constraints, often
642 the appearance of the assembler code is determined mostly by which alternative
643 was matched. When this is so, the C code can test the variable
644 @code{which_alternative}, which is the ordinal number of the alternative
645 that was actually satisfied (0 for the first, 1 for the second alternative,
648 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
649 for registers and @samp{clrmem} for memory locations. Here is how
650 a pattern could use @code{which_alternative} to choose between them:
654 [(set (match_operand:SI 0 "general_operand" "=r,m")
658 return (which_alternative == 0
659 ? \"clrreg %0\" : \"clrmem %0\");
663 The example above, where the assembler code to generate was
664 @emph{solely} determined by the alternative, could also have been specified
665 as follows, having the output control string start with a @samp{@@}:
670 [(set (match_operand:SI 0 "general_operand" "=r,m")
680 @c Most of this node appears by itself (in a different place) even
681 @c when the INTERNALS flag is clear. Passages that require the full
682 @c manual's context are conditionalized to appear only in the full manual.
685 @section Operand Constraints
686 @cindex operand constraints
689 Each @code{match_operand} in an instruction pattern can specify a
690 constraint for the type of operands allowed.
694 @section Constraints for @code{asm} Operands
695 @cindex operand constraints, @code{asm}
696 @cindex constraints, @code{asm}
697 @cindex @code{asm} constraints
699 Here are specific details on what constraint letters you can use with
702 Constraints can say whether
703 an operand may be in a register, and which kinds of register; whether the
704 operand can be a memory reference, and which kinds of address; whether the
705 operand may be an immediate constant, and which possible values it may
706 have. Constraints can also require two operands to match.
710 * Simple Constraints:: Basic use of constraints.
711 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
712 * Class Preferences:: Constraints guide which hard register to put things in.
713 * Modifiers:: More precise control over effects of constraints.
714 * Machine Constraints:: Existing constraints for some particular machines.
720 * Simple Constraints:: Basic use of constraints.
721 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
722 * Modifiers:: More precise control over effects of constraints.
723 * Machine Constraints:: Special constraints for some particular machines.
727 @node Simple Constraints
728 @subsection Simple Constraints
729 @cindex simple constraints
731 The simplest kind of constraint is a string full of letters, each of
732 which describes one kind of operand that is permitted. Here are
733 the letters that are allowed:
737 Whitespace characters are ignored and can be inserted at any position
738 except the first. This enables each alternative for different operands to
739 be visually aligned in the machine description even if they have different
740 number of constraints and modifiers.
742 @cindex @samp{m} in constraint
743 @cindex memory references in constraints
745 A memory operand is allowed, with any kind of address that the machine
748 @cindex offsettable address
749 @cindex @samp{o} in constraint
751 A memory operand is allowed, but only if the address is
752 @dfn{offsettable}. This means that adding a small integer (actually,
753 the width in bytes of the operand, as determined by its machine mode)
754 may be added to the address and the result is also a valid memory
757 @cindex autoincrement/decrement addressing
758 For example, an address which is constant is offsettable; so is an
759 address that is the sum of a register and a constant (as long as a
760 slightly larger constant is also within the range of address-offsets
761 supported by the machine); but an autoincrement or autodecrement
762 address is not offsettable. More complicated indirect/indexed
763 addresses may or may not be offsettable depending on the other
764 addressing modes that the machine supports.
766 Note that in an output operand which can be matched by another
767 operand, the constraint letter @samp{o} is valid only when accompanied
768 by both @samp{<} (if the target machine has predecrement addressing)
769 and @samp{>} (if the target machine has preincrement addressing).
771 @cindex @samp{V} in constraint
773 A memory operand that is not offsettable. In other words, anything that
774 would fit the @samp{m} constraint but not the @samp{o} constraint.
776 @cindex @samp{<} in constraint
778 A memory operand with autodecrement addressing (either predecrement or
779 postdecrement) is allowed.
781 @cindex @samp{>} in constraint
783 A memory operand with autoincrement addressing (either preincrement or
784 postincrement) is allowed.
786 @cindex @samp{r} in constraint
787 @cindex registers in constraints
789 A register operand is allowed provided that it is in a general
792 @cindex constants in constraints
793 @cindex @samp{i} in constraint
795 An immediate integer operand (one with constant value) is allowed.
796 This includes symbolic constants whose values will be known only at
799 @cindex @samp{n} in constraint
801 An immediate integer operand with a known numeric value is allowed.
802 Many systems cannot support assembly-time constants for operands less
803 than a word wide. Constraints for these operands should use @samp{n}
804 rather than @samp{i}.
806 @cindex @samp{I} in constraint
807 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
808 Other letters in the range @samp{I} through @samp{P} may be defined in
809 a machine-dependent fashion to permit immediate integer operands with
810 explicit integer values in specified ranges. For example, on the
811 68000, @samp{I} is defined to stand for the range of values 1 to 8.
812 This is the range permitted as a shift count in the shift
815 @cindex @samp{E} in constraint
817 An immediate floating operand (expression code @code{const_double}) is
818 allowed, but only if the target floating point format is the same as
819 that of the host machine (on which the compiler is running).
821 @cindex @samp{F} in constraint
823 An immediate floating operand (expression code @code{const_double}) is
826 @cindex @samp{G} in constraint
827 @cindex @samp{H} in constraint
828 @item @samp{G}, @samp{H}
829 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
830 permit immediate floating operands in particular ranges of values.
832 @cindex @samp{s} in constraint
834 An immediate integer operand whose value is not an explicit integer is
837 This might appear strange; if an insn allows a constant operand with a
838 value not known at compile time, it certainly must allow any known
839 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
840 better code to be generated.
842 For example, on the 68000 in a fullword instruction it is possible to
843 use an immediate operand; but if the immediate value is between -128
844 and 127, better code results from loading the value into a register and
845 using the register. This is because the load into the register can be
846 done with a @samp{moveq} instruction. We arrange for this to happen
847 by defining the letter @samp{K} to mean ``any integer outside the
848 range -128 to 127'', and then specifying @samp{Ks} in the operand
851 @cindex @samp{g} in constraint
853 Any register, memory or immediate integer operand is allowed, except for
854 registers that are not general registers.
856 @cindex @samp{X} in constraint
859 Any operand whatsoever is allowed, even if it does not satisfy
860 @code{general_operand}. This is normally used in the constraint of
861 a @code{match_scratch} when certain alternatives will not actually
862 require a scratch register.
865 Any operand whatsoever is allowed.
868 @cindex @samp{0} in constraint
869 @cindex digits in constraint
870 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
871 An operand that matches the specified operand number is allowed. If a
872 digit is used together with letters within the same alternative, the
873 digit should come last.
875 @cindex matching constraint
876 @cindex constraint, matching
877 This is called a @dfn{matching constraint} and what it really means is
878 that the assembler has only a single operand that fills two roles
880 considered separate in the RTL insn. For example, an add insn has two
881 input operands and one output operand in the RTL, but on most CISC
884 which @code{asm} distinguishes. For example, an add instruction uses
885 two input operands and an output operand, but on most CISC
887 machines an add instruction really has only two operands, one of them an
888 input-output operand:
894 Matching constraints are used in these circumstances.
895 More precisely, the two operands that match must include one input-only
896 operand and one output-only operand. Moreover, the digit must be a
897 smaller number than the number of the operand that uses it in the
901 For operands to match in a particular case usually means that they
902 are identical-looking RTL expressions. But in a few special cases
903 specific kinds of dissimilarity are allowed. For example, @code{*x}
904 as an input operand will match @code{*x++} as an output operand.
905 For proper results in such cases, the output template should always
906 use the output-operand's number when printing the operand.
909 @cindex load address instruction
910 @cindex push address instruction
911 @cindex address constraints
912 @cindex @samp{p} in constraint
914 An operand that is a valid memory address is allowed. This is
915 for ``load address'' and ``push address'' instructions.
917 @findex address_operand
918 @samp{p} in the constraint must be accompanied by @code{address_operand}
919 as the predicate in the @code{match_operand}. This predicate interprets
920 the mode specified in the @code{match_operand} as the mode of the memory
921 reference for which the address would be valid.
923 @cindex other register constraints
924 @cindex extensible constraints
925 @item @var{other letters}
926 Other letters can be defined in machine-dependent fashion to stand for
927 particular classes of registers or other arbitrary operand types.
928 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
929 for data, address and floating point registers.
932 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
933 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
934 then @code{EXTRA_CONSTRAINT} is evaluated.
936 A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain
937 types of memory references that affect other insn operands.
942 In order to have valid assembler code, each operand must satisfy
943 its constraint. But a failure to do so does not prevent the pattern
944 from applying to an insn. Instead, it directs the compiler to modify
945 the code so that the constraint will be satisfied. Usually this is
946 done by copying an operand into a register.
948 Contrast, therefore, the two instruction patterns that follow:
952 [(set (match_operand:SI 0 "general_operand" "=r")
953 (plus:SI (match_dup 0)
954 (match_operand:SI 1 "general_operand" "r")))]
960 which has two operands, one of which must appear in two places, and
964 [(set (match_operand:SI 0 "general_operand" "=r")
965 (plus:SI (match_operand:SI 1 "general_operand" "0")
966 (match_operand:SI 2 "general_operand" "r")))]
972 which has three operands, two of which are required by a constraint to be
973 identical. If we are considering an insn of the form
976 (insn @var{n} @var{prev} @var{next}
978 (plus:SI (reg:SI 6) (reg:SI 109)))
983 the first pattern would not apply at all, because this insn does not
984 contain two identical subexpressions in the right place. The pattern would
985 say, ``That does not look like an add instruction; try other patterns.''
986 The second pattern would say, ``Yes, that's an add instruction, but there
987 is something wrong with it.'' It would direct the reload pass of the
988 compiler to generate additional insns to make the constraint true. The
989 results might look like this:
992 (insn @var{n2} @var{prev} @var{n}
993 (set (reg:SI 3) (reg:SI 6))
996 (insn @var{n} @var{n2} @var{next}
998 (plus:SI (reg:SI 3) (reg:SI 109)))
1002 It is up to you to make sure that each operand, in each pattern, has
1003 constraints that can handle any RTL expression that could be present for
1004 that operand. (When multiple alternatives are in use, each pattern must,
1005 for each possible combination of operand expressions, have at least one
1006 alternative which can handle that combination of operands.) The
1007 constraints don't need to @emph{allow} any possible operand---when this is
1008 the case, they do not constrain---but they must at least point the way to
1009 reloading any possible operand so that it will fit.
1013 If the constraint accepts whatever operands the predicate permits,
1014 there is no problem: reloading is never necessary for this operand.
1016 For example, an operand whose constraints permit everything except
1017 registers is safe provided its predicate rejects registers.
1019 An operand whose predicate accepts only constant values is safe
1020 provided its constraints include the letter @samp{i}. If any possible
1021 constant value is accepted, then nothing less than @samp{i} will do;
1022 if the predicate is more selective, then the constraints may also be
1026 Any operand expression can be reloaded by copying it into a register.
1027 So if an operand's constraints allow some kind of register, it is
1028 certain to be safe. It need not permit all classes of registers; the
1029 compiler knows how to copy a register into another register of the
1030 proper class in order to make an instruction valid.
1032 @cindex nonoffsettable memory reference
1033 @cindex memory reference, nonoffsettable
1035 A nonoffsettable memory reference can be reloaded by copying the
1036 address into a register. So if the constraint uses the letter
1037 @samp{o}, all memory references are taken care of.
1040 A constant operand can be reloaded by allocating space in memory to
1041 hold it as preinitialized data. Then the memory reference can be used
1042 in place of the constant. So if the constraint uses the letters
1043 @samp{o} or @samp{m}, constant operands are not a problem.
1046 If the constraint permits a constant and a pseudo register used in an insn
1047 was not allocated to a hard register and is equivalent to a constant,
1048 the register will be replaced with the constant. If the predicate does
1049 not permit a constant and the insn is re-recognized for some reason, the
1050 compiler will crash. Thus the predicate must always recognize any
1051 objects allowed by the constraint.
1054 If the operand's predicate can recognize registers, but the constraint does
1055 not permit them, it can make the compiler crash. When this operand happens
1056 to be a register, the reload pass will be stymied, because it does not know
1057 how to copy a register temporarily into memory.
1059 If the predicate accepts a unary operator, the constraint applies to the
1060 operand. For example, the MIPS processor at ISA level 3 supports an
1061 instruction which adds two registers in @code{SImode} to produce a
1062 @code{DImode} result, but only if the registers are correctly sign
1063 extended. This predicate for the input operands accepts a
1064 @code{sign_extend} of an @code{SImode} register. Write the constraint
1065 to indicate the type of register that is required for the operand of the
1069 @node Multi-Alternative
1070 @subsection Multiple Alternative Constraints
1071 @cindex multiple alternative constraints
1073 Sometimes a single instruction has multiple alternative sets of possible
1074 operands. For example, on the 68000, a logical-or instruction can combine
1075 register or an immediate value into memory, or it can combine any kind of
1076 operand into a register; but it cannot combine one memory location into
1079 These constraints are represented as multiple alternatives. An alternative
1080 can be described by a series of letters for each operand. The overall
1081 constraint for an operand is made from the letters for this operand
1082 from the first alternative, a comma, the letters for this operand from
1083 the second alternative, a comma, and so on until the last alternative.
1085 Here is how it is done for fullword logical-or on the 68000:
1088 (define_insn "iorsi3"
1089 [(set (match_operand:SI 0 "general_operand" "=m,d")
1090 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1091 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1095 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1096 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1097 2. The second alternative has @samp{d} (data register) for operand 0,
1098 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1099 @samp{%} in the constraints apply to all the alternatives; their
1100 meaning is explained in the next section (@pxref{Class Preferences}).
1103 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1104 If all the operands fit any one alternative, the instruction is valid.
1105 Otherwise, for each alternative, the compiler counts how many instructions
1106 must be added to copy the operands so that that alternative applies.
1107 The alternative requiring the least copying is chosen. If two alternatives
1108 need the same amount of copying, the one that comes first is chosen.
1109 These choices can be altered with the @samp{?} and @samp{!} characters:
1112 @cindex @samp{?} in constraint
1113 @cindex question mark
1115 Disparage slightly the alternative that the @samp{?} appears in,
1116 as a choice when no alternative applies exactly. The compiler regards
1117 this alternative as one unit more costly for each @samp{?} that appears
1120 @cindex @samp{!} in constraint
1121 @cindex exclamation point
1123 Disparage severely the alternative that the @samp{!} appears in.
1124 This alternative can still be used if it fits without reloading,
1125 but if reloading is needed, some other alternative will be used.
1129 When an insn pattern has multiple alternatives in its constraints, often
1130 the appearance of the assembler code is determined mostly by which
1131 alternative was matched. When this is so, the C code for writing the
1132 assembler code can use the variable @code{which_alternative}, which is
1133 the ordinal number of the alternative that was actually satisfied (0 for
1134 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1138 @node Class Preferences
1139 @subsection Register Class Preferences
1140 @cindex class preference constraints
1141 @cindex register class preference constraints
1143 @cindex voting between constraint alternatives
1144 The operand constraints have another function: they enable the compiler
1145 to decide which kind of hardware register a pseudo register is best
1146 allocated to. The compiler examines the constraints that apply to the
1147 insns that use the pseudo register, looking for the machine-dependent
1148 letters such as @samp{d} and @samp{a} that specify classes of registers.
1149 The pseudo register is put in whichever class gets the most ``votes''.
1150 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1151 favor of a general register. The machine description says which registers
1152 are considered general.
1154 Of course, on some machines all registers are equivalent, and no register
1155 classes are defined. Then none of this complexity is relevant.
1159 @subsection Constraint Modifier Characters
1160 @cindex modifiers in constraints
1161 @cindex constraint modifier characters
1163 @c prevent bad page break with this line
1164 Here are constraint modifier characters.
1167 @cindex @samp{=} in constraint
1169 Means that this operand is write-only for this instruction: the previous
1170 value is discarded and replaced by output data.
1172 @cindex @samp{+} in constraint
1174 Means that this operand is both read and written by the instruction.
1176 When the compiler fixes up the operands to satisfy the constraints,
1177 it needs to know which operands are inputs to the instruction and
1178 which are outputs from it. @samp{=} identifies an output; @samp{+}
1179 identifies an operand that is both input and output; all other operands
1180 are assumed to be input only.
1182 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1183 first character of the constraint string.
1185 @cindex @samp{&} in constraint
1186 @cindex earlyclobber operand
1188 Means (in a particular alternative) that this operand is an
1189 @dfn{earlyclobber} operand, which is modified before the instruction is
1190 finished using the input operands. Therefore, this operand may not lie
1191 in a register that is used as an input operand or as part of any memory
1194 @samp{&} applies only to the alternative in which it is written. In
1195 constraints with multiple alternatives, sometimes one alternative
1196 requires @samp{&} while others do not. See, for example, the
1197 @samp{movdf} insn of the 68000.
1199 An input operand can be tied to an earlyclobber operand if its only
1200 use as an input occurs before the early result is written. Adding
1201 alternatives of this form often allows GCC to produce better code
1202 when only some of the inputs can be affected by the earlyclobber.
1203 See, for example, the @samp{mulsi3} insn of the ARM.
1205 @samp{&} does not obviate the need to write @samp{=}.
1207 @cindex @samp{%} in constraint
1209 Declares the instruction to be commutative for this operand and the
1210 following operand. This means that the compiler may interchange the
1211 two operands if that is the cheapest way to make all operands fit the
1214 This is often used in patterns for addition instructions
1215 that really have only two operands: the result must go in one of the
1216 arguments. Here for example, is how the 68000 halfword-add
1217 instruction is defined:
1220 (define_insn "addhi3"
1221 [(set (match_operand:HI 0 "general_operand" "=m,r")
1222 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1223 (match_operand:HI 2 "general_operand" "di,g")))]
1228 @cindex @samp{#} in constraint
1230 Says that all following characters, up to the next comma, are to be
1231 ignored as a constraint. They are significant only for choosing
1232 register preferences.
1235 @cindex @samp{*} in constraint
1237 Says that the following character should be ignored when choosing
1238 register preferences. @samp{*} has no effect on the meaning of the
1239 constraint as a constraint, and no effect on reloading.
1241 Here is an example: the 68000 has an instruction to sign-extend a
1242 halfword in a data register, and can also sign-extend a value by
1243 copying it into an address register. While either kind of register is
1244 acceptable, the constraints on an address-register destination are
1245 less strict, so it is best if register allocation makes an address
1246 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1247 constraint letter (for data register) is ignored when computing
1248 register preferences.
1251 (define_insn "extendhisi2"
1252 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1254 (match_operand:HI 1 "general_operand" "0,g")))]
1260 @node Machine Constraints
1261 @subsection Constraints for Particular Machines
1262 @cindex machine specific constraints
1263 @cindex constraints, machine specific
1265 Whenever possible, you should use the general-purpose constraint letters
1266 in @code{asm} arguments, since they will convey meaning more readily to
1267 people reading your code. Failing that, use the constraint letters
1268 that usually have very similar meanings across architectures. The most
1269 commonly used constraints are @samp{m} and @samp{r} (for memory and
1270 general-purpose registers respectively; @pxref{Simple Constraints}), and
1271 @samp{I}, usually the letter indicating the most common
1272 immediate-constant format.
1274 For each machine architecture, the @file{config/@var{machine}.h} file
1275 defines additional constraints. These constraints are used by the
1276 compiler itself for instruction generation, as well as for @code{asm}
1277 statements; therefore, some of the constraints are not particularly
1278 interesting for @code{asm}. The constraints are defined through these
1282 @item REG_CLASS_FROM_LETTER
1283 Register class constraints (usually lower case).
1285 @item CONST_OK_FOR_LETTER_P
1286 Immediate constant constraints, for non-floating point constants of
1287 word size or smaller precision (usually upper case).
1289 @item CONST_DOUBLE_OK_FOR_LETTER_P
1290 Immediate constant constraints, for all floating point constants and for
1291 constants of greater than word size precision (usually upper case).
1293 @item EXTRA_CONSTRAINT
1294 Special cases of registers or memory. This macro is not required, and
1295 is only defined for some machines.
1298 Inspecting these macro definitions in the compiler source for your
1299 machine is the best way to be certain you have the right constraints.
1300 However, here is a summary of the machine-dependent constraints
1301 available on some particular machines.
1304 @item ARM family---@file{arm.h}
1307 Floating-point register
1310 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1314 Floating-point constant that would satisfy the constraint @samp{F} if it
1318 Integer that is valid as an immediate operand in a data processing
1319 instruction. That is, an integer in the range 0 to 255 rotated by a
1323 Integer in the range -4095 to 4095
1326 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1329 Integer that satisfies constraint @samp{I} when negated (twos complement)
1332 Integer in the range 0 to 32
1335 A memory reference where the exact address is in a single register
1336 (`@samp{m}' is preferable for @code{asm} statements)
1339 An item in the constant pool
1342 A symbol in the text segment of the current file
1345 @item AMD 29000 family---@file{a29k.h}
1351 Byte Pointer (@samp{BP}) register
1357 Special purpose register
1360 First accumulator register
1363 Other accumulator register
1366 Floating point register
1369 Constant greater than 0, less than 0x100
1372 Constant greater than 0, less than 0x10000
1375 Constant whose high 24 bits are on (1)
1378 16 bit constant whose high 8 bits are on (1)
1381 32 bit constant whose high 16 bits are on (1)
1384 32 bit negative constant that fits in 8 bits
1387 The constant 0x80000000 or, on the 29050, any 32 bit constant
1388 whose low 16 bits are 0.
1391 16 bit negative constant that fits in 8 bits
1395 A floating point constant (in @code{asm} statements, use the machine
1396 independent @samp{E} or @samp{F} instead)
1399 @item AVR family---@file{avr.h}
1402 Registers from r0 to r15
1405 Registers from r16 to r23
1408 Registers from r16 to r31
1411 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1414 Pointer register (r26 - r31)
1417 Base pointer register (r28 - r31)
1420 Stack pointer register (SPH:SPL)
1423 Temporary register r0
1426 Register pair X (r27:r26)
1429 Register pair Y (r29:r28)
1432 Register pair Z (r31:r30)
1435 Constant greater than -1, less than 64
1438 Constant greater than -64, less than 1
1447 Constant that fits in 8 bits
1453 Constant integer 8, 16, or 24
1459 A floating point constant 0.0
1462 @item IBM RS6000---@file{rs6000.h}
1465 Address base register
1468 Floating point register
1471 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1480 @samp{LINK} register
1483 @samp{CR} register (condition register) number 0
1486 @samp{CR} register (condition register)
1489 @samp{FPMEM} stack memory for FPR-GPR transfers
1492 Signed 16 bit constant
1495 Unsigned 16 bit constant shifted left 16 bits (use @samp{L} instead for
1496 @code{SImode} constants)
1499 Unsigned 16 bit constant
1502 Signed 16 bit constant shifted left 16 bits
1505 Constant larger than 31
1514 Constant whose negation is a signed 16 bit constant
1517 Floating point constant that can be loaded into a register with one
1518 instruction per word
1521 Memory operand that is an offset from a register (@samp{m} is preferable
1522 for @code{asm} statements)
1528 Constant suitable as a 64-bit mask operand
1531 Constant suitable as a 32-bit mask operand
1534 System V Release 4 small data area reference
1537 @item Intel 386---@file{i386.h}
1540 @samp{a}, @code{b}, @code{c}, or @code{d} register
1543 @samp{a}, or @code{d} register (for 64-bit ints)
1546 Floating point register
1549 First (top of stack) floating point register
1552 Second floating point register
1573 Constant in range 0 to 31 (for 32 bit shifts)
1576 Constant in range 0 to 63 (for 64 bit shifts)
1585 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1588 Constant in range 0 to 255 (for @code{out} instruction)
1591 Standard 80387 floating point constant
1594 @item Intel 960---@file{i960.h}
1597 Floating point register (@code{fp0} to @code{fp3})
1600 Local register (@code{r0} to @code{r15})
1603 Global register (@code{g0} to @code{g15})
1606 Any local or global register
1609 Integers from 0 to 31
1615 Integers from -31 to 0
1624 @item MIPS---@file{mips.h}
1627 General-purpose integer register
1630 Floating-point register (if available)
1639 @samp{Hi} or @samp{Lo} register
1642 General-purpose integer register
1645 Floating-point status register
1648 Signed 16 bit constant (for arithmetic instructions)
1654 Zero-extended 16-bit constant (for logic instructions)
1657 Constant with low 16 bits zero (can be loaded with @code{lui})
1660 32 bit constant which requires two instructions to load (a constant
1661 which is not @samp{I}, @samp{K}, or @samp{L})
1664 Negative 16 bit constant
1670 Positive 16 bit constant
1676 Memory reference that can be loaded with more than one instruction
1677 (@samp{m} is preferable for @code{asm} statements)
1680 Memory reference that can be loaded with one instruction
1681 (@samp{m} is preferable for @code{asm} statements)
1684 Memory reference in external OSF/rose PIC format
1685 (@samp{m} is preferable for @code{asm} statements)
1688 @item Motorola 680x0---@file{m68k.h}
1697 68881 floating-point register, if available
1700 Sun FPA (floating-point) register, if available
1703 First 16 Sun FPA registers, if available
1706 Integer in the range 1 to 8
1709 16 bit signed number
1712 Signed number whose magnitude is greater than 0x80
1715 Integer in the range -8 to -1
1718 Signed number whose magnitude is greater than 0x100
1721 Floating point constant that is not a 68881 constant
1724 Floating point constant that can be used by Sun FPA
1727 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
1742 Temporary soft register _.tmp
1745 A soft register _.d1 to _.d31
1748 Stack pointer register
1757 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
1760 An address register: x, y or z
1763 An address register: x or y
1766 Register pair (x:d) to form a 32-bit value
1769 Constants in the range -65536 to 65535
1772 Constants whose 16-bit low part is zero
1775 Constant integer 1 or -1
1781 Constants in the range -8 to 2
1786 @item SPARC---@file{sparc.h}
1789 Floating-point register that can hold 32 or 64 bit values.
1792 Floating-point register that can hold 64 or 128 bit values.
1795 Signed 13 bit constant
1801 32 bit constant with the low 12 bits clear (a constant that can be
1802 loaded with the @code{sethi} instruction)
1808 Signed 13 bit constant, sign-extended to 32 or 64 bits
1811 Floating-point constant whose integral representation can
1812 be moved into an integer register using a single sethi
1816 Floating-point constant whose integral representation can
1817 be moved into an integer register using a single mov
1821 Floating-point constant whose integral representation can
1822 be moved into an integer register using a high/lo_sum
1823 instruction sequence
1826 Memory address aligned to an 8-byte boundary
1833 @item TMS320C3x/C4x---@file{c4x.h}
1836 Auxiliary (address) register (ar0-ar7)
1839 Stack pointer register (sp)
1842 Standard (32 bit) precision integer register
1845 Extended (40 bit) precision register (r0-r11)
1848 Block count register (bk)
1851 Extended (40 bit) precision low register (r0-r7)
1854 Extended (40 bit) precision register (r0-r1)
1857 Extended (40 bit) precision register (r2-r3)
1860 Repeat count register (rc)
1863 Index register (ir0-ir1)
1866 Status (condition code) register (st)
1869 Data page register (dp)
1875 Immediate 16 bit floating-point constant
1878 Signed 16 bit constant
1881 Signed 8 bit constant
1884 Signed 5 bit constant
1887 Unsigned 16 bit constant
1890 Unsigned 8 bit constant
1893 Ones complement of unsigned 16 bit constant
1896 High 16 bit constant (32 bit constant with 16 LSBs zero)
1899 Indirect memory reference with signed 8 bit or index register displacement
1902 Indirect memory reference with unsigned 5 bit displacement
1905 Indirect memory reference with 1 bit or index register displacement
1908 Direct memory reference
1917 @node Standard Names
1918 @section Standard Pattern Names For Generation
1919 @cindex standard pattern names
1920 @cindex pattern names
1921 @cindex names, pattern
1923 Here is a table of the instruction names that are meaningful in the RTL
1924 generation pass of the compiler. Giving one of these names to an
1925 instruction pattern tells the RTL generation pass that it can use the
1926 pattern to accomplish a certain task.
1929 @cindex @code{mov@var{m}} instruction pattern
1930 @item @samp{mov@var{m}}
1931 Here @var{m} stands for a two-letter machine mode name, in lower case.
1932 This instruction pattern moves data with that machine mode from operand
1933 1 to operand 0. For example, @samp{movsi} moves full-word data.
1935 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1936 own mode is wider than @var{m}, the effect of this instruction is
1937 to store the specified value in the part of the register that corresponds
1938 to mode @var{m}. The effect on the rest of the register is undefined.
1940 This class of patterns is special in several ways. First of all, each
1941 of these names up to and including full word size @emph{must} be defined,
1942 because there is no other way to copy a datum from one place to another.
1943 If there are patterns accepting operands in larger modes,
1944 @samp{mov@var{m}} must be defined for integer modes of those sizes.
1946 Second, these patterns are not used solely in the RTL generation pass.
1947 Even the reload pass can generate move insns to copy values from stack
1948 slots into temporary registers. When it does so, one of the operands is
1949 a hard register and the other is an operand that can need to be reloaded
1953 Therefore, when given such a pair of operands, the pattern must generate
1954 RTL which needs no reloading and needs no temporary registers---no
1955 registers other than the operands. For example, if you support the
1956 pattern with a @code{define_expand}, then in such a case the
1957 @code{define_expand} mustn't call @code{force_reg} or any other such
1958 function which might generate new pseudo registers.
1960 This requirement exists even for subword modes on a RISC machine where
1961 fetching those modes from memory normally requires several insns and
1962 some temporary registers. Look in @file{spur.md} to see how the
1963 requirement can be satisfied.
1965 @findex change_address
1966 During reload a memory reference with an invalid address may be passed
1967 as an operand. Such an address will be replaced with a valid address
1968 later in the reload pass. In this case, nothing may be done with the
1969 address except to use it as it stands. If it is copied, it will not be
1970 replaced with a valid address. No attempt should be made to make such
1971 an address into a valid address and no routine (such as
1972 @code{change_address}) that will do so may be called. Note that
1973 @code{general_operand} will fail when applied to such an address.
1975 @findex reload_in_progress
1976 The global variable @code{reload_in_progress} (which must be explicitly
1977 declared if required) can be used to determine whether such special
1978 handling is required.
1980 The variety of operands that have reloads depends on the rest of the
1981 machine description, but typically on a RISC machine these can only be
1982 pseudo registers that did not get hard registers, while on other
1983 machines explicit memory references will get optional reloads.
1985 If a scratch register is required to move an object to or from memory,
1986 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
1988 If there are cases needing
1989 scratch registers after reload, you must define
1990 @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
1991 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1992 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1993 them. @xref{Register Classes}.
1995 @findex no_new_pseudos
1996 The global variable @code{no_new_pseudos} can be used to determine if it
1997 is unsafe to create new pseudo registers. If this variable is nonzero, then
1998 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2000 The constraints on a @samp{mov@var{m}} must permit moving any hard
2001 register to any other hard register provided that
2002 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2003 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2005 It is obligatory to support floating point @samp{mov@var{m}}
2006 instructions into and out of any registers that can hold fixed point
2007 values, because unions and structures (which have modes @code{SImode} or
2008 @code{DImode}) can be in those registers and they may have floating
2011 There may also be a need to support fixed point @samp{mov@var{m}}
2012 instructions in and out of floating point registers. Unfortunately, I
2013 have forgotten why this was so, and I don't know whether it is still
2014 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2015 floating point registers, then the constraints of the fixed point
2016 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2017 reload into a floating point register.
2019 @cindex @code{reload_in} instruction pattern
2020 @cindex @code{reload_out} instruction pattern
2021 @item @samp{reload_in@var{m}}
2022 @itemx @samp{reload_out@var{m}}
2023 Like @samp{mov@var{m}}, but used when a scratch register is required to
2024 move between operand 0 and operand 1. Operand 2 describes the scratch
2025 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2026 macro in @pxref{Register Classes}.
2028 @cindex @code{movstrict@var{m}} instruction pattern
2029 @item @samp{movstrict@var{m}}
2030 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2031 with mode @var{m} of a register whose natural mode is wider,
2032 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2033 any of the register except the part which belongs to mode @var{m}.
2035 @cindex @code{load_multiple} instruction pattern
2036 @item @samp{load_multiple}
2037 Load several consecutive memory locations into consecutive registers.
2038 Operand 0 is the first of the consecutive registers, operand 1
2039 is the first memory location, and operand 2 is a constant: the
2040 number of consecutive registers.
2042 Define this only if the target machine really has such an instruction;
2043 do not define this if the most efficient way of loading consecutive
2044 registers from memory is to do them one at a time.
2046 On some machines, there are restrictions as to which consecutive
2047 registers can be stored into memory, such as particular starting or
2048 ending register numbers or only a range of valid counts. For those
2049 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2050 and make the pattern fail if the restrictions are not met.
2052 Write the generated insn as a @code{parallel} with elements being a
2053 @code{set} of one register from the appropriate memory location (you may
2054 also need @code{use} or @code{clobber} elements). Use a
2055 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2056 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
2059 @cindex @samp{store_multiple} instruction pattern
2060 @item @samp{store_multiple}
2061 Similar to @samp{load_multiple}, but store several consecutive registers
2062 into consecutive memory locations. Operand 0 is the first of the
2063 consecutive memory locations, operand 1 is the first register, and
2064 operand 2 is a constant: the number of consecutive registers.
2066 @cindex @code{add@var{m}3} instruction pattern
2067 @item @samp{add@var{m}3}
2068 Add operand 2 and operand 1, storing the result in operand 0. All operands
2069 must have mode @var{m}. This can be used even on two-address machines, by
2070 means of constraints requiring operands 1 and 0 to be the same location.
2072 @cindex @code{sub@var{m}3} instruction pattern
2073 @cindex @code{mul@var{m}3} instruction pattern
2074 @cindex @code{div@var{m}3} instruction pattern
2075 @cindex @code{udiv@var{m}3} instruction pattern
2076 @cindex @code{mod@var{m}3} instruction pattern
2077 @cindex @code{umod@var{m}3} instruction pattern
2078 @cindex @code{smin@var{m}3} instruction pattern
2079 @cindex @code{smax@var{m}3} instruction pattern
2080 @cindex @code{umin@var{m}3} instruction pattern
2081 @cindex @code{umax@var{m}3} instruction pattern
2082 @cindex @code{and@var{m}3} instruction pattern
2083 @cindex @code{ior@var{m}3} instruction pattern
2084 @cindex @code{xor@var{m}3} instruction pattern
2085 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2086 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2087 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2088 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2089 Similar, for other arithmetic operations.
2091 @cindex @code{mulhisi3} instruction pattern
2092 @item @samp{mulhisi3}
2093 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2094 a @code{SImode} product in operand 0.
2096 @cindex @code{mulqihi3} instruction pattern
2097 @cindex @code{mulsidi3} instruction pattern
2098 @item @samp{mulqihi3}, @samp{mulsidi3}
2099 Similar widening-multiplication instructions of other widths.
2101 @cindex @code{umulqihi3} instruction pattern
2102 @cindex @code{umulhisi3} instruction pattern
2103 @cindex @code{umulsidi3} instruction pattern
2104 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2105 Similar widening-multiplication instructions that do unsigned
2108 @cindex @code{smul@var{m}3_highpart} instruction pattern
2109 @item @samp{smul@var{m}3_highpart}
2110 Perform a signed multiplication of operands 1 and 2, which have mode
2111 @var{m}, and store the most significant half of the product in operand 0.
2112 The least significant half of the product is discarded.
2114 @cindex @code{umul@var{m}3_highpart} instruction pattern
2115 @item @samp{umul@var{m}3_highpart}
2116 Similar, but the multiplication is unsigned.
2118 @cindex @code{divmod@var{m}4} instruction pattern
2119 @item @samp{divmod@var{m}4}
2120 Signed division that produces both a quotient and a remainder.
2121 Operand 1 is divided by operand 2 to produce a quotient stored
2122 in operand 0 and a remainder stored in operand 3.
2124 For machines with an instruction that produces both a quotient and a
2125 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2126 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2127 allows optimization in the relatively common case when both the quotient
2128 and remainder are computed.
2130 If an instruction that just produces a quotient or just a remainder
2131 exists and is more efficient than the instruction that produces both,
2132 write the output routine of @samp{divmod@var{m}4} to call
2133 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2134 quotient or remainder and generate the appropriate instruction.
2136 @cindex @code{udivmod@var{m}4} instruction pattern
2137 @item @samp{udivmod@var{m}4}
2138 Similar, but does unsigned division.
2140 @cindex @code{ashl@var{m}3} instruction pattern
2141 @item @samp{ashl@var{m}3}
2142 Arithmetic-shift operand 1 left by a number of bits specified by operand
2143 2, and store the result in operand 0. Here @var{m} is the mode of
2144 operand 0 and operand 1; operand 2's mode is specified by the
2145 instruction pattern, and the compiler will convert the operand to that
2146 mode before generating the instruction.
2148 @cindex @code{ashr@var{m}3} instruction pattern
2149 @cindex @code{lshr@var{m}3} instruction pattern
2150 @cindex @code{rotl@var{m}3} instruction pattern
2151 @cindex @code{rotr@var{m}3} instruction pattern
2152 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2153 Other shift and rotate instructions, analogous to the
2154 @code{ashl@var{m}3} instructions.
2156 @cindex @code{neg@var{m}2} instruction pattern
2157 @item @samp{neg@var{m}2}
2158 Negate operand 1 and store the result in operand 0.
2160 @cindex @code{abs@var{m}2} instruction pattern
2161 @item @samp{abs@var{m}2}
2162 Store the absolute value of operand 1 into operand 0.
2164 @cindex @code{sqrt@var{m}2} instruction pattern
2165 @item @samp{sqrt@var{m}2}
2166 Store the square root of operand 1 into operand 0.
2168 The @code{sqrt} built-in function of C always uses the mode which
2169 corresponds to the C data type @code{double}.
2171 @cindex @code{ffs@var{m}2} instruction pattern
2172 @item @samp{ffs@var{m}2}
2173 Store into operand 0 one plus the index of the least significant 1-bit
2174 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2175 of operand 0; operand 1's mode is specified by the instruction
2176 pattern, and the compiler will convert the operand to that mode before
2177 generating the instruction.
2179 The @code{ffs} built-in function of C always uses the mode which
2180 corresponds to the C data type @code{int}.
2182 @cindex @code{one_cmpl@var{m}2} instruction pattern
2183 @item @samp{one_cmpl@var{m}2}
2184 Store the bitwise-complement of operand 1 into operand 0.
2186 @cindex @code{cmp@var{m}} instruction pattern
2187 @item @samp{cmp@var{m}}
2188 Compare operand 0 and operand 1, and set the condition codes.
2189 The RTL pattern should look like this:
2192 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2193 (match_operand:@var{m} 1 @dots{})))
2196 @cindex @code{tst@var{m}} instruction pattern
2197 @item @samp{tst@var{m}}
2198 Compare operand 0 against zero, and set the condition codes.
2199 The RTL pattern should look like this:
2202 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2205 @samp{tst@var{m}} patterns should not be defined for machines that do
2206 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2207 would no longer be clear which @code{set} operations were comparisons.
2208 The @samp{cmp@var{m}} patterns should be used instead.
2210 @cindex @code{movstr@var{m}} instruction pattern
2211 @item @samp{movstr@var{m}}
2212 Block move instruction. The addresses of the destination and source
2213 strings are the first two operands, and both are in mode @code{Pmode}.
2215 The number of bytes to move is the third operand, in mode @var{m}.
2216 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2217 generate better code knowing the range of valid lengths is smaller than
2218 those representable in a full word, you should provide a pattern with a
2219 mode corresponding to the range of values you can handle efficiently
2220 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2221 that appear negative) and also a pattern with @code{word_mode}.
2223 The fourth operand is the known shared alignment of the source and
2224 destination, in the form of a @code{const_int} rtx. Thus, if the
2225 compiler knows that both source and destination are word-aligned,
2226 it may provide the value 4 for this operand.
2228 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2229 beneficial if the patterns for smaller modes have fewer restrictions
2230 on their first, second and fourth operands. Note that the mode @var{m}
2231 in @code{movstr@var{m}} does not impose any restriction on the mode of
2232 individually moved data units in the block.
2234 These patterns need not give special consideration to the possibility
2235 that the source and destination strings might overlap.
2237 @cindex @code{clrstr@var{m}} instruction pattern
2238 @item @samp{clrstr@var{m}}
2239 Block clear instruction. The addresses of the destination string is the
2240 first operand, in mode @code{Pmode}. The number of bytes to clear is
2241 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2242 a discussion of the choice of mode.
2244 The third operand is the known alignment of the destination, in the form
2245 of a @code{const_int} rtx. Thus, if the compiler knows that the
2246 destination is word-aligned, it may provide the value 4 for this
2249 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2251 @cindex @code{cmpstr@var{m}} instruction pattern
2252 @item @samp{cmpstr@var{m}}
2253 Block compare instruction, with five operands. Operand 0 is the output;
2254 it has mode @var{m}. The remaining four operands are like the operands
2255 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2256 byte by byte in lexicographic order. The effect of the instruction is
2257 to store a value in operand 0 whose sign indicates the result of the
2260 @cindex @code{strlen@var{m}} instruction pattern
2261 @item @samp{strlen@var{m}}
2262 Compute the length of a string, with three operands.
2263 Operand 0 is the result (of mode @var{m}), operand 1 is
2264 a @code{mem} referring to the first character of the string,
2265 operand 2 is the character to search for (normally zero),
2266 and operand 3 is a constant describing the known alignment
2267 of the beginning of the string.
2269 @cindex @code{float@var{mn}2} instruction pattern
2270 @item @samp{float@var{m}@var{n}2}
2271 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2272 floating point mode @var{n} and store in operand 0 (which has mode
2275 @cindex @code{floatuns@var{mn}2} instruction pattern
2276 @item @samp{floatuns@var{m}@var{n}2}
2277 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2278 to floating point mode @var{n} and store in operand 0 (which has mode
2281 @cindex @code{fix@var{mn}2} instruction pattern
2282 @item @samp{fix@var{m}@var{n}2}
2283 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2284 point mode @var{n} as a signed number and store in operand 0 (which
2285 has mode @var{n}). This instruction's result is defined only when
2286 the value of operand 1 is an integer.
2288 @cindex @code{fixuns@var{mn}2} instruction pattern
2289 @item @samp{fixuns@var{m}@var{n}2}
2290 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2291 point mode @var{n} as an unsigned number and store in operand 0 (which
2292 has mode @var{n}). This instruction's result is defined only when the
2293 value of operand 1 is an integer.
2295 @cindex @code{ftrunc@var{m}2} instruction pattern
2296 @item @samp{ftrunc@var{m}2}
2297 Convert operand 1 (valid for floating point mode @var{m}) to an
2298 integer value, still represented in floating point mode @var{m}, and
2299 store it in operand 0 (valid for floating point mode @var{m}).
2301 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2302 @item @samp{fix_trunc@var{m}@var{n}2}
2303 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2304 of mode @var{m} by converting the value to an integer.
2306 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2307 @item @samp{fixuns_trunc@var{m}@var{n}2}
2308 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2309 value of mode @var{m} by converting the value to an integer.
2311 @cindex @code{trunc@var{mn}2} instruction pattern
2312 @item @samp{trunc@var{m}@var{n}2}
2313 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2314 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2315 point or both floating point.
2317 @cindex @code{extend@var{mn}2} instruction pattern
2318 @item @samp{extend@var{m}@var{n}2}
2319 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2320 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2321 point or both floating point.
2323 @cindex @code{zero_extend@var{mn}2} instruction pattern
2324 @item @samp{zero_extend@var{m}@var{n}2}
2325 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2326 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2329 @cindex @code{extv} instruction pattern
2331 Extract a bit field from operand 1 (a register or memory operand), where
2332 operand 2 specifies the width in bits and operand 3 the starting bit,
2333 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2334 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2335 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2336 be valid for @code{word_mode}.
2338 The RTL generation pass generates this instruction only with constants
2339 for operands 2 and 3.
2341 The bit-field value is sign-extended to a full word integer
2342 before it is stored in operand 0.
2344 @cindex @code{extzv} instruction pattern
2346 Like @samp{extv} except that the bit-field value is zero-extended.
2348 @cindex @code{insv} instruction pattern
2350 Store operand 3 (which must be valid for @code{word_mode}) into a bit
2351 field in operand 0, where operand 1 specifies the width in bits and
2352 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2353 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2354 Operands 1 and 2 must be valid for @code{word_mode}.
2356 The RTL generation pass generates this instruction only with constants
2357 for operands 1 and 2.
2359 @cindex @code{mov@var{mode}cc} instruction pattern
2360 @item @samp{mov@var{mode}cc}
2361 Conditionally move operand 2 or operand 3 into operand 0 according to the
2362 comparison in operand 1. If the comparison is true, operand 2 is moved
2363 into operand 0, otherwise operand 3 is moved.
2365 The mode of the operands being compared need not be the same as the operands
2366 being moved. Some machines, sparc64 for example, have instructions that
2367 conditionally move an integer value based on the floating point condition
2368 codes and vice versa.
2370 If the machine does not have conditional move instructions, do not
2371 define these patterns.
2373 @cindex @code{s@var{cond}} instruction pattern
2374 @item @samp{s@var{cond}}
2375 Store zero or nonzero in the operand according to the condition codes.
2376 Value stored is nonzero iff the condition @var{cond} is true.
2377 @var{cond} is the name of a comparison operation expression code, such
2378 as @code{eq}, @code{lt} or @code{leu}.
2380 You specify the mode that the operand must have when you write the
2381 @code{match_operand} expression. The compiler automatically sees
2382 which mode you have used and supplies an operand of that mode.
2384 The value stored for a true condition must have 1 as its low bit, or
2385 else must be negative. Otherwise the instruction is not suitable and
2386 you should omit it from the machine description. You describe to the
2387 compiler exactly which value is stored by defining the macro
2388 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2389 found that can be used for all the @samp{s@var{cond}} patterns, you
2390 should omit those operations from the machine description.
2392 These operations may fail, but should do so only in relatively
2393 uncommon cases; if they would fail for common cases involving
2394 integer comparisons, it is best to omit these patterns.
2396 If these operations are omitted, the compiler will usually generate code
2397 that copies the constant one to the target and branches around an
2398 assignment of zero to the target. If this code is more efficient than
2399 the potential instructions used for the @samp{s@var{cond}} pattern
2400 followed by those required to convert the result into a 1 or a zero in
2401 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2402 the machine description.
2404 @cindex @code{b@var{cond}} instruction pattern
2405 @item @samp{b@var{cond}}
2406 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2407 refers to the label to jump to. Jump if the condition codes meet
2408 condition @var{cond}.
2410 Some machines do not follow the model assumed here where a comparison
2411 instruction is followed by a conditional branch instruction. In that
2412 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2413 simply store the operands away and generate all the required insns in a
2414 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2415 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2416 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2417 pattern or a @samp{tst@var{m}} pattern.
2419 Machines that use a pseudo register for the condition code value, or
2420 where the mode used for the comparison depends on the condition being
2421 tested, should also use the above mechanism. @xref{Jump Patterns}.
2423 The above discussion also applies to the @samp{mov@var{mode}cc} and
2424 @samp{s@var{cond}} patterns.
2426 @cindex @code{jump} instruction pattern
2428 A jump inside a function; an unconditional branch. Operand 0 is the
2429 @code{label_ref} of the label to jump to. This pattern name is mandatory
2432 @cindex @code{call} instruction pattern
2434 Subroutine call instruction returning no value. Operand 0 is the
2435 function to call; operand 1 is the number of bytes of arguments pushed
2436 as a @code{const_int}; operand 2 is the number of registers used as
2439 On most machines, operand 2 is not actually stored into the RTL
2440 pattern. It is supplied for the sake of some RISC machines which need
2441 to put this information into the assembler code; they can put it in
2442 the RTL instead of operand 1.
2444 Operand 0 should be a @code{mem} RTX whose address is the address of the
2445 function. Note, however, that this address can be a @code{symbol_ref}
2446 expression even if it would not be a legitimate memory address on the
2447 target machine. If it is also not a valid argument for a call
2448 instruction, the pattern for this operation should be a
2449 @code{define_expand} (@pxref{Expander Definitions}) that places the
2450 address into a register and uses that register in the call instruction.
2452 @cindex @code{call_value} instruction pattern
2453 @item @samp{call_value}
2454 Subroutine call instruction returning a value. Operand 0 is the hard
2455 register in which the value is returned. There are three more
2456 operands, the same as the three operands of the @samp{call}
2457 instruction (but with numbers increased by one).
2459 Subroutines that return @code{BLKmode} objects use the @samp{call}
2462 @cindex @code{call_pop} instruction pattern
2463 @cindex @code{call_value_pop} instruction pattern
2464 @item @samp{call_pop}, @samp{call_value_pop}
2465 Similar to @samp{call} and @samp{call_value}, except used if defined and
2466 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2467 that contains both the function call and a @code{set} to indicate the
2468 adjustment made to the frame pointer.
2470 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2471 patterns increases the number of functions for which the frame pointer
2472 can be eliminated, if desired.
2474 @cindex @code{untyped_call} instruction pattern
2475 @item @samp{untyped_call}
2476 Subroutine call instruction returning a value of any type. Operand 0 is
2477 the function to call; operand 1 is a memory location where the result of
2478 calling the function is to be stored; operand 2 is a @code{parallel}
2479 expression where each element is a @code{set} expression that indicates
2480 the saving of a function return value into the result block.
2482 This instruction pattern should be defined to support
2483 @code{__builtin_apply} on machines where special instructions are needed
2484 to call a subroutine with arbitrary arguments or to save the value
2485 returned. This instruction pattern is required on machines that have
2486 multiple registers that can hold a return value (i.e.
2487 @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2489 @cindex @code{return} instruction pattern
2491 Subroutine return instruction. This instruction pattern name should be
2492 defined only if a single instruction can do all the work of returning
2495 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2496 RTL generation phase. In this case it is to support machines where
2497 multiple instructions are usually needed to return from a function, but
2498 some class of functions only requires one instruction to implement a
2499 return. Normally, the applicable functions are those which do not need
2500 to save any registers or allocate stack space.
2502 @findex reload_completed
2503 @findex leaf_function_p
2504 For such machines, the condition specified in this pattern should only
2505 be true when @code{reload_completed} is non-zero and the function's
2506 epilogue would only be a single instruction. For machines with register
2507 windows, the routine @code{leaf_function_p} may be used to determine if
2508 a register window push is required.
2510 Machines that have conditional return instructions should define patterns
2516 (if_then_else (match_operator
2517 0 "comparison_operator"
2518 [(cc0) (const_int 0)])
2525 where @var{condition} would normally be the same condition specified on the
2526 named @samp{return} pattern.
2528 @cindex @code{untyped_return} instruction pattern
2529 @item @samp{untyped_return}
2530 Untyped subroutine return instruction. This instruction pattern should
2531 be defined to support @code{__builtin_return} on machines where special
2532 instructions are needed to return a value of any type.
2534 Operand 0 is a memory location where the result of calling a function
2535 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2536 expression where each element is a @code{set} expression that indicates
2537 the restoring of a function return value from the result block.
2539 @cindex @code{nop} instruction pattern
2541 No-op instruction. This instruction pattern name should always be defined
2542 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2545 @cindex @code{indirect_jump} instruction pattern
2546 @item @samp{indirect_jump}
2547 An instruction to jump to an address which is operand zero.
2548 This pattern name is mandatory on all machines.
2550 @cindex @code{casesi} instruction pattern
2552 Instruction to jump through a dispatch table, including bounds checking.
2553 This instruction takes five operands:
2557 The index to dispatch on, which has mode @code{SImode}.
2560 The lower bound for indices in the table, an integer constant.
2563 The total range of indices in the table---the largest index
2564 minus the smallest one (both inclusive).
2567 A label that precedes the table itself.
2570 A label to jump to if the index has a value outside the bounds.
2571 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2572 then an out-of-bounds index drops through to the code following
2573 the jump table instead of jumping to this label. In that case,
2574 this label is not actually used by the @samp{casesi} instruction,
2575 but it is always provided as an operand.)
2578 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2579 @code{jump_insn}. The number of elements in the table is one plus the
2580 difference between the upper bound and the lower bound.
2582 @cindex @code{tablejump} instruction pattern
2583 @item @samp{tablejump}
2584 Instruction to jump to a variable address. This is a low-level
2585 capability which can be used to implement a dispatch table when there
2586 is no @samp{casesi} pattern.
2588 This pattern requires two operands: the address or offset, and a label
2589 which should immediately precede the jump table. If the macro
2590 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2591 operand is an offset which counts from the address of the table; otherwise,
2592 it is an absolute address to jump to. In either case, the first operand has
2595 The @samp{tablejump} insn is always the last insn before the jump
2596 table it uses. Its assembler code normally has no need to use the
2597 second operand, but you should incorporate it in the RTL pattern so
2598 that the jump optimizer will not delete the table as unreachable code.
2600 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2601 @item @samp{canonicalize_funcptr_for_compare}
2602 Canonicalize the function pointer in operand 1 and store the result
2605 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2606 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2607 and also has mode @code{Pmode}.
2609 Canonicalization of a function pointer usually involves computing
2610 the address of the function which would be called if the function
2611 pointer were used in an indirect call.
2613 Only define this pattern if function pointers on the target machine
2614 can have different values but still call the same function when
2615 used in an indirect call.
2617 @cindex @code{save_stack_block} instruction pattern
2618 @cindex @code{save_stack_function} instruction pattern
2619 @cindex @code{save_stack_nonlocal} instruction pattern
2620 @cindex @code{restore_stack_block} instruction pattern
2621 @cindex @code{restore_stack_function} instruction pattern
2622 @cindex @code{restore_stack_nonlocal} instruction pattern
2623 @item @samp{save_stack_block}
2624 @itemx @samp{save_stack_function}
2625 @itemx @samp{save_stack_nonlocal}
2626 @itemx @samp{restore_stack_block}
2627 @itemx @samp{restore_stack_function}
2628 @itemx @samp{restore_stack_nonlocal}
2629 Most machines save and restore the stack pointer by copying it to or
2630 from an object of mode @code{Pmode}. Do not define these patterns on
2633 Some machines require special handling for stack pointer saves and
2634 restores. On those machines, define the patterns corresponding to the
2635 non-standard cases by using a @code{define_expand} (@pxref{Expander
2636 Definitions}) that produces the required insns. The three types of
2637 saves and restores are:
2641 @samp{save_stack_block} saves the stack pointer at the start of a block
2642 that allocates a variable-sized object, and @samp{restore_stack_block}
2643 restores the stack pointer when the block is exited.
2646 @samp{save_stack_function} and @samp{restore_stack_function} do a
2647 similar job for the outermost block of a function and are used when the
2648 function allocates variable-sized objects or calls @code{alloca}. Only
2649 the epilogue uses the restored stack pointer, allowing a simpler save or
2650 restore sequence on some machines.
2653 @samp{save_stack_nonlocal} is used in functions that contain labels
2654 branched to by nested functions. It saves the stack pointer in such a
2655 way that the inner function can use @samp{restore_stack_nonlocal} to
2656 restore the stack pointer. The compiler generates code to restore the
2657 frame and argument pointer registers, but some machines require saving
2658 and restoring additional data such as register window information or
2659 stack backchains. Place insns in these patterns to save and restore any
2663 When saving the stack pointer, operand 0 is the save area and operand 1
2664 is the stack pointer. The mode used to allocate the save area defaults
2665 to @code{Pmode} but you can override that choice by defining the
2666 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
2667 specify an integral mode, or @code{VOIDmode} if no save area is needed
2668 for a particular type of save (either because no save is needed or
2669 because a machine-specific save area can be used). Operand 0 is the
2670 stack pointer and operand 1 is the save area for restore operations. If
2671 @samp{save_stack_block} is defined, operand 0 must not be
2672 @code{VOIDmode} since these saves can be arbitrarily nested.
2674 A save area is a @code{mem} that is at a constant offset from
2675 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2676 nonlocal gotos and a @code{reg} in the other two cases.
2678 @cindex @code{allocate_stack} instruction pattern
2679 @item @samp{allocate_stack}
2680 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2681 the stack pointer to create space for dynamically allocated data.
2683 Store the resultant pointer to this space into operand 0. If you
2684 are allocating space from the main stack, do this by emitting a
2685 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2686 If you are allocating the space elsewhere, generate code to copy the
2687 location of the space to operand 0. In the latter case, you must
2688 ensure this space gets freed when the corresponding space on the main
2691 Do not define this pattern if all that must be done is the subtraction.
2692 Some machines require other operations such as stack probes or
2693 maintaining the back chain. Define this pattern to emit those
2694 operations in addition to updating the stack pointer.
2696 @cindex @code{probe} instruction pattern
2698 Some machines require instructions to be executed after space is
2699 allocated from the stack, for example to generate a reference at
2700 the bottom of the stack.
2702 If you need to emit instructions before the stack has been adjusted,
2703 put them into the @samp{allocate_stack} pattern. Otherwise, define
2704 this pattern to emit the required instructions.
2706 No operands are provided.
2708 @cindex @code{check_stack} instruction pattern
2709 @item @samp{check_stack}
2710 If stack checking cannot be done on your system by probing the stack with
2711 a load or store instruction (@pxref{Stack Checking}), define this pattern
2712 to perform the needed check and signaling an error if the stack
2713 has overflowed. The single operand is the location in the stack furthest
2714 from the current stack pointer that you need to validate. Normally,
2715 on machines where this pattern is needed, you would obtain the stack
2716 limit from a global or thread-specific variable or register.
2718 @cindex @code{nonlocal_goto} instruction pattern
2719 @item @samp{nonlocal_goto}
2720 Emit code to generate a non-local goto, e.g., a jump from one function
2721 to a label in an outer function. This pattern has four arguments,
2722 each representing a value to be used in the jump. The first
2723 argument is to be loaded into the frame pointer, the second is
2724 the address to branch to (code to dispatch to the actual label),
2725 the third is the address of a location where the stack is saved,
2726 and the last is the address of the label, to be placed in the
2727 location for the incoming static chain.
2729 On most machines you need not define this pattern, since GNU CC will
2730 already generate the correct code, which is to load the frame pointer
2731 and static chain, restore the stack (using the
2732 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2733 to the dispatcher. You need only define this pattern if this code will
2734 not work on your machine.
2736 @cindex @code{nonlocal_goto_receiver} instruction pattern
2737 @item @samp{nonlocal_goto_receiver}
2738 This pattern, if defined, contains code needed at the target of a
2739 nonlocal goto after the code already generated by GNU CC. You will not
2740 normally need to define this pattern. A typical reason why you might
2741 need this pattern is if some value, such as a pointer to a global table,
2742 must be restored when the frame pointer is restored. Note that a nonlocal
2743 goto only occurs within a unit-of-translation, so a global table pointer
2744 that is shared by all functions of a given module need not be restored.
2745 There are no arguments.
2747 @cindex @code{exception_receiver} instruction pattern
2748 @item @samp{exception_receiver}
2749 This pattern, if defined, contains code needed at the site of an
2750 exception handler that isn't needed at the site of a nonlocal goto. You
2751 will not normally need to define this pattern. A typical reason why you
2752 might need this pattern is if some value, such as a pointer to a global
2753 table, must be restored after control flow is branched to the handler of
2754 an exception. There are no arguments.
2756 @cindex @code{builtin_setjmp_setup} instruction pattern
2757 @item @samp{builtin_setjmp_setup}
2758 This pattern, if defined, contains additional code needed to initialize
2759 the @code{jmp_buf}. You will not normally need to define this pattern.
2760 A typical reason why you might need this pattern is if some value, such
2761 as a pointer to a global table, must be restored. Though it is
2762 preferred that the pointer value be recalculated if possible (given the
2763 address of a label for instance). The single argument is a pointer to
2764 the @code{jmp_buf}. Note that the buffer is five words long and that
2765 the first three are normally used by the generic mechanism.
2767 @cindex @code{builtin_setjmp_receiver} instruction pattern
2768 @item @samp{builtin_setjmp_receiver}
2769 This pattern, if defined, contains code needed at the site of an
2770 builtin setjmp that isn't needed at the site of a nonlocal goto. You
2771 will not normally need to define this pattern. A typical reason why you
2772 might need this pattern is if some value, such as a pointer to a global
2773 table, must be restored. It takes one argument, which is the label
2774 to which builtin_longjmp transfered control; this pattern may be emitted
2775 at a small offset from that label.
2777 @cindex @code{builtin_longjmp} instruction pattern
2778 @item @samp{builtin_longjmp}
2779 This pattern, if defined, performs the entire action of the longjmp.
2780 You will not normally need to define this pattern unless you also define
2781 @code{builtin_setjmp_setup}. The single argument is a pointer to the
2784 @cindex @code{eh_epilogue} instruction pattern
2785 @item @samp{eh_epilogue}
2786 This pattern, if defined, affects the way @code{__builtin_eh_return},
2787 and thence @code{__throw} are built. It is intended to allow communication
2788 between the exception handling machinery and the normal epilogue code
2791 The pattern takes three arguments. The first is the exception context
2792 pointer. This will have already been copied to the function return
2793 register appropriate for a pointer; normally this can be ignored. The
2794 second argument is an offset to be added to the stack pointer. It will
2795 have been copied to some arbitrary call-clobbered hard reg so that it
2796 will survive until after reload to when the normal epilogue is generated.
2797 The final argument is the address of the exception handler to which
2798 the function should return. This will normally need to copied by the
2799 pattern to some special register.
2801 This pattern must be defined if @code{RETURN_ADDR_RTX} does not yield
2802 something that can be reliably and permanently modified, i.e. a fixed
2803 hard register or a stack memory reference.
2805 @cindex @code{prologue} instruction pattern
2806 @item @samp{prologue}
2807 This pattern, if defined, emits RTL for entry to a function. The function
2808 entry is responsible for setting up the stack frame, initializing the frame
2809 pointer register, saving callee saved registers, etc.
2811 Using a prologue pattern is generally preferred over defining
2812 @code{FUNCTION_PROLOGUE} to emit assembly code for the prologue.
2814 The @code{prologue} pattern is particularly useful for targets which perform
2815 instruction scheduling.
2817 @cindex @code{epilogue} instruction pattern
2818 @item @samp{epilogue}
2819 This pattern, if defined, emits RTL for exit from a function. The function
2820 exit is responsible for deallocating the stack frame, restoring callee saved
2821 registers and emitting the return instruction.
2823 Using an epilogue pattern is generally preferred over defining
2824 @code{FUNCTION_EPILOGUE} to emit assembly code for the prologue.
2826 The @code{epilogue} pattern is particularly useful for targets which perform
2827 instruction scheduling or which have delay slots for their return instruction.
2829 @cindex @code{sibcall_epilogue} instruction pattern
2830 @item @samp{sibcall_epilogue}
2831 This pattern, if defined, emits RTL for exit from a function without the final
2832 branch back to the calling function. This pattern will be emitted before any
2833 sibling call (aka tail call) sites.
2835 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
2836 parameter passing or any stack slots for arguments passed to the current
2839 @cindex @code{trap} instruction pattern
2841 This pattern, if defined, signals an error, typically by causing some
2842 kind of signal to be raised. Among other places, it is used by the Java
2843 frontend to signal `invalid array index' exceptions.
2845 @cindex @code{conditional_trap} instruction pattern
2846 @item @samp{conditional_trap}
2847 Conditional trap instruction. Operand 0 is a piece of RTL which
2848 performs a comparison. Operand 1 is the trap code, an integer.
2850 A typical @code{conditional_trap} pattern looks like
2853 (define_insn "conditional_trap"
2854 [(trap_if (match_operator 0 "trap_operator"
2855 [(cc0) (const_int 0)])
2856 (match_operand 1 "const_int_operand" "i"))]
2863 @node Pattern Ordering
2864 @section When the Order of Patterns Matters
2865 @cindex Pattern Ordering
2866 @cindex Ordering of Patterns
2868 Sometimes an insn can match more than one instruction pattern. Then the
2869 pattern that appears first in the machine description is the one used.
2870 Therefore, more specific patterns (patterns that will match fewer things)
2871 and faster instructions (those that will produce better code when they
2872 do match) should usually go first in the description.
2874 In some cases the effect of ordering the patterns can be used to hide
2875 a pattern when it is not valid. For example, the 68000 has an
2876 instruction for converting a fullword to floating point and another
2877 for converting a byte to floating point. An instruction converting
2878 an integer to floating point could match either one. We put the
2879 pattern to convert the fullword first to make sure that one will
2880 be used rather than the other. (Otherwise a large integer might
2881 be generated as a single-byte immediate quantity, which would not work.)
2882 Instead of using this pattern ordering it would be possible to make the
2883 pattern for convert-a-byte smart enough to deal properly with any
2886 @node Dependent Patterns
2887 @section Interdependence of Patterns
2888 @cindex Dependent Patterns
2889 @cindex Interdependence of Patterns
2891 Every machine description must have a named pattern for each of the
2892 conditional branch names @samp{b@var{cond}}. The recognition template
2893 must always have the form
2897 (if_then_else (@var{cond} (cc0) (const_int 0))
2898 (label_ref (match_operand 0 "" ""))
2903 In addition, every machine description must have an anonymous pattern
2904 for each of the possible reverse-conditional branches. Their templates
2909 (if_then_else (@var{cond} (cc0) (const_int 0))
2911 (label_ref (match_operand 0 "" ""))))
2915 They are necessary because jump optimization can turn direct-conditional
2916 branches into reverse-conditional branches.
2918 It is often convenient to use the @code{match_operator} construct to
2919 reduce the number of patterns that must be specified for branches. For
2925 (if_then_else (match_operator 0 "comparison_operator"
2926 [(cc0) (const_int 0)])
2928 (label_ref (match_operand 1 "" ""))))]
2933 In some cases machines support instructions identical except for the
2934 machine mode of one or more operands. For example, there may be
2935 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
2939 (set (match_operand:SI 0 @dots{})
2940 (extend:SI (match_operand:HI 1 @dots{})))
2942 (set (match_operand:SI 0 @dots{})
2943 (extend:SI (match_operand:QI 1 @dots{})))
2947 Constant integers do not specify a machine mode, so an instruction to
2948 extend a constant value could match either pattern. The pattern it
2949 actually will match is the one that appears first in the file. For correct
2950 results, this must be the one for the widest possible mode (@code{HImode},
2951 here). If the pattern matches the @code{QImode} instruction, the results
2952 will be incorrect if the constant value does not actually fit that mode.
2954 Such instructions to extend constants are rarely generated because they are
2955 optimized away, but they do occasionally happen in nonoptimized
2958 If a constraint in a pattern allows a constant, the reload pass may
2959 replace a register with a constant permitted by the constraint in some
2960 cases. Similarly for memory references. Because of this substitution,
2961 you should not provide separate patterns for increment and decrement
2962 instructions. Instead, they should be generated from the same pattern
2963 that supports register-register add insns by examining the operands and
2964 generating the appropriate machine instruction.
2967 @section Defining Jump Instruction Patterns
2968 @cindex jump instruction patterns
2969 @cindex defining jump instruction patterns
2971 For most machines, GNU CC assumes that the machine has a condition code.
2972 A comparison insn sets the condition code, recording the results of both
2973 signed and unsigned comparison of the given operands. A separate branch
2974 insn tests the condition code and branches or not according its value.
2975 The branch insns come in distinct signed and unsigned flavors. Many
2976 common machines, such as the Vax, the 68000 and the 32000, work this
2979 Some machines have distinct signed and unsigned compare instructions, and
2980 only one set of conditional branch instructions. The easiest way to handle
2981 these machines is to treat them just like the others until the final stage
2982 where assembly code is written. At this time, when outputting code for the
2983 compare instruction, peek ahead at the following branch using
2984 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
2985 being output, in the output-writing code in an instruction pattern.) If
2986 the RTL says that is an unsigned branch, output an unsigned compare;
2987 otherwise output a signed compare. When the branch itself is output, you
2988 can treat signed and unsigned branches identically.
2990 The reason you can do this is that GNU CC always generates a pair of
2991 consecutive RTL insns, possibly separated by @code{note} insns, one to
2992 set the condition code and one to test it, and keeps the pair inviolate
2995 To go with this technique, you must define the machine-description macro
2996 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
2997 compare instruction is superfluous.
2999 Some machines have compare-and-branch instructions and no condition code.
3000 A similar technique works for them. When it is time to ``output'' a
3001 compare instruction, record its operands in two static variables. When
3002 outputting the branch-on-condition-code instruction that follows, actually
3003 output a compare-and-branch instruction that uses the remembered operands.
3005 It also works to define patterns for compare-and-branch instructions.
3006 In optimizing compilation, the pair of compare and branch instructions
3007 will be combined according to these patterns. But this does not happen
3008 if optimization is not requested. So you must use one of the solutions
3009 above in addition to any special patterns you define.
3011 In many RISC machines, most instructions do not affect the condition
3012 code and there may not even be a separate condition code register. On
3013 these machines, the restriction that the definition and use of the
3014 condition code be adjacent insns is not necessary and can prevent
3015 important optimizations. For example, on the IBM RS/6000, there is a
3016 delay for taken branches unless the condition code register is set three
3017 instructions earlier than the conditional branch. The instruction
3018 scheduler cannot perform this optimization if it is not permitted to
3019 separate the definition and use of the condition code register.
3021 On these machines, do not use @code{(cc0)}, but instead use a register
3022 to represent the condition code. If there is a specific condition code
3023 register in the machine, use a hard register. If the condition code or
3024 comparison result can be placed in any general register, or if there are
3025 multiple condition registers, use a pseudo register.
3027 @findex prev_cc0_setter
3028 @findex next_cc0_user
3029 On some machines, the type of branch instruction generated may depend on
3030 the way the condition code was produced; for example, on the 68k and
3031 Sparc, setting the condition code directly from an add or subtract
3032 instruction does not clear the overflow bit the way that a test
3033 instruction does, so a different branch instruction must be used for
3034 some conditional branches. For machines that use @code{(cc0)}, the set
3035 and use of the condition code must be adjacent (separated only by
3036 @code{note} insns) allowing flags in @code{cc_status} to be used.
3037 (@xref{Condition Code}.) Also, the comparison and branch insns can be
3038 located from each other by using the functions @code{prev_cc0_setter}
3039 and @code{next_cc0_user}.
3041 However, this is not true on machines that do not use @code{(cc0)}. On
3042 those machines, no assumptions can be made about the adjacency of the
3043 compare and branch insns and the above methods cannot be used. Instead,
3044 we use the machine mode of the condition code register to record
3045 different formats of the condition code register.
3047 Registers used to store the condition code value should have a mode that
3048 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
3049 additional modes are required (as for the add example mentioned above in
3050 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
3051 additional modes required (@pxref{Condition Code}). Also define
3052 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
3054 If it is known during RTL generation that a different mode will be
3055 required (for example, if the machine has separate compare instructions
3056 for signed and unsigned quantities, like most IBM processors), they can
3057 be specified at that time.
3059 If the cases that require different modes would be made by instruction
3060 combination, the macro @code{SELECT_CC_MODE} determines which machine
3061 mode should be used for the comparison result. The patterns should be
3062 written using that mode. To support the case of the add on the Sparc
3063 discussed above, we have the pattern
3067 [(set (reg:CC_NOOV 0)
3069 (plus:SI (match_operand:SI 0 "register_operand" "%r")
3070 (match_operand:SI 1 "arith_operand" "rI"))
3076 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
3077 for comparisons whose argument is a @code{plus}.
3079 @node Insn Canonicalizations
3080 @section Canonicalization of Instructions
3081 @cindex canonicalization of instructions
3082 @cindex insn canonicalization
3084 There are often cases where multiple RTL expressions could represent an
3085 operation performed by a single machine instruction. This situation is
3086 most commonly encountered with logical, branch, and multiply-accumulate
3087 instructions. In such cases, the compiler attempts to convert these
3088 multiple RTL expressions into a single canonical form to reduce the
3089 number of insn patterns required.
3091 In addition to algebraic simplifications, following canonicalizations
3096 For commutative and comparison operators, a constant is always made the
3097 second operand. If a machine only supports a constant as the second
3098 operand, only patterns that match a constant in the second operand need
3101 @cindex @code{neg}, canonicalization of
3102 @cindex @code{not}, canonicalization of
3103 @cindex @code{mult}, canonicalization of
3104 @cindex @code{plus}, canonicalization of
3105 @cindex @code{minus}, canonicalization of
3106 For these operators, if only one operand is a @code{neg}, @code{not},
3107 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
3110 @cindex @code{compare}, canonicalization of
3112 For the @code{compare} operator, a constant is always the second operand
3113 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
3114 machines, there are rare cases where the compiler might want to construct
3115 a @code{compare} with a constant as the first operand. However, these
3116 cases are not common enough for it to be worthwhile to provide a pattern
3117 matching a constant as the first operand unless the machine actually has
3118 such an instruction.
3120 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
3121 @code{minus} is made the first operand under the same conditions as
3125 @code{(minus @var{x} (const_int @var{n}))} is converted to
3126 @code{(plus @var{x} (const_int @var{-n}))}.
3129 Within address computations (i.e., inside @code{mem}), a left shift is
3130 converted into the appropriate multiplication by a power of two.
3132 @cindex @code{ior}, canonicalization of
3133 @cindex @code{and}, canonicalization of
3134 @cindex De Morgan's law
3136 De`Morgan's Law is used to move bitwise negation inside a bitwise
3137 logical-and or logical-or operation. If this results in only one
3138 operand being a @code{not} expression, it will be the first one.
3140 A machine that has an instruction that performs a bitwise logical-and of one
3141 operand with the bitwise negation of the other should specify the pattern
3142 for that instruction as
3146 [(set (match_operand:@var{m} 0 @dots{})
3147 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3148 (match_operand:@var{m} 2 @dots{})))]
3154 Similarly, a pattern for a ``NAND'' instruction should be written
3158 [(set (match_operand:@var{m} 0 @dots{})
3159 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3160 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3165 In both cases, it is not necessary to include patterns for the many
3166 logically equivalent RTL expressions.
3168 @cindex @code{xor}, canonicalization of
3170 The only possible RTL expressions involving both bitwise exclusive-or
3171 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3172 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
3175 The sum of three items, one of which is a constant, will only appear in
3179 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3183 On machines that do not use @code{cc0},
3184 @code{(compare @var{x} (const_int 0))} will be converted to
3187 @cindex @code{zero_extract}, canonicalization of
3188 @cindex @code{sign_extract}, canonicalization of
3190 Equality comparisons of a group of bits (usually a single bit) with zero
3191 will be written using @code{zero_extract} rather than the equivalent
3192 @code{and} or @code{sign_extract} operations.
3196 @node Expander Definitions
3197 @section Defining RTL Sequences for Code Generation
3198 @cindex expander definitions
3199 @cindex code generation RTL sequences
3200 @cindex defining RTL sequences for code generation
3202 On some target machines, some standard pattern names for RTL generation
3203 cannot be handled with single insn, but a sequence of RTL insns can
3204 represent them. For these target machines, you can write a
3205 @code{define_expand} to specify how to generate the sequence of RTL.
3207 @findex define_expand
3208 A @code{define_expand} is an RTL expression that looks almost like a
3209 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3210 only for RTL generation and it can produce more than one RTL insn.
3212 A @code{define_expand} RTX has four operands:
3216 The name. Each @code{define_expand} must have a name, since the only
3217 use for it is to refer to it by name.
3220 The RTL template. This is a vector of RTL expressions representing
3221 a sequence of separate instructions. Unlike @code{define_insn}, there
3222 is no implicit surrounding @code{PARALLEL}.
3225 The condition, a string containing a C expression. This expression is
3226 used to express how the availability of this pattern depends on
3227 subclasses of target machine, selected by command-line options when GNU
3228 CC is run. This is just like the condition of a @code{define_insn} that
3229 has a standard name. Therefore, the condition (if present) may not
3230 depend on the data in the insn being matched, but only the
3231 target-machine-type flags. The compiler needs to test these conditions
3232 during initialization in order to learn exactly which named instructions
3233 are available in a particular run.
3236 The preparation statements, a string containing zero or more C
3237 statements which are to be executed before RTL code is generated from
3240 Usually these statements prepare temporary registers for use as
3241 internal operands in the RTL template, but they can also generate RTL
3242 insns directly by calling routines such as @code{emit_insn}, etc.
3243 Any such insns precede the ones that come from the RTL template.
3246 Every RTL insn emitted by a @code{define_expand} must match some
3247 @code{define_insn} in the machine description. Otherwise, the compiler
3248 will crash when trying to generate code for the insn or trying to optimize
3251 The RTL template, in addition to controlling generation of RTL insns,
3252 also describes the operands that need to be specified when this pattern
3253 is used. In particular, it gives a predicate for each operand.
3255 A true operand, which needs to be specified in order to generate RTL from
3256 the pattern, should be described with a @code{match_operand} in its first
3257 occurrence in the RTL template. This enters information on the operand's
3258 predicate into the tables that record such things. GNU CC uses the
3259 information to preload the operand into a register if that is required for
3260 valid RTL code. If the operand is referred to more than once, subsequent
3261 references should use @code{match_dup}.
3263 The RTL template may also refer to internal ``operands'' which are
3264 temporary registers or labels used only within the sequence made by the
3265 @code{define_expand}. Internal operands are substituted into the RTL
3266 template with @code{match_dup}, never with @code{match_operand}. The
3267 values of the internal operands are not passed in as arguments by the
3268 compiler when it requests use of this pattern. Instead, they are computed
3269 within the pattern, in the preparation statements. These statements
3270 compute the values and store them into the appropriate elements of
3271 @code{operands} so that @code{match_dup} can find them.
3273 There are two special macros defined for use in the preparation statements:
3274 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3281 Use the @code{DONE} macro to end RTL generation for the pattern. The
3282 only RTL insns resulting from the pattern on this occasion will be
3283 those already emitted by explicit calls to @code{emit_insn} within the
3284 preparation statements; the RTL template will not be generated.
3288 Make the pattern fail on this occasion. When a pattern fails, it means
3289 that the pattern was not truly available. The calling routines in the
3290 compiler will try other strategies for code generation using other patterns.
3292 Failure is currently supported only for binary (addition, multiplication,
3293 shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
3297 If the preparation falls through (invokes neither @code{DONE} nor
3298 @code{FAIL}), then the @code{define_expand} acts like a
3299 @code{define_insn} in that the RTL template is used to generate the
3302 The RTL template is not used for matching, only for generating the
3303 initial insn list. If the preparation statement always invokes
3304 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
3305 list of operands, such as this example:
3309 (define_expand "addsi3"
3310 [(match_operand:SI 0 "register_operand" "")
3311 (match_operand:SI 1 "register_operand" "")
3312 (match_operand:SI 2 "register_operand" "")]
3318 handle_add (operands[0], operands[1], operands[2]);
3324 Here is an example, the definition of left-shift for the SPUR chip:
3328 (define_expand "ashlsi3"
3329 [(set (match_operand:SI 0 "register_operand" "")
3333 (match_operand:SI 1 "register_operand" "")
3334 (match_operand:SI 2 "nonmemory_operand" "")))]
3343 if (GET_CODE (operands[2]) != CONST_INT
3344 || (unsigned) INTVAL (operands[2]) > 3)
3351 This example uses @code{define_expand} so that it can generate an RTL insn
3352 for shifting when the shift-count is in the supported range of 0 to 3 but
3353 fail in other cases where machine insns aren't available. When it fails,
3354 the compiler tries another strategy using different patterns (such as, a
3357 If the compiler were able to handle nontrivial condition-strings in
3358 patterns with names, then it would be possible to use a
3359 @code{define_insn} in that case. Here is another case (zero-extension
3360 on the 68000) which makes more use of the power of @code{define_expand}:
3363 (define_expand "zero_extendhisi2"
3364 [(set (match_operand:SI 0 "general_operand" "")
3366 (set (strict_low_part
3370 (match_operand:HI 1 "general_operand" ""))]
3372 "operands[1] = make_safe_from (operands[1], operands[0]);")
3376 @findex make_safe_from
3377 Here two RTL insns are generated, one to clear the entire output operand
3378 and the other to copy the input operand into its low half. This sequence
3379 is incorrect if the input operand refers to [the old value of] the output
3380 operand, so the preparation statement makes sure this isn't so. The
3381 function @code{make_safe_from} copies the @code{operands[1]} into a
3382 temporary register if it refers to @code{operands[0]}. It does this
3383 by emitting another RTL insn.
3385 Finally, a third example shows the use of an internal operand.
3386 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3387 against a halfword mask. But this mask cannot be represented by a
3388 @code{const_int} because the constant value is too large to be legitimate
3389 on this machine. So it must be copied into a register with
3390 @code{force_reg} and then the register used in the @code{and}.
3393 (define_expand "zero_extendhisi2"
3394 [(set (match_operand:SI 0 "register_operand" "")
3396 (match_operand:HI 1 "register_operand" "")
3401 = force_reg (SImode, GEN_INT (65535)); ")
3404 @strong{Note:} If the @code{define_expand} is used to serve a
3405 standard binary or unary arithmetic operation or a bitfield operation,
3406 then the last insn it generates must not be a @code{code_label},
3407 @code{barrier} or @code{note}. It must be an @code{insn},
3408 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3409 at the end, emit an insn to copy the result of the operation into
3410 itself. Such an insn will generate no code, but it can avoid problems
3411 in the compiler.@refill
3413 @node Insn Splitting
3414 @section Defining How to Split Instructions
3415 @cindex insn splitting
3416 @cindex instruction splitting
3417 @cindex splitting instructions
3419 There are two cases where you should specify how to split a pattern into
3420 multiple insns. On machines that have instructions requiring delay
3421 slots (@pxref{Delay Slots}) or that have instructions whose output is
3422 not available for multiple cycles (@pxref{Function Units}), the compiler
3423 phases that optimize these cases need to be able to move insns into
3424 one-instruction delay slots. However, some insns may generate more than one
3425 machine instruction. These insns cannot be placed into a delay slot.
3427 Often you can rewrite the single insn as a list of individual insns,
3428 each corresponding to one machine instruction. The disadvantage of
3429 doing so is that it will cause the compilation to be slower and require
3430 more space. If the resulting insns are too complex, it may also
3431 suppress some optimizations. The compiler splits the insn if there is a
3432 reason to believe that it might improve instruction or delay slot
3435 The insn combiner phase also splits putative insns. If three insns are
3436 merged into one insn with a complex expression that cannot be matched by
3437 some @code{define_insn} pattern, the combiner phase attempts to split
3438 the complex pattern into two insns that are recognized. Usually it can
3439 break the complex pattern into two patterns by splitting out some
3440 subexpression. However, in some other cases, such as performing an
3441 addition of a large constant in two insns on a RISC machine, the way to
3442 split the addition into two insns is machine-dependent.
3444 @findex define_split
3445 The @code{define_split} definition tells the compiler how to split a
3446 complex insn into several simpler insns. It looks like this:
3450 [@var{insn-pattern}]
3452 [@var{new-insn-pattern-1}
3453 @var{new-insn-pattern-2}
3455 "@var{preparation statements}")
3458 @var{insn-pattern} is a pattern that needs to be split and
3459 @var{condition} is the final condition to be tested, as in a
3460 @code{define_insn}. When an insn matching @var{insn-pattern} and
3461 satisfying @var{condition} is found, it is replaced in the insn list
3462 with the insns given by @var{new-insn-pattern-1},
3463 @var{new-insn-pattern-2}, etc.
3465 The @var{preparation statements} are similar to those statements that
3466 are specified for @code{define_expand} (@pxref{Expander Definitions})
3467 and are executed before the new RTL is generated to prepare for the
3468 generated code or emit some insns whose pattern is not fixed. Unlike
3469 those in @code{define_expand}, however, these statements must not
3470 generate any new pseudo-registers. Once reload has completed, they also
3471 must not allocate any space in the stack frame.
3473 Patterns are matched against @var{insn-pattern} in two different
3474 circumstances. If an insn needs to be split for delay slot scheduling
3475 or insn scheduling, the insn is already known to be valid, which means
3476 that it must have been matched by some @code{define_insn} and, if
3477 @code{reload_completed} is non-zero, is known to satisfy the constraints
3478 of that @code{define_insn}. In that case, the new insn patterns must
3479 also be insns that are matched by some @code{define_insn} and, if
3480 @code{reload_completed} is non-zero, must also satisfy the constraints
3481 of those definitions.
3483 As an example of this usage of @code{define_split}, consider the following
3484 example from @file{a29k.md}, which splits a @code{sign_extend} from
3485 @code{HImode} to @code{SImode} into a pair of shift insns:
3489 [(set (match_operand:SI 0 "gen_reg_operand" "")
3490 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3493 (ashift:SI (match_dup 1)
3496 (ashiftrt:SI (match_dup 0)
3499 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3502 When the combiner phase tries to split an insn pattern, it is always the
3503 case that the pattern is @emph{not} matched by any @code{define_insn}.
3504 The combiner pass first tries to split a single @code{set} expression
3505 and then the same @code{set} expression inside a @code{parallel}, but
3506 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3507 register. In these cases, the combiner expects exactly two new insn
3508 patterns to be generated. It will verify that these patterns match some
3509 @code{define_insn} definitions, so you need not do this test in the
3510 @code{define_split} (of course, there is no point in writing a
3511 @code{define_split} that will never produce insns that match).
3513 Here is an example of this use of @code{define_split}, taken from
3518 [(set (match_operand:SI 0 "gen_reg_operand" "")
3519 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3520 (match_operand:SI 2 "non_add_cint_operand" "")))]
3522 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3523 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3526 int low = INTVAL (operands[2]) & 0xffff;
3527 int high = (unsigned) INTVAL (operands[2]) >> 16;
3530 high++, low |= 0xffff0000;
3532 operands[3] = GEN_INT (high << 16);
3533 operands[4] = GEN_INT (low);
3537 Here the predicate @code{non_add_cint_operand} matches any
3538 @code{const_int} that is @emph{not} a valid operand of a single add
3539 insn. The add with the smaller displacement is written so that it
3540 can be substituted into the address of a subsequent operation.
3542 An example that uses a scratch register, from the same file, generates
3543 an equality comparison of a register and a large constant:
3547 [(set (match_operand:CC 0 "cc_reg_operand" "")
3548 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3549 (match_operand:SI 2 "non_short_cint_operand" "")))
3550 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3551 "find_single_use (operands[0], insn, 0)
3552 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3553 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3554 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3555 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3558 /* Get the constant we are comparing against, C, and see what it
3559 looks like sign-extended to 16 bits. Then see what constant
3560 could be XOR'ed with C to get the sign-extended value. */
3562 int c = INTVAL (operands[2]);
3563 int sextc = (c << 16) >> 16;
3564 int xorv = c ^ sextc;
3566 operands[4] = GEN_INT (xorv);
3567 operands[5] = GEN_INT (sextc);
3571 To avoid confusion, don't write a single @code{define_split} that
3572 accepts some insns that match some @code{define_insn} as well as some
3573 insns that don't. Instead, write two separate @code{define_split}
3574 definitions, one for the insns that are valid and one for the insns that
3577 For the common case where the pattern of a define_split exactly matches the
3578 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
3582 (define_insn_and_split
3583 [@var{insn-pattern}]
3585 "@var{output-template}"
3586 "@var{split-condition}"
3587 [@var{new-insn-pattern-1}
3588 @var{new-insn-pattern-2}
3590 "@var{preparation statements}"
3591 [@var{insn-attributes}])
3595 @var{insn-pattern}, @var{condition}, @var{output-template}, and
3596 @var{insn-attributes} are used as in @code{define_insn}. The
3597 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
3598 in a @code{define_split}. The @var{split-condition} is also used as in
3599 @code{define_split}, with the additional behavior that if the condition starts
3600 with @samp{&&}, the condition used for the split will be the constructed as a
3601 logical "and" of the split condition with the insn condition. For example,
3605 (define_insn_and_split "zero_extendhisi2_and"
3606 [(set (match_operand:SI 0 "register_operand" "=r")
3607 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3608 (clobber (reg:CC 17))]
3609 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3611 "&& reload_completed"
3612 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3613 (clobber (reg:CC 17))])]
3615 [(set_attr "type" "alu1")])
3619 In this case, the actual split condition will be
3620 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed."
3622 The @code{define_insn_and_split} construction provides exactly the same
3623 functionality as two separate @code{define_insn} and @code{define_split}
3624 patterns. It exists for compactness, and as a maintenance tool to prevent
3625 having to ensure the two patterns' templates match.
3627 @node Peephole Definitions
3628 @section Machine-Specific Peephole Optimizers
3629 @cindex peephole optimizer definitions
3630 @cindex defining peephole optimizers
3632 In addition to instruction patterns the @file{md} file may contain
3633 definitions of machine-specific peephole optimizations.
3635 The combiner does not notice certain peephole optimizations when the data
3636 flow in the program does not suggest that it should try them. For example,
3637 sometimes two consecutive insns related in purpose can be combined even
3638 though the second one does not appear to use a register computed in the
3639 first one. A machine-specific peephole optimizer can detect such
3642 There are two forms of peephole definitions that may be used. The
3643 original @code{define_peephole} is run at assembly output time to
3644 match insns and substitute assembly text. Use of @code{define_peephole}
3647 A newer @code{define_peephole2} matches insns and substitutes new
3648 insns. The @code{peephole2} pass is run after register allocation
3649 but before scheduling, which may result in much better code for
3650 targets that do scheduling.
3653 * define_peephole:: RTL to Text Peephole Optimizers
3654 * define_peephole2:: RTL to RTL Peephole Optimizers
3657 @node define_peephole
3658 @subsection RTL to Text Peephole Optimizers
3659 @findex define_peephole
3662 A definition looks like this:
3666 [@var{insn-pattern-1}
3667 @var{insn-pattern-2}
3671 "@var{optional insn-attributes}")
3675 The last string operand may be omitted if you are not using any
3676 machine-specific information in this machine description. If present,
3677 it must obey the same rules as in a @code{define_insn}.
3679 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
3680 consecutive insns. The optimization applies to a sequence of insns when
3681 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
3682 the next, and so on.@refill
3684 Each of the insns matched by a peephole must also match a
3685 @code{define_insn}. Peepholes are checked only at the last stage just
3686 before code generation, and only optionally. Therefore, any insn which
3687 would match a peephole but no @code{define_insn} will cause a crash in code
3688 generation in an unoptimized compilation, or at various optimization
3691 The operands of the insns are matched with @code{match_operands},
3692 @code{match_operator}, and @code{match_dup}, as usual. What is not
3693 usual is that the operand numbers apply to all the insn patterns in the
3694 definition. So, you can check for identical operands in two insns by
3695 using @code{match_operand} in one insn and @code{match_dup} in the
3698 The operand constraints used in @code{match_operand} patterns do not have
3699 any direct effect on the applicability of the peephole, but they will
3700 be validated afterward, so make sure your constraints are general enough
3701 to apply whenever the peephole matches. If the peephole matches
3702 but the constraints are not satisfied, the compiler will crash.
3704 It is safe to omit constraints in all the operands of the peephole; or
3705 you can write constraints which serve as a double-check on the criteria
3708 Once a sequence of insns matches the patterns, the @var{condition} is
3709 checked. This is a C expression which makes the final decision whether to
3710 perform the optimization (we do so if the expression is nonzero). If
3711 @var{condition} is omitted (in other words, the string is empty) then the
3712 optimization is applied to every sequence of insns that matches the
3715 The defined peephole optimizations are applied after register allocation
3716 is complete. Therefore, the peephole definition can check which
3717 operands have ended up in which kinds of registers, just by looking at
3720 @findex prev_active_insn
3721 The way to refer to the operands in @var{condition} is to write
3722 @code{operands[@var{i}]} for operand number @var{i} (as matched by
3723 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
3724 to refer to the last of the insns being matched; use
3725 @code{prev_active_insn} to find the preceding insns.
3727 @findex dead_or_set_p
3728 When optimizing computations with intermediate results, you can use
3729 @var{condition} to match only when the intermediate results are not used
3730 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
3731 @var{op})}, where @var{insn} is the insn in which you expect the value
3732 to be used for the last time (from the value of @code{insn}, together
3733 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
3734 value (from @code{operands[@var{i}]}).@refill
3736 Applying the optimization means replacing the sequence of insns with one
3737 new insn. The @var{template} controls ultimate output of assembler code
3738 for this combined insn. It works exactly like the template of a
3739 @code{define_insn}. Operand numbers in this template are the same ones
3740 used in matching the original sequence of insns.
3742 The result of a defined peephole optimizer does not need to match any of
3743 the insn patterns in the machine description; it does not even have an
3744 opportunity to match them. The peephole optimizer definition itself serves
3745 as the insn pattern to control how the insn is output.
3747 Defined peephole optimizers are run as assembler code is being output,
3748 so the insns they produce are never combined or rearranged in any way.
3750 Here is an example, taken from the 68000 machine description:
3754 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3755 (set (match_operand:DF 0 "register_operand" "=f")
3756 (match_operand:DF 1 "register_operand" "ad"))]
3757 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3761 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3763 output_asm_insn (\"move.l %1,(sp)\", xoperands);
3764 output_asm_insn (\"move.l %1,-(sp)\", operands);
3765 return \"fmove.d (sp)+,%0\";
3767 output_asm_insn (\"movel %1,sp@@\", xoperands);
3768 output_asm_insn (\"movel %1,sp@@-\", operands);
3769 return \"fmoved sp@@+,%0\";
3776 The effect of this optimization is to change
3802 If a peephole matches a sequence including one or more jump insns, you must
3803 take account of the flags such as @code{CC_REVERSED} which specify that the
3804 condition codes are represented in an unusual manner. The compiler
3805 automatically alters any ordinary conditional jumps which occur in such
3806 situations, but the compiler cannot alter jumps which have been replaced by
3807 peephole optimizations. So it is up to you to alter the assembler code
3808 that the peephole produces. Supply C code to write the assembler output,
3809 and in this C code check the condition code status flags and change the
3810 assembler code as appropriate.
3813 @var{insn-pattern-1} and so on look @emph{almost} like the second
3814 operand of @code{define_insn}. There is one important difference: the
3815 second operand of @code{define_insn} consists of one or more RTX's
3816 enclosed in square brackets. Usually, there is only one: then the same
3817 action can be written as an element of a @code{define_peephole}. But
3818 when there are multiple actions in a @code{define_insn}, they are
3819 implicitly enclosed in a @code{parallel}. Then you must explicitly
3820 write the @code{parallel}, and the square brackets within it, in the
3821 @code{define_peephole}. Thus, if an insn pattern looks like this,
3824 (define_insn "divmodsi4"
3825 [(set (match_operand:SI 0 "general_operand" "=d")
3826 (div:SI (match_operand:SI 1 "general_operand" "0")
3827 (match_operand:SI 2 "general_operand" "dmsK")))
3828 (set (match_operand:SI 3 "general_operand" "=d")
3829 (mod:SI (match_dup 1) (match_dup 2)))]
3831 "divsl%.l %2,%3:%0")
3835 then the way to mention this insn in a peephole is as follows:
3841 [(set (match_operand:SI 0 "general_operand" "=d")
3842 (div:SI (match_operand:SI 1 "general_operand" "0")
3843 (match_operand:SI 2 "general_operand" "dmsK")))
3844 (set (match_operand:SI 3 "general_operand" "=d")
3845 (mod:SI (match_dup 1) (match_dup 2)))])
3850 @node define_peephole2
3851 @subsection RTL to RTL Peephole Optimizers
3852 @findex define_peephole2
3854 The @code{define_peephole2} definition tells the compiler how to
3855 substitute one sequence of instructions for another sequence,
3856 what additional scratch registers may be needed and what their
3861 [@var{insn-pattern-1}
3862 @var{insn-pattern-2}
3865 [@var{new-insn-pattern-1}
3866 @var{new-insn-pattern-2}
3868 "@var{preparation statements}")
3871 The definition is almost identical to @code{define_split}
3872 (@pxref{Insn Splitting}) except that the pattern to match is not a
3873 single instruction, but a sequence of instructions.
3875 It is possible to request additional scratch registers for use in the
3876 output template. If appropriate registers are not free, the pattern
3877 will simply not match.
3879 @findex match_scratch
3881 Scratch registers are requested with a @code{match_scratch} pattern at
3882 the top level of the input pattern. The allocated register (initially) will
3883 be dead at the point requested within the original sequence. If the scratch
3884 is used at more than a single point, a @code{match_dup} pattern at the
3885 top level of the input pattern marks the last position in the input sequence
3886 at which the register must be available.
3888 Here is an example from the IA-32 machine description:
3892 [(match_scratch:SI 2 "r")
3893 (parallel [(set (match_operand:SI 0 "register_operand" "")
3894 (match_operator:SI 3 "arith_or_logical_operator"
3896 (match_operand:SI 1 "memory_operand" "")]))
3897 (clobber (reg:CC 17))])]
3898 "! optimize_size && ! TARGET_READ_MODIFY"
3899 [(set (match_dup 2) (match_dup 1))
3900 (parallel [(set (match_dup 0)
3901 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
3902 (clobber (reg:CC 17))])]
3907 This pattern tries to split a load from its use in the hopes that we'll be
3908 able to schedule around the memory load latency. It allocates a single
3909 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
3910 to be live only at the point just before the arithmetic.
3912 A real example requiring extended scratch lifetimes is harder to come by,
3913 so here's a silly made-up example:
3917 [(match_scratch:SI 4 "r")
3918 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
3919 (set (match_operand:SI 2 "" "") (match_dup 1))
3921 (set (match_operand:SI 3 "" "") (match_dup 1))]
3922 "@var{determine 1 does not overlap 0 and 2}"
3923 [(set (match_dup 4) (match_dup 1))
3924 (set (match_dup 0) (match_dup 4))
3925 (set (match_dup 2) (match_dup 4))]
3926 (set (match_dup 3) (match_dup 4))]
3931 If we had not added the @code{(match_dup 4)} in the middle of the input
3932 sequence, it might have been the case that the register we chose at the
3933 beginning of the sequence is killed by the first or second @code{set}.
3935 @node Insn Attributes
3936 @section Instruction Attributes
3937 @cindex insn attributes
3938 @cindex instruction attributes
3940 In addition to describing the instruction supported by the target machine,
3941 the @file{md} file also defines a group of @dfn{attributes} and a set of
3942 values for each. Every generated insn is assigned a value for each attribute.
3943 One possible attribute would be the effect that the insn has on the machine's
3944 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
3945 to track the condition codes.
3948 * Defining Attributes:: Specifying attributes and their values.
3949 * Expressions:: Valid expressions for attribute values.
3950 * Tagging Insns:: Assigning attribute values to insns.
3951 * Attr Example:: An example of assigning attributes.
3952 * Insn Lengths:: Computing the length of insns.
3953 * Constant Attributes:: Defining attributes that are constant.
3954 * Delay Slots:: Defining delay slots required for a machine.
3955 * Function Units:: Specifying information for insn scheduling.
3958 @node Defining Attributes
3959 @subsection Defining Attributes and their Values
3960 @cindex defining attributes and their values
3961 @cindex attributes, defining
3964 The @code{define_attr} expression is used to define each attribute required
3965 by the target machine. It looks like:
3968 (define_attr @var{name} @var{list-of-values} @var{default})
3971 @var{name} is a string specifying the name of the attribute being defined.
3973 @var{list-of-values} is either a string that specifies a comma-separated
3974 list of values that can be assigned to the attribute, or a null string to
3975 indicate that the attribute takes numeric values.
3977 @var{default} is an attribute expression that gives the value of this
3978 attribute for insns that match patterns whose definition does not include
3979 an explicit value for this attribute. @xref{Attr Example}, for more
3980 information on the handling of defaults. @xref{Constant Attributes},
3981 for information on attributes that do not depend on any particular insn.
3984 For each defined attribute, a number of definitions are written to the
3985 @file{insn-attr.h} file. For cases where an explicit set of values is
3986 specified for an attribute, the following are defined:
3990 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
3993 An enumeral class is defined for @samp{attr_@var{name}} with
3994 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
3995 the attribute name and value are first converted to upper case.
3998 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
3999 returns the attribute value for that insn.
4002 For example, if the following is present in the @file{md} file:
4005 (define_attr "type" "branch,fp,load,store,arith" @dots{})
4009 the following lines will be written to the file @file{insn-attr.h}.
4012 #define HAVE_ATTR_type
4013 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
4014 TYPE_STORE, TYPE_ARITH@};
4015 extern enum attr_type get_attr_type ();
4018 If the attribute takes numeric values, no @code{enum} type will be
4019 defined and the function to obtain the attribute's value will return
4023 @subsection Attribute Expressions
4024 @cindex attribute expressions
4026 RTL expressions used to define attributes use the codes described above
4027 plus a few specific to attribute definitions, to be discussed below.
4028 Attribute value expressions must have one of the following forms:
4031 @cindex @code{const_int} and attributes
4032 @item (const_int @var{i})
4033 The integer @var{i} specifies the value of a numeric attribute. @var{i}
4034 must be non-negative.
4036 The value of a numeric attribute can be specified either with a
4037 @code{const_int}, or as an integer represented as a string in
4038 @code{const_string}, @code{eq_attr} (see below), @code{attr},
4039 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
4040 overrides on specific instructions (@pxref{Tagging Insns}).
4042 @cindex @code{const_string} and attributes
4043 @item (const_string @var{value})
4044 The string @var{value} specifies a constant attribute value.
4045 If @var{value} is specified as @samp{"*"}, it means that the default value of
4046 the attribute is to be used for the insn containing this expression.
4047 @samp{"*"} obviously cannot be used in the @var{default} expression
4048 of a @code{define_attr}.@refill
4050 If the attribute whose value is being specified is numeric, @var{value}
4051 must be a string containing a non-negative integer (normally
4052 @code{const_int} would be used in this case). Otherwise, it must
4053 contain one of the valid values for the attribute.
4055 @cindex @code{if_then_else} and attributes
4056 @item (if_then_else @var{test} @var{true-value} @var{false-value})
4057 @var{test} specifies an attribute test, whose format is defined below.
4058 The value of this expression is @var{true-value} if @var{test} is true,
4059 otherwise it is @var{false-value}.
4061 @cindex @code{cond} and attributes
4062 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
4063 The first operand of this expression is a vector containing an even
4064 number of expressions and consisting of pairs of @var{test} and @var{value}
4065 expressions. The value of the @code{cond} expression is that of the
4066 @var{value} corresponding to the first true @var{test} expression. If
4067 none of the @var{test} expressions are true, the value of the @code{cond}
4068 expression is that of the @var{default} expression.
4071 @var{test} expressions can have one of the following forms:
4074 @cindex @code{const_int} and attribute tests
4075 @item (const_int @var{i})
4076 This test is true if @var{i} is non-zero and false otherwise.
4078 @cindex @code{not} and attributes
4079 @cindex @code{ior} and attributes
4080 @cindex @code{and} and attributes
4081 @item (not @var{test})
4082 @itemx (ior @var{test1} @var{test2})
4083 @itemx (and @var{test1} @var{test2})
4084 These tests are true if the indicated logical function is true.
4086 @cindex @code{match_operand} and attributes
4087 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
4088 This test is true if operand @var{n} of the insn whose attribute value
4089 is being determined has mode @var{m} (this part of the test is ignored
4090 if @var{m} is @code{VOIDmode}) and the function specified by the string
4091 @var{pred} returns a non-zero value when passed operand @var{n} and mode
4092 @var{m} (this part of the test is ignored if @var{pred} is the null
4095 The @var{constraints} operand is ignored and should be the null string.
4097 @cindex @code{le} and attributes
4098 @cindex @code{leu} and attributes
4099 @cindex @code{lt} and attributes
4100 @cindex @code{gt} and attributes
4101 @cindex @code{gtu} and attributes
4102 @cindex @code{ge} and attributes
4103 @cindex @code{geu} and attributes
4104 @cindex @code{ne} and attributes
4105 @cindex @code{eq} and attributes
4106 @cindex @code{plus} and attributes
4107 @cindex @code{minus} and attributes
4108 @cindex @code{mult} and attributes
4109 @cindex @code{div} and attributes
4110 @cindex @code{mod} and attributes
4111 @cindex @code{abs} and attributes
4112 @cindex @code{neg} and attributes
4113 @cindex @code{ashift} and attributes
4114 @cindex @code{lshiftrt} and attributes
4115 @cindex @code{ashiftrt} and attributes
4116 @item (le @var{arith1} @var{arith2})
4117 @itemx (leu @var{arith1} @var{arith2})
4118 @itemx (lt @var{arith1} @var{arith2})
4119 @itemx (ltu @var{arith1} @var{arith2})
4120 @itemx (gt @var{arith1} @var{arith2})
4121 @itemx (gtu @var{arith1} @var{arith2})
4122 @itemx (ge @var{arith1} @var{arith2})
4123 @itemx (geu @var{arith1} @var{arith2})
4124 @itemx (ne @var{arith1} @var{arith2})
4125 @itemx (eq @var{arith1} @var{arith2})
4126 These tests are true if the indicated comparison of the two arithmetic
4127 expressions is true. Arithmetic expressions are formed with
4128 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
4129 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
4130 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill
4133 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
4134 Lengths},for additional forms). @code{symbol_ref} is a string
4135 denoting a C expression that yields an @code{int} when evaluated by the
4136 @samp{get_attr_@dots{}} routine. It should normally be a global
4140 @item (eq_attr @var{name} @var{value})
4141 @var{name} is a string specifying the name of an attribute.
4143 @var{value} is a string that is either a valid value for attribute
4144 @var{name}, a comma-separated list of values, or @samp{!} followed by a
4145 value or list. If @var{value} does not begin with a @samp{!}, this
4146 test is true if the value of the @var{name} attribute of the current
4147 insn is in the list specified by @var{value}. If @var{value} begins
4148 with a @samp{!}, this test is true if the attribute's value is
4149 @emph{not} in the specified list.
4154 (eq_attr "type" "load,store")
4161 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
4164 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
4165 value of the compiler variable @code{which_alternative}
4166 (@pxref{Output Statement}) and the values must be small integers. For
4170 (eq_attr "alternative" "2,3")
4177 (ior (eq (symbol_ref "which_alternative") (const_int 2))
4178 (eq (symbol_ref "which_alternative") (const_int 3)))
4181 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
4182 where the value of the attribute being tested is known for all insns matching
4183 a particular pattern. This is by far the most common case.@refill
4186 @item (attr_flag @var{name})
4187 The value of an @code{attr_flag} expression is true if the flag
4188 specified by @var{name} is true for the @code{insn} currently being
4191 @var{name} is a string specifying one of a fixed set of flags to test.
4192 Test the flags @code{forward} and @code{backward} to determine the
4193 direction of a conditional branch. Test the flags @code{very_likely},
4194 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
4195 if a conditional branch is expected to be taken.
4197 If the @code{very_likely} flag is true, then the @code{likely} flag is also
4198 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
4200 This example describes a conditional branch delay slot which
4201 can be nullified for forward branches that are taken (annul-true) or
4202 for backward branches which are not taken (annul-false).
4205 (define_delay (eq_attr "type" "cbranch")
4206 [(eq_attr "in_branch_delay" "true")
4207 (and (eq_attr "in_branch_delay" "true")
4208 (attr_flag "forward"))
4209 (and (eq_attr "in_branch_delay" "true")
4210 (attr_flag "backward"))])
4213 The @code{forward} and @code{backward} flags are false if the current
4214 @code{insn} being scheduled is not a conditional branch.
4216 The @code{very_likely} and @code{likely} flags are true if the
4217 @code{insn} being scheduled is not a conditional branch.
4218 The @code{very_unlikely} and @code{unlikely} flags are false if the
4219 @code{insn} being scheduled is not a conditional branch.
4221 @code{attr_flag} is only used during delay slot scheduling and has no
4222 meaning to other passes of the compiler.
4225 @item (attr @var{name})
4226 The value of another attribute is returned. This is most useful
4227 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
4228 produce more efficient code for non-numeric attributes.
4232 @subsection Assigning Attribute Values to Insns
4233 @cindex tagging insns
4234 @cindex assigning attribute values to insns
4236 The value assigned to an attribute of an insn is primarily determined by
4237 which pattern is matched by that insn (or which @code{define_peephole}
4238 generated it). Every @code{define_insn} and @code{define_peephole} can
4239 have an optional last argument to specify the values of attributes for
4240 matching insns. The value of any attribute not specified in a particular
4241 insn is set to the default value for that attribute, as specified in its
4242 @code{define_attr}. Extensive use of default values for attributes
4243 permits the specification of the values for only one or two attributes
4244 in the definition of most insn patterns, as seen in the example in the
4245 next section.@refill
4247 The optional last argument of @code{define_insn} and
4248 @code{define_peephole} is a vector of expressions, each of which defines
4249 the value for a single attribute. The most general way of assigning an
4250 attribute's value is to use a @code{set} expression whose first operand is an
4251 @code{attr} expression giving the name of the attribute being set. The
4252 second operand of the @code{set} is an attribute expression
4253 (@pxref{Expressions}) giving the value of the attribute.@refill
4255 When the attribute value depends on the @samp{alternative} attribute
4256 (i.e., which is the applicable alternative in the constraint of the
4257 insn), the @code{set_attr_alternative} expression can be used. It
4258 allows the specification of a vector of attribute expressions, one for
4262 When the generality of arbitrary attribute expressions is not required,
4263 the simpler @code{set_attr} expression can be used, which allows
4264 specifying a string giving either a single attribute value or a list
4265 of attribute values, one for each alternative.
4267 The form of each of the above specifications is shown below. In each case,
4268 @var{name} is a string specifying the attribute to be set.
4271 @item (set_attr @var{name} @var{value-string})
4272 @var{value-string} is either a string giving the desired attribute value,
4273 or a string containing a comma-separated list giving the values for
4274 succeeding alternatives. The number of elements must match the number
4275 of alternatives in the constraint of the insn pattern.
4277 Note that it may be useful to specify @samp{*} for some alternative, in
4278 which case the attribute will assume its default value for insns matching
4281 @findex set_attr_alternative
4282 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
4283 Depending on the alternative of the insn, the value will be one of the
4284 specified values. This is a shorthand for using a @code{cond} with
4285 tests on the @samp{alternative} attribute.
4288 @item (set (attr @var{name}) @var{value})
4289 The first operand of this @code{set} must be the special RTL expression
4290 @code{attr}, whose sole operand is a string giving the name of the
4291 attribute being set. @var{value} is the value of the attribute.
4294 The following shows three different ways of representing the same
4295 attribute value specification:
4298 (set_attr "type" "load,store,arith")
4300 (set_attr_alternative "type"
4301 [(const_string "load") (const_string "store")
4302 (const_string "arith")])
4305 (cond [(eq_attr "alternative" "1") (const_string "load")
4306 (eq_attr "alternative" "2") (const_string "store")]
4307 (const_string "arith")))
4311 @findex define_asm_attributes
4312 The @code{define_asm_attributes} expression provides a mechanism to
4313 specify the attributes assigned to insns produced from an @code{asm}
4314 statement. It has the form:
4317 (define_asm_attributes [@var{attr-sets}])
4321 where @var{attr-sets} is specified the same as for both the
4322 @code{define_insn} and the @code{define_peephole} expressions.
4324 These values will typically be the ``worst case'' attribute values. For
4325 example, they might indicate that the condition code will be clobbered.
4327 A specification for a @code{length} attribute is handled specially. The
4328 way to compute the length of an @code{asm} insn is to multiply the
4329 length specified in the expression @code{define_asm_attributes} by the
4330 number of machine instructions specified in the @code{asm} statement,
4331 determined by counting the number of semicolons and newlines in the
4332 string. Therefore, the value of the @code{length} attribute specified
4333 in a @code{define_asm_attributes} should be the maximum possible length
4334 of a single machine instruction.
4337 @subsection Example of Attribute Specifications
4338 @cindex attribute specifications example
4339 @cindex attribute specifications
4341 The judicious use of defaulting is important in the efficient use of
4342 insn attributes. Typically, insns are divided into @dfn{types} and an
4343 attribute, customarily called @code{type}, is used to represent this
4344 value. This attribute is normally used only to define the default value
4345 for other attributes. An example will clarify this usage.
4347 Assume we have a RISC machine with a condition code and in which only
4348 full-word operations are performed in registers. Let us assume that we
4349 can divide all insns into loads, stores, (integer) arithmetic
4350 operations, floating point operations, and branches.
4352 Here we will concern ourselves with determining the effect of an insn on
4353 the condition code and will limit ourselves to the following possible
4354 effects: The condition code can be set unpredictably (clobbered), not
4355 be changed, be set to agree with the results of the operation, or only
4356 changed if the item previously set into the condition code has been
4359 Here is part of a sample @file{md} file for such a machine:
4362 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
4364 (define_attr "cc" "clobber,unchanged,set,change0"
4365 (cond [(eq_attr "type" "load")
4366 (const_string "change0")
4367 (eq_attr "type" "store,branch")
4368 (const_string "unchanged")
4369 (eq_attr "type" "arith")
4370 (if_then_else (match_operand:SI 0 "" "")
4371 (const_string "set")
4372 (const_string "clobber"))]
4373 (const_string "clobber")))
4376 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
4377 (match_operand:SI 1 "general_operand" "r,m,r"))]
4383 [(set_attr "type" "arith,load,store")])
4386 Note that we assume in the above example that arithmetic operations
4387 performed on quantities smaller than a machine word clobber the condition
4388 code since they will set the condition code to a value corresponding to the
4392 @subsection Computing the Length of an Insn
4393 @cindex insn lengths, computing
4394 @cindex computing the length of an insn
4396 For many machines, multiple types of branch instructions are provided, each
4397 for different length branch displacements. In most cases, the assembler
4398 will choose the correct instruction to use. However, when the assembler
4399 cannot do so, GCC can when a special attribute, the @samp{length}
4400 attribute, is defined. This attribute must be defined to have numeric
4401 values by specifying a null string in its @code{define_attr}.
4403 In the case of the @samp{length} attribute, two additional forms of
4404 arithmetic terms are allowed in test expressions:
4407 @cindex @code{match_dup} and attributes
4408 @item (match_dup @var{n})
4409 This refers to the address of operand @var{n} of the current insn, which
4410 must be a @code{label_ref}.
4412 @cindex @code{pc} and attributes
4414 This refers to the address of the @emph{current} insn. It might have
4415 been more consistent with other usage to make this the address of the
4416 @emph{next} insn but this would be confusing because the length of the
4417 current insn is to be computed.
4420 @cindex @code{addr_vec}, length of
4421 @cindex @code{addr_diff_vec}, length of
4422 For normal insns, the length will be determined by value of the
4423 @samp{length} attribute. In the case of @code{addr_vec} and
4424 @code{addr_diff_vec} insn patterns, the length is computed as
4425 the number of vectors multiplied by the size of each vector.
4427 Lengths are measured in addressable storage units (bytes).
4429 The following macros can be used to refine the length computation:
4432 @findex FIRST_INSN_ADDRESS
4433 @item FIRST_INSN_ADDRESS
4434 When the @code{length} insn attribute is used, this macro specifies the
4435 value to be assigned to the address of the first insn in a function. If
4436 not specified, 0 is used.
4438 @findex ADJUST_INSN_LENGTH
4439 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
4440 If defined, modifies the length assigned to instruction @var{insn} as a
4441 function of the context in which it is used. @var{length} is an lvalue
4442 that contains the initially computed length of the insn and should be
4443 updated with the correct length of the insn.
4445 This macro will normally not be required. A case in which it is
4446 required is the ROMP. On this machine, the size of an @code{addr_vec}
4447 insn must be increased by two to compensate for the fact that alignment
4451 @findex get_attr_length
4452 The routine that returns @code{get_attr_length} (the value of the
4453 @code{length} attribute) can be used by the output routine to
4454 determine the form of the branch instruction to be written, as the
4455 example below illustrates.
4457 As an example of the specification of variable-length branches, consider
4458 the IBM 360. If we adopt the convention that a register will be set to
4459 the starting address of a function, we can jump to labels within 4k of
4460 the start using a four-byte instruction. Otherwise, we need a six-byte
4461 sequence to load the address from memory and then branch to it.
4463 On such a machine, a pattern for a branch instruction might be specified
4469 (label_ref (match_operand 0 "" "")))]
4473 return (get_attr_length (insn) == 4
4474 ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
4476 [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
4481 @node Constant Attributes
4482 @subsection Constant Attributes
4483 @cindex constant attributes
4485 A special form of @code{define_attr}, where the expression for the
4486 default value is a @code{const} expression, indicates an attribute that
4487 is constant for a given run of the compiler. Constant attributes may be
4488 used to specify which variety of processor is used. For example,
4491 (define_attr "cpu" "m88100,m88110,m88000"
4493 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
4494 (symbol_ref "TARGET_88110") (const_string "m88110")]
4495 (const_string "m88000"))))
4497 (define_attr "memory" "fast,slow"
4499 (if_then_else (symbol_ref "TARGET_FAST_MEM")
4500 (const_string "fast")
4501 (const_string "slow"))))
4504 The routine generated for constant attributes has no parameters as it
4505 does not depend on any particular insn. RTL expressions used to define
4506 the value of a constant attribute may use the @code{symbol_ref} form,
4507 but may not use either the @code{match_operand} form or @code{eq_attr}
4508 forms involving insn attributes.
4511 @subsection Delay Slot Scheduling
4512 @cindex delay slots, defining
4514 The insn attribute mechanism can be used to specify the requirements for
4515 delay slots, if any, on a target machine. An instruction is said to
4516 require a @dfn{delay slot} if some instructions that are physically
4517 after the instruction are executed as if they were located before it.
4518 Classic examples are branch and call instructions, which often execute
4519 the following instruction before the branch or call is performed.
4521 On some machines, conditional branch instructions can optionally
4522 @dfn{annul} instructions in the delay slot. This means that the
4523 instruction will not be executed for certain branch outcomes. Both
4524 instructions that annul if the branch is true and instructions that
4525 annul if the branch is false are supported.
4527 Delay slot scheduling differs from instruction scheduling in that
4528 determining whether an instruction needs a delay slot is dependent only
4529 on the type of instruction being generated, not on data flow between the
4530 instructions. See the next section for a discussion of data-dependent
4531 instruction scheduling.
4533 @findex define_delay
4534 The requirement of an insn needing one or more delay slots is indicated
4535 via the @code{define_delay} expression. It has the following form:
4538 (define_delay @var{test}
4539 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
4540 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
4544 @var{test} is an attribute test that indicates whether this
4545 @code{define_delay} applies to a particular insn. If so, the number of
4546 required delay slots is determined by the length of the vector specified
4547 as the second argument. An insn placed in delay slot @var{n} must
4548 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
4549 attribute test that specifies which insns may be annulled if the branch
4550 is true. Similarly, @var{annul-false-n} specifies which insns in the
4551 delay slot may be annulled if the branch is false. If annulling is not
4552 supported for that delay slot, @code{(nil)} should be coded.@refill
4554 For example, in the common case where branch and call insns require
4555 a single delay slot, which may contain any insn other than a branch or
4556 call, the following would be placed in the @file{md} file:
4559 (define_delay (eq_attr "type" "branch,call")
4560 [(eq_attr "type" "!branch,call") (nil) (nil)])
4563 Multiple @code{define_delay} expressions may be specified. In this
4564 case, each such expression specifies different delay slot requirements
4565 and there must be no insn for which tests in two @code{define_delay}
4566 expressions are both true.
4568 For example, if we have a machine that requires one delay slot for branches
4569 but two for calls, no delay slot can contain a branch or call insn,
4570 and any valid insn in the delay slot for the branch can be annulled if the
4571 branch is true, we might represent this as follows:
4574 (define_delay (eq_attr "type" "branch")
4575 [(eq_attr "type" "!branch,call")
4576 (eq_attr "type" "!branch,call")
4579 (define_delay (eq_attr "type" "call")
4580 [(eq_attr "type" "!branch,call") (nil) (nil)
4581 (eq_attr "type" "!branch,call") (nil) (nil)])
4583 @c the above is *still* too long. --mew 4feb93
4585 @node Function Units
4586 @subsection Specifying Function Units
4587 @cindex function units, for scheduling
4589 On most RISC machines, there are instructions whose results are not
4590 available for a specific number of cycles. Common cases are instructions
4591 that load data from memory. On many machines, a pipeline stall will result
4592 if the data is referenced too soon after the load instruction.
4594 In addition, many newer microprocessors have multiple function units, usually
4595 one for integer and one for floating point, and often will incur pipeline
4596 stalls when a result that is needed is not yet ready.
4598 The descriptions in this section allow the specification of how much
4599 time must elapse between the execution of an instruction and the time
4600 when its result is used. It also allows specification of when the
4601 execution of an instruction will delay execution of similar instructions
4602 due to function unit conflicts.
4604 For the purposes of the specifications in this section, a machine is
4605 divided into @dfn{function units}, each of which execute a specific
4606 class of instructions in first-in-first-out order. Function units that
4607 accept one instruction each cycle and allow a result to be used in the
4608 succeeding instruction (usually via forwarding) need not be specified.
4609 Classic RISC microprocessors will normally have a single function unit,
4610 which we can call @samp{memory}. The newer ``superscalar'' processors
4611 will often have function units for floating point operations, usually at
4612 least a floating point adder and multiplier.
4614 @findex define_function_unit
4615 Each usage of a function units by a class of insns is specified with a
4616 @code{define_function_unit} expression, which looks like this:
4619 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4620 @var{test} @var{ready-delay} @var{issue-delay}
4621 [@var{conflict-list}])
4624 @var{name} is a string giving the name of the function unit.
4626 @var{multiplicity} is an integer specifying the number of identical
4627 units in the processor. If more than one unit is specified, they will
4628 be scheduled independently. Only truly independent units should be
4629 counted; a pipelined unit should be specified as a single unit. (The
4630 only common example of a machine that has multiple function units for a
4631 single instruction class that are truly independent and not pipelined
4632 are the two multiply and two increment units of the CDC 6600.)
4634 @var{simultaneity} specifies the maximum number of insns that can be
4635 executing in each instance of the function unit simultaneously or zero
4636 if the unit is pipelined and has no limit.
4638 All @code{define_function_unit} definitions referring to function unit
4639 @var{name} must have the same name and values for @var{multiplicity} and
4642 @var{test} is an attribute test that selects the insns we are describing
4643 in this definition. Note that an insn may use more than one function
4644 unit and a function unit may be specified in more than one
4645 @code{define_function_unit}.
4647 @var{ready-delay} is an integer that specifies the number of cycles
4648 after which the result of the instruction can be used without
4649 introducing any stalls.
4651 @var{issue-delay} is an integer that specifies the number of cycles
4652 after the instruction matching the @var{test} expression begins using
4653 this unit until a subsequent instruction can begin. A cost of @var{N}
4654 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4655 be delayed if an earlier instruction has a longer @var{ready-delay}
4656 value. This blocking effect is computed using the @var{simultaneity},
4657 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4658 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4659 unit is taken to block for the @var{ready-delay} cycles of the executing
4660 insn, and smaller values of @var{issue-delay} are ignored.
4662 @var{conflict-list} is an optional list giving detailed conflict costs
4663 for this unit. If specified, it is a list of condition test expressions
4664 to be applied to insns chosen to execute in @var{name} following the
4665 particular insn matching @var{test} that is already executing in
4666 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4667 conflict cost; for insns not in the list, the cost is zero. If not
4668 specified, @var{conflict-list} defaults to all instructions that use the
4671 Typical uses of this vector are where a floating point function unit can
4672 pipeline either single- or double-precision operations, but not both, or
4673 where a memory unit can pipeline loads, but not stores, etc.
4675 As an example, consider a classic RISC machine where the result of a
4676 load instruction is not available for two cycles (a single ``delay''
4677 instruction is required) and where only one load instruction can be executed
4678 simultaneously. This would be specified as:
4681 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4684 For the case of a floating point function unit that can pipeline either
4685 single or double precision, but not both, the following could be specified:
4688 (define_function_unit
4689 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4690 (define_function_unit
4691 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4694 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4695 and uses all the specifications in the @code{define_function_unit}
4696 expression. It has recently come to our attention that these
4697 specifications may not allow modeling of some of the newer
4698 ``superscalar'' processors that have insns using multiple pipelined
4699 units. These insns will cause a potential conflict for the second unit
4700 used during their execution and there is no way of representing that
4701 conflict. We welcome any examples of how function unit conflicts work
4702 in such processors and suggestions for their representation.
4705 @node Conditional Execution
4706 @section Conditional Execution
4707 @cindex conditional execution
4710 A number of architectures provide for some form of conditional
4711 execution, or predication. The hallmark of this feature is the
4712 ability to nullify most of the instructions in the instruction set.
4713 When the instruction set is large and not entirely symmetric, it
4714 can be quite tedious to describe these forms directly in the
4715 @file{.md} file. An alternative is the @code{define_cond_exec} template.
4717 @findex define_cond_exec
4720 [@var{predicate-pattern}]
4722 "@var{output template}")
4725 @var{predicate-pattern} is the condition that must be true for the
4726 insn to be executed at runtime and should match a relational operator.
4727 One can use @code{match_operator} to match several relational operators
4728 at once. Any @code{match_operand} operands must have no more than one
4731 @var{condition} is a C expression that must be true for the generated
4734 @findex current_insn_predicate
4735 @var{output template} is a string similar to the @code{define_insn}
4736 output template (@pxref{Output Template}), except that the @samp{*}
4737 and @samp{@@} special cases do not apply. This is only useful if the
4738 assembly text for the predicate is a simple prefix to the main insn.
4739 In order to handle the general case, there is a global variable
4740 @code{current_insn_predicate} that will contain the entire predicate
4741 if the current insn is predicated, and will otherwise be @code{NULL}.
4743 When @code{define_cond_exec} is used, an implicit reference to
4744 the @code{predicable} instruction attribute is made.
4745 @xref{Insn Attributes}. This attribute must be boolean (i.e. have
4746 exactly two elements in its @var{list-of-values}). Further, it must
4747 not be used with complex expressions. That is, the default and all
4748 uses in the insns must be a simple constant, not dependent on the
4749 alternative or anything else.
4751 For each @code{define_insn} for which the @code{predicable}
4752 attribute is true, a new @code{define_insn} pattern will be
4753 generated that matches a predicated version of the instruction.
4757 (define_insn "addsi"
4758 [(set (match_operand:SI 0 "register_operand" "r")
4759 (plus:SI (match_operand:SI 1 "register_operand" "r")
4760 (match_operand:SI 2 "register_operand" "r")))]
4765 [(ne (match_operand:CC 0 "register_operand" "c")
4772 generates a new pattern
4777 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
4778 (set (match_operand:SI 0 "register_operand" "r")
4779 (plus:SI (match_operand:SI 1 "register_operand" "r")
4780 (match_operand:SI 2 "register_operand" "r"))))]
4781 "(@var{test2}) && (@var{test1})"
4782 "(%3) add %2,%1,%0")
4785 @node Constant Definitions
4786 @section Constant Definitions
4787 @cindex constant definitions
4788 @findex define_constants
4790 Using literal constants inside instruction patterns reduces legibility and
4791 can be a maintenance problem.
4793 To overcome this problem, you may use the @code{define_constants}
4794 expression. It contains a vector of name-value pairs. From that
4795 point on, wherever any of the names appears in the MD file, it is as
4796 if the corresponding value had been written instead. You may use
4797 @code{define_constants} multiple times; each appearance adds more
4798 constants to the table. It is an error to redefine a constant with
4801 To come back to the a29k load multiple example, instead of
4805 [(match_parallel 0 "load_multiple_operation"
4806 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
4807 (match_operand:SI 2 "memory_operand" "m"))
4809 (clobber (reg:SI 179))])]
4825 [(match_parallel 0 "load_multiple_operation"
4826 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
4827 (match_operand:SI 2 "memory_operand" "m"))
4829 (clobber (reg:SI R_CR))])]
4834 The constants that are defined with a define_constant are also output
4835 in the insn-codes.h header file as #defines.