1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
70 #include "insn-attr.h"
75 /* Next quantity number available for allocation. */
79 /* In all the following vectors indexed by quantity number. */
81 /* Element Q is the hard reg number chosen for quantity Q,
82 or -1 if none was found. */
84 static short *qty_phys_reg;
86 /* We maintain two hard register sets that indicate suggested hard registers
87 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
88 that are tied to the quantity by a simple copy. The second contains all
89 hard registers that are tied to the quantity via an arithmetic operation.
91 The former register set is given priority for allocation. This tends to
92 eliminate copy insns. */
94 /* Element Q is a set of hard registers that are suggested for quantity Q by
97 static HARD_REG_SET *qty_phys_copy_sugg;
99 /* Element Q is a set of hard registers that are suggested for quantity Q by
102 static HARD_REG_SET *qty_phys_sugg;
104 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
106 static short *qty_phys_num_copy_sugg;
108 /* Element Q is the number of suggested registers in qty_phys_sugg. */
110 static short *qty_phys_num_sugg;
112 /* Element Q is the number of refs to quantity Q. */
114 static int *qty_n_refs;
116 /* Element Q is a reg class contained in (smaller than) the
117 preferred classes of all the pseudo regs that are tied in quantity Q.
118 This is the preferred class for allocating that quantity. */
120 static enum reg_class *qty_min_class;
122 /* Insn number (counting from head of basic block)
123 where quantity Q was born. -1 if birth has not been recorded. */
125 static int *qty_birth;
127 /* Insn number (counting from head of basic block)
128 where quantity Q died. Due to the way tying is done,
129 and the fact that we consider in this pass only regs that die but once,
130 a quantity can die only once. Each quantity's life span
131 is a set of consecutive insns. -1 if death has not been recorded. */
133 static int *qty_death;
135 /* Number of words needed to hold the data in quantity Q.
136 This depends on its machine mode. It is used for these purposes:
137 1. It is used in computing the relative importances of qtys,
138 which determines the order in which we look for regs for them.
139 2. It is used in rules that prevent tying several registers of
140 different sizes in a way that is geometrically impossible
141 (see combine_regs). */
143 static int *qty_size;
145 /* This holds the mode of the registers that are tied to qty Q,
146 or VOIDmode if registers with differing modes are tied together. */
148 static enum machine_mode *qty_mode;
150 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
152 static int *qty_n_calls_crossed;
154 /* Register class within which we allocate qty Q if we can't get
155 its preferred class. */
157 static enum reg_class *qty_alternate_class;
159 /* Element Q is nonzero if this quantity has been used in a SUBREG
160 that changes its size. */
162 static char *qty_changes_size;
164 /* Element Q is the register number of one pseudo register whose
165 reg_qty value is Q. This register should be the head of the chain
166 maintained in reg_next_in_qty. */
168 static int *qty_first_reg;
170 /* If (REG N) has been assigned a quantity number, is a register number
171 of another register assigned the same quantity number, or -1 for the
172 end of the chain. qty_first_reg point to the head of this chain. */
174 static int *reg_next_in_qty;
176 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
178 of -1 if this register cannot be allocated by local-alloc,
179 or -2 if not known yet.
181 Note that if we see a use or death of pseudo register N with
182 reg_qty[N] == -2, register N must be local to the current block. If
183 it were used in more than one block, we would have reg_qty[N] == -1.
184 This relies on the fact that if reg_basic_block[N] is >= 0, register N
185 will not appear in any other block. We save a considerable number of
186 tests by exploiting this.
188 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
193 /* The offset (in words) of register N within its quantity.
194 This can be nonzero if register N is SImode, and has been tied
195 to a subreg of a DImode register. */
197 static char *reg_offset;
199 /* Vector of substitutions of register numbers,
200 used to map pseudo regs into hardware regs.
201 This is set up as a result of register allocation.
202 Element N is the hard reg assigned to pseudo reg N,
203 or is -1 if no hard reg was assigned.
204 If N is a hard reg number, element N is N. */
208 /* Set of hard registers live at the current point in the scan
209 of the instructions in a basic block. */
211 static HARD_REG_SET regs_live;
213 /* Each set of hard registers indicates registers live at a particular
214 point in the basic block. For N even, regs_live_at[N] says which
215 hard registers are needed *after* insn N/2 (i.e., they may not
216 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
218 If an object is to conflict with the inputs of insn J but not the
219 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
220 if it is to conflict with the outputs of insn J but not the inputs of
221 insn J + 1, it is said to die at index J*2 + 1. */
223 static HARD_REG_SET *regs_live_at;
225 /* Communicate local vars `insn_number' and `insn'
226 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
227 static int this_insn_number;
228 static rtx this_insn;
230 /* Used to communicate changes made by update_equiv_regs to
231 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
232 found or created, so that we can keep track of what memory accesses might
233 be created later, e.g. by reload. */
235 static rtx *reg_equiv_replacement;
237 /* Used for communication between update_equiv_regs and no_equiv. */
238 static rtx *reg_equiv_init_insns;
240 static void alloc_qty PROTO((int, enum machine_mode, int, int));
241 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
242 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
243 static int contains_replace_regs PROTO((rtx, char *));
244 static int memref_referenced_p PROTO((rtx, rtx));
245 static int memref_used_between_p PROTO((rtx, rtx, rtx));
246 static void update_equiv_regs PROTO((void));
247 static void no_equiv PROTO((rtx, rtx));
248 static void block_alloc PROTO((int));
249 static int qty_sugg_compare PROTO((int, int));
250 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
251 static int qty_compare PROTO((int, int));
252 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
253 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
254 static int reg_meets_class_p PROTO((int, enum reg_class));
255 static void update_qty_class PROTO((int, int));
256 static void reg_is_set PROTO((rtx, rtx));
257 static void reg_is_born PROTO((rtx, int));
258 static void wipe_dead_reg PROTO((rtx, int));
259 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
260 int, int, int, int, int));
261 static void mark_life PROTO((int, enum machine_mode, int));
262 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
263 static int no_conflict_p PROTO((rtx, rtx, rtx));
264 static int requires_inout PROTO((char *));
266 /* Allocate a new quantity (new within current basic block)
267 for register number REGNO which is born at index BIRTH
268 within the block. MODE and SIZE are info on reg REGNO. */
271 alloc_qty (regno, mode, size, birth)
273 enum machine_mode mode;
276 register int qty = next_qty++;
278 reg_qty[regno] = qty;
279 reg_offset[regno] = 0;
280 reg_next_in_qty[regno] = -1;
282 qty_first_reg[qty] = regno;
283 qty_size[qty] = size;
284 qty_mode[qty] = mode;
285 qty_birth[qty] = birth;
286 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
287 qty_min_class[qty] = reg_preferred_class (regno);
288 qty_alternate_class[qty] = reg_alternate_class (regno);
289 qty_n_refs[qty] = REG_N_REFS (regno);
290 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
293 /* Main entry point of this file. */
301 /* Leaf functions and non-leaf functions have different needs.
302 If defined, let the machine say what kind of ordering we
304 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
305 ORDER_REGS_FOR_LOCAL_ALLOC;
308 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
310 update_equiv_regs ();
312 /* This sets the maximum number of quantities we can have. Quantity
313 numbers start at zero and we can have one for each pseudo. */
314 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
316 /* Allocate vectors of temporary data.
317 See the declarations of these variables, above,
318 for what they mean. */
320 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
322 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
323 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
324 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
325 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
326 qty_birth = (int *) alloca (max_qty * sizeof (int));
327 qty_death = (int *) alloca (max_qty * sizeof (int));
328 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
329 qty_size = (int *) alloca (max_qty * sizeof (int));
331 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
332 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
334 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
336 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
337 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
338 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
340 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
341 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
342 reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int));
344 /* Allocate the reg_renumber array */
345 allocate_reg_info (max_regno, FALSE, TRUE);
347 /* Determine which pseudo-registers can be allocated by local-alloc.
348 In general, these are the registers used only in a single block and
349 which only die once. However, if a register's preferred class has only
350 a few entries, don't allocate this register here unless it is preferred
351 or nothing since retry_global_alloc won't be able to move it to
352 GENERAL_REGS if a reload register of this class is needed.
354 We need not be concerned with which block actually uses the register
355 since we will never see it outside that block. */
357 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
359 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
360 && (reg_alternate_class (i) == NO_REGS
361 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
367 /* Force loop below to initialize entire quantity array. */
370 /* Allocate each block's local registers, block by block. */
372 for (b = 0; b < n_basic_blocks; b++)
374 /* NEXT_QTY indicates which elements of the `qty_...'
375 vectors might need to be initialized because they were used
376 for the previous block; it is set to the entire array before
377 block 0. Initialize those, with explicit loop if there are few,
378 else with bzero and bcopy. Do not initialize vectors that are
379 explicit set by `alloc_qty'. */
383 for (i = 0; i < next_qty; i++)
385 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
386 qty_phys_num_copy_sugg[i] = 0;
387 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
388 qty_phys_num_sugg[i] = 0;
393 #define CLEAR(vector) \
394 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
396 CLEAR (qty_phys_copy_sugg);
397 CLEAR (qty_phys_num_copy_sugg);
398 CLEAR (qty_phys_sugg);
399 CLEAR (qty_phys_num_sugg);
412 free (reg_next_in_qty);
415 /* Depth of loops we are in while in update_equiv_regs. */
416 static int loop_depth;
418 /* Used for communication between the following two functions: contains
419 a MEM that we wish to ensure remains unchanged. */
420 static rtx equiv_mem;
422 /* Set nonzero if EQUIV_MEM is modified. */
423 static int equiv_mem_modified;
425 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
426 Called via note_stores. */
429 validate_equiv_mem_from_store (dest, set)
431 rtx set ATTRIBUTE_UNUSED;
433 if ((GET_CODE (dest) == REG
434 && reg_overlap_mentioned_p (dest, equiv_mem))
435 || (GET_CODE (dest) == MEM
436 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
437 equiv_mem_modified = 1;
440 /* Verify that no store between START and the death of REG invalidates
441 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
442 by storing into an overlapping memory location, or with a non-const
445 Return 1 if MEMREF remains valid. */
448 validate_equiv_mem (start, reg, memref)
457 equiv_mem_modified = 0;
459 /* If the memory reference has side effects or is volatile, it isn't a
460 valid equivalence. */
461 if (side_effects_p (memref))
464 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
466 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
469 if (find_reg_note (insn, REG_DEAD, reg))
472 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
473 && ! CONST_CALL_P (insn))
476 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
478 /* If a register mentioned in MEMREF is modified via an
479 auto-increment, we lose the equivalence. Do the same if one
480 dies; although we could extend the life, it doesn't seem worth
483 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
484 if ((REG_NOTE_KIND (note) == REG_INC
485 || REG_NOTE_KIND (note) == REG_DEAD)
486 && GET_CODE (XEXP (note, 0)) == REG
487 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
494 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
497 contains_replace_regs (x, reg_equiv_replace)
499 char *reg_equiv_replace;
503 enum rtx_code code = GET_CODE (x);
519 return reg_equiv_replace[REGNO (x)];
525 fmt = GET_RTX_FORMAT (code);
526 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
530 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
534 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
535 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
543 /* TRUE if X references a memory location that would be affected by a store
547 memref_referenced_p (memref, x)
553 enum rtx_code code = GET_CODE (x);
569 return (reg_equiv_replacement[REGNO (x)]
570 && memref_referenced_p (memref,
571 reg_equiv_replacement[REGNO (x)]));
574 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
579 /* If we are setting a MEM, it doesn't count (its address does), but any
580 other SET_DEST that has a MEM in it is referencing the MEM. */
581 if (GET_CODE (SET_DEST (x)) == MEM)
583 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
586 else if (memref_referenced_p (memref, SET_DEST (x)))
589 return memref_referenced_p (memref, SET_SRC (x));
595 fmt = GET_RTX_FORMAT (code);
596 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
600 if (memref_referenced_p (memref, XEXP (x, i)))
604 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
605 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
613 /* TRUE if some insn in the range (START, END] references a memory location
614 that would be affected by a store to MEMREF. */
617 memref_used_between_p (memref, start, end)
624 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
625 insn = NEXT_INSN (insn))
626 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
627 && memref_referenced_p (memref, PATTERN (insn)))
633 /* Return nonzero if the rtx X is invariant over the current function. */
635 function_invariant_p (x)
640 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
642 if (GET_CODE (x) == PLUS
643 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
644 && CONSTANT_P (XEXP (x, 1)))
649 /* Find registers that are equivalent to a single value throughout the
650 compilation (either because they can be referenced in memory or are set once
651 from a single constant). Lower their priority for a register.
653 If such a register is only referenced once, try substituting its value
654 into the using insn. If it succeeds, we can eliminate the register
660 /* Set when an attempt should be made to replace a register with the
661 associated reg_equiv_replacement entry at the end of this function. */
662 char *reg_equiv_replace
663 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
667 reg_equiv_init_insns = (rtx *) alloca (max_regno * sizeof (rtx));
668 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx));
670 bzero ((char *) reg_equiv_init_insns, max_regno * sizeof (rtx));
671 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx));
672 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
674 init_alias_analysis ();
678 /* Scan the insns and find which registers have equivalences. Do this
679 in a separate scan of the insns because (due to -fcse-follow-jumps)
680 a register can be set below its use. */
681 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
688 if (GET_CODE (insn) == NOTE)
690 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
692 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
696 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
699 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
700 if (REG_NOTE_KIND (note) == REG_INC)
701 no_equiv (XEXP (note, 0), note);
703 set = single_set (insn);
705 /* If this insn contains more (or less) than a single SET,
706 only mark all destinations as having no known equivalence. */
709 note_stores (PATTERN (insn), no_equiv);
712 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
716 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
718 rtx part = XVECEXP (PATTERN (insn), 0, i);
720 note_stores (part, no_equiv);
724 dest = SET_DEST (set);
727 /* If this sets a MEM to the contents of a REG that is only used
728 in a single basic block, see if the register is always equivalent
729 to that memory location and if moving the store from INSN to the
730 insn that set REG is safe. If so, put a REG_EQUIV note on the
733 Don't add a REG_EQUIV note if the insn already has one. The existing
734 REG_EQUIV is likely more useful than the one we are adding.
736 If one of the regs in the address is marked as reg_equiv_replace,
737 then we can't add this REG_EQUIV note. The reg_equiv_replace
738 optimization may move the set of this register immediately before
739 insn, which puts it after reg_equiv_init_insns[regno], and hence
740 the mention in the REG_EQUIV note would be to an uninitialized
742 /* ????? This test isn't good enough; we might see a MEM with a use of
743 a pseudo register before we see its setting insn that will cause
744 reg_equiv_replace for that pseudo to be set.
745 Equivalences to MEMs should be made in another pass, after the
746 reg_equiv_replace information has been gathered. */
748 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
749 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
750 && REG_BASIC_BLOCK (regno) >= 0
751 && REG_N_SETS (regno) == 1
752 && reg_equiv_init_insns[regno] != 0
753 && reg_equiv_init_insns[regno] != const0_rtx
754 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
755 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))
757 rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);
758 if (validate_equiv_mem (init_insn, src, dest)
759 && ! memref_used_between_p (dest, init_insn, insn))
760 REG_NOTES (init_insn)
761 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
764 /* We only handle the case of a pseudo register being set
765 once, or always to the same value. */
766 /* ??? The mn10200 port breaks if we add equivalences for
767 values that need an ADDRESS_REGS register and set them equivalent
768 to a MEM of a pseudo. The actual problem is in the over-conservative
769 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
770 calculate_needs, but we traditionally work around this problem
771 here by rejecting equivalences when the destination is in a register
772 that's likely spilled. This is fragile, of course, since the
773 preferred class of a pseudo depends on all instructions that set
776 if (GET_CODE (dest) != REG
777 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
778 || reg_equiv_init_insns[regno] == const0_rtx
779 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
780 && GET_CODE (src) == MEM))
782 /* This might be seting a SUBREG of a pseudo, a pseudo that is
783 also set somewhere else to a constant. */
784 note_stores (set, no_equiv);
787 /* Don't handle the equivalence if the source is in a register
788 class that's likely to be spilled. */
789 if (GET_CODE (src) == REG
790 && REGNO (src) >= FIRST_PSEUDO_REGISTER
791 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src))))
793 no_equiv (dest, set);
797 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
799 #ifdef DONT_RECORD_EQUIVALENCE
800 /* Allow the target to reject promotions of some REG_EQUAL notes to
803 In some cases this can improve register allocation if the existence
804 of the REG_EQUIV note is likely to increase the lifetime of a register
805 that is likely to be spilled.
807 It may also be necessary if the target can't handle certain constant
808 expressions appearing randomly in insns, but for whatever reason
809 those expressions must be considered legitimate constant expressions
810 to prevent them from being forced into memory. */
811 if (note && DONT_RECORD_EQUIVALENCE (note))
815 if (REG_N_SETS (regno) != 1
817 || ! function_invariant_p (XEXP (note, 0))
818 || (reg_equiv_replacement[regno]
819 && ! rtx_equal_p (XEXP (note, 0),
820 reg_equiv_replacement[regno]))))
822 no_equiv (dest, set);
825 /* Record this insn as initializing this register. */
826 reg_equiv_init_insns[regno]
827 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]);
829 /* If this register is known to be equal to a constant, record that
830 it is always equivalent to the constant. */
831 if (note && function_invariant_p (XEXP (note, 0)))
832 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
834 /* If this insn introduces a "constant" register, decrease the priority
835 of that register. Record this insn if the register is only used once
836 more and the equivalence value is the same as our source.
838 The latter condition is checked for two reasons: First, it is an
839 indication that it may be more efficient to actually emit the insn
840 as written (if no registers are available, reload will substitute
841 the equivalence). Secondly, it avoids problems with any registers
842 dying in this insn whose death notes would be missed.
844 If we don't have a REG_EQUIV note, see if this insn is loading
845 a register used only in one basic block from a MEM. If so, and the
846 MEM remains unchanged for the life of the register, add a REG_EQUIV
849 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
851 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
852 && GET_CODE (SET_SRC (set)) == MEM
853 && validate_equiv_mem (insn, dest, SET_SRC (set)))
854 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
859 int regno = REGNO (dest);
861 reg_equiv_replacement[regno] = XEXP (note, 0);
863 /* Don't mess with things live during setjmp. */
864 if (REG_LIVE_LENGTH (regno) >= 0)
866 /* Note that the statement below does not affect the priority
868 REG_LIVE_LENGTH (regno) *= 2;
871 /* If the register is referenced exactly twice, meaning it is
872 set once and used once, indicate that the reference may be
873 replaced by the equivalence we computed above. If the
874 register is only used in one basic block, this can't succeed
875 or combine would have done it.
877 It would be nice to use "loop_depth * 2" in the compare
878 below. Unfortunately, LOOP_DEPTH need not be constant within
879 a basic block so this would be too complicated.
881 This case normally occurs when a parameter is read from
882 memory and then used exactly once, not in a loop. */
884 if (REG_N_REFS (regno) == 2
885 && REG_BASIC_BLOCK (regno) < 0
886 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
887 reg_equiv_replace[regno] = 1;
892 /* Now scan all regs killed in an insn to see if any of them are
893 registers only used that once. If so, see if we can replace the
894 reference with the equivalent from. If we can, delete the
895 initializing reference and this register will go away. If we
896 can't replace the reference, and the instruction is not in a
897 loop, then move the register initialization just before the use,
898 so that they are in the same basic block. */
901 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
905 /* Keep track of which basic block we are in. */
906 if (block + 1 < n_basic_blocks
907 && basic_block_head[block + 1] == insn)
910 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
912 if (GET_CODE (insn) == NOTE)
914 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
916 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
927 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
929 if (REG_NOTE_KIND (link) == REG_DEAD
930 /* Make sure this insn still refers to the register. */
931 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
933 int regno = REGNO (XEXP (link, 0));
936 if (! reg_equiv_replace[regno])
939 /* reg_equiv_replace[REGNO] gets set only when
940 REG_N_REFS[REGNO] is 2, i.e. the register is set
941 once and used once. (If it were only set, but not used,
942 flow would have deleted the setting insns.) Hence
943 there can only be one insn in reg_equiv_init_insns. */
944 equiv_insn = XEXP (reg_equiv_init_insns[regno], 0);
946 if (validate_replace_rtx (regno_reg_rtx[regno],
947 reg_equiv_replacement[regno], insn))
949 remove_death (regno, insn);
950 REG_N_REFS (regno) = 0;
951 PUT_CODE (equiv_insn, NOTE);
952 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
953 NOTE_SOURCE_FILE (equiv_insn) = 0;
955 /* If we aren't in a loop, and there are no calls in
956 INSN or in the initialization of the register, then
957 move the initialization of the register to just
958 before INSN. Update the flow information. */
960 && GET_CODE (equiv_insn) == INSN
961 && GET_CODE (insn) == INSN
962 && REG_BASIC_BLOCK (regno) < 0)
966 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
967 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
969 PUT_CODE (equiv_insn, NOTE);
970 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
971 NOTE_SOURCE_FILE (equiv_insn) = 0;
972 REG_NOTES (equiv_insn) = 0;
975 REG_BASIC_BLOCK (regno) = 0;
977 REG_BASIC_BLOCK (regno) = block;
978 REG_N_CALLS_CROSSED (regno) = 0;
979 REG_LIVE_LENGTH (regno) = 2;
981 if (block >= 0 && insn == basic_block_head[block])
982 basic_block_head[block] = PREV_INSN (insn);
984 for (l = 0; l < n_basic_blocks; l++)
985 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
992 /* Mark REG as having no known equivalence.
993 Some instructions might have been proceessed before and furnished
994 with REG_EQUIV notes for this register; these notes will have to be
996 STORE is the piece of RTL that does the non-constant / conflicting
997 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
998 but needs to be there because this function is called from note_stores. */
1000 no_equiv (reg, store)
1006 if (GET_CODE (reg) != REG)
1008 regno = REGNO (reg);
1009 list = reg_equiv_init_insns[regno];
1010 if (list == const0_rtx)
1012 for (; list; list = XEXP (list, 1))
1014 rtx insn = XEXP (list, 0);
1015 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1017 reg_equiv_init_insns[regno] = const0_rtx;
1018 reg_equiv_replacement[regno] = NULL_RTX;
1021 /* Allocate hard regs to the pseudo regs used only within block number B.
1022 Only the pseudos that die but once can be handled. */
1031 int insn_number = 0;
1033 int max_uid = get_max_uid ();
1035 int no_conflict_combined_regno = -1;
1037 /* Count the instructions in the basic block. */
1039 insn = basic_block_end[b];
1042 if (GET_CODE (insn) != NOTE)
1043 if (++insn_count > max_uid)
1045 if (insn == basic_block_head[b])
1047 insn = PREV_INSN (insn);
1050 /* +2 to leave room for a post_mark_life at the last insn and for
1051 the birth of a CLOBBER in the first insn. */
1052 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1053 * sizeof (HARD_REG_SET));
1054 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1056 /* Initialize table of hardware registers currently live. */
1058 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1060 /* This loop scans the instructions of the basic block
1061 and assigns quantities to registers.
1062 It computes which registers to tie. */
1064 insn = basic_block_head[b];
1067 register rtx body = PATTERN (insn);
1069 if (GET_CODE (insn) != NOTE)
1072 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1074 register rtx link, set;
1075 register int win = 0;
1076 register rtx r0, r1;
1077 int combined_regno = -1;
1080 this_insn_number = insn_number;
1083 extract_insn (insn);
1084 which_alternative = -1;
1086 /* Is this insn suitable for tying two registers?
1087 If so, try doing that.
1088 Suitable insns are those with at least two operands and where
1089 operand 0 is an output that is a register that is not
1092 We can tie operand 0 with some operand that dies in this insn.
1093 First look for operands that are required to be in the same
1094 register as operand 0. If we find such, only try tying that
1095 operand or one that can be put into that operand if the
1096 operation is commutative. If we don't find an operand
1097 that is required to be in the same register as operand 0,
1098 we can tie with any operand.
1100 Subregs in place of regs are also ok.
1102 If tying is done, WIN is set nonzero. */
1105 #ifdef REGISTER_CONSTRAINTS
1106 && recog_n_operands > 1
1107 && recog_constraints[0][0] == '='
1108 && recog_constraints[0][1] != '&'
1110 && GET_CODE (PATTERN (insn)) == SET
1111 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1115 #ifdef REGISTER_CONSTRAINTS
1116 /* If non-negative, is an operand that must match operand 0. */
1117 int must_match_0 = -1;
1118 /* Counts number of alternatives that require a match with
1120 int n_matching_alts = 0;
1122 for (i = 1; i < recog_n_operands; i++)
1124 char *p = recog_constraints[i];
1125 int this_match = (requires_inout (p));
1127 n_matching_alts += this_match;
1128 if (this_match == recog_n_alternatives)
1133 r0 = recog_operand[0];
1134 for (i = 1; i < recog_n_operands; i++)
1136 #ifdef REGISTER_CONSTRAINTS
1137 /* Skip this operand if we found an operand that
1138 must match operand 0 and this operand isn't it
1139 and can't be made to be it by commutativity. */
1141 if (must_match_0 >= 0 && i != must_match_0
1142 && ! (i == must_match_0 + 1
1143 && recog_constraints[i-1][0] == '%')
1144 && ! (i == must_match_0 - 1
1145 && recog_constraints[i][0] == '%'))
1148 /* Likewise if each alternative has some operand that
1149 must match operand zero. In that case, skip any
1150 operand that doesn't list operand 0 since we know that
1151 the operand always conflicts with operand 0. We
1152 ignore commutatity in this case to keep things simple. */
1153 if (n_matching_alts == recog_n_alternatives
1154 && 0 == requires_inout (recog_constraints[i]))
1158 r1 = recog_operand[i];
1160 /* If the operand is an address, find a register in it.
1161 There may be more than one register, but we only try one
1164 #ifdef REGISTER_CONSTRAINTS
1165 recog_constraints[i][0] == 'p'
1167 recog_operand_address_p[i]
1170 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1173 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1175 /* We have two priorities for hard register preferences.
1176 If we have a move insn or an insn whose first input
1177 can only be in the same register as the output, give
1178 priority to an equivalence found from that insn. */
1180 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1181 #ifdef REGISTER_CONSTRAINTS
1182 || (r1 == recog_operand[i] && must_match_0 >= 0)
1186 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1187 win = combine_regs (r1, r0, may_save_copy,
1188 insn_number, insn, 0);
1195 /* Recognize an insn sequence with an ultimate result
1196 which can safely overlap one of the inputs.
1197 The sequence begins with a CLOBBER of its result,
1198 and ends with an insn that copies the result to itself
1199 and has a REG_EQUAL note for an equivalent formula.
1200 That note indicates what the inputs are.
1201 The result and the input can overlap if each insn in
1202 the sequence either doesn't mention the input
1203 or has a REG_NO_CONFLICT note to inhibit the conflict.
1205 We do the combining test at the CLOBBER so that the
1206 destination register won't have had a quantity number
1207 assigned, since that would prevent combining. */
1209 if (GET_CODE (PATTERN (insn)) == CLOBBER
1210 && (r0 = XEXP (PATTERN (insn), 0),
1211 GET_CODE (r0) == REG)
1212 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1213 && XEXP (link, 0) != 0
1214 && GET_CODE (XEXP (link, 0)) == INSN
1215 && (set = single_set (XEXP (link, 0))) != 0
1216 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1217 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1220 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1221 /* Check that we have such a sequence. */
1222 && no_conflict_p (insn, r0, r1))
1223 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1224 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1225 && (r1 = XEXP (XEXP (note, 0), 0),
1226 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1227 && no_conflict_p (insn, r0, r1))
1228 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1230 /* Here we care if the operation to be computed is
1232 else if ((GET_CODE (XEXP (note, 0)) == EQ
1233 || GET_CODE (XEXP (note, 0)) == NE
1234 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1235 && (r1 = XEXP (XEXP (note, 0), 1),
1236 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1237 && no_conflict_p (insn, r0, r1))
1238 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1240 /* If we did combine something, show the register number
1241 in question so that we know to ignore its death. */
1243 no_conflict_combined_regno = REGNO (r1);
1246 /* If registers were just tied, set COMBINED_REGNO
1247 to the number of the register used in this insn
1248 that was tied to the register set in this insn.
1249 This register's qty should not be "killed". */
1253 while (GET_CODE (r1) == SUBREG)
1254 r1 = SUBREG_REG (r1);
1255 combined_regno = REGNO (r1);
1258 /* Mark the death of everything that dies in this instruction,
1259 except for anything that was just combined. */
1261 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1262 if (REG_NOTE_KIND (link) == REG_DEAD
1263 && GET_CODE (XEXP (link, 0)) == REG
1264 && combined_regno != REGNO (XEXP (link, 0))
1265 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1266 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1267 wipe_dead_reg (XEXP (link, 0), 0);
1269 /* Allocate qty numbers for all registers local to this block
1270 that are born (set) in this instruction.
1271 A pseudo that already has a qty is not changed. */
1273 note_stores (PATTERN (insn), reg_is_set);
1275 /* If anything is set in this insn and then unused, mark it as dying
1276 after this insn, so it will conflict with our outputs. This
1277 can't match with something that combined, and it doesn't matter
1278 if it did. Do this after the calls to reg_is_set since these
1279 die after, not during, the current insn. */
1281 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1282 if (REG_NOTE_KIND (link) == REG_UNUSED
1283 && GET_CODE (XEXP (link, 0)) == REG)
1284 wipe_dead_reg (XEXP (link, 0), 1);
1286 /* If this is an insn that has a REG_RETVAL note pointing at a
1287 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1288 block, so clear any register number that combined within it. */
1289 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1290 && GET_CODE (XEXP (note, 0)) == INSN
1291 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1292 no_conflict_combined_regno = -1;
1295 /* Set the registers live after INSN_NUMBER. Note that we never
1296 record the registers live before the block's first insn, since no
1297 pseudos we care about are live before that insn. */
1299 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1300 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1302 if (insn == basic_block_end[b])
1305 insn = NEXT_INSN (insn);
1308 /* Now every register that is local to this basic block
1309 should have been given a quantity, or else -1 meaning ignore it.
1310 Every quantity should have a known birth and death.
1312 Order the qtys so we assign them registers in order of the
1313 number of suggested registers they need so we allocate those with
1314 the most restrictive needs first. */
1316 qty_order = (int *) alloca (next_qty * sizeof (int));
1317 for (i = 0; i < next_qty; i++)
1320 #define EXCHANGE(I1, I2) \
1321 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1326 /* Make qty_order[2] be the one to allocate last. */
1327 if (qty_sugg_compare (0, 1) > 0)
1329 if (qty_sugg_compare (1, 2) > 0)
1332 /* ... Fall through ... */
1334 /* Put the best one to allocate in qty_order[0]. */
1335 if (qty_sugg_compare (0, 1) > 0)
1338 /* ... Fall through ... */
1342 /* Nothing to do here. */
1346 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1349 /* Try to put each quantity in a suggested physical register, if it has one.
1350 This may cause registers to be allocated that otherwise wouldn't be, but
1351 this seems acceptable in local allocation (unlike global allocation). */
1352 for (i = 0; i < next_qty; i++)
1355 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1356 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1357 0, 1, qty_birth[q], qty_death[q]);
1359 qty_phys_reg[q] = -1;
1362 /* Order the qtys so we assign them registers in order of
1363 decreasing length of life. Normally call qsort, but if we
1364 have only a very small number of quantities, sort them ourselves. */
1366 for (i = 0; i < next_qty; i++)
1369 #define EXCHANGE(I1, I2) \
1370 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1375 /* Make qty_order[2] be the one to allocate last. */
1376 if (qty_compare (0, 1) > 0)
1378 if (qty_compare (1, 2) > 0)
1381 /* ... Fall through ... */
1383 /* Put the best one to allocate in qty_order[0]. */
1384 if (qty_compare (0, 1) > 0)
1387 /* ... Fall through ... */
1391 /* Nothing to do here. */
1395 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1398 /* Now for each qty that is not a hardware register,
1399 look for a hardware register to put it in.
1400 First try the register class that is cheapest for this qty,
1401 if there is more than one class. */
1403 for (i = 0; i < next_qty; i++)
1406 if (qty_phys_reg[q] < 0)
1408 #ifdef INSN_SCHEDULING
1409 /* These values represent the adjusted lifetime of a qty so
1410 that it conflicts with qtys which appear near the start/end
1411 of this qty's lifetime.
1413 The purpose behind extending the lifetime of this qty is to
1414 discourage the register allocator from creating false
1417 The adjustment value is choosen to indicate that this qty
1418 conflicts with all the qtys in the instructions immediately
1419 before and after the lifetime of this qty.
1421 Experiments have shown that higher values tend to hurt
1422 overall code performance.
1424 If allocation using the extended lifetime fails we will try
1425 again with the qty's unadjusted lifetime. */
1426 int fake_birth = MAX (0, qty_birth[q] - 2 + qty_birth[q] % 2);
1427 int fake_death = MIN (insn_number * 2 + 1,
1428 qty_death[q] + 2 - qty_death[q] % 2);
1431 if (N_REG_CLASSES > 1)
1433 #ifdef INSN_SCHEDULING
1434 /* We try to avoid using hard registers allocated to qtys which
1435 are born immediately after this qty or die immediately before
1438 This optimization is only appropriate when we will run
1439 a scheduling pass after reload and we are not optimizing
1441 if (flag_schedule_insns_after_reload
1443 && !SMALL_REGISTER_CLASSES)
1446 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1447 qty_mode[q], q, 0, 0,
1448 fake_birth, fake_death);
1449 if (qty_phys_reg[q] >= 0)
1453 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1454 qty_mode[q], q, 0, 0,
1455 qty_birth[q], qty_death[q]);
1456 if (qty_phys_reg[q] >= 0)
1460 #ifdef INSN_SCHEDULING
1461 /* Similarly, avoid false dependencies. */
1462 if (flag_schedule_insns_after_reload
1464 && !SMALL_REGISTER_CLASSES
1465 && qty_alternate_class[q] != NO_REGS)
1466 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1467 qty_mode[q], q, 0, 0,
1468 fake_birth, fake_death);
1470 if (qty_alternate_class[q] != NO_REGS)
1471 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1472 qty_mode[q], q, 0, 0,
1473 qty_birth[q], qty_death[q]);
1477 /* Now propagate the register assignments
1478 to the pseudo regs belonging to the qtys. */
1480 for (q = 0; q < next_qty; q++)
1481 if (qty_phys_reg[q] >= 0)
1483 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1484 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1488 /* Compare two quantities' priority for getting real registers.
1489 We give shorter-lived quantities higher priority.
1490 Quantities with more references are also preferred, as are quantities that
1491 require multiple registers. This is the identical prioritization as
1492 done by global-alloc.
1494 We used to give preference to registers with *longer* lives, but using
1495 the same algorithm in both local- and global-alloc can speed up execution
1496 of some programs by as much as a factor of three! */
1498 /* Note that the quotient will never be bigger than
1499 the value of floor_log2 times the maximum number of
1500 times a register can occur in one insn (surely less than 100).
1501 Multiplying this by 10000 can't overflow.
1502 QTY_CMP_PRI is also used by qty_sugg_compare. */
1504 #define QTY_CMP_PRI(q) \
1505 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1506 / (qty_death[q] - qty_birth[q])) * 10000))
1509 qty_compare (q1, q2)
1512 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1516 qty_compare_1 (q1p, q2p)
1517 const GENERIC_PTR q1p;
1518 const GENERIC_PTR q2p;
1520 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1521 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1526 /* If qtys are equally good, sort by qty number,
1527 so that the results of qsort leave nothing to chance. */
1531 /* Compare two quantities' priority for getting real registers. This version
1532 is called for quantities that have suggested hard registers. First priority
1533 goes to quantities that have copy preferences, then to those that have
1534 normal preferences. Within those groups, quantities with the lower
1535 number of preferences have the highest priority. Of those, we use the same
1536 algorithm as above. */
1538 #define QTY_CMP_SUGG(q) \
1539 (qty_phys_num_copy_sugg[q] \
1540 ? qty_phys_num_copy_sugg[q] \
1541 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1544 qty_sugg_compare (q1, q2)
1547 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1552 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1556 qty_sugg_compare_1 (q1p, q2p)
1557 const GENERIC_PTR q1p;
1558 const GENERIC_PTR q2p;
1560 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1561 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1566 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1570 /* If qtys are equally good, sort by qty number,
1571 so that the results of qsort leave nothing to chance. */
1578 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1579 Returns 1 if have done so, or 0 if cannot.
1581 Combining registers means marking them as having the same quantity
1582 and adjusting the offsets within the quantity if either of
1585 We don't actually combine a hard reg with a pseudo; instead
1586 we just record the hard reg as the suggestion for the pseudo's quantity.
1587 If we really combined them, we could lose if the pseudo lives
1588 across an insn that clobbers the hard reg (eg, movstr).
1590 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1591 there is no REG_DEAD note on INSN. This occurs during the processing
1592 of REG_NO_CONFLICT blocks.
1594 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1595 SETREG or if the input and output must share a register.
1596 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1598 There are elaborate checks for the validity of combining. */
1602 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1603 rtx usedreg, setreg;
1609 register int ureg, sreg;
1610 register int offset = 0;
1614 /* Determine the numbers and sizes of registers being used. If a subreg
1615 is present that does not change the entire register, don't consider
1616 this a copy insn. */
1618 while (GET_CODE (usedreg) == SUBREG)
1620 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1622 offset += SUBREG_WORD (usedreg);
1623 usedreg = SUBREG_REG (usedreg);
1625 if (GET_CODE (usedreg) != REG)
1627 ureg = REGNO (usedreg);
1628 usize = REG_SIZE (usedreg);
1630 while (GET_CODE (setreg) == SUBREG)
1632 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1634 offset -= SUBREG_WORD (setreg);
1635 setreg = SUBREG_REG (setreg);
1637 if (GET_CODE (setreg) != REG)
1639 sreg = REGNO (setreg);
1640 ssize = REG_SIZE (setreg);
1642 /* If UREG is a pseudo-register that hasn't already been assigned a
1643 quantity number, it means that it is not local to this block or dies
1644 more than once. In either event, we can't do anything with it. */
1645 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1646 /* Do not combine registers unless one fits within the other. */
1647 || (offset > 0 && usize + offset > ssize)
1648 || (offset < 0 && usize + offset < ssize)
1649 /* Do not combine with a smaller already-assigned object
1650 if that smaller object is already combined with something bigger. */
1651 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1652 && usize < qty_size[reg_qty[ureg]])
1653 /* Can't combine if SREG is not a register we can allocate. */
1654 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1655 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1656 These have already been taken care of. This probably wouldn't
1657 combine anyway, but don't take any chances. */
1658 || (ureg >= FIRST_PSEUDO_REGISTER
1659 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1660 /* Don't tie something to itself. In most cases it would make no
1661 difference, but it would screw up if the reg being tied to itself
1662 also dies in this insn. */
1664 /* Don't try to connect two different hardware registers. */
1665 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1666 /* Don't connect two different machine modes if they have different
1667 implications as to which registers may be used. */
1668 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1671 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1672 qty_phys_sugg for the pseudo instead of tying them.
1674 Return "failure" so that the lifespan of UREG is terminated here;
1675 that way the two lifespans will be disjoint and nothing will prevent
1676 the pseudo reg from being given this hard reg. */
1678 if (ureg < FIRST_PSEUDO_REGISTER)
1680 /* Allocate a quantity number so we have a place to put our
1682 if (reg_qty[sreg] == -2)
1683 reg_is_born (setreg, 2 * insn_number);
1685 if (reg_qty[sreg] >= 0)
1688 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1690 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1691 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1693 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1695 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1696 qty_phys_num_sugg[reg_qty[sreg]]++;
1702 /* Similarly for SREG a hard register and UREG a pseudo register. */
1704 if (sreg < FIRST_PSEUDO_REGISTER)
1707 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1709 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1710 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1712 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1714 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1715 qty_phys_num_sugg[reg_qty[ureg]]++;
1720 /* At this point we know that SREG and UREG are both pseudos.
1721 Do nothing if SREG already has a quantity or is a register that we
1723 if (reg_qty[sreg] >= -1
1724 /* If we are not going to let any regs live across calls,
1725 don't tie a call-crossing reg to a non-call-crossing reg. */
1726 || (current_function_has_nonlocal_label
1727 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1728 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1731 /* We don't already know about SREG, so tie it to UREG
1732 if this is the last use of UREG, provided the classes they want
1735 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1736 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1738 /* Add SREG to UREG's quantity. */
1739 sqty = reg_qty[ureg];
1740 reg_qty[sreg] = sqty;
1741 reg_offset[sreg] = reg_offset[ureg] + offset;
1742 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1743 qty_first_reg[sqty] = sreg;
1745 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1746 update_qty_class (sqty, sreg);
1748 /* Update info about quantity SQTY. */
1749 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1750 qty_n_refs[sqty] += REG_N_REFS (sreg);
1755 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1756 reg_offset[i] -= offset;
1758 qty_size[sqty] = ssize;
1759 qty_mode[sqty] = GET_MODE (setreg);
1768 /* Return 1 if the preferred class of REG allows it to be tied
1769 to a quantity or register whose class is CLASS.
1770 True if REG's reg class either contains or is contained in CLASS. */
1773 reg_meets_class_p (reg, class)
1775 enum reg_class class;
1777 register enum reg_class rclass = reg_preferred_class (reg);
1778 return (reg_class_subset_p (rclass, class)
1779 || reg_class_subset_p (class, rclass));
1782 /* Update the class of QTY assuming that REG is being tied to it. */
1785 update_qty_class (qty, reg)
1789 enum reg_class rclass = reg_preferred_class (reg);
1790 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1791 qty_min_class[qty] = rclass;
1793 rclass = reg_alternate_class (reg);
1794 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1795 qty_alternate_class[qty] = rclass;
1797 if (REG_CHANGES_SIZE (reg))
1798 qty_changes_size[qty] = 1;
1801 /* Handle something which alters the value of an rtx REG.
1803 REG is whatever is set or clobbered. SETTER is the rtx that
1804 is modifying the register.
1806 If it is not really a register, we do nothing.
1807 The file-global variables `this_insn' and `this_insn_number'
1808 carry info from `block_alloc'. */
1811 reg_is_set (reg, setter)
1815 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1816 a hard register. These may actually not exist any more. */
1818 if (GET_CODE (reg) != SUBREG
1819 && GET_CODE (reg) != REG)
1822 /* Mark this register as being born. If it is used in a CLOBBER, mark
1823 it as being born halfway between the previous insn and this insn so that
1824 it conflicts with our inputs but not the outputs of the previous insn. */
1826 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1829 /* Handle beginning of the life of register REG.
1830 BIRTH is the index at which this is happening. */
1833 reg_is_born (reg, birth)
1839 if (GET_CODE (reg) == SUBREG)
1840 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1842 regno = REGNO (reg);
1844 if (regno < FIRST_PSEUDO_REGISTER)
1846 mark_life (regno, GET_MODE (reg), 1);
1848 /* If the register was to have been born earlier that the present
1849 insn, mark it as live where it is actually born. */
1850 if (birth < 2 * this_insn_number)
1851 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1855 if (reg_qty[regno] == -2)
1856 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1858 /* If this register has a quantity number, show that it isn't dead. */
1859 if (reg_qty[regno] >= 0)
1860 qty_death[reg_qty[regno]] = -1;
1864 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1865 REG is an output that is dying (i.e., it is never used), otherwise it
1866 is an input (the normal case).
1867 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1870 wipe_dead_reg (reg, output_p)
1874 register int regno = REGNO (reg);
1876 /* If this insn has multiple results,
1877 and the dead reg is used in one of the results,
1878 extend its life to after this insn,
1879 so it won't get allocated together with any other result of this insn.
1881 It is unsafe to use !single_set here since it will ignore an unused
1882 output. Just because an output is unused does not mean the compiler
1883 can assume the side effect will not occur. Consider if REG appears
1884 in the address of an output and we reload the output. If we allocate
1885 REG to the same hard register as an unused output we could set the hard
1886 register before the output reload insn. */
1887 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1888 && multiple_sets (this_insn))
1891 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1893 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1894 if (GET_CODE (set) == SET
1895 && GET_CODE (SET_DEST (set)) != REG
1896 && !rtx_equal_p (reg, SET_DEST (set))
1897 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1902 /* If this register is used in an auto-increment address, then extend its
1903 life to after this insn, so that it won't get allocated together with
1904 the result of this insn. */
1905 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1908 if (regno < FIRST_PSEUDO_REGISTER)
1910 mark_life (regno, GET_MODE (reg), 0);
1912 /* If a hard register is dying as an output, mark it as in use at
1913 the beginning of this insn (the above statement would cause this
1916 post_mark_life (regno, GET_MODE (reg), 1,
1917 2 * this_insn_number, 2 * this_insn_number+ 1);
1920 else if (reg_qty[regno] >= 0)
1921 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1924 /* Find a block of SIZE words of hard regs in reg_class CLASS
1925 that can hold something of machine-mode MODE
1926 (but actually we test only the first of the block for holding MODE)
1927 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1928 and return the number of the first of them.
1929 Return -1 if such a block cannot be found.
1930 If QTY crosses calls, insist on a register preserved by calls,
1931 unless ACCEPT_CALL_CLOBBERED is nonzero.
1933 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1934 register is available. If not, return -1. */
1937 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1938 born_index, dead_index)
1939 enum reg_class class;
1940 enum machine_mode mode;
1942 int accept_call_clobbered;
1943 int just_try_suggested;
1944 int born_index, dead_index;
1946 register int i, ins;
1948 register /* Declare it register if it's a scalar. */
1950 HARD_REG_SET used, first_used;
1951 #ifdef ELIMINABLE_REGS
1952 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1955 /* Validate our parameters. */
1956 if (born_index < 0 || born_index > dead_index)
1959 /* Don't let a pseudo live in a reg across a function call
1960 if we might get a nonlocal goto. */
1961 if (current_function_has_nonlocal_label
1962 && qty_n_calls_crossed[qty] > 0)
1965 if (accept_call_clobbered)
1966 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1967 else if (qty_n_calls_crossed[qty] == 0)
1968 COPY_HARD_REG_SET (used, fixed_reg_set);
1970 COPY_HARD_REG_SET (used, call_used_reg_set);
1972 if (accept_call_clobbered)
1973 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1975 for (ins = born_index; ins < dead_index; ins++)
1976 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1978 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1980 /* Don't use the frame pointer reg in local-alloc even if
1981 we may omit the frame pointer, because if we do that and then we
1982 need a frame pointer, reload won't know how to move the pseudo
1983 to another hard reg. It can move only regs made by global-alloc.
1985 This is true of any register that can be eliminated. */
1986 #ifdef ELIMINABLE_REGS
1987 for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++)
1988 SET_HARD_REG_BIT (used, eliminables[i].from);
1989 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1990 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1991 that it might be eliminated into. */
1992 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1995 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1998 #ifdef CLASS_CANNOT_CHANGE_SIZE
1999 if (qty_changes_size[qty])
2000 IOR_HARD_REG_SET (used,
2001 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2004 /* Normally, the registers that can be used for the first register in
2005 a multi-register quantity are the same as those that can be used for
2006 subsequent registers. However, if just trying suggested registers,
2007 restrict our consideration to them. If there are copy-suggested
2008 register, try them. Otherwise, try the arithmetic-suggested
2010 COPY_HARD_REG_SET (first_used, used);
2012 if (just_try_suggested)
2014 if (qty_phys_num_copy_sugg[qty] != 0)
2015 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2017 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2020 /* If all registers are excluded, we can't do anything. */
2021 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2023 /* If at least one would be suitable, test each hard reg. */
2025 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2027 #ifdef REG_ALLOC_ORDER
2028 int regno = reg_alloc_order[i];
2032 if (! TEST_HARD_REG_BIT (first_used, regno)
2033 && HARD_REGNO_MODE_OK (regno, mode)
2034 && (qty_n_calls_crossed[qty] == 0
2035 || accept_call_clobbered
2036 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2039 register int size1 = HARD_REGNO_NREGS (regno, mode);
2040 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2043 /* Mark that this register is in use between its birth and death
2045 post_mark_life (regno, mode, 1, born_index, dead_index);
2048 #ifndef REG_ALLOC_ORDER
2049 i += j; /* Skip starting points we know will lose */
2056 /* If we are just trying suggested register, we have just tried copy-
2057 suggested registers, and there are arithmetic-suggested registers,
2060 /* If it would be profitable to allocate a call-clobbered register
2061 and save and restore it around calls, do that. */
2062 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2063 && qty_phys_num_sugg[qty] != 0)
2065 /* Don't try the copy-suggested regs again. */
2066 qty_phys_num_copy_sugg[qty] = 0;
2067 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2068 born_index, dead_index);
2071 /* We need not check to see if the current function has nonlocal
2072 labels because we don't put any pseudos that are live over calls in
2073 registers in that case. */
2075 if (! accept_call_clobbered
2076 && flag_caller_saves
2077 && ! just_try_suggested
2078 && qty_n_calls_crossed[qty] != 0
2079 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2081 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2083 caller_save_needed = 1;
2089 /* Mark that REGNO with machine-mode MODE is live starting from the current
2090 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2094 mark_life (regno, mode, life)
2096 enum machine_mode mode;
2099 register int j = HARD_REGNO_NREGS (regno, mode);
2102 SET_HARD_REG_BIT (regs_live, regno + j);
2105 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2108 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2109 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2110 to insn number DEATH (exclusive). */
2113 post_mark_life (regno, mode, life, birth, death)
2115 enum machine_mode mode;
2116 int life, birth, death;
2118 register int j = HARD_REGNO_NREGS (regno, mode);
2120 register /* Declare it register if it's a scalar. */
2122 HARD_REG_SET this_reg;
2124 CLEAR_HARD_REG_SET (this_reg);
2126 SET_HARD_REG_BIT (this_reg, regno + j);
2129 while (birth < death)
2131 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2135 while (birth < death)
2137 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2142 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2143 is the register being clobbered, and R1 is a register being used in
2144 the equivalent expression.
2146 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2147 in which it is used, return 1.
2149 Otherwise, return 0. */
2152 no_conflict_p (insn, r0, r1)
2156 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2159 /* If R1 is a hard register, return 0 since we handle this case
2160 when we scan the insns that actually use it. */
2163 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2164 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2165 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2168 last = XEXP (note, 0);
2170 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2171 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2173 if (find_reg_note (p, REG_DEAD, r1))
2176 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2177 some earlier optimization pass has inserted instructions into
2178 the sequence, and it is not safe to perform this optimization.
2179 Note that emit_no_conflict_block always ensures that this is
2180 true when these sequences are created. */
2181 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2188 #ifdef REGISTER_CONSTRAINTS
2190 /* Return the number of alternatives for which the constraint string P
2191 indicates that the operand must be equal to operand 0 and that no register
2200 int reg_allowed = 0;
2201 int num_matching_alts = 0;
2206 case '=': case '+': case '?':
2207 case '#': case '&': case '!':
2209 case '1': case '2': case '3': case '4':
2210 case 'm': case '<': case '>': case 'V': case 'o':
2211 case 'E': case 'F': case 'G': case 'H':
2212 case 's': case 'i': case 'n':
2213 case 'I': case 'J': case 'K': case 'L':
2214 case 'M': case 'N': case 'O': case 'P':
2215 #ifdef EXTRA_CONSTRAINT
2216 case 'Q': case 'R': case 'S': case 'T': case 'U':
2219 /* These don't say anything we care about. */
2223 if (found_zero && ! reg_allowed)
2224 num_matching_alts++;
2226 found_zero = reg_allowed = 0;
2240 if (found_zero && ! reg_allowed)
2241 num_matching_alts++;
2243 return num_matching_alts;
2245 #endif /* REGISTER_CONSTRAINTS */
2248 dump_local_alloc (file)
2252 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2253 if (reg_renumber[i] != -1)
2254 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);