1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Allocation of hard register numbers to pseudo registers is done in
22 two passes. In this pass we consider only regs that are born and
23 die once within one basic block. We do this one basic block at a
24 time. Then the next pass allocates the registers that remain.
25 Two passes are used because this pass uses methods that work only
26 on linear code, but that do a better job than the general methods
27 used in global_alloc, and more quickly too.
29 The assignments made are recorded in the vector reg_renumber
30 whose space is allocated here. The rtl code itself is not altered.
32 We assign each instruction in the basic block a number
33 which is its order from the beginning of the block.
34 Then we can represent the lifetime of a pseudo register with
35 a pair of numbers, and check for conflicts easily.
36 We can record the availability of hard registers with a
37 HARD_REG_SET for each instruction. The HARD_REG_SET
38 contains 0 or 1 for each hard reg.
40 To avoid register shuffling, we tie registers together when one
41 dies by being copied into another, or dies in an instruction that
42 does arithmetic to produce another. The tied registers are
43 allocated as one. Registers with different reg class preferences
44 can never be tied unless the class preferred by one is a subclass
45 of the one preferred by the other.
47 Tying is represented with "quantity numbers".
48 A non-tied register is given a new quantity number.
49 Tied registers have the same quantity number.
51 We have provision to exempt registers, even when they are contained
52 within the block, that can be tied to others that are not contained in it.
53 This is so that global_alloc could process them both and tie them then.
54 But this is currently disabled since tying in global_alloc is not
61 #include "basic-block.h"
63 #include "hard-reg-set.h"
64 #include "insn-config.h"
68 /* Pseudos allocated here cannot be reallocated by global.c if the hard
69 register is used as a spill register. So we don't allocate such pseudos
70 here if their preferred class is likely to be used by spills.
72 On most machines, the appropriate test is if the class has one
73 register, so we default to that. */
75 #ifndef CLASS_LIKELY_SPILLED_P
76 #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1)
79 /* Next quantity number available for allocation. */
83 /* In all the following vectors indexed by quantity number. */
85 /* Element Q is the hard reg number chosen for quantity Q,
86 or -1 if none was found. */
88 static short *qty_phys_reg;
90 /* We maintain two hard register sets that indicate suggested hard registers
91 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
92 that are tied to the quantity by a simple copy. The second contains all
93 hard registers that are tied to the quantity via an arithmetic operation.
95 The former register set is given priority for allocation. This tends to
96 eliminate copy insns. */
98 /* Element Q is a set of hard registers that are suggested for quantity Q by
101 static HARD_REG_SET *qty_phys_copy_sugg;
103 /* Element Q is a set of hard registers that are suggested for quantity Q by
106 static HARD_REG_SET *qty_phys_sugg;
108 /* Element Q is non-zero if there is a suggested register in
109 qty_phys_copy_sugg. */
111 static char *qty_phys_has_copy_sugg;
113 /* Element Q is non-zero if there is a suggested register in qty_phys_sugg. */
115 static char *qty_phys_has_sugg;
117 /* Element Q is the number of refs to quantity Q. */
119 static int *qty_n_refs;
121 /* Element Q is a reg class contained in (smaller than) the
122 preferred classes of all the pseudo regs that are tied in quantity Q.
123 This is the preferred class for allocating that quantity. */
125 static enum reg_class *qty_min_class;
127 /* Insn number (counting from head of basic block)
128 where quantity Q was born. -1 if birth has not been recorded. */
130 static int *qty_birth;
132 /* Insn number (counting from head of basic block)
133 where quantity Q died. Due to the way tying is done,
134 and the fact that we consider in this pass only regs that die but once,
135 a quantity can die only once. Each quantity's life span
136 is a set of consecutive insns. -1 if death has not been recorded. */
138 static int *qty_death;
140 /* Number of words needed to hold the data in quantity Q.
141 This depends on its machine mode. It is used for these purposes:
142 1. It is used in computing the relative importances of qtys,
143 which determines the order in which we look for regs for them.
144 2. It is used in rules that prevent tying several registers of
145 different sizes in a way that is geometrically impossible
146 (see combine_regs). */
148 static int *qty_size;
150 /* This holds the mode of the registers that are tied to qty Q,
151 or VOIDmode if registers with differing modes are tied together. */
153 static enum machine_mode *qty_mode;
155 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
157 static int *qty_n_calls_crossed;
159 /* Register class within which we allocate qty Q if we can't get
160 its preferred class. */
162 static enum reg_class *qty_alternate_class;
164 /* Element Q is the SCRATCH expression for which this quantity is being
165 allocated or 0 if this quantity is allocating registers. */
167 static rtx *qty_scratch_rtx;
169 /* Element Q is the register number of one pseudo register whose
170 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
171 register should be the head of the chain maintained in reg_next_in_qty. */
173 static int *qty_first_reg;
175 /* If (REG N) has been assigned a quantity number, is a register number
176 of another register assigned the same quantity number, or -1 for the
177 end of the chain. qty_first_reg point to the head of this chain. */
179 static int *reg_next_in_qty;
181 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
183 of -1 if this register cannot be allocated by local-alloc,
184 or -2 if not known yet.
186 Note that if we see a use or death of pseudo register N with
187 reg_qty[N] == -2, register N must be local to the current block. If
188 it were used in more than one block, we would have reg_qty[N] == -1.
189 This relies on the fact that if reg_basic_block[N] is >= 0, register N
190 will not appear in any other block. We save a considerable number of
191 tests by exploiting this.
193 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
198 /* The offset (in words) of register N within its quantity.
199 This can be nonzero if register N is SImode, and has been tied
200 to a subreg of a DImode register. */
202 static char *reg_offset;
204 /* Vector of substitutions of register numbers,
205 used to map pseudo regs into hardware regs.
206 This is set up as a result of register allocation.
207 Element N is the hard reg assigned to pseudo reg N,
208 or is -1 if no hard reg was assigned.
209 If N is a hard reg number, element N is N. */
213 /* Set of hard registers live at the current point in the scan
214 of the instructions in a basic block. */
216 static HARD_REG_SET regs_live;
218 /* Each set of hard registers indicates registers live at a particular
219 point in the basic block. For N even, regs_live_at[N] says which
220 hard registers are needed *after* insn N/2 (i.e., they may not
221 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
223 If an object is to conflict with the inputs of insn J but not the
224 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
225 if it is to conflict with the outputs of insn J but not the inputs of
226 insn J + 1, it is said to die at index J*2 + 1. */
228 static HARD_REG_SET *regs_live_at;
232 int scratch_list_length;
233 static int scratch_index;
235 /* Communicate local vars `insn_number' and `insn'
236 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
237 static int this_insn_number;
238 static rtx this_insn;
240 static void block_alloc ();
241 static void update_equiv_regs ();
242 static int no_conflict_p ();
243 static int combine_regs ();
244 static void wipe_dead_reg ();
245 static int find_free_reg ();
246 static void reg_is_born ();
247 static void reg_is_set ();
248 static void mark_life ();
249 static void post_mark_life ();
250 static int qty_compare ();
251 static int qty_compare_1 ();
252 static int reg_meets_class_p ();
253 static void update_qty_class ();
254 static int requires_inout_p ();
256 /* Allocate a new quantity (new within current basic block)
257 for register number REGNO which is born at index BIRTH
258 within the block. MODE and SIZE are info on reg REGNO. */
261 alloc_qty (regno, mode, size, birth)
263 enum machine_mode mode;
266 register int qty = next_qty++;
268 reg_qty[regno] = qty;
269 reg_offset[regno] = 0;
270 reg_next_in_qty[regno] = -1;
272 qty_first_reg[qty] = regno;
273 qty_size[qty] = size;
274 qty_mode[qty] = mode;
275 qty_birth[qty] = birth;
276 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
277 qty_min_class[qty] = reg_preferred_class (regno);
278 qty_alternate_class[qty] = reg_alternate_class (regno);
279 qty_n_refs[qty] = reg_n_refs[regno];
282 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
283 used as operand N in INSN. We assume here that the SCRATCH is used in
287 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
291 int insn_code_num, insn_number;
294 enum reg_class class;
298 #ifdef REGISTER_CONSTRAINTS
299 /* If we haven't yet computed which alternative will be used, do so now.
300 Then set P to the constraints for that alternative. */
301 if (which_alternative == -1)
302 if (! constrain_operands (insn_code_num, 0))
305 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
306 *p && i < which_alternative; p++)
310 /* Compute the class required for this SCRATCH. If we don't need a
311 register, the class will remain NO_REGS. If we guessed the alternative
312 number incorrectly, reload will fix things up for us. */
315 while ((c = *p++) != '\0' && c != ',')
318 case '=': case '+': case '?':
319 case '#': case '&': case '!':
321 case '0': case '1': case '2': case '3': case '4':
322 case 'm': case '<': case '>': case 'V': case 'o':
323 case 'E': case 'F': case 'G': case 'H':
324 case 's': case 'i': case 'n':
325 case 'I': case 'J': case 'K': case 'L':
326 case 'M': case 'N': case 'O': case 'P':
327 #ifdef EXTRA_CONSTRAINT
328 case 'Q': case 'R': case 'S': case 'T': case 'U':
331 /* These don't say anything we care about. */
335 /* We don't need to allocate this SCRATCH. */
339 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
344 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
348 /* If CLASS has only a few registers, don't allocate the SCRATCH here since
349 it will prevent that register from being used as a spill register.
350 reload will do the allocation. */
352 if (class == NO_REGS || CLASS_LIKELY_SPILLED_P (class))
355 #else /* REGISTER_CONSTRAINTS */
357 class = GENERAL_REGS;
363 qty_first_reg[qty] = -1;
364 qty_scratch_rtx[qty] = scratch;
365 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
366 qty_mode[qty] = GET_MODE (scratch);
367 qty_birth[qty] = 2 * insn_number - 1;
368 qty_death[qty] = 2 * insn_number + 1;
369 qty_n_calls_crossed[qty] = 0;
370 qty_min_class[qty] = class;
371 qty_alternate_class[qty] = NO_REGS;
375 /* Main entry point of this file. */
383 /* Leaf functions and non-leaf functions have different needs.
384 If defined, let the machine say what kind of ordering we
386 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
387 ORDER_REGS_FOR_LOCAL_ALLOC;
390 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
392 update_equiv_regs ();
394 /* This sets the maximum number of quantities we can have. Quantity
395 numbers start at zero and we can have one for each pseudo plus the
396 number of SCRATCHes in the largest block, in the worst case. */
397 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
399 /* Allocate vectors of temporary data.
400 See the declarations of these variables, above,
401 for what they mean. */
403 scratch_list_length = max_qty;
404 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
405 bzero (scratch_list, scratch_list_length * sizeof (rtx));
406 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
407 bzero (scratch_block, scratch_list_length * sizeof (int));
410 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
411 qty_phys_copy_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
412 qty_phys_has_copy_sugg = (char *) alloca (max_qty * sizeof (char));
413 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
414 qty_phys_has_sugg = (char *) alloca (max_qty * sizeof (char));
415 qty_birth = (int *) alloca (max_qty * sizeof (int));
416 qty_death = (int *) alloca (max_qty * sizeof (int));
417 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
418 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
419 qty_size = (int *) alloca (max_qty * sizeof (int));
420 qty_mode = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
421 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
422 qty_min_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
423 qty_alternate_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
424 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
426 reg_qty = (int *) alloca (max_regno * sizeof (int));
427 reg_offset = (char *) alloca (max_regno * sizeof (char));
428 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
430 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
431 for (i = 0; i < max_regno; i++)
432 reg_renumber[i] = -1;
434 /* Determine which pseudo-registers can be allocated by local-alloc.
435 In general, these are the registers used only in a single block and
436 which only die once. However, if a register's preferred class has only
437 a few entries, don't allocate this register here unless it is preferred
438 or nothing since retry_global_alloc won't be able to move it to
439 GENERAL_REGS if a reload register of this class is needed.
441 We need not be concerned with which block actually uses the register
442 since we will never see it outside that block. */
444 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
446 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
447 && (reg_alternate_class (i) == NO_REGS
448 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
454 /* Force loop below to initialize entire quantity array. */
457 /* Allocate each block's local registers, block by block. */
459 for (b = 0; b < n_basic_blocks; b++)
461 /* NEXT_QTY indicates which elements of the `qty_...'
462 vectors might need to be initialized because they were used
463 for the previous block; it is set to the entire array before
464 block 0. Initialize those, with explicit loop if there are few,
465 else with bzero and bcopy. Do not initialize vectors that are
466 explicit set by `alloc_qty'. */
470 for (i = 0; i < next_qty; i++)
472 qty_scratch_rtx[i] = 0;
473 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
474 qty_phys_has_copy_sugg[i] = 0;
475 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
476 qty_phys_has_sugg[i] = 0;
481 #define CLEAR(vector) \
482 bzero ((vector), (sizeof (*(vector))) * next_qty);
484 CLEAR (qty_scratch_rtx);
485 CLEAR (qty_phys_copy_sugg);
486 CLEAR (qty_phys_has_copy_sugg);
487 CLEAR (qty_phys_sugg);
488 CLEAR (qty_phys_has_sugg);
500 /* Depth of loops we are in while in update_equiv_regs. */
501 static int loop_depth;
503 /* Used for communication between the following two functions: contains
504 a MEM that we wish to ensure remains unchanged. */
505 static rtx equiv_mem;
507 /* Set nonzero if EQUIV_MEM is modified. */
508 static int equiv_mem_modified;
510 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
511 Called via note_stores. */
514 validate_equiv_mem_from_store (dest, set)
518 if ((GET_CODE (dest) == REG
519 && reg_overlap_mentioned_p (dest, equiv_mem))
520 || (GET_CODE (dest) == MEM
521 && true_dependence (dest, equiv_mem)))
522 equiv_mem_modified = 1;
525 /* Verify that no store between START and the death of REG invalidates
526 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
527 by storing into an overlapping memory location, or with a non-const
530 Return 1 if MEMREF remains valid. */
533 validate_equiv_mem (start, reg, memref)
542 equiv_mem_modified = 0;
544 /* If the memory reference has side effects or is volatile, it isn't a
545 valid equivalence. */
546 if (side_effects_p (memref))
549 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
551 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
554 if (find_reg_note (insn, REG_DEAD, reg))
557 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
558 && ! CONST_CALL_P (insn))
561 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
563 /* If a register mentioned in MEMREF is modified via an
564 auto-increment, we lose the equivalence. Do the same if one
565 dies; although we could extend the life, it doesn't seem worth
568 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
569 if ((REG_NOTE_KIND (note) == REG_INC
570 || REG_NOTE_KIND (note) == REG_DEAD)
571 && GET_CODE (XEXP (note, 0)) == REG
572 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
579 /* TRUE if X references a memory location that would be affected by a store
583 memref_referenced_p (memref, x)
589 enum rtx_code code = GET_CODE (x);
606 if (true_dependence (memref, x))
611 /* If we are setting a MEM, it doesn't count (its address does), but any
612 other SET_DEST that has a MEM in it is referencing the MEM. */
613 if (GET_CODE (SET_DEST (x)) == MEM)
615 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
618 else if (memref_referenced_p (memref, SET_DEST (x)))
621 return memref_referenced_p (memref, SET_SRC (x));
624 fmt = GET_RTX_FORMAT (code);
625 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
629 if (memref_referenced_p (memref, XEXP (x, i)))
633 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
634 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
642 /* TRUE if some insn in the range (START, END] references a memory location
643 that would be affected by a store to MEMREF. */
646 memref_used_between_p (memref, start, end)
653 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
654 insn = NEXT_INSN (insn))
655 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
656 && memref_referenced_p (memref, PATTERN (insn)))
662 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
665 Search forward to see if SRC dies before either it or DEST is modified,
666 but don't scan past the end of a basic block. If so, we can replace SRC
667 with DEST and let SRC die in INSN.
669 This will reduce the number of registers live in that range and may enable
670 DEST to be tied to SRC, thus often saving one register in addition to a
671 register-register copy. */
674 optimize_reg_copy_1 (insn, dest, src)
682 int sregno = REGNO (src);
683 int dregno = REGNO (dest);
686 #ifdef SMALL_REGISTER_CLASSES
687 /* We don't want to mess with hard regs if register classes are small. */
688 || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER
690 /* We don't see all updates to SP if they are in an auto-inc memory
691 reference, so we must disallow this optimization on them. */
692 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
695 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
697 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
698 || (GET_CODE (p) == NOTE
699 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
700 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
703 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
706 if (reg_set_p (src, p) || reg_set_p (dest, p)
707 /* Don't change a USE of a register. */
708 || (GET_CODE (PATTERN (p)) == USE
709 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
712 /* See if all of SRC dies in P. This test is slightly more
713 conservative than it needs to be. */
714 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
715 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
723 /* We can do the optimization. Scan forward from INSN again,
724 replacing regs as we go. Set FAILED if a replacement can't
725 be done. In that case, we can't move the death note for SRC.
726 This should be rare. */
728 /* Set to stop at next insn. */
729 for (q = next_real_insn (insn);
730 q != next_real_insn (p);
731 q = next_real_insn (q))
733 if (reg_overlap_mentioned_p (src, PATTERN (q)))
735 /* If SRC is a hard register, we might miss some
736 overlapping registers with validate_replace_rtx,
737 so we would have to undo it. We can't if DEST is
738 present in the insn, so fail in that combination
740 if (sregno < FIRST_PSEUDO_REGISTER
741 && reg_mentioned_p (dest, PATTERN (q)))
744 /* Replace all uses and make sure that the register
745 isn't still present. */
746 else if (validate_replace_rtx (src, dest, q)
747 && (sregno >= FIRST_PSEUDO_REGISTER
748 || ! reg_overlap_mentioned_p (src,
751 /* We assume that a register is used exactly once per
752 insn in the updates below. If this is not correct,
753 no great harm is done. */
754 if (sregno >= FIRST_PSEUDO_REGISTER)
755 reg_n_refs[sregno] -= loop_depth;
756 if (dregno >= FIRST_PSEUDO_REGISTER)
757 reg_n_refs[dregno] += loop_depth;
761 validate_replace_rtx (dest, src, q);
766 /* Count the insns and CALL_INSNs passed. If we passed the
767 death note of DEST, show increased live length. */
772 if (GET_CODE (q) == CALL_INSN)
779 /* If DEST dies here, remove the death note and save it for
780 later. Make sure ALL of DEST dies here; again, this is
781 overly conservative. */
783 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
784 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
785 remove_note (q, dest_death);
790 if (sregno >= FIRST_PSEUDO_REGISTER)
792 reg_live_length[sregno] -= length;
793 reg_n_calls_crossed[sregno] -= n_calls;
796 if (dregno >= FIRST_PSEUDO_REGISTER)
798 reg_live_length[dregno] += d_length;
799 reg_n_calls_crossed[dregno] += d_n_calls;
802 /* Move death note of SRC from P to INSN. */
803 remove_note (p, note);
804 XEXP (note, 1) = REG_NOTES (insn);
805 REG_NOTES (insn) = note;
808 /* Put death note of DEST on P if we saw it die. */
811 XEXP (dest_death, 1) = REG_NOTES (p);
812 REG_NOTES (p) = dest_death;
818 /* If SRC is a hard register which is set or killed in some other
819 way, we can't do this optimization. */
820 else if (sregno < FIRST_PSEUDO_REGISTER
821 && dead_or_set_p (p, src))
826 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
827 a sequence of insns that modify DEST followed by an insn that sets
828 SRC to DEST in which DEST dies, with no prior modification of DEST.
829 (There is no need to check if the insns in between actually modify
830 DEST. We should not have cases where DEST is not modified, but
831 the optimization is safe if no such modification is detected.)
832 In that case, we can replace all uses of DEST, starting with INSN and
833 ending with the set of SRC to DEST, with SRC. We do not do this
834 optimization if a CALL_INSN is crossed unless SRC already crosses a
837 It is assumed that DEST and SRC are pseudos; it is too complicated to do
838 this for hard registers since the substitutions we may make might fail. */
841 optimize_reg_copy_2 (insn, dest, src)
848 int sregno = REGNO (src);
849 int dregno = REGNO (dest);
851 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
853 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
854 || (GET_CODE (p) == NOTE
855 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
856 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
859 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
862 set = single_set (p);
863 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
864 && find_reg_note (p, REG_DEAD, dest))
866 /* We can do the optimization. Scan forward from INSN again,
867 replacing regs as we go. */
869 /* Set to stop at next insn. */
870 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
871 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
873 if (reg_mentioned_p (dest, PATTERN (q)))
875 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
877 /* We assume that a register is used exactly once per
878 insn in the updates below. If this is not correct,
879 no great harm is done. */
880 reg_n_refs[dregno] -= loop_depth;
881 reg_n_refs[sregno] += loop_depth;
885 if (GET_CODE (q) == CALL_INSN)
887 reg_n_calls_crossed[dregno]--;
888 reg_n_calls_crossed[sregno]++;
892 remove_note (p, find_reg_note (p, REG_DEAD, dest));
893 reg_n_deaths[dregno]--;
894 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
895 reg_n_deaths[sregno]--;
899 if (reg_set_p (src, p)
900 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
905 /* Find registers that are equivalent to a single value throughout the
906 compilation (either because they can be referenced in memory or are set once
907 from a single constant). Lower their priority for a register.
909 If such a register is only referenced once, try substituting its value
910 into the using insn. If it succeeds, we can eliminate the register
916 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
917 rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
920 bzero (reg_equiv_init_insn, max_regno * sizeof (rtx *));
921 bzero (reg_equiv_replacement, max_regno * sizeof (rtx *));
923 init_alias_analysis ();
927 /* Scan the insns and find which registers have equivalences. Do this
928 in a separate scan of the insns because (due to -fcse-follow-jumps)
929 a register can be set below its use. */
930 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
933 rtx set = single_set (insn);
937 if (GET_CODE (insn) == NOTE)
939 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
941 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
945 /* If this insn contains more (or less) than a single SET, ignore it. */
949 dest = SET_DEST (set);
951 /* If this sets a MEM to the contents of a REG that is only used
952 in a single basic block, see if the register is always equivalent
953 to that memory location and if moving the store from INSN to the
954 insn that set REG is safe. If so, put a REG_EQUIV note on the
955 initializing insn. */
957 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
958 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
959 && reg_basic_block[regno] >= 0
960 && reg_equiv_init_insn[regno] != 0
961 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
963 && ! memref_used_between_p (SET_DEST (set),
964 reg_equiv_init_insn[regno], insn))
965 REG_NOTES (reg_equiv_init_insn[regno])
966 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
967 REG_NOTES (reg_equiv_init_insn[regno]));
969 /* If this is a register-register copy where SRC is not dead, see if we
971 if (flag_expensive_optimizations && GET_CODE (dest) == REG
972 && GET_CODE (SET_SRC (set)) == REG
973 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
974 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
976 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
977 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
978 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
979 && GET_CODE (SET_SRC (set)) == REG
980 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
981 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
982 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
984 /* Otherwise, we only handle the case of a pseudo register being set
986 if (GET_CODE (dest) != REG
987 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
988 || reg_n_sets[regno] != 1)
991 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
993 /* Record this insn as initializing this register. */
994 reg_equiv_init_insn[regno] = insn;
996 /* If this register is known to be equal to a constant, record that
997 it is always equivalent to the constant. */
998 if (note && CONSTANT_P (XEXP (note, 0)))
999 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1001 /* If this insn introduces a "constant" register, decrease the priority
1002 of that register. Record this insn if the register is only used once
1003 more and the equivalence value is the same as our source.
1005 The latter condition is checked for two reasons: First, it is an
1006 indication that it may be more efficient to actually emit the insn
1007 as written (if no registers are available, reload will substitute
1008 the equivalence). Secondly, it avoids problems with any registers
1009 dying in this insn whose death notes would be missed.
1011 If we don't have a REG_EQUIV note, see if this insn is loading
1012 a register used only in one basic block from a MEM. If so, and the
1013 MEM remains unchanged for the life of the register, add a REG_EQUIV
1016 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1018 if (note == 0 && reg_basic_block[regno] >= 0
1019 && GET_CODE (SET_SRC (set)) == MEM
1020 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1021 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1024 /* Don't mess with things live during setjmp. */
1025 if (note && reg_live_length[regno] >= 0)
1027 int regno = REGNO (dest);
1029 /* Note that the statement below does not affect the priority
1031 reg_live_length[regno] *= 2;
1033 /* If the register is referenced exactly twice, meaning it is set
1034 once and used once, indicate that the reference may be replaced
1035 by the equivalence we computed above. If the register is only
1036 used in one basic block, this can't succeed or combine would
1039 It would be nice to use "loop_depth * 2" in the compare
1040 below. Unfortunately, LOOP_DEPTH need not be constant within
1041 a basic block so this would be too complicated.
1043 This case normally occurs when a parameter is read from memory
1044 and then used exactly once, not in a loop. */
1046 if (reg_n_refs[regno] == 2
1047 && reg_basic_block[regno] < 0
1048 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1049 reg_equiv_replacement[regno] = SET_SRC (set);
1053 /* Now scan all regs killed in an insn to see if any of them are registers
1054 only used that once. If so, see if we can replace the reference with
1055 the equivalent from. If we can, delete the initializing reference
1056 and this register will go away. */
1057 for (insn = next_active_insn (get_insns ());
1059 insn = next_active_insn (insn))
1063 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1064 if (REG_NOTE_KIND (link) == REG_DEAD
1065 /* Make sure this insn still refers to the register. */
1066 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1068 int regno = REGNO (XEXP (link, 0));
1070 if (reg_equiv_replacement[regno]
1071 && validate_replace_rtx (regno_reg_rtx[regno],
1072 reg_equiv_replacement[regno], insn))
1074 rtx equiv_insn = reg_equiv_init_insn[regno];
1076 remove_death (regno, insn);
1077 reg_n_refs[regno] = 0;
1078 PUT_CODE (equiv_insn, NOTE);
1079 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1080 NOTE_SOURCE_FILE (equiv_insn) = 0;
1086 /* Allocate hard regs to the pseudo regs used only within block number B.
1087 Only the pseudos that die but once can be handled. */
1096 int insn_number = 0;
1098 int max_uid = get_max_uid ();
1100 int no_conflict_combined_regno = -1;
1102 /* Count the instructions in the basic block. */
1104 insn = basic_block_end[b];
1107 if (GET_CODE (insn) != NOTE)
1108 if (++insn_count > max_uid)
1110 if (insn == basic_block_head[b])
1112 insn = PREV_INSN (insn);
1115 /* +2 to leave room for a post_mark_life at the last insn and for
1116 the birth of a CLOBBER in the first insn. */
1117 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1118 * sizeof (HARD_REG_SET));
1119 bzero (regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1121 /* Initialize table of hardware registers currently live. */
1124 regs_live = *basic_block_live_at_start[b];
1126 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1129 /* This loop scans the instructions of the basic block
1130 and assigns quantities to registers.
1131 It computes which registers to tie. */
1133 insn = basic_block_head[b];
1136 register rtx body = PATTERN (insn);
1138 if (GET_CODE (insn) != NOTE)
1141 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1143 register rtx link, set;
1144 register int win = 0;
1145 register rtx r0, r1;
1146 int combined_regno = -1;
1148 int insn_code_number = recog_memoized (insn);
1150 this_insn_number = insn_number;
1153 if (insn_code_number >= 0)
1154 insn_extract (insn);
1155 which_alternative = -1;
1157 /* Is this insn suitable for tying two registers?
1158 If so, try doing that.
1159 Suitable insns are those with at least two operands and where
1160 operand 0 is an output that is a register that is not
1163 We can tie operand 0 with some operand that dies in this insn.
1164 First look for operands that are required to be in the same
1165 register as operand 0. If we find such, only try tying that
1166 operand or one that can be put into that operand if the
1167 operation is commutative. If we don't find an operand
1168 that is required to be in the same register as operand 0,
1169 we can tie with any operand.
1171 Subregs in place of regs are also ok.
1173 If tying is done, WIN is set nonzero. */
1175 if (insn_code_number >= 0
1176 #ifdef REGISTER_CONSTRAINTS
1177 && insn_n_operands[insn_code_number] > 1
1178 && insn_operand_constraint[insn_code_number][0][0] == '='
1179 && insn_operand_constraint[insn_code_number][0][1] != '&'
1181 && GET_CODE (PATTERN (insn)) == SET
1182 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1186 #ifdef REGISTER_CONSTRAINTS
1187 int must_match_0 = -1;
1190 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1191 if (requires_inout_p
1192 (insn_operand_constraint[insn_code_number][i]))
1196 r0 = recog_operand[0];
1197 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1199 #ifdef REGISTER_CONSTRAINTS
1200 /* Skip this operand if we found an operand that
1201 must match operand 0 and this operand isn't it
1202 and can't be made to be it by commutativity. */
1204 if (must_match_0 >= 0 && i != must_match_0
1205 && ! (i == must_match_0 + 1
1206 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1207 && ! (i == must_match_0 - 1
1208 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1212 r1 = recog_operand[i];
1214 /* If the operand is an address, find a register in it.
1215 There may be more than one register, but we only try one
1218 #ifdef REGISTER_CONSTRAINTS
1219 insn_operand_constraint[insn_code_number][i][0] == 'p'
1221 insn_operand_address_p[insn_code_number][i]
1224 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1227 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1229 /* We have two priorities for hard register preferences.
1230 If we have a move insn or an insn whose first input
1231 can only be in the same register as the output, give
1232 priority to an equivalence found from that insn. */
1234 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1235 #ifdef REGISTER_CONSTRAINTS
1236 || (r1 == recog_operand[i] && must_match_0 >= 0)
1240 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1241 win = combine_regs (r1, r0, may_save_copy,
1242 insn_number, insn, 0);
1247 /* Recognize an insn sequence with an ultimate result
1248 which can safely overlap one of the inputs.
1249 The sequence begins with a CLOBBER of its result,
1250 and ends with an insn that copies the result to itself
1251 and has a REG_EQUAL note for an equivalent formula.
1252 That note indicates what the inputs are.
1253 The result and the input can overlap if each insn in
1254 the sequence either doesn't mention the input
1255 or has a REG_NO_CONFLICT note to inhibit the conflict.
1257 We do the combining test at the CLOBBER so that the
1258 destination register won't have had a quantity number
1259 assigned, since that would prevent combining. */
1261 if (GET_CODE (PATTERN (insn)) == CLOBBER
1262 && (r0 = XEXP (PATTERN (insn), 0),
1263 GET_CODE (r0) == REG)
1264 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1265 && XEXP (link, 0) != 0
1266 && GET_CODE (XEXP (link, 0)) == INSN
1267 && (set = single_set (XEXP (link, 0))) != 0
1268 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1269 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1272 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1273 /* Check that we have such a sequence. */
1274 && no_conflict_p (insn, r0, r1))
1275 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1276 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1277 && (r1 = XEXP (XEXP (note, 0), 0),
1278 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1279 && no_conflict_p (insn, r0, r1))
1280 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1282 /* Here we care if the operation to be computed is
1284 else if ((GET_CODE (XEXP (note, 0)) == EQ
1285 || GET_CODE (XEXP (note, 0)) == NE
1286 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1287 && (r1 = XEXP (XEXP (note, 0), 1),
1288 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1289 && no_conflict_p (insn, r0, r1))
1290 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1292 /* If we did combine something, show the register number
1293 in question so that we know to ignore its death. */
1295 no_conflict_combined_regno = REGNO (r1);
1298 /* If registers were just tied, set COMBINED_REGNO
1299 to the number of the register used in this insn
1300 that was tied to the register set in this insn.
1301 This register's qty should not be "killed". */
1305 while (GET_CODE (r1) == SUBREG)
1306 r1 = SUBREG_REG (r1);
1307 combined_regno = REGNO (r1);
1310 /* Mark the death of everything that dies in this instruction,
1311 except for anything that was just combined. */
1313 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1314 if (REG_NOTE_KIND (link) == REG_DEAD
1315 && GET_CODE (XEXP (link, 0)) == REG
1316 && combined_regno != REGNO (XEXP (link, 0))
1317 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1318 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1319 wipe_dead_reg (XEXP (link, 0), 0);
1321 /* Allocate qty numbers for all registers local to this block
1322 that are born (set) in this instruction.
1323 A pseudo that already has a qty is not changed. */
1325 note_stores (PATTERN (insn), reg_is_set);
1327 /* If anything is set in this insn and then unused, mark it as dying
1328 after this insn, so it will conflict with our outputs. This
1329 can't match with something that combined, and it doesn't matter
1330 if it did. Do this after the calls to reg_is_set since these
1331 die after, not during, the current insn. */
1333 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1334 if (REG_NOTE_KIND (link) == REG_UNUSED
1335 && GET_CODE (XEXP (link, 0)) == REG)
1336 wipe_dead_reg (XEXP (link, 0), 1);
1338 #ifndef SMALL_REGISTER_CLASSES
1339 /* Allocate quantities for any SCRATCH operands of this insn. We
1340 don't do this for machines with small register classes because
1341 those machines can use registers explicitly mentioned in the
1342 RTL as spill registers and our usage of hard registers
1343 explicitly for SCRATCH operands will conflict. On those machines,
1344 reload will allocate the SCRATCH. */
1346 if (insn_code_number >= 0)
1347 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1348 if (GET_CODE (recog_operand[i]) == SCRATCH
1349 && scratch_index < scratch_list_length - 1)
1350 alloc_qty_for_scratch (recog_operand[i], i, insn,
1351 insn_code_number, insn_number);
1354 /* If this is an insn that has a REG_RETVAL note pointing at a
1355 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1356 block, so clear any register number that combined within it. */
1357 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1358 && GET_CODE (XEXP (note, 0)) == INSN
1359 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1360 no_conflict_combined_regno = -1;
1363 /* Set the registers live after INSN_NUMBER. Note that we never
1364 record the registers live before the block's first insn, since no
1365 pseudos we care about are live before that insn. */
1367 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1368 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1370 if (insn == basic_block_end[b])
1373 insn = NEXT_INSN (insn);
1376 /* Now every register that is local to this basic block
1377 should have been given a quantity, or else -1 meaning ignore it.
1378 Every quantity should have a known birth and death.
1380 Order the qtys so we assign them registers in order of
1381 decreasing length of life. Normally call qsort, but if we
1382 have only a very small number of quantities, sort them ourselves. */
1384 qty_order = (int *) alloca (next_qty * sizeof (int));
1385 for (i = 0; i < next_qty; i++)
1388 #define EXCHANGE(I1, I2) \
1389 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1394 /* Make qty_order[2] be the one to allocate last. */
1395 if (qty_compare (0, 1) > 0)
1397 if (qty_compare (1, 2) > 0)
1400 /* ... Fall through ... */
1402 /* Put the best one to allocate in qty_order[0]. */
1403 if (qty_compare (0, 1) > 0)
1406 /* ... Fall through ... */
1410 /* Nothing to do here. */
1414 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1417 /* Try to put each quantity in a suggested physical register, if it has one.
1418 This may cause registers to be allocated that otherwise wouldn't be, but
1419 this seems acceptable in local allocation (unlike global allocation). */
1420 for (i = 0; i < next_qty; i++)
1423 if (qty_phys_has_sugg[q] || qty_phys_has_copy_sugg[q])
1424 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1425 0, 1, qty_birth[q], qty_death[q]);
1427 qty_phys_reg[q] = -1;
1430 /* Now for each qty that is not a hardware register,
1431 look for a hardware register to put it in.
1432 First try the register class that is cheapest for this qty,
1433 if there is more than one class. */
1435 for (i = 0; i < next_qty; i++)
1438 if (qty_phys_reg[q] < 0)
1440 if (N_REG_CLASSES > 1)
1442 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1443 qty_mode[q], q, 0, 0,
1444 qty_birth[q], qty_death[q]);
1445 if (qty_phys_reg[q] >= 0)
1449 if (qty_alternate_class[q] != NO_REGS)
1450 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1451 qty_mode[q], q, 0, 0,
1452 qty_birth[q], qty_death[q]);
1456 /* Now propagate the register assignments
1457 to the pseudo regs belonging to the qtys. */
1459 for (q = 0; q < next_qty; q++)
1460 if (qty_phys_reg[q] >= 0)
1462 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1463 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1464 if (qty_scratch_rtx[q])
1466 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1468 PUT_CODE (qty_scratch_rtx[q], REG);
1469 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1471 scratch_block[scratch_index] = b;
1472 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1474 /* Must clear the USED field, because it will have been set by
1475 copy_rtx_if_shared, but the leaf_register code expects that
1476 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1477 used bit for REGs, but does for SCRATCHes. */
1478 qty_scratch_rtx[q]->used = 0;
1483 /* Compare two quantities' priority for getting real registers.
1484 We give shorter-lived quantities higher priority.
1485 Quantities with more references are also preferred, as are quantities that
1486 require multiple registers. This is the identical prioritization as
1487 done by global-alloc.
1489 We used to give preference to registers with *longer* lives, but using
1490 the same algorithm in both local- and global-alloc can speed up execution
1491 of some programs by as much as a factor of three! */
1494 qty_compare (q1, q2)
1497 /* Note that the quotient will never be bigger than
1498 the value of floor_log2 times the maximum number of
1499 times a register can occur in one insn (surely less than 100).
1500 Multiplying this by 10000 can't overflow. */
1502 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1])
1503 / ((qty_death[q1] - qty_birth[q1]) * qty_size[q1]))
1506 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2])
1507 / ((qty_death[q2] - qty_birth[q2]) * qty_size[q2]))
1513 qty_compare_1 (q1, q2)
1518 /* Note that the quotient will never be bigger than
1519 the value of floor_log2 times the maximum number of
1520 times a register can occur in one insn (surely less than 100).
1521 Multiplying this by 10000 can't overflow. */
1523 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1])
1524 / ((qty_death[*q1] - qty_birth[*q1]) * qty_size[*q1]))
1527 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2])
1528 / ((qty_death[*q2] - qty_birth[*q2]) * qty_size[*q2]))
1532 if (tem != 0) return tem;
1533 /* If qtys are equally good, sort by qty number,
1534 so that the results of qsort leave nothing to chance. */
1538 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1539 Returns 1 if have done so, or 0 if cannot.
1541 Combining registers means marking them as having the same quantity
1542 and adjusting the offsets within the quantity if either of
1545 We don't actually combine a hard reg with a pseudo; instead
1546 we just record the hard reg as the suggestion for the pseudo's quantity.
1547 If we really combined them, we could lose if the pseudo lives
1548 across an insn that clobbers the hard reg (eg, movstr).
1550 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1551 there is no REG_DEAD note on INSN. This occurs during the processing
1552 of REG_NO_CONFLICT blocks.
1554 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1555 SETREG or if the input and output must share a register.
1556 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1558 There are elaborate checks for the validity of combining. */
1562 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1563 rtx usedreg, setreg;
1569 register int ureg, sreg;
1570 register int offset = 0;
1574 /* Determine the numbers and sizes of registers being used. If a subreg
1575 is present that does not change the entire register, don't consider
1576 this a copy insn. */
1578 while (GET_CODE (usedreg) == SUBREG)
1580 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1582 offset += SUBREG_WORD (usedreg);
1583 usedreg = SUBREG_REG (usedreg);
1585 if (GET_CODE (usedreg) != REG)
1587 ureg = REGNO (usedreg);
1588 usize = REG_SIZE (usedreg);
1590 while (GET_CODE (setreg) == SUBREG)
1592 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1594 offset -= SUBREG_WORD (setreg);
1595 setreg = SUBREG_REG (setreg);
1597 if (GET_CODE (setreg) != REG)
1599 sreg = REGNO (setreg);
1600 ssize = REG_SIZE (setreg);
1602 /* If UREG is a pseudo-register that hasn't already been assigned a
1603 quantity number, it means that it is not local to this block or dies
1604 more than once. In either event, we can't do anything with it. */
1605 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1606 /* Do not combine registers unless one fits within the other. */
1607 || (offset > 0 && usize + offset > ssize)
1608 || (offset < 0 && usize + offset < ssize)
1609 /* Do not combine with a smaller already-assigned object
1610 if that smaller object is already combined with something bigger. */
1611 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1612 && usize < qty_size[reg_qty[ureg]])
1613 /* Can't combine if SREG is not a register we can allocate. */
1614 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1615 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1616 These have already been taken care of. This probably wouldn't
1617 combine anyway, but don't take any chances. */
1618 || (ureg >= FIRST_PSEUDO_REGISTER
1619 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1620 /* Don't tie something to itself. In most cases it would make no
1621 difference, but it would screw up if the reg being tied to itself
1622 also dies in this insn. */
1624 /* Don't try to connect two different hardware registers. */
1625 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1626 /* Don't connect two different machine modes if they have different
1627 implications as to which registers may be used. */
1628 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1631 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1632 qty_phys_sugg for the pseudo instead of tying them.
1634 Return "failure" so that the lifespan of UREG is terminated here;
1635 that way the two lifespans will be disjoint and nothing will prevent
1636 the pseudo reg from being given this hard reg. */
1638 if (ureg < FIRST_PSEUDO_REGISTER)
1640 /* Allocate a quantity number so we have a place to put our
1642 if (reg_qty[sreg] == -2)
1643 reg_is_born (setreg, 2 * insn_number);
1645 if (reg_qty[sreg] >= 0)
1649 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1650 qty_phys_has_copy_sugg[reg_qty[sreg]] = 1;
1654 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1655 qty_phys_has_sugg[reg_qty[sreg]] = 1;
1661 /* Similarly for SREG a hard register and UREG a pseudo register. */
1663 if (sreg < FIRST_PSEUDO_REGISTER)
1667 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1668 qty_phys_has_copy_sugg[reg_qty[ureg]] = 1;
1672 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1673 qty_phys_has_sugg[reg_qty[ureg]] = 1;
1678 /* At this point we know that SREG and UREG are both pseudos.
1679 Do nothing if SREG already has a quantity or is a register that we
1681 if (reg_qty[sreg] >= -1
1682 /* If we are not going to let any regs live across calls,
1683 don't tie a call-crossing reg to a non-call-crossing reg. */
1684 || (current_function_has_nonlocal_label
1685 && ((reg_n_calls_crossed[ureg] > 0)
1686 != (reg_n_calls_crossed[sreg] > 0))))
1689 /* We don't already know about SREG, so tie it to UREG
1690 if this is the last use of UREG, provided the classes they want
1693 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1694 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1696 /* Add SREG to UREG's quantity. */
1697 sqty = reg_qty[ureg];
1698 reg_qty[sreg] = sqty;
1699 reg_offset[sreg] = reg_offset[ureg] + offset;
1700 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1701 qty_first_reg[sqty] = sreg;
1703 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1704 update_qty_class (sqty, sreg);
1706 /* Update info about quantity SQTY. */
1707 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1708 qty_n_refs[sqty] += reg_n_refs[sreg];
1713 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1714 reg_offset[i] -= offset;
1716 qty_size[sqty] = ssize;
1717 qty_mode[sqty] = GET_MODE (setreg);
1726 /* Return 1 if the preferred class of REG allows it to be tied
1727 to a quantity or register whose class is CLASS.
1728 True if REG's reg class either contains or is contained in CLASS. */
1731 reg_meets_class_p (reg, class)
1733 enum reg_class class;
1735 register enum reg_class rclass = reg_preferred_class (reg);
1736 return (reg_class_subset_p (rclass, class)
1737 || reg_class_subset_p (class, rclass));
1740 /* Return 1 if the two specified classes have registers in common.
1741 If CALL_SAVED, then consider only call-saved registers. */
1744 reg_classes_overlap_p (c1, c2, call_saved)
1745 register enum reg_class c1;
1746 register enum reg_class c2;
1752 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1753 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1755 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1756 if (TEST_HARD_REG_BIT (c, i)
1757 && (! call_saved || ! call_used_regs[i]))
1763 /* Update the class of QTY assuming that REG is being tied to it. */
1766 update_qty_class (qty, reg)
1770 enum reg_class rclass = reg_preferred_class (reg);
1771 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1772 qty_min_class[qty] = rclass;
1774 rclass = reg_alternate_class (reg);
1775 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1776 qty_alternate_class[qty] = rclass;
1779 /* Handle something which alters the value of an rtx REG.
1781 REG is whatever is set or clobbered. SETTER is the rtx that
1782 is modifying the register.
1784 If it is not really a register, we do nothing.
1785 The file-global variables `this_insn' and `this_insn_number'
1786 carry info from `block_alloc'. */
1789 reg_is_set (reg, setter)
1793 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1794 a hard register. These may actually not exist any more. */
1796 if (GET_CODE (reg) != SUBREG
1797 && GET_CODE (reg) != REG)
1800 /* Mark this register as being born. If it is used in a CLOBBER, mark
1801 it as being born halfway between the previous insn and this insn so that
1802 it conflicts with our inputs but not the outputs of the previous insn. */
1804 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1807 /* Handle beginning of the life of register REG.
1808 BIRTH is the index at which this is happening. */
1811 reg_is_born (reg, birth)
1817 if (GET_CODE (reg) == SUBREG)
1818 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1820 regno = REGNO (reg);
1822 if (regno < FIRST_PSEUDO_REGISTER)
1824 mark_life (regno, GET_MODE (reg), 1);
1826 /* If the register was to have been born earlier that the present
1827 insn, mark it as live where it is actually born. */
1828 if (birth < 2 * this_insn_number)
1829 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1833 if (reg_qty[regno] == -2)
1834 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1836 /* If this register has a quantity number, show that it isn't dead. */
1837 if (reg_qty[regno] >= 0)
1838 qty_death[reg_qty[regno]] = -1;
1842 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1843 REG is an output that is dying (i.e., it is never used), otherwise it
1844 is an input (the normal case).
1845 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1848 wipe_dead_reg (reg, output_p)
1852 register int regno = REGNO (reg);
1854 /* If this insn has multiple results,
1855 and the dead reg is used in one of the results,
1856 extend its life to after this insn,
1857 so it won't get allocated together with any other result of this insn. */
1858 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1859 && !single_set (this_insn))
1862 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1864 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1865 if (GET_CODE (set) == SET
1866 && GET_CODE (SET_DEST (set)) != REG
1867 && !rtx_equal_p (reg, SET_DEST (set))
1868 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1873 if (regno < FIRST_PSEUDO_REGISTER)
1875 mark_life (regno, GET_MODE (reg), 0);
1877 /* If a hard register is dying as an output, mark it as in use at
1878 the beginning of this insn (the above statement would cause this
1881 post_mark_life (regno, GET_MODE (reg), 1,
1882 2 * this_insn_number, 2 * this_insn_number+ 1);
1885 else if (reg_qty[regno] >= 0)
1886 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1889 /* Find a block of SIZE words of hard regs in reg_class CLASS
1890 that can hold something of machine-mode MODE
1891 (but actually we test only the first of the block for holding MODE)
1892 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1893 and return the number of the first of them.
1894 Return -1 if such a block cannot be found.
1895 If QTY crosses calls, insist on a register preserved by calls,
1896 unless ACCEPT_CALL_CLOBBERED is nonzero.
1898 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1899 register is available. If not, return -1. */
1902 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1903 born_index, dead_index)
1904 enum reg_class class;
1905 enum machine_mode mode;
1906 int accept_call_clobbered;
1907 int just_try_suggested;
1909 int born_index, dead_index;
1911 register int i, ins;
1913 register /* Declare it register if it's a scalar. */
1915 HARD_REG_SET used, first_used;
1916 #ifdef ELIMINABLE_REGS
1917 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1920 /* Validate our parameters. */
1921 if (born_index < 0 || born_index > dead_index)
1924 /* Don't let a pseudo live in a reg across a function call
1925 if we might get a nonlocal goto. */
1926 if (current_function_has_nonlocal_label
1927 && qty_n_calls_crossed[qty] > 0)
1930 if (accept_call_clobbered)
1931 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1932 else if (qty_n_calls_crossed[qty] == 0)
1933 COPY_HARD_REG_SET (used, fixed_reg_set);
1935 COPY_HARD_REG_SET (used, call_used_reg_set);
1937 for (ins = born_index; ins < dead_index; ins++)
1938 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1940 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1942 /* Don't use the frame pointer reg in local-alloc even if
1943 we may omit the frame pointer, because if we do that and then we
1944 need a frame pointer, reload won't know how to move the pseudo
1945 to another hard reg. It can move only regs made by global-alloc.
1947 This is true of any register that can be eliminated. */
1948 #ifdef ELIMINABLE_REGS
1949 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
1950 SET_HARD_REG_BIT (used, eliminables[i].from);
1952 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1955 /* Normally, the registers that can be used for the first register in
1956 a multi-register quantity are the same as those that can be used for
1957 subsequent registers. However, if just trying suggested registers,
1958 restrict our consideration to them. If there are copy-suggested
1959 register, try them. Otherwise, try the arithmetic-suggested
1961 COPY_HARD_REG_SET (first_used, used);
1963 if (just_try_suggested)
1965 if (qty_phys_has_copy_sugg[qty])
1966 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
1968 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
1971 /* If all registers are excluded, we can't do anything. */
1972 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
1974 /* If at least one would be suitable, test each hard reg. */
1976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1978 #ifdef REG_ALLOC_ORDER
1979 int regno = reg_alloc_order[i];
1983 if (! TEST_HARD_REG_BIT (first_used, regno)
1984 && HARD_REGNO_MODE_OK (regno, mode))
1987 register int size1 = HARD_REGNO_NREGS (regno, mode);
1988 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
1991 /* Mark that this register is in use between its birth and death
1993 post_mark_life (regno, mode, 1, born_index, dead_index);
1996 #ifndef REG_ALLOC_ORDER
1997 i += j; /* Skip starting points we know will lose */
2004 /* If we are just trying suggested register, we have just tried copy-
2005 suggested registers, and there are arithmetic-suggested registers,
2008 /* If it would be profitable to allocate a call-clobbered register
2009 and save and restore it around calls, do that. */
2010 if (just_try_suggested && qty_phys_has_copy_sugg[qty]
2011 && qty_phys_has_sugg[qty])
2013 /* Don't try the copy-suggested regs again. */
2014 qty_phys_has_copy_sugg[qty] = 0;
2015 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2016 born_index, dead_index);
2019 /* We need not check to see if the current function has nonlocal
2020 labels because we don't put any pseudos that are live over calls in
2021 registers in that case. */
2023 if (! accept_call_clobbered
2024 && flag_caller_saves
2025 && ! just_try_suggested
2026 && qty_n_calls_crossed[qty] != 0
2027 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2029 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2031 caller_save_needed = 1;
2037 /* Mark that REGNO with machine-mode MODE is live starting from the current
2038 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2042 mark_life (regno, mode, life)
2044 enum machine_mode mode;
2047 register int j = HARD_REGNO_NREGS (regno, mode);
2050 SET_HARD_REG_BIT (regs_live, regno + j);
2053 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2056 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2057 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2058 to insn number DEATH (exclusive). */
2061 post_mark_life (regno, mode, life, birth, death)
2062 register int regno, life, birth;
2063 enum machine_mode mode;
2066 register int j = HARD_REGNO_NREGS (regno, mode);
2068 register /* Declare it register if it's a scalar. */
2070 HARD_REG_SET this_reg;
2072 CLEAR_HARD_REG_SET (this_reg);
2074 SET_HARD_REG_BIT (this_reg, regno + j);
2077 while (birth < death)
2079 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2083 while (birth < death)
2085 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2090 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2091 is the register being clobbered, and R1 is a register being used in
2092 the equivalent expression.
2094 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2095 in which it is used, return 1.
2097 Otherwise, return 0. */
2100 no_conflict_p (insn, r0, r1)
2104 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2107 /* If R1 is a hard register, return 0 since we handle this case
2108 when we scan the insns that actually use it. */
2111 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2112 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2113 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2116 last = XEXP (note, 0);
2118 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2119 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2121 if (find_reg_note (p, REG_DEAD, r1))
2124 if (reg_mentioned_p (r1, PATTERN (p))
2125 && ! find_reg_note (p, REG_NO_CONFLICT, r1))
2132 #ifdef REGISTER_CONSTRAINTS
2134 /* Return 1 if the constraint string P indicates that the a the operand
2135 must be equal to operand 0 and that no register is acceptable. */
2138 requires_inout_p (p)
2151 case '=': case '+': case '?':
2152 case '#': case '&': case '!':
2153 case '*': case '%': case ',':
2154 case '1': case '2': case '3': case '4':
2155 case 'm': case '<': case '>': case 'V': case 'o':
2156 case 'E': case 'F': case 'G': case 'H':
2157 case 's': case 'i': case 'n':
2158 case 'I': case 'J': case 'K': case 'L':
2159 case 'M': case 'N': case 'O': case 'P':
2160 #ifdef EXTRA_CONSTRAINT
2161 case 'Q': case 'R': case 'S': case 'T': case 'U':
2164 /* These don't say anything we care about. */
2170 /* These mean a register is allowed. Fail if so. */
2176 #endif /* REGISTER_CONSTRAINTS */
2179 dump_local_alloc (file)
2183 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2184 if (reg_renumber[i] != -1)
2185 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);