1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93, 94, 1995 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
62 #include "basic-block.h"
64 #include "hard-reg-set.h"
65 #include "insn-config.h"
69 /* Pseudos allocated here cannot be reallocated by global.c if the hard
70 register is used as a spill register. So we don't allocate such pseudos
71 here if their preferred class is likely to be used by spills.
73 On most machines, the appropriate test is if the class has one
74 register, so we default to that. */
76 #ifndef CLASS_LIKELY_SPILLED_P
77 #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1)
80 /* Next quantity number available for allocation. */
84 /* In all the following vectors indexed by quantity number. */
86 /* Element Q is the hard reg number chosen for quantity Q,
87 or -1 if none was found. */
89 static short *qty_phys_reg;
91 /* We maintain two hard register sets that indicate suggested hard registers
92 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
93 that are tied to the quantity by a simple copy. The second contains all
94 hard registers that are tied to the quantity via an arithmetic operation.
96 The former register set is given priority for allocation. This tends to
97 eliminate copy insns. */
99 /* Element Q is a set of hard registers that are suggested for quantity Q by
102 static HARD_REG_SET *qty_phys_copy_sugg;
104 /* Element Q is a set of hard registers that are suggested for quantity Q by
107 static HARD_REG_SET *qty_phys_sugg;
109 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
111 static short *qty_phys_num_copy_sugg;
113 /* Element Q is the number of suggested registers in qty_phys_sugg. */
115 static short *qty_phys_num_sugg;
117 /* Element Q is the number of refs to quantity Q. */
119 static int *qty_n_refs;
121 /* Element Q is a reg class contained in (smaller than) the
122 preferred classes of all the pseudo regs that are tied in quantity Q.
123 This is the preferred class for allocating that quantity. */
125 static enum reg_class *qty_min_class;
127 /* Insn number (counting from head of basic block)
128 where quantity Q was born. -1 if birth has not been recorded. */
130 static int *qty_birth;
132 /* Insn number (counting from head of basic block)
133 where quantity Q died. Due to the way tying is done,
134 and the fact that we consider in this pass only regs that die but once,
135 a quantity can die only once. Each quantity's life span
136 is a set of consecutive insns. -1 if death has not been recorded. */
138 static int *qty_death;
140 /* Number of words needed to hold the data in quantity Q.
141 This depends on its machine mode. It is used for these purposes:
142 1. It is used in computing the relative importances of qtys,
143 which determines the order in which we look for regs for them.
144 2. It is used in rules that prevent tying several registers of
145 different sizes in a way that is geometrically impossible
146 (see combine_regs). */
148 static int *qty_size;
150 /* This holds the mode of the registers that are tied to qty Q,
151 or VOIDmode if registers with differing modes are tied together. */
153 static enum machine_mode *qty_mode;
155 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
157 static int *qty_n_calls_crossed;
159 /* Register class within which we allocate qty Q if we can't get
160 its preferred class. */
162 static enum reg_class *qty_alternate_class;
164 /* Element Q is the SCRATCH expression for which this quantity is being
165 allocated or 0 if this quantity is allocating registers. */
167 static rtx *qty_scratch_rtx;
169 /* Element Q is nonzero if this quantity has been used in a SUBREG
170 that changes its size. */
172 static char *qty_changes_size;
174 /* Element Q is the register number of one pseudo register whose
175 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
176 register should be the head of the chain maintained in reg_next_in_qty. */
178 static int *qty_first_reg;
180 /* If (REG N) has been assigned a quantity number, is a register number
181 of another register assigned the same quantity number, or -1 for the
182 end of the chain. qty_first_reg point to the head of this chain. */
184 static int *reg_next_in_qty;
186 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
188 of -1 if this register cannot be allocated by local-alloc,
189 or -2 if not known yet.
191 Note that if we see a use or death of pseudo register N with
192 reg_qty[N] == -2, register N must be local to the current block. If
193 it were used in more than one block, we would have reg_qty[N] == -1.
194 This relies on the fact that if reg_basic_block[N] is >= 0, register N
195 will not appear in any other block. We save a considerable number of
196 tests by exploiting this.
198 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
203 /* The offset (in words) of register N within its quantity.
204 This can be nonzero if register N is SImode, and has been tied
205 to a subreg of a DImode register. */
207 static char *reg_offset;
209 /* Vector of substitutions of register numbers,
210 used to map pseudo regs into hardware regs.
211 This is set up as a result of register allocation.
212 Element N is the hard reg assigned to pseudo reg N,
213 or is -1 if no hard reg was assigned.
214 If N is a hard reg number, element N is N. */
218 /* Set of hard registers live at the current point in the scan
219 of the instructions in a basic block. */
221 static HARD_REG_SET regs_live;
223 /* Each set of hard registers indicates registers live at a particular
224 point in the basic block. For N even, regs_live_at[N] says which
225 hard registers are needed *after* insn N/2 (i.e., they may not
226 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
228 If an object is to conflict with the inputs of insn J but not the
229 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
230 if it is to conflict with the outputs of insn J but not the inputs of
231 insn J + 1, it is said to die at index J*2 + 1. */
233 static HARD_REG_SET *regs_live_at;
237 int scratch_list_length;
238 static int scratch_index;
240 /* Communicate local vars `insn_number' and `insn'
241 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
242 static int this_insn_number;
243 static rtx this_insn;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int memref_referenced_p PROTO((rtx, rtx));
250 static int memref_used_between_p PROTO((rtx, rtx, rtx));
251 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
253 static void update_equiv_regs PROTO((void));
254 static void block_alloc PROTO((int));
255 static int qty_sugg_compare PROTO((int, int));
256 static int qty_sugg_compare_1 PROTO((int *, int *));
257 static int qty_compare PROTO((int, int));
258 static int qty_compare_1 PROTO((int *, int *));
259 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
260 static int reg_meets_class_p PROTO((int, enum reg_class));
261 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
263 static void update_qty_class PROTO((int, int));
264 static void reg_is_set PROTO((rtx, rtx));
265 static void reg_is_born PROTO((rtx, int));
266 static void wipe_dead_reg PROTO((rtx, int));
267 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
268 int, int, int, int, int));
269 static void mark_life PROTO((int, enum machine_mode, int));
270 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
271 static int no_conflict_p PROTO((rtx, rtx, rtx));
272 static int requires_inout PROTO((char *));
274 /* Allocate a new quantity (new within current basic block)
275 for register number REGNO which is born at index BIRTH
276 within the block. MODE and SIZE are info on reg REGNO. */
279 alloc_qty (regno, mode, size, birth)
281 enum machine_mode mode;
284 register int qty = next_qty++;
286 reg_qty[regno] = qty;
287 reg_offset[regno] = 0;
288 reg_next_in_qty[regno] = -1;
290 qty_first_reg[qty] = regno;
291 qty_size[qty] = size;
292 qty_mode[qty] = mode;
293 qty_birth[qty] = birth;
294 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
295 qty_min_class[qty] = reg_preferred_class (regno);
296 qty_alternate_class[qty] = reg_alternate_class (regno);
297 qty_n_refs[qty] = reg_n_refs[regno];
298 qty_changes_size[qty] = reg_changes_size[regno];
301 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
302 used as operand N in INSN. We assume here that the SCRATCH is used in
306 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
310 int insn_code_num, insn_number;
313 enum reg_class class;
317 #ifdef REGISTER_CONSTRAINTS
318 /* If we haven't yet computed which alternative will be used, do so now.
319 Then set P to the constraints for that alternative. */
320 if (which_alternative == -1)
321 if (! constrain_operands (insn_code_num, 0))
324 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
325 *p && i < which_alternative; p++)
329 /* Compute the class required for this SCRATCH. If we don't need a
330 register, the class will remain NO_REGS. If we guessed the alternative
331 number incorrectly, reload will fix things up for us. */
334 while ((c = *p++) != '\0' && c != ',')
337 case '=': case '+': case '?':
338 case '#': case '&': case '!':
340 case '0': case '1': case '2': case '3': case '4':
341 case 'm': case '<': case '>': case 'V': case 'o':
342 case 'E': case 'F': case 'G': case 'H':
343 case 's': case 'i': case 'n':
344 case 'I': case 'J': case 'K': case 'L':
345 case 'M': case 'N': case 'O': case 'P':
346 #ifdef EXTRA_CONSTRAINT
347 case 'Q': case 'R': case 'S': case 'T': case 'U':
350 /* These don't say anything we care about. */
354 /* We don't need to allocate this SCRATCH. */
358 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
363 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
367 if (class == NO_REGS)
370 #else /* REGISTER_CONSTRAINTS */
372 class = GENERAL_REGS;
378 qty_first_reg[qty] = -1;
379 qty_scratch_rtx[qty] = scratch;
380 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
381 qty_mode[qty] = GET_MODE (scratch);
382 qty_birth[qty] = 2 * insn_number - 1;
383 qty_death[qty] = 2 * insn_number + 1;
384 qty_n_calls_crossed[qty] = 0;
385 qty_min_class[qty] = class;
386 qty_alternate_class[qty] = NO_REGS;
388 qty_changes_size[qty] = 0;
391 /* Main entry point of this file. */
399 /* Leaf functions and non-leaf functions have different needs.
400 If defined, let the machine say what kind of ordering we
402 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
403 ORDER_REGS_FOR_LOCAL_ALLOC;
406 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
408 update_equiv_regs ();
410 /* This sets the maximum number of quantities we can have. Quantity
411 numbers start at zero and we can have one for each pseudo plus the
412 number of SCRATCHes in the largest block, in the worst case. */
413 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
415 /* Allocate vectors of temporary data.
416 See the declarations of these variables, above,
417 for what they mean. */
419 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
420 Instead of allocating this much memory from now until the end of
421 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
422 reload will allocate them. */
424 scratch_list_length = max_qty;
425 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
426 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
427 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
428 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
431 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
433 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
434 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
435 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
436 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
437 qty_birth = (int *) alloca (max_qty * sizeof (int));
438 qty_death = (int *) alloca (max_qty * sizeof (int));
439 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
440 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
441 qty_size = (int *) alloca (max_qty * sizeof (int));
443 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
444 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
446 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
448 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
450 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
452 reg_qty = (int *) alloca (max_regno * sizeof (int));
453 reg_offset = (char *) alloca (max_regno * sizeof (char));
454 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
456 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
457 for (i = 0; i < max_regno; i++)
458 reg_renumber[i] = -1;
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, equiv_mem)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X references a memory location that would be affected by a store
609 memref_referenced_p (memref, x)
615 enum rtx_code code = GET_CODE (x);
632 if (true_dependence (memref, x))
637 /* If we are setting a MEM, it doesn't count (its address does), but any
638 other SET_DEST that has a MEM in it is referencing the MEM. */
639 if (GET_CODE (SET_DEST (x)) == MEM)
641 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
644 else if (memref_referenced_p (memref, SET_DEST (x)))
647 return memref_referenced_p (memref, SET_SRC (x));
650 fmt = GET_RTX_FORMAT (code);
651 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
655 if (memref_referenced_p (memref, XEXP (x, i)))
659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
660 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
668 /* TRUE if some insn in the range (START, END] references a memory location
669 that would be affected by a store to MEMREF. */
672 memref_used_between_p (memref, start, end)
679 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
680 insn = NEXT_INSN (insn))
681 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
682 && memref_referenced_p (memref, PATTERN (insn)))
688 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
691 Search forward to see if SRC dies before either it or DEST is modified,
692 but don't scan past the end of a basic block. If so, we can replace SRC
693 with DEST and let SRC die in INSN.
695 This will reduce the number of registers live in that range and may enable
696 DEST to be tied to SRC, thus often saving one register in addition to a
697 register-register copy. */
700 optimize_reg_copy_1 (insn, dest, src)
708 int sregno = REGNO (src);
709 int dregno = REGNO (dest);
712 #ifdef SMALL_REGISTER_CLASSES
713 /* We don't want to mess with hard regs if register classes are small. */
714 || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER
716 /* We don't see all updates to SP if they are in an auto-inc memory
717 reference, so we must disallow this optimization on them. */
718 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
721 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
723 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
724 || (GET_CODE (p) == NOTE
725 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
726 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
729 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
732 if (reg_set_p (src, p) || reg_set_p (dest, p)
733 /* Don't change a USE of a register. */
734 || (GET_CODE (PATTERN (p)) == USE
735 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
738 /* See if all of SRC dies in P. This test is slightly more
739 conservative than it needs to be. */
740 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
741 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
749 /* We can do the optimization. Scan forward from INSN again,
750 replacing regs as we go. Set FAILED if a replacement can't
751 be done. In that case, we can't move the death note for SRC.
752 This should be rare. */
754 /* Set to stop at next insn. */
755 for (q = next_real_insn (insn);
756 q != next_real_insn (p);
757 q = next_real_insn (q))
759 if (reg_overlap_mentioned_p (src, PATTERN (q)))
761 /* If SRC is a hard register, we might miss some
762 overlapping registers with validate_replace_rtx,
763 so we would have to undo it. We can't if DEST is
764 present in the insn, so fail in that combination
766 if (sregno < FIRST_PSEUDO_REGISTER
767 && reg_mentioned_p (dest, PATTERN (q)))
770 /* Replace all uses and make sure that the register
771 isn't still present. */
772 else if (validate_replace_rtx (src, dest, q)
773 && (sregno >= FIRST_PSEUDO_REGISTER
774 || ! reg_overlap_mentioned_p (src,
777 /* We assume that a register is used exactly once per
778 insn in the updates below. If this is not correct,
779 no great harm is done. */
780 if (sregno >= FIRST_PSEUDO_REGISTER)
781 reg_n_refs[sregno] -= loop_depth;
782 if (dregno >= FIRST_PSEUDO_REGISTER)
783 reg_n_refs[dregno] += loop_depth;
787 validate_replace_rtx (dest, src, q);
792 /* Count the insns and CALL_INSNs passed. If we passed the
793 death note of DEST, show increased live length. */
798 /* If the insn in which SRC dies is a CALL_INSN, don't count it
799 as a call that has been crossed. Otherwise, count it. */
800 if (q != p && GET_CODE (q) == CALL_INSN)
807 /* If DEST dies here, remove the death note and save it for
808 later. Make sure ALL of DEST dies here; again, this is
809 overly conservative. */
811 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
812 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
813 remove_note (q, dest_death);
818 if (sregno >= FIRST_PSEUDO_REGISTER)
820 reg_live_length[sregno] -= length;
821 /* reg_live_length is only an approximation after combine
822 if sched is not run, so make sure that we still have
823 a reasonable value. */
824 if (reg_live_length[sregno] < 2)
825 reg_live_length[sregno] = 2;
826 reg_n_calls_crossed[sregno] -= n_calls;
829 if (dregno >= FIRST_PSEUDO_REGISTER)
831 reg_live_length[dregno] += d_length;
832 reg_n_calls_crossed[dregno] += d_n_calls;
835 /* Move death note of SRC from P to INSN. */
836 remove_note (p, note);
837 XEXP (note, 1) = REG_NOTES (insn);
838 REG_NOTES (insn) = note;
841 /* Put death note of DEST on P if we saw it die. */
844 XEXP (dest_death, 1) = REG_NOTES (p);
845 REG_NOTES (p) = dest_death;
851 /* If SRC is a hard register which is set or killed in some other
852 way, we can't do this optimization. */
853 else if (sregno < FIRST_PSEUDO_REGISTER
854 && dead_or_set_p (p, src))
859 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
860 a sequence of insns that modify DEST followed by an insn that sets
861 SRC to DEST in which DEST dies, with no prior modification of DEST.
862 (There is no need to check if the insns in between actually modify
863 DEST. We should not have cases where DEST is not modified, but
864 the optimization is safe if no such modification is detected.)
865 In that case, we can replace all uses of DEST, starting with INSN and
866 ending with the set of SRC to DEST, with SRC. We do not do this
867 optimization if a CALL_INSN is crossed unless SRC already crosses a
868 call or if DEST dies before the copy back to SRC.
870 It is assumed that DEST and SRC are pseudos; it is too complicated to do
871 this for hard registers since the substitutions we may make might fail. */
874 optimize_reg_copy_2 (insn, dest, src)
881 int sregno = REGNO (src);
882 int dregno = REGNO (dest);
884 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
886 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
887 || (GET_CODE (p) == NOTE
888 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
889 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
892 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
895 set = single_set (p);
896 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
897 && find_reg_note (p, REG_DEAD, dest))
899 /* We can do the optimization. Scan forward from INSN again,
900 replacing regs as we go. */
902 /* Set to stop at next insn. */
903 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
904 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
906 if (reg_mentioned_p (dest, PATTERN (q)))
908 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
910 /* We assume that a register is used exactly once per
911 insn in the updates below. If this is not correct,
912 no great harm is done. */
913 reg_n_refs[dregno] -= loop_depth;
914 reg_n_refs[sregno] += loop_depth;
918 if (GET_CODE (q) == CALL_INSN)
920 reg_n_calls_crossed[dregno]--;
921 reg_n_calls_crossed[sregno]++;
925 remove_note (p, find_reg_note (p, REG_DEAD, dest));
926 reg_n_deaths[dregno]--;
927 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
928 reg_n_deaths[sregno]--;
932 if (reg_set_p (src, p)
933 || find_reg_note (p, REG_DEAD, dest)
934 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
939 /* Find registers that are equivalent to a single value throughout the
940 compilation (either because they can be referenced in memory or are set once
941 from a single constant). Lower their priority for a register.
943 If such a register is only referenced once, try substituting its value
944 into the using insn. If it succeeds, we can eliminate the register
950 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
951 rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
954 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
955 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
957 init_alias_analysis ();
961 /* Scan the insns and find which registers have equivalences. Do this
962 in a separate scan of the insns because (due to -fcse-follow-jumps)
963 a register can be set below its use. */
964 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
967 rtx set = single_set (insn);
971 if (GET_CODE (insn) == NOTE)
973 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
975 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
979 /* If this insn contains more (or less) than a single SET, ignore it. */
983 dest = SET_DEST (set);
985 /* If this sets a MEM to the contents of a REG that is only used
986 in a single basic block, see if the register is always equivalent
987 to that memory location and if moving the store from INSN to the
988 insn that set REG is safe. If so, put a REG_EQUIV note on the
989 initializing insn. */
991 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
992 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
993 && reg_basic_block[regno] >= 0
994 && reg_equiv_init_insn[regno] != 0
995 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
997 && ! memref_used_between_p (SET_DEST (set),
998 reg_equiv_init_insn[regno], insn))
999 REG_NOTES (reg_equiv_init_insn[regno])
1000 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1001 REG_NOTES (reg_equiv_init_insn[regno]));
1003 /* If this is a register-register copy where SRC is not dead, see if we
1005 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1006 && GET_CODE (SET_SRC (set)) == REG
1007 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1008 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1010 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1011 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1012 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1013 && GET_CODE (SET_SRC (set)) == REG
1014 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1015 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1016 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1018 /* Otherwise, we only handle the case of a pseudo register being set
1020 if (GET_CODE (dest) != REG
1021 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1022 || reg_n_sets[regno] != 1)
1025 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1027 /* Record this insn as initializing this register. */
1028 reg_equiv_init_insn[regno] = insn;
1030 /* If this register is known to be equal to a constant, record that
1031 it is always equivalent to the constant. */
1032 if (note && CONSTANT_P (XEXP (note, 0)))
1033 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1035 /* If this insn introduces a "constant" register, decrease the priority
1036 of that register. Record this insn if the register is only used once
1037 more and the equivalence value is the same as our source.
1039 The latter condition is checked for two reasons: First, it is an
1040 indication that it may be more efficient to actually emit the insn
1041 as written (if no registers are available, reload will substitute
1042 the equivalence). Secondly, it avoids problems with any registers
1043 dying in this insn whose death notes would be missed.
1045 If we don't have a REG_EQUIV note, see if this insn is loading
1046 a register used only in one basic block from a MEM. If so, and the
1047 MEM remains unchanged for the life of the register, add a REG_EQUIV
1050 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1052 if (note == 0 && reg_basic_block[regno] >= 0
1053 && GET_CODE (SET_SRC (set)) == MEM
1054 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1055 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1058 /* Don't mess with things live during setjmp. */
1059 if (note && reg_live_length[regno] >= 0)
1061 int regno = REGNO (dest);
1063 /* Note that the statement below does not affect the priority
1065 reg_live_length[regno] *= 2;
1067 /* If the register is referenced exactly twice, meaning it is set
1068 once and used once, indicate that the reference may be replaced
1069 by the equivalence we computed above. If the register is only
1070 used in one basic block, this can't succeed or combine would
1073 It would be nice to use "loop_depth * 2" in the compare
1074 below. Unfortunately, LOOP_DEPTH need not be constant within
1075 a basic block so this would be too complicated.
1077 This case normally occurs when a parameter is read from memory
1078 and then used exactly once, not in a loop. */
1080 if (reg_n_refs[regno] == 2
1081 && reg_basic_block[regno] < 0
1082 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1083 reg_equiv_replacement[regno] = SET_SRC (set);
1087 /* Now scan all regs killed in an insn to see if any of them are registers
1088 only used that once. If so, see if we can replace the reference with
1089 the equivalent from. If we can, delete the initializing reference
1090 and this register will go away. */
1091 for (insn = next_active_insn (get_insns ());
1093 insn = next_active_insn (insn))
1097 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1098 if (REG_NOTE_KIND (link) == REG_DEAD
1099 /* Make sure this insn still refers to the register. */
1100 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1102 int regno = REGNO (XEXP (link, 0));
1104 if (reg_equiv_replacement[regno]
1105 && validate_replace_rtx (regno_reg_rtx[regno],
1106 reg_equiv_replacement[regno], insn))
1108 rtx equiv_insn = reg_equiv_init_insn[regno];
1110 remove_death (regno, insn);
1111 reg_n_refs[regno] = 0;
1112 PUT_CODE (equiv_insn, NOTE);
1113 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1114 NOTE_SOURCE_FILE (equiv_insn) = 0;
1120 /* Allocate hard regs to the pseudo regs used only within block number B.
1121 Only the pseudos that die but once can be handled. */
1130 int insn_number = 0;
1132 int max_uid = get_max_uid ();
1134 int no_conflict_combined_regno = -1;
1135 /* Counter to prevent allocating more SCRATCHes than can be stored
1137 int scratches_allocated = scratch_index;
1139 /* Count the instructions in the basic block. */
1141 insn = basic_block_end[b];
1144 if (GET_CODE (insn) != NOTE)
1145 if (++insn_count > max_uid)
1147 if (insn == basic_block_head[b])
1149 insn = PREV_INSN (insn);
1152 /* +2 to leave room for a post_mark_life at the last insn and for
1153 the birth of a CLOBBER in the first insn. */
1154 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1155 * sizeof (HARD_REG_SET));
1156 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1158 /* Initialize table of hardware registers currently live. */
1161 regs_live = *basic_block_live_at_start[b];
1163 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1166 /* This loop scans the instructions of the basic block
1167 and assigns quantities to registers.
1168 It computes which registers to tie. */
1170 insn = basic_block_head[b];
1173 register rtx body = PATTERN (insn);
1175 if (GET_CODE (insn) != NOTE)
1178 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1180 register rtx link, set;
1181 register int win = 0;
1182 register rtx r0, r1;
1183 int combined_regno = -1;
1185 int insn_code_number = recog_memoized (insn);
1187 this_insn_number = insn_number;
1190 if (insn_code_number >= 0)
1191 insn_extract (insn);
1192 which_alternative = -1;
1194 /* Is this insn suitable for tying two registers?
1195 If so, try doing that.
1196 Suitable insns are those with at least two operands and where
1197 operand 0 is an output that is a register that is not
1200 We can tie operand 0 with some operand that dies in this insn.
1201 First look for operands that are required to be in the same
1202 register as operand 0. If we find such, only try tying that
1203 operand or one that can be put into that operand if the
1204 operation is commutative. If we don't find an operand
1205 that is required to be in the same register as operand 0,
1206 we can tie with any operand.
1208 Subregs in place of regs are also ok.
1210 If tying is done, WIN is set nonzero. */
1212 if (insn_code_number >= 0
1213 #ifdef REGISTER_CONSTRAINTS
1214 && insn_n_operands[insn_code_number] > 1
1215 && insn_operand_constraint[insn_code_number][0][0] == '='
1216 && insn_operand_constraint[insn_code_number][0][1] != '&'
1218 && GET_CODE (PATTERN (insn)) == SET
1219 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1223 #ifdef REGISTER_CONSTRAINTS
1224 /* If non-negative, is an operand that must match operand 0. */
1225 int must_match_0 = -1;
1226 /* Counts number of alternatives that require a match with
1228 int n_matching_alts = 0;
1230 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1232 char *p = insn_operand_constraint[insn_code_number][i];
1233 int this_match = (requires_inout (p));
1235 n_matching_alts += this_match;
1236 if (this_match == insn_n_alternatives[insn_code_number])
1241 r0 = recog_operand[0];
1242 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1244 #ifdef REGISTER_CONSTRAINTS
1245 /* Skip this operand if we found an operand that
1246 must match operand 0 and this operand isn't it
1247 and can't be made to be it by commutativity. */
1249 if (must_match_0 >= 0 && i != must_match_0
1250 && ! (i == must_match_0 + 1
1251 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1252 && ! (i == must_match_0 - 1
1253 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1256 /* Likewise if each alternative has some operand that
1257 must match operand zero. In that case, skip any
1258 operand that doesn't list operand 0 since we know that
1259 the operand always conflicts with operand 0. We
1260 ignore commutatity in this case to keep things simple. */
1261 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1262 && (0 == requires_inout
1263 (insn_operand_constraint[insn_code_number][i])))
1267 r1 = recog_operand[i];
1269 /* If the operand is an address, find a register in it.
1270 There may be more than one register, but we only try one
1273 #ifdef REGISTER_CONSTRAINTS
1274 insn_operand_constraint[insn_code_number][i][0] == 'p'
1276 insn_operand_address_p[insn_code_number][i]
1279 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1282 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1284 /* We have two priorities for hard register preferences.
1285 If we have a move insn or an insn whose first input
1286 can only be in the same register as the output, give
1287 priority to an equivalence found from that insn. */
1289 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1290 #ifdef REGISTER_CONSTRAINTS
1291 || (r1 == recog_operand[i] && must_match_0 >= 0)
1295 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1296 win = combine_regs (r1, r0, may_save_copy,
1297 insn_number, insn, 0);
1304 /* Recognize an insn sequence with an ultimate result
1305 which can safely overlap one of the inputs.
1306 The sequence begins with a CLOBBER of its result,
1307 and ends with an insn that copies the result to itself
1308 and has a REG_EQUAL note for an equivalent formula.
1309 That note indicates what the inputs are.
1310 The result and the input can overlap if each insn in
1311 the sequence either doesn't mention the input
1312 or has a REG_NO_CONFLICT note to inhibit the conflict.
1314 We do the combining test at the CLOBBER so that the
1315 destination register won't have had a quantity number
1316 assigned, since that would prevent combining. */
1318 if (GET_CODE (PATTERN (insn)) == CLOBBER
1319 && (r0 = XEXP (PATTERN (insn), 0),
1320 GET_CODE (r0) == REG)
1321 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1322 && XEXP (link, 0) != 0
1323 && GET_CODE (XEXP (link, 0)) == INSN
1324 && (set = single_set (XEXP (link, 0))) != 0
1325 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1326 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1329 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1330 /* Check that we have such a sequence. */
1331 && no_conflict_p (insn, r0, r1))
1332 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1333 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1334 && (r1 = XEXP (XEXP (note, 0), 0),
1335 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1336 && no_conflict_p (insn, r0, r1))
1337 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1339 /* Here we care if the operation to be computed is
1341 else if ((GET_CODE (XEXP (note, 0)) == EQ
1342 || GET_CODE (XEXP (note, 0)) == NE
1343 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1344 && (r1 = XEXP (XEXP (note, 0), 1),
1345 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1346 && no_conflict_p (insn, r0, r1))
1347 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1349 /* If we did combine something, show the register number
1350 in question so that we know to ignore its death. */
1352 no_conflict_combined_regno = REGNO (r1);
1355 /* If registers were just tied, set COMBINED_REGNO
1356 to the number of the register used in this insn
1357 that was tied to the register set in this insn.
1358 This register's qty should not be "killed". */
1362 while (GET_CODE (r1) == SUBREG)
1363 r1 = SUBREG_REG (r1);
1364 combined_regno = REGNO (r1);
1367 /* Mark the death of everything that dies in this instruction,
1368 except for anything that was just combined. */
1370 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1371 if (REG_NOTE_KIND (link) == REG_DEAD
1372 && GET_CODE (XEXP (link, 0)) == REG
1373 && combined_regno != REGNO (XEXP (link, 0))
1374 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1375 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1376 wipe_dead_reg (XEXP (link, 0), 0);
1378 /* Allocate qty numbers for all registers local to this block
1379 that are born (set) in this instruction.
1380 A pseudo that already has a qty is not changed. */
1382 note_stores (PATTERN (insn), reg_is_set);
1384 /* If anything is set in this insn and then unused, mark it as dying
1385 after this insn, so it will conflict with our outputs. This
1386 can't match with something that combined, and it doesn't matter
1387 if it did. Do this after the calls to reg_is_set since these
1388 die after, not during, the current insn. */
1390 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1391 if (REG_NOTE_KIND (link) == REG_UNUSED
1392 && GET_CODE (XEXP (link, 0)) == REG)
1393 wipe_dead_reg (XEXP (link, 0), 1);
1395 /* Allocate quantities for any SCRATCH operands of this insn. */
1397 if (insn_code_number >= 0)
1398 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1399 if (GET_CODE (recog_operand[i]) == SCRATCH
1400 && scratches_allocated++ < scratch_list_length)
1401 alloc_qty_for_scratch (recog_operand[i], i, insn,
1402 insn_code_number, insn_number);
1404 /* If this is an insn that has a REG_RETVAL note pointing at a
1405 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1406 block, so clear any register number that combined within it. */
1407 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1408 && GET_CODE (XEXP (note, 0)) == INSN
1409 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1410 no_conflict_combined_regno = -1;
1413 /* Set the registers live after INSN_NUMBER. Note that we never
1414 record the registers live before the block's first insn, since no
1415 pseudos we care about are live before that insn. */
1417 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1418 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1420 if (insn == basic_block_end[b])
1423 insn = NEXT_INSN (insn);
1426 /* Now every register that is local to this basic block
1427 should have been given a quantity, or else -1 meaning ignore it.
1428 Every quantity should have a known birth and death.
1430 Order the qtys so we assign them registers in order of the
1431 number of suggested registers they need so we allocate those with
1432 the most restrictive needs first. */
1434 qty_order = (int *) alloca (next_qty * sizeof (int));
1435 for (i = 0; i < next_qty; i++)
1438 #define EXCHANGE(I1, I2) \
1439 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1444 /* Make qty_order[2] be the one to allocate last. */
1445 if (qty_sugg_compare (0, 1) > 0)
1447 if (qty_sugg_compare (1, 2) > 0)
1450 /* ... Fall through ... */
1452 /* Put the best one to allocate in qty_order[0]. */
1453 if (qty_sugg_compare (0, 1) > 0)
1456 /* ... Fall through ... */
1460 /* Nothing to do here. */
1464 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1467 /* Try to put each quantity in a suggested physical register, if it has one.
1468 This may cause registers to be allocated that otherwise wouldn't be, but
1469 this seems acceptable in local allocation (unlike global allocation). */
1470 for (i = 0; i < next_qty; i++)
1473 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1474 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1475 0, 1, qty_birth[q], qty_death[q]);
1477 qty_phys_reg[q] = -1;
1480 /* Order the qtys so we assign them registers in order of
1481 decreasing length of life. Normally call qsort, but if we
1482 have only a very small number of quantities, sort them ourselves. */
1484 for (i = 0; i < next_qty; i++)
1487 #define EXCHANGE(I1, I2) \
1488 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1493 /* Make qty_order[2] be the one to allocate last. */
1494 if (qty_compare (0, 1) > 0)
1496 if (qty_compare (1, 2) > 0)
1499 /* ... Fall through ... */
1501 /* Put the best one to allocate in qty_order[0]. */
1502 if (qty_compare (0, 1) > 0)
1505 /* ... Fall through ... */
1509 /* Nothing to do here. */
1513 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1516 /* Now for each qty that is not a hardware register,
1517 look for a hardware register to put it in.
1518 First try the register class that is cheapest for this qty,
1519 if there is more than one class. */
1521 for (i = 0; i < next_qty; i++)
1524 if (qty_phys_reg[q] < 0)
1526 if (N_REG_CLASSES > 1)
1528 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1529 qty_mode[q], q, 0, 0,
1530 qty_birth[q], qty_death[q]);
1531 if (qty_phys_reg[q] >= 0)
1535 if (qty_alternate_class[q] != NO_REGS)
1536 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1537 qty_mode[q], q, 0, 0,
1538 qty_birth[q], qty_death[q]);
1542 /* Now propagate the register assignments
1543 to the pseudo regs belonging to the qtys. */
1545 for (q = 0; q < next_qty; q++)
1546 if (qty_phys_reg[q] >= 0)
1548 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1549 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1550 if (qty_scratch_rtx[q])
1552 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1554 PUT_CODE (qty_scratch_rtx[q], REG);
1555 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1557 scratch_block[scratch_index] = b;
1558 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1560 /* Must clear the USED field, because it will have been set by
1561 copy_rtx_if_shared, but the leaf_register code expects that
1562 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1563 used bit for REGs, but does for SCRATCHes. */
1564 qty_scratch_rtx[q]->used = 0;
1569 /* Compare two quantities' priority for getting real registers.
1570 We give shorter-lived quantities higher priority.
1571 Quantities with more references are also preferred, as are quantities that
1572 require multiple registers. This is the identical prioritization as
1573 done by global-alloc.
1575 We used to give preference to registers with *longer* lives, but using
1576 the same algorithm in both local- and global-alloc can speed up execution
1577 of some programs by as much as a factor of three! */
1580 qty_compare (q1, q2)
1583 /* Note that the quotient will never be bigger than
1584 the value of floor_log2 times the maximum number of
1585 times a register can occur in one insn (surely less than 100).
1586 Multiplying this by 10000 can't overflow. */
1588 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1])
1589 / (qty_death[q1] - qty_birth[q1]))
1592 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2])
1593 / (qty_death[q2] - qty_birth[q2]))
1599 qty_compare_1 (q1, q2)
1604 /* Note that the quotient will never be bigger than
1605 the value of floor_log2 times the maximum number of
1606 times a register can occur in one insn (surely less than 100).
1607 Multiplying this by 10000 can't overflow. */
1609 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]
1611 / (qty_death[*q1] - qty_birth[*q1]))
1614 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]
1616 / (qty_death[*q2] - qty_birth[*q2]))
1620 if (tem != 0) return tem;
1621 /* If qtys are equally good, sort by qty number,
1622 so that the results of qsort leave nothing to chance. */
1626 /* Compare two quantities' priority for getting real registers. This version
1627 is called for quantities that have suggested hard registers. First priority
1628 goes to quantities that have copy preferences, then to those that have
1629 normal preferences. Within those groups, quantities with the lower
1630 number of preferences have the highest priority. Of those, we use the same
1631 algorithm as above. */
1634 qty_sugg_compare (q1, q2)
1637 register int sugg1 = (qty_phys_num_copy_sugg[q1]
1638 ? qty_phys_num_copy_sugg[q1]
1639 : qty_phys_num_sugg[q1] * FIRST_PSEUDO_REGISTER);
1640 register int sugg2 = (qty_phys_num_copy_sugg[q2]
1641 ? qty_phys_num_copy_sugg[q2]
1642 : qty_phys_num_sugg[q2] * FIRST_PSEUDO_REGISTER);
1643 /* Note that the quotient will never be bigger than
1644 the value of floor_log2 times the maximum number of
1645 times a register can occur in one insn (surely less than 100).
1646 Multiplying this by 10000 can't overflow. */
1648 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1])
1649 / (qty_death[q1] - qty_birth[q1]))
1652 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2])
1653 / (qty_death[q2] - qty_birth[q2]))
1657 return sugg1 - sugg2;
1663 qty_sugg_compare_1 (q1, q2)
1666 register int sugg1 = (qty_phys_num_copy_sugg[*q1]
1667 ? qty_phys_num_copy_sugg[*q1]
1668 : qty_phys_num_sugg[*q1] * FIRST_PSEUDO_REGISTER);
1669 register int sugg2 = (qty_phys_num_copy_sugg[*q2]
1670 ? qty_phys_num_copy_sugg[*q2]
1671 : qty_phys_num_sugg[*q2] * FIRST_PSEUDO_REGISTER);
1673 /* Note that the quotient will never be bigger than
1674 the value of floor_log2 times the maximum number of
1675 times a register can occur in one insn (surely less than 100).
1676 Multiplying this by 10000 can't overflow. */
1678 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]
1680 / (qty_death[*q1] - qty_birth[*q1]))
1683 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]
1685 / (qty_death[*q2] - qty_birth[*q2]))
1689 return sugg1 - sugg2;
1694 /* If qtys are equally good, sort by qty number,
1695 so that the results of qsort leave nothing to chance. */
1699 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1700 Returns 1 if have done so, or 0 if cannot.
1702 Combining registers means marking them as having the same quantity
1703 and adjusting the offsets within the quantity if either of
1706 We don't actually combine a hard reg with a pseudo; instead
1707 we just record the hard reg as the suggestion for the pseudo's quantity.
1708 If we really combined them, we could lose if the pseudo lives
1709 across an insn that clobbers the hard reg (eg, movstr).
1711 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1712 there is no REG_DEAD note on INSN. This occurs during the processing
1713 of REG_NO_CONFLICT blocks.
1715 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1716 SETREG or if the input and output must share a register.
1717 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1719 There are elaborate checks for the validity of combining. */
1723 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1724 rtx usedreg, setreg;
1730 register int ureg, sreg;
1731 register int offset = 0;
1735 /* Determine the numbers and sizes of registers being used. If a subreg
1736 is present that does not change the entire register, don't consider
1737 this a copy insn. */
1739 while (GET_CODE (usedreg) == SUBREG)
1741 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1743 offset += SUBREG_WORD (usedreg);
1744 usedreg = SUBREG_REG (usedreg);
1746 if (GET_CODE (usedreg) != REG)
1748 ureg = REGNO (usedreg);
1749 usize = REG_SIZE (usedreg);
1751 while (GET_CODE (setreg) == SUBREG)
1753 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1755 offset -= SUBREG_WORD (setreg);
1756 setreg = SUBREG_REG (setreg);
1758 if (GET_CODE (setreg) != REG)
1760 sreg = REGNO (setreg);
1761 ssize = REG_SIZE (setreg);
1763 /* If UREG is a pseudo-register that hasn't already been assigned a
1764 quantity number, it means that it is not local to this block or dies
1765 more than once. In either event, we can't do anything with it. */
1766 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1767 /* Do not combine registers unless one fits within the other. */
1768 || (offset > 0 && usize + offset > ssize)
1769 || (offset < 0 && usize + offset < ssize)
1770 /* Do not combine with a smaller already-assigned object
1771 if that smaller object is already combined with something bigger. */
1772 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1773 && usize < qty_size[reg_qty[ureg]])
1774 /* Can't combine if SREG is not a register we can allocate. */
1775 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1776 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1777 These have already been taken care of. This probably wouldn't
1778 combine anyway, but don't take any chances. */
1779 || (ureg >= FIRST_PSEUDO_REGISTER
1780 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1781 /* Don't tie something to itself. In most cases it would make no
1782 difference, but it would screw up if the reg being tied to itself
1783 also dies in this insn. */
1785 /* Don't try to connect two different hardware registers. */
1786 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1787 /* Don't connect two different machine modes if they have different
1788 implications as to which registers may be used. */
1789 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1792 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1793 qty_phys_sugg for the pseudo instead of tying them.
1795 Return "failure" so that the lifespan of UREG is terminated here;
1796 that way the two lifespans will be disjoint and nothing will prevent
1797 the pseudo reg from being given this hard reg. */
1799 if (ureg < FIRST_PSEUDO_REGISTER)
1801 /* Allocate a quantity number so we have a place to put our
1803 if (reg_qty[sreg] == -2)
1804 reg_is_born (setreg, 2 * insn_number);
1806 if (reg_qty[sreg] >= 0)
1809 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1811 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1812 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1814 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1816 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1817 qty_phys_num_sugg[reg_qty[sreg]]++;
1823 /* Similarly for SREG a hard register and UREG a pseudo register. */
1825 if (sreg < FIRST_PSEUDO_REGISTER)
1828 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1830 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1831 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1833 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1835 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1836 qty_phys_num_sugg[reg_qty[ureg]]++;
1841 /* At this point we know that SREG and UREG are both pseudos.
1842 Do nothing if SREG already has a quantity or is a register that we
1844 if (reg_qty[sreg] >= -1
1845 /* If we are not going to let any regs live across calls,
1846 don't tie a call-crossing reg to a non-call-crossing reg. */
1847 || (current_function_has_nonlocal_label
1848 && ((reg_n_calls_crossed[ureg] > 0)
1849 != (reg_n_calls_crossed[sreg] > 0))))
1852 /* We don't already know about SREG, so tie it to UREG
1853 if this is the last use of UREG, provided the classes they want
1856 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1857 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1859 /* Add SREG to UREG's quantity. */
1860 sqty = reg_qty[ureg];
1861 reg_qty[sreg] = sqty;
1862 reg_offset[sreg] = reg_offset[ureg] + offset;
1863 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1864 qty_first_reg[sqty] = sreg;
1866 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1867 update_qty_class (sqty, sreg);
1869 /* Update info about quantity SQTY. */
1870 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1871 qty_n_refs[sqty] += reg_n_refs[sreg];
1876 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1877 reg_offset[i] -= offset;
1879 qty_size[sqty] = ssize;
1880 qty_mode[sqty] = GET_MODE (setreg);
1889 /* Return 1 if the preferred class of REG allows it to be tied
1890 to a quantity or register whose class is CLASS.
1891 True if REG's reg class either contains or is contained in CLASS. */
1894 reg_meets_class_p (reg, class)
1896 enum reg_class class;
1898 register enum reg_class rclass = reg_preferred_class (reg);
1899 return (reg_class_subset_p (rclass, class)
1900 || reg_class_subset_p (class, rclass));
1903 /* Return 1 if the two specified classes have registers in common.
1904 If CALL_SAVED, then consider only call-saved registers. */
1907 reg_classes_overlap_p (c1, c2, call_saved)
1908 register enum reg_class c1;
1909 register enum reg_class c2;
1915 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1916 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1918 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1919 if (TEST_HARD_REG_BIT (c, i)
1920 && (! call_saved || ! call_used_regs[i]))
1926 /* Update the class of QTY assuming that REG is being tied to it. */
1929 update_qty_class (qty, reg)
1933 enum reg_class rclass = reg_preferred_class (reg);
1934 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1935 qty_min_class[qty] = rclass;
1937 rclass = reg_alternate_class (reg);
1938 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1939 qty_alternate_class[qty] = rclass;
1941 if (reg_changes_size[reg])
1942 qty_changes_size[qty] = 1;
1945 /* Handle something which alters the value of an rtx REG.
1947 REG is whatever is set or clobbered. SETTER is the rtx that
1948 is modifying the register.
1950 If it is not really a register, we do nothing.
1951 The file-global variables `this_insn' and `this_insn_number'
1952 carry info from `block_alloc'. */
1955 reg_is_set (reg, setter)
1959 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1960 a hard register. These may actually not exist any more. */
1962 if (GET_CODE (reg) != SUBREG
1963 && GET_CODE (reg) != REG)
1966 /* Mark this register as being born. If it is used in a CLOBBER, mark
1967 it as being born halfway between the previous insn and this insn so that
1968 it conflicts with our inputs but not the outputs of the previous insn. */
1970 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1973 /* Handle beginning of the life of register REG.
1974 BIRTH is the index at which this is happening. */
1977 reg_is_born (reg, birth)
1983 if (GET_CODE (reg) == SUBREG)
1984 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1986 regno = REGNO (reg);
1988 if (regno < FIRST_PSEUDO_REGISTER)
1990 mark_life (regno, GET_MODE (reg), 1);
1992 /* If the register was to have been born earlier that the present
1993 insn, mark it as live where it is actually born. */
1994 if (birth < 2 * this_insn_number)
1995 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1999 if (reg_qty[regno] == -2)
2000 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2002 /* If this register has a quantity number, show that it isn't dead. */
2003 if (reg_qty[regno] >= 0)
2004 qty_death[reg_qty[regno]] = -1;
2008 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2009 REG is an output that is dying (i.e., it is never used), otherwise it
2010 is an input (the normal case).
2011 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2014 wipe_dead_reg (reg, output_p)
2018 register int regno = REGNO (reg);
2020 /* If this insn has multiple results,
2021 and the dead reg is used in one of the results,
2022 extend its life to after this insn,
2023 so it won't get allocated together with any other result of this insn. */
2024 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2025 && !single_set (this_insn))
2028 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2030 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2031 if (GET_CODE (set) == SET
2032 && GET_CODE (SET_DEST (set)) != REG
2033 && !rtx_equal_p (reg, SET_DEST (set))
2034 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2039 /* If this register is used in an auto-increment address, then extend its
2040 life to after this insn, so that it won't get allocated together with
2041 the result of this insn. */
2042 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2045 if (regno < FIRST_PSEUDO_REGISTER)
2047 mark_life (regno, GET_MODE (reg), 0);
2049 /* If a hard register is dying as an output, mark it as in use at
2050 the beginning of this insn (the above statement would cause this
2053 post_mark_life (regno, GET_MODE (reg), 1,
2054 2 * this_insn_number, 2 * this_insn_number+ 1);
2057 else if (reg_qty[regno] >= 0)
2058 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2061 /* Find a block of SIZE words of hard regs in reg_class CLASS
2062 that can hold something of machine-mode MODE
2063 (but actually we test only the first of the block for holding MODE)
2064 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2065 and return the number of the first of them.
2066 Return -1 if such a block cannot be found.
2067 If QTY crosses calls, insist on a register preserved by calls,
2068 unless ACCEPT_CALL_CLOBBERED is nonzero.
2070 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2071 register is available. If not, return -1. */
2074 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2075 born_index, dead_index)
2076 enum reg_class class;
2077 enum machine_mode mode;
2079 int accept_call_clobbered;
2080 int just_try_suggested;
2081 int born_index, dead_index;
2083 register int i, ins;
2085 register /* Declare it register if it's a scalar. */
2087 HARD_REG_SET used, first_used;
2088 #ifdef ELIMINABLE_REGS
2089 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2092 /* Validate our parameters. */
2093 if (born_index < 0 || born_index > dead_index)
2096 /* Don't let a pseudo live in a reg across a function call
2097 if we might get a nonlocal goto. */
2098 if (current_function_has_nonlocal_label
2099 && qty_n_calls_crossed[qty] > 0)
2102 if (accept_call_clobbered)
2103 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2104 else if (qty_n_calls_crossed[qty] == 0)
2105 COPY_HARD_REG_SET (used, fixed_reg_set);
2107 COPY_HARD_REG_SET (used, call_used_reg_set);
2109 for (ins = born_index; ins < dead_index; ins++)
2110 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2112 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2114 /* Don't use the frame pointer reg in local-alloc even if
2115 we may omit the frame pointer, because if we do that and then we
2116 need a frame pointer, reload won't know how to move the pseudo
2117 to another hard reg. It can move only regs made by global-alloc.
2119 This is true of any register that can be eliminated. */
2120 #ifdef ELIMINABLE_REGS
2121 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2122 SET_HARD_REG_BIT (used, eliminables[i].from);
2123 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2124 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2125 that it might be eliminated into. */
2126 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2129 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2132 #ifdef CLASS_CANNOT_CHANGE_SIZE
2133 if (qty_changes_size[qty])
2134 IOR_HARD_REG_SET (used,
2135 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2138 /* Normally, the registers that can be used for the first register in
2139 a multi-register quantity are the same as those that can be used for
2140 subsequent registers. However, if just trying suggested registers,
2141 restrict our consideration to them. If there are copy-suggested
2142 register, try them. Otherwise, try the arithmetic-suggested
2144 COPY_HARD_REG_SET (first_used, used);
2146 if (just_try_suggested)
2148 if (qty_phys_num_copy_sugg[qty] != 0)
2149 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2151 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2154 /* If all registers are excluded, we can't do anything. */
2155 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2157 /* If at least one would be suitable, test each hard reg. */
2159 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2161 #ifdef REG_ALLOC_ORDER
2162 int regno = reg_alloc_order[i];
2166 if (! TEST_HARD_REG_BIT (first_used, regno)
2167 && HARD_REGNO_MODE_OK (regno, mode))
2170 register int size1 = HARD_REGNO_NREGS (regno, mode);
2171 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2174 /* Mark that this register is in use between its birth and death
2176 post_mark_life (regno, mode, 1, born_index, dead_index);
2179 #ifndef REG_ALLOC_ORDER
2180 i += j; /* Skip starting points we know will lose */
2187 /* If we are just trying suggested register, we have just tried copy-
2188 suggested registers, and there are arithmetic-suggested registers,
2191 /* If it would be profitable to allocate a call-clobbered register
2192 and save and restore it around calls, do that. */
2193 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2194 && qty_phys_num_sugg[qty] != 0)
2196 /* Don't try the copy-suggested regs again. */
2197 qty_phys_num_copy_sugg[qty] = 0;
2198 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2199 born_index, dead_index);
2202 /* We need not check to see if the current function has nonlocal
2203 labels because we don't put any pseudos that are live over calls in
2204 registers in that case. */
2206 if (! accept_call_clobbered
2207 && flag_caller_saves
2208 && ! just_try_suggested
2209 && qty_n_calls_crossed[qty] != 0
2210 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2212 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2214 caller_save_needed = 1;
2220 /* Mark that REGNO with machine-mode MODE is live starting from the current
2221 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2225 mark_life (regno, mode, life)
2227 enum machine_mode mode;
2230 register int j = HARD_REGNO_NREGS (regno, mode);
2233 SET_HARD_REG_BIT (regs_live, regno + j);
2236 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2239 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2240 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2241 to insn number DEATH (exclusive). */
2244 post_mark_life (regno, mode, life, birth, death)
2246 enum machine_mode mode;
2247 int life, birth, death;
2249 register int j = HARD_REGNO_NREGS (regno, mode);
2251 register /* Declare it register if it's a scalar. */
2253 HARD_REG_SET this_reg;
2255 CLEAR_HARD_REG_SET (this_reg);
2257 SET_HARD_REG_BIT (this_reg, regno + j);
2260 while (birth < death)
2262 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2266 while (birth < death)
2268 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2273 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2274 is the register being clobbered, and R1 is a register being used in
2275 the equivalent expression.
2277 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2278 in which it is used, return 1.
2280 Otherwise, return 0. */
2283 no_conflict_p (insn, r0, r1)
2287 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2290 /* If R1 is a hard register, return 0 since we handle this case
2291 when we scan the insns that actually use it. */
2294 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2295 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2296 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2299 last = XEXP (note, 0);
2301 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2302 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2304 if (find_reg_note (p, REG_DEAD, r1))
2307 if (reg_mentioned_p (r1, PATTERN (p))
2308 && ! find_reg_note (p, REG_NO_CONFLICT, r1))
2315 #ifdef REGISTER_CONSTRAINTS
2317 /* Return the number of alternatives for which the constraint string P
2318 indicates that the operand must be equal to operand 0 and that no register
2327 int reg_allowed = 0;
2328 int num_matching_alts = 0;
2333 case '=': case '+': case '?':
2334 case '#': case '&': case '!':
2336 case '1': case '2': case '3': case '4':
2337 case 'm': case '<': case '>': case 'V': case 'o':
2338 case 'E': case 'F': case 'G': case 'H':
2339 case 's': case 'i': case 'n':
2340 case 'I': case 'J': case 'K': case 'L':
2341 case 'M': case 'N': case 'O': case 'P':
2342 #ifdef EXTRA_CONSTRAINT
2343 case 'Q': case 'R': case 'S': case 'T': case 'U':
2346 /* These don't say anything we care about. */
2350 if (found_zero && ! reg_allowed)
2351 num_matching_alts++;
2353 found_zero = reg_allowed = 0;
2367 if (found_zero && ! reg_allowed)
2368 num_matching_alts++;
2370 return num_matching_alts;
2372 #endif /* REGISTER_CONSTRAINTS */
2375 dump_local_alloc (file)
2379 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2380 if (reg_renumber[i] != -1)
2381 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);