1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int contains_replace_regs PROTO((rtx, char *));
250 static int memref_referenced_p PROTO((rtx, rtx));
251 static int memref_used_between_p PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
253 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
254 static void update_equiv_regs PROTO((void));
255 static void block_alloc PROTO((int));
256 static int qty_sugg_compare PROTO((int, int));
257 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
258 static int qty_compare PROTO((int, int));
259 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
260 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
261 static int reg_meets_class_p PROTO((int, enum reg_class));
262 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
264 static void update_qty_class PROTO((int, int));
265 static void reg_is_set PROTO((rtx, rtx));
266 static void reg_is_born PROTO((rtx, int));
267 static void wipe_dead_reg PROTO((rtx, int));
268 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
269 int, int, int, int, int));
270 static void mark_life PROTO((int, enum machine_mode, int));
271 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
272 static int no_conflict_p PROTO((rtx, rtx, rtx));
273 static int requires_inout PROTO((char *));
275 /* Allocate a new quantity (new within current basic block)
276 for register number REGNO which is born at index BIRTH
277 within the block. MODE and SIZE are info on reg REGNO. */
280 alloc_qty (regno, mode, size, birth)
282 enum machine_mode mode;
285 register int qty = next_qty++;
287 reg_qty[regno] = qty;
288 reg_offset[regno] = 0;
289 reg_next_in_qty[regno] = -1;
291 qty_first_reg[qty] = regno;
292 qty_size[qty] = size;
293 qty_mode[qty] = mode;
294 qty_birth[qty] = birth;
295 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
296 qty_min_class[qty] = reg_preferred_class (regno);
297 qty_alternate_class[qty] = reg_alternate_class (regno);
298 qty_n_refs[qty] = REG_N_REFS (regno);
299 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
302 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
303 used as operand N in INSN. We assume here that the SCRATCH is used in
307 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
311 int insn_code_num, insn_number;
314 enum reg_class class;
318 #ifdef REGISTER_CONSTRAINTS
319 /* If we haven't yet computed which alternative will be used, do so now.
320 Then set P to the constraints for that alternative. */
321 if (which_alternative == -1)
322 if (! constrain_operands (insn_code_num, 0))
325 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
326 *p && i < which_alternative; p++)
330 /* Compute the class required for this SCRATCH. If we don't need a
331 register, the class will remain NO_REGS. If we guessed the alternative
332 number incorrectly, reload will fix things up for us. */
335 while ((c = *p++) != '\0' && c != ',')
338 case '=': case '+': case '?':
339 case '#': case '&': case '!':
341 case '0': case '1': case '2': case '3': case '4':
342 case 'm': case '<': case '>': case 'V': case 'o':
343 case 'E': case 'F': case 'G': case 'H':
344 case 's': case 'i': case 'n':
345 case 'I': case 'J': case 'K': case 'L':
346 case 'M': case 'N': case 'O': case 'P':
347 #ifdef EXTRA_CONSTRAINT
348 case 'Q': case 'R': case 'S': case 'T': case 'U':
351 /* These don't say anything we care about. */
355 /* We don't need to allocate this SCRATCH. */
359 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
364 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
368 if (class == NO_REGS)
371 #else /* REGISTER_CONSTRAINTS */
373 class = GENERAL_REGS;
379 qty_first_reg[qty] = -1;
380 qty_scratch_rtx[qty] = scratch;
381 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
382 qty_mode[qty] = GET_MODE (scratch);
383 qty_birth[qty] = 2 * insn_number - 1;
384 qty_death[qty] = 2 * insn_number + 1;
385 qty_n_calls_crossed[qty] = 0;
386 qty_min_class[qty] = class;
387 qty_alternate_class[qty] = NO_REGS;
389 qty_changes_size[qty] = 0;
392 /* Main entry point of this file. */
400 /* Leaf functions and non-leaf functions have different needs.
401 If defined, let the machine say what kind of ordering we
403 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
404 ORDER_REGS_FOR_LOCAL_ALLOC;
407 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
409 update_equiv_regs ();
411 /* This sets the maximum number of quantities we can have. Quantity
412 numbers start at zero and we can have one for each pseudo plus the
413 number of SCRATCHes in the largest block, in the worst case. */
414 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
416 /* Allocate vectors of temporary data.
417 See the declarations of these variables, above,
418 for what they mean. */
420 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
421 Instead of allocating this much memory from now until the end of
422 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
423 reload will allocate them. */
425 scratch_list_length = max_qty;
426 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
427 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
428 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
429 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
432 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
434 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
435 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
436 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
437 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
438 qty_birth = (int *) alloca (max_qty * sizeof (int));
439 qty_death = (int *) alloca (max_qty * sizeof (int));
440 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
441 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
442 qty_size = (int *) alloca (max_qty * sizeof (int));
444 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
445 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
447 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
450 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
451 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
453 reg_qty = (int *) alloca (max_regno * sizeof (int));
454 reg_offset = (char *) alloca (max_regno * sizeof (char));
455 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
457 /* Allocate the reg_renumber array */
458 allocate_reg_info (max_regno, FALSE, TRUE);
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
608 contains_replace_regs (x, reg_equiv_replace)
610 char *reg_equiv_replace;
614 enum rtx_code code = GET_CODE (x);
630 return reg_equiv_replace[REGNO (x)];
636 fmt = GET_RTX_FORMAT (code);
637 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
641 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
645 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
646 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
654 /* TRUE if X references a memory location that would be affected by a store
658 memref_referenced_p (memref, x)
664 enum rtx_code code = GET_CODE (x);
680 return (reg_equiv_replacement[REGNO (x)]
681 && memref_referenced_p (memref,
682 reg_equiv_replacement[REGNO (x)]));
685 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
690 /* If we are setting a MEM, it doesn't count (its address does), but any
691 other SET_DEST that has a MEM in it is referencing the MEM. */
692 if (GET_CODE (SET_DEST (x)) == MEM)
694 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
697 else if (memref_referenced_p (memref, SET_DEST (x)))
700 return memref_referenced_p (memref, SET_SRC (x));
706 fmt = GET_RTX_FORMAT (code);
707 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
711 if (memref_referenced_p (memref, XEXP (x, i)))
715 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
716 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
724 /* TRUE if some insn in the range (START, END] references a memory location
725 that would be affected by a store to MEMREF. */
728 memref_used_between_p (memref, start, end)
735 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
736 insn = NEXT_INSN (insn))
737 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
738 && memref_referenced_p (memref, PATTERN (insn)))
744 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
747 Search forward to see if SRC dies before either it or DEST is modified,
748 but don't scan past the end of a basic block. If so, we can replace SRC
749 with DEST and let SRC die in INSN.
751 This will reduce the number of registers live in that range and may enable
752 DEST to be tied to SRC, thus often saving one register in addition to a
753 register-register copy. */
756 optimize_reg_copy_1 (insn, dest, src)
764 int sregno = REGNO (src);
765 int dregno = REGNO (dest);
767 /* We don't want to mess with hard regs if register classes are small. */
769 || (SMALL_REGISTER_CLASSES
770 && (sregno < FIRST_PSEUDO_REGISTER
771 || dregno < FIRST_PSEUDO_REGISTER))
772 /* We don't see all updates to SP if they are in an auto-inc memory
773 reference, so we must disallow this optimization on them. */
774 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
777 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
779 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
780 || (GET_CODE (p) == NOTE
781 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
782 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
785 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
788 if (reg_set_p (src, p) || reg_set_p (dest, p)
789 /* Don't change a USE of a register. */
790 || (GET_CODE (PATTERN (p)) == USE
791 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
794 /* See if all of SRC dies in P. This test is slightly more
795 conservative than it needs to be. */
796 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
797 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
805 /* We can do the optimization. Scan forward from INSN again,
806 replacing regs as we go. Set FAILED if a replacement can't
807 be done. In that case, we can't move the death note for SRC.
808 This should be rare. */
810 /* Set to stop at next insn. */
811 for (q = next_real_insn (insn);
812 q != next_real_insn (p);
813 q = next_real_insn (q))
815 if (reg_overlap_mentioned_p (src, PATTERN (q)))
817 /* If SRC is a hard register, we might miss some
818 overlapping registers with validate_replace_rtx,
819 so we would have to undo it. We can't if DEST is
820 present in the insn, so fail in that combination
822 if (sregno < FIRST_PSEUDO_REGISTER
823 && reg_mentioned_p (dest, PATTERN (q)))
826 /* Replace all uses and make sure that the register
827 isn't still present. */
828 else if (validate_replace_rtx (src, dest, q)
829 && (sregno >= FIRST_PSEUDO_REGISTER
830 || ! reg_overlap_mentioned_p (src,
833 /* We assume that a register is used exactly once per
834 insn in the updates below. If this is not correct,
835 no great harm is done. */
836 if (sregno >= FIRST_PSEUDO_REGISTER)
837 REG_N_REFS (sregno) -= loop_depth;
838 if (dregno >= FIRST_PSEUDO_REGISTER)
839 REG_N_REFS (dregno) += loop_depth;
843 validate_replace_rtx (dest, src, q);
848 /* Count the insns and CALL_INSNs passed. If we passed the
849 death note of DEST, show increased live length. */
854 /* If the insn in which SRC dies is a CALL_INSN, don't count it
855 as a call that has been crossed. Otherwise, count it. */
856 if (q != p && GET_CODE (q) == CALL_INSN)
863 /* If DEST dies here, remove the death note and save it for
864 later. Make sure ALL of DEST dies here; again, this is
865 overly conservative. */
867 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
868 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
869 remove_note (q, dest_death);
874 if (sregno >= FIRST_PSEUDO_REGISTER)
876 if (REG_LIVE_LENGTH (sregno) >= 0)
878 REG_LIVE_LENGTH (sregno) -= length;
879 /* reg_live_length is only an approximation after
880 combine if sched is not run, so make sure that we
881 still have a reasonable value. */
882 if (REG_LIVE_LENGTH (sregno) < 2)
883 REG_LIVE_LENGTH (sregno) = 2;
886 REG_N_CALLS_CROSSED (sregno) -= n_calls;
889 if (dregno >= FIRST_PSEUDO_REGISTER)
891 if (REG_LIVE_LENGTH (dregno) >= 0)
892 REG_LIVE_LENGTH (dregno) += d_length;
894 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
897 /* Move death note of SRC from P to INSN. */
898 remove_note (p, note);
899 XEXP (note, 1) = REG_NOTES (insn);
900 REG_NOTES (insn) = note;
903 /* Put death note of DEST on P if we saw it die. */
906 XEXP (dest_death, 1) = REG_NOTES (p);
907 REG_NOTES (p) = dest_death;
913 /* If SRC is a hard register which is set or killed in some other
914 way, we can't do this optimization. */
915 else if (sregno < FIRST_PSEUDO_REGISTER
916 && dead_or_set_p (p, src))
921 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
922 a sequence of insns that modify DEST followed by an insn that sets
923 SRC to DEST in which DEST dies, with no prior modification of DEST.
924 (There is no need to check if the insns in between actually modify
925 DEST. We should not have cases where DEST is not modified, but
926 the optimization is safe if no such modification is detected.)
927 In that case, we can replace all uses of DEST, starting with INSN and
928 ending with the set of SRC to DEST, with SRC. We do not do this
929 optimization if a CALL_INSN is crossed unless SRC already crosses a
930 call or if DEST dies before the copy back to SRC.
932 It is assumed that DEST and SRC are pseudos; it is too complicated to do
933 this for hard registers since the substitutions we may make might fail. */
936 optimize_reg_copy_2 (insn, dest, src)
943 int sregno = REGNO (src);
944 int dregno = REGNO (dest);
946 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
948 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
949 || (GET_CODE (p) == NOTE
950 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
951 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
954 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
957 set = single_set (p);
958 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
959 && find_reg_note (p, REG_DEAD, dest))
961 /* We can do the optimization. Scan forward from INSN again,
962 replacing regs as we go. */
964 /* Set to stop at next insn. */
965 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
966 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
968 if (reg_mentioned_p (dest, PATTERN (q)))
970 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
972 /* We assume that a register is used exactly once per
973 insn in the updates below. If this is not correct,
974 no great harm is done. */
975 REG_N_REFS (dregno) -= loop_depth;
976 REG_N_REFS (sregno) += loop_depth;
980 if (GET_CODE (q) == CALL_INSN)
982 REG_N_CALLS_CROSSED (dregno)--;
983 REG_N_CALLS_CROSSED (sregno)++;
987 remove_note (p, find_reg_note (p, REG_DEAD, dest));
988 REG_N_DEATHS (dregno)--;
989 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
990 REG_N_DEATHS (sregno)--;
994 if (reg_set_p (src, p)
995 || find_reg_note (p, REG_DEAD, dest)
996 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0))
1001 /* Find registers that are equivalent to a single value throughout the
1002 compilation (either because they can be referenced in memory or are set once
1003 from a single constant). Lower their priority for a register.
1005 If such a register is only referenced once, try substituting its value
1006 into the using insn. If it succeeds, we can eliminate the register
1010 update_equiv_regs ()
1012 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
1013 /* Set when an attempt should be made to replace a register with the
1014 associated reg_equiv_replacement entry at the end of this function. */
1015 char *reg_equiv_replace
1016 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
1020 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
1022 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
1023 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
1024 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
1026 init_alias_analysis ();
1030 /* Scan the insns and find which registers have equivalences. Do this
1031 in a separate scan of the insns because (due to -fcse-follow-jumps)
1032 a register can be set below its use. */
1033 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1036 rtx set = single_set (insn);
1040 if (GET_CODE (insn) == NOTE)
1042 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1044 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1048 /* If this insn contains more (or less) than a single SET, ignore it. */
1052 dest = SET_DEST (set);
1053 src = SET_SRC (set);
1055 /* If this sets a MEM to the contents of a REG that is only used
1056 in a single basic block, see if the register is always equivalent
1057 to that memory location and if moving the store from INSN to the
1058 insn that set REG is safe. If so, put a REG_EQUIV note on the
1061 Don't add a REG_EQUIV note if the insn already has one. The existing
1062 REG_EQUIV is likely more useful than the one we are adding.
1064 If one of the regs in the address is marked as reg_equiv_replace,
1065 then we can't add this REG_EQUIV note. The reg_equiv_replace
1066 optimization may move the set of this register immediately before
1067 insn, which puts it after reg_equiv_init_insn[regno], and hence
1068 the mention in the REG_EQUIV note would be to an uninitialized
1071 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
1072 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
1073 && REG_BASIC_BLOCK (regno) >= 0
1074 && reg_equiv_init_insn[regno] != 0
1075 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
1076 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
1077 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
1079 && ! memref_used_between_p (SET_DEST (set),
1080 reg_equiv_init_insn[regno], insn))
1081 REG_NOTES (reg_equiv_init_insn[regno])
1082 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1083 REG_NOTES (reg_equiv_init_insn[regno]));
1085 /* If this is a register-register copy where SRC is not dead, see if we
1087 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1088 && GET_CODE (SET_SRC (set)) == REG
1089 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1090 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1092 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1093 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1094 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1095 && GET_CODE (SET_SRC (set)) == REG
1096 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1097 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1098 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1100 /* Otherwise, we only handle the case of a pseudo register being set
1101 once and only if neither the source nor the destination are
1102 in a register class that's likely to be spilled. */
1103 if (GET_CODE (dest) != REG
1104 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1105 || REG_N_SETS (regno) != 1
1106 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
1107 || (GET_CODE (src) == REG
1108 && REGNO (src) >= FIRST_PSEUDO_REGISTER
1109 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
1112 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1114 #ifdef DONT_RECORD_EQUIVALENCE
1115 /* Allow the target to reject promotions of some REG_EQUAL notes to
1118 In some cases this can improve register allocation if the existence
1119 of the REG_EQUIV note is likely to increase the lifetime of a register
1120 that is likely to be spilled.
1122 It may also be necessary if the target can't handle certain constant
1123 expressions appearing randomly in insns, but for whatever reason
1124 those expressions must be considered legitimate constant expressions
1125 to prevent them from being forced into memory. */
1126 if (note && DONT_RECORD_EQUIVALENCE (note))
1130 /* Record this insn as initializing this register. */
1131 reg_equiv_init_insn[regno] = insn;
1133 /* If this register is known to be equal to a constant, record that
1134 it is always equivalent to the constant. */
1135 if (note && CONSTANT_P (XEXP (note, 0)))
1136 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1138 /* If this insn introduces a "constant" register, decrease the priority
1139 of that register. Record this insn if the register is only used once
1140 more and the equivalence value is the same as our source.
1142 The latter condition is checked for two reasons: First, it is an
1143 indication that it may be more efficient to actually emit the insn
1144 as written (if no registers are available, reload will substitute
1145 the equivalence). Secondly, it avoids problems with any registers
1146 dying in this insn whose death notes would be missed.
1148 If we don't have a REG_EQUIV note, see if this insn is loading
1149 a register used only in one basic block from a MEM. If so, and the
1150 MEM remains unchanged for the life of the register, add a REG_EQUIV
1153 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1155 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
1156 && GET_CODE (SET_SRC (set)) == MEM
1157 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1158 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1163 int regno = REGNO (dest);
1165 reg_equiv_replacement[regno] = XEXP (note, 0);
1167 /* Don't mess with things live during setjmp. */
1168 if (REG_LIVE_LENGTH (regno) >= 0)
1170 /* Note that the statement below does not affect the priority
1172 REG_LIVE_LENGTH (regno) *= 2;
1175 /* If the register is referenced exactly twice, meaning it is
1176 set once and used once, indicate that the reference may be
1177 replaced by the equivalence we computed above. If the
1178 register is only used in one basic block, this can't succeed
1179 or combine would have done it.
1181 It would be nice to use "loop_depth * 2" in the compare
1182 below. Unfortunately, LOOP_DEPTH need not be constant within
1183 a basic block so this would be too complicated.
1185 This case normally occurs when a parameter is read from
1186 memory and then used exactly once, not in a loop. */
1188 if (REG_N_REFS (regno) == 2
1189 && REG_BASIC_BLOCK (regno) < 0
1190 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1191 reg_equiv_replace[regno] = 1;
1196 /* Now scan all regs killed in an insn to see if any of them are
1197 registers only used that once. If so, see if we can replace the
1198 reference with the equivalent from. If we can, delete the
1199 initializing reference and this register will go away. If we
1200 can't replace the reference, and the instruction is not in a
1201 loop, then move the register initialization just before the use,
1202 so that they are in the same basic block. */
1205 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1209 /* Keep track of which basic block we are in. */
1210 if (block + 1 < n_basic_blocks
1211 && basic_block_head[block + 1] == insn)
1214 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1216 if (GET_CODE (insn) == NOTE)
1218 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1220 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1231 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1233 if (REG_NOTE_KIND (link) == REG_DEAD
1234 /* Make sure this insn still refers to the register. */
1235 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1237 int regno = REGNO (XEXP (link, 0));
1240 if (! reg_equiv_replace[regno])
1243 equiv_insn = reg_equiv_init_insn[regno];
1245 if (validate_replace_rtx (regno_reg_rtx[regno],
1246 reg_equiv_replacement[regno], insn))
1248 remove_death (regno, insn);
1249 REG_N_REFS (regno) = 0;
1250 PUT_CODE (equiv_insn, NOTE);
1251 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1252 NOTE_SOURCE_FILE (equiv_insn) = 0;
1254 /* If we aren't in a loop, and there are no calls in
1255 INSN or in the initialization of the register, then
1256 move the initialization of the register to just
1257 before INSN. Update the flow information. */
1259 && GET_CODE (equiv_insn) == INSN
1260 && GET_CODE (insn) == INSN
1261 && REG_BASIC_BLOCK (regno) < 0)
1265 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
1266 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
1268 PUT_CODE (equiv_insn, NOTE);
1269 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1270 NOTE_SOURCE_FILE (equiv_insn) = 0;
1271 REG_NOTES (equiv_insn) = 0;
1274 REG_BASIC_BLOCK (regno) = 0;
1276 REG_BASIC_BLOCK (regno) = block;
1277 REG_N_CALLS_CROSSED (regno) = 0;
1278 REG_LIVE_LENGTH (regno) = 2;
1280 if (block >= 0 && insn == basic_block_head[block])
1281 basic_block_head[block] = PREV_INSN (insn);
1283 for (l = 0; l < n_basic_blocks; l++)
1284 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1291 /* Allocate hard regs to the pseudo regs used only within block number B.
1292 Only the pseudos that die but once can be handled. */
1301 int insn_number = 0;
1303 int max_uid = get_max_uid ();
1305 int no_conflict_combined_regno = -1;
1306 /* Counter to prevent allocating more SCRATCHes than can be stored
1308 int scratches_allocated = scratch_index;
1310 /* Count the instructions in the basic block. */
1312 insn = basic_block_end[b];
1315 if (GET_CODE (insn) != NOTE)
1316 if (++insn_count > max_uid)
1318 if (insn == basic_block_head[b])
1320 insn = PREV_INSN (insn);
1323 /* +2 to leave room for a post_mark_life at the last insn and for
1324 the birth of a CLOBBER in the first insn. */
1325 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1326 * sizeof (HARD_REG_SET));
1327 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1329 /* Initialize table of hardware registers currently live. */
1331 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1333 /* This loop scans the instructions of the basic block
1334 and assigns quantities to registers.
1335 It computes which registers to tie. */
1337 insn = basic_block_head[b];
1340 register rtx body = PATTERN (insn);
1342 if (GET_CODE (insn) != NOTE)
1345 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1347 register rtx link, set;
1348 register int win = 0;
1349 register rtx r0, r1;
1350 int combined_regno = -1;
1352 int insn_code_number = recog_memoized (insn);
1354 this_insn_number = insn_number;
1357 if (insn_code_number >= 0)
1358 insn_extract (insn);
1359 which_alternative = -1;
1361 /* Is this insn suitable for tying two registers?
1362 If so, try doing that.
1363 Suitable insns are those with at least two operands and where
1364 operand 0 is an output that is a register that is not
1367 We can tie operand 0 with some operand that dies in this insn.
1368 First look for operands that are required to be in the same
1369 register as operand 0. If we find such, only try tying that
1370 operand or one that can be put into that operand if the
1371 operation is commutative. If we don't find an operand
1372 that is required to be in the same register as operand 0,
1373 we can tie with any operand.
1375 Subregs in place of regs are also ok.
1377 If tying is done, WIN is set nonzero. */
1379 if (insn_code_number >= 0
1380 #ifdef REGISTER_CONSTRAINTS
1381 && insn_n_operands[insn_code_number] > 1
1382 && insn_operand_constraint[insn_code_number][0][0] == '='
1383 && insn_operand_constraint[insn_code_number][0][1] != '&'
1385 && GET_CODE (PATTERN (insn)) == SET
1386 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1390 #ifdef REGISTER_CONSTRAINTS
1391 /* If non-negative, is an operand that must match operand 0. */
1392 int must_match_0 = -1;
1393 /* Counts number of alternatives that require a match with
1395 int n_matching_alts = 0;
1397 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1399 char *p = insn_operand_constraint[insn_code_number][i];
1400 int this_match = (requires_inout (p));
1402 n_matching_alts += this_match;
1403 if (this_match == insn_n_alternatives[insn_code_number])
1408 r0 = recog_operand[0];
1409 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1411 #ifdef REGISTER_CONSTRAINTS
1412 /* Skip this operand if we found an operand that
1413 must match operand 0 and this operand isn't it
1414 and can't be made to be it by commutativity. */
1416 if (must_match_0 >= 0 && i != must_match_0
1417 && ! (i == must_match_0 + 1
1418 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1419 && ! (i == must_match_0 - 1
1420 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1423 /* Likewise if each alternative has some operand that
1424 must match operand zero. In that case, skip any
1425 operand that doesn't list operand 0 since we know that
1426 the operand always conflicts with operand 0. We
1427 ignore commutatity in this case to keep things simple. */
1428 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1429 && (0 == requires_inout
1430 (insn_operand_constraint[insn_code_number][i])))
1434 r1 = recog_operand[i];
1436 /* If the operand is an address, find a register in it.
1437 There may be more than one register, but we only try one
1440 #ifdef REGISTER_CONSTRAINTS
1441 insn_operand_constraint[insn_code_number][i][0] == 'p'
1443 insn_operand_address_p[insn_code_number][i]
1446 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1449 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1451 /* We have two priorities for hard register preferences.
1452 If we have a move insn or an insn whose first input
1453 can only be in the same register as the output, give
1454 priority to an equivalence found from that insn. */
1456 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1457 #ifdef REGISTER_CONSTRAINTS
1458 || (r1 == recog_operand[i] && must_match_0 >= 0)
1462 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1463 win = combine_regs (r1, r0, may_save_copy,
1464 insn_number, insn, 0);
1471 /* Recognize an insn sequence with an ultimate result
1472 which can safely overlap one of the inputs.
1473 The sequence begins with a CLOBBER of its result,
1474 and ends with an insn that copies the result to itself
1475 and has a REG_EQUAL note for an equivalent formula.
1476 That note indicates what the inputs are.
1477 The result and the input can overlap if each insn in
1478 the sequence either doesn't mention the input
1479 or has a REG_NO_CONFLICT note to inhibit the conflict.
1481 We do the combining test at the CLOBBER so that the
1482 destination register won't have had a quantity number
1483 assigned, since that would prevent combining. */
1485 if (GET_CODE (PATTERN (insn)) == CLOBBER
1486 && (r0 = XEXP (PATTERN (insn), 0),
1487 GET_CODE (r0) == REG)
1488 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1489 && XEXP (link, 0) != 0
1490 && GET_CODE (XEXP (link, 0)) == INSN
1491 && (set = single_set (XEXP (link, 0))) != 0
1492 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1493 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1496 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1497 /* Check that we have such a sequence. */
1498 && no_conflict_p (insn, r0, r1))
1499 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1500 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1501 && (r1 = XEXP (XEXP (note, 0), 0),
1502 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1503 && no_conflict_p (insn, r0, r1))
1504 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1506 /* Here we care if the operation to be computed is
1508 else if ((GET_CODE (XEXP (note, 0)) == EQ
1509 || GET_CODE (XEXP (note, 0)) == NE
1510 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1511 && (r1 = XEXP (XEXP (note, 0), 1),
1512 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1513 && no_conflict_p (insn, r0, r1))
1514 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1516 /* If we did combine something, show the register number
1517 in question so that we know to ignore its death. */
1519 no_conflict_combined_regno = REGNO (r1);
1522 /* If registers were just tied, set COMBINED_REGNO
1523 to the number of the register used in this insn
1524 that was tied to the register set in this insn.
1525 This register's qty should not be "killed". */
1529 while (GET_CODE (r1) == SUBREG)
1530 r1 = SUBREG_REG (r1);
1531 combined_regno = REGNO (r1);
1534 /* Mark the death of everything that dies in this instruction,
1535 except for anything that was just combined. */
1537 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1538 if (REG_NOTE_KIND (link) == REG_DEAD
1539 && GET_CODE (XEXP (link, 0)) == REG
1540 && combined_regno != REGNO (XEXP (link, 0))
1541 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1542 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1543 wipe_dead_reg (XEXP (link, 0), 0);
1545 /* Allocate qty numbers for all registers local to this block
1546 that are born (set) in this instruction.
1547 A pseudo that already has a qty is not changed. */
1549 note_stores (PATTERN (insn), reg_is_set);
1551 /* If anything is set in this insn and then unused, mark it as dying
1552 after this insn, so it will conflict with our outputs. This
1553 can't match with something that combined, and it doesn't matter
1554 if it did. Do this after the calls to reg_is_set since these
1555 die after, not during, the current insn. */
1557 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1558 if (REG_NOTE_KIND (link) == REG_UNUSED
1559 && GET_CODE (XEXP (link, 0)) == REG)
1560 wipe_dead_reg (XEXP (link, 0), 1);
1562 /* Allocate quantities for any SCRATCH operands of this insn. */
1564 if (insn_code_number >= 0)
1565 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1566 if (GET_CODE (recog_operand[i]) == SCRATCH
1567 && scratches_allocated++ < scratch_list_length)
1568 alloc_qty_for_scratch (recog_operand[i], i, insn,
1569 insn_code_number, insn_number);
1571 /* If this is an insn that has a REG_RETVAL note pointing at a
1572 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1573 block, so clear any register number that combined within it. */
1574 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1575 && GET_CODE (XEXP (note, 0)) == INSN
1576 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1577 no_conflict_combined_regno = -1;
1580 /* Set the registers live after INSN_NUMBER. Note that we never
1581 record the registers live before the block's first insn, since no
1582 pseudos we care about are live before that insn. */
1584 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1585 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1587 if (insn == basic_block_end[b])
1590 insn = NEXT_INSN (insn);
1593 /* Now every register that is local to this basic block
1594 should have been given a quantity, or else -1 meaning ignore it.
1595 Every quantity should have a known birth and death.
1597 Order the qtys so we assign them registers in order of the
1598 number of suggested registers they need so we allocate those with
1599 the most restrictive needs first. */
1601 qty_order = (int *) alloca (next_qty * sizeof (int));
1602 for (i = 0; i < next_qty; i++)
1605 #define EXCHANGE(I1, I2) \
1606 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1611 /* Make qty_order[2] be the one to allocate last. */
1612 if (qty_sugg_compare (0, 1) > 0)
1614 if (qty_sugg_compare (1, 2) > 0)
1617 /* ... Fall through ... */
1619 /* Put the best one to allocate in qty_order[0]. */
1620 if (qty_sugg_compare (0, 1) > 0)
1623 /* ... Fall through ... */
1627 /* Nothing to do here. */
1631 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1634 /* Try to put each quantity in a suggested physical register, if it has one.
1635 This may cause registers to be allocated that otherwise wouldn't be, but
1636 this seems acceptable in local allocation (unlike global allocation). */
1637 for (i = 0; i < next_qty; i++)
1640 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1641 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1642 0, 1, qty_birth[q], qty_death[q]);
1644 qty_phys_reg[q] = -1;
1647 /* Order the qtys so we assign them registers in order of
1648 decreasing length of life. Normally call qsort, but if we
1649 have only a very small number of quantities, sort them ourselves. */
1651 for (i = 0; i < next_qty; i++)
1654 #define EXCHANGE(I1, I2) \
1655 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1660 /* Make qty_order[2] be the one to allocate last. */
1661 if (qty_compare (0, 1) > 0)
1663 if (qty_compare (1, 2) > 0)
1666 /* ... Fall through ... */
1668 /* Put the best one to allocate in qty_order[0]. */
1669 if (qty_compare (0, 1) > 0)
1672 /* ... Fall through ... */
1676 /* Nothing to do here. */
1680 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1683 /* Now for each qty that is not a hardware register,
1684 look for a hardware register to put it in.
1685 First try the register class that is cheapest for this qty,
1686 if there is more than one class. */
1688 for (i = 0; i < next_qty; i++)
1691 if (qty_phys_reg[q] < 0)
1693 if (N_REG_CLASSES > 1)
1695 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1696 qty_mode[q], q, 0, 0,
1697 qty_birth[q], qty_death[q]);
1698 if (qty_phys_reg[q] >= 0)
1702 if (qty_alternate_class[q] != NO_REGS)
1703 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1704 qty_mode[q], q, 0, 0,
1705 qty_birth[q], qty_death[q]);
1709 /* Now propagate the register assignments
1710 to the pseudo regs belonging to the qtys. */
1712 for (q = 0; q < next_qty; q++)
1713 if (qty_phys_reg[q] >= 0)
1715 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1716 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1717 if (qty_scratch_rtx[q])
1719 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1721 qty_scratch_rtx[q] = gen_rtx (REG, GET_MODE (qty_scratch_rtx[q]),
1723 scratch_block[scratch_index] = b;
1724 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1730 /* Compare two quantities' priority for getting real registers.
1731 We give shorter-lived quantities higher priority.
1732 Quantities with more references are also preferred, as are quantities that
1733 require multiple registers. This is the identical prioritization as
1734 done by global-alloc.
1736 We used to give preference to registers with *longer* lives, but using
1737 the same algorithm in both local- and global-alloc can speed up execution
1738 of some programs by as much as a factor of three! */
1740 /* Note that the quotient will never be bigger than
1741 the value of floor_log2 times the maximum number of
1742 times a register can occur in one insn (surely less than 100).
1743 Multiplying this by 10000 can't overflow.
1744 QTY_CMP_PRI is also used by qty_sugg_compare. */
1746 #define QTY_CMP_PRI(q) \
1747 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1748 / (qty_death[q] - qty_birth[q])) * 10000))
1751 qty_compare (q1, q2)
1754 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1758 qty_compare_1 (q1p, q2p)
1759 const GENERIC_PTR q1p;
1760 const GENERIC_PTR q2p;
1762 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1763 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1768 /* If qtys are equally good, sort by qty number,
1769 so that the results of qsort leave nothing to chance. */
1773 /* Compare two quantities' priority for getting real registers. This version
1774 is called for quantities that have suggested hard registers. First priority
1775 goes to quantities that have copy preferences, then to those that have
1776 normal preferences. Within those groups, quantities with the lower
1777 number of preferences have the highest priority. Of those, we use the same
1778 algorithm as above. */
1780 #define QTY_CMP_SUGG(q) \
1781 (qty_phys_num_copy_sugg[q] \
1782 ? qty_phys_num_copy_sugg[q] \
1783 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1786 qty_sugg_compare (q1, q2)
1789 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1794 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1798 qty_sugg_compare_1 (q1p, q2p)
1799 const GENERIC_PTR q1p;
1800 const GENERIC_PTR q2p;
1802 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1803 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1808 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1812 /* If qtys are equally good, sort by qty number,
1813 so that the results of qsort leave nothing to chance. */
1820 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1821 Returns 1 if have done so, or 0 if cannot.
1823 Combining registers means marking them as having the same quantity
1824 and adjusting the offsets within the quantity if either of
1827 We don't actually combine a hard reg with a pseudo; instead
1828 we just record the hard reg as the suggestion for the pseudo's quantity.
1829 If we really combined them, we could lose if the pseudo lives
1830 across an insn that clobbers the hard reg (eg, movstr).
1832 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1833 there is no REG_DEAD note on INSN. This occurs during the processing
1834 of REG_NO_CONFLICT blocks.
1836 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1837 SETREG or if the input and output must share a register.
1838 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1840 There are elaborate checks for the validity of combining. */
1844 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1845 rtx usedreg, setreg;
1851 register int ureg, sreg;
1852 register int offset = 0;
1856 /* Determine the numbers and sizes of registers being used. If a subreg
1857 is present that does not change the entire register, don't consider
1858 this a copy insn. */
1860 while (GET_CODE (usedreg) == SUBREG)
1862 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1864 offset += SUBREG_WORD (usedreg);
1865 usedreg = SUBREG_REG (usedreg);
1867 if (GET_CODE (usedreg) != REG)
1869 ureg = REGNO (usedreg);
1870 usize = REG_SIZE (usedreg);
1872 while (GET_CODE (setreg) == SUBREG)
1874 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1876 offset -= SUBREG_WORD (setreg);
1877 setreg = SUBREG_REG (setreg);
1879 if (GET_CODE (setreg) != REG)
1881 sreg = REGNO (setreg);
1882 ssize = REG_SIZE (setreg);
1884 /* If UREG is a pseudo-register that hasn't already been assigned a
1885 quantity number, it means that it is not local to this block or dies
1886 more than once. In either event, we can't do anything with it. */
1887 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1888 /* Do not combine registers unless one fits within the other. */
1889 || (offset > 0 && usize + offset > ssize)
1890 || (offset < 0 && usize + offset < ssize)
1891 /* Do not combine with a smaller already-assigned object
1892 if that smaller object is already combined with something bigger. */
1893 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1894 && usize < qty_size[reg_qty[ureg]])
1895 /* Can't combine if SREG is not a register we can allocate. */
1896 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1897 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1898 These have already been taken care of. This probably wouldn't
1899 combine anyway, but don't take any chances. */
1900 || (ureg >= FIRST_PSEUDO_REGISTER
1901 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1902 /* Don't tie something to itself. In most cases it would make no
1903 difference, but it would screw up if the reg being tied to itself
1904 also dies in this insn. */
1906 /* Don't try to connect two different hardware registers. */
1907 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1908 /* Don't connect two different machine modes if they have different
1909 implications as to which registers may be used. */
1910 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1913 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1914 qty_phys_sugg for the pseudo instead of tying them.
1916 Return "failure" so that the lifespan of UREG is terminated here;
1917 that way the two lifespans will be disjoint and nothing will prevent
1918 the pseudo reg from being given this hard reg. */
1920 if (ureg < FIRST_PSEUDO_REGISTER)
1922 /* Allocate a quantity number so we have a place to put our
1924 if (reg_qty[sreg] == -2)
1925 reg_is_born (setreg, 2 * insn_number);
1927 if (reg_qty[sreg] >= 0)
1930 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1932 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1933 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1935 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1937 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1938 qty_phys_num_sugg[reg_qty[sreg]]++;
1944 /* Similarly for SREG a hard register and UREG a pseudo register. */
1946 if (sreg < FIRST_PSEUDO_REGISTER)
1949 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1951 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1952 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1954 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1956 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1957 qty_phys_num_sugg[reg_qty[ureg]]++;
1962 /* At this point we know that SREG and UREG are both pseudos.
1963 Do nothing if SREG already has a quantity or is a register that we
1965 if (reg_qty[sreg] >= -1
1966 /* If we are not going to let any regs live across calls,
1967 don't tie a call-crossing reg to a non-call-crossing reg. */
1968 || (current_function_has_nonlocal_label
1969 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1970 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1973 /* We don't already know about SREG, so tie it to UREG
1974 if this is the last use of UREG, provided the classes they want
1977 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1978 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1980 /* Add SREG to UREG's quantity. */
1981 sqty = reg_qty[ureg];
1982 reg_qty[sreg] = sqty;
1983 reg_offset[sreg] = reg_offset[ureg] + offset;
1984 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1985 qty_first_reg[sqty] = sreg;
1987 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1988 update_qty_class (sqty, sreg);
1990 /* Update info about quantity SQTY. */
1991 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1992 qty_n_refs[sqty] += REG_N_REFS (sreg);
1997 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1998 reg_offset[i] -= offset;
2000 qty_size[sqty] = ssize;
2001 qty_mode[sqty] = GET_MODE (setreg);
2010 /* Return 1 if the preferred class of REG allows it to be tied
2011 to a quantity or register whose class is CLASS.
2012 True if REG's reg class either contains or is contained in CLASS. */
2015 reg_meets_class_p (reg, class)
2017 enum reg_class class;
2019 register enum reg_class rclass = reg_preferred_class (reg);
2020 return (reg_class_subset_p (rclass, class)
2021 || reg_class_subset_p (class, rclass));
2024 /* Return 1 if the two specified classes have registers in common.
2025 If CALL_SAVED, then consider only call-saved registers. */
2028 reg_classes_overlap_p (c1, c2, call_saved)
2029 register enum reg_class c1;
2030 register enum reg_class c2;
2036 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2037 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2039 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2040 if (TEST_HARD_REG_BIT (c, i)
2041 && (! call_saved || ! call_used_regs[i]))
2047 /* Update the class of QTY assuming that REG is being tied to it. */
2050 update_qty_class (qty, reg)
2054 enum reg_class rclass = reg_preferred_class (reg);
2055 if (reg_class_subset_p (rclass, qty_min_class[qty]))
2056 qty_min_class[qty] = rclass;
2058 rclass = reg_alternate_class (reg);
2059 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
2060 qty_alternate_class[qty] = rclass;
2062 if (REG_CHANGES_SIZE (reg))
2063 qty_changes_size[qty] = 1;
2066 /* Handle something which alters the value of an rtx REG.
2068 REG is whatever is set or clobbered. SETTER is the rtx that
2069 is modifying the register.
2071 If it is not really a register, we do nothing.
2072 The file-global variables `this_insn' and `this_insn_number'
2073 carry info from `block_alloc'. */
2076 reg_is_set (reg, setter)
2080 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2081 a hard register. These may actually not exist any more. */
2083 if (GET_CODE (reg) != SUBREG
2084 && GET_CODE (reg) != REG)
2087 /* Mark this register as being born. If it is used in a CLOBBER, mark
2088 it as being born halfway between the previous insn and this insn so that
2089 it conflicts with our inputs but not the outputs of the previous insn. */
2091 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2094 /* Handle beginning of the life of register REG.
2095 BIRTH is the index at which this is happening. */
2098 reg_is_born (reg, birth)
2104 if (GET_CODE (reg) == SUBREG)
2105 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
2107 regno = REGNO (reg);
2109 if (regno < FIRST_PSEUDO_REGISTER)
2111 mark_life (regno, GET_MODE (reg), 1);
2113 /* If the register was to have been born earlier that the present
2114 insn, mark it as live where it is actually born. */
2115 if (birth < 2 * this_insn_number)
2116 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2120 if (reg_qty[regno] == -2)
2121 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2123 /* If this register has a quantity number, show that it isn't dead. */
2124 if (reg_qty[regno] >= 0)
2125 qty_death[reg_qty[regno]] = -1;
2129 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2130 REG is an output that is dying (i.e., it is never used), otherwise it
2131 is an input (the normal case).
2132 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2135 wipe_dead_reg (reg, output_p)
2139 register int regno = REGNO (reg);
2141 /* If this insn has multiple results,
2142 and the dead reg is used in one of the results,
2143 extend its life to after this insn,
2144 so it won't get allocated together with any other result of this insn. */
2145 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2146 && !single_set (this_insn))
2149 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2151 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2152 if (GET_CODE (set) == SET
2153 && GET_CODE (SET_DEST (set)) != REG
2154 && !rtx_equal_p (reg, SET_DEST (set))
2155 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2160 /* If this register is used in an auto-increment address, then extend its
2161 life to after this insn, so that it won't get allocated together with
2162 the result of this insn. */
2163 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2166 if (regno < FIRST_PSEUDO_REGISTER)
2168 mark_life (regno, GET_MODE (reg), 0);
2170 /* If a hard register is dying as an output, mark it as in use at
2171 the beginning of this insn (the above statement would cause this
2174 post_mark_life (regno, GET_MODE (reg), 1,
2175 2 * this_insn_number, 2 * this_insn_number+ 1);
2178 else if (reg_qty[regno] >= 0)
2179 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2182 /* Find a block of SIZE words of hard regs in reg_class CLASS
2183 that can hold something of machine-mode MODE
2184 (but actually we test only the first of the block for holding MODE)
2185 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2186 and return the number of the first of them.
2187 Return -1 if such a block cannot be found.
2188 If QTY crosses calls, insist on a register preserved by calls,
2189 unless ACCEPT_CALL_CLOBBERED is nonzero.
2191 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2192 register is available. If not, return -1. */
2195 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2196 born_index, dead_index)
2197 enum reg_class class;
2198 enum machine_mode mode;
2200 int accept_call_clobbered;
2201 int just_try_suggested;
2202 int born_index, dead_index;
2204 register int i, ins;
2206 register /* Declare it register if it's a scalar. */
2208 HARD_REG_SET used, first_used;
2209 #ifdef ELIMINABLE_REGS
2210 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2213 /* Validate our parameters. */
2214 if (born_index < 0 || born_index > dead_index)
2217 /* Don't let a pseudo live in a reg across a function call
2218 if we might get a nonlocal goto. */
2219 if (current_function_has_nonlocal_label
2220 && qty_n_calls_crossed[qty] > 0)
2223 if (accept_call_clobbered)
2224 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2225 else if (qty_n_calls_crossed[qty] == 0)
2226 COPY_HARD_REG_SET (used, fixed_reg_set);
2228 COPY_HARD_REG_SET (used, call_used_reg_set);
2230 if (accept_call_clobbered)
2231 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2233 for (ins = born_index; ins < dead_index; ins++)
2234 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2236 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2238 /* Don't use the frame pointer reg in local-alloc even if
2239 we may omit the frame pointer, because if we do that and then we
2240 need a frame pointer, reload won't know how to move the pseudo
2241 to another hard reg. It can move only regs made by global-alloc.
2243 This is true of any register that can be eliminated. */
2244 #ifdef ELIMINABLE_REGS
2245 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2246 SET_HARD_REG_BIT (used, eliminables[i].from);
2247 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2248 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2249 that it might be eliminated into. */
2250 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2253 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2256 #ifdef CLASS_CANNOT_CHANGE_SIZE
2257 if (qty_changes_size[qty])
2258 IOR_HARD_REG_SET (used,
2259 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2262 /* Normally, the registers that can be used for the first register in
2263 a multi-register quantity are the same as those that can be used for
2264 subsequent registers. However, if just trying suggested registers,
2265 restrict our consideration to them. If there are copy-suggested
2266 register, try them. Otherwise, try the arithmetic-suggested
2268 COPY_HARD_REG_SET (first_used, used);
2270 if (just_try_suggested)
2272 if (qty_phys_num_copy_sugg[qty] != 0)
2273 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2275 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2278 /* If all registers are excluded, we can't do anything. */
2279 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2281 /* If at least one would be suitable, test each hard reg. */
2283 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2285 #ifdef REG_ALLOC_ORDER
2286 int regno = reg_alloc_order[i];
2290 if (! TEST_HARD_REG_BIT (first_used, regno)
2291 && HARD_REGNO_MODE_OK (regno, mode))
2294 register int size1 = HARD_REGNO_NREGS (regno, mode);
2295 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2298 /* Mark that this register is in use between its birth and death
2300 post_mark_life (regno, mode, 1, born_index, dead_index);
2303 #ifndef REG_ALLOC_ORDER
2304 i += j; /* Skip starting points we know will lose */
2311 /* If we are just trying suggested register, we have just tried copy-
2312 suggested registers, and there are arithmetic-suggested registers,
2315 /* If it would be profitable to allocate a call-clobbered register
2316 and save and restore it around calls, do that. */
2317 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2318 && qty_phys_num_sugg[qty] != 0)
2320 /* Don't try the copy-suggested regs again. */
2321 qty_phys_num_copy_sugg[qty] = 0;
2322 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2323 born_index, dead_index);
2326 /* We need not check to see if the current function has nonlocal
2327 labels because we don't put any pseudos that are live over calls in
2328 registers in that case. */
2330 if (! accept_call_clobbered
2331 && flag_caller_saves
2332 && ! just_try_suggested
2333 && qty_n_calls_crossed[qty] != 0
2334 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2336 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2338 caller_save_needed = 1;
2344 /* Mark that REGNO with machine-mode MODE is live starting from the current
2345 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2349 mark_life (regno, mode, life)
2351 enum machine_mode mode;
2354 register int j = HARD_REGNO_NREGS (regno, mode);
2357 SET_HARD_REG_BIT (regs_live, regno + j);
2360 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2363 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2364 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2365 to insn number DEATH (exclusive). */
2368 post_mark_life (regno, mode, life, birth, death)
2370 enum machine_mode mode;
2371 int life, birth, death;
2373 register int j = HARD_REGNO_NREGS (regno, mode);
2375 register /* Declare it register if it's a scalar. */
2377 HARD_REG_SET this_reg;
2379 CLEAR_HARD_REG_SET (this_reg);
2381 SET_HARD_REG_BIT (this_reg, regno + j);
2384 while (birth < death)
2386 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2390 while (birth < death)
2392 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2397 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2398 is the register being clobbered, and R1 is a register being used in
2399 the equivalent expression.
2401 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2402 in which it is used, return 1.
2404 Otherwise, return 0. */
2407 no_conflict_p (insn, r0, r1)
2411 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2414 /* If R1 is a hard register, return 0 since we handle this case
2415 when we scan the insns that actually use it. */
2418 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2419 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2420 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2423 last = XEXP (note, 0);
2425 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2426 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2428 if (find_reg_note (p, REG_DEAD, r1))
2431 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2432 some earlier optimization pass has inserted instructions into
2433 the sequence, and it is not safe to perform this optimization.
2434 Note that emit_no_conflict_block always ensures that this is
2435 true when these sequences are created. */
2436 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2443 #ifdef REGISTER_CONSTRAINTS
2445 /* Return the number of alternatives for which the constraint string P
2446 indicates that the operand must be equal to operand 0 and that no register
2455 int reg_allowed = 0;
2456 int num_matching_alts = 0;
2461 case '=': case '+': case '?':
2462 case '#': case '&': case '!':
2464 case '1': case '2': case '3': case '4':
2465 case 'm': case '<': case '>': case 'V': case 'o':
2466 case 'E': case 'F': case 'G': case 'H':
2467 case 's': case 'i': case 'n':
2468 case 'I': case 'J': case 'K': case 'L':
2469 case 'M': case 'N': case 'O': case 'P':
2470 #ifdef EXTRA_CONSTRAINT
2471 case 'Q': case 'R': case 'S': case 'T': case 'U':
2474 /* These don't say anything we care about. */
2478 if (found_zero && ! reg_allowed)
2479 num_matching_alts++;
2481 found_zero = reg_allowed = 0;
2495 if (found_zero && ! reg_allowed)
2496 num_matching_alts++;
2498 return num_matching_alts;
2500 #endif /* REGISTER_CONSTRAINTS */
2503 dump_local_alloc (file)
2507 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2508 if (reg_renumber[i] != -1)
2509 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
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