1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
69 #include "basic-block.h"
71 #include "hard-reg-set.h"
72 #include "insn-config.h"
76 /* Next quantity number available for allocation. */
80 /* In all the following vectors indexed by quantity number. */
82 /* Element Q is the hard reg number chosen for quantity Q,
83 or -1 if none was found. */
85 static short *qty_phys_reg;
87 /* We maintain two hard register sets that indicate suggested hard registers
88 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
89 that are tied to the quantity by a simple copy. The second contains all
90 hard registers that are tied to the quantity via an arithmetic operation.
92 The former register set is given priority for allocation. This tends to
93 eliminate copy insns. */
95 /* Element Q is a set of hard registers that are suggested for quantity Q by
98 static HARD_REG_SET *qty_phys_copy_sugg;
100 /* Element Q is a set of hard registers that are suggested for quantity Q by
103 static HARD_REG_SET *qty_phys_sugg;
105 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
107 static short *qty_phys_num_copy_sugg;
109 /* Element Q is the number of suggested registers in qty_phys_sugg. */
111 static short *qty_phys_num_sugg;
113 /* Element Q is the number of refs to quantity Q. */
115 static int *qty_n_refs;
117 /* Element Q is a reg class contained in (smaller than) the
118 preferred classes of all the pseudo regs that are tied in quantity Q.
119 This is the preferred class for allocating that quantity. */
121 static enum reg_class *qty_min_class;
123 /* Insn number (counting from head of basic block)
124 where quantity Q was born. -1 if birth has not been recorded. */
126 static int *qty_birth;
128 /* Insn number (counting from head of basic block)
129 where quantity Q died. Due to the way tying is done,
130 and the fact that we consider in this pass only regs that die but once,
131 a quantity can die only once. Each quantity's life span
132 is a set of consecutive insns. -1 if death has not been recorded. */
134 static int *qty_death;
136 /* Number of words needed to hold the data in quantity Q.
137 This depends on its machine mode. It is used for these purposes:
138 1. It is used in computing the relative importances of qtys,
139 which determines the order in which we look for regs for them.
140 2. It is used in rules that prevent tying several registers of
141 different sizes in a way that is geometrically impossible
142 (see combine_regs). */
144 static int *qty_size;
146 /* This holds the mode of the registers that are tied to qty Q,
147 or VOIDmode if registers with differing modes are tied together. */
149 static enum machine_mode *qty_mode;
151 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
153 static int *qty_n_calls_crossed;
155 /* Register class within which we allocate qty Q if we can't get
156 its preferred class. */
158 static enum reg_class *qty_alternate_class;
160 /* Element Q is the SCRATCH expression for which this quantity is being
161 allocated or 0 if this quantity is allocating registers. */
163 static rtx *qty_scratch_rtx;
165 /* Element Q is nonzero if this quantity has been used in a SUBREG
166 that changes its size. */
168 static char *qty_changes_size;
170 /* Element Q is the register number of one pseudo register whose
171 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
172 register should be the head of the chain maintained in reg_next_in_qty. */
174 static int *qty_first_reg;
176 /* If (REG N) has been assigned a quantity number, is a register number
177 of another register assigned the same quantity number, or -1 for the
178 end of the chain. qty_first_reg point to the head of this chain. */
180 static int *reg_next_in_qty;
182 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
184 of -1 if this register cannot be allocated by local-alloc,
185 or -2 if not known yet.
187 Note that if we see a use or death of pseudo register N with
188 reg_qty[N] == -2, register N must be local to the current block. If
189 it were used in more than one block, we would have reg_qty[N] == -1.
190 This relies on the fact that if reg_basic_block[N] is >= 0, register N
191 will not appear in any other block. We save a considerable number of
192 tests by exploiting this.
194 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
199 /* The offset (in words) of register N within its quantity.
200 This can be nonzero if register N is SImode, and has been tied
201 to a subreg of a DImode register. */
203 static char *reg_offset;
205 /* Vector of substitutions of register numbers,
206 used to map pseudo regs into hardware regs.
207 This is set up as a result of register allocation.
208 Element N is the hard reg assigned to pseudo reg N,
209 or is -1 if no hard reg was assigned.
210 If N is a hard reg number, element N is N. */
214 /* Set of hard registers live at the current point in the scan
215 of the instructions in a basic block. */
217 static HARD_REG_SET regs_live;
219 /* Each set of hard registers indicates registers live at a particular
220 point in the basic block. For N even, regs_live_at[N] says which
221 hard registers are needed *after* insn N/2 (i.e., they may not
222 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
224 If an object is to conflict with the inputs of insn J but not the
225 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
226 if it is to conflict with the outputs of insn J but not the inputs of
227 insn J + 1, it is said to die at index J*2 + 1. */
229 static HARD_REG_SET *regs_live_at;
233 int scratch_list_length;
234 static int scratch_index;
236 /* Communicate local vars `insn_number' and `insn'
237 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
238 static int this_insn_number;
239 static rtx this_insn;
241 /* Used to communicate changes made by update_equiv_regs to
242 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
243 found or created, so that we can keep track of what memory accesses might
244 be created later, e.g. by reload. */
246 static rtx *reg_equiv_replacement;
248 static void alloc_qty PROTO((int, enum machine_mode, int, int));
249 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
250 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
251 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
252 static int contains_replace_regs PROTO((rtx, char *));
253 static int memref_referenced_p PROTO((rtx, rtx));
254 static int memref_used_between_p PROTO((rtx, rtx, rtx));
255 static void update_equiv_regs PROTO((void));
256 static void block_alloc PROTO((int));
257 static int qty_sugg_compare PROTO((int, int));
258 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
259 static int qty_compare PROTO((int, int));
260 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
261 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
262 static int reg_meets_class_p PROTO((int, enum reg_class));
263 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
265 static void update_qty_class PROTO((int, int));
266 static void reg_is_set PROTO((rtx, rtx));
267 static void reg_is_born PROTO((rtx, int));
268 static void wipe_dead_reg PROTO((rtx, int));
269 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
270 int, int, int, int, int));
271 static void mark_life PROTO((int, enum machine_mode, int));
272 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
273 static int no_conflict_p PROTO((rtx, rtx, rtx));
274 static int requires_inout PROTO((char *));
276 /* Allocate a new quantity (new within current basic block)
277 for register number REGNO which is born at index BIRTH
278 within the block. MODE and SIZE are info on reg REGNO. */
281 alloc_qty (regno, mode, size, birth)
283 enum machine_mode mode;
286 register int qty = next_qty++;
288 reg_qty[regno] = qty;
289 reg_offset[regno] = 0;
290 reg_next_in_qty[regno] = -1;
292 qty_first_reg[qty] = regno;
293 qty_size[qty] = size;
294 qty_mode[qty] = mode;
295 qty_birth[qty] = birth;
296 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
297 qty_min_class[qty] = reg_preferred_class (regno);
298 qty_alternate_class[qty] = reg_alternate_class (regno);
299 qty_n_refs[qty] = REG_N_REFS (regno);
300 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
303 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
304 used as operand N in INSN. We assume here that the SCRATCH is used in
308 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
312 int insn_code_num, insn_number;
315 enum reg_class class;
319 #ifdef REGISTER_CONSTRAINTS
320 /* If we haven't yet computed which alternative will be used, do so now.
321 Then set P to the constraints for that alternative. */
322 if (which_alternative == -1)
323 if (! constrain_operands (insn_code_num, 0))
326 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
327 *p && i < which_alternative; p++)
331 /* Compute the class required for this SCRATCH. If we don't need a
332 register, the class will remain NO_REGS. If we guessed the alternative
333 number incorrectly, reload will fix things up for us. */
336 while ((c = *p++) != '\0' && c != ',')
339 case '=': case '+': case '?':
340 case '#': case '&': case '!':
342 case '0': case '1': case '2': case '3': case '4':
343 case 'm': case '<': case '>': case 'V': case 'o':
344 case 'E': case 'F': case 'G': case 'H':
345 case 's': case 'i': case 'n':
346 case 'I': case 'J': case 'K': case 'L':
347 case 'M': case 'N': case 'O': case 'P':
348 #ifdef EXTRA_CONSTRAINT
349 case 'Q': case 'R': case 'S': case 'T': case 'U':
352 /* These don't say anything we care about. */
356 /* We don't need to allocate this SCRATCH. */
360 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
365 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
369 if (class == NO_REGS)
372 #else /* REGISTER_CONSTRAINTS */
374 class = GENERAL_REGS;
380 qty_first_reg[qty] = -1;
381 qty_scratch_rtx[qty] = scratch;
382 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
383 qty_mode[qty] = GET_MODE (scratch);
384 qty_birth[qty] = 2 * insn_number - 1;
385 qty_death[qty] = 2 * insn_number + 1;
386 qty_n_calls_crossed[qty] = 0;
387 qty_min_class[qty] = class;
388 qty_alternate_class[qty] = NO_REGS;
390 qty_changes_size[qty] = 0;
393 /* Main entry point of this file. */
401 /* Leaf functions and non-leaf functions have different needs.
402 If defined, let the machine say what kind of ordering we
404 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
405 ORDER_REGS_FOR_LOCAL_ALLOC;
408 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
410 update_equiv_regs ();
412 /* This sets the maximum number of quantities we can have. Quantity
413 numbers start at zero and we can have one for each pseudo plus the
414 number of SCRATCHes in the largest block, in the worst case. */
415 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
417 /* Allocate vectors of temporary data.
418 See the declarations of these variables, above,
419 for what they mean. */
421 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
422 Instead of allocating this much memory from now until the end of
423 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
424 reload will allocate them. */
426 scratch_list_length = max_qty;
427 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
428 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
429 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
430 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
433 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
435 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
436 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
437 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
438 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
439 qty_birth = (int *) alloca (max_qty * sizeof (int));
440 qty_death = (int *) alloca (max_qty * sizeof (int));
441 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
442 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
443 qty_size = (int *) alloca (max_qty * sizeof (int));
445 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
446 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
448 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
450 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
451 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
452 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
454 reg_qty = (int *) alloca (max_regno * sizeof (int));
455 reg_offset = (char *) alloca (max_regno * sizeof (char));
456 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
458 /* Allocate the reg_renumber array */
459 allocate_reg_info (max_regno, FALSE, TRUE);
461 /* Determine which pseudo-registers can be allocated by local-alloc.
462 In general, these are the registers used only in a single block and
463 which only die once. However, if a register's preferred class has only
464 a few entries, don't allocate this register here unless it is preferred
465 or nothing since retry_global_alloc won't be able to move it to
466 GENERAL_REGS if a reload register of this class is needed.
468 We need not be concerned with which block actually uses the register
469 since we will never see it outside that block. */
471 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
473 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
474 && (reg_alternate_class (i) == NO_REGS
475 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
481 /* Force loop below to initialize entire quantity array. */
484 /* Allocate each block's local registers, block by block. */
486 for (b = 0; b < n_basic_blocks; b++)
488 /* NEXT_QTY indicates which elements of the `qty_...'
489 vectors might need to be initialized because they were used
490 for the previous block; it is set to the entire array before
491 block 0. Initialize those, with explicit loop if there are few,
492 else with bzero and bcopy. Do not initialize vectors that are
493 explicit set by `alloc_qty'. */
497 for (i = 0; i < next_qty; i++)
499 qty_scratch_rtx[i] = 0;
500 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
501 qty_phys_num_copy_sugg[i] = 0;
502 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
503 qty_phys_num_sugg[i] = 0;
508 #define CLEAR(vector) \
509 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
511 CLEAR (qty_scratch_rtx);
512 CLEAR (qty_phys_copy_sugg);
513 CLEAR (qty_phys_num_copy_sugg);
514 CLEAR (qty_phys_sugg);
515 CLEAR (qty_phys_num_sugg);
527 /* Depth of loops we are in while in update_equiv_regs. */
528 static int loop_depth;
530 /* Used for communication between the following two functions: contains
531 a MEM that we wish to ensure remains unchanged. */
532 static rtx equiv_mem;
534 /* Set nonzero if EQUIV_MEM is modified. */
535 static int equiv_mem_modified;
537 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
538 Called via note_stores. */
541 validate_equiv_mem_from_store (dest, set)
545 if ((GET_CODE (dest) == REG
546 && reg_overlap_mentioned_p (dest, equiv_mem))
547 || (GET_CODE (dest) == MEM
548 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
549 equiv_mem_modified = 1;
552 /* Verify that no store between START and the death of REG invalidates
553 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
554 by storing into an overlapping memory location, or with a non-const
557 Return 1 if MEMREF remains valid. */
560 validate_equiv_mem (start, reg, memref)
569 equiv_mem_modified = 0;
571 /* If the memory reference has side effects or is volatile, it isn't a
572 valid equivalence. */
573 if (side_effects_p (memref))
576 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
578 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
581 if (find_reg_note (insn, REG_DEAD, reg))
584 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
585 && ! CONST_CALL_P (insn))
588 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
590 /* If a register mentioned in MEMREF is modified via an
591 auto-increment, we lose the equivalence. Do the same if one
592 dies; although we could extend the life, it doesn't seem worth
595 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
596 if ((REG_NOTE_KIND (note) == REG_INC
597 || REG_NOTE_KIND (note) == REG_DEAD)
598 && GET_CODE (XEXP (note, 0)) == REG
599 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
606 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
609 contains_replace_regs (x, reg_equiv_replace)
611 char *reg_equiv_replace;
615 enum rtx_code code = GET_CODE (x);
631 return reg_equiv_replace[REGNO (x)];
637 fmt = GET_RTX_FORMAT (code);
638 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
642 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
646 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
647 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
655 /* TRUE if X references a memory location that would be affected by a store
659 memref_referenced_p (memref, x)
665 enum rtx_code code = GET_CODE (x);
681 return (reg_equiv_replacement[REGNO (x)]
682 && memref_referenced_p (memref,
683 reg_equiv_replacement[REGNO (x)]));
686 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
691 /* If we are setting a MEM, it doesn't count (its address does), but any
692 other SET_DEST that has a MEM in it is referencing the MEM. */
693 if (GET_CODE (SET_DEST (x)) == MEM)
695 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
698 else if (memref_referenced_p (memref, SET_DEST (x)))
701 return memref_referenced_p (memref, SET_SRC (x));
707 fmt = GET_RTX_FORMAT (code);
708 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
712 if (memref_referenced_p (memref, XEXP (x, i)))
716 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
717 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
725 /* TRUE if some insn in the range (START, END] references a memory location
726 that would be affected by a store to MEMREF. */
729 memref_used_between_p (memref, start, end)
736 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
737 insn = NEXT_INSN (insn))
738 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
739 && memref_referenced_p (memref, PATTERN (insn)))
745 /* Find registers that are equivalent to a single value throughout the
746 compilation (either because they can be referenced in memory or are set once
747 from a single constant). Lower their priority for a register.
749 If such a register is only referenced once, try substituting its value
750 into the using insn. If it succeeds, we can eliminate the register
756 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
757 /* Set when an attempt should be made to replace a register with the
758 associated reg_equiv_replacement entry at the end of this function. */
759 char *reg_equiv_replace
760 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
764 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
766 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
767 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
768 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
770 init_alias_analysis ();
774 /* Scan the insns and find which registers have equivalences. Do this
775 in a separate scan of the insns because (due to -fcse-follow-jumps)
776 a register can be set below its use. */
777 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
780 rtx set = single_set (insn);
784 if (GET_CODE (insn) == NOTE)
786 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
788 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
792 /* If this insn contains more (or less) than a single SET, ignore it. */
796 dest = SET_DEST (set);
799 /* If this sets a MEM to the contents of a REG that is only used
800 in a single basic block, see if the register is always equivalent
801 to that memory location and if moving the store from INSN to the
802 insn that set REG is safe. If so, put a REG_EQUIV note on the
805 Don't add a REG_EQUIV note if the insn already has one. The existing
806 REG_EQUIV is likely more useful than the one we are adding.
808 If one of the regs in the address is marked as reg_equiv_replace,
809 then we can't add this REG_EQUIV note. The reg_equiv_replace
810 optimization may move the set of this register immediately before
811 insn, which puts it after reg_equiv_init_insn[regno], and hence
812 the mention in the REG_EQUIV note would be to an uninitialized
815 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
816 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
817 && REG_BASIC_BLOCK (regno) >= 0
818 && reg_equiv_init_insn[regno] != 0
819 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
820 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
821 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
823 && ! memref_used_between_p (SET_DEST (set),
824 reg_equiv_init_insn[regno], insn))
825 REG_NOTES (reg_equiv_init_insn[regno])
826 = gen_rtx_EXPR_LIST (REG_EQUIV, dest,
827 REG_NOTES (reg_equiv_init_insn[regno]));
829 /* We only handle the case of a pseudo register being set
830 once and only if neither the source nor the destination are
831 in a register class that's likely to be spilled. */
832 if (GET_CODE (dest) != REG
833 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
834 || REG_N_SETS (regno) != 1
835 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
836 || (GET_CODE (src) == REG
837 && REGNO (src) >= FIRST_PSEUDO_REGISTER
838 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
841 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
843 #ifdef DONT_RECORD_EQUIVALENCE
844 /* Allow the target to reject promotions of some REG_EQUAL notes to
847 In some cases this can improve register allocation if the existence
848 of the REG_EQUIV note is likely to increase the lifetime of a register
849 that is likely to be spilled.
851 It may also be necessary if the target can't handle certain constant
852 expressions appearing randomly in insns, but for whatever reason
853 those expressions must be considered legitimate constant expressions
854 to prevent them from being forced into memory. */
855 if (note && DONT_RECORD_EQUIVALENCE (note))
859 /* Record this insn as initializing this register. */
860 reg_equiv_init_insn[regno] = insn;
862 /* If this register is known to be equal to a constant, record that
863 it is always equivalent to the constant. */
864 if (note && CONSTANT_P (XEXP (note, 0)))
865 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
867 /* If this insn introduces a "constant" register, decrease the priority
868 of that register. Record this insn if the register is only used once
869 more and the equivalence value is the same as our source.
871 The latter condition is checked for two reasons: First, it is an
872 indication that it may be more efficient to actually emit the insn
873 as written (if no registers are available, reload will substitute
874 the equivalence). Secondly, it avoids problems with any registers
875 dying in this insn whose death notes would be missed.
877 If we don't have a REG_EQUIV note, see if this insn is loading
878 a register used only in one basic block from a MEM. If so, and the
879 MEM remains unchanged for the life of the register, add a REG_EQUIV
882 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
884 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
885 && GET_CODE (SET_SRC (set)) == MEM
886 && validate_equiv_mem (insn, dest, SET_SRC (set)))
887 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
892 int regno = REGNO (dest);
894 reg_equiv_replacement[regno] = XEXP (note, 0);
896 /* Don't mess with things live during setjmp. */
897 if (REG_LIVE_LENGTH (regno) >= 0)
899 /* Note that the statement below does not affect the priority
901 REG_LIVE_LENGTH (regno) *= 2;
904 /* If the register is referenced exactly twice, meaning it is
905 set once and used once, indicate that the reference may be
906 replaced by the equivalence we computed above. If the
907 register is only used in one basic block, this can't succeed
908 or combine would have done it.
910 It would be nice to use "loop_depth * 2" in the compare
911 below. Unfortunately, LOOP_DEPTH need not be constant within
912 a basic block so this would be too complicated.
914 This case normally occurs when a parameter is read from
915 memory and then used exactly once, not in a loop. */
917 if (REG_N_REFS (regno) == 2
918 && REG_BASIC_BLOCK (regno) < 0
919 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
920 reg_equiv_replace[regno] = 1;
925 /* Now scan all regs killed in an insn to see if any of them are
926 registers only used that once. If so, see if we can replace the
927 reference with the equivalent from. If we can, delete the
928 initializing reference and this register will go away. If we
929 can't replace the reference, and the instruction is not in a
930 loop, then move the register initialization just before the use,
931 so that they are in the same basic block. */
934 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
938 /* Keep track of which basic block we are in. */
939 if (block + 1 < n_basic_blocks
940 && basic_block_head[block + 1] == insn)
943 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
945 if (GET_CODE (insn) == NOTE)
947 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
949 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
960 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
962 if (REG_NOTE_KIND (link) == REG_DEAD
963 /* Make sure this insn still refers to the register. */
964 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
966 int regno = REGNO (XEXP (link, 0));
969 if (! reg_equiv_replace[regno])
972 equiv_insn = reg_equiv_init_insn[regno];
974 if (validate_replace_rtx (regno_reg_rtx[regno],
975 reg_equiv_replacement[regno], insn))
977 remove_death (regno, insn);
978 REG_N_REFS (regno) = 0;
979 PUT_CODE (equiv_insn, NOTE);
980 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
981 NOTE_SOURCE_FILE (equiv_insn) = 0;
983 /* If we aren't in a loop, and there are no calls in
984 INSN or in the initialization of the register, then
985 move the initialization of the register to just
986 before INSN. Update the flow information. */
988 && GET_CODE (equiv_insn) == INSN
989 && GET_CODE (insn) == INSN
990 && REG_BASIC_BLOCK (regno) < 0)
994 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
995 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
997 PUT_CODE (equiv_insn, NOTE);
998 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
999 NOTE_SOURCE_FILE (equiv_insn) = 0;
1000 REG_NOTES (equiv_insn) = 0;
1003 REG_BASIC_BLOCK (regno) = 0;
1005 REG_BASIC_BLOCK (regno) = block;
1006 REG_N_CALLS_CROSSED (regno) = 0;
1007 REG_LIVE_LENGTH (regno) = 2;
1009 if (block >= 0 && insn == basic_block_head[block])
1010 basic_block_head[block] = PREV_INSN (insn);
1012 for (l = 0; l < n_basic_blocks; l++)
1013 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1020 /* Allocate hard regs to the pseudo regs used only within block number B.
1021 Only the pseudos that die but once can be handled. */
1030 int insn_number = 0;
1032 int max_uid = get_max_uid ();
1034 int no_conflict_combined_regno = -1;
1035 /* Counter to prevent allocating more SCRATCHes than can be stored
1037 int scratches_allocated = scratch_index;
1039 /* Count the instructions in the basic block. */
1041 insn = basic_block_end[b];
1044 if (GET_CODE (insn) != NOTE)
1045 if (++insn_count > max_uid)
1047 if (insn == basic_block_head[b])
1049 insn = PREV_INSN (insn);
1052 /* +2 to leave room for a post_mark_life at the last insn and for
1053 the birth of a CLOBBER in the first insn. */
1054 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1055 * sizeof (HARD_REG_SET));
1056 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1058 /* Initialize table of hardware registers currently live. */
1060 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1062 /* This loop scans the instructions of the basic block
1063 and assigns quantities to registers.
1064 It computes which registers to tie. */
1066 insn = basic_block_head[b];
1069 register rtx body = PATTERN (insn);
1071 if (GET_CODE (insn) != NOTE)
1074 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1076 register rtx link, set;
1077 register int win = 0;
1078 register rtx r0, r1;
1079 int combined_regno = -1;
1081 int insn_code_number = recog_memoized (insn);
1083 this_insn_number = insn_number;
1086 if (insn_code_number >= 0)
1087 insn_extract (insn);
1088 which_alternative = -1;
1090 /* Is this insn suitable for tying two registers?
1091 If so, try doing that.
1092 Suitable insns are those with at least two operands and where
1093 operand 0 is an output that is a register that is not
1096 We can tie operand 0 with some operand that dies in this insn.
1097 First look for operands that are required to be in the same
1098 register as operand 0. If we find such, only try tying that
1099 operand or one that can be put into that operand if the
1100 operation is commutative. If we don't find an operand
1101 that is required to be in the same register as operand 0,
1102 we can tie with any operand.
1104 Subregs in place of regs are also ok.
1106 If tying is done, WIN is set nonzero. */
1108 if (insn_code_number >= 0
1109 #ifdef REGISTER_CONSTRAINTS
1110 && insn_n_operands[insn_code_number] > 1
1111 && insn_operand_constraint[insn_code_number][0][0] == '='
1112 && insn_operand_constraint[insn_code_number][0][1] != '&'
1114 && GET_CODE (PATTERN (insn)) == SET
1115 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1119 #ifdef REGISTER_CONSTRAINTS
1120 /* If non-negative, is an operand that must match operand 0. */
1121 int must_match_0 = -1;
1122 /* Counts number of alternatives that require a match with
1124 int n_matching_alts = 0;
1126 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1128 char *p = insn_operand_constraint[insn_code_number][i];
1129 int this_match = (requires_inout (p));
1131 n_matching_alts += this_match;
1132 if (this_match == insn_n_alternatives[insn_code_number])
1137 r0 = recog_operand[0];
1138 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1140 #ifdef REGISTER_CONSTRAINTS
1141 /* Skip this operand if we found an operand that
1142 must match operand 0 and this operand isn't it
1143 and can't be made to be it by commutativity. */
1145 if (must_match_0 >= 0 && i != must_match_0
1146 && ! (i == must_match_0 + 1
1147 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1148 && ! (i == must_match_0 - 1
1149 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1152 /* Likewise if each alternative has some operand that
1153 must match operand zero. In that case, skip any
1154 operand that doesn't list operand 0 since we know that
1155 the operand always conflicts with operand 0. We
1156 ignore commutatity in this case to keep things simple. */
1157 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1158 && (0 == requires_inout
1159 (insn_operand_constraint[insn_code_number][i])))
1163 r1 = recog_operand[i];
1165 /* If the operand is an address, find a register in it.
1166 There may be more than one register, but we only try one
1169 #ifdef REGISTER_CONSTRAINTS
1170 insn_operand_constraint[insn_code_number][i][0] == 'p'
1172 insn_operand_address_p[insn_code_number][i]
1175 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1178 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1180 /* We have two priorities for hard register preferences.
1181 If we have a move insn or an insn whose first input
1182 can only be in the same register as the output, give
1183 priority to an equivalence found from that insn. */
1185 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1186 #ifdef REGISTER_CONSTRAINTS
1187 || (r1 == recog_operand[i] && must_match_0 >= 0)
1191 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1192 win = combine_regs (r1, r0, may_save_copy,
1193 insn_number, insn, 0);
1200 /* Recognize an insn sequence with an ultimate result
1201 which can safely overlap one of the inputs.
1202 The sequence begins with a CLOBBER of its result,
1203 and ends with an insn that copies the result to itself
1204 and has a REG_EQUAL note for an equivalent formula.
1205 That note indicates what the inputs are.
1206 The result and the input can overlap if each insn in
1207 the sequence either doesn't mention the input
1208 or has a REG_NO_CONFLICT note to inhibit the conflict.
1210 We do the combining test at the CLOBBER so that the
1211 destination register won't have had a quantity number
1212 assigned, since that would prevent combining. */
1214 if (GET_CODE (PATTERN (insn)) == CLOBBER
1215 && (r0 = XEXP (PATTERN (insn), 0),
1216 GET_CODE (r0) == REG)
1217 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1218 && XEXP (link, 0) != 0
1219 && GET_CODE (XEXP (link, 0)) == INSN
1220 && (set = single_set (XEXP (link, 0))) != 0
1221 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1222 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1225 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1226 /* Check that we have such a sequence. */
1227 && no_conflict_p (insn, r0, r1))
1228 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1229 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1230 && (r1 = XEXP (XEXP (note, 0), 0),
1231 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1232 && no_conflict_p (insn, r0, r1))
1233 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1235 /* Here we care if the operation to be computed is
1237 else if ((GET_CODE (XEXP (note, 0)) == EQ
1238 || GET_CODE (XEXP (note, 0)) == NE
1239 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1240 && (r1 = XEXP (XEXP (note, 0), 1),
1241 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1242 && no_conflict_p (insn, r0, r1))
1243 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1245 /* If we did combine something, show the register number
1246 in question so that we know to ignore its death. */
1248 no_conflict_combined_regno = REGNO (r1);
1251 /* If registers were just tied, set COMBINED_REGNO
1252 to the number of the register used in this insn
1253 that was tied to the register set in this insn.
1254 This register's qty should not be "killed". */
1258 while (GET_CODE (r1) == SUBREG)
1259 r1 = SUBREG_REG (r1);
1260 combined_regno = REGNO (r1);
1263 /* Mark the death of everything that dies in this instruction,
1264 except for anything that was just combined. */
1266 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1267 if (REG_NOTE_KIND (link) == REG_DEAD
1268 && GET_CODE (XEXP (link, 0)) == REG
1269 && combined_regno != REGNO (XEXP (link, 0))
1270 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1271 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1272 wipe_dead_reg (XEXP (link, 0), 0);
1274 /* Allocate qty numbers for all registers local to this block
1275 that are born (set) in this instruction.
1276 A pseudo that already has a qty is not changed. */
1278 note_stores (PATTERN (insn), reg_is_set);
1280 /* If anything is set in this insn and then unused, mark it as dying
1281 after this insn, so it will conflict with our outputs. This
1282 can't match with something that combined, and it doesn't matter
1283 if it did. Do this after the calls to reg_is_set since these
1284 die after, not during, the current insn. */
1286 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1287 if (REG_NOTE_KIND (link) == REG_UNUSED
1288 && GET_CODE (XEXP (link, 0)) == REG)
1289 wipe_dead_reg (XEXP (link, 0), 1);
1291 /* Allocate quantities for any SCRATCH operands of this insn. */
1293 if (insn_code_number >= 0)
1294 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1295 if (GET_CODE (recog_operand[i]) == SCRATCH
1296 && scratches_allocated++ < scratch_list_length)
1297 alloc_qty_for_scratch (recog_operand[i], i, insn,
1298 insn_code_number, insn_number);
1300 /* If this is an insn that has a REG_RETVAL note pointing at a
1301 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1302 block, so clear any register number that combined within it. */
1303 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1304 && GET_CODE (XEXP (note, 0)) == INSN
1305 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1306 no_conflict_combined_regno = -1;
1309 /* Set the registers live after INSN_NUMBER. Note that we never
1310 record the registers live before the block's first insn, since no
1311 pseudos we care about are live before that insn. */
1313 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1314 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1316 if (insn == basic_block_end[b])
1319 insn = NEXT_INSN (insn);
1322 /* Now every register that is local to this basic block
1323 should have been given a quantity, or else -1 meaning ignore it.
1324 Every quantity should have a known birth and death.
1326 Order the qtys so we assign them registers in order of the
1327 number of suggested registers they need so we allocate those with
1328 the most restrictive needs first. */
1330 qty_order = (int *) alloca (next_qty * sizeof (int));
1331 for (i = 0; i < next_qty; i++)
1334 #define EXCHANGE(I1, I2) \
1335 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1340 /* Make qty_order[2] be the one to allocate last. */
1341 if (qty_sugg_compare (0, 1) > 0)
1343 if (qty_sugg_compare (1, 2) > 0)
1346 /* ... Fall through ... */
1348 /* Put the best one to allocate in qty_order[0]. */
1349 if (qty_sugg_compare (0, 1) > 0)
1352 /* ... Fall through ... */
1356 /* Nothing to do here. */
1360 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1363 /* Try to put each quantity in a suggested physical register, if it has one.
1364 This may cause registers to be allocated that otherwise wouldn't be, but
1365 this seems acceptable in local allocation (unlike global allocation). */
1366 for (i = 0; i < next_qty; i++)
1369 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1370 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1371 0, 1, qty_birth[q], qty_death[q]);
1373 qty_phys_reg[q] = -1;
1376 /* Order the qtys so we assign them registers in order of
1377 decreasing length of life. Normally call qsort, but if we
1378 have only a very small number of quantities, sort them ourselves. */
1380 for (i = 0; i < next_qty; i++)
1383 #define EXCHANGE(I1, I2) \
1384 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1389 /* Make qty_order[2] be the one to allocate last. */
1390 if (qty_compare (0, 1) > 0)
1392 if (qty_compare (1, 2) > 0)
1395 /* ... Fall through ... */
1397 /* Put the best one to allocate in qty_order[0]. */
1398 if (qty_compare (0, 1) > 0)
1401 /* ... Fall through ... */
1405 /* Nothing to do here. */
1409 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1412 /* Now for each qty that is not a hardware register,
1413 look for a hardware register to put it in.
1414 First try the register class that is cheapest for this qty,
1415 if there is more than one class. */
1417 for (i = 0; i < next_qty; i++)
1420 if (qty_phys_reg[q] < 0)
1422 if (N_REG_CLASSES > 1)
1424 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1425 qty_mode[q], q, 0, 0,
1426 qty_birth[q], qty_death[q]);
1427 if (qty_phys_reg[q] >= 0)
1431 if (qty_alternate_class[q] != NO_REGS)
1432 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1433 qty_mode[q], q, 0, 0,
1434 qty_birth[q], qty_death[q]);
1438 /* Now propagate the register assignments
1439 to the pseudo regs belonging to the qtys. */
1441 for (q = 0; q < next_qty; q++)
1442 if (qty_phys_reg[q] >= 0)
1444 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1445 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1446 if (qty_scratch_rtx[q])
1448 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1450 qty_scratch_rtx[q] = gen_rtx_REG (GET_MODE (qty_scratch_rtx[q]),
1452 scratch_block[scratch_index] = b;
1453 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1459 /* Compare two quantities' priority for getting real registers.
1460 We give shorter-lived quantities higher priority.
1461 Quantities with more references are also preferred, as are quantities that
1462 require multiple registers. This is the identical prioritization as
1463 done by global-alloc.
1465 We used to give preference to registers with *longer* lives, but using
1466 the same algorithm in both local- and global-alloc can speed up execution
1467 of some programs by as much as a factor of three! */
1469 /* Note that the quotient will never be bigger than
1470 the value of floor_log2 times the maximum number of
1471 times a register can occur in one insn (surely less than 100).
1472 Multiplying this by 10000 can't overflow.
1473 QTY_CMP_PRI is also used by qty_sugg_compare. */
1475 #define QTY_CMP_PRI(q) \
1476 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1477 / (qty_death[q] - qty_birth[q])) * 10000))
1480 qty_compare (q1, q2)
1483 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1487 qty_compare_1 (q1p, q2p)
1488 const GENERIC_PTR q1p;
1489 const GENERIC_PTR q2p;
1491 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1492 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1497 /* If qtys are equally good, sort by qty number,
1498 so that the results of qsort leave nothing to chance. */
1502 /* Compare two quantities' priority for getting real registers. This version
1503 is called for quantities that have suggested hard registers. First priority
1504 goes to quantities that have copy preferences, then to those that have
1505 normal preferences. Within those groups, quantities with the lower
1506 number of preferences have the highest priority. Of those, we use the same
1507 algorithm as above. */
1509 #define QTY_CMP_SUGG(q) \
1510 (qty_phys_num_copy_sugg[q] \
1511 ? qty_phys_num_copy_sugg[q] \
1512 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1515 qty_sugg_compare (q1, q2)
1518 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1523 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1527 qty_sugg_compare_1 (q1p, q2p)
1528 const GENERIC_PTR q1p;
1529 const GENERIC_PTR q2p;
1531 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1532 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1537 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1541 /* If qtys are equally good, sort by qty number,
1542 so that the results of qsort leave nothing to chance. */
1549 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1550 Returns 1 if have done so, or 0 if cannot.
1552 Combining registers means marking them as having the same quantity
1553 and adjusting the offsets within the quantity if either of
1556 We don't actually combine a hard reg with a pseudo; instead
1557 we just record the hard reg as the suggestion for the pseudo's quantity.
1558 If we really combined them, we could lose if the pseudo lives
1559 across an insn that clobbers the hard reg (eg, movstr).
1561 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1562 there is no REG_DEAD note on INSN. This occurs during the processing
1563 of REG_NO_CONFLICT blocks.
1565 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1566 SETREG or if the input and output must share a register.
1567 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1569 There are elaborate checks for the validity of combining. */
1573 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1574 rtx usedreg, setreg;
1580 register int ureg, sreg;
1581 register int offset = 0;
1585 /* Determine the numbers and sizes of registers being used. If a subreg
1586 is present that does not change the entire register, don't consider
1587 this a copy insn. */
1589 while (GET_CODE (usedreg) == SUBREG)
1591 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1593 offset += SUBREG_WORD (usedreg);
1594 usedreg = SUBREG_REG (usedreg);
1596 if (GET_CODE (usedreg) != REG)
1598 ureg = REGNO (usedreg);
1599 usize = REG_SIZE (usedreg);
1601 while (GET_CODE (setreg) == SUBREG)
1603 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1605 offset -= SUBREG_WORD (setreg);
1606 setreg = SUBREG_REG (setreg);
1608 if (GET_CODE (setreg) != REG)
1610 sreg = REGNO (setreg);
1611 ssize = REG_SIZE (setreg);
1613 /* If UREG is a pseudo-register that hasn't already been assigned a
1614 quantity number, it means that it is not local to this block or dies
1615 more than once. In either event, we can't do anything with it. */
1616 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1617 /* Do not combine registers unless one fits within the other. */
1618 || (offset > 0 && usize + offset > ssize)
1619 || (offset < 0 && usize + offset < ssize)
1620 /* Do not combine with a smaller already-assigned object
1621 if that smaller object is already combined with something bigger. */
1622 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1623 && usize < qty_size[reg_qty[ureg]])
1624 /* Can't combine if SREG is not a register we can allocate. */
1625 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1626 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1627 These have already been taken care of. This probably wouldn't
1628 combine anyway, but don't take any chances. */
1629 || (ureg >= FIRST_PSEUDO_REGISTER
1630 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1631 /* Don't tie something to itself. In most cases it would make no
1632 difference, but it would screw up if the reg being tied to itself
1633 also dies in this insn. */
1635 /* Don't try to connect two different hardware registers. */
1636 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1637 /* Don't connect two different machine modes if they have different
1638 implications as to which registers may be used. */
1639 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1642 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1643 qty_phys_sugg for the pseudo instead of tying them.
1645 Return "failure" so that the lifespan of UREG is terminated here;
1646 that way the two lifespans will be disjoint and nothing will prevent
1647 the pseudo reg from being given this hard reg. */
1649 if (ureg < FIRST_PSEUDO_REGISTER)
1651 /* Allocate a quantity number so we have a place to put our
1653 if (reg_qty[sreg] == -2)
1654 reg_is_born (setreg, 2 * insn_number);
1656 if (reg_qty[sreg] >= 0)
1659 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1661 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1662 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1664 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1666 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1667 qty_phys_num_sugg[reg_qty[sreg]]++;
1673 /* Similarly for SREG a hard register and UREG a pseudo register. */
1675 if (sreg < FIRST_PSEUDO_REGISTER)
1678 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1680 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1681 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1683 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1685 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1686 qty_phys_num_sugg[reg_qty[ureg]]++;
1691 /* At this point we know that SREG and UREG are both pseudos.
1692 Do nothing if SREG already has a quantity or is a register that we
1694 if (reg_qty[sreg] >= -1
1695 /* If we are not going to let any regs live across calls,
1696 don't tie a call-crossing reg to a non-call-crossing reg. */
1697 || (current_function_has_nonlocal_label
1698 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1699 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1702 /* We don't already know about SREG, so tie it to UREG
1703 if this is the last use of UREG, provided the classes they want
1706 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1707 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1709 /* Add SREG to UREG's quantity. */
1710 sqty = reg_qty[ureg];
1711 reg_qty[sreg] = sqty;
1712 reg_offset[sreg] = reg_offset[ureg] + offset;
1713 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1714 qty_first_reg[sqty] = sreg;
1716 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1717 update_qty_class (sqty, sreg);
1719 /* Update info about quantity SQTY. */
1720 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1721 qty_n_refs[sqty] += REG_N_REFS (sreg);
1726 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1727 reg_offset[i] -= offset;
1729 qty_size[sqty] = ssize;
1730 qty_mode[sqty] = GET_MODE (setreg);
1739 /* Return 1 if the preferred class of REG allows it to be tied
1740 to a quantity or register whose class is CLASS.
1741 True if REG's reg class either contains or is contained in CLASS. */
1744 reg_meets_class_p (reg, class)
1746 enum reg_class class;
1748 register enum reg_class rclass = reg_preferred_class (reg);
1749 return (reg_class_subset_p (rclass, class)
1750 || reg_class_subset_p (class, rclass));
1753 /* Return 1 if the two specified classes have registers in common.
1754 If CALL_SAVED, then consider only call-saved registers. */
1757 reg_classes_overlap_p (c1, c2, call_saved)
1758 register enum reg_class c1;
1759 register enum reg_class c2;
1765 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1766 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1768 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1769 if (TEST_HARD_REG_BIT (c, i)
1770 && (! call_saved || ! call_used_regs[i]))
1776 /* Update the class of QTY assuming that REG is being tied to it. */
1779 update_qty_class (qty, reg)
1783 enum reg_class rclass = reg_preferred_class (reg);
1784 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1785 qty_min_class[qty] = rclass;
1787 rclass = reg_alternate_class (reg);
1788 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1789 qty_alternate_class[qty] = rclass;
1791 if (REG_CHANGES_SIZE (reg))
1792 qty_changes_size[qty] = 1;
1795 /* Handle something which alters the value of an rtx REG.
1797 REG is whatever is set or clobbered. SETTER is the rtx that
1798 is modifying the register.
1800 If it is not really a register, we do nothing.
1801 The file-global variables `this_insn' and `this_insn_number'
1802 carry info from `block_alloc'. */
1805 reg_is_set (reg, setter)
1809 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1810 a hard register. These may actually not exist any more. */
1812 if (GET_CODE (reg) != SUBREG
1813 && GET_CODE (reg) != REG)
1816 /* Mark this register as being born. If it is used in a CLOBBER, mark
1817 it as being born halfway between the previous insn and this insn so that
1818 it conflicts with our inputs but not the outputs of the previous insn. */
1820 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1823 /* Handle beginning of the life of register REG.
1824 BIRTH is the index at which this is happening. */
1827 reg_is_born (reg, birth)
1833 if (GET_CODE (reg) == SUBREG)
1834 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1836 regno = REGNO (reg);
1838 if (regno < FIRST_PSEUDO_REGISTER)
1840 mark_life (regno, GET_MODE (reg), 1);
1842 /* If the register was to have been born earlier that the present
1843 insn, mark it as live where it is actually born. */
1844 if (birth < 2 * this_insn_number)
1845 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1849 if (reg_qty[regno] == -2)
1850 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1852 /* If this register has a quantity number, show that it isn't dead. */
1853 if (reg_qty[regno] >= 0)
1854 qty_death[reg_qty[regno]] = -1;
1858 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1859 REG is an output that is dying (i.e., it is never used), otherwise it
1860 is an input (the normal case).
1861 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1864 wipe_dead_reg (reg, output_p)
1868 register int regno = REGNO (reg);
1870 /* If this insn has multiple results,
1871 and the dead reg is used in one of the results,
1872 extend its life to after this insn,
1873 so it won't get allocated together with any other result of this insn. */
1874 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1875 && !single_set (this_insn))
1878 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1880 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1881 if (GET_CODE (set) == SET
1882 && GET_CODE (SET_DEST (set)) != REG
1883 && !rtx_equal_p (reg, SET_DEST (set))
1884 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1889 /* If this register is used in an auto-increment address, then extend its
1890 life to after this insn, so that it won't get allocated together with
1891 the result of this insn. */
1892 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1895 if (regno < FIRST_PSEUDO_REGISTER)
1897 mark_life (regno, GET_MODE (reg), 0);
1899 /* If a hard register is dying as an output, mark it as in use at
1900 the beginning of this insn (the above statement would cause this
1903 post_mark_life (regno, GET_MODE (reg), 1,
1904 2 * this_insn_number, 2 * this_insn_number+ 1);
1907 else if (reg_qty[regno] >= 0)
1908 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1911 /* Find a block of SIZE words of hard regs in reg_class CLASS
1912 that can hold something of machine-mode MODE
1913 (but actually we test only the first of the block for holding MODE)
1914 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1915 and return the number of the first of them.
1916 Return -1 if such a block cannot be found.
1917 If QTY crosses calls, insist on a register preserved by calls,
1918 unless ACCEPT_CALL_CLOBBERED is nonzero.
1920 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1921 register is available. If not, return -1. */
1924 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1925 born_index, dead_index)
1926 enum reg_class class;
1927 enum machine_mode mode;
1929 int accept_call_clobbered;
1930 int just_try_suggested;
1931 int born_index, dead_index;
1933 register int i, ins;
1935 register /* Declare it register if it's a scalar. */
1937 HARD_REG_SET used, first_used;
1938 #ifdef ELIMINABLE_REGS
1939 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1942 /* Validate our parameters. */
1943 if (born_index < 0 || born_index > dead_index)
1946 /* Don't let a pseudo live in a reg across a function call
1947 if we might get a nonlocal goto. */
1948 if (current_function_has_nonlocal_label
1949 && qty_n_calls_crossed[qty] > 0)
1952 if (accept_call_clobbered)
1953 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1954 else if (qty_n_calls_crossed[qty] == 0)
1955 COPY_HARD_REG_SET (used, fixed_reg_set);
1957 COPY_HARD_REG_SET (used, call_used_reg_set);
1959 if (accept_call_clobbered)
1960 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1962 for (ins = born_index; ins < dead_index; ins++)
1963 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1965 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1967 /* Don't use the frame pointer reg in local-alloc even if
1968 we may omit the frame pointer, because if we do that and then we
1969 need a frame pointer, reload won't know how to move the pseudo
1970 to another hard reg. It can move only regs made by global-alloc.
1972 This is true of any register that can be eliminated. */
1973 #ifdef ELIMINABLE_REGS
1974 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
1975 SET_HARD_REG_BIT (used, eliminables[i].from);
1976 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1977 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1978 that it might be eliminated into. */
1979 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1982 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1985 #ifdef CLASS_CANNOT_CHANGE_SIZE
1986 if (qty_changes_size[qty])
1987 IOR_HARD_REG_SET (used,
1988 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
1991 /* Normally, the registers that can be used for the first register in
1992 a multi-register quantity are the same as those that can be used for
1993 subsequent registers. However, if just trying suggested registers,
1994 restrict our consideration to them. If there are copy-suggested
1995 register, try them. Otherwise, try the arithmetic-suggested
1997 COPY_HARD_REG_SET (first_used, used);
1999 if (just_try_suggested)
2001 if (qty_phys_num_copy_sugg[qty] != 0)
2002 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2004 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2007 /* If all registers are excluded, we can't do anything. */
2008 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2010 /* If at least one would be suitable, test each hard reg. */
2012 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2014 #ifdef REG_ALLOC_ORDER
2015 int regno = reg_alloc_order[i];
2019 if (! TEST_HARD_REG_BIT (first_used, regno)
2020 && HARD_REGNO_MODE_OK (regno, mode))
2023 register int size1 = HARD_REGNO_NREGS (regno, mode);
2024 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2027 /* Mark that this register is in use between its birth and death
2029 post_mark_life (regno, mode, 1, born_index, dead_index);
2032 #ifndef REG_ALLOC_ORDER
2033 i += j; /* Skip starting points we know will lose */
2040 /* If we are just trying suggested register, we have just tried copy-
2041 suggested registers, and there are arithmetic-suggested registers,
2044 /* If it would be profitable to allocate a call-clobbered register
2045 and save and restore it around calls, do that. */
2046 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2047 && qty_phys_num_sugg[qty] != 0)
2049 /* Don't try the copy-suggested regs again. */
2050 qty_phys_num_copy_sugg[qty] = 0;
2051 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2052 born_index, dead_index);
2055 /* We need not check to see if the current function has nonlocal
2056 labels because we don't put any pseudos that are live over calls in
2057 registers in that case. */
2059 if (! accept_call_clobbered
2060 && flag_caller_saves
2061 && ! just_try_suggested
2062 && qty_n_calls_crossed[qty] != 0
2063 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2065 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2067 caller_save_needed = 1;
2073 /* Mark that REGNO with machine-mode MODE is live starting from the current
2074 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2078 mark_life (regno, mode, life)
2080 enum machine_mode mode;
2083 register int j = HARD_REGNO_NREGS (regno, mode);
2086 SET_HARD_REG_BIT (regs_live, regno + j);
2089 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2092 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2093 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2094 to insn number DEATH (exclusive). */
2097 post_mark_life (regno, mode, life, birth, death)
2099 enum machine_mode mode;
2100 int life, birth, death;
2102 register int j = HARD_REGNO_NREGS (regno, mode);
2104 register /* Declare it register if it's a scalar. */
2106 HARD_REG_SET this_reg;
2108 CLEAR_HARD_REG_SET (this_reg);
2110 SET_HARD_REG_BIT (this_reg, regno + j);
2113 while (birth < death)
2115 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2119 while (birth < death)
2121 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2126 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2127 is the register being clobbered, and R1 is a register being used in
2128 the equivalent expression.
2130 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2131 in which it is used, return 1.
2133 Otherwise, return 0. */
2136 no_conflict_p (insn, r0, r1)
2140 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2143 /* If R1 is a hard register, return 0 since we handle this case
2144 when we scan the insns that actually use it. */
2147 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2148 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2149 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2152 last = XEXP (note, 0);
2154 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2155 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2157 if (find_reg_note (p, REG_DEAD, r1))
2160 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2161 some earlier optimization pass has inserted instructions into
2162 the sequence, and it is not safe to perform this optimization.
2163 Note that emit_no_conflict_block always ensures that this is
2164 true when these sequences are created. */
2165 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2172 #ifdef REGISTER_CONSTRAINTS
2174 /* Return the number of alternatives for which the constraint string P
2175 indicates that the operand must be equal to operand 0 and that no register
2184 int reg_allowed = 0;
2185 int num_matching_alts = 0;
2190 case '=': case '+': case '?':
2191 case '#': case '&': case '!':
2193 case '1': case '2': case '3': case '4':
2194 case 'm': case '<': case '>': case 'V': case 'o':
2195 case 'E': case 'F': case 'G': case 'H':
2196 case 's': case 'i': case 'n':
2197 case 'I': case 'J': case 'K': case 'L':
2198 case 'M': case 'N': case 'O': case 'P':
2199 #ifdef EXTRA_CONSTRAINT
2200 case 'Q': case 'R': case 'S': case 'T': case 'U':
2203 /* These don't say anything we care about. */
2207 if (found_zero && ! reg_allowed)
2208 num_matching_alts++;
2210 found_zero = reg_allowed = 0;
2224 if (found_zero && ! reg_allowed)
2225 num_matching_alts++;
2227 return num_matching_alts;
2229 #endif /* REGISTER_CONSTRAINTS */
2232 dump_local_alloc (file)
2236 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2237 if (reg_renumber[i] != -1)
2238 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
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