1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Allocation of hard register numbers to pseudo registers is done in
22 two passes. In this pass we consider only regs that are born and
23 die once within one basic block. We do this one basic block at a
24 time. Then the next pass allocates the registers that remain.
25 Two passes are used because this pass uses methods that work only
26 on linear code, but that do a better job than the general methods
27 used in global_alloc, and more quickly too.
29 The assignments made are recorded in the vector reg_renumber
30 whose space is allocated here. The rtl code itself is not altered.
32 We assign each instruction in the basic block a number
33 which is its order from the beginning of the block.
34 Then we can represent the lifetime of a pseudo register with
35 a pair of numbers, and check for conflicts easily.
36 We can record the availability of hard registers with a
37 HARD_REG_SET for each instruction. The HARD_REG_SET
38 contains 0 or 1 for each hard reg.
40 To avoid register shuffling, we tie registers together when one
41 dies by being copied into another, or dies in an instruction that
42 does arithmetic to produce another. The tied registers are
43 allocated as one. Registers with different reg class preferences
44 can never be tied unless the class preferred by one is a subclass
45 of the one preferred by the other.
47 Tying is represented with "quantity numbers".
48 A non-tied register is given a new quantity number.
49 Tied registers have the same quantity number.
51 We have provision to exempt registers, even when they are contained
52 within the block, that can be tied to others that are not contained in it.
53 This is so that global_alloc could process them both and tie them then.
54 But this is currently disabled since tying in global_alloc is not
61 #include "basic-block.h"
63 #include "hard-reg-set.h"
64 #include "insn-config.h"
68 /* Pseudos allocated here cannot be reallocated by global.c if the hard
69 register is used as a spill register. So we don't allocate such pseudos
70 here if their preferred class is likely to be used by spills.
72 On most machines, the appropriate test is if the class has one
73 register, so we default to that. */
75 #ifndef CLASS_LIKELY_SPILLED_P
76 #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1)
79 /* Next quantity number available for allocation. */
83 /* In all the following vectors indexed by quantity number. */
85 /* Element Q is the hard reg number chosen for quantity Q,
86 or -1 if none was found. */
88 static short *qty_phys_reg;
90 /* We maintain two hard register sets that indicate suggested hard registers
91 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
92 that are tied to the quantity by a simple copy. The second contains all
93 hard registers that are tied to the quantity via an arithmetic operation.
95 The former register set is given priority for allocation. This tends to
96 eliminate copy insns. */
98 /* Element Q is a set of hard registers that are suggested for quantity Q by
101 static HARD_REG_SET *qty_phys_copy_sugg;
103 /* Element Q is a set of hard registers that are suggested for quantity Q by
106 static HARD_REG_SET *qty_phys_sugg;
108 /* Element Q is non-zero if there is a suggested register in
109 qty_phys_copy_sugg. */
111 static char *qty_phys_has_copy_sugg;
113 /* Element Q is non-zero if there is a suggested register in qty_phys_sugg. */
115 static char *qty_phys_has_sugg;
117 /* Element Q is the number of refs to quantity Q. */
119 static int *qty_n_refs;
121 /* Element Q is a reg class contained in (smaller than) the
122 preferred classes of all the pseudo regs that are tied in quantity Q.
123 This is the preferred class for allocating that quantity. */
125 static enum reg_class *qty_min_class;
127 /* Insn number (counting from head of basic block)
128 where quantity Q was born. -1 if birth has not been recorded. */
130 static int *qty_birth;
132 /* Insn number (counting from head of basic block)
133 where quantity Q died. Due to the way tying is done,
134 and the fact that we consider in this pass only regs that die but once,
135 a quantity can die only once. Each quantity's life span
136 is a set of consecutive insns. -1 if death has not been recorded. */
138 static int *qty_death;
140 /* Number of words needed to hold the data in quantity Q.
141 This depends on its machine mode. It is used for these purposes:
142 1. It is used in computing the relative importances of qtys,
143 which determines the order in which we look for regs for them.
144 2. It is used in rules that prevent tying several registers of
145 different sizes in a way that is geometrically impossible
146 (see combine_regs). */
148 static int *qty_size;
150 /* This holds the mode of the registers that are tied to qty Q,
151 or VOIDmode if registers with differing modes are tied together. */
153 static enum machine_mode *qty_mode;
155 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
157 static int *qty_n_calls_crossed;
159 /* Register class within which we allocate qty Q if we can't get
160 its preferred class. */
162 static enum reg_class *qty_alternate_class;
164 /* Element Q is the SCRATCH expression for which this quantity is being
165 allocated or 0 if this quantity is allocating registers. */
167 static rtx *qty_scratch_rtx;
169 /* Element Q is the register number of one pseudo register whose
170 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
171 register should be the head of the chain maintained in reg_next_in_qty. */
173 static int *qty_first_reg;
175 /* If (REG N) has been assigned a quantity number, is a register number
176 of another register assigned the same quantity number, or -1 for the
177 end of the chain. qty_first_reg point to the head of this chain. */
179 static int *reg_next_in_qty;
181 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
183 of -1 if this register cannot be allocated by local-alloc,
184 or -2 if not known yet.
186 Note that if we see a use or death of pseudo register N with
187 reg_qty[N] == -2, register N must be local to the current block. If
188 it were used in more than one block, we would have reg_qty[N] == -1.
189 This relies on the fact that if reg_basic_block[N] is >= 0, register N
190 will not appear in any other block. We save a considerable number of
191 tests by exploiting this.
193 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
198 /* The offset (in words) of register N within its quantity.
199 This can be nonzero if register N is SImode, and has been tied
200 to a subreg of a DImode register. */
202 static char *reg_offset;
204 /* Vector of substitutions of register numbers,
205 used to map pseudo regs into hardware regs.
206 This is set up as a result of register allocation.
207 Element N is the hard reg assigned to pseudo reg N,
208 or is -1 if no hard reg was assigned.
209 If N is a hard reg number, element N is N. */
213 /* Set of hard registers live at the current point in the scan
214 of the instructions in a basic block. */
216 static HARD_REG_SET regs_live;
218 /* Each set of hard registers indicates registers live at a particular
219 point in the basic block. For N even, regs_live_at[N] says which
220 hard registers are needed *after* insn N/2 (i.e., they may not
221 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
223 If an object is to conflict with the inputs of insn J but not the
224 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
225 if it is to conflict with the outputs of insn J but not the inputs of
226 insn J + 1, it is said to die at index J*2 + 1. */
228 static HARD_REG_SET *regs_live_at;
232 int scratch_list_length;
233 static int scratch_index;
235 /* Communicate local vars `insn_number' and `insn'
236 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
237 static int this_insn_number;
238 static rtx this_insn;
240 static void block_alloc ();
241 static void update_equiv_regs ();
242 static int no_conflict_p ();
243 static int combine_regs ();
244 static void wipe_dead_reg ();
245 static int find_free_reg ();
246 static void reg_is_born ();
247 static void reg_is_set ();
248 static void mark_life ();
249 static void post_mark_life ();
250 static int qty_compare ();
251 static int qty_compare_1 ();
252 static int reg_meets_class_p ();
253 static void update_qty_class ();
254 static int requires_inout_p ();
256 /* Allocate a new quantity (new within current basic block)
257 for register number REGNO which is born at index BIRTH
258 within the block. MODE and SIZE are info on reg REGNO. */
261 alloc_qty (regno, mode, size, birth)
263 enum machine_mode mode;
266 register int qty = next_qty++;
268 reg_qty[regno] = qty;
269 reg_offset[regno] = 0;
270 reg_next_in_qty[regno] = -1;
272 qty_first_reg[qty] = regno;
273 qty_size[qty] = size;
274 qty_mode[qty] = mode;
275 qty_birth[qty] = birth;
276 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
277 qty_min_class[qty] = reg_preferred_class (regno);
278 qty_alternate_class[qty] = reg_alternate_class (regno);
279 qty_n_refs[qty] = reg_n_refs[regno];
282 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
283 used as operand N in INSN. We assume here that the SCRATCH is used in
287 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
291 int insn_code_num, insn_number;
294 enum reg_class class;
298 #ifdef REGISTER_CONSTRAINTS
299 /* If we haven't yet computed which alternative will be used, do so now.
300 Then set P to the constraints for that alternative. */
301 if (which_alternative == -1)
302 if (! constrain_operands (insn_code_num, 0))
305 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
306 *p && i < which_alternative; p++)
310 /* Compute the class required for this SCRATCH. If we don't need a
311 register, the class will remain NO_REGS. If we guessed the alternative
312 number incorrectly, reload will fix things up for us. */
315 while ((c = *p++) != '\0' && c != ',')
318 case '=': case '+': case '?':
319 case '#': case '&': case '!':
321 case '0': case '1': case '2': case '3': case '4':
322 case 'm': case '<': case '>': case 'V': case 'o':
323 case 'E': case 'F': case 'G': case 'H':
324 case 's': case 'i': case 'n':
325 case 'I': case 'J': case 'K': case 'L':
326 case 'M': case 'N': case 'O': case 'P':
327 #ifdef EXTRA_CONSTRAINT
328 case 'Q': case 'R': case 'S': case 'T': case 'U':
331 /* These don't say anything we care about. */
335 /* We don't need to allocate this SCRATCH. */
339 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
344 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
348 if (class == NO_REGS)
351 #else /* REGISTER_CONSTRAINTS */
353 class = GENERAL_REGS;
359 qty_first_reg[qty] = -1;
360 qty_scratch_rtx[qty] = scratch;
361 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
362 qty_mode[qty] = GET_MODE (scratch);
363 qty_birth[qty] = 2 * insn_number - 1;
364 qty_death[qty] = 2 * insn_number + 1;
365 qty_n_calls_crossed[qty] = 0;
366 qty_min_class[qty] = class;
367 qty_alternate_class[qty] = NO_REGS;
371 /* Main entry point of this file. */
379 /* Leaf functions and non-leaf functions have different needs.
380 If defined, let the machine say what kind of ordering we
382 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
383 ORDER_REGS_FOR_LOCAL_ALLOC;
386 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
388 update_equiv_regs ();
390 /* This sets the maximum number of quantities we can have. Quantity
391 numbers start at zero and we can have one for each pseudo plus the
392 number of SCRATCHes in the largest block, in the worst case. */
393 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
395 /* Allocate vectors of temporary data.
396 See the declarations of these variables, above,
397 for what they mean. */
399 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
400 Instead of allocating this much memory from now until the end of
401 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
402 reload will allocate them. */
404 scratch_list_length = max_qty;
405 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
406 bzero (scratch_list, scratch_list_length * sizeof (rtx));
407 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
408 bzero (scratch_block, scratch_list_length * sizeof (int));
411 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
412 qty_phys_copy_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
413 qty_phys_has_copy_sugg = (char *) alloca (max_qty * sizeof (char));
414 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
415 qty_phys_has_sugg = (char *) alloca (max_qty * sizeof (char));
416 qty_birth = (int *) alloca (max_qty * sizeof (int));
417 qty_death = (int *) alloca (max_qty * sizeof (int));
418 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
419 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
420 qty_size = (int *) alloca (max_qty * sizeof (int));
421 qty_mode = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
422 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
423 qty_min_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
424 qty_alternate_class = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
425 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
427 reg_qty = (int *) alloca (max_regno * sizeof (int));
428 reg_offset = (char *) alloca (max_regno * sizeof (char));
429 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
431 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
432 for (i = 0; i < max_regno; i++)
433 reg_renumber[i] = -1;
435 /* Determine which pseudo-registers can be allocated by local-alloc.
436 In general, these are the registers used only in a single block and
437 which only die once. However, if a register's preferred class has only
438 a few entries, don't allocate this register here unless it is preferred
439 or nothing since retry_global_alloc won't be able to move it to
440 GENERAL_REGS if a reload register of this class is needed.
442 We need not be concerned with which block actually uses the register
443 since we will never see it outside that block. */
445 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
447 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
448 && (reg_alternate_class (i) == NO_REGS
449 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
455 /* Force loop below to initialize entire quantity array. */
458 /* Allocate each block's local registers, block by block. */
460 for (b = 0; b < n_basic_blocks; b++)
462 /* NEXT_QTY indicates which elements of the `qty_...'
463 vectors might need to be initialized because they were used
464 for the previous block; it is set to the entire array before
465 block 0. Initialize those, with explicit loop if there are few,
466 else with bzero and bcopy. Do not initialize vectors that are
467 explicit set by `alloc_qty'. */
471 for (i = 0; i < next_qty; i++)
473 qty_scratch_rtx[i] = 0;
474 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
475 qty_phys_has_copy_sugg[i] = 0;
476 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
477 qty_phys_has_sugg[i] = 0;
482 #define CLEAR(vector) \
483 bzero ((vector), (sizeof (*(vector))) * next_qty);
485 CLEAR (qty_scratch_rtx);
486 CLEAR (qty_phys_copy_sugg);
487 CLEAR (qty_phys_has_copy_sugg);
488 CLEAR (qty_phys_sugg);
489 CLEAR (qty_phys_has_sugg);
501 /* Depth of loops we are in while in update_equiv_regs. */
502 static int loop_depth;
504 /* Used for communication between the following two functions: contains
505 a MEM that we wish to ensure remains unchanged. */
506 static rtx equiv_mem;
508 /* Set nonzero if EQUIV_MEM is modified. */
509 static int equiv_mem_modified;
511 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
512 Called via note_stores. */
515 validate_equiv_mem_from_store (dest, set)
519 if ((GET_CODE (dest) == REG
520 && reg_overlap_mentioned_p (dest, equiv_mem))
521 || (GET_CODE (dest) == MEM
522 && true_dependence (dest, equiv_mem)))
523 equiv_mem_modified = 1;
526 /* Verify that no store between START and the death of REG invalidates
527 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
528 by storing into an overlapping memory location, or with a non-const
531 Return 1 if MEMREF remains valid. */
534 validate_equiv_mem (start, reg, memref)
543 equiv_mem_modified = 0;
545 /* If the memory reference has side effects or is volatile, it isn't a
546 valid equivalence. */
547 if (side_effects_p (memref))
550 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
552 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
555 if (find_reg_note (insn, REG_DEAD, reg))
558 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
559 && ! CONST_CALL_P (insn))
562 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
564 /* If a register mentioned in MEMREF is modified via an
565 auto-increment, we lose the equivalence. Do the same if one
566 dies; although we could extend the life, it doesn't seem worth
569 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
570 if ((REG_NOTE_KIND (note) == REG_INC
571 || REG_NOTE_KIND (note) == REG_DEAD)
572 && GET_CODE (XEXP (note, 0)) == REG
573 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
580 /* TRUE if X references a memory location that would be affected by a store
584 memref_referenced_p (memref, x)
590 enum rtx_code code = GET_CODE (x);
607 if (true_dependence (memref, x))
612 /* If we are setting a MEM, it doesn't count (its address does), but any
613 other SET_DEST that has a MEM in it is referencing the MEM. */
614 if (GET_CODE (SET_DEST (x)) == MEM)
616 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
619 else if (memref_referenced_p (memref, SET_DEST (x)))
622 return memref_referenced_p (memref, SET_SRC (x));
625 fmt = GET_RTX_FORMAT (code);
626 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
630 if (memref_referenced_p (memref, XEXP (x, i)))
634 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
635 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
643 /* TRUE if some insn in the range (START, END] references a memory location
644 that would be affected by a store to MEMREF. */
647 memref_used_between_p (memref, start, end)
654 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
655 insn = NEXT_INSN (insn))
656 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
657 && memref_referenced_p (memref, PATTERN (insn)))
663 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
666 Search forward to see if SRC dies before either it or DEST is modified,
667 but don't scan past the end of a basic block. If so, we can replace SRC
668 with DEST and let SRC die in INSN.
670 This will reduce the number of registers live in that range and may enable
671 DEST to be tied to SRC, thus often saving one register in addition to a
672 register-register copy. */
675 optimize_reg_copy_1 (insn, dest, src)
683 int sregno = REGNO (src);
684 int dregno = REGNO (dest);
687 #ifdef SMALL_REGISTER_CLASSES
688 /* We don't want to mess with hard regs if register classes are small. */
689 || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER
691 /* We don't see all updates to SP if they are in an auto-inc memory
692 reference, so we must disallow this optimization on them. */
693 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
696 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
698 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
699 || (GET_CODE (p) == NOTE
700 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
701 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
704 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
707 if (reg_set_p (src, p) || reg_set_p (dest, p)
708 /* Don't change a USE of a register. */
709 || (GET_CODE (PATTERN (p)) == USE
710 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
713 /* See if all of SRC dies in P. This test is slightly more
714 conservative than it needs to be. */
715 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
716 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
724 /* We can do the optimization. Scan forward from INSN again,
725 replacing regs as we go. Set FAILED if a replacement can't
726 be done. In that case, we can't move the death note for SRC.
727 This should be rare. */
729 /* Set to stop at next insn. */
730 for (q = next_real_insn (insn);
731 q != next_real_insn (p);
732 q = next_real_insn (q))
734 if (reg_overlap_mentioned_p (src, PATTERN (q)))
736 /* If SRC is a hard register, we might miss some
737 overlapping registers with validate_replace_rtx,
738 so we would have to undo it. We can't if DEST is
739 present in the insn, so fail in that combination
741 if (sregno < FIRST_PSEUDO_REGISTER
742 && reg_mentioned_p (dest, PATTERN (q)))
745 /* Replace all uses and make sure that the register
746 isn't still present. */
747 else if (validate_replace_rtx (src, dest, q)
748 && (sregno >= FIRST_PSEUDO_REGISTER
749 || ! reg_overlap_mentioned_p (src,
752 /* We assume that a register is used exactly once per
753 insn in the updates below. If this is not correct,
754 no great harm is done. */
755 if (sregno >= FIRST_PSEUDO_REGISTER)
756 reg_n_refs[sregno] -= loop_depth;
757 if (dregno >= FIRST_PSEUDO_REGISTER)
758 reg_n_refs[dregno] += loop_depth;
762 validate_replace_rtx (dest, src, q);
767 /* Count the insns and CALL_INSNs passed. If we passed the
768 death note of DEST, show increased live length. */
773 /* If the insn in which SRC dies is a CALL_INSN, don't count it
774 as a call that has been crossed. Otherwise, count it. */
775 if (q != p && GET_CODE (q) == CALL_INSN)
782 /* If DEST dies here, remove the death note and save it for
783 later. Make sure ALL of DEST dies here; again, this is
784 overly conservative. */
786 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
787 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
788 remove_note (q, dest_death);
793 if (sregno >= FIRST_PSEUDO_REGISTER)
795 reg_live_length[sregno] -= length;
796 /* reg_live_length is only an approximation after combine
797 if sched is not run, so make sure that we still have
798 a reasonable value. */
799 if (reg_live_length[sregno] < 2)
800 reg_live_length[sregno] = 2;
801 reg_n_calls_crossed[sregno] -= n_calls;
804 if (dregno >= FIRST_PSEUDO_REGISTER)
806 reg_live_length[dregno] += d_length;
807 reg_n_calls_crossed[dregno] += d_n_calls;
810 /* Move death note of SRC from P to INSN. */
811 remove_note (p, note);
812 XEXP (note, 1) = REG_NOTES (insn);
813 REG_NOTES (insn) = note;
816 /* Put death note of DEST on P if we saw it die. */
819 XEXP (dest_death, 1) = REG_NOTES (p);
820 REG_NOTES (p) = dest_death;
826 /* If SRC is a hard register which is set or killed in some other
827 way, we can't do this optimization. */
828 else if (sregno < FIRST_PSEUDO_REGISTER
829 && dead_or_set_p (p, src))
834 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
835 a sequence of insns that modify DEST followed by an insn that sets
836 SRC to DEST in which DEST dies, with no prior modification of DEST.
837 (There is no need to check if the insns in between actually modify
838 DEST. We should not have cases where DEST is not modified, but
839 the optimization is safe if no such modification is detected.)
840 In that case, we can replace all uses of DEST, starting with INSN and
841 ending with the set of SRC to DEST, with SRC. We do not do this
842 optimization if a CALL_INSN is crossed unless SRC already crosses a
845 It is assumed that DEST and SRC are pseudos; it is too complicated to do
846 this for hard registers since the substitutions we may make might fail. */
849 optimize_reg_copy_2 (insn, dest, src)
856 int sregno = REGNO (src);
857 int dregno = REGNO (dest);
859 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
861 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
862 || (GET_CODE (p) == NOTE
863 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
864 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
867 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
870 set = single_set (p);
871 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
872 && find_reg_note (p, REG_DEAD, dest))
874 /* We can do the optimization. Scan forward from INSN again,
875 replacing regs as we go. */
877 /* Set to stop at next insn. */
878 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
879 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
881 if (reg_mentioned_p (dest, PATTERN (q)))
883 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
885 /* We assume that a register is used exactly once per
886 insn in the updates below. If this is not correct,
887 no great harm is done. */
888 reg_n_refs[dregno] -= loop_depth;
889 reg_n_refs[sregno] += loop_depth;
893 if (GET_CODE (q) == CALL_INSN)
895 reg_n_calls_crossed[dregno]--;
896 reg_n_calls_crossed[sregno]++;
900 remove_note (p, find_reg_note (p, REG_DEAD, dest));
901 reg_n_deaths[dregno]--;
902 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
903 reg_n_deaths[sregno]--;
907 if (reg_set_p (src, p)
908 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
913 /* Find registers that are equivalent to a single value throughout the
914 compilation (either because they can be referenced in memory or are set once
915 from a single constant). Lower their priority for a register.
917 If such a register is only referenced once, try substituting its value
918 into the using insn. If it succeeds, we can eliminate the register
924 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
925 rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
928 bzero (reg_equiv_init_insn, max_regno * sizeof (rtx *));
929 bzero (reg_equiv_replacement, max_regno * sizeof (rtx *));
931 init_alias_analysis ();
935 /* Scan the insns and find which registers have equivalences. Do this
936 in a separate scan of the insns because (due to -fcse-follow-jumps)
937 a register can be set below its use. */
938 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
941 rtx set = single_set (insn);
945 if (GET_CODE (insn) == NOTE)
947 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
949 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
953 /* If this insn contains more (or less) than a single SET, ignore it. */
957 dest = SET_DEST (set);
959 /* If this sets a MEM to the contents of a REG that is only used
960 in a single basic block, see if the register is always equivalent
961 to that memory location and if moving the store from INSN to the
962 insn that set REG is safe. If so, put a REG_EQUIV note on the
963 initializing insn. */
965 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
966 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
967 && reg_basic_block[regno] >= 0
968 && reg_equiv_init_insn[regno] != 0
969 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
971 && ! memref_used_between_p (SET_DEST (set),
972 reg_equiv_init_insn[regno], insn))
973 REG_NOTES (reg_equiv_init_insn[regno])
974 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
975 REG_NOTES (reg_equiv_init_insn[regno]));
977 /* If this is a register-register copy where SRC is not dead, see if we
979 if (flag_expensive_optimizations && GET_CODE (dest) == REG
980 && GET_CODE (SET_SRC (set)) == REG
981 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
982 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
984 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
985 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
986 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
987 && GET_CODE (SET_SRC (set)) == REG
988 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
989 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
990 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
992 /* Otherwise, we only handle the case of a pseudo register being set
994 if (GET_CODE (dest) != REG
995 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
996 || reg_n_sets[regno] != 1)
999 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1001 /* Record this insn as initializing this register. */
1002 reg_equiv_init_insn[regno] = insn;
1004 /* If this register is known to be equal to a constant, record that
1005 it is always equivalent to the constant. */
1006 if (note && CONSTANT_P (XEXP (note, 0)))
1007 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1009 /* If this insn introduces a "constant" register, decrease the priority
1010 of that register. Record this insn if the register is only used once
1011 more and the equivalence value is the same as our source.
1013 The latter condition is checked for two reasons: First, it is an
1014 indication that it may be more efficient to actually emit the insn
1015 as written (if no registers are available, reload will substitute
1016 the equivalence). Secondly, it avoids problems with any registers
1017 dying in this insn whose death notes would be missed.
1019 If we don't have a REG_EQUIV note, see if this insn is loading
1020 a register used only in one basic block from a MEM. If so, and the
1021 MEM remains unchanged for the life of the register, add a REG_EQUIV
1024 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1026 if (note == 0 && reg_basic_block[regno] >= 0
1027 && GET_CODE (SET_SRC (set)) == MEM
1028 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1029 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1032 /* Don't mess with things live during setjmp. */
1033 if (note && reg_live_length[regno] >= 0)
1035 int regno = REGNO (dest);
1037 /* Note that the statement below does not affect the priority
1039 reg_live_length[regno] *= 2;
1041 /* If the register is referenced exactly twice, meaning it is set
1042 once and used once, indicate that the reference may be replaced
1043 by the equivalence we computed above. If the register is only
1044 used in one basic block, this can't succeed or combine would
1047 It would be nice to use "loop_depth * 2" in the compare
1048 below. Unfortunately, LOOP_DEPTH need not be constant within
1049 a basic block so this would be too complicated.
1051 This case normally occurs when a parameter is read from memory
1052 and then used exactly once, not in a loop. */
1054 if (reg_n_refs[regno] == 2
1055 && reg_basic_block[regno] < 0
1056 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1057 reg_equiv_replacement[regno] = SET_SRC (set);
1061 /* Now scan all regs killed in an insn to see if any of them are registers
1062 only used that once. If so, see if we can replace the reference with
1063 the equivalent from. If we can, delete the initializing reference
1064 and this register will go away. */
1065 for (insn = next_active_insn (get_insns ());
1067 insn = next_active_insn (insn))
1071 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1072 if (REG_NOTE_KIND (link) == REG_DEAD
1073 /* Make sure this insn still refers to the register. */
1074 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1076 int regno = REGNO (XEXP (link, 0));
1078 if (reg_equiv_replacement[regno]
1079 && validate_replace_rtx (regno_reg_rtx[regno],
1080 reg_equiv_replacement[regno], insn))
1082 rtx equiv_insn = reg_equiv_init_insn[regno];
1084 remove_death (regno, insn);
1085 reg_n_refs[regno] = 0;
1086 PUT_CODE (equiv_insn, NOTE);
1087 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1088 NOTE_SOURCE_FILE (equiv_insn) = 0;
1094 /* Allocate hard regs to the pseudo regs used only within block number B.
1095 Only the pseudos that die but once can be handled. */
1104 int insn_number = 0;
1106 int max_uid = get_max_uid ();
1108 int no_conflict_combined_regno = -1;
1109 /* Counter to prevent allocating more SCRATCHes than can be stored
1111 int scratches_allocated = scratch_index;
1113 /* Count the instructions in the basic block. */
1115 insn = basic_block_end[b];
1118 if (GET_CODE (insn) != NOTE)
1119 if (++insn_count > max_uid)
1121 if (insn == basic_block_head[b])
1123 insn = PREV_INSN (insn);
1126 /* +2 to leave room for a post_mark_life at the last insn and for
1127 the birth of a CLOBBER in the first insn. */
1128 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1129 * sizeof (HARD_REG_SET));
1130 bzero (regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1132 /* Initialize table of hardware registers currently live. */
1135 regs_live = *basic_block_live_at_start[b];
1137 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1140 /* This loop scans the instructions of the basic block
1141 and assigns quantities to registers.
1142 It computes which registers to tie. */
1144 insn = basic_block_head[b];
1147 register rtx body = PATTERN (insn);
1149 if (GET_CODE (insn) != NOTE)
1152 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1154 register rtx link, set;
1155 register int win = 0;
1156 register rtx r0, r1;
1157 int combined_regno = -1;
1159 int insn_code_number = recog_memoized (insn);
1161 this_insn_number = insn_number;
1164 if (insn_code_number >= 0)
1165 insn_extract (insn);
1166 which_alternative = -1;
1168 /* Is this insn suitable for tying two registers?
1169 If so, try doing that.
1170 Suitable insns are those with at least two operands and where
1171 operand 0 is an output that is a register that is not
1174 We can tie operand 0 with some operand that dies in this insn.
1175 First look for operands that are required to be in the same
1176 register as operand 0. If we find such, only try tying that
1177 operand or one that can be put into that operand if the
1178 operation is commutative. If we don't find an operand
1179 that is required to be in the same register as operand 0,
1180 we can tie with any operand.
1182 Subregs in place of regs are also ok.
1184 If tying is done, WIN is set nonzero. */
1186 if (insn_code_number >= 0
1187 #ifdef REGISTER_CONSTRAINTS
1188 && insn_n_operands[insn_code_number] > 1
1189 && insn_operand_constraint[insn_code_number][0][0] == '='
1190 && insn_operand_constraint[insn_code_number][0][1] != '&'
1192 && GET_CODE (PATTERN (insn)) == SET
1193 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1197 #ifdef REGISTER_CONSTRAINTS
1198 int must_match_0 = -1;
1201 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1202 if (requires_inout_p
1203 (insn_operand_constraint[insn_code_number][i]))
1207 r0 = recog_operand[0];
1208 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1210 #ifdef REGISTER_CONSTRAINTS
1211 /* Skip this operand if we found an operand that
1212 must match operand 0 and this operand isn't it
1213 and can't be made to be it by commutativity. */
1215 if (must_match_0 >= 0 && i != must_match_0
1216 && ! (i == must_match_0 + 1
1217 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1218 && ! (i == must_match_0 - 1
1219 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1223 r1 = recog_operand[i];
1225 /* If the operand is an address, find a register in it.
1226 There may be more than one register, but we only try one
1229 #ifdef REGISTER_CONSTRAINTS
1230 insn_operand_constraint[insn_code_number][i][0] == 'p'
1232 insn_operand_address_p[insn_code_number][i]
1235 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1238 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1240 /* We have two priorities for hard register preferences.
1241 If we have a move insn or an insn whose first input
1242 can only be in the same register as the output, give
1243 priority to an equivalence found from that insn. */
1245 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1246 #ifdef REGISTER_CONSTRAINTS
1247 || (r1 == recog_operand[i] && must_match_0 >= 0)
1251 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1252 win = combine_regs (r1, r0, may_save_copy,
1253 insn_number, insn, 0);
1258 /* Recognize an insn sequence with an ultimate result
1259 which can safely overlap one of the inputs.
1260 The sequence begins with a CLOBBER of its result,
1261 and ends with an insn that copies the result to itself
1262 and has a REG_EQUAL note for an equivalent formula.
1263 That note indicates what the inputs are.
1264 The result and the input can overlap if each insn in
1265 the sequence either doesn't mention the input
1266 or has a REG_NO_CONFLICT note to inhibit the conflict.
1268 We do the combining test at the CLOBBER so that the
1269 destination register won't have had a quantity number
1270 assigned, since that would prevent combining. */
1272 if (GET_CODE (PATTERN (insn)) == CLOBBER
1273 && (r0 = XEXP (PATTERN (insn), 0),
1274 GET_CODE (r0) == REG)
1275 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1276 && XEXP (link, 0) != 0
1277 && GET_CODE (XEXP (link, 0)) == INSN
1278 && (set = single_set (XEXP (link, 0))) != 0
1279 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1280 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1283 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1284 /* Check that we have such a sequence. */
1285 && no_conflict_p (insn, r0, r1))
1286 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1287 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1288 && (r1 = XEXP (XEXP (note, 0), 0),
1289 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1290 && no_conflict_p (insn, r0, r1))
1291 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1293 /* Here we care if the operation to be computed is
1295 else if ((GET_CODE (XEXP (note, 0)) == EQ
1296 || GET_CODE (XEXP (note, 0)) == NE
1297 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1298 && (r1 = XEXP (XEXP (note, 0), 1),
1299 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1300 && no_conflict_p (insn, r0, r1))
1301 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1303 /* If we did combine something, show the register number
1304 in question so that we know to ignore its death. */
1306 no_conflict_combined_regno = REGNO (r1);
1309 /* If registers were just tied, set COMBINED_REGNO
1310 to the number of the register used in this insn
1311 that was tied to the register set in this insn.
1312 This register's qty should not be "killed". */
1316 while (GET_CODE (r1) == SUBREG)
1317 r1 = SUBREG_REG (r1);
1318 combined_regno = REGNO (r1);
1321 /* Mark the death of everything that dies in this instruction,
1322 except for anything that was just combined. */
1324 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1325 if (REG_NOTE_KIND (link) == REG_DEAD
1326 && GET_CODE (XEXP (link, 0)) == REG
1327 && combined_regno != REGNO (XEXP (link, 0))
1328 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1329 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1330 wipe_dead_reg (XEXP (link, 0), 0);
1332 /* Allocate qty numbers for all registers local to this block
1333 that are born (set) in this instruction.
1334 A pseudo that already has a qty is not changed. */
1336 note_stores (PATTERN (insn), reg_is_set);
1338 /* If anything is set in this insn and then unused, mark it as dying
1339 after this insn, so it will conflict with our outputs. This
1340 can't match with something that combined, and it doesn't matter
1341 if it did. Do this after the calls to reg_is_set since these
1342 die after, not during, the current insn. */
1344 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1345 if (REG_NOTE_KIND (link) == REG_UNUSED
1346 && GET_CODE (XEXP (link, 0)) == REG)
1347 wipe_dead_reg (XEXP (link, 0), 1);
1349 /* Allocate quantities for any SCRATCH operands of this insn. */
1351 if (insn_code_number >= 0)
1352 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1353 if (GET_CODE (recog_operand[i]) == SCRATCH
1354 && scratches_allocated++ < scratch_list_length)
1355 alloc_qty_for_scratch (recog_operand[i], i, insn,
1356 insn_code_number, insn_number);
1358 /* If this is an insn that has a REG_RETVAL note pointing at a
1359 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1360 block, so clear any register number that combined within it. */
1361 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1362 && GET_CODE (XEXP (note, 0)) == INSN
1363 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1364 no_conflict_combined_regno = -1;
1367 /* Set the registers live after INSN_NUMBER. Note that we never
1368 record the registers live before the block's first insn, since no
1369 pseudos we care about are live before that insn. */
1371 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1372 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1374 if (insn == basic_block_end[b])
1377 insn = NEXT_INSN (insn);
1380 /* Now every register that is local to this basic block
1381 should have been given a quantity, or else -1 meaning ignore it.
1382 Every quantity should have a known birth and death.
1384 Order the qtys so we assign them registers in order of
1385 decreasing length of life. Normally call qsort, but if we
1386 have only a very small number of quantities, sort them ourselves. */
1388 qty_order = (int *) alloca (next_qty * sizeof (int));
1389 for (i = 0; i < next_qty; i++)
1392 #define EXCHANGE(I1, I2) \
1393 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1398 /* Make qty_order[2] be the one to allocate last. */
1399 if (qty_compare (0, 1) > 0)
1401 if (qty_compare (1, 2) > 0)
1404 /* ... Fall through ... */
1406 /* Put the best one to allocate in qty_order[0]. */
1407 if (qty_compare (0, 1) > 0)
1410 /* ... Fall through ... */
1414 /* Nothing to do here. */
1418 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1421 /* Try to put each quantity in a suggested physical register, if it has one.
1422 This may cause registers to be allocated that otherwise wouldn't be, but
1423 this seems acceptable in local allocation (unlike global allocation). */
1424 for (i = 0; i < next_qty; i++)
1427 if (qty_phys_has_sugg[q] || qty_phys_has_copy_sugg[q])
1428 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1429 0, 1, qty_birth[q], qty_death[q]);
1431 qty_phys_reg[q] = -1;
1434 /* Now for each qty that is not a hardware register,
1435 look for a hardware register to put it in.
1436 First try the register class that is cheapest for this qty,
1437 if there is more than one class. */
1439 for (i = 0; i < next_qty; i++)
1442 if (qty_phys_reg[q] < 0)
1444 if (N_REG_CLASSES > 1)
1446 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1447 qty_mode[q], q, 0, 0,
1448 qty_birth[q], qty_death[q]);
1449 if (qty_phys_reg[q] >= 0)
1453 if (qty_alternate_class[q] != NO_REGS)
1454 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1455 qty_mode[q], q, 0, 0,
1456 qty_birth[q], qty_death[q]);
1460 /* Now propagate the register assignments
1461 to the pseudo regs belonging to the qtys. */
1463 for (q = 0; q < next_qty; q++)
1464 if (qty_phys_reg[q] >= 0)
1466 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1467 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1468 if (qty_scratch_rtx[q])
1470 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1472 PUT_CODE (qty_scratch_rtx[q], REG);
1473 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1475 scratch_block[scratch_index] = b;
1476 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1478 /* Must clear the USED field, because it will have been set by
1479 copy_rtx_if_shared, but the leaf_register code expects that
1480 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1481 used bit for REGs, but does for SCRATCHes. */
1482 qty_scratch_rtx[q]->used = 0;
1487 /* Compare two quantities' priority for getting real registers.
1488 We give shorter-lived quantities higher priority.
1489 Quantities with more references are also preferred, as are quantities that
1490 require multiple registers. This is the identical prioritization as
1491 done by global-alloc.
1493 We used to give preference to registers with *longer* lives, but using
1494 the same algorithm in both local- and global-alloc can speed up execution
1495 of some programs by as much as a factor of three! */
1498 qty_compare (q1, q2)
1501 /* Note that the quotient will never be bigger than
1502 the value of floor_log2 times the maximum number of
1503 times a register can occur in one insn (surely less than 100).
1504 Multiplying this by 10000 can't overflow. */
1506 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1])
1507 / ((qty_death[q1] - qty_birth[q1]) * qty_size[q1]))
1510 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2])
1511 / ((qty_death[q2] - qty_birth[q2]) * qty_size[q2]))
1517 qty_compare_1 (q1, q2)
1522 /* Note that the quotient will never be bigger than
1523 the value of floor_log2 times the maximum number of
1524 times a register can occur in one insn (surely less than 100).
1525 Multiplying this by 10000 can't overflow. */
1527 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1])
1528 / ((qty_death[*q1] - qty_birth[*q1]) * qty_size[*q1]))
1531 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2])
1532 / ((qty_death[*q2] - qty_birth[*q2]) * qty_size[*q2]))
1536 if (tem != 0) return tem;
1537 /* If qtys are equally good, sort by qty number,
1538 so that the results of qsort leave nothing to chance. */
1542 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1543 Returns 1 if have done so, or 0 if cannot.
1545 Combining registers means marking them as having the same quantity
1546 and adjusting the offsets within the quantity if either of
1549 We don't actually combine a hard reg with a pseudo; instead
1550 we just record the hard reg as the suggestion for the pseudo's quantity.
1551 If we really combined them, we could lose if the pseudo lives
1552 across an insn that clobbers the hard reg (eg, movstr).
1554 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1555 there is no REG_DEAD note on INSN. This occurs during the processing
1556 of REG_NO_CONFLICT blocks.
1558 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1559 SETREG or if the input and output must share a register.
1560 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1562 There are elaborate checks for the validity of combining. */
1566 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1567 rtx usedreg, setreg;
1573 register int ureg, sreg;
1574 register int offset = 0;
1578 /* Determine the numbers and sizes of registers being used. If a subreg
1579 is present that does not change the entire register, don't consider
1580 this a copy insn. */
1582 while (GET_CODE (usedreg) == SUBREG)
1584 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1586 offset += SUBREG_WORD (usedreg);
1587 usedreg = SUBREG_REG (usedreg);
1589 if (GET_CODE (usedreg) != REG)
1591 ureg = REGNO (usedreg);
1592 usize = REG_SIZE (usedreg);
1594 while (GET_CODE (setreg) == SUBREG)
1596 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1598 offset -= SUBREG_WORD (setreg);
1599 setreg = SUBREG_REG (setreg);
1601 if (GET_CODE (setreg) != REG)
1603 sreg = REGNO (setreg);
1604 ssize = REG_SIZE (setreg);
1606 /* If UREG is a pseudo-register that hasn't already been assigned a
1607 quantity number, it means that it is not local to this block or dies
1608 more than once. In either event, we can't do anything with it. */
1609 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1610 /* Do not combine registers unless one fits within the other. */
1611 || (offset > 0 && usize + offset > ssize)
1612 || (offset < 0 && usize + offset < ssize)
1613 /* Do not combine with a smaller already-assigned object
1614 if that smaller object is already combined with something bigger. */
1615 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1616 && usize < qty_size[reg_qty[ureg]])
1617 /* Can't combine if SREG is not a register we can allocate. */
1618 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1619 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1620 These have already been taken care of. This probably wouldn't
1621 combine anyway, but don't take any chances. */
1622 || (ureg >= FIRST_PSEUDO_REGISTER
1623 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1624 /* Don't tie something to itself. In most cases it would make no
1625 difference, but it would screw up if the reg being tied to itself
1626 also dies in this insn. */
1628 /* Don't try to connect two different hardware registers. */
1629 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1630 /* Don't connect two different machine modes if they have different
1631 implications as to which registers may be used. */
1632 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1635 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1636 qty_phys_sugg for the pseudo instead of tying them.
1638 Return "failure" so that the lifespan of UREG is terminated here;
1639 that way the two lifespans will be disjoint and nothing will prevent
1640 the pseudo reg from being given this hard reg. */
1642 if (ureg < FIRST_PSEUDO_REGISTER)
1644 /* Allocate a quantity number so we have a place to put our
1646 if (reg_qty[sreg] == -2)
1647 reg_is_born (setreg, 2 * insn_number);
1649 if (reg_qty[sreg] >= 0)
1653 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1654 qty_phys_has_copy_sugg[reg_qty[sreg]] = 1;
1658 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1659 qty_phys_has_sugg[reg_qty[sreg]] = 1;
1665 /* Similarly for SREG a hard register and UREG a pseudo register. */
1667 if (sreg < FIRST_PSEUDO_REGISTER)
1671 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1672 qty_phys_has_copy_sugg[reg_qty[ureg]] = 1;
1676 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1677 qty_phys_has_sugg[reg_qty[ureg]] = 1;
1682 /* At this point we know that SREG and UREG are both pseudos.
1683 Do nothing if SREG already has a quantity or is a register that we
1685 if (reg_qty[sreg] >= -1
1686 /* If we are not going to let any regs live across calls,
1687 don't tie a call-crossing reg to a non-call-crossing reg. */
1688 || (current_function_has_nonlocal_label
1689 && ((reg_n_calls_crossed[ureg] > 0)
1690 != (reg_n_calls_crossed[sreg] > 0))))
1693 /* We don't already know about SREG, so tie it to UREG
1694 if this is the last use of UREG, provided the classes they want
1697 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1698 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1700 /* Add SREG to UREG's quantity. */
1701 sqty = reg_qty[ureg];
1702 reg_qty[sreg] = sqty;
1703 reg_offset[sreg] = reg_offset[ureg] + offset;
1704 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1705 qty_first_reg[sqty] = sreg;
1707 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1708 update_qty_class (sqty, sreg);
1710 /* Update info about quantity SQTY. */
1711 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1712 qty_n_refs[sqty] += reg_n_refs[sreg];
1717 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1718 reg_offset[i] -= offset;
1720 qty_size[sqty] = ssize;
1721 qty_mode[sqty] = GET_MODE (setreg);
1730 /* Return 1 if the preferred class of REG allows it to be tied
1731 to a quantity or register whose class is CLASS.
1732 True if REG's reg class either contains or is contained in CLASS. */
1735 reg_meets_class_p (reg, class)
1737 enum reg_class class;
1739 register enum reg_class rclass = reg_preferred_class (reg);
1740 return (reg_class_subset_p (rclass, class)
1741 || reg_class_subset_p (class, rclass));
1744 /* Return 1 if the two specified classes have registers in common.
1745 If CALL_SAVED, then consider only call-saved registers. */
1748 reg_classes_overlap_p (c1, c2, call_saved)
1749 register enum reg_class c1;
1750 register enum reg_class c2;
1756 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1757 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1759 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1760 if (TEST_HARD_REG_BIT (c, i)
1761 && (! call_saved || ! call_used_regs[i]))
1767 /* Update the class of QTY assuming that REG is being tied to it. */
1770 update_qty_class (qty, reg)
1774 enum reg_class rclass = reg_preferred_class (reg);
1775 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1776 qty_min_class[qty] = rclass;
1778 rclass = reg_alternate_class (reg);
1779 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1780 qty_alternate_class[qty] = rclass;
1783 /* Handle something which alters the value of an rtx REG.
1785 REG is whatever is set or clobbered. SETTER is the rtx that
1786 is modifying the register.
1788 If it is not really a register, we do nothing.
1789 The file-global variables `this_insn' and `this_insn_number'
1790 carry info from `block_alloc'. */
1793 reg_is_set (reg, setter)
1797 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1798 a hard register. These may actually not exist any more. */
1800 if (GET_CODE (reg) != SUBREG
1801 && GET_CODE (reg) != REG)
1804 /* Mark this register as being born. If it is used in a CLOBBER, mark
1805 it as being born halfway between the previous insn and this insn so that
1806 it conflicts with our inputs but not the outputs of the previous insn. */
1808 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1811 /* Handle beginning of the life of register REG.
1812 BIRTH is the index at which this is happening. */
1815 reg_is_born (reg, birth)
1821 if (GET_CODE (reg) == SUBREG)
1822 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1824 regno = REGNO (reg);
1826 if (regno < FIRST_PSEUDO_REGISTER)
1828 mark_life (regno, GET_MODE (reg), 1);
1830 /* If the register was to have been born earlier that the present
1831 insn, mark it as live where it is actually born. */
1832 if (birth < 2 * this_insn_number)
1833 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1837 if (reg_qty[regno] == -2)
1838 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1840 /* If this register has a quantity number, show that it isn't dead. */
1841 if (reg_qty[regno] >= 0)
1842 qty_death[reg_qty[regno]] = -1;
1846 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1847 REG is an output that is dying (i.e., it is never used), otherwise it
1848 is an input (the normal case).
1849 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1852 wipe_dead_reg (reg, output_p)
1856 register int regno = REGNO (reg);
1858 /* If this insn has multiple results,
1859 and the dead reg is used in one of the results,
1860 extend its life to after this insn,
1861 so it won't get allocated together with any other result of this insn. */
1862 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1863 && !single_set (this_insn))
1866 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1868 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1869 if (GET_CODE (set) == SET
1870 && GET_CODE (SET_DEST (set)) != REG
1871 && !rtx_equal_p (reg, SET_DEST (set))
1872 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1877 if (regno < FIRST_PSEUDO_REGISTER)
1879 mark_life (regno, GET_MODE (reg), 0);
1881 /* If a hard register is dying as an output, mark it as in use at
1882 the beginning of this insn (the above statement would cause this
1885 post_mark_life (regno, GET_MODE (reg), 1,
1886 2 * this_insn_number, 2 * this_insn_number+ 1);
1889 else if (reg_qty[regno] >= 0)
1890 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1893 /* Find a block of SIZE words of hard regs in reg_class CLASS
1894 that can hold something of machine-mode MODE
1895 (but actually we test only the first of the block for holding MODE)
1896 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1897 and return the number of the first of them.
1898 Return -1 if such a block cannot be found.
1899 If QTY crosses calls, insist on a register preserved by calls,
1900 unless ACCEPT_CALL_CLOBBERED is nonzero.
1902 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1903 register is available. If not, return -1. */
1906 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1907 born_index, dead_index)
1908 enum reg_class class;
1909 enum machine_mode mode;
1910 int accept_call_clobbered;
1911 int just_try_suggested;
1913 int born_index, dead_index;
1915 register int i, ins;
1917 register /* Declare it register if it's a scalar. */
1919 HARD_REG_SET used, first_used;
1920 #ifdef ELIMINABLE_REGS
1921 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1924 /* Validate our parameters. */
1925 if (born_index < 0 || born_index > dead_index)
1928 /* Don't let a pseudo live in a reg across a function call
1929 if we might get a nonlocal goto. */
1930 if (current_function_has_nonlocal_label
1931 && qty_n_calls_crossed[qty] > 0)
1934 if (accept_call_clobbered)
1935 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1936 else if (qty_n_calls_crossed[qty] == 0)
1937 COPY_HARD_REG_SET (used, fixed_reg_set);
1939 COPY_HARD_REG_SET (used, call_used_reg_set);
1941 for (ins = born_index; ins < dead_index; ins++)
1942 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1944 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1946 /* Don't use the frame pointer reg in local-alloc even if
1947 we may omit the frame pointer, because if we do that and then we
1948 need a frame pointer, reload won't know how to move the pseudo
1949 to another hard reg. It can move only regs made by global-alloc.
1951 This is true of any register that can be eliminated. */
1952 #ifdef ELIMINABLE_REGS
1953 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
1954 SET_HARD_REG_BIT (used, eliminables[i].from);
1955 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1956 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1957 that it might be eliminated into. */
1958 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1961 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1964 /* Normally, the registers that can be used for the first register in
1965 a multi-register quantity are the same as those that can be used for
1966 subsequent registers. However, if just trying suggested registers,
1967 restrict our consideration to them. If there are copy-suggested
1968 register, try them. Otherwise, try the arithmetic-suggested
1970 COPY_HARD_REG_SET (first_used, used);
1972 if (just_try_suggested)
1974 if (qty_phys_has_copy_sugg[qty])
1975 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
1977 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
1980 /* If all registers are excluded, we can't do anything. */
1981 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
1983 /* If at least one would be suitable, test each hard reg. */
1985 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1987 #ifdef REG_ALLOC_ORDER
1988 int regno = reg_alloc_order[i];
1992 if (! TEST_HARD_REG_BIT (first_used, regno)
1993 && HARD_REGNO_MODE_OK (regno, mode))
1996 register int size1 = HARD_REGNO_NREGS (regno, mode);
1997 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2000 /* Mark that this register is in use between its birth and death
2002 post_mark_life (regno, mode, 1, born_index, dead_index);
2005 #ifndef REG_ALLOC_ORDER
2006 i += j; /* Skip starting points we know will lose */
2013 /* If we are just trying suggested register, we have just tried copy-
2014 suggested registers, and there are arithmetic-suggested registers,
2017 /* If it would be profitable to allocate a call-clobbered register
2018 and save and restore it around calls, do that. */
2019 if (just_try_suggested && qty_phys_has_copy_sugg[qty]
2020 && qty_phys_has_sugg[qty])
2022 /* Don't try the copy-suggested regs again. */
2023 qty_phys_has_copy_sugg[qty] = 0;
2024 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2025 born_index, dead_index);
2028 /* We need not check to see if the current function has nonlocal
2029 labels because we don't put any pseudos that are live over calls in
2030 registers in that case. */
2032 if (! accept_call_clobbered
2033 && flag_caller_saves
2034 && ! just_try_suggested
2035 && qty_n_calls_crossed[qty] != 0
2036 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2038 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2040 caller_save_needed = 1;
2046 /* Mark that REGNO with machine-mode MODE is live starting from the current
2047 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2051 mark_life (regno, mode, life)
2053 enum machine_mode mode;
2056 register int j = HARD_REGNO_NREGS (regno, mode);
2059 SET_HARD_REG_BIT (regs_live, regno + j);
2062 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2065 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2066 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2067 to insn number DEATH (exclusive). */
2070 post_mark_life (regno, mode, life, birth, death)
2071 register int regno, life, birth;
2072 enum machine_mode mode;
2075 register int j = HARD_REGNO_NREGS (regno, mode);
2077 register /* Declare it register if it's a scalar. */
2079 HARD_REG_SET this_reg;
2081 CLEAR_HARD_REG_SET (this_reg);
2083 SET_HARD_REG_BIT (this_reg, regno + j);
2086 while (birth < death)
2088 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2092 while (birth < death)
2094 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2099 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2100 is the register being clobbered, and R1 is a register being used in
2101 the equivalent expression.
2103 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2104 in which it is used, return 1.
2106 Otherwise, return 0. */
2109 no_conflict_p (insn, r0, r1)
2113 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2116 /* If R1 is a hard register, return 0 since we handle this case
2117 when we scan the insns that actually use it. */
2120 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2121 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2122 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2125 last = XEXP (note, 0);
2127 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2128 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2130 if (find_reg_note (p, REG_DEAD, r1))
2133 if (reg_mentioned_p (r1, PATTERN (p))
2134 && ! find_reg_note (p, REG_NO_CONFLICT, r1))
2141 #ifdef REGISTER_CONSTRAINTS
2143 /* Return 1 if the constraint string P indicates that the a the operand
2144 must be equal to operand 0 and that no register is acceptable. */
2147 requires_inout_p (p)
2160 case '=': case '+': case '?':
2161 case '#': case '&': case '!':
2162 case '*': case '%': case ',':
2163 case '1': case '2': case '3': case '4':
2164 case 'm': case '<': case '>': case 'V': case 'o':
2165 case 'E': case 'F': case 'G': case 'H':
2166 case 's': case 'i': case 'n':
2167 case 'I': case 'J': case 'K': case 'L':
2168 case 'M': case 'N': case 'O': case 'P':
2169 #ifdef EXTRA_CONSTRAINT
2170 case 'Q': case 'R': case 'S': case 'T': case 'U':
2173 /* These don't say anything we care about. */
2179 /* These mean a register is allowed. Fail if so. */
2185 #endif /* REGISTER_CONSTRAINTS */
2188 dump_local_alloc (file)
2192 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2193 if (reg_renumber[i] != -1)
2194 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);