1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
70 #include "insn-attr.h"
75 /* Next quantity number available for allocation. */
79 /* In all the following vectors indexed by quantity number. */
81 /* Element Q is the hard reg number chosen for quantity Q,
82 or -1 if none was found. */
84 static short *qty_phys_reg;
86 /* We maintain two hard register sets that indicate suggested hard registers
87 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
88 that are tied to the quantity by a simple copy. The second contains all
89 hard registers that are tied to the quantity via an arithmetic operation.
91 The former register set is given priority for allocation. This tends to
92 eliminate copy insns. */
94 /* Element Q is a set of hard registers that are suggested for quantity Q by
97 static HARD_REG_SET *qty_phys_copy_sugg;
99 /* Element Q is a set of hard registers that are suggested for quantity Q by
102 static HARD_REG_SET *qty_phys_sugg;
104 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
106 static short *qty_phys_num_copy_sugg;
108 /* Element Q is the number of suggested registers in qty_phys_sugg. */
110 static short *qty_phys_num_sugg;
112 /* Element Q is the number of refs to quantity Q. */
114 static int *qty_n_refs;
116 /* Element Q is a reg class contained in (smaller than) the
117 preferred classes of all the pseudo regs that are tied in quantity Q.
118 This is the preferred class for allocating that quantity. */
120 static enum reg_class *qty_min_class;
122 /* Insn number (counting from head of basic block)
123 where quantity Q was born. -1 if birth has not been recorded. */
125 static int *qty_birth;
127 /* Insn number (counting from head of basic block)
128 where quantity Q died. Due to the way tying is done,
129 and the fact that we consider in this pass only regs that die but once,
130 a quantity can die only once. Each quantity's life span
131 is a set of consecutive insns. -1 if death has not been recorded. */
133 static int *qty_death;
135 /* Number of words needed to hold the data in quantity Q.
136 This depends on its machine mode. It is used for these purposes:
137 1. It is used in computing the relative importances of qtys,
138 which determines the order in which we look for regs for them.
139 2. It is used in rules that prevent tying several registers of
140 different sizes in a way that is geometrically impossible
141 (see combine_regs). */
143 static int *qty_size;
145 /* This holds the mode of the registers that are tied to qty Q,
146 or VOIDmode if registers with differing modes are tied together. */
148 static enum machine_mode *qty_mode;
150 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
152 static int *qty_n_calls_crossed;
154 /* Register class within which we allocate qty Q if we can't get
155 its preferred class. */
157 static enum reg_class *qty_alternate_class;
159 /* Element Q is nonzero if this quantity has been used in a SUBREG
160 that changes its size. */
162 static char *qty_changes_size;
164 /* Element Q is the register number of one pseudo register whose
165 reg_qty value is Q. This register should be the head of the chain
166 maintained in reg_next_in_qty. */
168 static int *qty_first_reg;
170 /* If (REG N) has been assigned a quantity number, is a register number
171 of another register assigned the same quantity number, or -1 for the
172 end of the chain. qty_first_reg point to the head of this chain. */
174 static int *reg_next_in_qty;
176 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
178 of -1 if this register cannot be allocated by local-alloc,
179 or -2 if not known yet.
181 Note that if we see a use or death of pseudo register N with
182 reg_qty[N] == -2, register N must be local to the current block. If
183 it were used in more than one block, we would have reg_qty[N] == -1.
184 This relies on the fact that if reg_basic_block[N] is >= 0, register N
185 will not appear in any other block. We save a considerable number of
186 tests by exploiting this.
188 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
193 /* The offset (in words) of register N within its quantity.
194 This can be nonzero if register N is SImode, and has been tied
195 to a subreg of a DImode register. */
197 static char *reg_offset;
199 /* Vector of substitutions of register numbers,
200 used to map pseudo regs into hardware regs.
201 This is set up as a result of register allocation.
202 Element N is the hard reg assigned to pseudo reg N,
203 or is -1 if no hard reg was assigned.
204 If N is a hard reg number, element N is N. */
208 /* Set of hard registers live at the current point in the scan
209 of the instructions in a basic block. */
211 static HARD_REG_SET regs_live;
213 /* Each set of hard registers indicates registers live at a particular
214 point in the basic block. For N even, regs_live_at[N] says which
215 hard registers are needed *after* insn N/2 (i.e., they may not
216 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
218 If an object is to conflict with the inputs of insn J but not the
219 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
220 if it is to conflict with the outputs of insn J but not the inputs of
221 insn J + 1, it is said to die at index J*2 + 1. */
223 static HARD_REG_SET *regs_live_at;
225 /* Communicate local vars `insn_number' and `insn'
226 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
227 static int this_insn_number;
228 static rtx this_insn;
230 /* Used to communicate changes made by update_equiv_regs to
231 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
232 found or created, so that we can keep track of what memory accesses might
233 be created later, e.g. by reload. */
235 static rtx *reg_equiv_replacement;
237 static void alloc_qty PROTO((int, enum machine_mode, int, int));
238 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
239 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
240 static int contains_replace_regs PROTO((rtx, char *));
241 static int memref_referenced_p PROTO((rtx, rtx));
242 static int memref_used_between_p PROTO((rtx, rtx, rtx));
243 static void update_equiv_regs PROTO((void));
244 static void block_alloc PROTO((int));
245 static int qty_sugg_compare PROTO((int, int));
246 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
247 static int qty_compare PROTO((int, int));
248 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
249 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
250 static int reg_meets_class_p PROTO((int, enum reg_class));
251 static void update_qty_class PROTO((int, int));
252 static void reg_is_set PROTO((rtx, rtx));
253 static void reg_is_born PROTO((rtx, int));
254 static void wipe_dead_reg PROTO((rtx, int));
255 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
256 int, int, int, int, int));
257 static void mark_life PROTO((int, enum machine_mode, int));
258 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
259 static int no_conflict_p PROTO((rtx, rtx, rtx));
260 static int requires_inout PROTO((char *));
262 /* Allocate a new quantity (new within current basic block)
263 for register number REGNO which is born at index BIRTH
264 within the block. MODE and SIZE are info on reg REGNO. */
267 alloc_qty (regno, mode, size, birth)
269 enum machine_mode mode;
272 register int qty = next_qty++;
274 reg_qty[regno] = qty;
275 reg_offset[regno] = 0;
276 reg_next_in_qty[regno] = -1;
278 qty_first_reg[qty] = regno;
279 qty_size[qty] = size;
280 qty_mode[qty] = mode;
281 qty_birth[qty] = birth;
282 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
283 qty_min_class[qty] = reg_preferred_class (regno);
284 qty_alternate_class[qty] = reg_alternate_class (regno);
285 qty_n_refs[qty] = REG_N_REFS (regno);
286 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
289 /* Main entry point of this file. */
297 /* Leaf functions and non-leaf functions have different needs.
298 If defined, let the machine say what kind of ordering we
300 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
301 ORDER_REGS_FOR_LOCAL_ALLOC;
304 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
306 update_equiv_regs ();
308 /* This sets the maximum number of quantities we can have. Quantity
309 numbers start at zero and we can have one for each pseudo. */
310 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
312 /* Allocate vectors of temporary data.
313 See the declarations of these variables, above,
314 for what they mean. */
316 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
318 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
319 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
320 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
321 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
322 qty_birth = (int *) alloca (max_qty * sizeof (int));
323 qty_death = (int *) alloca (max_qty * sizeof (int));
324 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
325 qty_size = (int *) alloca (max_qty * sizeof (int));
327 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
328 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
330 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
332 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
333 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
334 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
336 reg_qty = (int *) alloca (max_regno * sizeof (int));
337 reg_offset = (char *) alloca (max_regno * sizeof (char));
338 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
340 /* Allocate the reg_renumber array */
341 allocate_reg_info (max_regno, FALSE, TRUE);
343 /* Determine which pseudo-registers can be allocated by local-alloc.
344 In general, these are the registers used only in a single block and
345 which only die once. However, if a register's preferred class has only
346 a few entries, don't allocate this register here unless it is preferred
347 or nothing since retry_global_alloc won't be able to move it to
348 GENERAL_REGS if a reload register of this class is needed.
350 We need not be concerned with which block actually uses the register
351 since we will never see it outside that block. */
353 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
355 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
356 && (reg_alternate_class (i) == NO_REGS
357 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
363 /* Force loop below to initialize entire quantity array. */
366 /* Allocate each block's local registers, block by block. */
368 for (b = 0; b < n_basic_blocks; b++)
370 /* NEXT_QTY indicates which elements of the `qty_...'
371 vectors might need to be initialized because they were used
372 for the previous block; it is set to the entire array before
373 block 0. Initialize those, with explicit loop if there are few,
374 else with bzero and bcopy. Do not initialize vectors that are
375 explicit set by `alloc_qty'. */
379 for (i = 0; i < next_qty; i++)
381 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
382 qty_phys_num_copy_sugg[i] = 0;
383 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
384 qty_phys_num_sugg[i] = 0;
389 #define CLEAR(vector) \
390 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
392 CLEAR (qty_phys_copy_sugg);
393 CLEAR (qty_phys_num_copy_sugg);
394 CLEAR (qty_phys_sugg);
395 CLEAR (qty_phys_num_sugg);
407 /* Depth of loops we are in while in update_equiv_regs. */
408 static int loop_depth;
410 /* Used for communication between the following two functions: contains
411 a MEM that we wish to ensure remains unchanged. */
412 static rtx equiv_mem;
414 /* Set nonzero if EQUIV_MEM is modified. */
415 static int equiv_mem_modified;
417 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
418 Called via note_stores. */
421 validate_equiv_mem_from_store (dest, set)
423 rtx set ATTRIBUTE_UNUSED;
425 if ((GET_CODE (dest) == REG
426 && reg_overlap_mentioned_p (dest, equiv_mem))
427 || (GET_CODE (dest) == MEM
428 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
429 equiv_mem_modified = 1;
432 /* Verify that no store between START and the death of REG invalidates
433 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
434 by storing into an overlapping memory location, or with a non-const
437 Return 1 if MEMREF remains valid. */
440 validate_equiv_mem (start, reg, memref)
449 equiv_mem_modified = 0;
451 /* If the memory reference has side effects or is volatile, it isn't a
452 valid equivalence. */
453 if (side_effects_p (memref))
456 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
458 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
461 if (find_reg_note (insn, REG_DEAD, reg))
464 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
465 && ! CONST_CALL_P (insn))
468 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
470 /* If a register mentioned in MEMREF is modified via an
471 auto-increment, we lose the equivalence. Do the same if one
472 dies; although we could extend the life, it doesn't seem worth
475 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
476 if ((REG_NOTE_KIND (note) == REG_INC
477 || REG_NOTE_KIND (note) == REG_DEAD)
478 && GET_CODE (XEXP (note, 0)) == REG
479 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
486 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
489 contains_replace_regs (x, reg_equiv_replace)
491 char *reg_equiv_replace;
495 enum rtx_code code = GET_CODE (x);
511 return reg_equiv_replace[REGNO (x)];
517 fmt = GET_RTX_FORMAT (code);
518 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
522 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
526 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
527 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
535 /* TRUE if X references a memory location that would be affected by a store
539 memref_referenced_p (memref, x)
545 enum rtx_code code = GET_CODE (x);
561 return (reg_equiv_replacement[REGNO (x)]
562 && memref_referenced_p (memref,
563 reg_equiv_replacement[REGNO (x)]));
566 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
571 /* If we are setting a MEM, it doesn't count (its address does), but any
572 other SET_DEST that has a MEM in it is referencing the MEM. */
573 if (GET_CODE (SET_DEST (x)) == MEM)
575 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
578 else if (memref_referenced_p (memref, SET_DEST (x)))
581 return memref_referenced_p (memref, SET_SRC (x));
587 fmt = GET_RTX_FORMAT (code);
588 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
592 if (memref_referenced_p (memref, XEXP (x, i)))
596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
597 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
605 /* TRUE if some insn in the range (START, END] references a memory location
606 that would be affected by a store to MEMREF. */
609 memref_used_between_p (memref, start, end)
616 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
617 insn = NEXT_INSN (insn))
618 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
619 && memref_referenced_p (memref, PATTERN (insn)))
625 /* Find registers that are equivalent to a single value throughout the
626 compilation (either because they can be referenced in memory or are set once
627 from a single constant). Lower their priority for a register.
629 If such a register is only referenced once, try substituting its value
630 into the using insn. If it succeeds, we can eliminate the register
636 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx));
637 /* Set when an attempt should be made to replace a register with the
638 associated reg_equiv_replacement entry at the end of this function. */
639 char *reg_equiv_replace
640 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
644 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx));
646 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx));
647 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx));
648 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
650 init_alias_analysis ();
654 /* Scan the insns and find which registers have equivalences. Do this
655 in a separate scan of the insns because (due to -fcse-follow-jumps)
656 a register can be set below its use. */
657 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
660 rtx set = single_set (insn);
664 if (GET_CODE (insn) == NOTE)
666 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
668 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
672 /* If this insn contains more (or less) than a single SET, ignore it. */
676 dest = SET_DEST (set);
679 /* If this sets a MEM to the contents of a REG that is only used
680 in a single basic block, see if the register is always equivalent
681 to that memory location and if moving the store from INSN to the
682 insn that set REG is safe. If so, put a REG_EQUIV note on the
685 Don't add a REG_EQUIV note if the insn already has one. The existing
686 REG_EQUIV is likely more useful than the one we are adding.
688 If one of the regs in the address is marked as reg_equiv_replace,
689 then we can't add this REG_EQUIV note. The reg_equiv_replace
690 optimization may move the set of this register immediately before
691 insn, which puts it after reg_equiv_init_insn[regno], and hence
692 the mention in the REG_EQUIV note would be to an uninitialized
695 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
696 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
697 && REG_BASIC_BLOCK (regno) >= 0
698 && reg_equiv_init_insn[regno] != 0
699 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
700 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
701 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
703 && ! memref_used_between_p (SET_DEST (set),
704 reg_equiv_init_insn[regno], insn))
705 REG_NOTES (reg_equiv_init_insn[regno])
706 = gen_rtx_EXPR_LIST (REG_EQUIV, dest,
707 REG_NOTES (reg_equiv_init_insn[regno]));
709 /* We only handle the case of a pseudo register being set
710 once and only if neither the source nor the destination are
711 in a register class that's likely to be spilled. */
712 if (GET_CODE (dest) != REG
713 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
714 || REG_N_SETS (regno) != 1
715 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
716 || (GET_CODE (src) == REG
717 && REGNO (src) >= FIRST_PSEUDO_REGISTER
718 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
721 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
723 #ifdef DONT_RECORD_EQUIVALENCE
724 /* Allow the target to reject promotions of some REG_EQUAL notes to
727 In some cases this can improve register allocation if the existence
728 of the REG_EQUIV note is likely to increase the lifetime of a register
729 that is likely to be spilled.
731 It may also be necessary if the target can't handle certain constant
732 expressions appearing randomly in insns, but for whatever reason
733 those expressions must be considered legitimate constant expressions
734 to prevent them from being forced into memory. */
735 if (note && DONT_RECORD_EQUIVALENCE (note))
739 /* Record this insn as initializing this register. */
740 reg_equiv_init_insn[regno] = insn;
742 /* If this register is known to be equal to a constant, record that
743 it is always equivalent to the constant. */
744 if (note && CONSTANT_P (XEXP (note, 0)))
745 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
747 /* If this insn introduces a "constant" register, decrease the priority
748 of that register. Record this insn if the register is only used once
749 more and the equivalence value is the same as our source.
751 The latter condition is checked for two reasons: First, it is an
752 indication that it may be more efficient to actually emit the insn
753 as written (if no registers are available, reload will substitute
754 the equivalence). Secondly, it avoids problems with any registers
755 dying in this insn whose death notes would be missed.
757 If we don't have a REG_EQUIV note, see if this insn is loading
758 a register used only in one basic block from a MEM. If so, and the
759 MEM remains unchanged for the life of the register, add a REG_EQUIV
762 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
764 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
765 && GET_CODE (SET_SRC (set)) == MEM
766 && validate_equiv_mem (insn, dest, SET_SRC (set)))
767 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
772 int regno = REGNO (dest);
774 reg_equiv_replacement[regno] = XEXP (note, 0);
776 /* Don't mess with things live during setjmp. */
777 if (REG_LIVE_LENGTH (regno) >= 0)
779 /* Note that the statement below does not affect the priority
781 REG_LIVE_LENGTH (regno) *= 2;
784 /* If the register is referenced exactly twice, meaning it is
785 set once and used once, indicate that the reference may be
786 replaced by the equivalence we computed above. If the
787 register is only used in one basic block, this can't succeed
788 or combine would have done it.
790 It would be nice to use "loop_depth * 2" in the compare
791 below. Unfortunately, LOOP_DEPTH need not be constant within
792 a basic block so this would be too complicated.
794 This case normally occurs when a parameter is read from
795 memory and then used exactly once, not in a loop. */
797 if (REG_N_REFS (regno) == 2
798 && REG_BASIC_BLOCK (regno) < 0
799 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
800 reg_equiv_replace[regno] = 1;
805 /* Now scan all regs killed in an insn to see if any of them are
806 registers only used that once. If so, see if we can replace the
807 reference with the equivalent from. If we can, delete the
808 initializing reference and this register will go away. If we
809 can't replace the reference, and the instruction is not in a
810 loop, then move the register initialization just before the use,
811 so that they are in the same basic block. */
814 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
818 /* Keep track of which basic block we are in. */
819 if (block + 1 < n_basic_blocks
820 && basic_block_head[block + 1] == insn)
823 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
825 if (GET_CODE (insn) == NOTE)
827 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
829 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
840 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
842 if (REG_NOTE_KIND (link) == REG_DEAD
843 /* Make sure this insn still refers to the register. */
844 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
846 int regno = REGNO (XEXP (link, 0));
849 if (! reg_equiv_replace[regno])
852 equiv_insn = reg_equiv_init_insn[regno];
854 if (validate_replace_rtx (regno_reg_rtx[regno],
855 reg_equiv_replacement[regno], insn))
857 remove_death (regno, insn);
858 REG_N_REFS (regno) = 0;
859 PUT_CODE (equiv_insn, NOTE);
860 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
861 NOTE_SOURCE_FILE (equiv_insn) = 0;
863 /* If we aren't in a loop, and there are no calls in
864 INSN or in the initialization of the register, then
865 move the initialization of the register to just
866 before INSN. Update the flow information. */
868 && GET_CODE (equiv_insn) == INSN
869 && GET_CODE (insn) == INSN
870 && REG_BASIC_BLOCK (regno) < 0)
874 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
875 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
877 PUT_CODE (equiv_insn, NOTE);
878 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
879 NOTE_SOURCE_FILE (equiv_insn) = 0;
880 REG_NOTES (equiv_insn) = 0;
883 REG_BASIC_BLOCK (regno) = 0;
885 REG_BASIC_BLOCK (regno) = block;
886 REG_N_CALLS_CROSSED (regno) = 0;
887 REG_LIVE_LENGTH (regno) = 2;
889 if (block >= 0 && insn == basic_block_head[block])
890 basic_block_head[block] = PREV_INSN (insn);
892 for (l = 0; l < n_basic_blocks; l++)
893 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
900 /* Allocate hard regs to the pseudo regs used only within block number B.
901 Only the pseudos that die but once can be handled. */
912 int max_uid = get_max_uid ();
914 int no_conflict_combined_regno = -1;
916 /* Count the instructions in the basic block. */
918 insn = basic_block_end[b];
921 if (GET_CODE (insn) != NOTE)
922 if (++insn_count > max_uid)
924 if (insn == basic_block_head[b])
926 insn = PREV_INSN (insn);
929 /* +2 to leave room for a post_mark_life at the last insn and for
930 the birth of a CLOBBER in the first insn. */
931 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
932 * sizeof (HARD_REG_SET));
933 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
935 /* Initialize table of hardware registers currently live. */
937 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
939 /* This loop scans the instructions of the basic block
940 and assigns quantities to registers.
941 It computes which registers to tie. */
943 insn = basic_block_head[b];
946 register rtx body = PATTERN (insn);
948 if (GET_CODE (insn) != NOTE)
951 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
953 register rtx link, set;
954 register int win = 0;
956 int combined_regno = -1;
959 this_insn_number = insn_number;
963 which_alternative = -1;
965 /* Is this insn suitable for tying two registers?
966 If so, try doing that.
967 Suitable insns are those with at least two operands and where
968 operand 0 is an output that is a register that is not
971 We can tie operand 0 with some operand that dies in this insn.
972 First look for operands that are required to be in the same
973 register as operand 0. If we find such, only try tying that
974 operand or one that can be put into that operand if the
975 operation is commutative. If we don't find an operand
976 that is required to be in the same register as operand 0,
977 we can tie with any operand.
979 Subregs in place of regs are also ok.
981 If tying is done, WIN is set nonzero. */
984 #ifdef REGISTER_CONSTRAINTS
985 && recog_n_operands > 1
986 && recog_constraints[0][0] == '='
987 && recog_constraints[0][1] != '&'
989 && GET_CODE (PATTERN (insn)) == SET
990 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
994 #ifdef REGISTER_CONSTRAINTS
995 /* If non-negative, is an operand that must match operand 0. */
996 int must_match_0 = -1;
997 /* Counts number of alternatives that require a match with
999 int n_matching_alts = 0;
1001 for (i = 1; i < recog_n_operands; i++)
1003 char *p = recog_constraints[i];
1004 int this_match = (requires_inout (p));
1006 n_matching_alts += this_match;
1007 if (this_match == recog_n_alternatives)
1012 r0 = recog_operand[0];
1013 for (i = 1; i < recog_n_operands; i++)
1015 #ifdef REGISTER_CONSTRAINTS
1016 /* Skip this operand if we found an operand that
1017 must match operand 0 and this operand isn't it
1018 and can't be made to be it by commutativity. */
1020 if (must_match_0 >= 0 && i != must_match_0
1021 && ! (i == must_match_0 + 1
1022 && recog_constraints[i-1][0] == '%')
1023 && ! (i == must_match_0 - 1
1024 && recog_constraints[i][0] == '%'))
1027 /* Likewise if each alternative has some operand that
1028 must match operand zero. In that case, skip any
1029 operand that doesn't list operand 0 since we know that
1030 the operand always conflicts with operand 0. We
1031 ignore commutatity in this case to keep things simple. */
1032 if (n_matching_alts == recog_n_alternatives
1033 && 0 == requires_inout (recog_constraints[i]))
1037 r1 = recog_operand[i];
1039 /* If the operand is an address, find a register in it.
1040 There may be more than one register, but we only try one
1043 #ifdef REGISTER_CONSTRAINTS
1044 recog_constraints[i][0] == 'p'
1046 recog_operand_address_p[i]
1049 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1052 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1054 /* We have two priorities for hard register preferences.
1055 If we have a move insn or an insn whose first input
1056 can only be in the same register as the output, give
1057 priority to an equivalence found from that insn. */
1059 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1060 #ifdef REGISTER_CONSTRAINTS
1061 || (r1 == recog_operand[i] && must_match_0 >= 0)
1065 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1066 win = combine_regs (r1, r0, may_save_copy,
1067 insn_number, insn, 0);
1074 /* Recognize an insn sequence with an ultimate result
1075 which can safely overlap one of the inputs.
1076 The sequence begins with a CLOBBER of its result,
1077 and ends with an insn that copies the result to itself
1078 and has a REG_EQUAL note for an equivalent formula.
1079 That note indicates what the inputs are.
1080 The result and the input can overlap if each insn in
1081 the sequence either doesn't mention the input
1082 or has a REG_NO_CONFLICT note to inhibit the conflict.
1084 We do the combining test at the CLOBBER so that the
1085 destination register won't have had a quantity number
1086 assigned, since that would prevent combining. */
1088 if (GET_CODE (PATTERN (insn)) == CLOBBER
1089 && (r0 = XEXP (PATTERN (insn), 0),
1090 GET_CODE (r0) == REG)
1091 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1092 && XEXP (link, 0) != 0
1093 && GET_CODE (XEXP (link, 0)) == INSN
1094 && (set = single_set (XEXP (link, 0))) != 0
1095 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1096 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1099 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1100 /* Check that we have such a sequence. */
1101 && no_conflict_p (insn, r0, r1))
1102 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1103 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1104 && (r1 = XEXP (XEXP (note, 0), 0),
1105 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1106 && no_conflict_p (insn, r0, r1))
1107 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1109 /* Here we care if the operation to be computed is
1111 else if ((GET_CODE (XEXP (note, 0)) == EQ
1112 || GET_CODE (XEXP (note, 0)) == NE
1113 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1114 && (r1 = XEXP (XEXP (note, 0), 1),
1115 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1116 && no_conflict_p (insn, r0, r1))
1117 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1119 /* If we did combine something, show the register number
1120 in question so that we know to ignore its death. */
1122 no_conflict_combined_regno = REGNO (r1);
1125 /* If registers were just tied, set COMBINED_REGNO
1126 to the number of the register used in this insn
1127 that was tied to the register set in this insn.
1128 This register's qty should not be "killed". */
1132 while (GET_CODE (r1) == SUBREG)
1133 r1 = SUBREG_REG (r1);
1134 combined_regno = REGNO (r1);
1137 /* Mark the death of everything that dies in this instruction,
1138 except for anything that was just combined. */
1140 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1141 if (REG_NOTE_KIND (link) == REG_DEAD
1142 && GET_CODE (XEXP (link, 0)) == REG
1143 && combined_regno != REGNO (XEXP (link, 0))
1144 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1145 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1146 wipe_dead_reg (XEXP (link, 0), 0);
1148 /* Allocate qty numbers for all registers local to this block
1149 that are born (set) in this instruction.
1150 A pseudo that already has a qty is not changed. */
1152 note_stores (PATTERN (insn), reg_is_set);
1154 /* If anything is set in this insn and then unused, mark it as dying
1155 after this insn, so it will conflict with our outputs. This
1156 can't match with something that combined, and it doesn't matter
1157 if it did. Do this after the calls to reg_is_set since these
1158 die after, not during, the current insn. */
1160 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1161 if (REG_NOTE_KIND (link) == REG_UNUSED
1162 && GET_CODE (XEXP (link, 0)) == REG)
1163 wipe_dead_reg (XEXP (link, 0), 1);
1165 /* If this is an insn that has a REG_RETVAL note pointing at a
1166 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1167 block, so clear any register number that combined within it. */
1168 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1169 && GET_CODE (XEXP (note, 0)) == INSN
1170 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1171 no_conflict_combined_regno = -1;
1174 /* Set the registers live after INSN_NUMBER. Note that we never
1175 record the registers live before the block's first insn, since no
1176 pseudos we care about are live before that insn. */
1178 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1179 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1181 if (insn == basic_block_end[b])
1184 insn = NEXT_INSN (insn);
1187 /* Now every register that is local to this basic block
1188 should have been given a quantity, or else -1 meaning ignore it.
1189 Every quantity should have a known birth and death.
1191 Order the qtys so we assign them registers in order of the
1192 number of suggested registers they need so we allocate those with
1193 the most restrictive needs first. */
1195 qty_order = (int *) alloca (next_qty * sizeof (int));
1196 for (i = 0; i < next_qty; i++)
1199 #define EXCHANGE(I1, I2) \
1200 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1205 /* Make qty_order[2] be the one to allocate last. */
1206 if (qty_sugg_compare (0, 1) > 0)
1208 if (qty_sugg_compare (1, 2) > 0)
1211 /* ... Fall through ... */
1213 /* Put the best one to allocate in qty_order[0]. */
1214 if (qty_sugg_compare (0, 1) > 0)
1217 /* ... Fall through ... */
1221 /* Nothing to do here. */
1225 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1228 /* Try to put each quantity in a suggested physical register, if it has one.
1229 This may cause registers to be allocated that otherwise wouldn't be, but
1230 this seems acceptable in local allocation (unlike global allocation). */
1231 for (i = 0; i < next_qty; i++)
1234 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1235 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1236 0, 1, qty_birth[q], qty_death[q]);
1238 qty_phys_reg[q] = -1;
1241 /* Order the qtys so we assign them registers in order of
1242 decreasing length of life. Normally call qsort, but if we
1243 have only a very small number of quantities, sort them ourselves. */
1245 for (i = 0; i < next_qty; i++)
1248 #define EXCHANGE(I1, I2) \
1249 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1254 /* Make qty_order[2] be the one to allocate last. */
1255 if (qty_compare (0, 1) > 0)
1257 if (qty_compare (1, 2) > 0)
1260 /* ... Fall through ... */
1262 /* Put the best one to allocate in qty_order[0]. */
1263 if (qty_compare (0, 1) > 0)
1266 /* ... Fall through ... */
1270 /* Nothing to do here. */
1274 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1277 /* Now for each qty that is not a hardware register,
1278 look for a hardware register to put it in.
1279 First try the register class that is cheapest for this qty,
1280 if there is more than one class. */
1282 for (i = 0; i < next_qty; i++)
1285 if (qty_phys_reg[q] < 0)
1287 #ifdef INSN_SCHEDULING
1288 /* These values represent the adjusted lifetime of a qty so
1289 that it conflicts with qtys which appear near the start/end
1290 of this qty's lifetime.
1292 The purpose behind extending the lifetime of this qty is to
1293 discourage the register allocator from creating false
1296 The adjustment by the value +-3 indicates precisely that
1297 this qty conflicts with qtys in the instructions immediately
1298 before and after the lifetime of this qty.
1300 Experiments have shown that higher values tend to hurt
1301 overall code performance.
1303 If allocation using the extended lifetime fails we will try
1304 again with the qty's unadjusted lifetime. */
1305 int fake_birth = MAX (0, qty_birth[q] - 3);
1306 int fake_death = MIN (insn_number * 2 + 1, qty_death[q] + 3);
1309 if (N_REG_CLASSES > 1)
1311 #ifdef INSN_SCHEDULING
1312 /* We try to avoid using hard registers allocated to qtys which
1313 are born immediately after this qty or die immediately before
1316 This optimization is only appropriate when we will run
1317 a scheduling pass after reload and we are not optimizing
1319 if (flag_schedule_insns_after_reload
1321 && !SMALL_REGISTER_CLASSES)
1324 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1325 qty_mode[q], q, 0, 0,
1326 fake_birth, fake_death);
1327 if (qty_phys_reg[q] >= 0)
1331 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1332 qty_mode[q], q, 0, 0,
1333 qty_birth[q], qty_death[q]);
1334 if (qty_phys_reg[q] >= 0)
1338 #ifdef INSN_SCHEDULING
1339 /* Similarly, avoid false dependencies. */
1340 if (flag_schedule_insns_after_reload
1342 && !SMALL_REGISTER_CLASSES
1343 && qty_alternate_class[q] != NO_REGS)
1344 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1345 qty_mode[q], q, 0, 0,
1346 fake_birth, fake_death);
1348 if (qty_alternate_class[q] != NO_REGS)
1349 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1350 qty_mode[q], q, 0, 0,
1351 qty_birth[q], qty_death[q]);
1355 /* Now propagate the register assignments
1356 to the pseudo regs belonging to the qtys. */
1358 for (q = 0; q < next_qty; q++)
1359 if (qty_phys_reg[q] >= 0)
1361 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1362 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1366 /* Compare two quantities' priority for getting real registers.
1367 We give shorter-lived quantities higher priority.
1368 Quantities with more references are also preferred, as are quantities that
1369 require multiple registers. This is the identical prioritization as
1370 done by global-alloc.
1372 We used to give preference to registers with *longer* lives, but using
1373 the same algorithm in both local- and global-alloc can speed up execution
1374 of some programs by as much as a factor of three! */
1376 /* Note that the quotient will never be bigger than
1377 the value of floor_log2 times the maximum number of
1378 times a register can occur in one insn (surely less than 100).
1379 Multiplying this by 10000 can't overflow.
1380 QTY_CMP_PRI is also used by qty_sugg_compare. */
1382 #define QTY_CMP_PRI(q) \
1383 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1384 / (qty_death[q] - qty_birth[q])) * 10000))
1387 qty_compare (q1, q2)
1390 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1394 qty_compare_1 (q1p, q2p)
1395 const GENERIC_PTR q1p;
1396 const GENERIC_PTR q2p;
1398 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1399 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1404 /* If qtys are equally good, sort by qty number,
1405 so that the results of qsort leave nothing to chance. */
1409 /* Compare two quantities' priority for getting real registers. This version
1410 is called for quantities that have suggested hard registers. First priority
1411 goes to quantities that have copy preferences, then to those that have
1412 normal preferences. Within those groups, quantities with the lower
1413 number of preferences have the highest priority. Of those, we use the same
1414 algorithm as above. */
1416 #define QTY_CMP_SUGG(q) \
1417 (qty_phys_num_copy_sugg[q] \
1418 ? qty_phys_num_copy_sugg[q] \
1419 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1422 qty_sugg_compare (q1, q2)
1425 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1430 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1434 qty_sugg_compare_1 (q1p, q2p)
1435 const GENERIC_PTR q1p;
1436 const GENERIC_PTR q2p;
1438 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1439 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1444 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1448 /* If qtys are equally good, sort by qty number,
1449 so that the results of qsort leave nothing to chance. */
1456 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1457 Returns 1 if have done so, or 0 if cannot.
1459 Combining registers means marking them as having the same quantity
1460 and adjusting the offsets within the quantity if either of
1463 We don't actually combine a hard reg with a pseudo; instead
1464 we just record the hard reg as the suggestion for the pseudo's quantity.
1465 If we really combined them, we could lose if the pseudo lives
1466 across an insn that clobbers the hard reg (eg, movstr).
1468 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1469 there is no REG_DEAD note on INSN. This occurs during the processing
1470 of REG_NO_CONFLICT blocks.
1472 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1473 SETREG or if the input and output must share a register.
1474 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1476 There are elaborate checks for the validity of combining. */
1480 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1481 rtx usedreg, setreg;
1487 register int ureg, sreg;
1488 register int offset = 0;
1492 /* Determine the numbers and sizes of registers being used. If a subreg
1493 is present that does not change the entire register, don't consider
1494 this a copy insn. */
1496 while (GET_CODE (usedreg) == SUBREG)
1498 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1500 offset += SUBREG_WORD (usedreg);
1501 usedreg = SUBREG_REG (usedreg);
1503 if (GET_CODE (usedreg) != REG)
1505 ureg = REGNO (usedreg);
1506 usize = REG_SIZE (usedreg);
1508 while (GET_CODE (setreg) == SUBREG)
1510 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1512 offset -= SUBREG_WORD (setreg);
1513 setreg = SUBREG_REG (setreg);
1515 if (GET_CODE (setreg) != REG)
1517 sreg = REGNO (setreg);
1518 ssize = REG_SIZE (setreg);
1520 /* If UREG is a pseudo-register that hasn't already been assigned a
1521 quantity number, it means that it is not local to this block or dies
1522 more than once. In either event, we can't do anything with it. */
1523 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1524 /* Do not combine registers unless one fits within the other. */
1525 || (offset > 0 && usize + offset > ssize)
1526 || (offset < 0 && usize + offset < ssize)
1527 /* Do not combine with a smaller already-assigned object
1528 if that smaller object is already combined with something bigger. */
1529 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1530 && usize < qty_size[reg_qty[ureg]])
1531 /* Can't combine if SREG is not a register we can allocate. */
1532 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1533 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1534 These have already been taken care of. This probably wouldn't
1535 combine anyway, but don't take any chances. */
1536 || (ureg >= FIRST_PSEUDO_REGISTER
1537 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1538 /* Don't tie something to itself. In most cases it would make no
1539 difference, but it would screw up if the reg being tied to itself
1540 also dies in this insn. */
1542 /* Don't try to connect two different hardware registers. */
1543 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1544 /* Don't connect two different machine modes if they have different
1545 implications as to which registers may be used. */
1546 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1549 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1550 qty_phys_sugg for the pseudo instead of tying them.
1552 Return "failure" so that the lifespan of UREG is terminated here;
1553 that way the two lifespans will be disjoint and nothing will prevent
1554 the pseudo reg from being given this hard reg. */
1556 if (ureg < FIRST_PSEUDO_REGISTER)
1558 /* Allocate a quantity number so we have a place to put our
1560 if (reg_qty[sreg] == -2)
1561 reg_is_born (setreg, 2 * insn_number);
1563 if (reg_qty[sreg] >= 0)
1566 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1568 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1569 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1571 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1573 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1574 qty_phys_num_sugg[reg_qty[sreg]]++;
1580 /* Similarly for SREG a hard register and UREG a pseudo register. */
1582 if (sreg < FIRST_PSEUDO_REGISTER)
1585 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1587 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1588 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1590 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1592 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1593 qty_phys_num_sugg[reg_qty[ureg]]++;
1598 /* At this point we know that SREG and UREG are both pseudos.
1599 Do nothing if SREG already has a quantity or is a register that we
1601 if (reg_qty[sreg] >= -1
1602 /* If we are not going to let any regs live across calls,
1603 don't tie a call-crossing reg to a non-call-crossing reg. */
1604 || (current_function_has_nonlocal_label
1605 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1606 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1609 /* We don't already know about SREG, so tie it to UREG
1610 if this is the last use of UREG, provided the classes they want
1613 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1614 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1616 /* Add SREG to UREG's quantity. */
1617 sqty = reg_qty[ureg];
1618 reg_qty[sreg] = sqty;
1619 reg_offset[sreg] = reg_offset[ureg] + offset;
1620 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1621 qty_first_reg[sqty] = sreg;
1623 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1624 update_qty_class (sqty, sreg);
1626 /* Update info about quantity SQTY. */
1627 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1628 qty_n_refs[sqty] += REG_N_REFS (sreg);
1633 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1634 reg_offset[i] -= offset;
1636 qty_size[sqty] = ssize;
1637 qty_mode[sqty] = GET_MODE (setreg);
1646 /* Return 1 if the preferred class of REG allows it to be tied
1647 to a quantity or register whose class is CLASS.
1648 True if REG's reg class either contains or is contained in CLASS. */
1651 reg_meets_class_p (reg, class)
1653 enum reg_class class;
1655 register enum reg_class rclass = reg_preferred_class (reg);
1656 return (reg_class_subset_p (rclass, class)
1657 || reg_class_subset_p (class, rclass));
1660 /* Update the class of QTY assuming that REG is being tied to it. */
1663 update_qty_class (qty, reg)
1667 enum reg_class rclass = reg_preferred_class (reg);
1668 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1669 qty_min_class[qty] = rclass;
1671 rclass = reg_alternate_class (reg);
1672 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1673 qty_alternate_class[qty] = rclass;
1675 if (REG_CHANGES_SIZE (reg))
1676 qty_changes_size[qty] = 1;
1679 /* Handle something which alters the value of an rtx REG.
1681 REG is whatever is set or clobbered. SETTER is the rtx that
1682 is modifying the register.
1684 If it is not really a register, we do nothing.
1685 The file-global variables `this_insn' and `this_insn_number'
1686 carry info from `block_alloc'. */
1689 reg_is_set (reg, setter)
1693 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1694 a hard register. These may actually not exist any more. */
1696 if (GET_CODE (reg) != SUBREG
1697 && GET_CODE (reg) != REG)
1700 /* Mark this register as being born. If it is used in a CLOBBER, mark
1701 it as being born halfway between the previous insn and this insn so that
1702 it conflicts with our inputs but not the outputs of the previous insn. */
1704 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1707 /* Handle beginning of the life of register REG.
1708 BIRTH is the index at which this is happening. */
1711 reg_is_born (reg, birth)
1717 if (GET_CODE (reg) == SUBREG)
1718 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1720 regno = REGNO (reg);
1722 if (regno < FIRST_PSEUDO_REGISTER)
1724 mark_life (regno, GET_MODE (reg), 1);
1726 /* If the register was to have been born earlier that the present
1727 insn, mark it as live where it is actually born. */
1728 if (birth < 2 * this_insn_number)
1729 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1733 if (reg_qty[regno] == -2)
1734 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1736 /* If this register has a quantity number, show that it isn't dead. */
1737 if (reg_qty[regno] >= 0)
1738 qty_death[reg_qty[regno]] = -1;
1742 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1743 REG is an output that is dying (i.e., it is never used), otherwise it
1744 is an input (the normal case).
1745 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1748 wipe_dead_reg (reg, output_p)
1752 register int regno = REGNO (reg);
1754 /* If this insn has multiple results,
1755 and the dead reg is used in one of the results,
1756 extend its life to after this insn,
1757 so it won't get allocated together with any other result of this insn. */
1758 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1759 && !single_set (this_insn))
1762 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1764 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1765 if (GET_CODE (set) == SET
1766 && GET_CODE (SET_DEST (set)) != REG
1767 && !rtx_equal_p (reg, SET_DEST (set))
1768 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1773 /* If this register is used in an auto-increment address, then extend its
1774 life to after this insn, so that it won't get allocated together with
1775 the result of this insn. */
1776 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1779 if (regno < FIRST_PSEUDO_REGISTER)
1781 mark_life (regno, GET_MODE (reg), 0);
1783 /* If a hard register is dying as an output, mark it as in use at
1784 the beginning of this insn (the above statement would cause this
1787 post_mark_life (regno, GET_MODE (reg), 1,
1788 2 * this_insn_number, 2 * this_insn_number+ 1);
1791 else if (reg_qty[regno] >= 0)
1792 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1795 /* Find a block of SIZE words of hard regs in reg_class CLASS
1796 that can hold something of machine-mode MODE
1797 (but actually we test only the first of the block for holding MODE)
1798 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1799 and return the number of the first of them.
1800 Return -1 if such a block cannot be found.
1801 If QTY crosses calls, insist on a register preserved by calls,
1802 unless ACCEPT_CALL_CLOBBERED is nonzero.
1804 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1805 register is available. If not, return -1. */
1808 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1809 born_index, dead_index)
1810 enum reg_class class;
1811 enum machine_mode mode;
1813 int accept_call_clobbered;
1814 int just_try_suggested;
1815 int born_index, dead_index;
1817 register int i, ins;
1819 register /* Declare it register if it's a scalar. */
1821 HARD_REG_SET used, first_used;
1822 #ifdef ELIMINABLE_REGS
1823 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1826 /* Validate our parameters. */
1827 if (born_index < 0 || born_index > dead_index)
1830 /* Don't let a pseudo live in a reg across a function call
1831 if we might get a nonlocal goto. */
1832 if (current_function_has_nonlocal_label
1833 && qty_n_calls_crossed[qty] > 0)
1836 if (accept_call_clobbered)
1837 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1838 else if (qty_n_calls_crossed[qty] == 0)
1839 COPY_HARD_REG_SET (used, fixed_reg_set);
1841 COPY_HARD_REG_SET (used, call_used_reg_set);
1843 if (accept_call_clobbered)
1844 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1846 for (ins = born_index; ins < dead_index; ins++)
1847 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1849 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1851 /* Don't use the frame pointer reg in local-alloc even if
1852 we may omit the frame pointer, because if we do that and then we
1853 need a frame pointer, reload won't know how to move the pseudo
1854 to another hard reg. It can move only regs made by global-alloc.
1856 This is true of any register that can be eliminated. */
1857 #ifdef ELIMINABLE_REGS
1858 for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++)
1859 SET_HARD_REG_BIT (used, eliminables[i].from);
1860 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1861 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1862 that it might be eliminated into. */
1863 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1866 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1869 #ifdef CLASS_CANNOT_CHANGE_SIZE
1870 if (qty_changes_size[qty])
1871 IOR_HARD_REG_SET (used,
1872 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
1875 /* Normally, the registers that can be used for the first register in
1876 a multi-register quantity are the same as those that can be used for
1877 subsequent registers. However, if just trying suggested registers,
1878 restrict our consideration to them. If there are copy-suggested
1879 register, try them. Otherwise, try the arithmetic-suggested
1881 COPY_HARD_REG_SET (first_used, used);
1883 if (just_try_suggested)
1885 if (qty_phys_num_copy_sugg[qty] != 0)
1886 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
1888 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
1891 /* If all registers are excluded, we can't do anything. */
1892 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
1894 /* If at least one would be suitable, test each hard reg. */
1896 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1898 #ifdef REG_ALLOC_ORDER
1899 int regno = reg_alloc_order[i];
1903 if (! TEST_HARD_REG_BIT (first_used, regno)
1904 && HARD_REGNO_MODE_OK (regno, mode)
1905 && (qty_n_calls_crossed[qty] == 0
1906 || accept_call_clobbered
1907 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
1910 register int size1 = HARD_REGNO_NREGS (regno, mode);
1911 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
1914 /* Mark that this register is in use between its birth and death
1916 post_mark_life (regno, mode, 1, born_index, dead_index);
1919 #ifndef REG_ALLOC_ORDER
1920 i += j; /* Skip starting points we know will lose */
1927 /* If we are just trying suggested register, we have just tried copy-
1928 suggested registers, and there are arithmetic-suggested registers,
1931 /* If it would be profitable to allocate a call-clobbered register
1932 and save and restore it around calls, do that. */
1933 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
1934 && qty_phys_num_sugg[qty] != 0)
1936 /* Don't try the copy-suggested regs again. */
1937 qty_phys_num_copy_sugg[qty] = 0;
1938 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
1939 born_index, dead_index);
1942 /* We need not check to see if the current function has nonlocal
1943 labels because we don't put any pseudos that are live over calls in
1944 registers in that case. */
1946 if (! accept_call_clobbered
1947 && flag_caller_saves
1948 && ! just_try_suggested
1949 && qty_n_calls_crossed[qty] != 0
1950 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
1952 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
1954 caller_save_needed = 1;
1960 /* Mark that REGNO with machine-mode MODE is live starting from the current
1961 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
1965 mark_life (regno, mode, life)
1967 enum machine_mode mode;
1970 register int j = HARD_REGNO_NREGS (regno, mode);
1973 SET_HARD_REG_BIT (regs_live, regno + j);
1976 CLEAR_HARD_REG_BIT (regs_live, regno + j);
1979 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
1980 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
1981 to insn number DEATH (exclusive). */
1984 post_mark_life (regno, mode, life, birth, death)
1986 enum machine_mode mode;
1987 int life, birth, death;
1989 register int j = HARD_REGNO_NREGS (regno, mode);
1991 register /* Declare it register if it's a scalar. */
1993 HARD_REG_SET this_reg;
1995 CLEAR_HARD_REG_SET (this_reg);
1997 SET_HARD_REG_BIT (this_reg, regno + j);
2000 while (birth < death)
2002 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2006 while (birth < death)
2008 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2013 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2014 is the register being clobbered, and R1 is a register being used in
2015 the equivalent expression.
2017 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2018 in which it is used, return 1.
2020 Otherwise, return 0. */
2023 no_conflict_p (insn, r0, r1)
2027 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2030 /* If R1 is a hard register, return 0 since we handle this case
2031 when we scan the insns that actually use it. */
2034 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2035 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2036 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2039 last = XEXP (note, 0);
2041 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2042 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2044 if (find_reg_note (p, REG_DEAD, r1))
2047 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2048 some earlier optimization pass has inserted instructions into
2049 the sequence, and it is not safe to perform this optimization.
2050 Note that emit_no_conflict_block always ensures that this is
2051 true when these sequences are created. */
2052 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2059 #ifdef REGISTER_CONSTRAINTS
2061 /* Return the number of alternatives for which the constraint string P
2062 indicates that the operand must be equal to operand 0 and that no register
2071 int reg_allowed = 0;
2072 int num_matching_alts = 0;
2077 case '=': case '+': case '?':
2078 case '#': case '&': case '!':
2080 case '1': case '2': case '3': case '4':
2081 case 'm': case '<': case '>': case 'V': case 'o':
2082 case 'E': case 'F': case 'G': case 'H':
2083 case 's': case 'i': case 'n':
2084 case 'I': case 'J': case 'K': case 'L':
2085 case 'M': case 'N': case 'O': case 'P':
2086 #ifdef EXTRA_CONSTRAINT
2087 case 'Q': case 'R': case 'S': case 'T': case 'U':
2090 /* These don't say anything we care about. */
2094 if (found_zero && ! reg_allowed)
2095 num_matching_alts++;
2097 found_zero = reg_allowed = 0;
2111 if (found_zero && ! reg_allowed)
2112 num_matching_alts++;
2114 return num_matching_alts;
2116 #endif /* REGISTER_CONSTRAINTS */
2119 dump_local_alloc (file)
2123 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2124 if (reg_renumber[i] != -1)
2125 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);