1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
70 #include "insn-attr.h"
75 /* Next quantity number available for allocation. */
79 /* In all the following vectors indexed by quantity number. */
81 /* Element Q is the hard reg number chosen for quantity Q,
82 or -1 if none was found. */
84 static short *qty_phys_reg;
86 /* We maintain two hard register sets that indicate suggested hard registers
87 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
88 that are tied to the quantity by a simple copy. The second contains all
89 hard registers that are tied to the quantity via an arithmetic operation.
91 The former register set is given priority for allocation. This tends to
92 eliminate copy insns. */
94 /* Element Q is a set of hard registers that are suggested for quantity Q by
97 static HARD_REG_SET *qty_phys_copy_sugg;
99 /* Element Q is a set of hard registers that are suggested for quantity Q by
102 static HARD_REG_SET *qty_phys_sugg;
104 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
106 static short *qty_phys_num_copy_sugg;
108 /* Element Q is the number of suggested registers in qty_phys_sugg. */
110 static short *qty_phys_num_sugg;
112 /* Element Q is the number of refs to quantity Q. */
114 static int *qty_n_refs;
116 /* Element Q is a reg class contained in (smaller than) the
117 preferred classes of all the pseudo regs that are tied in quantity Q.
118 This is the preferred class for allocating that quantity. */
120 static enum reg_class *qty_min_class;
122 /* Insn number (counting from head of basic block)
123 where quantity Q was born. -1 if birth has not been recorded. */
125 static int *qty_birth;
127 /* Insn number (counting from head of basic block)
128 where quantity Q died. Due to the way tying is done,
129 and the fact that we consider in this pass only regs that die but once,
130 a quantity can die only once. Each quantity's life span
131 is a set of consecutive insns. -1 if death has not been recorded. */
133 static int *qty_death;
135 /* Number of words needed to hold the data in quantity Q.
136 This depends on its machine mode. It is used for these purposes:
137 1. It is used in computing the relative importances of qtys,
138 which determines the order in which we look for regs for them.
139 2. It is used in rules that prevent tying several registers of
140 different sizes in a way that is geometrically impossible
141 (see combine_regs). */
143 static int *qty_size;
145 /* This holds the mode of the registers that are tied to qty Q,
146 or VOIDmode if registers with differing modes are tied together. */
148 static enum machine_mode *qty_mode;
150 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
152 static int *qty_n_calls_crossed;
154 /* Register class within which we allocate qty Q if we can't get
155 its preferred class. */
157 static enum reg_class *qty_alternate_class;
159 /* Element Q is nonzero if this quantity has been used in a SUBREG
160 that changes its size. */
162 static char *qty_changes_size;
164 /* Element Q is the register number of one pseudo register whose
165 reg_qty value is Q. This register should be the head of the chain
166 maintained in reg_next_in_qty. */
168 static int *qty_first_reg;
170 /* If (REG N) has been assigned a quantity number, is a register number
171 of another register assigned the same quantity number, or -1 for the
172 end of the chain. qty_first_reg point to the head of this chain. */
174 static int *reg_next_in_qty;
176 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
178 of -1 if this register cannot be allocated by local-alloc,
179 or -2 if not known yet.
181 Note that if we see a use or death of pseudo register N with
182 reg_qty[N] == -2, register N must be local to the current block. If
183 it were used in more than one block, we would have reg_qty[N] == -1.
184 This relies on the fact that if reg_basic_block[N] is >= 0, register N
185 will not appear in any other block. We save a considerable number of
186 tests by exploiting this.
188 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
193 /* The offset (in words) of register N within its quantity.
194 This can be nonzero if register N is SImode, and has been tied
195 to a subreg of a DImode register. */
197 static char *reg_offset;
199 /* Vector of substitutions of register numbers,
200 used to map pseudo regs into hardware regs.
201 This is set up as a result of register allocation.
202 Element N is the hard reg assigned to pseudo reg N,
203 or is -1 if no hard reg was assigned.
204 If N is a hard reg number, element N is N. */
208 /* Set of hard registers live at the current point in the scan
209 of the instructions in a basic block. */
211 static HARD_REG_SET regs_live;
213 /* Each set of hard registers indicates registers live at a particular
214 point in the basic block. For N even, regs_live_at[N] says which
215 hard registers are needed *after* insn N/2 (i.e., they may not
216 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
218 If an object is to conflict with the inputs of insn J but not the
219 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
220 if it is to conflict with the outputs of insn J but not the inputs of
221 insn J + 1, it is said to die at index J*2 + 1. */
223 static HARD_REG_SET *regs_live_at;
225 /* Communicate local vars `insn_number' and `insn'
226 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
227 static int this_insn_number;
228 static rtx this_insn;
230 /* Used to communicate changes made by update_equiv_regs to
231 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
232 found or created, so that we can keep track of what memory accesses might
233 be created later, e.g. by reload. */
235 static rtx *reg_equiv_replacement;
237 /* Used for communication between update_equiv_regs and no_equiv. */
238 static rtx *reg_equiv_init_insns;
240 static void alloc_qty PROTO((int, enum machine_mode, int, int));
241 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
242 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
243 static int contains_replace_regs PROTO((rtx, char *));
244 static int memref_referenced_p PROTO((rtx, rtx));
245 static int memref_used_between_p PROTO((rtx, rtx, rtx));
246 static void update_equiv_regs PROTO((void));
247 static void no_equiv PROTO((rtx, rtx));
248 static void block_alloc PROTO((int));
249 static int qty_sugg_compare PROTO((int, int));
250 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
251 static int qty_compare PROTO((int, int));
252 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
253 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
254 static int reg_meets_class_p PROTO((int, enum reg_class));
255 static void update_qty_class PROTO((int, int));
256 static void reg_is_set PROTO((rtx, rtx));
257 static void reg_is_born PROTO((rtx, int));
258 static void wipe_dead_reg PROTO((rtx, int));
259 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
260 int, int, int, int, int));
261 static void mark_life PROTO((int, enum machine_mode, int));
262 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
263 static int no_conflict_p PROTO((rtx, rtx, rtx));
264 static int requires_inout PROTO((char *));
266 /* Allocate a new quantity (new within current basic block)
267 for register number REGNO which is born at index BIRTH
268 within the block. MODE and SIZE are info on reg REGNO. */
271 alloc_qty (regno, mode, size, birth)
273 enum machine_mode mode;
276 register int qty = next_qty++;
278 reg_qty[regno] = qty;
279 reg_offset[regno] = 0;
280 reg_next_in_qty[regno] = -1;
282 qty_first_reg[qty] = regno;
283 qty_size[qty] = size;
284 qty_mode[qty] = mode;
285 qty_birth[qty] = birth;
286 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
287 qty_min_class[qty] = reg_preferred_class (regno);
288 qty_alternate_class[qty] = reg_alternate_class (regno);
289 qty_n_refs[qty] = REG_N_REFS (regno);
290 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
293 /* Main entry point of this file. */
301 /* Leaf functions and non-leaf functions have different needs.
302 If defined, let the machine say what kind of ordering we
304 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
305 ORDER_REGS_FOR_LOCAL_ALLOC;
308 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
310 update_equiv_regs ();
312 /* This sets the maximum number of quantities we can have. Quantity
313 numbers start at zero and we can have one for each pseudo. */
314 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
316 /* Allocate vectors of temporary data.
317 See the declarations of these variables, above,
318 for what they mean. */
320 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
322 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
323 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
324 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
325 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
326 qty_birth = (int *) alloca (max_qty * sizeof (int));
327 qty_death = (int *) alloca (max_qty * sizeof (int));
328 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
329 qty_size = (int *) alloca (max_qty * sizeof (int));
331 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
332 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
334 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
336 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
337 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
338 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
340 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
341 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
342 reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int));
344 /* Allocate the reg_renumber array */
345 allocate_reg_info (max_regno, FALSE, TRUE);
347 /* Determine which pseudo-registers can be allocated by local-alloc.
348 In general, these are the registers used only in a single block and
349 which only die once. However, if a register's preferred class has only
350 a few entries, don't allocate this register here unless it is preferred
351 or nothing since retry_global_alloc won't be able to move it to
352 GENERAL_REGS if a reload register of this class is needed.
354 We need not be concerned with which block actually uses the register
355 since we will never see it outside that block. */
357 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
359 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
360 && (reg_alternate_class (i) == NO_REGS
361 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
367 /* Force loop below to initialize entire quantity array. */
370 /* Allocate each block's local registers, block by block. */
372 for (b = 0; b < n_basic_blocks; b++)
374 /* NEXT_QTY indicates which elements of the `qty_...'
375 vectors might need to be initialized because they were used
376 for the previous block; it is set to the entire array before
377 block 0. Initialize those, with explicit loop if there are few,
378 else with bzero and bcopy. Do not initialize vectors that are
379 explicit set by `alloc_qty'. */
383 for (i = 0; i < next_qty; i++)
385 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
386 qty_phys_num_copy_sugg[i] = 0;
387 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
388 qty_phys_num_sugg[i] = 0;
393 #define CLEAR(vector) \
394 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
396 CLEAR (qty_phys_copy_sugg);
397 CLEAR (qty_phys_num_copy_sugg);
398 CLEAR (qty_phys_sugg);
399 CLEAR (qty_phys_num_sugg);
412 free (reg_next_in_qty);
415 /* Depth of loops we are in while in update_equiv_regs. */
416 static int loop_depth;
418 /* Used for communication between the following two functions: contains
419 a MEM that we wish to ensure remains unchanged. */
420 static rtx equiv_mem;
422 /* Set nonzero if EQUIV_MEM is modified. */
423 static int equiv_mem_modified;
425 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
426 Called via note_stores. */
429 validate_equiv_mem_from_store (dest, set)
431 rtx set ATTRIBUTE_UNUSED;
433 if ((GET_CODE (dest) == REG
434 && reg_overlap_mentioned_p (dest, equiv_mem))
435 || (GET_CODE (dest) == MEM
436 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
437 equiv_mem_modified = 1;
440 /* Verify that no store between START and the death of REG invalidates
441 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
442 by storing into an overlapping memory location, or with a non-const
445 Return 1 if MEMREF remains valid. */
448 validate_equiv_mem (start, reg, memref)
457 equiv_mem_modified = 0;
459 /* If the memory reference has side effects or is volatile, it isn't a
460 valid equivalence. */
461 if (side_effects_p (memref))
464 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
466 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
469 if (find_reg_note (insn, REG_DEAD, reg))
472 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
473 && ! CONST_CALL_P (insn))
476 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
478 /* If a register mentioned in MEMREF is modified via an
479 auto-increment, we lose the equivalence. Do the same if one
480 dies; although we could extend the life, it doesn't seem worth
483 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
484 if ((REG_NOTE_KIND (note) == REG_INC
485 || REG_NOTE_KIND (note) == REG_DEAD)
486 && GET_CODE (XEXP (note, 0)) == REG
487 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
494 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
497 contains_replace_regs (x, reg_equiv_replace)
499 char *reg_equiv_replace;
503 enum rtx_code code = GET_CODE (x);
519 return reg_equiv_replace[REGNO (x)];
525 fmt = GET_RTX_FORMAT (code);
526 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
530 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
534 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
535 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
543 /* TRUE if X references a memory location that would be affected by a store
547 memref_referenced_p (memref, x)
553 enum rtx_code code = GET_CODE (x);
569 return (reg_equiv_replacement[REGNO (x)]
570 && memref_referenced_p (memref,
571 reg_equiv_replacement[REGNO (x)]));
574 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
579 /* If we are setting a MEM, it doesn't count (its address does), but any
580 other SET_DEST that has a MEM in it is referencing the MEM. */
581 if (GET_CODE (SET_DEST (x)) == MEM)
583 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
586 else if (memref_referenced_p (memref, SET_DEST (x)))
589 return memref_referenced_p (memref, SET_SRC (x));
595 fmt = GET_RTX_FORMAT (code);
596 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
600 if (memref_referenced_p (memref, XEXP (x, i)))
604 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
605 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
613 /* TRUE if some insn in the range (START, END] references a memory location
614 that would be affected by a store to MEMREF. */
617 memref_used_between_p (memref, start, end)
624 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
625 insn = NEXT_INSN (insn))
626 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
627 && memref_referenced_p (memref, PATTERN (insn)))
633 /* Find registers that are equivalent to a single value throughout the
634 compilation (either because they can be referenced in memory or are set once
635 from a single constant). Lower their priority for a register.
637 If such a register is only referenced once, try substituting its value
638 into the using insn. If it succeeds, we can eliminate the register
644 /* Set when an attempt should be made to replace a register with the
645 associated reg_equiv_replacement entry at the end of this function. */
646 char *reg_equiv_replace
647 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
651 reg_equiv_init_insns = (rtx *) alloca (max_regno * sizeof (rtx));
652 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx));
654 bzero ((char *) reg_equiv_init_insns, max_regno * sizeof (rtx));
655 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx));
656 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
658 init_alias_analysis ();
662 /* Scan the insns and find which registers have equivalences. Do this
663 in a separate scan of the insns because (due to -fcse-follow-jumps)
664 a register can be set below its use. */
665 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
672 if (GET_CODE (insn) == NOTE)
674 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
676 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
680 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
683 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
684 if (REG_NOTE_KIND (note) == REG_INC)
685 no_equiv (XEXP (note, 0), note);
687 set = single_set (insn);
689 /* If this insn contains more (or less) than a single SET,
690 only mark all destinations as having no known equivalence. */
693 note_stores (PATTERN (insn), no_equiv);
696 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
700 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
702 rtx part = XVECEXP (PATTERN (insn), 0, i);
704 note_stores (part, no_equiv);
708 dest = SET_DEST (set);
711 /* If this sets a MEM to the contents of a REG that is only used
712 in a single basic block, see if the register is always equivalent
713 to that memory location and if moving the store from INSN to the
714 insn that set REG is safe. If so, put a REG_EQUIV note on the
717 Don't add a REG_EQUIV note if the insn already has one. The existing
718 REG_EQUIV is likely more useful than the one we are adding.
720 If one of the regs in the address is marked as reg_equiv_replace,
721 then we can't add this REG_EQUIV note. The reg_equiv_replace
722 optimization may move the set of this register immediately before
723 insn, which puts it after reg_equiv_init_insns[regno], and hence
724 the mention in the REG_EQUIV note would be to an uninitialized
726 /* ????? This test isn't good enough; we might see a MEM with a use of
727 a pseudo register before we see its setting insn that will cause
728 reg_equiv_replace for that pseudo to be set.
729 Equivalences to MEMs should be made in another pass, after the
730 reg_equiv_replace information has been gathered. */
732 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
733 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
734 && REG_BASIC_BLOCK (regno) >= 0
735 && REG_N_SETS (regno) == 1
736 && reg_equiv_init_insns[regno] != 0
737 && reg_equiv_init_insns[regno] != const0_rtx
738 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
739 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))
741 rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);
742 if (validate_equiv_mem (init_insn, src, dest)
743 && ! memref_used_between_p (dest, init_insn, insn))
744 REG_NOTES (init_insn)
745 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
748 /* We only handle the case of a pseudo register being set
749 once, or always to the same value. */
750 /* ??? The mn10200 port breaks if we add equivalences for
751 values that need an ADDRESS_REGS register and set them equivalent
752 to a MEM of a pseudo. The actual problem is in the over-conservative
753 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
754 calculate_needs, but we traditionally work around this problem
755 here by rejecting equivalences when the destination is in a register
756 that's likely spilled. This is fragile, of course, since the
757 preferred class of a pseudo depends on all intructions that set
760 if (GET_CODE (dest) != REG
761 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
762 || reg_equiv_init_insns[regno] == const0_rtx
763 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
764 && GET_CODE (src) == MEM))
766 /* This might be seting a SUBREG of a pseudo, a pseudo that is
767 also set somewhere else to a constant. */
768 note_stores (set, no_equiv);
771 /* Don't handle the equivalence if the source is in a register
772 class that's likely to be spilled. */
773 if (GET_CODE (src) == REG
774 && REGNO (src) >= FIRST_PSEUDO_REGISTER
775 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src))))
777 no_equiv (dest, set);
781 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
783 #ifdef DONT_RECORD_EQUIVALENCE
784 /* Allow the target to reject promotions of some REG_EQUAL notes to
787 In some cases this can improve register allocation if the existence
788 of the REG_EQUIV note is likely to increase the lifetime of a register
789 that is likely to be spilled.
791 It may also be necessary if the target can't handle certain constant
792 expressions appearing randomly in insns, but for whatever reason
793 those expressions must be considered legitimate constant expressions
794 to prevent them from being forced into memory. */
795 if (note && DONT_RECORD_EQUIVALENCE (note))
799 if (REG_N_SETS (regno) != 1
801 || ! CONSTANT_P (XEXP (note, 0))
802 || (reg_equiv_replacement[regno]
803 && ! rtx_equal_p (XEXP (note, 0),
804 reg_equiv_replacement[regno]))))
806 no_equiv (dest, set);
809 /* Record this insn as initializing this register. */
810 reg_equiv_init_insns[regno]
811 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]);
813 /* If this register is known to be equal to a constant, record that
814 it is always equivalent to the constant. */
815 if (note && CONSTANT_P (XEXP (note, 0)))
816 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
818 /* If this insn introduces a "constant" register, decrease the priority
819 of that register. Record this insn if the register is only used once
820 more and the equivalence value is the same as our source.
822 The latter condition is checked for two reasons: First, it is an
823 indication that it may be more efficient to actually emit the insn
824 as written (if no registers are available, reload will substitute
825 the equivalence). Secondly, it avoids problems with any registers
826 dying in this insn whose death notes would be missed.
828 If we don't have a REG_EQUIV note, see if this insn is loading
829 a register used only in one basic block from a MEM. If so, and the
830 MEM remains unchanged for the life of the register, add a REG_EQUIV
833 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
835 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
836 && GET_CODE (SET_SRC (set)) == MEM
837 && validate_equiv_mem (insn, dest, SET_SRC (set)))
838 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
843 int regno = REGNO (dest);
845 reg_equiv_replacement[regno] = XEXP (note, 0);
847 /* Don't mess with things live during setjmp. */
848 if (REG_LIVE_LENGTH (regno) >= 0)
850 /* Note that the statement below does not affect the priority
852 REG_LIVE_LENGTH (regno) *= 2;
855 /* If the register is referenced exactly twice, meaning it is
856 set once and used once, indicate that the reference may be
857 replaced by the equivalence we computed above. If the
858 register is only used in one basic block, this can't succeed
859 or combine would have done it.
861 It would be nice to use "loop_depth * 2" in the compare
862 below. Unfortunately, LOOP_DEPTH need not be constant within
863 a basic block so this would be too complicated.
865 This case normally occurs when a parameter is read from
866 memory and then used exactly once, not in a loop. */
868 if (REG_N_REFS (regno) == 2
869 && REG_BASIC_BLOCK (regno) < 0
870 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
871 reg_equiv_replace[regno] = 1;
876 /* Now scan all regs killed in an insn to see if any of them are
877 registers only used that once. If so, see if we can replace the
878 reference with the equivalent from. If we can, delete the
879 initializing reference and this register will go away. If we
880 can't replace the reference, and the instruction is not in a
881 loop, then move the register initialization just before the use,
882 so that they are in the same basic block. */
885 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
889 /* Keep track of which basic block we are in. */
890 if (block + 1 < n_basic_blocks
891 && basic_block_head[block + 1] == insn)
894 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
896 if (GET_CODE (insn) == NOTE)
898 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
900 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
911 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
913 if (REG_NOTE_KIND (link) == REG_DEAD
914 /* Make sure this insn still refers to the register. */
915 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
917 int regno = REGNO (XEXP (link, 0));
920 if (! reg_equiv_replace[regno])
923 /* reg_equiv_replace[REGNO] gets set only when
924 REG_N_REFS[REGNO] is 2, i.e. the register is set
925 once and used once. (If it were only set, but not used,
926 flow would have deleted the setting insns.) Hence
927 there can only be one insn in reg_equiv_init_insns. */
928 equiv_insn = XEXP (reg_equiv_init_insns[regno], 0);
930 if (validate_replace_rtx (regno_reg_rtx[regno],
931 reg_equiv_replacement[regno], insn))
933 remove_death (regno, insn);
934 REG_N_REFS (regno) = 0;
935 PUT_CODE (equiv_insn, NOTE);
936 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
937 NOTE_SOURCE_FILE (equiv_insn) = 0;
939 /* If we aren't in a loop, and there are no calls in
940 INSN or in the initialization of the register, then
941 move the initialization of the register to just
942 before INSN. Update the flow information. */
944 && GET_CODE (equiv_insn) == INSN
945 && GET_CODE (insn) == INSN
946 && REG_BASIC_BLOCK (regno) < 0)
950 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
951 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
953 PUT_CODE (equiv_insn, NOTE);
954 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
955 NOTE_SOURCE_FILE (equiv_insn) = 0;
956 REG_NOTES (equiv_insn) = 0;
959 REG_BASIC_BLOCK (regno) = 0;
961 REG_BASIC_BLOCK (regno) = block;
962 REG_N_CALLS_CROSSED (regno) = 0;
963 REG_LIVE_LENGTH (regno) = 2;
965 if (block >= 0 && insn == basic_block_head[block])
966 basic_block_head[block] = PREV_INSN (insn);
968 for (l = 0; l < n_basic_blocks; l++)
969 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
976 /* Mark REG as having no known equivalence.
977 Some instructions might have been proceessed before and furnished
978 with REG_EQUIV notes for this register; these notes will have to be
980 STORE is the piece of RTL that does the non-constant / conflicting
981 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
982 but needs to be there because this function is called from note_stores. */
984 no_equiv (reg, store)
990 if (GET_CODE (reg) != REG)
993 list = reg_equiv_init_insns[regno];
994 if (list == const0_rtx)
996 for (; list; list = XEXP (list, 1))
998 rtx insn = XEXP (list, 0);
999 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1001 reg_equiv_init_insns[regno] = const0_rtx;
1002 reg_equiv_replacement[regno] = NULL_RTX;
1005 /* Allocate hard regs to the pseudo regs used only within block number B.
1006 Only the pseudos that die but once can be handled. */
1015 int insn_number = 0;
1017 int max_uid = get_max_uid ();
1019 int no_conflict_combined_regno = -1;
1021 /* Count the instructions in the basic block. */
1023 insn = basic_block_end[b];
1026 if (GET_CODE (insn) != NOTE)
1027 if (++insn_count > max_uid)
1029 if (insn == basic_block_head[b])
1031 insn = PREV_INSN (insn);
1034 /* +2 to leave room for a post_mark_life at the last insn and for
1035 the birth of a CLOBBER in the first insn. */
1036 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1037 * sizeof (HARD_REG_SET));
1038 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1040 /* Initialize table of hardware registers currently live. */
1042 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1044 /* This loop scans the instructions of the basic block
1045 and assigns quantities to registers.
1046 It computes which registers to tie. */
1048 insn = basic_block_head[b];
1051 register rtx body = PATTERN (insn);
1053 if (GET_CODE (insn) != NOTE)
1056 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1058 register rtx link, set;
1059 register int win = 0;
1060 register rtx r0, r1;
1061 int combined_regno = -1;
1064 this_insn_number = insn_number;
1067 extract_insn (insn);
1068 which_alternative = -1;
1070 /* Is this insn suitable for tying two registers?
1071 If so, try doing that.
1072 Suitable insns are those with at least two operands and where
1073 operand 0 is an output that is a register that is not
1076 We can tie operand 0 with some operand that dies in this insn.
1077 First look for operands that are required to be in the same
1078 register as operand 0. If we find such, only try tying that
1079 operand or one that can be put into that operand if the
1080 operation is commutative. If we don't find an operand
1081 that is required to be in the same register as operand 0,
1082 we can tie with any operand.
1084 Subregs in place of regs are also ok.
1086 If tying is done, WIN is set nonzero. */
1089 #ifdef REGISTER_CONSTRAINTS
1090 && recog_n_operands > 1
1091 && recog_constraints[0][0] == '='
1092 && recog_constraints[0][1] != '&'
1094 && GET_CODE (PATTERN (insn)) == SET
1095 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1099 #ifdef REGISTER_CONSTRAINTS
1100 /* If non-negative, is an operand that must match operand 0. */
1101 int must_match_0 = -1;
1102 /* Counts number of alternatives that require a match with
1104 int n_matching_alts = 0;
1106 for (i = 1; i < recog_n_operands; i++)
1108 char *p = recog_constraints[i];
1109 int this_match = (requires_inout (p));
1111 n_matching_alts += this_match;
1112 if (this_match == recog_n_alternatives)
1117 r0 = recog_operand[0];
1118 for (i = 1; i < recog_n_operands; i++)
1120 #ifdef REGISTER_CONSTRAINTS
1121 /* Skip this operand if we found an operand that
1122 must match operand 0 and this operand isn't it
1123 and can't be made to be it by commutativity. */
1125 if (must_match_0 >= 0 && i != must_match_0
1126 && ! (i == must_match_0 + 1
1127 && recog_constraints[i-1][0] == '%')
1128 && ! (i == must_match_0 - 1
1129 && recog_constraints[i][0] == '%'))
1132 /* Likewise if each alternative has some operand that
1133 must match operand zero. In that case, skip any
1134 operand that doesn't list operand 0 since we know that
1135 the operand always conflicts with operand 0. We
1136 ignore commutatity in this case to keep things simple. */
1137 if (n_matching_alts == recog_n_alternatives
1138 && 0 == requires_inout (recog_constraints[i]))
1142 r1 = recog_operand[i];
1144 /* If the operand is an address, find a register in it.
1145 There may be more than one register, but we only try one
1148 #ifdef REGISTER_CONSTRAINTS
1149 recog_constraints[i][0] == 'p'
1151 recog_operand_address_p[i]
1154 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1157 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1159 /* We have two priorities for hard register preferences.
1160 If we have a move insn or an insn whose first input
1161 can only be in the same register as the output, give
1162 priority to an equivalence found from that insn. */
1164 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1165 #ifdef REGISTER_CONSTRAINTS
1166 || (r1 == recog_operand[i] && must_match_0 >= 0)
1170 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1171 win = combine_regs (r1, r0, may_save_copy,
1172 insn_number, insn, 0);
1179 /* Recognize an insn sequence with an ultimate result
1180 which can safely overlap one of the inputs.
1181 The sequence begins with a CLOBBER of its result,
1182 and ends with an insn that copies the result to itself
1183 and has a REG_EQUAL note for an equivalent formula.
1184 That note indicates what the inputs are.
1185 The result and the input can overlap if each insn in
1186 the sequence either doesn't mention the input
1187 or has a REG_NO_CONFLICT note to inhibit the conflict.
1189 We do the combining test at the CLOBBER so that the
1190 destination register won't have had a quantity number
1191 assigned, since that would prevent combining. */
1193 if (GET_CODE (PATTERN (insn)) == CLOBBER
1194 && (r0 = XEXP (PATTERN (insn), 0),
1195 GET_CODE (r0) == REG)
1196 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1197 && XEXP (link, 0) != 0
1198 && GET_CODE (XEXP (link, 0)) == INSN
1199 && (set = single_set (XEXP (link, 0))) != 0
1200 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1201 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1204 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1205 /* Check that we have such a sequence. */
1206 && no_conflict_p (insn, r0, r1))
1207 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1208 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1209 && (r1 = XEXP (XEXP (note, 0), 0),
1210 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1211 && no_conflict_p (insn, r0, r1))
1212 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1214 /* Here we care if the operation to be computed is
1216 else if ((GET_CODE (XEXP (note, 0)) == EQ
1217 || GET_CODE (XEXP (note, 0)) == NE
1218 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1219 && (r1 = XEXP (XEXP (note, 0), 1),
1220 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1221 && no_conflict_p (insn, r0, r1))
1222 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1224 /* If we did combine something, show the register number
1225 in question so that we know to ignore its death. */
1227 no_conflict_combined_regno = REGNO (r1);
1230 /* If registers were just tied, set COMBINED_REGNO
1231 to the number of the register used in this insn
1232 that was tied to the register set in this insn.
1233 This register's qty should not be "killed". */
1237 while (GET_CODE (r1) == SUBREG)
1238 r1 = SUBREG_REG (r1);
1239 combined_regno = REGNO (r1);
1242 /* Mark the death of everything that dies in this instruction,
1243 except for anything that was just combined. */
1245 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1246 if (REG_NOTE_KIND (link) == REG_DEAD
1247 && GET_CODE (XEXP (link, 0)) == REG
1248 && combined_regno != REGNO (XEXP (link, 0))
1249 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1250 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1251 wipe_dead_reg (XEXP (link, 0), 0);
1253 /* Allocate qty numbers for all registers local to this block
1254 that are born (set) in this instruction.
1255 A pseudo that already has a qty is not changed. */
1257 note_stores (PATTERN (insn), reg_is_set);
1259 /* If anything is set in this insn and then unused, mark it as dying
1260 after this insn, so it will conflict with our outputs. This
1261 can't match with something that combined, and it doesn't matter
1262 if it did. Do this after the calls to reg_is_set since these
1263 die after, not during, the current insn. */
1265 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1266 if (REG_NOTE_KIND (link) == REG_UNUSED
1267 && GET_CODE (XEXP (link, 0)) == REG)
1268 wipe_dead_reg (XEXP (link, 0), 1);
1270 /* If this is an insn that has a REG_RETVAL note pointing at a
1271 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1272 block, so clear any register number that combined within it. */
1273 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1274 && GET_CODE (XEXP (note, 0)) == INSN
1275 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1276 no_conflict_combined_regno = -1;
1279 /* Set the registers live after INSN_NUMBER. Note that we never
1280 record the registers live before the block's first insn, since no
1281 pseudos we care about are live before that insn. */
1283 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1284 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1286 if (insn == basic_block_end[b])
1289 insn = NEXT_INSN (insn);
1292 /* Now every register that is local to this basic block
1293 should have been given a quantity, or else -1 meaning ignore it.
1294 Every quantity should have a known birth and death.
1296 Order the qtys so we assign them registers in order of the
1297 number of suggested registers they need so we allocate those with
1298 the most restrictive needs first. */
1300 qty_order = (int *) alloca (next_qty * sizeof (int));
1301 for (i = 0; i < next_qty; i++)
1304 #define EXCHANGE(I1, I2) \
1305 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1310 /* Make qty_order[2] be the one to allocate last. */
1311 if (qty_sugg_compare (0, 1) > 0)
1313 if (qty_sugg_compare (1, 2) > 0)
1316 /* ... Fall through ... */
1318 /* Put the best one to allocate in qty_order[0]. */
1319 if (qty_sugg_compare (0, 1) > 0)
1322 /* ... Fall through ... */
1326 /* Nothing to do here. */
1330 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1333 /* Try to put each quantity in a suggested physical register, if it has one.
1334 This may cause registers to be allocated that otherwise wouldn't be, but
1335 this seems acceptable in local allocation (unlike global allocation). */
1336 for (i = 0; i < next_qty; i++)
1339 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1340 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1341 0, 1, qty_birth[q], qty_death[q]);
1343 qty_phys_reg[q] = -1;
1346 /* Order the qtys so we assign them registers in order of
1347 decreasing length of life. Normally call qsort, but if we
1348 have only a very small number of quantities, sort them ourselves. */
1350 for (i = 0; i < next_qty; i++)
1353 #define EXCHANGE(I1, I2) \
1354 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1359 /* Make qty_order[2] be the one to allocate last. */
1360 if (qty_compare (0, 1) > 0)
1362 if (qty_compare (1, 2) > 0)
1365 /* ... Fall through ... */
1367 /* Put the best one to allocate in qty_order[0]. */
1368 if (qty_compare (0, 1) > 0)
1371 /* ... Fall through ... */
1375 /* Nothing to do here. */
1379 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1382 /* Now for each qty that is not a hardware register,
1383 look for a hardware register to put it in.
1384 First try the register class that is cheapest for this qty,
1385 if there is more than one class. */
1387 for (i = 0; i < next_qty; i++)
1390 if (qty_phys_reg[q] < 0)
1392 #ifdef INSN_SCHEDULING
1393 /* These values represent the adjusted lifetime of a qty so
1394 that it conflicts with qtys which appear near the start/end
1395 of this qty's lifetime.
1397 The purpose behind extending the lifetime of this qty is to
1398 discourage the register allocator from creating false
1401 The adjustment by the value +-3 indicates precisely that
1402 this qty conflicts with qtys in the instructions immediately
1403 before and after the lifetime of this qty.
1405 Experiments have shown that higher values tend to hurt
1406 overall code performance.
1408 If allocation using the extended lifetime fails we will try
1409 again with the qty's unadjusted lifetime. */
1410 int fake_birth = MAX (0, qty_birth[q] - 3);
1411 int fake_death = MIN (insn_number * 2 + 1, qty_death[q] + 3);
1414 if (N_REG_CLASSES > 1)
1416 #ifdef INSN_SCHEDULING
1417 /* We try to avoid using hard registers allocated to qtys which
1418 are born immediately after this qty or die immediately before
1421 This optimization is only appropriate when we will run
1422 a scheduling pass after reload and we are not optimizing
1424 if (flag_schedule_insns_after_reload
1426 && !SMALL_REGISTER_CLASSES)
1429 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1430 qty_mode[q], q, 0, 0,
1431 fake_birth, fake_death);
1432 if (qty_phys_reg[q] >= 0)
1436 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1437 qty_mode[q], q, 0, 0,
1438 qty_birth[q], qty_death[q]);
1439 if (qty_phys_reg[q] >= 0)
1443 #ifdef INSN_SCHEDULING
1444 /* Similarly, avoid false dependencies. */
1445 if (flag_schedule_insns_after_reload
1447 && !SMALL_REGISTER_CLASSES
1448 && qty_alternate_class[q] != NO_REGS)
1449 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1450 qty_mode[q], q, 0, 0,
1451 fake_birth, fake_death);
1453 if (qty_alternate_class[q] != NO_REGS)
1454 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1455 qty_mode[q], q, 0, 0,
1456 qty_birth[q], qty_death[q]);
1460 /* Now propagate the register assignments
1461 to the pseudo regs belonging to the qtys. */
1463 for (q = 0; q < next_qty; q++)
1464 if (qty_phys_reg[q] >= 0)
1466 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1467 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1471 /* Compare two quantities' priority for getting real registers.
1472 We give shorter-lived quantities higher priority.
1473 Quantities with more references are also preferred, as are quantities that
1474 require multiple registers. This is the identical prioritization as
1475 done by global-alloc.
1477 We used to give preference to registers with *longer* lives, but using
1478 the same algorithm in both local- and global-alloc can speed up execution
1479 of some programs by as much as a factor of three! */
1481 /* Note that the quotient will never be bigger than
1482 the value of floor_log2 times the maximum number of
1483 times a register can occur in one insn (surely less than 100).
1484 Multiplying this by 10000 can't overflow.
1485 QTY_CMP_PRI is also used by qty_sugg_compare. */
1487 #define QTY_CMP_PRI(q) \
1488 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1489 / (qty_death[q] - qty_birth[q])) * 10000))
1492 qty_compare (q1, q2)
1495 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1499 qty_compare_1 (q1p, q2p)
1500 const GENERIC_PTR q1p;
1501 const GENERIC_PTR q2p;
1503 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1504 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1509 /* If qtys are equally good, sort by qty number,
1510 so that the results of qsort leave nothing to chance. */
1514 /* Compare two quantities' priority for getting real registers. This version
1515 is called for quantities that have suggested hard registers. First priority
1516 goes to quantities that have copy preferences, then to those that have
1517 normal preferences. Within those groups, quantities with the lower
1518 number of preferences have the highest priority. Of those, we use the same
1519 algorithm as above. */
1521 #define QTY_CMP_SUGG(q) \
1522 (qty_phys_num_copy_sugg[q] \
1523 ? qty_phys_num_copy_sugg[q] \
1524 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1527 qty_sugg_compare (q1, q2)
1530 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1535 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1539 qty_sugg_compare_1 (q1p, q2p)
1540 const GENERIC_PTR q1p;
1541 const GENERIC_PTR q2p;
1543 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1544 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1549 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1553 /* If qtys are equally good, sort by qty number,
1554 so that the results of qsort leave nothing to chance. */
1561 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1562 Returns 1 if have done so, or 0 if cannot.
1564 Combining registers means marking them as having the same quantity
1565 and adjusting the offsets within the quantity if either of
1568 We don't actually combine a hard reg with a pseudo; instead
1569 we just record the hard reg as the suggestion for the pseudo's quantity.
1570 If we really combined them, we could lose if the pseudo lives
1571 across an insn that clobbers the hard reg (eg, movstr).
1573 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1574 there is no REG_DEAD note on INSN. This occurs during the processing
1575 of REG_NO_CONFLICT blocks.
1577 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1578 SETREG or if the input and output must share a register.
1579 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1581 There are elaborate checks for the validity of combining. */
1585 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1586 rtx usedreg, setreg;
1592 register int ureg, sreg;
1593 register int offset = 0;
1597 /* Determine the numbers and sizes of registers being used. If a subreg
1598 is present that does not change the entire register, don't consider
1599 this a copy insn. */
1601 while (GET_CODE (usedreg) == SUBREG)
1603 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1605 offset += SUBREG_WORD (usedreg);
1606 usedreg = SUBREG_REG (usedreg);
1608 if (GET_CODE (usedreg) != REG)
1610 ureg = REGNO (usedreg);
1611 usize = REG_SIZE (usedreg);
1613 while (GET_CODE (setreg) == SUBREG)
1615 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1617 offset -= SUBREG_WORD (setreg);
1618 setreg = SUBREG_REG (setreg);
1620 if (GET_CODE (setreg) != REG)
1622 sreg = REGNO (setreg);
1623 ssize = REG_SIZE (setreg);
1625 /* If UREG is a pseudo-register that hasn't already been assigned a
1626 quantity number, it means that it is not local to this block or dies
1627 more than once. In either event, we can't do anything with it. */
1628 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1629 /* Do not combine registers unless one fits within the other. */
1630 || (offset > 0 && usize + offset > ssize)
1631 || (offset < 0 && usize + offset < ssize)
1632 /* Do not combine with a smaller already-assigned object
1633 if that smaller object is already combined with something bigger. */
1634 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1635 && usize < qty_size[reg_qty[ureg]])
1636 /* Can't combine if SREG is not a register we can allocate. */
1637 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1638 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1639 These have already been taken care of. This probably wouldn't
1640 combine anyway, but don't take any chances. */
1641 || (ureg >= FIRST_PSEUDO_REGISTER
1642 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1643 /* Don't tie something to itself. In most cases it would make no
1644 difference, but it would screw up if the reg being tied to itself
1645 also dies in this insn. */
1647 /* Don't try to connect two different hardware registers. */
1648 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1649 /* Don't connect two different machine modes if they have different
1650 implications as to which registers may be used. */
1651 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1654 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1655 qty_phys_sugg for the pseudo instead of tying them.
1657 Return "failure" so that the lifespan of UREG is terminated here;
1658 that way the two lifespans will be disjoint and nothing will prevent
1659 the pseudo reg from being given this hard reg. */
1661 if (ureg < FIRST_PSEUDO_REGISTER)
1663 /* Allocate a quantity number so we have a place to put our
1665 if (reg_qty[sreg] == -2)
1666 reg_is_born (setreg, 2 * insn_number);
1668 if (reg_qty[sreg] >= 0)
1671 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1673 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1674 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1676 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1678 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1679 qty_phys_num_sugg[reg_qty[sreg]]++;
1685 /* Similarly for SREG a hard register and UREG a pseudo register. */
1687 if (sreg < FIRST_PSEUDO_REGISTER)
1690 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1692 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1693 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1695 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1697 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1698 qty_phys_num_sugg[reg_qty[ureg]]++;
1703 /* At this point we know that SREG and UREG are both pseudos.
1704 Do nothing if SREG already has a quantity or is a register that we
1706 if (reg_qty[sreg] >= -1
1707 /* If we are not going to let any regs live across calls,
1708 don't tie a call-crossing reg to a non-call-crossing reg. */
1709 || (current_function_has_nonlocal_label
1710 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1711 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1714 /* We don't already know about SREG, so tie it to UREG
1715 if this is the last use of UREG, provided the classes they want
1718 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1719 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1721 /* Add SREG to UREG's quantity. */
1722 sqty = reg_qty[ureg];
1723 reg_qty[sreg] = sqty;
1724 reg_offset[sreg] = reg_offset[ureg] + offset;
1725 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1726 qty_first_reg[sqty] = sreg;
1728 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1729 update_qty_class (sqty, sreg);
1731 /* Update info about quantity SQTY. */
1732 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1733 qty_n_refs[sqty] += REG_N_REFS (sreg);
1738 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1739 reg_offset[i] -= offset;
1741 qty_size[sqty] = ssize;
1742 qty_mode[sqty] = GET_MODE (setreg);
1751 /* Return 1 if the preferred class of REG allows it to be tied
1752 to a quantity or register whose class is CLASS.
1753 True if REG's reg class either contains or is contained in CLASS. */
1756 reg_meets_class_p (reg, class)
1758 enum reg_class class;
1760 register enum reg_class rclass = reg_preferred_class (reg);
1761 return (reg_class_subset_p (rclass, class)
1762 || reg_class_subset_p (class, rclass));
1765 /* Update the class of QTY assuming that REG is being tied to it. */
1768 update_qty_class (qty, reg)
1772 enum reg_class rclass = reg_preferred_class (reg);
1773 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1774 qty_min_class[qty] = rclass;
1776 rclass = reg_alternate_class (reg);
1777 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1778 qty_alternate_class[qty] = rclass;
1780 if (REG_CHANGES_SIZE (reg))
1781 qty_changes_size[qty] = 1;
1784 /* Handle something which alters the value of an rtx REG.
1786 REG is whatever is set or clobbered. SETTER is the rtx that
1787 is modifying the register.
1789 If it is not really a register, we do nothing.
1790 The file-global variables `this_insn' and `this_insn_number'
1791 carry info from `block_alloc'. */
1794 reg_is_set (reg, setter)
1798 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1799 a hard register. These may actually not exist any more. */
1801 if (GET_CODE (reg) != SUBREG
1802 && GET_CODE (reg) != REG)
1805 /* Mark this register as being born. If it is used in a CLOBBER, mark
1806 it as being born halfway between the previous insn and this insn so that
1807 it conflicts with our inputs but not the outputs of the previous insn. */
1809 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1812 /* Handle beginning of the life of register REG.
1813 BIRTH is the index at which this is happening. */
1816 reg_is_born (reg, birth)
1822 if (GET_CODE (reg) == SUBREG)
1823 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1825 regno = REGNO (reg);
1827 if (regno < FIRST_PSEUDO_REGISTER)
1829 mark_life (regno, GET_MODE (reg), 1);
1831 /* If the register was to have been born earlier that the present
1832 insn, mark it as live where it is actually born. */
1833 if (birth < 2 * this_insn_number)
1834 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1838 if (reg_qty[regno] == -2)
1839 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1841 /* If this register has a quantity number, show that it isn't dead. */
1842 if (reg_qty[regno] >= 0)
1843 qty_death[reg_qty[regno]] = -1;
1847 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1848 REG is an output that is dying (i.e., it is never used), otherwise it
1849 is an input (the normal case).
1850 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1853 wipe_dead_reg (reg, output_p)
1857 register int regno = REGNO (reg);
1859 /* If this insn has multiple results,
1860 and the dead reg is used in one of the results,
1861 extend its life to after this insn,
1862 so it won't get allocated together with any other result of this insn. */
1863 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1864 && !single_set (this_insn))
1867 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1869 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1870 if (GET_CODE (set) == SET
1871 && GET_CODE (SET_DEST (set)) != REG
1872 && !rtx_equal_p (reg, SET_DEST (set))
1873 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1878 /* If this register is used in an auto-increment address, then extend its
1879 life to after this insn, so that it won't get allocated together with
1880 the result of this insn. */
1881 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1884 if (regno < FIRST_PSEUDO_REGISTER)
1886 mark_life (regno, GET_MODE (reg), 0);
1888 /* If a hard register is dying as an output, mark it as in use at
1889 the beginning of this insn (the above statement would cause this
1892 post_mark_life (regno, GET_MODE (reg), 1,
1893 2 * this_insn_number, 2 * this_insn_number+ 1);
1896 else if (reg_qty[regno] >= 0)
1897 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1900 /* Find a block of SIZE words of hard regs in reg_class CLASS
1901 that can hold something of machine-mode MODE
1902 (but actually we test only the first of the block for holding MODE)
1903 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1904 and return the number of the first of them.
1905 Return -1 if such a block cannot be found.
1906 If QTY crosses calls, insist on a register preserved by calls,
1907 unless ACCEPT_CALL_CLOBBERED is nonzero.
1909 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1910 register is available. If not, return -1. */
1913 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1914 born_index, dead_index)
1915 enum reg_class class;
1916 enum machine_mode mode;
1918 int accept_call_clobbered;
1919 int just_try_suggested;
1920 int born_index, dead_index;
1922 register int i, ins;
1924 register /* Declare it register if it's a scalar. */
1926 HARD_REG_SET used, first_used;
1927 #ifdef ELIMINABLE_REGS
1928 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1931 /* Validate our parameters. */
1932 if (born_index < 0 || born_index > dead_index)
1935 /* Don't let a pseudo live in a reg across a function call
1936 if we might get a nonlocal goto. */
1937 if (current_function_has_nonlocal_label
1938 && qty_n_calls_crossed[qty] > 0)
1941 if (accept_call_clobbered)
1942 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1943 else if (qty_n_calls_crossed[qty] == 0)
1944 COPY_HARD_REG_SET (used, fixed_reg_set);
1946 COPY_HARD_REG_SET (used, call_used_reg_set);
1948 if (accept_call_clobbered)
1949 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1951 for (ins = born_index; ins < dead_index; ins++)
1952 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1954 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1956 /* Don't use the frame pointer reg in local-alloc even if
1957 we may omit the frame pointer, because if we do that and then we
1958 need a frame pointer, reload won't know how to move the pseudo
1959 to another hard reg. It can move only regs made by global-alloc.
1961 This is true of any register that can be eliminated. */
1962 #ifdef ELIMINABLE_REGS
1963 for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++)
1964 SET_HARD_REG_BIT (used, eliminables[i].from);
1965 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1966 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1967 that it might be eliminated into. */
1968 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1971 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1974 #ifdef CLASS_CANNOT_CHANGE_SIZE
1975 if (qty_changes_size[qty])
1976 IOR_HARD_REG_SET (used,
1977 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
1980 /* Normally, the registers that can be used for the first register in
1981 a multi-register quantity are the same as those that can be used for
1982 subsequent registers. However, if just trying suggested registers,
1983 restrict our consideration to them. If there are copy-suggested
1984 register, try them. Otherwise, try the arithmetic-suggested
1986 COPY_HARD_REG_SET (first_used, used);
1988 if (just_try_suggested)
1990 if (qty_phys_num_copy_sugg[qty] != 0)
1991 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
1993 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
1996 /* If all registers are excluded, we can't do anything. */
1997 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
1999 /* If at least one would be suitable, test each hard reg. */
2001 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2003 #ifdef REG_ALLOC_ORDER
2004 int regno = reg_alloc_order[i];
2008 if (! TEST_HARD_REG_BIT (first_used, regno)
2009 && HARD_REGNO_MODE_OK (regno, mode)
2010 && (qty_n_calls_crossed[qty] == 0
2011 || accept_call_clobbered
2012 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2015 register int size1 = HARD_REGNO_NREGS (regno, mode);
2016 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2019 /* Mark that this register is in use between its birth and death
2021 post_mark_life (regno, mode, 1, born_index, dead_index);
2024 #ifndef REG_ALLOC_ORDER
2025 i += j; /* Skip starting points we know will lose */
2032 /* If we are just trying suggested register, we have just tried copy-
2033 suggested registers, and there are arithmetic-suggested registers,
2036 /* If it would be profitable to allocate a call-clobbered register
2037 and save and restore it around calls, do that. */
2038 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2039 && qty_phys_num_sugg[qty] != 0)
2041 /* Don't try the copy-suggested regs again. */
2042 qty_phys_num_copy_sugg[qty] = 0;
2043 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2044 born_index, dead_index);
2047 /* We need not check to see if the current function has nonlocal
2048 labels because we don't put any pseudos that are live over calls in
2049 registers in that case. */
2051 if (! accept_call_clobbered
2052 && flag_caller_saves
2053 && ! just_try_suggested
2054 && qty_n_calls_crossed[qty] != 0
2055 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2057 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2059 caller_save_needed = 1;
2065 /* Mark that REGNO with machine-mode MODE is live starting from the current
2066 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2070 mark_life (regno, mode, life)
2072 enum machine_mode mode;
2075 register int j = HARD_REGNO_NREGS (regno, mode);
2078 SET_HARD_REG_BIT (regs_live, regno + j);
2081 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2084 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2085 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2086 to insn number DEATH (exclusive). */
2089 post_mark_life (regno, mode, life, birth, death)
2091 enum machine_mode mode;
2092 int life, birth, death;
2094 register int j = HARD_REGNO_NREGS (regno, mode);
2096 register /* Declare it register if it's a scalar. */
2098 HARD_REG_SET this_reg;
2100 CLEAR_HARD_REG_SET (this_reg);
2102 SET_HARD_REG_BIT (this_reg, regno + j);
2105 while (birth < death)
2107 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2111 while (birth < death)
2113 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2118 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2119 is the register being clobbered, and R1 is a register being used in
2120 the equivalent expression.
2122 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2123 in which it is used, return 1.
2125 Otherwise, return 0. */
2128 no_conflict_p (insn, r0, r1)
2132 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2135 /* If R1 is a hard register, return 0 since we handle this case
2136 when we scan the insns that actually use it. */
2139 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2140 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2141 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2144 last = XEXP (note, 0);
2146 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2147 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2149 if (find_reg_note (p, REG_DEAD, r1))
2152 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2153 some earlier optimization pass has inserted instructions into
2154 the sequence, and it is not safe to perform this optimization.
2155 Note that emit_no_conflict_block always ensures that this is
2156 true when these sequences are created. */
2157 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2164 #ifdef REGISTER_CONSTRAINTS
2166 /* Return the number of alternatives for which the constraint string P
2167 indicates that the operand must be equal to operand 0 and that no register
2176 int reg_allowed = 0;
2177 int num_matching_alts = 0;
2182 case '=': case '+': case '?':
2183 case '#': case '&': case '!':
2185 case '1': case '2': case '3': case '4':
2186 case 'm': case '<': case '>': case 'V': case 'o':
2187 case 'E': case 'F': case 'G': case 'H':
2188 case 's': case 'i': case 'n':
2189 case 'I': case 'J': case 'K': case 'L':
2190 case 'M': case 'N': case 'O': case 'P':
2191 #ifdef EXTRA_CONSTRAINT
2192 case 'Q': case 'R': case 'S': case 'T': case 'U':
2195 /* These don't say anything we care about. */
2199 if (found_zero && ! reg_allowed)
2200 num_matching_alts++;
2202 found_zero = reg_allowed = 0;
2216 if (found_zero && ! reg_allowed)
2217 num_matching_alts++;
2219 return num_matching_alts;
2221 #endif /* REGISTER_CONSTRAINTS */
2224 dump_local_alloc (file)
2228 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2229 if (reg_renumber[i] != -1)
2230 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);