1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "basic-block.h"
70 #include "hard-reg-set.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* Information we maitain about each quantity. */
84 /* The number of refs to quantity Q. */
88 /* Insn number (counting from head of basic block)
89 where quantity Q was born. -1 if birth has not been recorded. */
93 /* Insn number (counting from head of basic block)
94 where given quantity died. Due to the way tying is done,
95 and the fact that we consider in this pass only regs that die but once,
96 a quantity can die only once. Each quantity's life span
97 is a set of consecutive insns. -1 if death has not been recorded. */
101 /* Number of words needed to hold the data in given quantity.
102 This depends on its machine mode. It is used for these purposes:
103 1. It is used in computing the relative importances of qtys,
104 which determines the order in which we look for regs for them.
105 2. It is used in rules that prevent tying several registers of
106 different sizes in a way that is geometrically impossible
107 (see combine_regs). */
111 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
115 /* The register number of one pseudo register whose reg_qty value is Q.
116 This register should be the head of the chain
117 maintained in reg_next_in_qty. */
121 /* Reg class contained in (smaller than) the preferred classes of all
122 the pseudo regs that are tied in given quantity.
123 This is the preferred class for allocating that quantity. */
125 enum reg_class min_class;
127 /* Register class within which we allocate given qty if we can't get
128 its preferred class. */
130 enum reg_class alternate_class;
132 /* This holds the mode of the registers that are tied to given qty,
133 or VOIDmode if registers with differing modes are tied together. */
135 enum machine_mode mode;
137 /* the hard reg number chosen for given quantity,
138 or -1 if none was found. */
142 /* Nonzero if this quantity has been used in a SUBREG that changes
149 static struct qty *qty;
151 /* These fields are kept separately to speedup their clearing. */
153 /* We maintain two hard register sets that indicate suggested hard registers
154 for each quantity. The first, phys_copy_sugg, contains hard registers
155 that are tied to the quantity by a simple copy. The second contains all
156 hard registers that are tied to the quantity via an arithmetic operation.
158 The former register set is given priority for allocation. This tends to
159 eliminate copy insns. */
161 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 static HARD_REG_SET *qty_phys_copy_sugg;
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET *qty_phys_sugg;
171 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
173 static short *qty_phys_num_copy_sugg;
175 /* Element Q is the number of suggested registers in qty_phys_sugg. */
177 static short *qty_phys_num_sugg;
180 /* If (REG N) has been assigned a quantity number, is a register number
181 of another register assigned the same quantity number, or -1 for the
182 end of the chain. qty->first_reg point to the head of this chain. */
184 static int *reg_next_in_qty;
186 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
188 of -1 if this register cannot be allocated by local-alloc,
189 or -2 if not known yet.
191 Note that if we see a use or death of pseudo register N with
192 reg_qty[N] == -2, register N must be local to the current block. If
193 it were used in more than one block, we would have reg_qty[N] == -1.
194 This relies on the fact that if reg_basic_block[N] is >= 0, register N
195 will not appear in any other block. We save a considerable number of
196 tests by exploiting this.
198 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
203 /* The offset (in words) of register N within its quantity.
204 This can be nonzero if register N is SImode, and has been tied
205 to a subreg of a DImode register. */
207 static char *reg_offset;
209 /* Vector of substitutions of register numbers,
210 used to map pseudo regs into hardware regs.
211 This is set up as a result of register allocation.
212 Element N is the hard reg assigned to pseudo reg N,
213 or is -1 if no hard reg was assigned.
214 If N is a hard reg number, element N is N. */
218 /* Set of hard registers live at the current point in the scan
219 of the instructions in a basic block. */
221 static HARD_REG_SET regs_live;
223 /* Each set of hard registers indicates registers live at a particular
224 point in the basic block. For N even, regs_live_at[N] says which
225 hard registers are needed *after* insn N/2 (i.e., they may not
226 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
228 If an object is to conflict with the inputs of insn J but not the
229 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
230 if it is to conflict with the outputs of insn J but not the inputs of
231 insn J + 1, it is said to die at index J*2 + 1. */
233 static HARD_REG_SET *regs_live_at;
235 /* Communicate local vars `insn_number' and `insn'
236 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
237 static int this_insn_number;
238 static rtx this_insn;
240 /* Used to communicate changes made by update_equiv_regs to
241 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
242 found or created, so that we can keep track of what memory accesses might
243 be created later, e.g. by reload. */
245 static rtx *reg_equiv_replacement;
247 /* Used for communication between update_equiv_regs and no_equiv. */
248 static rtx *reg_equiv_init_insns;
250 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
251 static int recorded_label_ref;
253 static void alloc_qty PROTO((int, enum machine_mode, int, int));
254 static void validate_equiv_mem_from_store PROTO((rtx, rtx, void *));
255 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
256 static int contains_replace_regs PROTO((rtx, char *));
257 static int memref_referenced_p PROTO((rtx, rtx));
258 static int memref_used_between_p PROTO((rtx, rtx, rtx));
259 static void update_equiv_regs PROTO((void));
260 static void no_equiv PROTO((rtx, rtx, void *));
261 static void block_alloc PROTO((int));
262 static int qty_sugg_compare PROTO((int, int));
263 static int qty_sugg_compare_1 PROTO((const PTR, const PTR));
264 static int qty_compare PROTO((int, int));
265 static int qty_compare_1 PROTO((const PTR, const PTR));
266 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
267 static int reg_meets_class_p PROTO((int, enum reg_class));
268 static void update_qty_class PROTO((int, int));
269 static void reg_is_set PROTO((rtx, rtx, void *));
270 static void reg_is_born PROTO((rtx, int));
271 static void wipe_dead_reg PROTO((rtx, int));
272 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
273 int, int, int, int, int));
274 static void mark_life PROTO((int, enum machine_mode, int));
275 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
276 static int no_conflict_p PROTO((rtx, rtx, rtx));
277 static int requires_inout PROTO((const char *));
279 /* Allocate a new quantity (new within current basic block)
280 for register number REGNO which is born at index BIRTH
281 within the block. MODE and SIZE are info on reg REGNO. */
284 alloc_qty (regno, mode, size, birth)
286 enum machine_mode mode;
289 register int qtyno = next_qty++;
291 reg_qty[regno] = qtyno;
292 reg_offset[regno] = 0;
293 reg_next_in_qty[regno] = -1;
295 qty[qtyno].first_reg = regno;
296 qty[qtyno].size = size;
297 qty[qtyno].mode = mode;
298 qty[qtyno].birth = birth;
299 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
300 qty[qtyno].min_class = reg_preferred_class (regno);
301 qty[qtyno].alternate_class = reg_alternate_class (regno);
302 qty[qtyno].n_refs = REG_N_REFS (regno);
303 qty[qtyno].changes_size = REG_CHANGES_SIZE (regno);
306 /* Main entry point of this file. */
314 /* We need to keep track of whether or not we recorded a LABEL_REF so
315 that we know if the jump optimizer needs to be rerun. */
316 recorded_label_ref = 0;
318 /* Leaf functions and non-leaf functions have different needs.
319 If defined, let the machine say what kind of ordering we
321 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
322 ORDER_REGS_FOR_LOCAL_ALLOC;
325 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
327 update_equiv_regs ();
329 /* This sets the maximum number of quantities we can have. Quantity
330 numbers start at zero and we can have one for each pseudo. */
331 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
333 /* Allocate vectors of temporary data.
334 See the declarations of these variables, above,
335 for what they mean. */
337 qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty));
339 = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
340 qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short));
341 qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
342 qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short));
344 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
345 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
346 reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int));
348 /* Allocate the reg_renumber array */
349 allocate_reg_info (max_regno, FALSE, TRUE);
351 /* Determine which pseudo-registers can be allocated by local-alloc.
352 In general, these are the registers used only in a single block and
353 which only die once. However, if a register's preferred class has only
354 a few entries, don't allocate this register here unless it is preferred
355 or nothing since retry_global_alloc won't be able to move it to
356 GENERAL_REGS if a reload register of this class is needed.
358 We need not be concerned with which block actually uses the register
359 since we will never see it outside that block. */
361 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
363 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
364 && (reg_alternate_class (i) == NO_REGS
365 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
371 /* Force loop below to initialize entire quantity array. */
374 /* Allocate each block's local registers, block by block. */
376 for (b = 0; b < n_basic_blocks; b++)
378 /* NEXT_QTY indicates which elements of the `qty_...'
379 vectors might need to be initialized because they were used
380 for the previous block; it is set to the entire array before
381 block 0. Initialize those, with explicit loop if there are few,
382 else with bzero and bcopy. Do not initialize vectors that are
383 explicit set by `alloc_qty'. */
387 for (i = 0; i < next_qty; i++)
389 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
390 qty_phys_num_copy_sugg[i] = 0;
391 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
392 qty_phys_num_sugg[i] = 0;
397 #define CLEAR(vector) \
398 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
400 CLEAR (qty_phys_copy_sugg);
401 CLEAR (qty_phys_num_copy_sugg);
402 CLEAR (qty_phys_sugg);
403 CLEAR (qty_phys_num_sugg);
412 free (qty_phys_copy_sugg);
413 free (qty_phys_num_copy_sugg);
414 free (qty_phys_sugg);
415 free (qty_phys_num_sugg);
419 free (reg_next_in_qty);
421 return recorded_label_ref;
424 /* Depth of loops we are in while in update_equiv_regs. */
425 static int loop_depth;
427 /* Used for communication between the following two functions: contains
428 a MEM that we wish to ensure remains unchanged. */
429 static rtx equiv_mem;
431 /* Set nonzero if EQUIV_MEM is modified. */
432 static int equiv_mem_modified;
434 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
435 Called via note_stores. */
438 validate_equiv_mem_from_store (dest, set, data)
440 rtx set ATTRIBUTE_UNUSED;
441 void *data ATTRIBUTE_UNUSED;
443 if ((GET_CODE (dest) == REG
444 && reg_overlap_mentioned_p (dest, equiv_mem))
445 || (GET_CODE (dest) == MEM
446 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
447 equiv_mem_modified = 1;
450 /* Verify that no store between START and the death of REG invalidates
451 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
452 by storing into an overlapping memory location, or with a non-const
455 Return 1 if MEMREF remains valid. */
458 validate_equiv_mem (start, reg, memref)
467 equiv_mem_modified = 0;
469 /* If the memory reference has side effects or is volatile, it isn't a
470 valid equivalence. */
471 if (side_effects_p (memref))
474 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
476 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
479 if (find_reg_note (insn, REG_DEAD, reg))
482 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
483 && ! CONST_CALL_P (insn))
486 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
488 /* If a register mentioned in MEMREF is modified via an
489 auto-increment, we lose the equivalence. Do the same if one
490 dies; although we could extend the life, it doesn't seem worth
493 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
494 if ((REG_NOTE_KIND (note) == REG_INC
495 || REG_NOTE_KIND (note) == REG_DEAD)
496 && GET_CODE (XEXP (note, 0)) == REG
497 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
504 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
507 contains_replace_regs (x, reg_equiv_replace)
509 char *reg_equiv_replace;
513 enum rtx_code code = GET_CODE (x);
529 return reg_equiv_replace[REGNO (x)];
535 fmt = GET_RTX_FORMAT (code);
536 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
540 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
544 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
545 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
553 /* TRUE if X references a memory location that would be affected by a store
557 memref_referenced_p (memref, x)
563 enum rtx_code code = GET_CODE (x);
579 return (reg_equiv_replacement[REGNO (x)]
580 && memref_referenced_p (memref,
581 reg_equiv_replacement[REGNO (x)]));
584 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
589 /* If we are setting a MEM, it doesn't count (its address does), but any
590 other SET_DEST that has a MEM in it is referencing the MEM. */
591 if (GET_CODE (SET_DEST (x)) == MEM)
593 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
596 else if (memref_referenced_p (memref, SET_DEST (x)))
599 return memref_referenced_p (memref, SET_SRC (x));
605 fmt = GET_RTX_FORMAT (code);
606 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
610 if (memref_referenced_p (memref, XEXP (x, i)))
614 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
615 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
623 /* TRUE if some insn in the range (START, END] references a memory location
624 that would be affected by a store to MEMREF. */
627 memref_used_between_p (memref, start, end)
634 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
635 insn = NEXT_INSN (insn))
636 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
637 && memref_referenced_p (memref, PATTERN (insn)))
643 /* Return nonzero if the rtx X is invariant over the current function. */
645 function_invariant_p (x)
650 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
652 if (GET_CODE (x) == PLUS
653 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
654 && CONSTANT_P (XEXP (x, 1)))
659 /* Find registers that are equivalent to a single value throughout the
660 compilation (either because they can be referenced in memory or are set once
661 from a single constant). Lower their priority for a register.
663 If such a register is only referenced once, try substituting its value
664 into the using insn. If it succeeds, we can eliminate the register
670 /* Set when an attempt should be made to replace a register with the
671 associated reg_equiv_replacement entry at the end of this function. */
672 char *reg_equiv_replace;
676 reg_equiv_replace = (char *) xcalloc (max_regno, sizeof *reg_equiv_replace);
677 reg_equiv_init_insns = (rtx *) xcalloc (max_regno, sizeof (rtx));
678 reg_equiv_replacement = (rtx *) xcalloc (max_regno, sizeof (rtx));
680 init_alias_analysis ();
684 /* Scan the insns and find which registers have equivalences. Do this
685 in a separate scan of the insns because (due to -fcse-follow-jumps)
686 a register can be set below its use. */
687 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
694 if (GET_CODE (insn) == NOTE)
696 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
698 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
702 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
705 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
706 if (REG_NOTE_KIND (note) == REG_INC)
707 no_equiv (XEXP (note, 0), note, NULL);
709 set = single_set (insn);
711 /* If this insn contains more (or less) than a single SET,
712 only mark all destinations as having no known equivalence. */
715 note_stores (PATTERN (insn), no_equiv, NULL);
718 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
722 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
724 rtx part = XVECEXP (PATTERN (insn), 0, i);
726 note_stores (part, no_equiv, NULL);
730 dest = SET_DEST (set);
733 /* If this sets a MEM to the contents of a REG that is only used
734 in a single basic block, see if the register is always equivalent
735 to that memory location and if moving the store from INSN to the
736 insn that set REG is safe. If so, put a REG_EQUIV note on the
739 Don't add a REG_EQUIV note if the insn already has one. The existing
740 REG_EQUIV is likely more useful than the one we are adding.
742 If one of the regs in the address is marked as reg_equiv_replace,
743 then we can't add this REG_EQUIV note. The reg_equiv_replace
744 optimization may move the set of this register immediately before
745 insn, which puts it after reg_equiv_init_insns[regno], and hence
746 the mention in the REG_EQUIV note would be to an uninitialized
748 /* ????? This test isn't good enough; we might see a MEM with a use of
749 a pseudo register before we see its setting insn that will cause
750 reg_equiv_replace for that pseudo to be set.
751 Equivalences to MEMs should be made in another pass, after the
752 reg_equiv_replace information has been gathered. */
754 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
755 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
756 && REG_BASIC_BLOCK (regno) >= 0
757 && REG_N_SETS (regno) == 1
758 && reg_equiv_init_insns[regno] != 0
759 && reg_equiv_init_insns[regno] != const0_rtx
760 && ! find_reg_note (XEXP (reg_equiv_init_insns[regno], 0),
762 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))
764 rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);
765 if (validate_equiv_mem (init_insn, src, dest)
766 && ! memref_used_between_p (dest, init_insn, insn))
767 REG_NOTES (init_insn)
768 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
771 /* We only handle the case of a pseudo register being set
772 once, or always to the same value. */
773 /* ??? The mn10200 port breaks if we add equivalences for
774 values that need an ADDRESS_REGS register and set them equivalent
775 to a MEM of a pseudo. The actual problem is in the over-conservative
776 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
777 calculate_needs, but we traditionally work around this problem
778 here by rejecting equivalences when the destination is in a register
779 that's likely spilled. This is fragile, of course, since the
780 preferred class of a pseudo depends on all instructions that set
783 if (GET_CODE (dest) != REG
784 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
785 || reg_equiv_init_insns[regno] == const0_rtx
786 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
787 && GET_CODE (src) == MEM))
789 /* This might be seting a SUBREG of a pseudo, a pseudo that is
790 also set somewhere else to a constant. */
791 note_stores (set, no_equiv, NULL);
794 /* Don't handle the equivalence if the source is in a register
795 class that's likely to be spilled. */
796 if (GET_CODE (src) == REG
797 && REGNO (src) >= FIRST_PSEUDO_REGISTER
798 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src))))
800 no_equiv (dest, set, NULL);
804 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
806 if (REG_N_SETS (regno) != 1
808 || ! function_invariant_p (XEXP (note, 0))
809 || (reg_equiv_replacement[regno]
810 && ! rtx_equal_p (XEXP (note, 0),
811 reg_equiv_replacement[regno]))))
813 no_equiv (dest, set, NULL);
816 /* Record this insn as initializing this register. */
817 reg_equiv_init_insns[regno]
818 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]);
820 /* If this register is known to be equal to a constant, record that
821 it is always equivalent to the constant. */
822 if (note && function_invariant_p (XEXP (note, 0)))
823 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
825 /* If this insn introduces a "constant" register, decrease the priority
826 of that register. Record this insn if the register is only used once
827 more and the equivalence value is the same as our source.
829 The latter condition is checked for two reasons: First, it is an
830 indication that it may be more efficient to actually emit the insn
831 as written (if no registers are available, reload will substitute
832 the equivalence). Secondly, it avoids problems with any registers
833 dying in this insn whose death notes would be missed.
835 If we don't have a REG_EQUIV note, see if this insn is loading
836 a register used only in one basic block from a MEM. If so, and the
837 MEM remains unchanged for the life of the register, add a REG_EQUIV
840 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
842 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
843 && GET_CODE (SET_SRC (set)) == MEM
844 && validate_equiv_mem (insn, dest, SET_SRC (set)))
845 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
850 int regno = REGNO (dest);
852 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
853 We might end up substituting the LABEL_REF for uses of the
854 pseudo here or later. That kind of transformation may turn an
855 indirect jump into a direct jump, in which case we must rerun the
856 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
857 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
858 || (GET_CODE (XEXP (note, 0)) == CONST
859 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
860 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
862 recorded_label_ref = 1;
865 reg_equiv_replacement[regno] = XEXP (note, 0);
867 /* Don't mess with things live during setjmp. */
868 if (REG_LIVE_LENGTH (regno) >= 0)
870 /* Note that the statement below does not affect the priority
872 REG_LIVE_LENGTH (regno) *= 2;
875 /* If the register is referenced exactly twice, meaning it is
876 set once and used once, indicate that the reference may be
877 replaced by the equivalence we computed above. If the
878 register is only used in one basic block, this can't succeed
879 or combine would have done it.
881 It would be nice to use "loop_depth * 2" in the compare
882 below. Unfortunately, LOOP_DEPTH need not be constant within
883 a basic block so this would be too complicated.
885 This case normally occurs when a parameter is read from
886 memory and then used exactly once, not in a loop. */
888 if (REG_N_REFS (regno) == 2
889 && REG_BASIC_BLOCK (regno) < 0
890 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
891 reg_equiv_replace[regno] = 1;
896 /* Now scan all regs killed in an insn to see if any of them are
897 registers only used that once. If so, see if we can replace the
898 reference with the equivalent from. If we can, delete the
899 initializing reference and this register will go away. If we
900 can't replace the reference, and the instruction is not in a
901 loop, then move the register initialization just before the use,
902 so that they are in the same basic block. */
905 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
909 /* Keep track of which basic block we are in. */
910 if (block + 1 < n_basic_blocks
911 && BLOCK_HEAD (block + 1) == insn)
914 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
916 if (GET_CODE (insn) == NOTE)
918 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
920 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
931 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
933 if (REG_NOTE_KIND (link) == REG_DEAD
934 /* Make sure this insn still refers to the register. */
935 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
937 int regno = REGNO (XEXP (link, 0));
940 if (! reg_equiv_replace[regno])
943 /* reg_equiv_replace[REGNO] gets set only when
944 REG_N_REFS[REGNO] is 2, i.e. the register is set
945 once and used once. (If it were only set, but not used,
946 flow would have deleted the setting insns.) Hence
947 there can only be one insn in reg_equiv_init_insns. */
948 equiv_insn = XEXP (reg_equiv_init_insns[regno], 0);
950 if (validate_replace_rtx (regno_reg_rtx[regno],
951 reg_equiv_replacement[regno], insn))
953 remove_death (regno, insn);
954 REG_N_REFS (regno) = 0;
955 PUT_CODE (equiv_insn, NOTE);
956 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
957 NOTE_SOURCE_FILE (equiv_insn) = 0;
959 /* If we aren't in a loop, and there are no calls in
960 INSN or in the initialization of the register, then
961 move the initialization of the register to just
962 before INSN. Update the flow information. */
964 && GET_CODE (equiv_insn) == INSN
965 && GET_CODE (insn) == INSN
966 && REG_BASIC_BLOCK (regno) < 0)
970 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
971 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
972 REG_NOTES (equiv_insn) = 0;
974 PUT_CODE (equiv_insn, NOTE);
975 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
976 NOTE_SOURCE_FILE (equiv_insn) = 0;
979 REG_BASIC_BLOCK (regno) = 0;
981 REG_BASIC_BLOCK (regno) = block;
982 REG_N_CALLS_CROSSED (regno) = 0;
983 REG_LIVE_LENGTH (regno) = 2;
985 if (block >= 0 && insn == BLOCK_HEAD (block))
986 BLOCK_HEAD (block) = PREV_INSN (insn);
988 for (l = 0; l < n_basic_blocks; l++)
989 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start,
997 end_alias_analysis ();
998 free (reg_equiv_replace);
999 free (reg_equiv_init_insns);
1000 free (reg_equiv_replacement);
1003 /* Mark REG as having no known equivalence.
1004 Some instructions might have been proceessed before and furnished
1005 with REG_EQUIV notes for this register; these notes will have to be
1007 STORE is the piece of RTL that does the non-constant / conflicting
1008 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1009 but needs to be there because this function is called from note_stores. */
1011 no_equiv (reg, store, data)
1012 rtx reg, store ATTRIBUTE_UNUSED;
1013 void *data ATTRIBUTE_UNUSED;
1018 if (GET_CODE (reg) != REG)
1020 regno = REGNO (reg);
1021 list = reg_equiv_init_insns[regno];
1022 if (list == const0_rtx)
1024 for (; list; list = XEXP (list, 1))
1026 rtx insn = XEXP (list, 0);
1027 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1029 reg_equiv_init_insns[regno] = const0_rtx;
1030 reg_equiv_replacement[regno] = NULL_RTX;
1033 /* Allocate hard regs to the pseudo regs used only within block number B.
1034 Only the pseudos that die but once can be handled. */
1043 int insn_number = 0;
1045 int max_uid = get_max_uid ();
1047 int no_conflict_combined_regno = -1;
1049 /* Count the instructions in the basic block. */
1051 insn = BLOCK_END (b);
1054 if (GET_CODE (insn) != NOTE)
1055 if (++insn_count > max_uid)
1057 if (insn == BLOCK_HEAD (b))
1059 insn = PREV_INSN (insn);
1062 /* +2 to leave room for a post_mark_life at the last insn and for
1063 the birth of a CLOBBER in the first insn. */
1064 regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2),
1065 sizeof (HARD_REG_SET));
1067 /* Initialize table of hardware registers currently live. */
1069 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1071 /* This loop scans the instructions of the basic block
1072 and assigns quantities to registers.
1073 It computes which registers to tie. */
1075 insn = BLOCK_HEAD (b);
1078 if (GET_CODE (insn) != NOTE)
1081 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1083 register rtx link, set;
1084 register int win = 0;
1085 register rtx r0, r1;
1086 int combined_regno = -1;
1089 this_insn_number = insn_number;
1092 extract_insn (insn);
1093 which_alternative = -1;
1095 /* Is this insn suitable for tying two registers?
1096 If so, try doing that.
1097 Suitable insns are those with at least two operands and where
1098 operand 0 is an output that is a register that is not
1101 We can tie operand 0 with some operand that dies in this insn.
1102 First look for operands that are required to be in the same
1103 register as operand 0. If we find such, only try tying that
1104 operand or one that can be put into that operand if the
1105 operation is commutative. If we don't find an operand
1106 that is required to be in the same register as operand 0,
1107 we can tie with any operand.
1109 Subregs in place of regs are also ok.
1111 If tying is done, WIN is set nonzero. */
1113 if (recog_data.n_operands > 1
1114 && recog_data.constraints[0][0] == '='
1115 && recog_data.constraints[0][1] != '&')
1117 /* If non-negative, is an operand that must match operand 0. */
1118 int must_match_0 = -1;
1119 /* Counts number of alternatives that require a match with
1121 int n_matching_alts = 0;
1123 for (i = 1; i < recog_data.n_operands; i++)
1125 const char *p = recog_data.constraints[i];
1126 int this_match = (requires_inout (p));
1128 n_matching_alts += this_match;
1129 if (this_match == recog_data.n_alternatives)
1133 r0 = recog_data.operand[0];
1134 for (i = 1; i < recog_data.n_operands; i++)
1136 /* Skip this operand if we found an operand that
1137 must match operand 0 and this operand isn't it
1138 and can't be made to be it by commutativity. */
1140 if (must_match_0 >= 0 && i != must_match_0
1141 && ! (i == must_match_0 + 1
1142 && recog_data.constraints[i-1][0] == '%')
1143 && ! (i == must_match_0 - 1
1144 && recog_data.constraints[i][0] == '%'))
1147 /* Likewise if each alternative has some operand that
1148 must match operand zero. In that case, skip any
1149 operand that doesn't list operand 0 since we know that
1150 the operand always conflicts with operand 0. We
1151 ignore commutatity in this case to keep things simple. */
1152 if (n_matching_alts == recog_data.n_alternatives
1153 && 0 == requires_inout (recog_data.constraints[i]))
1156 r1 = recog_data.operand[i];
1158 /* If the operand is an address, find a register in it.
1159 There may be more than one register, but we only try one
1161 if (recog_data.constraints[i][0] == 'p')
1162 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1165 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1167 /* We have two priorities for hard register preferences.
1168 If we have a move insn or an insn whose first input
1169 can only be in the same register as the output, give
1170 priority to an equivalence found from that insn. */
1172 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1174 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1175 win = combine_regs (r1, r0, may_save_copy,
1176 insn_number, insn, 0);
1183 /* Recognize an insn sequence with an ultimate result
1184 which can safely overlap one of the inputs.
1185 The sequence begins with a CLOBBER of its result,
1186 and ends with an insn that copies the result to itself
1187 and has a REG_EQUAL note for an equivalent formula.
1188 That note indicates what the inputs are.
1189 The result and the input can overlap if each insn in
1190 the sequence either doesn't mention the input
1191 or has a REG_NO_CONFLICT note to inhibit the conflict.
1193 We do the combining test at the CLOBBER so that the
1194 destination register won't have had a quantity number
1195 assigned, since that would prevent combining. */
1197 if (GET_CODE (PATTERN (insn)) == CLOBBER
1198 && (r0 = XEXP (PATTERN (insn), 0),
1199 GET_CODE (r0) == REG)
1200 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1201 && XEXP (link, 0) != 0
1202 && GET_CODE (XEXP (link, 0)) == INSN
1203 && (set = single_set (XEXP (link, 0))) != 0
1204 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1205 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1208 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1209 /* Check that we have such a sequence. */
1210 && no_conflict_p (insn, r0, r1))
1211 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1212 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1213 && (r1 = XEXP (XEXP (note, 0), 0),
1214 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1215 && no_conflict_p (insn, r0, r1))
1216 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1218 /* Here we care if the operation to be computed is
1220 else if ((GET_CODE (XEXP (note, 0)) == EQ
1221 || GET_CODE (XEXP (note, 0)) == NE
1222 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1223 && (r1 = XEXP (XEXP (note, 0), 1),
1224 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1225 && no_conflict_p (insn, r0, r1))
1226 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1228 /* If we did combine something, show the register number
1229 in question so that we know to ignore its death. */
1231 no_conflict_combined_regno = REGNO (r1);
1234 /* If registers were just tied, set COMBINED_REGNO
1235 to the number of the register used in this insn
1236 that was tied to the register set in this insn.
1237 This register's qty should not be "killed". */
1241 while (GET_CODE (r1) == SUBREG)
1242 r1 = SUBREG_REG (r1);
1243 combined_regno = REGNO (r1);
1246 /* Mark the death of everything that dies in this instruction,
1247 except for anything that was just combined. */
1249 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1250 if (REG_NOTE_KIND (link) == REG_DEAD
1251 && GET_CODE (XEXP (link, 0)) == REG
1252 && combined_regno != REGNO (XEXP (link, 0))
1253 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1254 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1255 wipe_dead_reg (XEXP (link, 0), 0);
1257 /* Allocate qty numbers for all registers local to this block
1258 that are born (set) in this instruction.
1259 A pseudo that already has a qty is not changed. */
1261 note_stores (PATTERN (insn), reg_is_set, NULL);
1263 /* If anything is set in this insn and then unused, mark it as dying
1264 after this insn, so it will conflict with our outputs. This
1265 can't match with something that combined, and it doesn't matter
1266 if it did. Do this after the calls to reg_is_set since these
1267 die after, not during, the current insn. */
1269 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1270 if (REG_NOTE_KIND (link) == REG_UNUSED
1271 && GET_CODE (XEXP (link, 0)) == REG)
1272 wipe_dead_reg (XEXP (link, 0), 1);
1274 /* If this is an insn that has a REG_RETVAL note pointing at a
1275 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1276 block, so clear any register number that combined within it. */
1277 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1278 && GET_CODE (XEXP (note, 0)) == INSN
1279 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1280 no_conflict_combined_regno = -1;
1283 /* Set the registers live after INSN_NUMBER. Note that we never
1284 record the registers live before the block's first insn, since no
1285 pseudos we care about are live before that insn. */
1287 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1288 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1290 if (insn == BLOCK_END (b))
1293 insn = NEXT_INSN (insn);
1296 /* Now every register that is local to this basic block
1297 should have been given a quantity, or else -1 meaning ignore it.
1298 Every quantity should have a known birth and death.
1300 Order the qtys so we assign them registers in order of the
1301 number of suggested registers they need so we allocate those with
1302 the most restrictive needs first. */
1304 qty_order = (int *) xmalloc (next_qty * sizeof (int));
1305 for (i = 0; i < next_qty; i++)
1308 #define EXCHANGE(I1, I2) \
1309 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1314 /* Make qty_order[2] be the one to allocate last. */
1315 if (qty_sugg_compare (0, 1) > 0)
1317 if (qty_sugg_compare (1, 2) > 0)
1320 /* ... Fall through ... */
1322 /* Put the best one to allocate in qty_order[0]. */
1323 if (qty_sugg_compare (0, 1) > 0)
1326 /* ... Fall through ... */
1330 /* Nothing to do here. */
1334 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1337 /* Try to put each quantity in a suggested physical register, if it has one.
1338 This may cause registers to be allocated that otherwise wouldn't be, but
1339 this seems acceptable in local allocation (unlike global allocation). */
1340 for (i = 0; i < next_qty; i++)
1343 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1344 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1345 0, 1, qty[q].birth, qty[q].death);
1347 qty[q].phys_reg = -1;
1350 /* Order the qtys so we assign them registers in order of
1351 decreasing length of life. Normally call qsort, but if we
1352 have only a very small number of quantities, sort them ourselves. */
1354 for (i = 0; i < next_qty; i++)
1357 #define EXCHANGE(I1, I2) \
1358 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1363 /* Make qty_order[2] be the one to allocate last. */
1364 if (qty_compare (0, 1) > 0)
1366 if (qty_compare (1, 2) > 0)
1369 /* ... Fall through ... */
1371 /* Put the best one to allocate in qty_order[0]. */
1372 if (qty_compare (0, 1) > 0)
1375 /* ... Fall through ... */
1379 /* Nothing to do here. */
1383 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1386 /* Now for each qty that is not a hardware register,
1387 look for a hardware register to put it in.
1388 First try the register class that is cheapest for this qty,
1389 if there is more than one class. */
1391 for (i = 0; i < next_qty; i++)
1394 if (qty[q].phys_reg < 0)
1396 #ifdef INSN_SCHEDULING
1397 /* These values represent the adjusted lifetime of a qty so
1398 that it conflicts with qtys which appear near the start/end
1399 of this qty's lifetime.
1401 The purpose behind extending the lifetime of this qty is to
1402 discourage the register allocator from creating false
1405 The adjustment value is choosen to indicate that this qty
1406 conflicts with all the qtys in the instructions immediately
1407 before and after the lifetime of this qty.
1409 Experiments have shown that higher values tend to hurt
1410 overall code performance.
1412 If allocation using the extended lifetime fails we will try
1413 again with the qty's unadjusted lifetime. */
1414 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1415 int fake_death = MIN (insn_number * 2 + 1,
1416 qty[q].death + 2 - qty[q].death % 2);
1419 if (N_REG_CLASSES > 1)
1421 #ifdef INSN_SCHEDULING
1422 /* We try to avoid using hard registers allocated to qtys which
1423 are born immediately after this qty or die immediately before
1426 This optimization is only appropriate when we will run
1427 a scheduling pass after reload and we are not optimizing
1429 if (flag_schedule_insns_after_reload
1431 && !SMALL_REGISTER_CLASSES)
1434 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1435 qty[q].mode, q, 0, 0,
1436 fake_birth, fake_death);
1437 if (qty[q].phys_reg >= 0)
1441 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1442 qty[q].mode, q, 0, 0,
1443 qty[q].birth, qty[q].death);
1444 if (qty[q].phys_reg >= 0)
1448 #ifdef INSN_SCHEDULING
1449 /* Similarly, avoid false dependencies. */
1450 if (flag_schedule_insns_after_reload
1452 && !SMALL_REGISTER_CLASSES
1453 && qty[q].alternate_class != NO_REGS)
1454 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1455 qty[q].mode, q, 0, 0,
1456 fake_birth, fake_death);
1458 if (qty[q].alternate_class != NO_REGS)
1459 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1460 qty[q].mode, q, 0, 0,
1461 qty[q].birth, qty[q].death);
1465 /* Now propagate the register assignments
1466 to the pseudo regs belonging to the qtys. */
1468 for (q = 0; q < next_qty; q++)
1469 if (qty[q].phys_reg >= 0)
1471 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1472 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1476 free (regs_live_at);
1480 /* Compare two quantities' priority for getting real registers.
1481 We give shorter-lived quantities higher priority.
1482 Quantities with more references are also preferred, as are quantities that
1483 require multiple registers. This is the identical prioritization as
1484 done by global-alloc.
1486 We used to give preference to registers with *longer* lives, but using
1487 the same algorithm in both local- and global-alloc can speed up execution
1488 of some programs by as much as a factor of three! */
1490 /* Note that the quotient will never be bigger than
1491 the value of floor_log2 times the maximum number of
1492 times a register can occur in one insn (surely less than 100).
1493 Multiplying this by 10000 can't overflow.
1494 QTY_CMP_PRI is also used by qty_sugg_compare. */
1496 #define QTY_CMP_PRI(q) \
1497 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
1498 / (qty[q].death - qty[q].birth)) * 10000))
1501 qty_compare (q1, q2)
1504 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1508 qty_compare_1 (q1p, q2p)
1512 register int q1 = *(const int *)q1p, q2 = *(const int *)q2p;
1513 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1518 /* If qtys are equally good, sort by qty number,
1519 so that the results of qsort leave nothing to chance. */
1523 /* Compare two quantities' priority for getting real registers. This version
1524 is called for quantities that have suggested hard registers. First priority
1525 goes to quantities that have copy preferences, then to those that have
1526 normal preferences. Within those groups, quantities with the lower
1527 number of preferences have the highest priority. Of those, we use the same
1528 algorithm as above. */
1530 #define QTY_CMP_SUGG(q) \
1531 (qty_phys_num_copy_sugg[q] \
1532 ? qty_phys_num_copy_sugg[q] \
1533 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1536 qty_sugg_compare (q1, q2)
1539 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1544 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1548 qty_sugg_compare_1 (q1p, q2p)
1552 register int q1 = *(const int *)q1p, q2 = *(const int *)q2p;
1553 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1558 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1562 /* If qtys are equally good, sort by qty number,
1563 so that the results of qsort leave nothing to chance. */
1570 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1571 Returns 1 if have done so, or 0 if cannot.
1573 Combining registers means marking them as having the same quantity
1574 and adjusting the offsets within the quantity if either of
1577 We don't actually combine a hard reg with a pseudo; instead
1578 we just record the hard reg as the suggestion for the pseudo's quantity.
1579 If we really combined them, we could lose if the pseudo lives
1580 across an insn that clobbers the hard reg (eg, movstr).
1582 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1583 there is no REG_DEAD note on INSN. This occurs during the processing
1584 of REG_NO_CONFLICT blocks.
1586 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1587 SETREG or if the input and output must share a register.
1588 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1590 There are elaborate checks for the validity of combining. */
1594 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1595 rtx usedreg, setreg;
1601 register int ureg, sreg;
1602 register int offset = 0;
1606 /* Determine the numbers and sizes of registers being used. If a subreg
1607 is present that does not change the entire register, don't consider
1608 this a copy insn. */
1610 while (GET_CODE (usedreg) == SUBREG)
1612 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1614 offset += SUBREG_WORD (usedreg);
1615 usedreg = SUBREG_REG (usedreg);
1617 if (GET_CODE (usedreg) != REG)
1619 ureg = REGNO (usedreg);
1620 usize = REG_SIZE (usedreg);
1622 while (GET_CODE (setreg) == SUBREG)
1624 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1626 offset -= SUBREG_WORD (setreg);
1627 setreg = SUBREG_REG (setreg);
1629 if (GET_CODE (setreg) != REG)
1631 sreg = REGNO (setreg);
1632 ssize = REG_SIZE (setreg);
1634 /* If UREG is a pseudo-register that hasn't already been assigned a
1635 quantity number, it means that it is not local to this block or dies
1636 more than once. In either event, we can't do anything with it. */
1637 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1638 /* Do not combine registers unless one fits within the other. */
1639 || (offset > 0 && usize + offset > ssize)
1640 || (offset < 0 && usize + offset < ssize)
1641 /* Do not combine with a smaller already-assigned object
1642 if that smaller object is already combined with something bigger. */
1643 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1644 && usize < qty[reg_qty[ureg]].size)
1645 /* Can't combine if SREG is not a register we can allocate. */
1646 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1647 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1648 These have already been taken care of. This probably wouldn't
1649 combine anyway, but don't take any chances. */
1650 || (ureg >= FIRST_PSEUDO_REGISTER
1651 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1652 /* Don't tie something to itself. In most cases it would make no
1653 difference, but it would screw up if the reg being tied to itself
1654 also dies in this insn. */
1656 /* Don't try to connect two different hardware registers. */
1657 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1658 /* Don't use a hard reg that might be spilled. */
1659 || (ureg < FIRST_PSEUDO_REGISTER
1660 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg)))
1661 || (sreg < FIRST_PSEUDO_REGISTER
1662 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg)))
1663 /* Don't connect two different machine modes if they have different
1664 implications as to which registers may be used. */
1665 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1668 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1669 qty_phys_sugg for the pseudo instead of tying them.
1671 Return "failure" so that the lifespan of UREG is terminated here;
1672 that way the two lifespans will be disjoint and nothing will prevent
1673 the pseudo reg from being given this hard reg. */
1675 if (ureg < FIRST_PSEUDO_REGISTER)
1677 /* Allocate a quantity number so we have a place to put our
1679 if (reg_qty[sreg] == -2)
1680 reg_is_born (setreg, 2 * insn_number);
1682 if (reg_qty[sreg] >= 0)
1685 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1687 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1688 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1690 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1692 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1693 qty_phys_num_sugg[reg_qty[sreg]]++;
1699 /* Similarly for SREG a hard register and UREG a pseudo register. */
1701 if (sreg < FIRST_PSEUDO_REGISTER)
1704 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1706 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1707 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1709 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1711 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1712 qty_phys_num_sugg[reg_qty[ureg]]++;
1717 /* At this point we know that SREG and UREG are both pseudos.
1718 Do nothing if SREG already has a quantity or is a register that we
1720 if (reg_qty[sreg] >= -1
1721 /* If we are not going to let any regs live across calls,
1722 don't tie a call-crossing reg to a non-call-crossing reg. */
1723 || (current_function_has_nonlocal_label
1724 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1725 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1728 /* We don't already know about SREG, so tie it to UREG
1729 if this is the last use of UREG, provided the classes they want
1732 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1733 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
1735 /* Add SREG to UREG's quantity. */
1736 sqty = reg_qty[ureg];
1737 reg_qty[sreg] = sqty;
1738 reg_offset[sreg] = reg_offset[ureg] + offset;
1739 reg_next_in_qty[sreg] = qty[sqty].first_reg;
1740 qty[sqty].first_reg = sreg;
1742 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1743 update_qty_class (sqty, sreg);
1745 /* Update info about quantity SQTY. */
1746 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
1747 qty[sqty].n_refs += REG_N_REFS (sreg);
1752 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
1753 reg_offset[i] -= offset;
1755 qty[sqty].size = ssize;
1756 qty[sqty].mode = GET_MODE (setreg);
1765 /* Return 1 if the preferred class of REG allows it to be tied
1766 to a quantity or register whose class is CLASS.
1767 True if REG's reg class either contains or is contained in CLASS. */
1770 reg_meets_class_p (reg, class)
1772 enum reg_class class;
1774 register enum reg_class rclass = reg_preferred_class (reg);
1775 return (reg_class_subset_p (rclass, class)
1776 || reg_class_subset_p (class, rclass));
1779 /* Update the class of QTYNO assuming that REG is being tied to it. */
1782 update_qty_class (qtyno, reg)
1786 enum reg_class rclass = reg_preferred_class (reg);
1787 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
1788 qty[qtyno].min_class = rclass;
1790 rclass = reg_alternate_class (reg);
1791 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
1792 qty[qtyno].alternate_class = rclass;
1794 if (REG_CHANGES_SIZE (reg))
1795 qty[qtyno].changes_size = 1;
1798 /* Handle something which alters the value of an rtx REG.
1800 REG is whatever is set or clobbered. SETTER is the rtx that
1801 is modifying the register.
1803 If it is not really a register, we do nothing.
1804 The file-global variables `this_insn' and `this_insn_number'
1805 carry info from `block_alloc'. */
1808 reg_is_set (reg, setter, data)
1811 void *data ATTRIBUTE_UNUSED;
1813 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1814 a hard register. These may actually not exist any more. */
1816 if (GET_CODE (reg) != SUBREG
1817 && GET_CODE (reg) != REG)
1820 /* Mark this register as being born. If it is used in a CLOBBER, mark
1821 it as being born halfway between the previous insn and this insn so that
1822 it conflicts with our inputs but not the outputs of the previous insn. */
1824 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1827 /* Handle beginning of the life of register REG.
1828 BIRTH is the index at which this is happening. */
1831 reg_is_born (reg, birth)
1837 if (GET_CODE (reg) == SUBREG)
1838 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1840 regno = REGNO (reg);
1842 if (regno < FIRST_PSEUDO_REGISTER)
1844 mark_life (regno, GET_MODE (reg), 1);
1846 /* If the register was to have been born earlier that the present
1847 insn, mark it as live where it is actually born. */
1848 if (birth < 2 * this_insn_number)
1849 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1853 if (reg_qty[regno] == -2)
1854 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1856 /* If this register has a quantity number, show that it isn't dead. */
1857 if (reg_qty[regno] >= 0)
1858 qty[reg_qty[regno]].death = -1;
1862 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1863 REG is an output that is dying (i.e., it is never used), otherwise it
1864 is an input (the normal case).
1865 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1868 wipe_dead_reg (reg, output_p)
1872 register int regno = REGNO (reg);
1874 /* If this insn has multiple results,
1875 and the dead reg is used in one of the results,
1876 extend its life to after this insn,
1877 so it won't get allocated together with any other result of this insn.
1879 It is unsafe to use !single_set here since it will ignore an unused
1880 output. Just because an output is unused does not mean the compiler
1881 can assume the side effect will not occur. Consider if REG appears
1882 in the address of an output and we reload the output. If we allocate
1883 REG to the same hard register as an unused output we could set the hard
1884 register before the output reload insn. */
1885 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1886 && multiple_sets (this_insn))
1889 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1891 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1892 if (GET_CODE (set) == SET
1893 && GET_CODE (SET_DEST (set)) != REG
1894 && !rtx_equal_p (reg, SET_DEST (set))
1895 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1900 /* If this register is used in an auto-increment address, then extend its
1901 life to after this insn, so that it won't get allocated together with
1902 the result of this insn. */
1903 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1906 if (regno < FIRST_PSEUDO_REGISTER)
1908 mark_life (regno, GET_MODE (reg), 0);
1910 /* If a hard register is dying as an output, mark it as in use at
1911 the beginning of this insn (the above statement would cause this
1914 post_mark_life (regno, GET_MODE (reg), 1,
1915 2 * this_insn_number, 2 * this_insn_number+ 1);
1918 else if (reg_qty[regno] >= 0)
1919 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
1922 /* Find a block of SIZE words of hard regs in reg_class CLASS
1923 that can hold something of machine-mode MODE
1924 (but actually we test only the first of the block for holding MODE)
1925 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1926 and return the number of the first of them.
1927 Return -1 if such a block cannot be found.
1928 If QTYNO crosses calls, insist on a register preserved by calls,
1929 unless ACCEPT_CALL_CLOBBERED is nonzero.
1931 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1932 register is available. If not, return -1. */
1935 find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested,
1936 born_index, dead_index)
1937 enum reg_class class;
1938 enum machine_mode mode;
1940 int accept_call_clobbered;
1941 int just_try_suggested;
1942 int born_index, dead_index;
1944 register int i, ins;
1946 register /* Declare it register if it's a scalar. */
1948 HARD_REG_SET used, first_used;
1949 #ifdef ELIMINABLE_REGS
1950 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1953 /* Validate our parameters. */
1954 if (born_index < 0 || born_index > dead_index)
1957 /* Don't let a pseudo live in a reg across a function call
1958 if we might get a nonlocal goto. */
1959 if (current_function_has_nonlocal_label
1960 && qty[qtyno].n_calls_crossed > 0)
1963 if (accept_call_clobbered)
1964 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1965 else if (qty[qtyno].n_calls_crossed == 0)
1966 COPY_HARD_REG_SET (used, fixed_reg_set);
1968 COPY_HARD_REG_SET (used, call_used_reg_set);
1970 if (accept_call_clobbered)
1971 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1973 for (ins = born_index; ins < dead_index; ins++)
1974 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1976 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1978 /* Don't use the frame pointer reg in local-alloc even if
1979 we may omit the frame pointer, because if we do that and then we
1980 need a frame pointer, reload won't know how to move the pseudo
1981 to another hard reg. It can move only regs made by global-alloc.
1983 This is true of any register that can be eliminated. */
1984 #ifdef ELIMINABLE_REGS
1985 for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++)
1986 SET_HARD_REG_BIT (used, eliminables[i].from);
1987 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1988 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1989 that it might be eliminated into. */
1990 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1993 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1996 #ifdef CLASS_CANNOT_CHANGE_SIZE
1997 if (qty[qtyno].changes_size)
1998 IOR_HARD_REG_SET (used,
1999 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2002 /* Normally, the registers that can be used for the first register in
2003 a multi-register quantity are the same as those that can be used for
2004 subsequent registers. However, if just trying suggested registers,
2005 restrict our consideration to them. If there are copy-suggested
2006 register, try them. Otherwise, try the arithmetic-suggested
2008 COPY_HARD_REG_SET (first_used, used);
2010 if (just_try_suggested)
2012 if (qty_phys_num_copy_sugg[qtyno] != 0)
2013 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
2015 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
2018 /* If all registers are excluded, we can't do anything. */
2019 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2021 /* If at least one would be suitable, test each hard reg. */
2023 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2025 #ifdef REG_ALLOC_ORDER
2026 int regno = reg_alloc_order[i];
2030 if (! TEST_HARD_REG_BIT (first_used, regno)
2031 && HARD_REGNO_MODE_OK (regno, mode)
2032 && (qty[qtyno].n_calls_crossed == 0
2033 || accept_call_clobbered
2034 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2037 register int size1 = HARD_REGNO_NREGS (regno, mode);
2038 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2041 /* Mark that this register is in use between its birth and death
2043 post_mark_life (regno, mode, 1, born_index, dead_index);
2046 #ifndef REG_ALLOC_ORDER
2047 i += j; /* Skip starting points we know will lose */
2054 /* If we are just trying suggested register, we have just tried copy-
2055 suggested registers, and there are arithmetic-suggested registers,
2058 /* If it would be profitable to allocate a call-clobbered register
2059 and save and restore it around calls, do that. */
2060 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2061 && qty_phys_num_sugg[qtyno] != 0)
2063 /* Don't try the copy-suggested regs again. */
2064 qty_phys_num_copy_sugg[qtyno] = 0;
2065 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2066 born_index, dead_index);
2069 /* We need not check to see if the current function has nonlocal
2070 labels because we don't put any pseudos that are live over calls in
2071 registers in that case. */
2073 if (! accept_call_clobbered
2074 && flag_caller_saves
2075 && ! just_try_suggested
2076 && qty[qtyno].n_calls_crossed != 0
2077 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs, qty[qtyno].n_calls_crossed))
2079 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2081 caller_save_needed = 1;
2087 /* Mark that REGNO with machine-mode MODE is live starting from the current
2088 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2092 mark_life (regno, mode, life)
2094 enum machine_mode mode;
2097 register int j = HARD_REGNO_NREGS (regno, mode);
2100 SET_HARD_REG_BIT (regs_live, regno + j);
2103 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2106 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2107 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2108 to insn number DEATH (exclusive). */
2111 post_mark_life (regno, mode, life, birth, death)
2113 enum machine_mode mode;
2114 int life, birth, death;
2116 register int j = HARD_REGNO_NREGS (regno, mode);
2118 register /* Declare it register if it's a scalar. */
2120 HARD_REG_SET this_reg;
2122 CLEAR_HARD_REG_SET (this_reg);
2124 SET_HARD_REG_BIT (this_reg, regno + j);
2127 while (birth < death)
2129 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2133 while (birth < death)
2135 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2140 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2141 is the register being clobbered, and R1 is a register being used in
2142 the equivalent expression.
2144 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2145 in which it is used, return 1.
2147 Otherwise, return 0. */
2150 no_conflict_p (insn, r0, r1)
2154 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2157 /* If R1 is a hard register, return 0 since we handle this case
2158 when we scan the insns that actually use it. */
2161 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2162 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2163 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2166 last = XEXP (note, 0);
2168 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2169 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2171 if (find_reg_note (p, REG_DEAD, r1))
2174 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2175 some earlier optimization pass has inserted instructions into
2176 the sequence, and it is not safe to perform this optimization.
2177 Note that emit_no_conflict_block always ensures that this is
2178 true when these sequences are created. */
2179 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2186 /* Return the number of alternatives for which the constraint string P
2187 indicates that the operand must be equal to operand 0 and that no register
2196 int reg_allowed = 0;
2197 int num_matching_alts = 0;
2202 case '=': case '+': case '?':
2203 case '#': case '&': case '!':
2205 case '1': case '2': case '3': case '4': case '5':
2206 case '6': case '7': case '8': case '9':
2207 case 'm': case '<': case '>': case 'V': case 'o':
2208 case 'E': case 'F': case 'G': case 'H':
2209 case 's': case 'i': case 'n':
2210 case 'I': case 'J': case 'K': case 'L':
2211 case 'M': case 'N': case 'O': case 'P':
2212 #ifdef EXTRA_CONSTRAINT
2213 case 'Q': case 'R': case 'S': case 'T': case 'U':
2216 /* These don't say anything we care about. */
2220 if (found_zero && ! reg_allowed)
2221 num_matching_alts++;
2223 found_zero = reg_allowed = 0;
2237 if (found_zero && ! reg_allowed)
2238 num_matching_alts++;
2240 return num_matching_alts;
2244 dump_local_alloc (file)
2248 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2249 if (reg_renumber[i] != -1)
2250 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);