1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int memref_referenced_p PROTO((rtx, rtx));
250 static int memref_used_between_p PROTO((rtx, rtx, rtx));
251 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
253 static void update_equiv_regs PROTO((void));
254 static void block_alloc PROTO((int));
255 static int qty_sugg_compare PROTO((int, int));
256 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
257 static int qty_compare PROTO((int, int));
258 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
259 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
260 static int reg_meets_class_p PROTO((int, enum reg_class));
261 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
263 static void update_qty_class PROTO((int, int));
264 static void reg_is_set PROTO((rtx, rtx));
265 static void reg_is_born PROTO((rtx, int));
266 static void wipe_dead_reg PROTO((rtx, int));
267 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
268 int, int, int, int, int));
269 static void mark_life PROTO((int, enum machine_mode, int));
270 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
271 static int no_conflict_p PROTO((rtx, rtx, rtx));
272 static int requires_inout PROTO((char *));
274 /* Allocate a new quantity (new within current basic block)
275 for register number REGNO which is born at index BIRTH
276 within the block. MODE and SIZE are info on reg REGNO. */
279 alloc_qty (regno, mode, size, birth)
281 enum machine_mode mode;
284 register int qty = next_qty++;
286 reg_qty[regno] = qty;
287 reg_offset[regno] = 0;
288 reg_next_in_qty[regno] = -1;
290 qty_first_reg[qty] = regno;
291 qty_size[qty] = size;
292 qty_mode[qty] = mode;
293 qty_birth[qty] = birth;
294 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
295 qty_min_class[qty] = reg_preferred_class (regno);
296 qty_alternate_class[qty] = reg_alternate_class (regno);
297 qty_n_refs[qty] = REG_N_REFS (regno);
298 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
301 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
302 used as operand N in INSN. We assume here that the SCRATCH is used in
306 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
310 int insn_code_num, insn_number;
313 enum reg_class class;
317 #ifdef REGISTER_CONSTRAINTS
318 /* If we haven't yet computed which alternative will be used, do so now.
319 Then set P to the constraints for that alternative. */
320 if (which_alternative == -1)
321 if (! constrain_operands (insn_code_num, 0))
324 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
325 *p && i < which_alternative; p++)
329 /* Compute the class required for this SCRATCH. If we don't need a
330 register, the class will remain NO_REGS. If we guessed the alternative
331 number incorrectly, reload will fix things up for us. */
334 while ((c = *p++) != '\0' && c != ',')
337 case '=': case '+': case '?':
338 case '#': case '&': case '!':
340 case '0': case '1': case '2': case '3': case '4':
341 case 'm': case '<': case '>': case 'V': case 'o':
342 case 'E': case 'F': case 'G': case 'H':
343 case 's': case 'i': case 'n':
344 case 'I': case 'J': case 'K': case 'L':
345 case 'M': case 'N': case 'O': case 'P':
346 #ifdef EXTRA_CONSTRAINT
347 case 'Q': case 'R': case 'S': case 'T': case 'U':
350 /* These don't say anything we care about. */
354 /* We don't need to allocate this SCRATCH. */
358 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
363 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
367 if (class == NO_REGS)
370 #else /* REGISTER_CONSTRAINTS */
372 class = GENERAL_REGS;
378 qty_first_reg[qty] = -1;
379 qty_scratch_rtx[qty] = scratch;
380 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
381 qty_mode[qty] = GET_MODE (scratch);
382 qty_birth[qty] = 2 * insn_number - 1;
383 qty_death[qty] = 2 * insn_number + 1;
384 qty_n_calls_crossed[qty] = 0;
385 qty_min_class[qty] = class;
386 qty_alternate_class[qty] = NO_REGS;
388 qty_changes_size[qty] = 0;
391 /* Main entry point of this file. */
399 /* Leaf functions and non-leaf functions have different needs.
400 If defined, let the machine say what kind of ordering we
402 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
403 ORDER_REGS_FOR_LOCAL_ALLOC;
406 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
408 update_equiv_regs ();
410 /* This sets the maximum number of quantities we can have. Quantity
411 numbers start at zero and we can have one for each pseudo plus the
412 number of SCRATCHes in the largest block, in the worst case. */
413 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
415 /* Allocate vectors of temporary data.
416 See the declarations of these variables, above,
417 for what they mean. */
419 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
420 Instead of allocating this much memory from now until the end of
421 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
422 reload will allocate them. */
424 scratch_list_length = max_qty;
425 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
426 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
427 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
428 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
431 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
433 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
434 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
435 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
436 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
437 qty_birth = (int *) alloca (max_qty * sizeof (int));
438 qty_death = (int *) alloca (max_qty * sizeof (int));
439 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
440 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
441 qty_size = (int *) alloca (max_qty * sizeof (int));
443 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
444 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
446 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
448 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
450 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
452 reg_qty = (int *) alloca (max_regno * sizeof (int));
453 reg_offset = (char *) alloca (max_regno * sizeof (char));
454 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
456 /* Allocate the reg_renumber array */
457 allocate_reg_info (max_regno, FALSE, TRUE);
459 /* Determine which pseudo-registers can be allocated by local-alloc.
460 In general, these are the registers used only in a single block and
461 which only die once. However, if a register's preferred class has only
462 a few entries, don't allocate this register here unless it is preferred
463 or nothing since retry_global_alloc won't be able to move it to
464 GENERAL_REGS if a reload register of this class is needed.
466 We need not be concerned with which block actually uses the register
467 since we will never see it outside that block. */
469 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
471 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
472 && (reg_alternate_class (i) == NO_REGS
473 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
479 /* Force loop below to initialize entire quantity array. */
482 /* Allocate each block's local registers, block by block. */
484 for (b = 0; b < n_basic_blocks; b++)
486 /* NEXT_QTY indicates which elements of the `qty_...'
487 vectors might need to be initialized because they were used
488 for the previous block; it is set to the entire array before
489 block 0. Initialize those, with explicit loop if there are few,
490 else with bzero and bcopy. Do not initialize vectors that are
491 explicit set by `alloc_qty'. */
495 for (i = 0; i < next_qty; i++)
497 qty_scratch_rtx[i] = 0;
498 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
499 qty_phys_num_copy_sugg[i] = 0;
500 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
501 qty_phys_num_sugg[i] = 0;
506 #define CLEAR(vector) \
507 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
509 CLEAR (qty_scratch_rtx);
510 CLEAR (qty_phys_copy_sugg);
511 CLEAR (qty_phys_num_copy_sugg);
512 CLEAR (qty_phys_sugg);
513 CLEAR (qty_phys_num_sugg);
525 /* Depth of loops we are in while in update_equiv_regs. */
526 static int loop_depth;
528 /* Used for communication between the following two functions: contains
529 a MEM that we wish to ensure remains unchanged. */
530 static rtx equiv_mem;
532 /* Set nonzero if EQUIV_MEM is modified. */
533 static int equiv_mem_modified;
535 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
536 Called via note_stores. */
539 validate_equiv_mem_from_store (dest, set)
543 if ((GET_CODE (dest) == REG
544 && reg_overlap_mentioned_p (dest, equiv_mem))
545 || (GET_CODE (dest) == MEM
546 && true_dependence (dest, equiv_mem)))
547 equiv_mem_modified = 1;
550 /* Verify that no store between START and the death of REG invalidates
551 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
552 by storing into an overlapping memory location, or with a non-const
555 Return 1 if MEMREF remains valid. */
558 validate_equiv_mem (start, reg, memref)
567 equiv_mem_modified = 0;
569 /* If the memory reference has side effects or is volatile, it isn't a
570 valid equivalence. */
571 if (side_effects_p (memref))
574 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
576 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
579 if (find_reg_note (insn, REG_DEAD, reg))
582 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
583 && ! CONST_CALL_P (insn))
586 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
588 /* If a register mentioned in MEMREF is modified via an
589 auto-increment, we lose the equivalence. Do the same if one
590 dies; although we could extend the life, it doesn't seem worth
593 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
594 if ((REG_NOTE_KIND (note) == REG_INC
595 || REG_NOTE_KIND (note) == REG_DEAD)
596 && GET_CODE (XEXP (note, 0)) == REG
597 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
604 /* TRUE if X references a memory location that would be affected by a store
608 memref_referenced_p (memref, x)
614 enum rtx_code code = GET_CODE (x);
630 return (reg_equiv_replacement[REGNO (x)]
631 && memref_referenced_p (memref,
632 reg_equiv_replacement[REGNO (x)]));
635 if (true_dependence (memref, x))
640 /* If we are setting a MEM, it doesn't count (its address does), but any
641 other SET_DEST that has a MEM in it is referencing the MEM. */
642 if (GET_CODE (SET_DEST (x)) == MEM)
644 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
647 else if (memref_referenced_p (memref, SET_DEST (x)))
650 return memref_referenced_p (memref, SET_SRC (x));
653 fmt = GET_RTX_FORMAT (code);
654 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
658 if (memref_referenced_p (memref, XEXP (x, i)))
662 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
663 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
671 /* TRUE if some insn in the range (START, END] references a memory location
672 that would be affected by a store to MEMREF. */
675 memref_used_between_p (memref, start, end)
682 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
683 insn = NEXT_INSN (insn))
684 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
685 && memref_referenced_p (memref, PATTERN (insn)))
691 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
694 Search forward to see if SRC dies before either it or DEST is modified,
695 but don't scan past the end of a basic block. If so, we can replace SRC
696 with DEST and let SRC die in INSN.
698 This will reduce the number of registers live in that range and may enable
699 DEST to be tied to SRC, thus often saving one register in addition to a
700 register-register copy. */
703 optimize_reg_copy_1 (insn, dest, src)
711 int sregno = REGNO (src);
712 int dregno = REGNO (dest);
715 #ifdef SMALL_REGISTER_CLASSES
716 /* We don't want to mess with hard regs if register classes are small. */
717 || (SMALL_REGISTER_CLASSES
718 && (sregno < FIRST_PSEUDO_REGISTER
719 || dregno < FIRST_PSEUDO_REGISTER))
721 /* We don't see all updates to SP if they are in an auto-inc memory
722 reference, so we must disallow this optimization on them. */
723 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
726 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
728 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
729 || (GET_CODE (p) == NOTE
730 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
731 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
734 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
737 if (reg_set_p (src, p) || reg_set_p (dest, p)
738 /* Don't change a USE of a register. */
739 || (GET_CODE (PATTERN (p)) == USE
740 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
743 /* See if all of SRC dies in P. This test is slightly more
744 conservative than it needs to be. */
745 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
746 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
754 /* We can do the optimization. Scan forward from INSN again,
755 replacing regs as we go. Set FAILED if a replacement can't
756 be done. In that case, we can't move the death note for SRC.
757 This should be rare. */
759 /* Set to stop at next insn. */
760 for (q = next_real_insn (insn);
761 q != next_real_insn (p);
762 q = next_real_insn (q))
764 if (reg_overlap_mentioned_p (src, PATTERN (q)))
766 /* If SRC is a hard register, we might miss some
767 overlapping registers with validate_replace_rtx,
768 so we would have to undo it. We can't if DEST is
769 present in the insn, so fail in that combination
771 if (sregno < FIRST_PSEUDO_REGISTER
772 && reg_mentioned_p (dest, PATTERN (q)))
775 /* Replace all uses and make sure that the register
776 isn't still present. */
777 else if (validate_replace_rtx (src, dest, q)
778 && (sregno >= FIRST_PSEUDO_REGISTER
779 || ! reg_overlap_mentioned_p (src,
782 /* We assume that a register is used exactly once per
783 insn in the updates below. If this is not correct,
784 no great harm is done. */
785 if (sregno >= FIRST_PSEUDO_REGISTER)
786 REG_N_REFS (sregno) -= loop_depth;
787 if (dregno >= FIRST_PSEUDO_REGISTER)
788 REG_N_REFS (dregno) += loop_depth;
792 validate_replace_rtx (dest, src, q);
797 /* Count the insns and CALL_INSNs passed. If we passed the
798 death note of DEST, show increased live length. */
803 /* If the insn in which SRC dies is a CALL_INSN, don't count it
804 as a call that has been crossed. Otherwise, count it. */
805 if (q != p && GET_CODE (q) == CALL_INSN)
812 /* If DEST dies here, remove the death note and save it for
813 later. Make sure ALL of DEST dies here; again, this is
814 overly conservative. */
816 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
817 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
818 remove_note (q, dest_death);
823 if (sregno >= FIRST_PSEUDO_REGISTER)
825 if (REG_LIVE_LENGTH (sregno) >= 0)
827 REG_LIVE_LENGTH (sregno) -= length;
828 /* reg_live_length is only an approximation after
829 combine if sched is not run, so make sure that we
830 still have a reasonable value. */
831 if (REG_LIVE_LENGTH (sregno) < 2)
832 REG_LIVE_LENGTH (sregno) = 2;
835 REG_N_CALLS_CROSSED (sregno) -= n_calls;
838 if (dregno >= FIRST_PSEUDO_REGISTER)
840 if (REG_LIVE_LENGTH (dregno) >= 0)
841 REG_LIVE_LENGTH (dregno) += d_length;
843 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
846 /* Move death note of SRC from P to INSN. */
847 remove_note (p, note);
848 XEXP (note, 1) = REG_NOTES (insn);
849 REG_NOTES (insn) = note;
852 /* Put death note of DEST on P if we saw it die. */
855 XEXP (dest_death, 1) = REG_NOTES (p);
856 REG_NOTES (p) = dest_death;
862 /* If SRC is a hard register which is set or killed in some other
863 way, we can't do this optimization. */
864 else if (sregno < FIRST_PSEUDO_REGISTER
865 && dead_or_set_p (p, src))
870 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
871 a sequence of insns that modify DEST followed by an insn that sets
872 SRC to DEST in which DEST dies, with no prior modification of DEST.
873 (There is no need to check if the insns in between actually modify
874 DEST. We should not have cases where DEST is not modified, but
875 the optimization is safe if no such modification is detected.)
876 In that case, we can replace all uses of DEST, starting with INSN and
877 ending with the set of SRC to DEST, with SRC. We do not do this
878 optimization if a CALL_INSN is crossed unless SRC already crosses a
879 call or if DEST dies before the copy back to SRC.
881 It is assumed that DEST and SRC are pseudos; it is too complicated to do
882 this for hard registers since the substitutions we may make might fail. */
885 optimize_reg_copy_2 (insn, dest, src)
892 int sregno = REGNO (src);
893 int dregno = REGNO (dest);
895 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
897 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
898 || (GET_CODE (p) == NOTE
899 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
900 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
903 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
906 set = single_set (p);
907 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
908 && find_reg_note (p, REG_DEAD, dest))
910 /* We can do the optimization. Scan forward from INSN again,
911 replacing regs as we go. */
913 /* Set to stop at next insn. */
914 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
915 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
917 if (reg_mentioned_p (dest, PATTERN (q)))
919 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
921 /* We assume that a register is used exactly once per
922 insn in the updates below. If this is not correct,
923 no great harm is done. */
924 REG_N_REFS (dregno) -= loop_depth;
925 REG_N_REFS (sregno) += loop_depth;
929 if (GET_CODE (q) == CALL_INSN)
931 REG_N_CALLS_CROSSED (dregno)--;
932 REG_N_CALLS_CROSSED (sregno)++;
936 remove_note (p, find_reg_note (p, REG_DEAD, dest));
937 REG_N_DEATHS (dregno)--;
938 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
939 REG_N_DEATHS (sregno)--;
943 if (reg_set_p (src, p)
944 || find_reg_note (p, REG_DEAD, dest)
945 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0))
950 /* Find registers that are equivalent to a single value throughout the
951 compilation (either because they can be referenced in memory or are set once
952 from a single constant). Lower their priority for a register.
954 If such a register is only referenced once, try substituting its value
955 into the using insn. If it succeeds, we can eliminate the register
961 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
962 /* Set when an attempt should be made to replace a register with the
963 associated reg_equiv_replacement entry at the end of this function. */
964 char *reg_equiv_replace
965 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
969 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
971 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
972 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
973 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
975 init_alias_analysis ();
979 /* Scan the insns and find which registers have equivalences. Do this
980 in a separate scan of the insns because (due to -fcse-follow-jumps)
981 a register can be set below its use. */
982 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
985 rtx set = single_set (insn);
989 if (GET_CODE (insn) == NOTE)
991 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
993 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
997 /* If this insn contains more (or less) than a single SET, ignore it. */
1001 dest = SET_DEST (set);
1002 src = SET_SRC (set);
1004 /* If this sets a MEM to the contents of a REG that is only used
1005 in a single basic block, see if the register is always equivalent
1006 to that memory location and if moving the store from INSN to the
1007 insn that set REG is safe. If so, put a REG_EQUIV note on the
1008 initializing insn. */
1010 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
1011 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
1012 && REG_BASIC_BLOCK (regno) >= 0
1013 && reg_equiv_init_insn[regno] != 0
1014 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
1016 && ! memref_used_between_p (SET_DEST (set),
1017 reg_equiv_init_insn[regno], insn))
1018 REG_NOTES (reg_equiv_init_insn[regno])
1019 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1020 REG_NOTES (reg_equiv_init_insn[regno]));
1022 /* If this is a register-register copy where SRC is not dead, see if we
1024 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1025 && GET_CODE (SET_SRC (set)) == REG
1026 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1027 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1029 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1030 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1031 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1032 && GET_CODE (SET_SRC (set)) == REG
1033 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1034 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1035 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1037 /* Otherwise, we only handle the case of a pseudo register being set
1038 once and only if neither the source nor the destination are
1039 in a register class that's likely to be spilled. */
1040 if (GET_CODE (dest) != REG
1041 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1042 || REG_N_SETS (regno) != 1
1043 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
1044 || (GET_CODE (src) == REG
1045 && REGNO (src) >= FIRST_PSEUDO_REGISTER
1046 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
1049 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1051 /* Record this insn as initializing this register. */
1052 reg_equiv_init_insn[regno] = insn;
1054 /* If this register is known to be equal to a constant, record that
1055 it is always equivalent to the constant. */
1056 if (note && CONSTANT_P (XEXP (note, 0)))
1057 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1059 /* If this insn introduces a "constant" register, decrease the priority
1060 of that register. Record this insn if the register is only used once
1061 more and the equivalence value is the same as our source.
1063 The latter condition is checked for two reasons: First, it is an
1064 indication that it may be more efficient to actually emit the insn
1065 as written (if no registers are available, reload will substitute
1066 the equivalence). Secondly, it avoids problems with any registers
1067 dying in this insn whose death notes would be missed.
1069 If we don't have a REG_EQUIV note, see if this insn is loading
1070 a register used only in one basic block from a MEM. If so, and the
1071 MEM remains unchanged for the life of the register, add a REG_EQUIV
1074 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1076 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
1077 && GET_CODE (SET_SRC (set)) == MEM
1078 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1079 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1084 int regno = REGNO (dest);
1086 reg_equiv_replacement[regno] = XEXP (note, 0);
1088 /* Don't mess with things live during setjmp. */
1089 if (REG_LIVE_LENGTH (regno) >= 0)
1091 /* Note that the statement below does not affect the priority
1093 REG_LIVE_LENGTH (regno) *= 2;
1096 /* If the register is referenced exactly twice, meaning it is
1097 set once and used once, indicate that the reference may be
1098 replaced by the equivalence we computed above. If the
1099 register is only used in one basic block, this can't succeed
1100 or combine would have done it.
1102 It would be nice to use "loop_depth * 2" in the compare
1103 below. Unfortunately, LOOP_DEPTH need not be constant within
1104 a basic block so this would be too complicated.
1106 This case normally occurs when a parameter is read from
1107 memory and then used exactly once, not in a loop. */
1109 if (REG_N_REFS (regno) == 2
1110 && REG_BASIC_BLOCK (regno) < 0
1111 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1112 reg_equiv_replace[regno] = 1;
1117 /* Now scan all regs killed in an insn to see if any of them are
1118 registers only used that once. If so, see if we can replace the
1119 reference with the equivalent from. If we can, delete the
1120 initializing reference and this register will go away. If we
1121 can't replace the reference, and the instruction is not in a
1122 loop, then move the register initialization just before the use,
1123 so that they are in the same basic block. */
1126 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1130 /* Keep track of which basic block we are in. */
1131 if (block + 1 < n_basic_blocks
1132 && basic_block_head[block + 1] == insn)
1135 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1137 if (GET_CODE (insn) == NOTE)
1139 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1141 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1152 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1154 if (REG_NOTE_KIND (link) == REG_DEAD
1155 /* Make sure this insn still refers to the register. */
1156 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1158 int regno = REGNO (XEXP (link, 0));
1161 if (! reg_equiv_replace[regno])
1164 equiv_insn = reg_equiv_init_insn[regno];
1166 if (validate_replace_rtx (regno_reg_rtx[regno],
1167 reg_equiv_replacement[regno], insn))
1169 remove_death (regno, insn);
1170 REG_N_REFS (regno) = 0;
1171 PUT_CODE (equiv_insn, NOTE);
1172 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1173 NOTE_SOURCE_FILE (equiv_insn) = 0;
1175 /* If we aren't in a loop, and there are no calls in
1176 INSN or in the initialization of the register, then
1177 move the initialization of the register to just
1178 before INSN. Update the flow information. */
1180 && GET_CODE (equiv_insn) == INSN
1181 && GET_CODE (insn) == INSN
1182 && REG_BASIC_BLOCK (regno) < 0)
1186 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
1187 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
1189 PUT_CODE (equiv_insn, NOTE);
1190 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1191 NOTE_SOURCE_FILE (equiv_insn) = 0;
1192 REG_NOTES (equiv_insn) = 0;
1195 REG_BASIC_BLOCK (regno) = 0;
1197 REG_BASIC_BLOCK (regno) = block;
1198 REG_N_CALLS_CROSSED (regno) = 0;
1199 REG_LIVE_LENGTH (regno) = 2;
1201 if (block >= 0 && insn == basic_block_head[block])
1202 basic_block_head[block] = PREV_INSN (insn);
1204 for (l = 0; l < n_basic_blocks; l++)
1205 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1212 /* Allocate hard regs to the pseudo regs used only within block number B.
1213 Only the pseudos that die but once can be handled. */
1222 int insn_number = 0;
1224 int max_uid = get_max_uid ();
1226 int no_conflict_combined_regno = -1;
1227 /* Counter to prevent allocating more SCRATCHes than can be stored
1229 int scratches_allocated = scratch_index;
1231 /* Count the instructions in the basic block. */
1233 insn = basic_block_end[b];
1236 if (GET_CODE (insn) != NOTE)
1237 if (++insn_count > max_uid)
1239 if (insn == basic_block_head[b])
1241 insn = PREV_INSN (insn);
1244 /* +2 to leave room for a post_mark_life at the last insn and for
1245 the birth of a CLOBBER in the first insn. */
1246 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1247 * sizeof (HARD_REG_SET));
1248 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1250 /* Initialize table of hardware registers currently live. */
1252 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1254 /* This loop scans the instructions of the basic block
1255 and assigns quantities to registers.
1256 It computes which registers to tie. */
1258 insn = basic_block_head[b];
1261 register rtx body = PATTERN (insn);
1263 if (GET_CODE (insn) != NOTE)
1266 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1268 register rtx link, set;
1269 register int win = 0;
1270 register rtx r0, r1;
1271 int combined_regno = -1;
1273 int insn_code_number = recog_memoized (insn);
1275 this_insn_number = insn_number;
1278 if (insn_code_number >= 0)
1279 insn_extract (insn);
1280 which_alternative = -1;
1282 /* Is this insn suitable for tying two registers?
1283 If so, try doing that.
1284 Suitable insns are those with at least two operands and where
1285 operand 0 is an output that is a register that is not
1288 We can tie operand 0 with some operand that dies in this insn.
1289 First look for operands that are required to be in the same
1290 register as operand 0. If we find such, only try tying that
1291 operand or one that can be put into that operand if the
1292 operation is commutative. If we don't find an operand
1293 that is required to be in the same register as operand 0,
1294 we can tie with any operand.
1296 Subregs in place of regs are also ok.
1298 If tying is done, WIN is set nonzero. */
1300 if (insn_code_number >= 0
1301 #ifdef REGISTER_CONSTRAINTS
1302 && insn_n_operands[insn_code_number] > 1
1303 && insn_operand_constraint[insn_code_number][0][0] == '='
1304 && insn_operand_constraint[insn_code_number][0][1] != '&'
1306 && GET_CODE (PATTERN (insn)) == SET
1307 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1311 #ifdef REGISTER_CONSTRAINTS
1312 /* If non-negative, is an operand that must match operand 0. */
1313 int must_match_0 = -1;
1314 /* Counts number of alternatives that require a match with
1316 int n_matching_alts = 0;
1318 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1320 char *p = insn_operand_constraint[insn_code_number][i];
1321 int this_match = (requires_inout (p));
1323 n_matching_alts += this_match;
1324 if (this_match == insn_n_alternatives[insn_code_number])
1329 r0 = recog_operand[0];
1330 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1332 #ifdef REGISTER_CONSTRAINTS
1333 /* Skip this operand if we found an operand that
1334 must match operand 0 and this operand isn't it
1335 and can't be made to be it by commutativity. */
1337 if (must_match_0 >= 0 && i != must_match_0
1338 && ! (i == must_match_0 + 1
1339 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1340 && ! (i == must_match_0 - 1
1341 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1344 /* Likewise if each alternative has some operand that
1345 must match operand zero. In that case, skip any
1346 operand that doesn't list operand 0 since we know that
1347 the operand always conflicts with operand 0. We
1348 ignore commutatity in this case to keep things simple. */
1349 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1350 && (0 == requires_inout
1351 (insn_operand_constraint[insn_code_number][i])))
1355 r1 = recog_operand[i];
1357 /* If the operand is an address, find a register in it.
1358 There may be more than one register, but we only try one
1361 #ifdef REGISTER_CONSTRAINTS
1362 insn_operand_constraint[insn_code_number][i][0] == 'p'
1364 insn_operand_address_p[insn_code_number][i]
1367 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1370 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1372 /* We have two priorities for hard register preferences.
1373 If we have a move insn or an insn whose first input
1374 can only be in the same register as the output, give
1375 priority to an equivalence found from that insn. */
1377 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1378 #ifdef REGISTER_CONSTRAINTS
1379 || (r1 == recog_operand[i] && must_match_0 >= 0)
1383 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1384 win = combine_regs (r1, r0, may_save_copy,
1385 insn_number, insn, 0);
1392 /* Recognize an insn sequence with an ultimate result
1393 which can safely overlap one of the inputs.
1394 The sequence begins with a CLOBBER of its result,
1395 and ends with an insn that copies the result to itself
1396 and has a REG_EQUAL note for an equivalent formula.
1397 That note indicates what the inputs are.
1398 The result and the input can overlap if each insn in
1399 the sequence either doesn't mention the input
1400 or has a REG_NO_CONFLICT note to inhibit the conflict.
1402 We do the combining test at the CLOBBER so that the
1403 destination register won't have had a quantity number
1404 assigned, since that would prevent combining. */
1406 if (GET_CODE (PATTERN (insn)) == CLOBBER
1407 && (r0 = XEXP (PATTERN (insn), 0),
1408 GET_CODE (r0) == REG)
1409 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1410 && XEXP (link, 0) != 0
1411 && GET_CODE (XEXP (link, 0)) == INSN
1412 && (set = single_set (XEXP (link, 0))) != 0
1413 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1414 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1417 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1418 /* Check that we have such a sequence. */
1419 && no_conflict_p (insn, r0, r1))
1420 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1421 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1422 && (r1 = XEXP (XEXP (note, 0), 0),
1423 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1424 && no_conflict_p (insn, r0, r1))
1425 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1427 /* Here we care if the operation to be computed is
1429 else if ((GET_CODE (XEXP (note, 0)) == EQ
1430 || GET_CODE (XEXP (note, 0)) == NE
1431 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1432 && (r1 = XEXP (XEXP (note, 0), 1),
1433 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1434 && no_conflict_p (insn, r0, r1))
1435 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1437 /* If we did combine something, show the register number
1438 in question so that we know to ignore its death. */
1440 no_conflict_combined_regno = REGNO (r1);
1443 /* If registers were just tied, set COMBINED_REGNO
1444 to the number of the register used in this insn
1445 that was tied to the register set in this insn.
1446 This register's qty should not be "killed". */
1450 while (GET_CODE (r1) == SUBREG)
1451 r1 = SUBREG_REG (r1);
1452 combined_regno = REGNO (r1);
1455 /* Mark the death of everything that dies in this instruction,
1456 except for anything that was just combined. */
1458 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1459 if (REG_NOTE_KIND (link) == REG_DEAD
1460 && GET_CODE (XEXP (link, 0)) == REG
1461 && combined_regno != REGNO (XEXP (link, 0))
1462 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1463 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1464 wipe_dead_reg (XEXP (link, 0), 0);
1466 /* Allocate qty numbers for all registers local to this block
1467 that are born (set) in this instruction.
1468 A pseudo that already has a qty is not changed. */
1470 note_stores (PATTERN (insn), reg_is_set);
1472 /* If anything is set in this insn and then unused, mark it as dying
1473 after this insn, so it will conflict with our outputs. This
1474 can't match with something that combined, and it doesn't matter
1475 if it did. Do this after the calls to reg_is_set since these
1476 die after, not during, the current insn. */
1478 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1479 if (REG_NOTE_KIND (link) == REG_UNUSED
1480 && GET_CODE (XEXP (link, 0)) == REG)
1481 wipe_dead_reg (XEXP (link, 0), 1);
1483 /* Allocate quantities for any SCRATCH operands of this insn. */
1485 if (insn_code_number >= 0)
1486 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1487 if (GET_CODE (recog_operand[i]) == SCRATCH
1488 && scratches_allocated++ < scratch_list_length)
1489 alloc_qty_for_scratch (recog_operand[i], i, insn,
1490 insn_code_number, insn_number);
1492 /* If this is an insn that has a REG_RETVAL note pointing at a
1493 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1494 block, so clear any register number that combined within it. */
1495 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1496 && GET_CODE (XEXP (note, 0)) == INSN
1497 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1498 no_conflict_combined_regno = -1;
1501 /* Set the registers live after INSN_NUMBER. Note that we never
1502 record the registers live before the block's first insn, since no
1503 pseudos we care about are live before that insn. */
1505 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1506 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1508 if (insn == basic_block_end[b])
1511 insn = NEXT_INSN (insn);
1514 /* Now every register that is local to this basic block
1515 should have been given a quantity, or else -1 meaning ignore it.
1516 Every quantity should have a known birth and death.
1518 Order the qtys so we assign them registers in order of the
1519 number of suggested registers they need so we allocate those with
1520 the most restrictive needs first. */
1522 qty_order = (int *) alloca (next_qty * sizeof (int));
1523 for (i = 0; i < next_qty; i++)
1526 #define EXCHANGE(I1, I2) \
1527 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1532 /* Make qty_order[2] be the one to allocate last. */
1533 if (qty_sugg_compare (0, 1) > 0)
1535 if (qty_sugg_compare (1, 2) > 0)
1538 /* ... Fall through ... */
1540 /* Put the best one to allocate in qty_order[0]. */
1541 if (qty_sugg_compare (0, 1) > 0)
1544 /* ... Fall through ... */
1548 /* Nothing to do here. */
1552 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1555 /* Try to put each quantity in a suggested physical register, if it has one.
1556 This may cause registers to be allocated that otherwise wouldn't be, but
1557 this seems acceptable in local allocation (unlike global allocation). */
1558 for (i = 0; i < next_qty; i++)
1561 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1562 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1563 0, 1, qty_birth[q], qty_death[q]);
1565 qty_phys_reg[q] = -1;
1568 /* Order the qtys so we assign them registers in order of
1569 decreasing length of life. Normally call qsort, but if we
1570 have only a very small number of quantities, sort them ourselves. */
1572 for (i = 0; i < next_qty; i++)
1575 #define EXCHANGE(I1, I2) \
1576 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1581 /* Make qty_order[2] be the one to allocate last. */
1582 if (qty_compare (0, 1) > 0)
1584 if (qty_compare (1, 2) > 0)
1587 /* ... Fall through ... */
1589 /* Put the best one to allocate in qty_order[0]. */
1590 if (qty_compare (0, 1) > 0)
1593 /* ... Fall through ... */
1597 /* Nothing to do here. */
1601 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1604 /* Now for each qty that is not a hardware register,
1605 look for a hardware register to put it in.
1606 First try the register class that is cheapest for this qty,
1607 if there is more than one class. */
1609 for (i = 0; i < next_qty; i++)
1612 if (qty_phys_reg[q] < 0)
1614 if (N_REG_CLASSES > 1)
1616 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1617 qty_mode[q], q, 0, 0,
1618 qty_birth[q], qty_death[q]);
1619 if (qty_phys_reg[q] >= 0)
1623 if (qty_alternate_class[q] != NO_REGS)
1624 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1625 qty_mode[q], q, 0, 0,
1626 qty_birth[q], qty_death[q]);
1630 /* Now propagate the register assignments
1631 to the pseudo regs belonging to the qtys. */
1633 for (q = 0; q < next_qty; q++)
1634 if (qty_phys_reg[q] >= 0)
1636 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1637 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1638 if (qty_scratch_rtx[q])
1640 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1642 PUT_CODE (qty_scratch_rtx[q], REG);
1643 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1645 scratch_block[scratch_index] = b;
1646 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1648 /* Must clear the USED field, because it will have been set by
1649 copy_rtx_if_shared, but the leaf_register code expects that
1650 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1651 used bit for REGs, but does for SCRATCHes. */
1652 qty_scratch_rtx[q]->used = 0;
1657 /* Compare two quantities' priority for getting real registers.
1658 We give shorter-lived quantities higher priority.
1659 Quantities with more references are also preferred, as are quantities that
1660 require multiple registers. This is the identical prioritization as
1661 done by global-alloc.
1663 We used to give preference to registers with *longer* lives, but using
1664 the same algorithm in both local- and global-alloc can speed up execution
1665 of some programs by as much as a factor of three! */
1667 /* Note that the quotient will never be bigger than
1668 the value of floor_log2 times the maximum number of
1669 times a register can occur in one insn (surely less than 100).
1670 Multiplying this by 10000 can't overflow.
1671 QTY_CMP_PRI is also used by qty_sugg_compare. */
1673 #define QTY_CMP_PRI(q) \
1674 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1675 / (qty_death[q] - qty_birth[q])) * 10000))
1678 qty_compare (q1, q2)
1681 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1685 qty_compare_1 (q1p, q2p)
1686 const GENERIC_PTR q1p;
1687 const GENERIC_PTR q2p;
1689 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1690 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1695 /* If qtys are equally good, sort by qty number,
1696 so that the results of qsort leave nothing to chance. */
1700 /* Compare two quantities' priority for getting real registers. This version
1701 is called for quantities that have suggested hard registers. First priority
1702 goes to quantities that have copy preferences, then to those that have
1703 normal preferences. Within those groups, quantities with the lower
1704 number of preferences have the highest priority. Of those, we use the same
1705 algorithm as above. */
1707 #define QTY_CMP_SUGG(q) \
1708 (qty_phys_num_copy_sugg[q] \
1709 ? qty_phys_num_copy_sugg[q] \
1710 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1713 qty_sugg_compare (q1, q2)
1716 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1721 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1725 qty_sugg_compare_1 (q1p, q2p)
1726 const GENERIC_PTR q1p;
1727 const GENERIC_PTR q2p;
1729 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1730 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1735 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1739 /* If qtys are equally good, sort by qty number,
1740 so that the results of qsort leave nothing to chance. */
1747 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1748 Returns 1 if have done so, or 0 if cannot.
1750 Combining registers means marking them as having the same quantity
1751 and adjusting the offsets within the quantity if either of
1754 We don't actually combine a hard reg with a pseudo; instead
1755 we just record the hard reg as the suggestion for the pseudo's quantity.
1756 If we really combined them, we could lose if the pseudo lives
1757 across an insn that clobbers the hard reg (eg, movstr).
1759 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1760 there is no REG_DEAD note on INSN. This occurs during the processing
1761 of REG_NO_CONFLICT blocks.
1763 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1764 SETREG or if the input and output must share a register.
1765 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1767 There are elaborate checks for the validity of combining. */
1771 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1772 rtx usedreg, setreg;
1778 register int ureg, sreg;
1779 register int offset = 0;
1783 /* Determine the numbers and sizes of registers being used. If a subreg
1784 is present that does not change the entire register, don't consider
1785 this a copy insn. */
1787 while (GET_CODE (usedreg) == SUBREG)
1789 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1791 offset += SUBREG_WORD (usedreg);
1792 usedreg = SUBREG_REG (usedreg);
1794 if (GET_CODE (usedreg) != REG)
1796 ureg = REGNO (usedreg);
1797 usize = REG_SIZE (usedreg);
1799 while (GET_CODE (setreg) == SUBREG)
1801 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1803 offset -= SUBREG_WORD (setreg);
1804 setreg = SUBREG_REG (setreg);
1806 if (GET_CODE (setreg) != REG)
1808 sreg = REGNO (setreg);
1809 ssize = REG_SIZE (setreg);
1811 /* If UREG is a pseudo-register that hasn't already been assigned a
1812 quantity number, it means that it is not local to this block or dies
1813 more than once. In either event, we can't do anything with it. */
1814 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1815 /* Do not combine registers unless one fits within the other. */
1816 || (offset > 0 && usize + offset > ssize)
1817 || (offset < 0 && usize + offset < ssize)
1818 /* Do not combine with a smaller already-assigned object
1819 if that smaller object is already combined with something bigger. */
1820 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1821 && usize < qty_size[reg_qty[ureg]])
1822 /* Can't combine if SREG is not a register we can allocate. */
1823 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1824 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1825 These have already been taken care of. This probably wouldn't
1826 combine anyway, but don't take any chances. */
1827 || (ureg >= FIRST_PSEUDO_REGISTER
1828 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1829 /* Don't tie something to itself. In most cases it would make no
1830 difference, but it would screw up if the reg being tied to itself
1831 also dies in this insn. */
1833 /* Don't try to connect two different hardware registers. */
1834 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1835 /* Don't connect two different machine modes if they have different
1836 implications as to which registers may be used. */
1837 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1840 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1841 qty_phys_sugg for the pseudo instead of tying them.
1843 Return "failure" so that the lifespan of UREG is terminated here;
1844 that way the two lifespans will be disjoint and nothing will prevent
1845 the pseudo reg from being given this hard reg. */
1847 if (ureg < FIRST_PSEUDO_REGISTER)
1849 /* Allocate a quantity number so we have a place to put our
1851 if (reg_qty[sreg] == -2)
1852 reg_is_born (setreg, 2 * insn_number);
1854 if (reg_qty[sreg] >= 0)
1857 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1859 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1860 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1862 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1864 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1865 qty_phys_num_sugg[reg_qty[sreg]]++;
1871 /* Similarly for SREG a hard register and UREG a pseudo register. */
1873 if (sreg < FIRST_PSEUDO_REGISTER)
1876 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1878 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1879 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1881 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1883 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1884 qty_phys_num_sugg[reg_qty[ureg]]++;
1889 /* At this point we know that SREG and UREG are both pseudos.
1890 Do nothing if SREG already has a quantity or is a register that we
1892 if (reg_qty[sreg] >= -1
1893 /* If we are not going to let any regs live across calls,
1894 don't tie a call-crossing reg to a non-call-crossing reg. */
1895 || (current_function_has_nonlocal_label
1896 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1897 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1900 /* We don't already know about SREG, so tie it to UREG
1901 if this is the last use of UREG, provided the classes they want
1904 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1905 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1907 /* Add SREG to UREG's quantity. */
1908 sqty = reg_qty[ureg];
1909 reg_qty[sreg] = sqty;
1910 reg_offset[sreg] = reg_offset[ureg] + offset;
1911 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1912 qty_first_reg[sqty] = sreg;
1914 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1915 update_qty_class (sqty, sreg);
1917 /* Update info about quantity SQTY. */
1918 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1919 qty_n_refs[sqty] += REG_N_REFS (sreg);
1924 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1925 reg_offset[i] -= offset;
1927 qty_size[sqty] = ssize;
1928 qty_mode[sqty] = GET_MODE (setreg);
1937 /* Return 1 if the preferred class of REG allows it to be tied
1938 to a quantity or register whose class is CLASS.
1939 True if REG's reg class either contains or is contained in CLASS. */
1942 reg_meets_class_p (reg, class)
1944 enum reg_class class;
1946 register enum reg_class rclass = reg_preferred_class (reg);
1947 return (reg_class_subset_p (rclass, class)
1948 || reg_class_subset_p (class, rclass));
1951 /* Return 1 if the two specified classes have registers in common.
1952 If CALL_SAVED, then consider only call-saved registers. */
1955 reg_classes_overlap_p (c1, c2, call_saved)
1956 register enum reg_class c1;
1957 register enum reg_class c2;
1963 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1964 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1966 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1967 if (TEST_HARD_REG_BIT (c, i)
1968 && (! call_saved || ! call_used_regs[i]))
1974 /* Update the class of QTY assuming that REG is being tied to it. */
1977 update_qty_class (qty, reg)
1981 enum reg_class rclass = reg_preferred_class (reg);
1982 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1983 qty_min_class[qty] = rclass;
1985 rclass = reg_alternate_class (reg);
1986 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1987 qty_alternate_class[qty] = rclass;
1989 if (REG_CHANGES_SIZE (reg))
1990 qty_changes_size[qty] = 1;
1993 /* Handle something which alters the value of an rtx REG.
1995 REG is whatever is set or clobbered. SETTER is the rtx that
1996 is modifying the register.
1998 If it is not really a register, we do nothing.
1999 The file-global variables `this_insn' and `this_insn_number'
2000 carry info from `block_alloc'. */
2003 reg_is_set (reg, setter)
2007 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2008 a hard register. These may actually not exist any more. */
2010 if (GET_CODE (reg) != SUBREG
2011 && GET_CODE (reg) != REG)
2014 /* Mark this register as being born. If it is used in a CLOBBER, mark
2015 it as being born halfway between the previous insn and this insn so that
2016 it conflicts with our inputs but not the outputs of the previous insn. */
2018 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2021 /* Handle beginning of the life of register REG.
2022 BIRTH is the index at which this is happening. */
2025 reg_is_born (reg, birth)
2031 if (GET_CODE (reg) == SUBREG)
2032 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
2034 regno = REGNO (reg);
2036 if (regno < FIRST_PSEUDO_REGISTER)
2038 mark_life (regno, GET_MODE (reg), 1);
2040 /* If the register was to have been born earlier that the present
2041 insn, mark it as live where it is actually born. */
2042 if (birth < 2 * this_insn_number)
2043 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2047 if (reg_qty[regno] == -2)
2048 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2050 /* If this register has a quantity number, show that it isn't dead. */
2051 if (reg_qty[regno] >= 0)
2052 qty_death[reg_qty[regno]] = -1;
2056 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2057 REG is an output that is dying (i.e., it is never used), otherwise it
2058 is an input (the normal case).
2059 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2062 wipe_dead_reg (reg, output_p)
2066 register int regno = REGNO (reg);
2068 /* If this insn has multiple results,
2069 and the dead reg is used in one of the results,
2070 extend its life to after this insn,
2071 so it won't get allocated together with any other result of this insn. */
2072 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2073 && !single_set (this_insn))
2076 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2078 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2079 if (GET_CODE (set) == SET
2080 && GET_CODE (SET_DEST (set)) != REG
2081 && !rtx_equal_p (reg, SET_DEST (set))
2082 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2087 /* If this register is used in an auto-increment address, then extend its
2088 life to after this insn, so that it won't get allocated together with
2089 the result of this insn. */
2090 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2093 if (regno < FIRST_PSEUDO_REGISTER)
2095 mark_life (regno, GET_MODE (reg), 0);
2097 /* If a hard register is dying as an output, mark it as in use at
2098 the beginning of this insn (the above statement would cause this
2101 post_mark_life (regno, GET_MODE (reg), 1,
2102 2 * this_insn_number, 2 * this_insn_number+ 1);
2105 else if (reg_qty[regno] >= 0)
2106 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2109 /* Find a block of SIZE words of hard regs in reg_class CLASS
2110 that can hold something of machine-mode MODE
2111 (but actually we test only the first of the block for holding MODE)
2112 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2113 and return the number of the first of them.
2114 Return -1 if such a block cannot be found.
2115 If QTY crosses calls, insist on a register preserved by calls,
2116 unless ACCEPT_CALL_CLOBBERED is nonzero.
2118 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2119 register is available. If not, return -1. */
2122 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2123 born_index, dead_index)
2124 enum reg_class class;
2125 enum machine_mode mode;
2127 int accept_call_clobbered;
2128 int just_try_suggested;
2129 int born_index, dead_index;
2131 register int i, ins;
2133 register /* Declare it register if it's a scalar. */
2135 HARD_REG_SET used, first_used;
2136 #ifdef ELIMINABLE_REGS
2137 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2140 /* Validate our parameters. */
2141 if (born_index < 0 || born_index > dead_index)
2144 /* Don't let a pseudo live in a reg across a function call
2145 if we might get a nonlocal goto. */
2146 if (current_function_has_nonlocal_label
2147 && qty_n_calls_crossed[qty] > 0)
2150 if (accept_call_clobbered)
2151 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2152 else if (qty_n_calls_crossed[qty] == 0)
2153 COPY_HARD_REG_SET (used, fixed_reg_set);
2155 COPY_HARD_REG_SET (used, call_used_reg_set);
2157 if (accept_call_clobbered)
2158 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2160 for (ins = born_index; ins < dead_index; ins++)
2161 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2163 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2165 /* Don't use the frame pointer reg in local-alloc even if
2166 we may omit the frame pointer, because if we do that and then we
2167 need a frame pointer, reload won't know how to move the pseudo
2168 to another hard reg. It can move only regs made by global-alloc.
2170 This is true of any register that can be eliminated. */
2171 #ifdef ELIMINABLE_REGS
2172 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2173 SET_HARD_REG_BIT (used, eliminables[i].from);
2174 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2175 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2176 that it might be eliminated into. */
2177 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2180 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2183 #ifdef CLASS_CANNOT_CHANGE_SIZE
2184 if (qty_changes_size[qty])
2185 IOR_HARD_REG_SET (used,
2186 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2189 /* Normally, the registers that can be used for the first register in
2190 a multi-register quantity are the same as those that can be used for
2191 subsequent registers. However, if just trying suggested registers,
2192 restrict our consideration to them. If there are copy-suggested
2193 register, try them. Otherwise, try the arithmetic-suggested
2195 COPY_HARD_REG_SET (first_used, used);
2197 if (just_try_suggested)
2199 if (qty_phys_num_copy_sugg[qty] != 0)
2200 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2202 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2205 /* If all registers are excluded, we can't do anything. */
2206 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2208 /* If at least one would be suitable, test each hard reg. */
2210 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2212 #ifdef REG_ALLOC_ORDER
2213 int regno = reg_alloc_order[i];
2217 if (! TEST_HARD_REG_BIT (first_used, regno)
2218 && HARD_REGNO_MODE_OK (regno, mode))
2221 register int size1 = HARD_REGNO_NREGS (regno, mode);
2222 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2225 /* Mark that this register is in use between its birth and death
2227 post_mark_life (regno, mode, 1, born_index, dead_index);
2230 #ifndef REG_ALLOC_ORDER
2231 i += j; /* Skip starting points we know will lose */
2238 /* If we are just trying suggested register, we have just tried copy-
2239 suggested registers, and there are arithmetic-suggested registers,
2242 /* If it would be profitable to allocate a call-clobbered register
2243 and save and restore it around calls, do that. */
2244 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2245 && qty_phys_num_sugg[qty] != 0)
2247 /* Don't try the copy-suggested regs again. */
2248 qty_phys_num_copy_sugg[qty] = 0;
2249 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2250 born_index, dead_index);
2253 /* We need not check to see if the current function has nonlocal
2254 labels because we don't put any pseudos that are live over calls in
2255 registers in that case. */
2257 if (! accept_call_clobbered
2258 && flag_caller_saves
2259 && ! just_try_suggested
2260 && qty_n_calls_crossed[qty] != 0
2261 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2263 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2265 caller_save_needed = 1;
2271 /* Mark that REGNO with machine-mode MODE is live starting from the current
2272 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2276 mark_life (regno, mode, life)
2278 enum machine_mode mode;
2281 register int j = HARD_REGNO_NREGS (regno, mode);
2284 SET_HARD_REG_BIT (regs_live, regno + j);
2287 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2290 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2291 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2292 to insn number DEATH (exclusive). */
2295 post_mark_life (regno, mode, life, birth, death)
2297 enum machine_mode mode;
2298 int life, birth, death;
2300 register int j = HARD_REGNO_NREGS (regno, mode);
2302 register /* Declare it register if it's a scalar. */
2304 HARD_REG_SET this_reg;
2306 CLEAR_HARD_REG_SET (this_reg);
2308 SET_HARD_REG_BIT (this_reg, regno + j);
2311 while (birth < death)
2313 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2317 while (birth < death)
2319 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2324 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2325 is the register being clobbered, and R1 is a register being used in
2326 the equivalent expression.
2328 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2329 in which it is used, return 1.
2331 Otherwise, return 0. */
2334 no_conflict_p (insn, r0, r1)
2338 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2341 /* If R1 is a hard register, return 0 since we handle this case
2342 when we scan the insns that actually use it. */
2345 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2346 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2347 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2350 last = XEXP (note, 0);
2352 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2353 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2355 if (find_reg_note (p, REG_DEAD, r1))
2358 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2359 some earlier optimization pass has inserted instructions into
2360 the sequence, and it is not safe to perform this optimization.
2361 Note that emit_no_conflict_block always ensures that this is
2362 true when these sequences are created. */
2363 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2370 #ifdef REGISTER_CONSTRAINTS
2372 /* Return the number of alternatives for which the constraint string P
2373 indicates that the operand must be equal to operand 0 and that no register
2382 int reg_allowed = 0;
2383 int num_matching_alts = 0;
2388 case '=': case '+': case '?':
2389 case '#': case '&': case '!':
2391 case '1': case '2': case '3': case '4':
2392 case 'm': case '<': case '>': case 'V': case 'o':
2393 case 'E': case 'F': case 'G': case 'H':
2394 case 's': case 'i': case 'n':
2395 case 'I': case 'J': case 'K': case 'L':
2396 case 'M': case 'N': case 'O': case 'P':
2397 #ifdef EXTRA_CONSTRAINT
2398 case 'Q': case 'R': case 'S': case 'T': case 'U':
2401 /* These don't say anything we care about. */
2405 if (found_zero && ! reg_allowed)
2406 num_matching_alts++;
2408 found_zero = reg_allowed = 0;
2422 if (found_zero && ! reg_allowed)
2423 num_matching_alts++;
2425 return num_matching_alts;
2427 #endif /* REGISTER_CONSTRAINTS */
2430 dump_local_alloc (file)
2434 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2435 if (reg_renumber[i] != -1)
2436 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
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